1 /** 2 * \file 3 * 4 * \brief Component description for SPI 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_SPI_COMPONENT_H_ 32 #define _SAME70_SPI_COMPONENT_H_ 33 #define _SAME70_SPI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Serial Peripheral Interface 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR SPI */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define SPI_6088 /**< (SPI) Module ID */ 46 #define REV_SPI ZF /**< (SPI) Module revision */ 47 48 /* -------- SPI_CR : (SPI Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t SPIEN:1; /**< bit: 0 SPI Enable */ 54 uint32_t SPIDIS:1; /**< bit: 1 SPI Disable */ 55 uint32_t :5; /**< bit: 2..6 Reserved */ 56 uint32_t SWRST:1; /**< bit: 7 SPI Software Reset */ 57 uint32_t :4; /**< bit: 8..11 Reserved */ 58 uint32_t REQCLR:1; /**< bit: 12 Request to Clear the Comparison Trigger */ 59 uint32_t :3; /**< bit: 13..15 Reserved */ 60 uint32_t TXFCLR:1; /**< bit: 16 Transmit FIFO Clear */ 61 uint32_t RXFCLR:1; /**< bit: 17 Receive FIFO Clear */ 62 uint32_t :6; /**< bit: 18..23 Reserved */ 63 uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */ 64 uint32_t :5; /**< bit: 25..29 Reserved */ 65 uint32_t FIFOEN:1; /**< bit: 30 FIFO Enable */ 66 uint32_t FIFODIS:1; /**< bit: 31 FIFO Disable */ 67 } bit; /**< Structure used for bit access */ 68 uint32_t reg; /**< Type used for register access */ 69 } SPI_CR_Type; 70 #endif 71 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #define SPI_CR_OFFSET (0x00) /**< (SPI_CR) Control Register Offset */ 74 75 #define SPI_CR_SPIEN_Pos 0 /**< (SPI_CR) SPI Enable Position */ 76 #define SPI_CR_SPIEN_Msk (_U_(0x1) << SPI_CR_SPIEN_Pos) /**< (SPI_CR) SPI Enable Mask */ 77 #define SPI_CR_SPIEN SPI_CR_SPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SPIEN_Msk instead */ 78 #define SPI_CR_SPIDIS_Pos 1 /**< (SPI_CR) SPI Disable Position */ 79 #define SPI_CR_SPIDIS_Msk (_U_(0x1) << SPI_CR_SPIDIS_Pos) /**< (SPI_CR) SPI Disable Mask */ 80 #define SPI_CR_SPIDIS SPI_CR_SPIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SPIDIS_Msk instead */ 81 #define SPI_CR_SWRST_Pos 7 /**< (SPI_CR) SPI Software Reset Position */ 82 #define SPI_CR_SWRST_Msk (_U_(0x1) << SPI_CR_SWRST_Pos) /**< (SPI_CR) SPI Software Reset Mask */ 83 #define SPI_CR_SWRST SPI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SWRST_Msk instead */ 84 #define SPI_CR_REQCLR_Pos 12 /**< (SPI_CR) Request to Clear the Comparison Trigger Position */ 85 #define SPI_CR_REQCLR_Msk (_U_(0x1) << SPI_CR_REQCLR_Pos) /**< (SPI_CR) Request to Clear the Comparison Trigger Mask */ 86 #define SPI_CR_REQCLR SPI_CR_REQCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_REQCLR_Msk instead */ 87 #define SPI_CR_TXFCLR_Pos 16 /**< (SPI_CR) Transmit FIFO Clear Position */ 88 #define SPI_CR_TXFCLR_Msk (_U_(0x1) << SPI_CR_TXFCLR_Pos) /**< (SPI_CR) Transmit FIFO Clear Mask */ 89 #define SPI_CR_TXFCLR SPI_CR_TXFCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_TXFCLR_Msk instead */ 90 #define SPI_CR_RXFCLR_Pos 17 /**< (SPI_CR) Receive FIFO Clear Position */ 91 #define SPI_CR_RXFCLR_Msk (_U_(0x1) << SPI_CR_RXFCLR_Pos) /**< (SPI_CR) Receive FIFO Clear Mask */ 92 #define SPI_CR_RXFCLR SPI_CR_RXFCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_RXFCLR_Msk instead */ 93 #define SPI_CR_LASTXFER_Pos 24 /**< (SPI_CR) Last Transfer Position */ 94 #define SPI_CR_LASTXFER_Msk (_U_(0x1) << SPI_CR_LASTXFER_Pos) /**< (SPI_CR) Last Transfer Mask */ 95 #define SPI_CR_LASTXFER SPI_CR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_LASTXFER_Msk instead */ 96 #define SPI_CR_FIFOEN_Pos 30 /**< (SPI_CR) FIFO Enable Position */ 97 #define SPI_CR_FIFOEN_Msk (_U_(0x1) << SPI_CR_FIFOEN_Pos) /**< (SPI_CR) FIFO Enable Mask */ 98 #define SPI_CR_FIFOEN SPI_CR_FIFOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_FIFOEN_Msk instead */ 99 #define SPI_CR_FIFODIS_Pos 31 /**< (SPI_CR) FIFO Disable Position */ 100 #define SPI_CR_FIFODIS_Msk (_U_(0x1) << SPI_CR_FIFODIS_Pos) /**< (SPI_CR) FIFO Disable Mask */ 101 #define SPI_CR_FIFODIS SPI_CR_FIFODIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_FIFODIS_Msk instead */ 102 #define SPI_CR_MASK _U_(0xC1031083) /**< \deprecated (SPI_CR) Register MASK (Use SPI_CR_Msk instead) */ 103 #define SPI_CR_Msk _U_(0xC1031083) /**< (SPI_CR) Register Mask */ 104 105 106 /* -------- SPI_MR : (SPI Offset: 0x04) (R/W 32) Mode Register -------- */ 107 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 108 #if COMPONENT_TYPEDEF_STYLE == 'N' 109 typedef union { 110 struct { 111 uint32_t MSTR:1; /**< bit: 0 Master/Slave Mode */ 112 uint32_t PS:1; /**< bit: 1 Peripheral Select */ 113 uint32_t PCSDEC:1; /**< bit: 2 Chip Select Decode */ 114 uint32_t :1; /**< bit: 3 Reserved */ 115 uint32_t MODFDIS:1; /**< bit: 4 Mode Fault Detection */ 116 uint32_t WDRBT:1; /**< bit: 5 Wait Data Read Before Transfer */ 117 uint32_t :1; /**< bit: 6 Reserved */ 118 uint32_t LLB:1; /**< bit: 7 Local Loopback Enable */ 119 uint32_t :8; /**< bit: 8..15 Reserved */ 120 uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */ 121 uint32_t :4; /**< bit: 20..23 Reserved */ 122 uint32_t DLYBCS:8; /**< bit: 24..31 Delay Between Chip Selects */ 123 } bit; /**< Structure used for bit access */ 124 uint32_t reg; /**< Type used for register access */ 125 } SPI_MR_Type; 126 #endif 127 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 128 129 #define SPI_MR_OFFSET (0x04) /**< (SPI_MR) Mode Register Offset */ 130 131 #define SPI_MR_MSTR_Pos 0 /**< (SPI_MR) Master/Slave Mode Position */ 132 #define SPI_MR_MSTR_Msk (_U_(0x1) << SPI_MR_MSTR_Pos) /**< (SPI_MR) Master/Slave Mode Mask */ 133 #define SPI_MR_MSTR SPI_MR_MSTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_MSTR_Msk instead */ 134 #define SPI_MR_PS_Pos 1 /**< (SPI_MR) Peripheral Select Position */ 135 #define SPI_MR_PS_Msk (_U_(0x1) << SPI_MR_PS_Pos) /**< (SPI_MR) Peripheral Select Mask */ 136 #define SPI_MR_PS SPI_MR_PS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_PS_Msk instead */ 137 #define SPI_MR_PCSDEC_Pos 2 /**< (SPI_MR) Chip Select Decode Position */ 138 #define SPI_MR_PCSDEC_Msk (_U_(0x1) << SPI_MR_PCSDEC_Pos) /**< (SPI_MR) Chip Select Decode Mask */ 139 #define SPI_MR_PCSDEC SPI_MR_PCSDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_PCSDEC_Msk instead */ 140 #define SPI_MR_MODFDIS_Pos 4 /**< (SPI_MR) Mode Fault Detection Position */ 141 #define SPI_MR_MODFDIS_Msk (_U_(0x1) << SPI_MR_MODFDIS_Pos) /**< (SPI_MR) Mode Fault Detection Mask */ 142 #define SPI_MR_MODFDIS SPI_MR_MODFDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_MODFDIS_Msk instead */ 143 #define SPI_MR_WDRBT_Pos 5 /**< (SPI_MR) Wait Data Read Before Transfer Position */ 144 #define SPI_MR_WDRBT_Msk (_U_(0x1) << SPI_MR_WDRBT_Pos) /**< (SPI_MR) Wait Data Read Before Transfer Mask */ 145 #define SPI_MR_WDRBT SPI_MR_WDRBT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_WDRBT_Msk instead */ 146 #define SPI_MR_LLB_Pos 7 /**< (SPI_MR) Local Loopback Enable Position */ 147 #define SPI_MR_LLB_Msk (_U_(0x1) << SPI_MR_LLB_Pos) /**< (SPI_MR) Local Loopback Enable Mask */ 148 #define SPI_MR_LLB SPI_MR_LLB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_LLB_Msk instead */ 149 #define SPI_MR_PCS_Pos 16 /**< (SPI_MR) Peripheral Chip Select Position */ 150 #define SPI_MR_PCS_Msk (_U_(0xF) << SPI_MR_PCS_Pos) /**< (SPI_MR) Peripheral Chip Select Mask */ 151 #define SPI_MR_PCS(value) (SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)) 152 #define SPI_MR_DLYBCS_Pos 24 /**< (SPI_MR) Delay Between Chip Selects Position */ 153 #define SPI_MR_DLYBCS_Msk (_U_(0xFF) << SPI_MR_DLYBCS_Pos) /**< (SPI_MR) Delay Between Chip Selects Mask */ 154 #define SPI_MR_DLYBCS(value) (SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)) 155 #define SPI_MR_MASK _U_(0xFF0F00B7) /**< \deprecated (SPI_MR) Register MASK (Use SPI_MR_Msk instead) */ 156 #define SPI_MR_Msk _U_(0xFF0F00B7) /**< (SPI_MR) Register Mask */ 157 158 159 /* -------- SPI_RDR : (SPI Offset: 0x08) (R/ 32) Receive Data Register -------- */ 160 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 161 #if COMPONENT_TYPEDEF_STYLE == 'N' 162 typedef union { 163 struct { 164 uint32_t RD:16; /**< bit: 0..15 Receive Data */ 165 uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */ 166 uint32_t :12; /**< bit: 20..31 Reserved */ 167 } bit; /**< Structure used for bit access */ 168 uint32_t reg; /**< Type used for register access */ 169 } SPI_RDR_Type; 170 #endif 171 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 172 173 #define SPI_RDR_OFFSET (0x08) /**< (SPI_RDR) Receive Data Register Offset */ 174 175 #define SPI_RDR_RD_Pos 0 /**< (SPI_RDR) Receive Data Position */ 176 #define SPI_RDR_RD_Msk (_U_(0xFFFF) << SPI_RDR_RD_Pos) /**< (SPI_RDR) Receive Data Mask */ 177 #define SPI_RDR_RD(value) (SPI_RDR_RD_Msk & ((value) << SPI_RDR_RD_Pos)) 178 #define SPI_RDR_PCS_Pos 16 /**< (SPI_RDR) Peripheral Chip Select Position */ 179 #define SPI_RDR_PCS_Msk (_U_(0xF) << SPI_RDR_PCS_Pos) /**< (SPI_RDR) Peripheral Chip Select Mask */ 180 #define SPI_RDR_PCS(value) (SPI_RDR_PCS_Msk & ((value) << SPI_RDR_PCS_Pos)) 181 #define SPI_RDR_MASK _U_(0xFFFFF) /**< \deprecated (SPI_RDR) Register MASK (Use SPI_RDR_Msk instead) */ 182 #define SPI_RDR_Msk _U_(0xFFFFF) /**< (SPI_RDR) Register Mask */ 183 184 185 /* -------- SPI_TDR : (SPI Offset: 0x0c) (/W 32) Transmit Data Register -------- */ 186 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 187 #if COMPONENT_TYPEDEF_STYLE == 'N' 188 typedef union { 189 struct { 190 uint32_t TD:16; /**< bit: 0..15 Transmit Data */ 191 uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */ 192 uint32_t :4; /**< bit: 20..23 Reserved */ 193 uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */ 194 uint32_t :7; /**< bit: 25..31 Reserved */ 195 } bit; /**< Structure used for bit access */ 196 uint32_t reg; /**< Type used for register access */ 197 } SPI_TDR_Type; 198 #endif 199 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 #define SPI_TDR_OFFSET (0x0C) /**< (SPI_TDR) Transmit Data Register Offset */ 202 203 #define SPI_TDR_TD_Pos 0 /**< (SPI_TDR) Transmit Data Position */ 204 #define SPI_TDR_TD_Msk (_U_(0xFFFF) << SPI_TDR_TD_Pos) /**< (SPI_TDR) Transmit Data Mask */ 205 #define SPI_TDR_TD(value) (SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)) 206 #define SPI_TDR_PCS_Pos 16 /**< (SPI_TDR) Peripheral Chip Select Position */ 207 #define SPI_TDR_PCS_Msk (_U_(0xF) << SPI_TDR_PCS_Pos) /**< (SPI_TDR) Peripheral Chip Select Mask */ 208 #define SPI_TDR_PCS(value) (SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)) 209 #define SPI_TDR_LASTXFER_Pos 24 /**< (SPI_TDR) Last Transfer Position */ 210 #define SPI_TDR_LASTXFER_Msk (_U_(0x1) << SPI_TDR_LASTXFER_Pos) /**< (SPI_TDR) Last Transfer Mask */ 211 #define SPI_TDR_LASTXFER SPI_TDR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_TDR_LASTXFER_Msk instead */ 212 #define SPI_TDR_MASK _U_(0x10FFFFF) /**< \deprecated (SPI_TDR) Register MASK (Use SPI_TDR_Msk instead) */ 213 #define SPI_TDR_Msk _U_(0x10FFFFF) /**< (SPI_TDR) Register Mask */ 214 215 216 /* -------- SPI_SR : (SPI Offset: 0x10) (R/ 32) Status Register -------- */ 217 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 218 #if COMPONENT_TYPEDEF_STYLE == 'N' 219 typedef union { 220 struct { 221 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full (cleared by reading SPI_RDR) */ 222 uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty (cleared by writing SPI_TDR) */ 223 uint32_t MODF:1; /**< bit: 2 Mode Fault Error (cleared on read) */ 224 uint32_t OVRES:1; /**< bit: 3 Overrun Error Status (cleared on read) */ 225 uint32_t :4; /**< bit: 4..7 Reserved */ 226 uint32_t NSSR:1; /**< bit: 8 NSS Rising (cleared on read) */ 227 uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty (cleared by writing SPI_TDR) */ 228 uint32_t UNDES:1; /**< bit: 10 Underrun Error Status (Slave mode only) (cleared on read) */ 229 uint32_t :5; /**< bit: 11..15 Reserved */ 230 uint32_t SPIENS:1; /**< bit: 16 SPI Enable Status */ 231 uint32_t :15; /**< bit: 17..31 Reserved */ 232 } bit; /**< Structure used for bit access */ 233 uint32_t reg; /**< Type used for register access */ 234 } SPI_SR_Type; 235 #endif 236 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 237 238 #define SPI_SR_OFFSET (0x10) /**< (SPI_SR) Status Register Offset */ 239 240 #define SPI_SR_RDRF_Pos 0 /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ 241 #define SPI_SR_RDRF_Msk (_U_(0x1) << SPI_SR_RDRF_Pos) /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ 242 #define SPI_SR_RDRF SPI_SR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_RDRF_Msk instead */ 243 #define SPI_SR_TDRE_Pos 1 /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ 244 #define SPI_SR_TDRE_Msk (_U_(0x1) << SPI_SR_TDRE_Pos) /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ 245 #define SPI_SR_TDRE SPI_SR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_TDRE_Msk instead */ 246 #define SPI_SR_MODF_Pos 2 /**< (SPI_SR) Mode Fault Error (cleared on read) Position */ 247 #define SPI_SR_MODF_Msk (_U_(0x1) << SPI_SR_MODF_Pos) /**< (SPI_SR) Mode Fault Error (cleared on read) Mask */ 248 #define SPI_SR_MODF SPI_SR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_MODF_Msk instead */ 249 #define SPI_SR_OVRES_Pos 3 /**< (SPI_SR) Overrun Error Status (cleared on read) Position */ 250 #define SPI_SR_OVRES_Msk (_U_(0x1) << SPI_SR_OVRES_Pos) /**< (SPI_SR) Overrun Error Status (cleared on read) Mask */ 251 #define SPI_SR_OVRES SPI_SR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_OVRES_Msk instead */ 252 #define SPI_SR_NSSR_Pos 8 /**< (SPI_SR) NSS Rising (cleared on read) Position */ 253 #define SPI_SR_NSSR_Msk (_U_(0x1) << SPI_SR_NSSR_Pos) /**< (SPI_SR) NSS Rising (cleared on read) Mask */ 254 #define SPI_SR_NSSR SPI_SR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_NSSR_Msk instead */ 255 #define SPI_SR_TXEMPTY_Pos 9 /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ 256 #define SPI_SR_TXEMPTY_Msk (_U_(0x1) << SPI_SR_TXEMPTY_Pos) /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ 257 #define SPI_SR_TXEMPTY SPI_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_TXEMPTY_Msk instead */ 258 #define SPI_SR_UNDES_Pos 10 /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Position */ 259 #define SPI_SR_UNDES_Msk (_U_(0x1) << SPI_SR_UNDES_Pos) /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Mask */ 260 #define SPI_SR_UNDES SPI_SR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_UNDES_Msk instead */ 261 #define SPI_SR_SPIENS_Pos 16 /**< (SPI_SR) SPI Enable Status Position */ 262 #define SPI_SR_SPIENS_Msk (_U_(0x1) << SPI_SR_SPIENS_Pos) /**< (SPI_SR) SPI Enable Status Mask */ 263 #define SPI_SR_SPIENS SPI_SR_SPIENS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_SPIENS_Msk instead */ 264 #define SPI_SR_MASK _U_(0x1070F) /**< \deprecated (SPI_SR) Register MASK (Use SPI_SR_Msk instead) */ 265 #define SPI_SR_Msk _U_(0x1070F) /**< (SPI_SR) Register Mask */ 266 267 268 /* -------- SPI_IER : (SPI Offset: 0x14) (/W 32) Interrupt Enable Register -------- */ 269 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 270 #if COMPONENT_TYPEDEF_STYLE == 'N' 271 typedef union { 272 struct { 273 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Enable */ 274 uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Enable */ 275 uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Enable */ 276 uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Enable */ 277 uint32_t :4; /**< bit: 4..7 Reserved */ 278 uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Enable */ 279 uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Enable */ 280 uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Enable */ 281 uint32_t :21; /**< bit: 11..31 Reserved */ 282 } bit; /**< Structure used for bit access */ 283 uint32_t reg; /**< Type used for register access */ 284 } SPI_IER_Type; 285 #endif 286 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 287 288 #define SPI_IER_OFFSET (0x14) /**< (SPI_IER) Interrupt Enable Register Offset */ 289 290 #define SPI_IER_RDRF_Pos 0 /**< (SPI_IER) Receive Data Register Full Interrupt Enable Position */ 291 #define SPI_IER_RDRF_Msk (_U_(0x1) << SPI_IER_RDRF_Pos) /**< (SPI_IER) Receive Data Register Full Interrupt Enable Mask */ 292 #define SPI_IER_RDRF SPI_IER_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_RDRF_Msk instead */ 293 #define SPI_IER_TDRE_Pos 1 /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Position */ 294 #define SPI_IER_TDRE_Msk (_U_(0x1) << SPI_IER_TDRE_Pos) /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Mask */ 295 #define SPI_IER_TDRE SPI_IER_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_TDRE_Msk instead */ 296 #define SPI_IER_MODF_Pos 2 /**< (SPI_IER) Mode Fault Error Interrupt Enable Position */ 297 #define SPI_IER_MODF_Msk (_U_(0x1) << SPI_IER_MODF_Pos) /**< (SPI_IER) Mode Fault Error Interrupt Enable Mask */ 298 #define SPI_IER_MODF SPI_IER_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_MODF_Msk instead */ 299 #define SPI_IER_OVRES_Pos 3 /**< (SPI_IER) Overrun Error Interrupt Enable Position */ 300 #define SPI_IER_OVRES_Msk (_U_(0x1) << SPI_IER_OVRES_Pos) /**< (SPI_IER) Overrun Error Interrupt Enable Mask */ 301 #define SPI_IER_OVRES SPI_IER_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_OVRES_Msk instead */ 302 #define SPI_IER_NSSR_Pos 8 /**< (SPI_IER) NSS Rising Interrupt Enable Position */ 303 #define SPI_IER_NSSR_Msk (_U_(0x1) << SPI_IER_NSSR_Pos) /**< (SPI_IER) NSS Rising Interrupt Enable Mask */ 304 #define SPI_IER_NSSR SPI_IER_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_NSSR_Msk instead */ 305 #define SPI_IER_TXEMPTY_Pos 9 /**< (SPI_IER) Transmission Registers Empty Enable Position */ 306 #define SPI_IER_TXEMPTY_Msk (_U_(0x1) << SPI_IER_TXEMPTY_Pos) /**< (SPI_IER) Transmission Registers Empty Enable Mask */ 307 #define SPI_IER_TXEMPTY SPI_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_TXEMPTY_Msk instead */ 308 #define SPI_IER_UNDES_Pos 10 /**< (SPI_IER) Underrun Error Interrupt Enable Position */ 309 #define SPI_IER_UNDES_Msk (_U_(0x1) << SPI_IER_UNDES_Pos) /**< (SPI_IER) Underrun Error Interrupt Enable Mask */ 310 #define SPI_IER_UNDES SPI_IER_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_UNDES_Msk instead */ 311 #define SPI_IER_MASK _U_(0x70F) /**< \deprecated (SPI_IER) Register MASK (Use SPI_IER_Msk instead) */ 312 #define SPI_IER_Msk _U_(0x70F) /**< (SPI_IER) Register Mask */ 313 314 315 /* -------- SPI_IDR : (SPI Offset: 0x18) (/W 32) Interrupt Disable Register -------- */ 316 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 317 #if COMPONENT_TYPEDEF_STYLE == 'N' 318 typedef union { 319 struct { 320 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Disable */ 321 uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Disable */ 322 uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Disable */ 323 uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Disable */ 324 uint32_t :4; /**< bit: 4..7 Reserved */ 325 uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Disable */ 326 uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Disable */ 327 uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Disable */ 328 uint32_t :21; /**< bit: 11..31 Reserved */ 329 } bit; /**< Structure used for bit access */ 330 uint32_t reg; /**< Type used for register access */ 331 } SPI_IDR_Type; 332 #endif 333 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 334 335 #define SPI_IDR_OFFSET (0x18) /**< (SPI_IDR) Interrupt Disable Register Offset */ 336 337 #define SPI_IDR_RDRF_Pos 0 /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Position */ 338 #define SPI_IDR_RDRF_Msk (_U_(0x1) << SPI_IDR_RDRF_Pos) /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Mask */ 339 #define SPI_IDR_RDRF SPI_IDR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_RDRF_Msk instead */ 340 #define SPI_IDR_TDRE_Pos 1 /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Position */ 341 #define SPI_IDR_TDRE_Msk (_U_(0x1) << SPI_IDR_TDRE_Pos) /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Mask */ 342 #define SPI_IDR_TDRE SPI_IDR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_TDRE_Msk instead */ 343 #define SPI_IDR_MODF_Pos 2 /**< (SPI_IDR) Mode Fault Error Interrupt Disable Position */ 344 #define SPI_IDR_MODF_Msk (_U_(0x1) << SPI_IDR_MODF_Pos) /**< (SPI_IDR) Mode Fault Error Interrupt Disable Mask */ 345 #define SPI_IDR_MODF SPI_IDR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_MODF_Msk instead */ 346 #define SPI_IDR_OVRES_Pos 3 /**< (SPI_IDR) Overrun Error Interrupt Disable Position */ 347 #define SPI_IDR_OVRES_Msk (_U_(0x1) << SPI_IDR_OVRES_Pos) /**< (SPI_IDR) Overrun Error Interrupt Disable Mask */ 348 #define SPI_IDR_OVRES SPI_IDR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_OVRES_Msk instead */ 349 #define SPI_IDR_NSSR_Pos 8 /**< (SPI_IDR) NSS Rising Interrupt Disable Position */ 350 #define SPI_IDR_NSSR_Msk (_U_(0x1) << SPI_IDR_NSSR_Pos) /**< (SPI_IDR) NSS Rising Interrupt Disable Mask */ 351 #define SPI_IDR_NSSR SPI_IDR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_NSSR_Msk instead */ 352 #define SPI_IDR_TXEMPTY_Pos 9 /**< (SPI_IDR) Transmission Registers Empty Disable Position */ 353 #define SPI_IDR_TXEMPTY_Msk (_U_(0x1) << SPI_IDR_TXEMPTY_Pos) /**< (SPI_IDR) Transmission Registers Empty Disable Mask */ 354 #define SPI_IDR_TXEMPTY SPI_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_TXEMPTY_Msk instead */ 355 #define SPI_IDR_UNDES_Pos 10 /**< (SPI_IDR) Underrun Error Interrupt Disable Position */ 356 #define SPI_IDR_UNDES_Msk (_U_(0x1) << SPI_IDR_UNDES_Pos) /**< (SPI_IDR) Underrun Error Interrupt Disable Mask */ 357 #define SPI_IDR_UNDES SPI_IDR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_UNDES_Msk instead */ 358 #define SPI_IDR_MASK _U_(0x70F) /**< \deprecated (SPI_IDR) Register MASK (Use SPI_IDR_Msk instead) */ 359 #define SPI_IDR_Msk _U_(0x70F) /**< (SPI_IDR) Register Mask */ 360 361 362 /* -------- SPI_IMR : (SPI Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */ 363 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 364 #if COMPONENT_TYPEDEF_STYLE == 'N' 365 typedef union { 366 struct { 367 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Mask */ 368 uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Mask */ 369 uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Mask */ 370 uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Mask */ 371 uint32_t :4; /**< bit: 4..7 Reserved */ 372 uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Mask */ 373 uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Mask */ 374 uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Mask */ 375 uint32_t :21; /**< bit: 11..31 Reserved */ 376 } bit; /**< Structure used for bit access */ 377 uint32_t reg; /**< Type used for register access */ 378 } SPI_IMR_Type; 379 #endif 380 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 381 382 #define SPI_IMR_OFFSET (0x1C) /**< (SPI_IMR) Interrupt Mask Register Offset */ 383 384 #define SPI_IMR_RDRF_Pos 0 /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Position */ 385 #define SPI_IMR_RDRF_Msk (_U_(0x1) << SPI_IMR_RDRF_Pos) /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Mask */ 386 #define SPI_IMR_RDRF SPI_IMR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_RDRF_Msk instead */ 387 #define SPI_IMR_TDRE_Pos 1 /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Position */ 388 #define SPI_IMR_TDRE_Msk (_U_(0x1) << SPI_IMR_TDRE_Pos) /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Mask */ 389 #define SPI_IMR_TDRE SPI_IMR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_TDRE_Msk instead */ 390 #define SPI_IMR_MODF_Pos 2 /**< (SPI_IMR) Mode Fault Error Interrupt Mask Position */ 391 #define SPI_IMR_MODF_Msk (_U_(0x1) << SPI_IMR_MODF_Pos) /**< (SPI_IMR) Mode Fault Error Interrupt Mask Mask */ 392 #define SPI_IMR_MODF SPI_IMR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_MODF_Msk instead */ 393 #define SPI_IMR_OVRES_Pos 3 /**< (SPI_IMR) Overrun Error Interrupt Mask Position */ 394 #define SPI_IMR_OVRES_Msk (_U_(0x1) << SPI_IMR_OVRES_Pos) /**< (SPI_IMR) Overrun Error Interrupt Mask Mask */ 395 #define SPI_IMR_OVRES SPI_IMR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_OVRES_Msk instead */ 396 #define SPI_IMR_NSSR_Pos 8 /**< (SPI_IMR) NSS Rising Interrupt Mask Position */ 397 #define SPI_IMR_NSSR_Msk (_U_(0x1) << SPI_IMR_NSSR_Pos) /**< (SPI_IMR) NSS Rising Interrupt Mask Mask */ 398 #define SPI_IMR_NSSR SPI_IMR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_NSSR_Msk instead */ 399 #define SPI_IMR_TXEMPTY_Pos 9 /**< (SPI_IMR) Transmission Registers Empty Mask Position */ 400 #define SPI_IMR_TXEMPTY_Msk (_U_(0x1) << SPI_IMR_TXEMPTY_Pos) /**< (SPI_IMR) Transmission Registers Empty Mask Mask */ 401 #define SPI_IMR_TXEMPTY SPI_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_TXEMPTY_Msk instead */ 402 #define SPI_IMR_UNDES_Pos 10 /**< (SPI_IMR) Underrun Error Interrupt Mask Position */ 403 #define SPI_IMR_UNDES_Msk (_U_(0x1) << SPI_IMR_UNDES_Pos) /**< (SPI_IMR) Underrun Error Interrupt Mask Mask */ 404 #define SPI_IMR_UNDES SPI_IMR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_UNDES_Msk instead */ 405 #define SPI_IMR_MASK _U_(0x70F) /**< \deprecated (SPI_IMR) Register MASK (Use SPI_IMR_Msk instead) */ 406 #define SPI_IMR_Msk _U_(0x70F) /**< (SPI_IMR) Register Mask */ 407 408 409 /* -------- SPI_CSR : (SPI Offset: 0x30) (R/W 32) Chip Select Register 0 -------- */ 410 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 411 #if COMPONENT_TYPEDEF_STYLE == 'N' 412 typedef union { 413 struct { 414 uint32_t CPOL:1; /**< bit: 0 Clock Polarity */ 415 uint32_t NCPHA:1; /**< bit: 1 Clock Phase */ 416 uint32_t CSNAAT:1; /**< bit: 2 Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ 417 uint32_t CSAAT:1; /**< bit: 3 Chip Select Active After Transfer */ 418 uint32_t BITS:4; /**< bit: 4..7 Bits Per Transfer */ 419 uint32_t SCBR:8; /**< bit: 8..15 Serial Clock Bit Rate */ 420 uint32_t DLYBS:8; /**< bit: 16..23 Delay Before SPCK */ 421 uint32_t DLYBCT:8; /**< bit: 24..31 Delay Between Consecutive Transfers */ 422 } bit; /**< Structure used for bit access */ 423 uint32_t reg; /**< Type used for register access */ 424 } SPI_CSR_Type; 425 #endif 426 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 427 428 #define SPI_CSR_OFFSET (0x30) /**< (SPI_CSR) Chip Select Register 0 Offset */ 429 430 #define SPI_CSR_CPOL_Pos 0 /**< (SPI_CSR) Clock Polarity Position */ 431 #define SPI_CSR_CPOL_Msk (_U_(0x1) << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock Polarity Mask */ 432 #define SPI_CSR_CPOL SPI_CSR_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CPOL_Msk instead */ 433 #define SPI_CSR_NCPHA_Pos 1 /**< (SPI_CSR) Clock Phase Position */ 434 #define SPI_CSR_NCPHA_Msk (_U_(0x1) << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Clock Phase Mask */ 435 #define SPI_CSR_NCPHA SPI_CSR_NCPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_NCPHA_Msk instead */ 436 #define SPI_CSR_CSNAAT_Pos 2 /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Position */ 437 #define SPI_CSR_CSNAAT_Msk (_U_(0x1) << SPI_CSR_CSNAAT_Pos) /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Mask */ 438 #define SPI_CSR_CSNAAT SPI_CSR_CSNAAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CSNAAT_Msk instead */ 439 #define SPI_CSR_CSAAT_Pos 3 /**< (SPI_CSR) Chip Select Active After Transfer Position */ 440 #define SPI_CSR_CSAAT_Msk (_U_(0x1) << SPI_CSR_CSAAT_Pos) /**< (SPI_CSR) Chip Select Active After Transfer Mask */ 441 #define SPI_CSR_CSAAT SPI_CSR_CSAAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CSAAT_Msk instead */ 442 #define SPI_CSR_BITS_Pos 4 /**< (SPI_CSR) Bits Per Transfer Position */ 443 #define SPI_CSR_BITS_Msk (_U_(0xF) << SPI_CSR_BITS_Pos) /**< (SPI_CSR) Bits Per Transfer Mask */ 444 #define SPI_CSR_BITS(value) (SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)) 445 #define SPI_CSR_BITS_8_BIT_Val _U_(0x0) /**< (SPI_CSR) 8 bits for transfer */ 446 #define SPI_CSR_BITS_9_BIT_Val _U_(0x1) /**< (SPI_CSR) 9 bits for transfer */ 447 #define SPI_CSR_BITS_10_BIT_Val _U_(0x2) /**< (SPI_CSR) 10 bits for transfer */ 448 #define SPI_CSR_BITS_11_BIT_Val _U_(0x3) /**< (SPI_CSR) 11 bits for transfer */ 449 #define SPI_CSR_BITS_12_BIT_Val _U_(0x4) /**< (SPI_CSR) 12 bits for transfer */ 450 #define SPI_CSR_BITS_13_BIT_Val _U_(0x5) /**< (SPI_CSR) 13 bits for transfer */ 451 #define SPI_CSR_BITS_14_BIT_Val _U_(0x6) /**< (SPI_CSR) 14 bits for transfer */ 452 #define SPI_CSR_BITS_15_BIT_Val _U_(0x7) /**< (SPI_CSR) 15 bits for transfer */ 453 #define SPI_CSR_BITS_16_BIT_Val _U_(0x8) /**< (SPI_CSR) 16 bits for transfer */ 454 #define SPI_CSR_BITS_8_BIT (SPI_CSR_BITS_8_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 8 bits for transfer Position */ 455 #define SPI_CSR_BITS_9_BIT (SPI_CSR_BITS_9_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 9 bits for transfer Position */ 456 #define SPI_CSR_BITS_10_BIT (SPI_CSR_BITS_10_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 10 bits for transfer Position */ 457 #define SPI_CSR_BITS_11_BIT (SPI_CSR_BITS_11_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 11 bits for transfer Position */ 458 #define SPI_CSR_BITS_12_BIT (SPI_CSR_BITS_12_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 12 bits for transfer Position */ 459 #define SPI_CSR_BITS_13_BIT (SPI_CSR_BITS_13_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 13 bits for transfer Position */ 460 #define SPI_CSR_BITS_14_BIT (SPI_CSR_BITS_14_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 14 bits for transfer Position */ 461 #define SPI_CSR_BITS_15_BIT (SPI_CSR_BITS_15_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 15 bits for transfer Position */ 462 #define SPI_CSR_BITS_16_BIT (SPI_CSR_BITS_16_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 16 bits for transfer Position */ 463 #define SPI_CSR_SCBR_Pos 8 /**< (SPI_CSR) Serial Clock Bit Rate Position */ 464 #define SPI_CSR_SCBR_Msk (_U_(0xFF) << SPI_CSR_SCBR_Pos) /**< (SPI_CSR) Serial Clock Bit Rate Mask */ 465 #define SPI_CSR_SCBR(value) (SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)) 466 #define SPI_CSR_DLYBS_Pos 16 /**< (SPI_CSR) Delay Before SPCK Position */ 467 #define SPI_CSR_DLYBS_Msk (_U_(0xFF) << SPI_CSR_DLYBS_Pos) /**< (SPI_CSR) Delay Before SPCK Mask */ 468 #define SPI_CSR_DLYBS(value) (SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)) 469 #define SPI_CSR_DLYBCT_Pos 24 /**< (SPI_CSR) Delay Between Consecutive Transfers Position */ 470 #define SPI_CSR_DLYBCT_Msk (_U_(0xFF) << SPI_CSR_DLYBCT_Pos) /**< (SPI_CSR) Delay Between Consecutive Transfers Mask */ 471 #define SPI_CSR_DLYBCT(value) (SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)) 472 #define SPI_CSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SPI_CSR) Register MASK (Use SPI_CSR_Msk instead) */ 473 #define SPI_CSR_Msk _U_(0xFFFFFFFF) /**< (SPI_CSR) Register Mask */ 474 475 476 /* -------- SPI_WPMR : (SPI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 477 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 478 #if COMPONENT_TYPEDEF_STYLE == 'N' 479 typedef union { 480 struct { 481 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 482 uint32_t :7; /**< bit: 1..7 Reserved */ 483 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 484 } bit; /**< Structure used for bit access */ 485 uint32_t reg; /**< Type used for register access */ 486 } SPI_WPMR_Type; 487 #endif 488 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 489 490 #define SPI_WPMR_OFFSET (0xE4) /**< (SPI_WPMR) Write Protection Mode Register Offset */ 491 492 #define SPI_WPMR_WPEN_Pos 0 /**< (SPI_WPMR) Write Protection Enable Position */ 493 #define SPI_WPMR_WPEN_Msk (_U_(0x1) << SPI_WPMR_WPEN_Pos) /**< (SPI_WPMR) Write Protection Enable Mask */ 494 #define SPI_WPMR_WPEN SPI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_WPMR_WPEN_Msk instead */ 495 #define SPI_WPMR_WPKEY_Pos 8 /**< (SPI_WPMR) Write Protection Key Position */ 496 #define SPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Write Protection Key Mask */ 497 #define SPI_WPMR_WPKEY(value) (SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)) 498 #define SPI_WPMR_WPKEY_PASSWD_Val _U_(0x535049) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 499 #define SPI_WPMR_WPKEY_PASSWD (SPI_WPMR_WPKEY_PASSWD_Val << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 500 #define SPI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SPI_WPMR) Register MASK (Use SPI_WPMR_Msk instead) */ 501 #define SPI_WPMR_Msk _U_(0xFFFFFF01) /**< (SPI_WPMR) Register Mask */ 502 503 504 /* -------- SPI_WPSR : (SPI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 505 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 506 #if COMPONENT_TYPEDEF_STYLE == 'N' 507 typedef union { 508 struct { 509 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 510 uint32_t :7; /**< bit: 1..7 Reserved */ 511 uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */ 512 uint32_t :16; /**< bit: 16..31 Reserved */ 513 } bit; /**< Structure used for bit access */ 514 uint32_t reg; /**< Type used for register access */ 515 } SPI_WPSR_Type; 516 #endif 517 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 518 519 #define SPI_WPSR_OFFSET (0xE8) /**< (SPI_WPSR) Write Protection Status Register Offset */ 520 521 #define SPI_WPSR_WPVS_Pos 0 /**< (SPI_WPSR) Write Protection Violation Status Position */ 522 #define SPI_WPSR_WPVS_Msk (_U_(0x1) << SPI_WPSR_WPVS_Pos) /**< (SPI_WPSR) Write Protection Violation Status Mask */ 523 #define SPI_WPSR_WPVS SPI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_WPSR_WPVS_Msk instead */ 524 #define SPI_WPSR_WPVSRC_Pos 8 /**< (SPI_WPSR) Write Protection Violation Source Position */ 525 #define SPI_WPSR_WPVSRC_Msk (_U_(0xFF) << SPI_WPSR_WPVSRC_Pos) /**< (SPI_WPSR) Write Protection Violation Source Mask */ 526 #define SPI_WPSR_WPVSRC(value) (SPI_WPSR_WPVSRC_Msk & ((value) << SPI_WPSR_WPVSRC_Pos)) 527 #define SPI_WPSR_MASK _U_(0xFF01) /**< \deprecated (SPI_WPSR) Register MASK (Use SPI_WPSR_Msk instead) */ 528 #define SPI_WPSR_Msk _U_(0xFF01) /**< (SPI_WPSR) Register Mask */ 529 530 531 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 532 #if COMPONENT_TYPEDEF_STYLE == 'R' 533 /** \brief SPI hardware registers */ 534 typedef struct { 535 __O uint32_t SPI_CR; /**< (SPI Offset: 0x00) Control Register */ 536 __IO uint32_t SPI_MR; /**< (SPI Offset: 0x04) Mode Register */ 537 __I uint32_t SPI_RDR; /**< (SPI Offset: 0x08) Receive Data Register */ 538 __O uint32_t SPI_TDR; /**< (SPI Offset: 0x0C) Transmit Data Register */ 539 __I uint32_t SPI_SR; /**< (SPI Offset: 0x10) Status Register */ 540 __O uint32_t SPI_IER; /**< (SPI Offset: 0x14) Interrupt Enable Register */ 541 __O uint32_t SPI_IDR; /**< (SPI Offset: 0x18) Interrupt Disable Register */ 542 __I uint32_t SPI_IMR; /**< (SPI Offset: 0x1C) Interrupt Mask Register */ 543 __I uint8_t Reserved1[16]; 544 __IO uint32_t SPI_CSR[4]; /**< (SPI Offset: 0x30) Chip Select Register 0 */ 545 __I uint8_t Reserved2[164]; 546 __IO uint32_t SPI_WPMR; /**< (SPI Offset: 0xE4) Write Protection Mode Register */ 547 __I uint32_t SPI_WPSR; /**< (SPI Offset: 0xE8) Write Protection Status Register */ 548 } Spi; 549 550 #elif COMPONENT_TYPEDEF_STYLE == 'N' 551 /** \brief SPI hardware registers */ 552 typedef struct { 553 __O SPI_CR_Type SPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 554 __IO SPI_MR_Type SPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 555 __I SPI_RDR_Type SPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ 556 __O SPI_TDR_Type SPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ 557 __I SPI_SR_Type SPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ 558 __O SPI_IER_Type SPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ 559 __O SPI_IDR_Type SPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ 560 __I SPI_IMR_Type SPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ 561 __I uint8_t Reserved1[16]; 562 __IO SPI_CSR_Type SPI_CSR[4]; /**< Offset: 0x30 (R/W 32) Chip Select Register 0 */ 563 __I uint8_t Reserved2[164]; 564 __IO SPI_WPMR_Type SPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 565 __I SPI_WPSR_Type SPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 566 } Spi; 567 568 #else /* COMPONENT_TYPEDEF_STYLE */ 569 #error Unknown component typedef style 570 #endif /* COMPONENT_TYPEDEF_STYLE */ 571 572 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 573 /** @} end of Serial Peripheral Interface */ 574 575 #endif /* _SAME70_SPI_COMPONENT_H_ */ 576
