1 /** 2 * \file 3 * 4 * \brief Component description for ISI 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_ISI_COMPONENT_H_ 32 #define _SAME70_ISI_COMPONENT_H_ 33 #define _SAME70_ISI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Image Sensor Interface 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR ISI */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define ISI_6350 /**< (ISI) Module ID */ 46 #define REV_ISI I /**< (ISI) Module revision */ 47 48 /* -------- ISI_CFG1 : (ISI Offset: 0x00) (R/W 32) ISI Configuration 1 Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t :2; /**< bit: 0..1 Reserved */ 54 uint32_t HSYNC_POL:1; /**< bit: 2 Horizontal Synchronization Polarity */ 55 uint32_t VSYNC_POL:1; /**< bit: 3 Vertical Synchronization Polarity */ 56 uint32_t PIXCLK_POL:1; /**< bit: 4 Pixel Clock Polarity */ 57 uint32_t GRAYLE:1; /**< bit: 5 Grayscale Little Endian */ 58 uint32_t EMB_SYNC:1; /**< bit: 6 Embedded Synchronization */ 59 uint32_t CRC_SYNC:1; /**< bit: 7 Embedded Synchronization Correction */ 60 uint32_t FRATE:3; /**< bit: 8..10 Frame Rate [0..7] */ 61 uint32_t DISCR:1; /**< bit: 11 Disable Codec Request */ 62 uint32_t FULL:1; /**< bit: 12 Full Mode is Allowed */ 63 uint32_t THMASK:2; /**< bit: 13..14 Threshold Mask */ 64 uint32_t :1; /**< bit: 15 Reserved */ 65 uint32_t SLD:8; /**< bit: 16..23 Start of Line Delay */ 66 uint32_t SFD:8; /**< bit: 24..31 Start of Frame Delay */ 67 } bit; /**< Structure used for bit access */ 68 uint32_t reg; /**< Type used for register access */ 69 } ISI_CFG1_Type; 70 #endif 71 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #define ISI_CFG1_OFFSET (0x00) /**< (ISI_CFG1) ISI Configuration 1 Register Offset */ 74 75 #define ISI_CFG1_HSYNC_POL_Pos 2 /**< (ISI_CFG1) Horizontal Synchronization Polarity Position */ 76 #define ISI_CFG1_HSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_HSYNC_POL_Pos) /**< (ISI_CFG1) Horizontal Synchronization Polarity Mask */ 77 #define ISI_CFG1_HSYNC_POL ISI_CFG1_HSYNC_POL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_HSYNC_POL_Msk instead */ 78 #define ISI_CFG1_VSYNC_POL_Pos 3 /**< (ISI_CFG1) Vertical Synchronization Polarity Position */ 79 #define ISI_CFG1_VSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_VSYNC_POL_Pos) /**< (ISI_CFG1) Vertical Synchronization Polarity Mask */ 80 #define ISI_CFG1_VSYNC_POL ISI_CFG1_VSYNC_POL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_VSYNC_POL_Msk instead */ 81 #define ISI_CFG1_PIXCLK_POL_Pos 4 /**< (ISI_CFG1) Pixel Clock Polarity Position */ 82 #define ISI_CFG1_PIXCLK_POL_Msk (_U_(0x1) << ISI_CFG1_PIXCLK_POL_Pos) /**< (ISI_CFG1) Pixel Clock Polarity Mask */ 83 #define ISI_CFG1_PIXCLK_POL ISI_CFG1_PIXCLK_POL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_PIXCLK_POL_Msk instead */ 84 #define ISI_CFG1_GRAYLE_Pos 5 /**< (ISI_CFG1) Grayscale Little Endian Position */ 85 #define ISI_CFG1_GRAYLE_Msk (_U_(0x1) << ISI_CFG1_GRAYLE_Pos) /**< (ISI_CFG1) Grayscale Little Endian Mask */ 86 #define ISI_CFG1_GRAYLE ISI_CFG1_GRAYLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_GRAYLE_Msk instead */ 87 #define ISI_CFG1_EMB_SYNC_Pos 6 /**< (ISI_CFG1) Embedded Synchronization Position */ 88 #define ISI_CFG1_EMB_SYNC_Msk (_U_(0x1) << ISI_CFG1_EMB_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Mask */ 89 #define ISI_CFG1_EMB_SYNC ISI_CFG1_EMB_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_EMB_SYNC_Msk instead */ 90 #define ISI_CFG1_CRC_SYNC_Pos 7 /**< (ISI_CFG1) Embedded Synchronization Correction Position */ 91 #define ISI_CFG1_CRC_SYNC_Msk (_U_(0x1) << ISI_CFG1_CRC_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Correction Mask */ 92 #define ISI_CFG1_CRC_SYNC ISI_CFG1_CRC_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_CRC_SYNC_Msk instead */ 93 #define ISI_CFG1_FRATE_Pos 8 /**< (ISI_CFG1) Frame Rate [0..7] Position */ 94 #define ISI_CFG1_FRATE_Msk (_U_(0x7) << ISI_CFG1_FRATE_Pos) /**< (ISI_CFG1) Frame Rate [0..7] Mask */ 95 #define ISI_CFG1_FRATE(value) (ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)) 96 #define ISI_CFG1_DISCR_Pos 11 /**< (ISI_CFG1) Disable Codec Request Position */ 97 #define ISI_CFG1_DISCR_Msk (_U_(0x1) << ISI_CFG1_DISCR_Pos) /**< (ISI_CFG1) Disable Codec Request Mask */ 98 #define ISI_CFG1_DISCR ISI_CFG1_DISCR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_DISCR_Msk instead */ 99 #define ISI_CFG1_FULL_Pos 12 /**< (ISI_CFG1) Full Mode is Allowed Position */ 100 #define ISI_CFG1_FULL_Msk (_U_(0x1) << ISI_CFG1_FULL_Pos) /**< (ISI_CFG1) Full Mode is Allowed Mask */ 101 #define ISI_CFG1_FULL ISI_CFG1_FULL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_FULL_Msk instead */ 102 #define ISI_CFG1_THMASK_Pos 13 /**< (ISI_CFG1) Threshold Mask Position */ 103 #define ISI_CFG1_THMASK_Msk (_U_(0x3) << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Threshold Mask Mask */ 104 #define ISI_CFG1_THMASK(value) (ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)) 105 #define ISI_CFG1_THMASK_BEATS_4_Val _U_(0x0) /**< (ISI_CFG1) Only 4 beats AHB burst allowed */ 106 #define ISI_CFG1_THMASK_BEATS_8_Val _U_(0x1) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ 107 #define ISI_CFG1_THMASK_BEATS_16_Val _U_(0x2) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ 108 #define ISI_CFG1_THMASK_BEATS_4 (ISI_CFG1_THMASK_BEATS_4_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 beats AHB burst allowed Position */ 109 #define ISI_CFG1_THMASK_BEATS_8 (ISI_CFG1_THMASK_BEATS_8_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed Position */ 110 #define ISI_CFG1_THMASK_BEATS_16 (ISI_CFG1_THMASK_BEATS_16_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed Position */ 111 #define ISI_CFG1_SLD_Pos 16 /**< (ISI_CFG1) Start of Line Delay Position */ 112 #define ISI_CFG1_SLD_Msk (_U_(0xFF) << ISI_CFG1_SLD_Pos) /**< (ISI_CFG1) Start of Line Delay Mask */ 113 #define ISI_CFG1_SLD(value) (ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)) 114 #define ISI_CFG1_SFD_Pos 24 /**< (ISI_CFG1) Start of Frame Delay Position */ 115 #define ISI_CFG1_SFD_Msk (_U_(0xFF) << ISI_CFG1_SFD_Pos) /**< (ISI_CFG1) Start of Frame Delay Mask */ 116 #define ISI_CFG1_SFD(value) (ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)) 117 #define ISI_CFG1_Msk _U_(0xFFFF7FFC) /**< (ISI_CFG1) Register Mask */ 118 119 120 /* -------- ISI_CFG2 : (ISI Offset: 0x04) (R/W 32) ISI Configuration 2 Register -------- */ 121 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 122 #if COMPONENT_TYPEDEF_STYLE == 'N' 123 typedef union { 124 struct { 125 uint32_t IM_VSIZE:11; /**< bit: 0..10 Vertical Size of the Image Sensor [0..2047] */ 126 uint32_t GS_MODE:1; /**< bit: 11 Grayscale Pixel Format Mode */ 127 uint32_t RGB_MODE:1; /**< bit: 12 RGB Input Mode */ 128 uint32_t GRAYSCALE:1; /**< bit: 13 Grayscale Mode Format Enable */ 129 uint32_t RGB_SWAP:1; /**< bit: 14 RGB Format Swap Mode */ 130 uint32_t COL_SPACE:1; /**< bit: 15 Color Space for the Image Data */ 131 uint32_t IM_HSIZE:11; /**< bit: 16..26 Horizontal Size of the Image Sensor [0..2047] */ 132 uint32_t :1; /**< bit: 27 Reserved */ 133 uint32_t YCC_SWAP:2; /**< bit: 28..29 YCrCb Format Swap Mode */ 134 uint32_t RGB_CFG:2; /**< bit: 30..31 RGB Pixel Mapping Configuration */ 135 } bit; /**< Structure used for bit access */ 136 uint32_t reg; /**< Type used for register access */ 137 } ISI_CFG2_Type; 138 #endif 139 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #define ISI_CFG2_OFFSET (0x04) /**< (ISI_CFG2) ISI Configuration 2 Register Offset */ 142 143 #define ISI_CFG2_IM_VSIZE_Pos 0 /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Position */ 144 #define ISI_CFG2_IM_VSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_VSIZE_Pos) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Mask */ 145 #define ISI_CFG2_IM_VSIZE(value) (ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)) 146 #define ISI_CFG2_GS_MODE_Pos 11 /**< (ISI_CFG2) Grayscale Pixel Format Mode Position */ 147 #define ISI_CFG2_GS_MODE_Msk (_U_(0x1) << ISI_CFG2_GS_MODE_Pos) /**< (ISI_CFG2) Grayscale Pixel Format Mode Mask */ 148 #define ISI_CFG2_GS_MODE ISI_CFG2_GS_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_GS_MODE_Msk instead */ 149 #define ISI_CFG2_RGB_MODE_Pos 12 /**< (ISI_CFG2) RGB Input Mode Position */ 150 #define ISI_CFG2_RGB_MODE_Msk (_U_(0x1) << ISI_CFG2_RGB_MODE_Pos) /**< (ISI_CFG2) RGB Input Mode Mask */ 151 #define ISI_CFG2_RGB_MODE ISI_CFG2_RGB_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_RGB_MODE_Msk instead */ 152 #define ISI_CFG2_GRAYSCALE_Pos 13 /**< (ISI_CFG2) Grayscale Mode Format Enable Position */ 153 #define ISI_CFG2_GRAYSCALE_Msk (_U_(0x1) << ISI_CFG2_GRAYSCALE_Pos) /**< (ISI_CFG2) Grayscale Mode Format Enable Mask */ 154 #define ISI_CFG2_GRAYSCALE ISI_CFG2_GRAYSCALE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_GRAYSCALE_Msk instead */ 155 #define ISI_CFG2_RGB_SWAP_Pos 14 /**< (ISI_CFG2) RGB Format Swap Mode Position */ 156 #define ISI_CFG2_RGB_SWAP_Msk (_U_(0x1) << ISI_CFG2_RGB_SWAP_Pos) /**< (ISI_CFG2) RGB Format Swap Mode Mask */ 157 #define ISI_CFG2_RGB_SWAP ISI_CFG2_RGB_SWAP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_RGB_SWAP_Msk instead */ 158 #define ISI_CFG2_COL_SPACE_Pos 15 /**< (ISI_CFG2) Color Space for the Image Data Position */ 159 #define ISI_CFG2_COL_SPACE_Msk (_U_(0x1) << ISI_CFG2_COL_SPACE_Pos) /**< (ISI_CFG2) Color Space for the Image Data Mask */ 160 #define ISI_CFG2_COL_SPACE ISI_CFG2_COL_SPACE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_COL_SPACE_Msk instead */ 161 #define ISI_CFG2_IM_HSIZE_Pos 16 /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Position */ 162 #define ISI_CFG2_IM_HSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_HSIZE_Pos) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Mask */ 163 #define ISI_CFG2_IM_HSIZE(value) (ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)) 164 #define ISI_CFG2_YCC_SWAP_Pos 28 /**< (ISI_CFG2) YCrCb Format Swap Mode Position */ 165 #define ISI_CFG2_YCC_SWAP_Msk (_U_(0x3) << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) YCrCb Format Swap Mode Mask */ 166 #define ISI_CFG2_YCC_SWAP(value) (ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)) 167 #define ISI_CFG2_YCC_SWAP_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ 168 #define ISI_CFG2_YCC_SWAP_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ 169 #define ISI_CFG2_YCC_SWAP_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ 170 #define ISI_CFG2_YCC_SWAP_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ 171 #define ISI_CFG2_YCC_SWAP_DEFAULT (ISI_CFG2_YCC_SWAP_DEFAULT_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) Position */ 172 #define ISI_CFG2_YCC_SWAP_MODE1 (ISI_CFG2_YCC_SWAP_MODE1_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) Position */ 173 #define ISI_CFG2_YCC_SWAP_MODE2 (ISI_CFG2_YCC_SWAP_MODE2_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) Position */ 174 #define ISI_CFG2_YCC_SWAP_MODE3 (ISI_CFG2_YCC_SWAP_MODE3_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) Position */ 175 #define ISI_CFG2_RGB_CFG_Pos 30 /**< (ISI_CFG2) RGB Pixel Mapping Configuration Position */ 176 #define ISI_CFG2_RGB_CFG_Msk (_U_(0x3) << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Mask */ 177 #define ISI_CFG2_RGB_CFG(value) (ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)) 178 #define ISI_CFG2_RGB_CFG_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ 179 #define ISI_CFG2_RGB_CFG_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ 180 #define ISI_CFG2_RGB_CFG_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ 181 #define ISI_CFG2_RGB_CFG_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ 182 #define ISI_CFG2_RGB_CFG_DEFAULT (ISI_CFG2_RGB_CFG_DEFAULT_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B Position */ 183 #define ISI_CFG2_RGB_CFG_MODE1 (ISI_CFG2_RGB_CFG_MODE1_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R Position */ 184 #define ISI_CFG2_RGB_CFG_MODE2 (ISI_CFG2_RGB_CFG_MODE2_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) Position */ 185 #define ISI_CFG2_RGB_CFG_MODE3 (ISI_CFG2_RGB_CFG_MODE3_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) Position */ 186 #define ISI_CFG2_MASK _U_(0xF7FFFFFF) /**< \deprecated (ISI_CFG2) Register MASK (Use ISI_CFG2_Msk instead) */ 187 #define ISI_CFG2_Msk _U_(0xF7FFFFFF) /**< (ISI_CFG2) Register Mask */ 188 189 190 /* -------- ISI_PSIZE : (ISI Offset: 0x08) (R/W 32) ISI Preview Size Register -------- */ 191 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 192 #if COMPONENT_TYPEDEF_STYLE == 'N' 193 typedef union { 194 struct { 195 uint32_t PREV_VSIZE:10; /**< bit: 0..9 Vertical Size for the Preview Path */ 196 uint32_t :6; /**< bit: 10..15 Reserved */ 197 uint32_t PREV_HSIZE:10; /**< bit: 16..25 Horizontal Size for the Preview Path */ 198 uint32_t :6; /**< bit: 26..31 Reserved */ 199 } bit; /**< Structure used for bit access */ 200 uint32_t reg; /**< Type used for register access */ 201 } ISI_PSIZE_Type; 202 #endif 203 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define ISI_PSIZE_OFFSET (0x08) /**< (ISI_PSIZE) ISI Preview Size Register Offset */ 206 207 #define ISI_PSIZE_PREV_VSIZE_Pos 0 /**< (ISI_PSIZE) Vertical Size for the Preview Path Position */ 208 #define ISI_PSIZE_PREV_VSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_VSIZE_Pos) /**< (ISI_PSIZE) Vertical Size for the Preview Path Mask */ 209 #define ISI_PSIZE_PREV_VSIZE(value) (ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)) 210 #define ISI_PSIZE_PREV_HSIZE_Pos 16 /**< (ISI_PSIZE) Horizontal Size for the Preview Path Position */ 211 #define ISI_PSIZE_PREV_HSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_HSIZE_Pos) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Mask */ 212 #define ISI_PSIZE_PREV_HSIZE(value) (ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)) 213 #define ISI_PSIZE_MASK _U_(0x3FF03FF) /**< \deprecated (ISI_PSIZE) Register MASK (Use ISI_PSIZE_Msk instead) */ 214 #define ISI_PSIZE_Msk _U_(0x3FF03FF) /**< (ISI_PSIZE) Register Mask */ 215 216 217 /* -------- ISI_PDECF : (ISI Offset: 0x0c) (R/W 32) ISI Preview Decimation Factor Register -------- */ 218 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 219 #if COMPONENT_TYPEDEF_STYLE == 'N' 220 typedef union { 221 struct { 222 uint32_t DEC_FACTOR:8; /**< bit: 0..7 Decimation Factor */ 223 uint32_t :24; /**< bit: 8..31 Reserved */ 224 } bit; /**< Structure used for bit access */ 225 uint32_t reg; /**< Type used for register access */ 226 } ISI_PDECF_Type; 227 #endif 228 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define ISI_PDECF_OFFSET (0x0C) /**< (ISI_PDECF) ISI Preview Decimation Factor Register Offset */ 231 232 #define ISI_PDECF_DEC_FACTOR_Pos 0 /**< (ISI_PDECF) Decimation Factor Position */ 233 #define ISI_PDECF_DEC_FACTOR_Msk (_U_(0xFF) << ISI_PDECF_DEC_FACTOR_Pos) /**< (ISI_PDECF) Decimation Factor Mask */ 234 #define ISI_PDECF_DEC_FACTOR(value) (ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)) 235 #define ISI_PDECF_MASK _U_(0xFF) /**< \deprecated (ISI_PDECF) Register MASK (Use ISI_PDECF_Msk instead) */ 236 #define ISI_PDECF_Msk _U_(0xFF) /**< (ISI_PDECF) Register Mask */ 237 238 239 /* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ 240 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 241 #if COMPONENT_TYPEDEF_STYLE == 'N' 242 typedef union { 243 struct { 244 uint32_t C0:8; /**< bit: 0..7 Color Space Conversion Matrix Coefficient C0 */ 245 uint32_t C1:8; /**< bit: 8..15 Color Space Conversion Matrix Coefficient C1 */ 246 uint32_t C2:8; /**< bit: 16..23 Color Space Conversion Matrix Coefficient C2 */ 247 uint32_t C3:8; /**< bit: 24..31 Color Space Conversion Matrix Coefficient C3 */ 248 } bit; /**< Structure used for bit access */ 249 uint32_t reg; /**< Type used for register access */ 250 } ISI_Y2R_SET0_Type; 251 #endif 252 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 253 254 #define ISI_Y2R_SET0_OFFSET (0x10) /**< (ISI_Y2R_SET0) ISI Color Space Conversion YCrCb To RGB Set 0 Register Offset */ 255 256 #define ISI_Y2R_SET0_C0_Pos 0 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Position */ 257 #define ISI_Y2R_SET0_C0_Msk (_U_(0xFF) << ISI_Y2R_SET0_C0_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ 258 #define ISI_Y2R_SET0_C0(value) (ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)) 259 #define ISI_Y2R_SET0_C1_Pos 8 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Position */ 260 #define ISI_Y2R_SET0_C1_Msk (_U_(0xFF) << ISI_Y2R_SET0_C1_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ 261 #define ISI_Y2R_SET0_C1(value) (ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)) 262 #define ISI_Y2R_SET0_C2_Pos 16 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Position */ 263 #define ISI_Y2R_SET0_C2_Msk (_U_(0xFF) << ISI_Y2R_SET0_C2_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ 264 #define ISI_Y2R_SET0_C2(value) (ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)) 265 #define ISI_Y2R_SET0_C3_Pos 24 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Position */ 266 #define ISI_Y2R_SET0_C3_Msk (_U_(0xFF) << ISI_Y2R_SET0_C3_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Mask */ 267 #define ISI_Y2R_SET0_C3(value) (ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)) 268 #define ISI_Y2R_SET0_MASK _U_(0xFFFFFFFF) /**< \deprecated (ISI_Y2R_SET0) Register MASK (Use ISI_Y2R_SET0_Msk instead) */ 269 #define ISI_Y2R_SET0_Msk _U_(0xFFFFFFFF) /**< (ISI_Y2R_SET0) Register Mask */ 270 271 272 /* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ 273 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 274 #if COMPONENT_TYPEDEF_STYLE == 'N' 275 typedef union { 276 struct { 277 uint32_t C4:9; /**< bit: 0..8 Color Space Conversion Matrix Coefficient C4 */ 278 uint32_t :3; /**< bit: 9..11 Reserved */ 279 uint32_t Yoff:1; /**< bit: 12 Color Space Conversion Luminance Default Offset */ 280 uint32_t Croff:1; /**< bit: 13 Color Space Conversion Red Chrominance Default Offset */ 281 uint32_t Cboff:1; /**< bit: 14 Color Space Conversion Blue Chrominance Default Offset */ 282 uint32_t :17; /**< bit: 15..31 Reserved */ 283 } bit; /**< Structure used for bit access */ 284 uint32_t reg; /**< Type used for register access */ 285 } ISI_Y2R_SET1_Type; 286 #endif 287 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 288 289 #define ISI_Y2R_SET1_OFFSET (0x14) /**< (ISI_Y2R_SET1) ISI Color Space Conversion YCrCb To RGB Set 1 Register Offset */ 290 291 #define ISI_Y2R_SET1_C4_Pos 0 /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Position */ 292 #define ISI_Y2R_SET1_C4_Msk (_U_(0x1FF) << ISI_Y2R_SET1_C4_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ 293 #define ISI_Y2R_SET1_C4(value) (ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)) 294 #define ISI_Y2R_SET1_Yoff_Pos 12 /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Position */ 295 #define ISI_Y2R_SET1_Yoff_Msk (_U_(0x1) << ISI_Y2R_SET1_Yoff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Mask */ 296 #define ISI_Y2R_SET1_Yoff ISI_Y2R_SET1_Yoff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_Y2R_SET1_Yoff_Msk instead */ 297 #define ISI_Y2R_SET1_Croff_Pos 13 /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Position */ 298 #define ISI_Y2R_SET1_Croff_Msk (_U_(0x1) << ISI_Y2R_SET1_Croff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Mask */ 299 #define ISI_Y2R_SET1_Croff ISI_Y2R_SET1_Croff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_Y2R_SET1_Croff_Msk instead */ 300 #define ISI_Y2R_SET1_Cboff_Pos 14 /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Position */ 301 #define ISI_Y2R_SET1_Cboff_Msk (_U_(0x1) << ISI_Y2R_SET1_Cboff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Mask */ 302 #define ISI_Y2R_SET1_Cboff ISI_Y2R_SET1_Cboff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_Y2R_SET1_Cboff_Msk instead */ 303 #define ISI_Y2R_SET1_MASK _U_(0x71FF) /**< \deprecated (ISI_Y2R_SET1) Register MASK (Use ISI_Y2R_SET1_Msk instead) */ 304 #define ISI_Y2R_SET1_Msk _U_(0x71FF) /**< (ISI_Y2R_SET1) Register Mask */ 305 306 307 /* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ 308 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 309 #if COMPONENT_TYPEDEF_STYLE == 'N' 310 typedef union { 311 struct { 312 uint32_t C0:7; /**< bit: 0..6 Color Space Conversion Matrix Coefficient C0 */ 313 uint32_t :1; /**< bit: 7 Reserved */ 314 uint32_t C1:7; /**< bit: 8..14 Color Space Conversion Matrix Coefficient C1 */ 315 uint32_t :1; /**< bit: 15 Reserved */ 316 uint32_t C2:7; /**< bit: 16..22 Color Space Conversion Matrix Coefficient C2 */ 317 uint32_t :1; /**< bit: 23 Reserved */ 318 uint32_t Roff:1; /**< bit: 24 Color Space Conversion Red Component Offset */ 319 uint32_t :7; /**< bit: 25..31 Reserved */ 320 } bit; /**< Structure used for bit access */ 321 uint32_t reg; /**< Type used for register access */ 322 } ISI_R2Y_SET0_Type; 323 #endif 324 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 325 326 #define ISI_R2Y_SET0_OFFSET (0x18) /**< (ISI_R2Y_SET0) ISI Color Space Conversion RGB To YCrCb Set 0 Register Offset */ 327 328 #define ISI_R2Y_SET0_C0_Pos 0 /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Position */ 329 #define ISI_R2Y_SET0_C0_Msk (_U_(0x7F) << ISI_R2Y_SET0_C0_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ 330 #define ISI_R2Y_SET0_C0(value) (ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)) 331 #define ISI_R2Y_SET0_C1_Pos 8 /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Position */ 332 #define ISI_R2Y_SET0_C1_Msk (_U_(0x7F) << ISI_R2Y_SET0_C1_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ 333 #define ISI_R2Y_SET0_C1(value) (ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)) 334 #define ISI_R2Y_SET0_C2_Pos 16 /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Position */ 335 #define ISI_R2Y_SET0_C2_Msk (_U_(0x7F) << ISI_R2Y_SET0_C2_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ 336 #define ISI_R2Y_SET0_C2(value) (ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)) 337 #define ISI_R2Y_SET0_Roff_Pos 24 /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Position */ 338 #define ISI_R2Y_SET0_Roff_Msk (_U_(0x1) << ISI_R2Y_SET0_Roff_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Mask */ 339 #define ISI_R2Y_SET0_Roff ISI_R2Y_SET0_Roff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_R2Y_SET0_Roff_Msk instead */ 340 #define ISI_R2Y_SET0_MASK _U_(0x17F7F7F) /**< \deprecated (ISI_R2Y_SET0) Register MASK (Use ISI_R2Y_SET0_Msk instead) */ 341 #define ISI_R2Y_SET0_Msk _U_(0x17F7F7F) /**< (ISI_R2Y_SET0) Register Mask */ 342 343 344 /* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1c) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ 345 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 346 #if COMPONENT_TYPEDEF_STYLE == 'N' 347 typedef union { 348 struct { 349 uint32_t C3:7; /**< bit: 0..6 Color Space Conversion Matrix Coefficient C3 */ 350 uint32_t :1; /**< bit: 7 Reserved */ 351 uint32_t C4:7; /**< bit: 8..14 Color Space Conversion Matrix Coefficient C4 */ 352 uint32_t :1; /**< bit: 15 Reserved */ 353 uint32_t C5:7; /**< bit: 16..22 Color Space Conversion Matrix Coefficient C5 */ 354 uint32_t :1; /**< bit: 23 Reserved */ 355 uint32_t Goff:1; /**< bit: 24 Color Space Conversion Green Component Offset */ 356 uint32_t :7; /**< bit: 25..31 Reserved */ 357 } bit; /**< Structure used for bit access */ 358 uint32_t reg; /**< Type used for register access */ 359 } ISI_R2Y_SET1_Type; 360 #endif 361 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 362 363 #define ISI_R2Y_SET1_OFFSET (0x1C) /**< (ISI_R2Y_SET1) ISI Color Space Conversion RGB To YCrCb Set 1 Register Offset */ 364 365 #define ISI_R2Y_SET1_C3_Pos 0 /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Position */ 366 #define ISI_R2Y_SET1_C3_Msk (_U_(0x7F) << ISI_R2Y_SET1_C3_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Mask */ 367 #define ISI_R2Y_SET1_C3(value) (ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)) 368 #define ISI_R2Y_SET1_C4_Pos 8 /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Position */ 369 #define ISI_R2Y_SET1_C4_Msk (_U_(0x7F) << ISI_R2Y_SET1_C4_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ 370 #define ISI_R2Y_SET1_C4(value) (ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)) 371 #define ISI_R2Y_SET1_C5_Pos 16 /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Position */ 372 #define ISI_R2Y_SET1_C5_Msk (_U_(0x7F) << ISI_R2Y_SET1_C5_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Mask */ 373 #define ISI_R2Y_SET1_C5(value) (ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)) 374 #define ISI_R2Y_SET1_Goff_Pos 24 /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Position */ 375 #define ISI_R2Y_SET1_Goff_Msk (_U_(0x1) << ISI_R2Y_SET1_Goff_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Mask */ 376 #define ISI_R2Y_SET1_Goff ISI_R2Y_SET1_Goff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_R2Y_SET1_Goff_Msk instead */ 377 #define ISI_R2Y_SET1_MASK _U_(0x17F7F7F) /**< \deprecated (ISI_R2Y_SET1) Register MASK (Use ISI_R2Y_SET1_Msk instead) */ 378 #define ISI_R2Y_SET1_Msk _U_(0x17F7F7F) /**< (ISI_R2Y_SET1) Register Mask */ 379 380 381 /* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ 382 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 383 #if COMPONENT_TYPEDEF_STYLE == 'N' 384 typedef union { 385 struct { 386 uint32_t C6:7; /**< bit: 0..6 Color Space Conversion Matrix Coefficient C6 */ 387 uint32_t :1; /**< bit: 7 Reserved */ 388 uint32_t C7:7; /**< bit: 8..14 Color Space Conversion Matrix Coefficient C7 */ 389 uint32_t :1; /**< bit: 15 Reserved */ 390 uint32_t C8:7; /**< bit: 16..22 Color Space Conversion Matrix Coefficient C8 */ 391 uint32_t :1; /**< bit: 23 Reserved */ 392 uint32_t Boff:1; /**< bit: 24 Color Space Conversion Blue Component Offset */ 393 uint32_t :7; /**< bit: 25..31 Reserved */ 394 } bit; /**< Structure used for bit access */ 395 uint32_t reg; /**< Type used for register access */ 396 } ISI_R2Y_SET2_Type; 397 #endif 398 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 399 400 #define ISI_R2Y_SET2_OFFSET (0x20) /**< (ISI_R2Y_SET2) ISI Color Space Conversion RGB To YCrCb Set 2 Register Offset */ 401 402 #define ISI_R2Y_SET2_C6_Pos 0 /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Position */ 403 #define ISI_R2Y_SET2_C6_Msk (_U_(0x7F) << ISI_R2Y_SET2_C6_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Mask */ 404 #define ISI_R2Y_SET2_C6(value) (ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)) 405 #define ISI_R2Y_SET2_C7_Pos 8 /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Position */ 406 #define ISI_R2Y_SET2_C7_Msk (_U_(0x7F) << ISI_R2Y_SET2_C7_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Mask */ 407 #define ISI_R2Y_SET2_C7(value) (ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)) 408 #define ISI_R2Y_SET2_C8_Pos 16 /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Position */ 409 #define ISI_R2Y_SET2_C8_Msk (_U_(0x7F) << ISI_R2Y_SET2_C8_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Mask */ 410 #define ISI_R2Y_SET2_C8(value) (ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)) 411 #define ISI_R2Y_SET2_Boff_Pos 24 /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Position */ 412 #define ISI_R2Y_SET2_Boff_Msk (_U_(0x1) << ISI_R2Y_SET2_Boff_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Mask */ 413 #define ISI_R2Y_SET2_Boff ISI_R2Y_SET2_Boff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_R2Y_SET2_Boff_Msk instead */ 414 #define ISI_R2Y_SET2_MASK _U_(0x17F7F7F) /**< \deprecated (ISI_R2Y_SET2) Register MASK (Use ISI_R2Y_SET2_Msk instead) */ 415 #define ISI_R2Y_SET2_Msk _U_(0x17F7F7F) /**< (ISI_R2Y_SET2) Register Mask */ 416 417 418 /* -------- ISI_CR : (ISI Offset: 0x24) (/W 32) ISI Control Register -------- */ 419 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 420 #if COMPONENT_TYPEDEF_STYLE == 'N' 421 typedef union { 422 struct { 423 uint32_t ISI_EN:1; /**< bit: 0 ISI Module Enable Request */ 424 uint32_t ISI_DIS:1; /**< bit: 1 ISI Module Disable Request */ 425 uint32_t ISI_SRST:1; /**< bit: 2 ISI Software Reset Request */ 426 uint32_t :5; /**< bit: 3..7 Reserved */ 427 uint32_t ISI_CDC:1; /**< bit: 8 ISI Codec Request */ 428 uint32_t :23; /**< bit: 9..31 Reserved */ 429 } bit; /**< Structure used for bit access */ 430 uint32_t reg; /**< Type used for register access */ 431 } ISI_CR_Type; 432 #endif 433 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 434 435 #define ISI_CR_OFFSET (0x24) /**< (ISI_CR) ISI Control Register Offset */ 436 437 #define ISI_CR_ISI_EN_Pos 0 /**< (ISI_CR) ISI Module Enable Request Position */ 438 #define ISI_CR_ISI_EN_Msk (_U_(0x1) << ISI_CR_ISI_EN_Pos) /**< (ISI_CR) ISI Module Enable Request Mask */ 439 #define ISI_CR_ISI_EN ISI_CR_ISI_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_EN_Msk instead */ 440 #define ISI_CR_ISI_DIS_Pos 1 /**< (ISI_CR) ISI Module Disable Request Position */ 441 #define ISI_CR_ISI_DIS_Msk (_U_(0x1) << ISI_CR_ISI_DIS_Pos) /**< (ISI_CR) ISI Module Disable Request Mask */ 442 #define ISI_CR_ISI_DIS ISI_CR_ISI_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_DIS_Msk instead */ 443 #define ISI_CR_ISI_SRST_Pos 2 /**< (ISI_CR) ISI Software Reset Request Position */ 444 #define ISI_CR_ISI_SRST_Msk (_U_(0x1) << ISI_CR_ISI_SRST_Pos) /**< (ISI_CR) ISI Software Reset Request Mask */ 445 #define ISI_CR_ISI_SRST ISI_CR_ISI_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_SRST_Msk instead */ 446 #define ISI_CR_ISI_CDC_Pos 8 /**< (ISI_CR) ISI Codec Request Position */ 447 #define ISI_CR_ISI_CDC_Msk (_U_(0x1) << ISI_CR_ISI_CDC_Pos) /**< (ISI_CR) ISI Codec Request Mask */ 448 #define ISI_CR_ISI_CDC ISI_CR_ISI_CDC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_CDC_Msk instead */ 449 #define ISI_CR_MASK _U_(0x107) /**< \deprecated (ISI_CR) Register MASK (Use ISI_CR_Msk instead) */ 450 #define ISI_CR_Msk _U_(0x107) /**< (ISI_CR) Register Mask */ 451 452 453 /* -------- ISI_SR : (ISI Offset: 0x28) (R/ 32) ISI Status Register -------- */ 454 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 455 #if COMPONENT_TYPEDEF_STYLE == 'N' 456 typedef union { 457 struct { 458 uint32_t ENABLE:1; /**< bit: 0 Module Enable */ 459 uint32_t DIS_DONE:1; /**< bit: 1 Module Disable Request has Terminated (cleared on read) */ 460 uint32_t SRST:1; /**< bit: 2 Module Software Reset Request has Terminated (cleared on read) */ 461 uint32_t :5; /**< bit: 3..7 Reserved */ 462 uint32_t CDC_PND:1; /**< bit: 8 Pending Codec Request */ 463 uint32_t :1; /**< bit: 9 Reserved */ 464 uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization (cleared on read) */ 465 uint32_t :5; /**< bit: 11..15 Reserved */ 466 uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer has Terminated (cleared on read) */ 467 uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer has Terminated (cleared on read) */ 468 uint32_t :1; /**< bit: 18 Reserved */ 469 uint32_t SIP:1; /**< bit: 19 Synchronization in Progress */ 470 uint32_t :4; /**< bit: 20..23 Reserved */ 471 uint32_t P_OVR:1; /**< bit: 24 Preview Datapath Overflow (cleared on read) */ 472 uint32_t C_OVR:1; /**< bit: 25 Codec Datapath Overflow (cleared on read) */ 473 uint32_t CRC_ERR:1; /**< bit: 26 CRC Synchronization Error (cleared on read) */ 474 uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overrun (cleared on read) */ 475 uint32_t :4; /**< bit: 28..31 Reserved */ 476 } bit; /**< Structure used for bit access */ 477 uint32_t reg; /**< Type used for register access */ 478 } ISI_SR_Type; 479 #endif 480 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 481 482 #define ISI_SR_OFFSET (0x28) /**< (ISI_SR) ISI Status Register Offset */ 483 484 #define ISI_SR_ENABLE_Pos 0 /**< (ISI_SR) Module Enable Position */ 485 #define ISI_SR_ENABLE_Msk (_U_(0x1) << ISI_SR_ENABLE_Pos) /**< (ISI_SR) Module Enable Mask */ 486 #define ISI_SR_ENABLE ISI_SR_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_ENABLE_Msk instead */ 487 #define ISI_SR_DIS_DONE_Pos 1 /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Position */ 488 #define ISI_SR_DIS_DONE_Msk (_U_(0x1) << ISI_SR_DIS_DONE_Pos) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Mask */ 489 #define ISI_SR_DIS_DONE ISI_SR_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_DIS_DONE_Msk instead */ 490 #define ISI_SR_SRST_Pos 2 /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Position */ 491 #define ISI_SR_SRST_Msk (_U_(0x1) << ISI_SR_SRST_Pos) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Mask */ 492 #define ISI_SR_SRST ISI_SR_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_SRST_Msk instead */ 493 #define ISI_SR_CDC_PND_Pos 8 /**< (ISI_SR) Pending Codec Request Position */ 494 #define ISI_SR_CDC_PND_Msk (_U_(0x1) << ISI_SR_CDC_PND_Pos) /**< (ISI_SR) Pending Codec Request Mask */ 495 #define ISI_SR_CDC_PND ISI_SR_CDC_PND_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_CDC_PND_Msk instead */ 496 #define ISI_SR_VSYNC_Pos 10 /**< (ISI_SR) Vertical Synchronization (cleared on read) Position */ 497 #define ISI_SR_VSYNC_Msk (_U_(0x1) << ISI_SR_VSYNC_Pos) /**< (ISI_SR) Vertical Synchronization (cleared on read) Mask */ 498 #define ISI_SR_VSYNC ISI_SR_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_VSYNC_Msk instead */ 499 #define ISI_SR_PXFR_DONE_Pos 16 /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Position */ 500 #define ISI_SR_PXFR_DONE_Msk (_U_(0x1) << ISI_SR_PXFR_DONE_Pos) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Mask */ 501 #define ISI_SR_PXFR_DONE ISI_SR_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_PXFR_DONE_Msk instead */ 502 #define ISI_SR_CXFR_DONE_Pos 17 /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Position */ 503 #define ISI_SR_CXFR_DONE_Msk (_U_(0x1) << ISI_SR_CXFR_DONE_Pos) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Mask */ 504 #define ISI_SR_CXFR_DONE ISI_SR_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_CXFR_DONE_Msk instead */ 505 #define ISI_SR_SIP_Pos 19 /**< (ISI_SR) Synchronization in Progress Position */ 506 #define ISI_SR_SIP_Msk (_U_(0x1) << ISI_SR_SIP_Pos) /**< (ISI_SR) Synchronization in Progress Mask */ 507 #define ISI_SR_SIP ISI_SR_SIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_SIP_Msk instead */ 508 #define ISI_SR_P_OVR_Pos 24 /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Position */ 509 #define ISI_SR_P_OVR_Msk (_U_(0x1) << ISI_SR_P_OVR_Pos) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Mask */ 510 #define ISI_SR_P_OVR ISI_SR_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_P_OVR_Msk instead */ 511 #define ISI_SR_C_OVR_Pos 25 /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Position */ 512 #define ISI_SR_C_OVR_Msk (_U_(0x1) << ISI_SR_C_OVR_Pos) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Mask */ 513 #define ISI_SR_C_OVR ISI_SR_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_C_OVR_Msk instead */ 514 #define ISI_SR_CRC_ERR_Pos 26 /**< (ISI_SR) CRC Synchronization Error (cleared on read) Position */ 515 #define ISI_SR_CRC_ERR_Msk (_U_(0x1) << ISI_SR_CRC_ERR_Pos) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Mask */ 516 #define ISI_SR_CRC_ERR ISI_SR_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_CRC_ERR_Msk instead */ 517 #define ISI_SR_FR_OVR_Pos 27 /**< (ISI_SR) Frame Rate Overrun (cleared on read) Position */ 518 #define ISI_SR_FR_OVR_Msk (_U_(0x1) << ISI_SR_FR_OVR_Pos) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Mask */ 519 #define ISI_SR_FR_OVR ISI_SR_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_FR_OVR_Msk instead */ 520 #define ISI_SR_MASK _U_(0xF0B0507) /**< \deprecated (ISI_SR) Register MASK (Use ISI_SR_Msk instead) */ 521 #define ISI_SR_Msk _U_(0xF0B0507) /**< (ISI_SR) Register Mask */ 522 523 524 /* -------- ISI_IER : (ISI Offset: 0x2c) (/W 32) ISI Interrupt Enable Register -------- */ 525 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 526 #if COMPONENT_TYPEDEF_STYLE == 'N' 527 typedef union { 528 struct { 529 uint32_t :1; /**< bit: 0 Reserved */ 530 uint32_t DIS_DONE:1; /**< bit: 1 Disable Done Interrupt Enable */ 531 uint32_t SRST:1; /**< bit: 2 Software Reset Interrupt Enable */ 532 uint32_t :7; /**< bit: 3..9 Reserved */ 533 uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization Interrupt Enable */ 534 uint32_t :5; /**< bit: 11..15 Reserved */ 535 uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer Done Interrupt Enable */ 536 uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer Done Interrupt Enable */ 537 uint32_t :6; /**< bit: 18..23 Reserved */ 538 uint32_t P_OVR:1; /**< bit: 24 Preview Datapath Overflow Interrupt Enable */ 539 uint32_t C_OVR:1; /**< bit: 25 Codec Datapath Overflow Interrupt Enable */ 540 uint32_t CRC_ERR:1; /**< bit: 26 Embedded Synchronization CRC Error Interrupt Enable */ 541 uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overflow Interrupt Enable */ 542 uint32_t :4; /**< bit: 28..31 Reserved */ 543 } bit; /**< Structure used for bit access */ 544 uint32_t reg; /**< Type used for register access */ 545 } ISI_IER_Type; 546 #endif 547 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 548 549 #define ISI_IER_OFFSET (0x2C) /**< (ISI_IER) ISI Interrupt Enable Register Offset */ 550 551 #define ISI_IER_DIS_DONE_Pos 1 /**< (ISI_IER) Disable Done Interrupt Enable Position */ 552 #define ISI_IER_DIS_DONE_Msk (_U_(0x1) << ISI_IER_DIS_DONE_Pos) /**< (ISI_IER) Disable Done Interrupt Enable Mask */ 553 #define ISI_IER_DIS_DONE ISI_IER_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_DIS_DONE_Msk instead */ 554 #define ISI_IER_SRST_Pos 2 /**< (ISI_IER) Software Reset Interrupt Enable Position */ 555 #define ISI_IER_SRST_Msk (_U_(0x1) << ISI_IER_SRST_Pos) /**< (ISI_IER) Software Reset Interrupt Enable Mask */ 556 #define ISI_IER_SRST ISI_IER_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_SRST_Msk instead */ 557 #define ISI_IER_VSYNC_Pos 10 /**< (ISI_IER) Vertical Synchronization Interrupt Enable Position */ 558 #define ISI_IER_VSYNC_Msk (_U_(0x1) << ISI_IER_VSYNC_Pos) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Mask */ 559 #define ISI_IER_VSYNC ISI_IER_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_VSYNC_Msk instead */ 560 #define ISI_IER_PXFR_DONE_Pos 16 /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Position */ 561 #define ISI_IER_PXFR_DONE_Msk (_U_(0x1) << ISI_IER_PXFR_DONE_Pos) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Mask */ 562 #define ISI_IER_PXFR_DONE ISI_IER_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_PXFR_DONE_Msk instead */ 563 #define ISI_IER_CXFR_DONE_Pos 17 /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Position */ 564 #define ISI_IER_CXFR_DONE_Msk (_U_(0x1) << ISI_IER_CXFR_DONE_Pos) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Mask */ 565 #define ISI_IER_CXFR_DONE ISI_IER_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_CXFR_DONE_Msk instead */ 566 #define ISI_IER_P_OVR_Pos 24 /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Position */ 567 #define ISI_IER_P_OVR_Msk (_U_(0x1) << ISI_IER_P_OVR_Pos) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Mask */ 568 #define ISI_IER_P_OVR ISI_IER_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_P_OVR_Msk instead */ 569 #define ISI_IER_C_OVR_Pos 25 /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Position */ 570 #define ISI_IER_C_OVR_Msk (_U_(0x1) << ISI_IER_C_OVR_Pos) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Mask */ 571 #define ISI_IER_C_OVR ISI_IER_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_C_OVR_Msk instead */ 572 #define ISI_IER_CRC_ERR_Pos 26 /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Position */ 573 #define ISI_IER_CRC_ERR_Msk (_U_(0x1) << ISI_IER_CRC_ERR_Pos) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Mask */ 574 #define ISI_IER_CRC_ERR ISI_IER_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_CRC_ERR_Msk instead */ 575 #define ISI_IER_FR_OVR_Pos 27 /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Position */ 576 #define ISI_IER_FR_OVR_Msk (_U_(0x1) << ISI_IER_FR_OVR_Pos) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Mask */ 577 #define ISI_IER_FR_OVR ISI_IER_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_FR_OVR_Msk instead */ 578 #define ISI_IER_MASK _U_(0xF030406) /**< \deprecated (ISI_IER) Register MASK (Use ISI_IER_Msk instead) */ 579 #define ISI_IER_Msk _U_(0xF030406) /**< (ISI_IER) Register Mask */ 580 581 582 /* -------- ISI_IDR : (ISI Offset: 0x30) (/W 32) ISI Interrupt Disable Register -------- */ 583 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 584 #if COMPONENT_TYPEDEF_STYLE == 'N' 585 typedef union { 586 struct { 587 uint32_t :1; /**< bit: 0 Reserved */ 588 uint32_t DIS_DONE:1; /**< bit: 1 Disable Done Interrupt Disable */ 589 uint32_t SRST:1; /**< bit: 2 Software Reset Interrupt Disable */ 590 uint32_t :7; /**< bit: 3..9 Reserved */ 591 uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization Interrupt Disable */ 592 uint32_t :5; /**< bit: 11..15 Reserved */ 593 uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer Done Interrupt Disable */ 594 uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer Done Interrupt Disable */ 595 uint32_t :6; /**< bit: 18..23 Reserved */ 596 uint32_t P_OVR:1; /**< bit: 24 Preview Datapath Overflow Interrupt Disable */ 597 uint32_t C_OVR:1; /**< bit: 25 Codec Datapath Overflow Interrupt Disable */ 598 uint32_t CRC_ERR:1; /**< bit: 26 Embedded Synchronization CRC Error Interrupt Disable */ 599 uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overflow Interrupt Disable */ 600 uint32_t :4; /**< bit: 28..31 Reserved */ 601 } bit; /**< Structure used for bit access */ 602 uint32_t reg; /**< Type used for register access */ 603 } ISI_IDR_Type; 604 #endif 605 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 606 607 #define ISI_IDR_OFFSET (0x30) /**< (ISI_IDR) ISI Interrupt Disable Register Offset */ 608 609 #define ISI_IDR_DIS_DONE_Pos 1 /**< (ISI_IDR) Disable Done Interrupt Disable Position */ 610 #define ISI_IDR_DIS_DONE_Msk (_U_(0x1) << ISI_IDR_DIS_DONE_Pos) /**< (ISI_IDR) Disable Done Interrupt Disable Mask */ 611 #define ISI_IDR_DIS_DONE ISI_IDR_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_DIS_DONE_Msk instead */ 612 #define ISI_IDR_SRST_Pos 2 /**< (ISI_IDR) Software Reset Interrupt Disable Position */ 613 #define ISI_IDR_SRST_Msk (_U_(0x1) << ISI_IDR_SRST_Pos) /**< (ISI_IDR) Software Reset Interrupt Disable Mask */ 614 #define ISI_IDR_SRST ISI_IDR_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_SRST_Msk instead */ 615 #define ISI_IDR_VSYNC_Pos 10 /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Position */ 616 #define ISI_IDR_VSYNC_Msk (_U_(0x1) << ISI_IDR_VSYNC_Pos) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Mask */ 617 #define ISI_IDR_VSYNC ISI_IDR_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_VSYNC_Msk instead */ 618 #define ISI_IDR_PXFR_DONE_Pos 16 /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Position */ 619 #define ISI_IDR_PXFR_DONE_Msk (_U_(0x1) << ISI_IDR_PXFR_DONE_Pos) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Mask */ 620 #define ISI_IDR_PXFR_DONE ISI_IDR_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_PXFR_DONE_Msk instead */ 621 #define ISI_IDR_CXFR_DONE_Pos 17 /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Position */ 622 #define ISI_IDR_CXFR_DONE_Msk (_U_(0x1) << ISI_IDR_CXFR_DONE_Pos) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Mask */ 623 #define ISI_IDR_CXFR_DONE ISI_IDR_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_CXFR_DONE_Msk instead */ 624 #define ISI_IDR_P_OVR_Pos 24 /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Position */ 625 #define ISI_IDR_P_OVR_Msk (_U_(0x1) << ISI_IDR_P_OVR_Pos) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Mask */ 626 #define ISI_IDR_P_OVR ISI_IDR_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_P_OVR_Msk instead */ 627 #define ISI_IDR_C_OVR_Pos 25 /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Position */ 628 #define ISI_IDR_C_OVR_Msk (_U_(0x1) << ISI_IDR_C_OVR_Pos) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Mask */ 629 #define ISI_IDR_C_OVR ISI_IDR_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_C_OVR_Msk instead */ 630 #define ISI_IDR_CRC_ERR_Pos 26 /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Position */ 631 #define ISI_IDR_CRC_ERR_Msk (_U_(0x1) << ISI_IDR_CRC_ERR_Pos) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Mask */ 632 #define ISI_IDR_CRC_ERR ISI_IDR_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_CRC_ERR_Msk instead */ 633 #define ISI_IDR_FR_OVR_Pos 27 /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Position */ 634 #define ISI_IDR_FR_OVR_Msk (_U_(0x1) << ISI_IDR_FR_OVR_Pos) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Mask */ 635 #define ISI_IDR_FR_OVR ISI_IDR_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_FR_OVR_Msk instead */ 636 #define ISI_IDR_MASK _U_(0xF030406) /**< \deprecated (ISI_IDR) Register MASK (Use ISI_IDR_Msk instead) */ 637 #define ISI_IDR_Msk _U_(0xF030406) /**< (ISI_IDR) Register Mask */ 638 639 640 /* -------- ISI_IMR : (ISI Offset: 0x34) (R/ 32) ISI Interrupt Mask Register -------- */ 641 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 642 #if COMPONENT_TYPEDEF_STYLE == 'N' 643 typedef union { 644 struct { 645 uint32_t :1; /**< bit: 0 Reserved */ 646 uint32_t DIS_DONE:1; /**< bit: 1 Module Disable Operation Completed */ 647 uint32_t SRST:1; /**< bit: 2 Software Reset Completed */ 648 uint32_t :7; /**< bit: 3..9 Reserved */ 649 uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization */ 650 uint32_t :5; /**< bit: 11..15 Reserved */ 651 uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer Completed */ 652 uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer Completed */ 653 uint32_t :6; /**< bit: 18..23 Reserved */ 654 uint32_t P_OVR:1; /**< bit: 24 Preview FIFO Overflow */ 655 uint32_t C_OVR:1; /**< bit: 25 Codec FIFO Overflow */ 656 uint32_t CRC_ERR:1; /**< bit: 26 CRC Synchronization Error */ 657 uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overrun */ 658 uint32_t :4; /**< bit: 28..31 Reserved */ 659 } bit; /**< Structure used for bit access */ 660 uint32_t reg; /**< Type used for register access */ 661 } ISI_IMR_Type; 662 #endif 663 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 664 665 #define ISI_IMR_OFFSET (0x34) /**< (ISI_IMR) ISI Interrupt Mask Register Offset */ 666 667 #define ISI_IMR_DIS_DONE_Pos 1 /**< (ISI_IMR) Module Disable Operation Completed Position */ 668 #define ISI_IMR_DIS_DONE_Msk (_U_(0x1) << ISI_IMR_DIS_DONE_Pos) /**< (ISI_IMR) Module Disable Operation Completed Mask */ 669 #define ISI_IMR_DIS_DONE ISI_IMR_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_DIS_DONE_Msk instead */ 670 #define ISI_IMR_SRST_Pos 2 /**< (ISI_IMR) Software Reset Completed Position */ 671 #define ISI_IMR_SRST_Msk (_U_(0x1) << ISI_IMR_SRST_Pos) /**< (ISI_IMR) Software Reset Completed Mask */ 672 #define ISI_IMR_SRST ISI_IMR_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_SRST_Msk instead */ 673 #define ISI_IMR_VSYNC_Pos 10 /**< (ISI_IMR) Vertical Synchronization Position */ 674 #define ISI_IMR_VSYNC_Msk (_U_(0x1) << ISI_IMR_VSYNC_Pos) /**< (ISI_IMR) Vertical Synchronization Mask */ 675 #define ISI_IMR_VSYNC ISI_IMR_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_VSYNC_Msk instead */ 676 #define ISI_IMR_PXFR_DONE_Pos 16 /**< (ISI_IMR) Preview DMA Transfer Completed Position */ 677 #define ISI_IMR_PXFR_DONE_Msk (_U_(0x1) << ISI_IMR_PXFR_DONE_Pos) /**< (ISI_IMR) Preview DMA Transfer Completed Mask */ 678 #define ISI_IMR_PXFR_DONE ISI_IMR_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_PXFR_DONE_Msk instead */ 679 #define ISI_IMR_CXFR_DONE_Pos 17 /**< (ISI_IMR) Codec DMA Transfer Completed Position */ 680 #define ISI_IMR_CXFR_DONE_Msk (_U_(0x1) << ISI_IMR_CXFR_DONE_Pos) /**< (ISI_IMR) Codec DMA Transfer Completed Mask */ 681 #define ISI_IMR_CXFR_DONE ISI_IMR_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_CXFR_DONE_Msk instead */ 682 #define ISI_IMR_P_OVR_Pos 24 /**< (ISI_IMR) Preview FIFO Overflow Position */ 683 #define ISI_IMR_P_OVR_Msk (_U_(0x1) << ISI_IMR_P_OVR_Pos) /**< (ISI_IMR) Preview FIFO Overflow Mask */ 684 #define ISI_IMR_P_OVR ISI_IMR_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_P_OVR_Msk instead */ 685 #define ISI_IMR_C_OVR_Pos 25 /**< (ISI_IMR) Codec FIFO Overflow Position */ 686 #define ISI_IMR_C_OVR_Msk (_U_(0x1) << ISI_IMR_C_OVR_Pos) /**< (ISI_IMR) Codec FIFO Overflow Mask */ 687 #define ISI_IMR_C_OVR ISI_IMR_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_C_OVR_Msk instead */ 688 #define ISI_IMR_CRC_ERR_Pos 26 /**< (ISI_IMR) CRC Synchronization Error Position */ 689 #define ISI_IMR_CRC_ERR_Msk (_U_(0x1) << ISI_IMR_CRC_ERR_Pos) /**< (ISI_IMR) CRC Synchronization Error Mask */ 690 #define ISI_IMR_CRC_ERR ISI_IMR_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_CRC_ERR_Msk instead */ 691 #define ISI_IMR_FR_OVR_Pos 27 /**< (ISI_IMR) Frame Rate Overrun Position */ 692 #define ISI_IMR_FR_OVR_Msk (_U_(0x1) << ISI_IMR_FR_OVR_Pos) /**< (ISI_IMR) Frame Rate Overrun Mask */ 693 #define ISI_IMR_FR_OVR ISI_IMR_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_FR_OVR_Msk instead */ 694 #define ISI_IMR_MASK _U_(0xF030406) /**< \deprecated (ISI_IMR) Register MASK (Use ISI_IMR_Msk instead) */ 695 #define ISI_IMR_Msk _U_(0xF030406) /**< (ISI_IMR) Register Mask */ 696 697 698 /* -------- ISI_DMA_CHER : (ISI Offset: 0x38) (/W 32) DMA Channel Enable Register -------- */ 699 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 700 #if COMPONENT_TYPEDEF_STYLE == 'N' 701 typedef union { 702 struct { 703 uint32_t P_CH_EN:1; /**< bit: 0 Preview Channel Enable */ 704 uint32_t C_CH_EN:1; /**< bit: 1 Codec Channel Enable */ 705 uint32_t :30; /**< bit: 2..31 Reserved */ 706 } bit; /**< Structure used for bit access */ 707 uint32_t reg; /**< Type used for register access */ 708 } ISI_DMA_CHER_Type; 709 #endif 710 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 711 712 #define ISI_DMA_CHER_OFFSET (0x38) /**< (ISI_DMA_CHER) DMA Channel Enable Register Offset */ 713 714 #define ISI_DMA_CHER_P_CH_EN_Pos 0 /**< (ISI_DMA_CHER) Preview Channel Enable Position */ 715 #define ISI_DMA_CHER_P_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_P_CH_EN_Pos) /**< (ISI_DMA_CHER) Preview Channel Enable Mask */ 716 #define ISI_DMA_CHER_P_CH_EN ISI_DMA_CHER_P_CH_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHER_P_CH_EN_Msk instead */ 717 #define ISI_DMA_CHER_C_CH_EN_Pos 1 /**< (ISI_DMA_CHER) Codec Channel Enable Position */ 718 #define ISI_DMA_CHER_C_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_C_CH_EN_Pos) /**< (ISI_DMA_CHER) Codec Channel Enable Mask */ 719 #define ISI_DMA_CHER_C_CH_EN ISI_DMA_CHER_C_CH_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHER_C_CH_EN_Msk instead */ 720 #define ISI_DMA_CHER_MASK _U_(0x03) /**< \deprecated (ISI_DMA_CHER) Register MASK (Use ISI_DMA_CHER_Msk instead) */ 721 #define ISI_DMA_CHER_Msk _U_(0x03) /**< (ISI_DMA_CHER) Register Mask */ 722 723 724 /* -------- ISI_DMA_CHDR : (ISI Offset: 0x3c) (/W 32) DMA Channel Disable Register -------- */ 725 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 726 #if COMPONENT_TYPEDEF_STYLE == 'N' 727 typedef union { 728 struct { 729 uint32_t P_CH_DIS:1; /**< bit: 0 Preview Channel Disable Request */ 730 uint32_t C_CH_DIS:1; /**< bit: 1 Codec Channel Disable Request */ 731 uint32_t :30; /**< bit: 2..31 Reserved */ 732 } bit; /**< Structure used for bit access */ 733 uint32_t reg; /**< Type used for register access */ 734 } ISI_DMA_CHDR_Type; 735 #endif 736 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 737 738 #define ISI_DMA_CHDR_OFFSET (0x3C) /**< (ISI_DMA_CHDR) DMA Channel Disable Register Offset */ 739 740 #define ISI_DMA_CHDR_P_CH_DIS_Pos 0 /**< (ISI_DMA_CHDR) Preview Channel Disable Request Position */ 741 #define ISI_DMA_CHDR_P_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_P_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Mask */ 742 #define ISI_DMA_CHDR_P_CH_DIS ISI_DMA_CHDR_P_CH_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHDR_P_CH_DIS_Msk instead */ 743 #define ISI_DMA_CHDR_C_CH_DIS_Pos 1 /**< (ISI_DMA_CHDR) Codec Channel Disable Request Position */ 744 #define ISI_DMA_CHDR_C_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_C_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Mask */ 745 #define ISI_DMA_CHDR_C_CH_DIS ISI_DMA_CHDR_C_CH_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHDR_C_CH_DIS_Msk instead */ 746 #define ISI_DMA_CHDR_MASK _U_(0x03) /**< \deprecated (ISI_DMA_CHDR) Register MASK (Use ISI_DMA_CHDR_Msk instead) */ 747 #define ISI_DMA_CHDR_Msk _U_(0x03) /**< (ISI_DMA_CHDR) Register Mask */ 748 749 750 /* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) (R/ 32) DMA Channel Status Register -------- */ 751 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 752 #if COMPONENT_TYPEDEF_STYLE == 'N' 753 typedef union { 754 struct { 755 uint32_t P_CH_S:1; /**< bit: 0 Preview DMA Channel Status */ 756 uint32_t C_CH_S:1; /**< bit: 1 Code DMA Channel Status */ 757 uint32_t :30; /**< bit: 2..31 Reserved */ 758 } bit; /**< Structure used for bit access */ 759 uint32_t reg; /**< Type used for register access */ 760 } ISI_DMA_CHSR_Type; 761 #endif 762 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 763 764 #define ISI_DMA_CHSR_OFFSET (0x40) /**< (ISI_DMA_CHSR) DMA Channel Status Register Offset */ 765 766 #define ISI_DMA_CHSR_P_CH_S_Pos 0 /**< (ISI_DMA_CHSR) Preview DMA Channel Status Position */ 767 #define ISI_DMA_CHSR_P_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_P_CH_S_Pos) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Mask */ 768 #define ISI_DMA_CHSR_P_CH_S ISI_DMA_CHSR_P_CH_S_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHSR_P_CH_S_Msk instead */ 769 #define ISI_DMA_CHSR_C_CH_S_Pos 1 /**< (ISI_DMA_CHSR) Code DMA Channel Status Position */ 770 #define ISI_DMA_CHSR_C_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_C_CH_S_Pos) /**< (ISI_DMA_CHSR) Code DMA Channel Status Mask */ 771 #define ISI_DMA_CHSR_C_CH_S ISI_DMA_CHSR_C_CH_S_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHSR_C_CH_S_Msk instead */ 772 #define ISI_DMA_CHSR_MASK _U_(0x03) /**< \deprecated (ISI_DMA_CHSR) Register MASK (Use ISI_DMA_CHSR_Msk instead) */ 773 #define ISI_DMA_CHSR_Msk _U_(0x03) /**< (ISI_DMA_CHSR) Register Mask */ 774 775 776 /* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) (R/W 32) DMA Preview Base Address Register -------- */ 777 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 778 #if COMPONENT_TYPEDEF_STYLE == 'N' 779 typedef union { 780 struct { 781 uint32_t :2; /**< bit: 0..1 Reserved */ 782 uint32_t P_ADDR:30; /**< bit: 2..31 Preview Image Base Address */ 783 } bit; /**< Structure used for bit access */ 784 uint32_t reg; /**< Type used for register access */ 785 } ISI_DMA_P_ADDR_Type; 786 #endif 787 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 788 789 #define ISI_DMA_P_ADDR_OFFSET (0x44) /**< (ISI_DMA_P_ADDR) DMA Preview Base Address Register Offset */ 790 791 #define ISI_DMA_P_ADDR_P_ADDR_Pos 2 /**< (ISI_DMA_P_ADDR) Preview Image Base Address Position */ 792 #define ISI_DMA_P_ADDR_P_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Mask */ 793 #define ISI_DMA_P_ADDR_P_ADDR(value) (ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)) 794 #define ISI_DMA_P_ADDR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_P_ADDR) Register MASK (Use ISI_DMA_P_ADDR_Msk instead) */ 795 #define ISI_DMA_P_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_ADDR) Register Mask */ 796 797 798 /* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) (R/W 32) DMA Preview Control Register -------- */ 799 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 800 #if COMPONENT_TYPEDEF_STYLE == 'N' 801 typedef union { 802 struct { 803 uint32_t P_FETCH:1; /**< bit: 0 Descriptor Fetch Control Bit */ 804 uint32_t P_WB:1; /**< bit: 1 Descriptor Writeback Control Bit */ 805 uint32_t P_IEN:1; /**< bit: 2 Transfer Done Flag Control */ 806 uint32_t P_DONE:1; /**< bit: 3 Preview Transfer Done */ 807 uint32_t :28; /**< bit: 4..31 Reserved */ 808 } bit; /**< Structure used for bit access */ 809 uint32_t reg; /**< Type used for register access */ 810 } ISI_DMA_P_CTRL_Type; 811 #endif 812 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 813 814 #define ISI_DMA_P_CTRL_OFFSET (0x48) /**< (ISI_DMA_P_CTRL) DMA Preview Control Register Offset */ 815 816 #define ISI_DMA_P_CTRL_P_FETCH_Pos 0 /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Position */ 817 #define ISI_DMA_P_CTRL_P_FETCH_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_FETCH_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Mask */ 818 #define ISI_DMA_P_CTRL_P_FETCH ISI_DMA_P_CTRL_P_FETCH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_FETCH_Msk instead */ 819 #define ISI_DMA_P_CTRL_P_WB_Pos 1 /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Position */ 820 #define ISI_DMA_P_CTRL_P_WB_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_WB_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Mask */ 821 #define ISI_DMA_P_CTRL_P_WB ISI_DMA_P_CTRL_P_WB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_WB_Msk instead */ 822 #define ISI_DMA_P_CTRL_P_IEN_Pos 2 /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Position */ 823 #define ISI_DMA_P_CTRL_P_IEN_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_IEN_Pos) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Mask */ 824 #define ISI_DMA_P_CTRL_P_IEN ISI_DMA_P_CTRL_P_IEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_IEN_Msk instead */ 825 #define ISI_DMA_P_CTRL_P_DONE_Pos 3 /**< (ISI_DMA_P_CTRL) Preview Transfer Done Position */ 826 #define ISI_DMA_P_CTRL_P_DONE_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_DONE_Pos) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Mask */ 827 #define ISI_DMA_P_CTRL_P_DONE ISI_DMA_P_CTRL_P_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_DONE_Msk instead */ 828 #define ISI_DMA_P_CTRL_MASK _U_(0x0F) /**< \deprecated (ISI_DMA_P_CTRL) Register MASK (Use ISI_DMA_P_CTRL_Msk instead) */ 829 #define ISI_DMA_P_CTRL_Msk _U_(0x0F) /**< (ISI_DMA_P_CTRL) Register Mask */ 830 831 832 /* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4c) (R/W 32) DMA Preview Descriptor Address Register -------- */ 833 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 834 #if COMPONENT_TYPEDEF_STYLE == 'N' 835 typedef union { 836 struct { 837 uint32_t :2; /**< bit: 0..1 Reserved */ 838 uint32_t P_DSCR:30; /**< bit: 2..31 Preview Descriptor Base Address */ 839 } bit; /**< Structure used for bit access */ 840 uint32_t reg; /**< Type used for register access */ 841 } ISI_DMA_P_DSCR_Type; 842 #endif 843 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 844 845 #define ISI_DMA_P_DSCR_OFFSET (0x4C) /**< (ISI_DMA_P_DSCR) DMA Preview Descriptor Address Register Offset */ 846 847 #define ISI_DMA_P_DSCR_P_DSCR_Pos 2 /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Position */ 848 #define ISI_DMA_P_DSCR_P_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Mask */ 849 #define ISI_DMA_P_DSCR_P_DSCR(value) (ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)) 850 #define ISI_DMA_P_DSCR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_P_DSCR) Register MASK (Use ISI_DMA_P_DSCR_Msk instead) */ 851 #define ISI_DMA_P_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_DSCR) Register Mask */ 852 853 854 /* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) (R/W 32) DMA Codec Base Address Register -------- */ 855 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 856 #if COMPONENT_TYPEDEF_STYLE == 'N' 857 typedef union { 858 struct { 859 uint32_t :2; /**< bit: 0..1 Reserved */ 860 uint32_t C_ADDR:30; /**< bit: 2..31 Codec Image Base Address */ 861 } bit; /**< Structure used for bit access */ 862 uint32_t reg; /**< Type used for register access */ 863 } ISI_DMA_C_ADDR_Type; 864 #endif 865 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 866 867 #define ISI_DMA_C_ADDR_OFFSET (0x50) /**< (ISI_DMA_C_ADDR) DMA Codec Base Address Register Offset */ 868 869 #define ISI_DMA_C_ADDR_C_ADDR_Pos 2 /**< (ISI_DMA_C_ADDR) Codec Image Base Address Position */ 870 #define ISI_DMA_C_ADDR_C_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Mask */ 871 #define ISI_DMA_C_ADDR_C_ADDR(value) (ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)) 872 #define ISI_DMA_C_ADDR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_C_ADDR) Register MASK (Use ISI_DMA_C_ADDR_Msk instead) */ 873 #define ISI_DMA_C_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_ADDR) Register Mask */ 874 875 876 /* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) (R/W 32) DMA Codec Control Register -------- */ 877 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 878 #if COMPONENT_TYPEDEF_STYLE == 'N' 879 typedef union { 880 struct { 881 uint32_t C_FETCH:1; /**< bit: 0 Descriptor Fetch Control Bit */ 882 uint32_t C_WB:1; /**< bit: 1 Descriptor Writeback Control Bit */ 883 uint32_t C_IEN:1; /**< bit: 2 Transfer Done Flag Control */ 884 uint32_t C_DONE:1; /**< bit: 3 Codec Transfer Done */ 885 uint32_t :28; /**< bit: 4..31 Reserved */ 886 } bit; /**< Structure used for bit access */ 887 uint32_t reg; /**< Type used for register access */ 888 } ISI_DMA_C_CTRL_Type; 889 #endif 890 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 891 892 #define ISI_DMA_C_CTRL_OFFSET (0x54) /**< (ISI_DMA_C_CTRL) DMA Codec Control Register Offset */ 893 894 #define ISI_DMA_C_CTRL_C_FETCH_Pos 0 /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Position */ 895 #define ISI_DMA_C_CTRL_C_FETCH_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_FETCH_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Mask */ 896 #define ISI_DMA_C_CTRL_C_FETCH ISI_DMA_C_CTRL_C_FETCH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_FETCH_Msk instead */ 897 #define ISI_DMA_C_CTRL_C_WB_Pos 1 /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Position */ 898 #define ISI_DMA_C_CTRL_C_WB_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_WB_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Mask */ 899 #define ISI_DMA_C_CTRL_C_WB ISI_DMA_C_CTRL_C_WB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_WB_Msk instead */ 900 #define ISI_DMA_C_CTRL_C_IEN_Pos 2 /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Position */ 901 #define ISI_DMA_C_CTRL_C_IEN_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_IEN_Pos) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Mask */ 902 #define ISI_DMA_C_CTRL_C_IEN ISI_DMA_C_CTRL_C_IEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_IEN_Msk instead */ 903 #define ISI_DMA_C_CTRL_C_DONE_Pos 3 /**< (ISI_DMA_C_CTRL) Codec Transfer Done Position */ 904 #define ISI_DMA_C_CTRL_C_DONE_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_DONE_Pos) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Mask */ 905 #define ISI_DMA_C_CTRL_C_DONE ISI_DMA_C_CTRL_C_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_DONE_Msk instead */ 906 #define ISI_DMA_C_CTRL_MASK _U_(0x0F) /**< \deprecated (ISI_DMA_C_CTRL) Register MASK (Use ISI_DMA_C_CTRL_Msk instead) */ 907 #define ISI_DMA_C_CTRL_Msk _U_(0x0F) /**< (ISI_DMA_C_CTRL) Register Mask */ 908 909 910 /* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) (R/W 32) DMA Codec Descriptor Address Register -------- */ 911 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 912 #if COMPONENT_TYPEDEF_STYLE == 'N' 913 typedef union { 914 struct { 915 uint32_t :2; /**< bit: 0..1 Reserved */ 916 uint32_t C_DSCR:30; /**< bit: 2..31 Codec Descriptor Base Address */ 917 } bit; /**< Structure used for bit access */ 918 uint32_t reg; /**< Type used for register access */ 919 } ISI_DMA_C_DSCR_Type; 920 #endif 921 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 922 923 #define ISI_DMA_C_DSCR_OFFSET (0x58) /**< (ISI_DMA_C_DSCR) DMA Codec Descriptor Address Register Offset */ 924 925 #define ISI_DMA_C_DSCR_C_DSCR_Pos 2 /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Position */ 926 #define ISI_DMA_C_DSCR_C_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Mask */ 927 #define ISI_DMA_C_DSCR_C_DSCR(value) (ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)) 928 #define ISI_DMA_C_DSCR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_C_DSCR) Register MASK (Use ISI_DMA_C_DSCR_Msk instead) */ 929 #define ISI_DMA_C_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_DSCR) Register Mask */ 930 931 932 /* -------- ISI_WPMR : (ISI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 933 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 934 #if COMPONENT_TYPEDEF_STYLE == 'N' 935 typedef union { 936 struct { 937 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 938 uint32_t :7; /**< bit: 1..7 Reserved */ 939 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key Password */ 940 } bit; /**< Structure used for bit access */ 941 uint32_t reg; /**< Type used for register access */ 942 } ISI_WPMR_Type; 943 #endif 944 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 945 946 #define ISI_WPMR_OFFSET (0xE4) /**< (ISI_WPMR) Write Protection Mode Register Offset */ 947 948 #define ISI_WPMR_WPEN_Pos 0 /**< (ISI_WPMR) Write Protection Enable Position */ 949 #define ISI_WPMR_WPEN_Msk (_U_(0x1) << ISI_WPMR_WPEN_Pos) /**< (ISI_WPMR) Write Protection Enable Mask */ 950 #define ISI_WPMR_WPEN ISI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_WPMR_WPEN_Msk instead */ 951 #define ISI_WPMR_WPKEY_Pos 8 /**< (ISI_WPMR) Write Protection Key Password Position */ 952 #define ISI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Write Protection Key Password Mask */ 953 #define ISI_WPMR_WPKEY(value) (ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)) 954 #define ISI_WPMR_WPKEY_PASSWD_Val _U_(0x495349) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 955 #define ISI_WPMR_WPKEY_PASSWD (ISI_WPMR_WPKEY_PASSWD_Val << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 956 #define ISI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (ISI_WPMR) Register MASK (Use ISI_WPMR_Msk instead) */ 957 #define ISI_WPMR_Msk _U_(0xFFFFFF01) /**< (ISI_WPMR) Register Mask */ 958 959 960 /* -------- ISI_WPSR : (ISI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 961 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 962 #if COMPONENT_TYPEDEF_STYLE == 'N' 963 typedef union { 964 struct { 965 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 966 uint32_t :7; /**< bit: 1..7 Reserved */ 967 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ 968 uint32_t :8; /**< bit: 24..31 Reserved */ 969 } bit; /**< Structure used for bit access */ 970 uint32_t reg; /**< Type used for register access */ 971 } ISI_WPSR_Type; 972 #endif 973 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 974 975 #define ISI_WPSR_OFFSET (0xE8) /**< (ISI_WPSR) Write Protection Status Register Offset */ 976 977 #define ISI_WPSR_WPVS_Pos 0 /**< (ISI_WPSR) Write Protection Violation Status Position */ 978 #define ISI_WPSR_WPVS_Msk (_U_(0x1) << ISI_WPSR_WPVS_Pos) /**< (ISI_WPSR) Write Protection Violation Status Mask */ 979 #define ISI_WPSR_WPVS ISI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_WPSR_WPVS_Msk instead */ 980 #define ISI_WPSR_WPVSRC_Pos 8 /**< (ISI_WPSR) Write Protection Violation Source Position */ 981 #define ISI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << ISI_WPSR_WPVSRC_Pos) /**< (ISI_WPSR) Write Protection Violation Source Mask */ 982 #define ISI_WPSR_WPVSRC(value) (ISI_WPSR_WPVSRC_Msk & ((value) << ISI_WPSR_WPVSRC_Pos)) 983 #define ISI_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (ISI_WPSR) Register MASK (Use ISI_WPSR_Msk instead) */ 984 #define ISI_WPSR_Msk _U_(0xFFFF01) /**< (ISI_WPSR) Register Mask */ 985 986 987 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 988 #if COMPONENT_TYPEDEF_STYLE == 'R' 989 /** \brief ISI hardware registers */ 990 typedef struct { 991 __IO uint32_t ISI_CFG1; /**< (ISI Offset: 0x00) ISI Configuration 1 Register */ 992 __IO uint32_t ISI_CFG2; /**< (ISI Offset: 0x04) ISI Configuration 2 Register */ 993 __IO uint32_t ISI_PSIZE; /**< (ISI Offset: 0x08) ISI Preview Size Register */ 994 __IO uint32_t ISI_PDECF; /**< (ISI Offset: 0x0C) ISI Preview Decimation Factor Register */ 995 __IO uint32_t ISI_Y2R_SET0; /**< (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ 996 __IO uint32_t ISI_Y2R_SET1; /**< (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ 997 __IO uint32_t ISI_R2Y_SET0; /**< (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ 998 __IO uint32_t ISI_R2Y_SET1; /**< (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ 999 __IO uint32_t ISI_R2Y_SET2; /**< (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ 1000 __O uint32_t ISI_CR; /**< (ISI Offset: 0x24) ISI Control Register */ 1001 __I uint32_t ISI_SR; /**< (ISI Offset: 0x28) ISI Status Register */ 1002 __O uint32_t ISI_IER; /**< (ISI Offset: 0x2C) ISI Interrupt Enable Register */ 1003 __O uint32_t ISI_IDR; /**< (ISI Offset: 0x30) ISI Interrupt Disable Register */ 1004 __I uint32_t ISI_IMR; /**< (ISI Offset: 0x34) ISI Interrupt Mask Register */ 1005 __O uint32_t ISI_DMA_CHER; /**< (ISI Offset: 0x38) DMA Channel Enable Register */ 1006 __O uint32_t ISI_DMA_CHDR; /**< (ISI Offset: 0x3C) DMA Channel Disable Register */ 1007 __I uint32_t ISI_DMA_CHSR; /**< (ISI Offset: 0x40) DMA Channel Status Register */ 1008 __IO uint32_t ISI_DMA_P_ADDR; /**< (ISI Offset: 0x44) DMA Preview Base Address Register */ 1009 __IO uint32_t ISI_DMA_P_CTRL; /**< (ISI Offset: 0x48) DMA Preview Control Register */ 1010 __IO uint32_t ISI_DMA_P_DSCR; /**< (ISI Offset: 0x4C) DMA Preview Descriptor Address Register */ 1011 __IO uint32_t ISI_DMA_C_ADDR; /**< (ISI Offset: 0x50) DMA Codec Base Address Register */ 1012 __IO uint32_t ISI_DMA_C_CTRL; /**< (ISI Offset: 0x54) DMA Codec Control Register */ 1013 __IO uint32_t ISI_DMA_C_DSCR; /**< (ISI Offset: 0x58) DMA Codec Descriptor Address Register */ 1014 __I uint8_t Reserved1[136]; 1015 __IO uint32_t ISI_WPMR; /**< (ISI Offset: 0xE4) Write Protection Mode Register */ 1016 __I uint32_t ISI_WPSR; /**< (ISI Offset: 0xE8) Write Protection Status Register */ 1017 } Isi; 1018 1019 #elif COMPONENT_TYPEDEF_STYLE == 'N' 1020 /** \brief ISI hardware registers */ 1021 typedef struct { 1022 __IO ISI_CFG1_Type ISI_CFG1; /**< Offset: 0x00 (R/W 32) ISI Configuration 1 Register */ 1023 __IO ISI_CFG2_Type ISI_CFG2; /**< Offset: 0x04 (R/W 32) ISI Configuration 2 Register */ 1024 __IO ISI_PSIZE_Type ISI_PSIZE; /**< Offset: 0x08 (R/W 32) ISI Preview Size Register */ 1025 __IO ISI_PDECF_Type ISI_PDECF; /**< Offset: 0x0C (R/W 32) ISI Preview Decimation Factor Register */ 1026 __IO ISI_Y2R_SET0_Type ISI_Y2R_SET0; /**< Offset: 0x10 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ 1027 __IO ISI_Y2R_SET1_Type ISI_Y2R_SET1; /**< Offset: 0x14 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ 1028 __IO ISI_R2Y_SET0_Type ISI_R2Y_SET0; /**< Offset: 0x18 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ 1029 __IO ISI_R2Y_SET1_Type ISI_R2Y_SET1; /**< Offset: 0x1C (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ 1030 __IO ISI_R2Y_SET2_Type ISI_R2Y_SET2; /**< Offset: 0x20 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ 1031 __O ISI_CR_Type ISI_CR; /**< Offset: 0x24 ( /W 32) ISI Control Register */ 1032 __I ISI_SR_Type ISI_SR; /**< Offset: 0x28 (R/ 32) ISI Status Register */ 1033 __O ISI_IER_Type ISI_IER; /**< Offset: 0x2C ( /W 32) ISI Interrupt Enable Register */ 1034 __O ISI_IDR_Type ISI_IDR; /**< Offset: 0x30 ( /W 32) ISI Interrupt Disable Register */ 1035 __I ISI_IMR_Type ISI_IMR; /**< Offset: 0x34 (R/ 32) ISI Interrupt Mask Register */ 1036 __O ISI_DMA_CHER_Type ISI_DMA_CHER; /**< Offset: 0x38 ( /W 32) DMA Channel Enable Register */ 1037 __O ISI_DMA_CHDR_Type ISI_DMA_CHDR; /**< Offset: 0x3C ( /W 32) DMA Channel Disable Register */ 1038 __I ISI_DMA_CHSR_Type ISI_DMA_CHSR; /**< Offset: 0x40 (R/ 32) DMA Channel Status Register */ 1039 __IO ISI_DMA_P_ADDR_Type ISI_DMA_P_ADDR; /**< Offset: 0x44 (R/W 32) DMA Preview Base Address Register */ 1040 __IO ISI_DMA_P_CTRL_Type ISI_DMA_P_CTRL; /**< Offset: 0x48 (R/W 32) DMA Preview Control Register */ 1041 __IO ISI_DMA_P_DSCR_Type ISI_DMA_P_DSCR; /**< Offset: 0x4C (R/W 32) DMA Preview Descriptor Address Register */ 1042 __IO ISI_DMA_C_ADDR_Type ISI_DMA_C_ADDR; /**< Offset: 0x50 (R/W 32) DMA Codec Base Address Register */ 1043 __IO ISI_DMA_C_CTRL_Type ISI_DMA_C_CTRL; /**< Offset: 0x54 (R/W 32) DMA Codec Control Register */ 1044 __IO ISI_DMA_C_DSCR_Type ISI_DMA_C_DSCR; /**< Offset: 0x58 (R/W 32) DMA Codec Descriptor Address Register */ 1045 __I uint8_t Reserved1[136]; 1046 __IO ISI_WPMR_Type ISI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 1047 __I ISI_WPSR_Type ISI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 1048 } Isi; 1049 1050 #else /* COMPONENT_TYPEDEF_STYLE */ 1051 #error Unknown component typedef style 1052 #endif /* COMPONENT_TYPEDEF_STYLE */ 1053 1054 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1055 /** @} end of Image Sensor Interface */ 1056 1057 #endif /* _SAME70_ISI_COMPONENT_H_ */ 1058
