1 /** 2 * \file 3 * 4 * \brief Component description for DACC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_DACC_COMPONENT_H_ 32 #define _SAME70_DACC_COMPONENT_H_ 33 #define _SAME70_DACC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Digital-to-Analog Converter Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR DACC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define DACC_11246 /**< (DACC) Module ID */ 46 #define REV_DACC D /**< (DACC) Module revision */ 47 48 /* -------- DACC_CR : (DACC Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t SWRST:1; /**< bit: 0 Software Reset */ 54 uint32_t :31; /**< bit: 1..31 Reserved */ 55 } bit; /**< Structure used for bit access */ 56 uint32_t reg; /**< Type used for register access */ 57 } DACC_CR_Type; 58 #endif 59 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 #define DACC_CR_OFFSET (0x00) /**< (DACC_CR) Control Register Offset */ 62 63 #define DACC_CR_SWRST_Pos 0 /**< (DACC_CR) Software Reset Position */ 64 #define DACC_CR_SWRST_Msk (_U_(0x1) << DACC_CR_SWRST_Pos) /**< (DACC_CR) Software Reset Mask */ 65 #define DACC_CR_SWRST DACC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CR_SWRST_Msk instead */ 66 #define DACC_CR_MASK _U_(0x01) /**< \deprecated (DACC_CR) Register MASK (Use DACC_CR_Msk instead) */ 67 #define DACC_CR_Msk _U_(0x01) /**< (DACC_CR) Register Mask */ 68 69 70 /* -------- DACC_MR : (DACC Offset: 0x04) (R/W 32) Mode Register -------- */ 71 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 72 #if COMPONENT_TYPEDEF_STYLE == 'N' 73 typedef union { 74 struct { 75 uint32_t MAXS0:1; /**< bit: 0 Max Speed Mode for Channel 0 */ 76 uint32_t MAXS1:1; /**< bit: 1 Max Speed Mode for Channel 1 */ 77 uint32_t :2; /**< bit: 2..3 Reserved */ 78 uint32_t WORD:1; /**< bit: 4 Word Transfer Mode */ 79 uint32_t ZERO:1; /**< bit: 5 Must always be written to 0. */ 80 uint32_t :17; /**< bit: 6..22 Reserved */ 81 uint32_t DIFF:1; /**< bit: 23 Differential Mode */ 82 uint32_t PRESCALER:4; /**< bit: 24..27 Peripheral Clock to DAC Clock Ratio */ 83 uint32_t :4; /**< bit: 28..31 Reserved */ 84 } bit; /**< Structure used for bit access */ 85 struct { 86 uint32_t MAXS:2; /**< bit: 0..1 Max Speed Mode for Channel x */ 87 uint32_t :30; /**< bit: 2..31 Reserved */ 88 } vec; /**< Structure used for vec access */ 89 uint32_t reg; /**< Type used for register access */ 90 } DACC_MR_Type; 91 #endif 92 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 #define DACC_MR_OFFSET (0x04) /**< (DACC_MR) Mode Register Offset */ 95 96 #define DACC_MR_MAXS0_Pos 0 /**< (DACC_MR) Max Speed Mode for Channel 0 Position */ 97 #define DACC_MR_MAXS0_Msk (_U_(0x1) << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max Speed Mode for Channel 0 Mask */ 98 #define DACC_MR_MAXS0 DACC_MR_MAXS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_MAXS0_Msk instead */ 99 #define DACC_MR_MAXS0_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ 100 #define DACC_MR_MAXS0_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ 101 #define DACC_MR_MAXS0_TRIG_EVENT (DACC_MR_MAXS0_TRIG_EVENT_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ 102 #define DACC_MR_MAXS0_MAXIMUM (DACC_MR_MAXS0_MAXIMUM_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ 103 #define DACC_MR_MAXS1_Pos 1 /**< (DACC_MR) Max Speed Mode for Channel 1 Position */ 104 #define DACC_MR_MAXS1_Msk (_U_(0x1) << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max Speed Mode for Channel 1 Mask */ 105 #define DACC_MR_MAXS1 DACC_MR_MAXS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_MAXS1_Msk instead */ 106 #define DACC_MR_MAXS1_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ 107 #define DACC_MR_MAXS1_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ 108 #define DACC_MR_MAXS1_TRIG_EVENT (DACC_MR_MAXS1_TRIG_EVENT_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ 109 #define DACC_MR_MAXS1_MAXIMUM (DACC_MR_MAXS1_MAXIMUM_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ 110 #define DACC_MR_WORD_Pos 4 /**< (DACC_MR) Word Transfer Mode Position */ 111 #define DACC_MR_WORD_Msk (_U_(0x1) << DACC_MR_WORD_Pos) /**< (DACC_MR) Word Transfer Mode Mask */ 112 #define DACC_MR_WORD DACC_MR_WORD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_WORD_Msk instead */ 113 #define DACC_MR_WORD_DISABLED_Val _U_(0x0) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ 114 #define DACC_MR_WORD_ENABLED_Val _U_(0x1) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ 115 #define DACC_MR_WORD_DISABLED (DACC_MR_WORD_DISABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. Position */ 116 #define DACC_MR_WORD_ENABLED (DACC_MR_WORD_ENABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). Position */ 117 #define DACC_MR_ZERO_Pos 5 /**< (DACC_MR) Must always be written to 0. Position */ 118 #define DACC_MR_ZERO_Msk (_U_(0x1) << DACC_MR_ZERO_Pos) /**< (DACC_MR) Must always be written to 0. Mask */ 119 #define DACC_MR_ZERO DACC_MR_ZERO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_ZERO_Msk instead */ 120 #define DACC_MR_DIFF_Pos 23 /**< (DACC_MR) Differential Mode Position */ 121 #define DACC_MR_DIFF_Msk (_U_(0x1) << DACC_MR_DIFF_Pos) /**< (DACC_MR) Differential Mode Mask */ 122 #define DACC_MR_DIFF DACC_MR_DIFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_DIFF_Msk instead */ 123 #define DACC_MR_DIFF_DISABLED_Val _U_(0x0) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ 124 #define DACC_MR_DIFF_ENABLED_Val _U_(0x1) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ 125 #define DACC_MR_DIFF_DISABLED (DACC_MR_DIFF_DISABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. Position */ 126 #define DACC_MR_DIFF_ENABLED (DACC_MR_DIFF_ENABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. Position */ 127 #define DACC_MR_PRESCALER_Pos 24 /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Position */ 128 #define DACC_MR_PRESCALER_Msk (_U_(0xF) << DACC_MR_PRESCALER_Pos) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Mask */ 129 #define DACC_MR_PRESCALER(value) (DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)) 130 #define DACC_MR_MASK _U_(0xF800033) /**< \deprecated (DACC_MR) Register MASK (Use DACC_MR_Msk instead) */ 131 #define DACC_MR_Msk _U_(0xF800033) /**< (DACC_MR) Register Mask */ 132 133 #define DACC_MR_MAXS_Pos 0 /**< (DACC_MR Position) Max Speed Mode for Channel x */ 134 #define DACC_MR_MAXS_Msk (_U_(0x3) << DACC_MR_MAXS_Pos) /**< (DACC_MR Mask) MAXS */ 135 #define DACC_MR_MAXS(value) (DACC_MR_MAXS_Msk & ((value) << DACC_MR_MAXS_Pos)) 136 137 /* -------- DACC_TRIGR : (DACC Offset: 0x08) (R/W 32) Trigger Register -------- */ 138 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 139 #if COMPONENT_TYPEDEF_STYLE == 'N' 140 typedef union { 141 struct { 142 uint32_t TRGEN0:1; /**< bit: 0 Trigger Enable of Channel 0 */ 143 uint32_t TRGEN1:1; /**< bit: 1 Trigger Enable of Channel 1 */ 144 uint32_t :2; /**< bit: 2..3 Reserved */ 145 uint32_t TRGSEL0:3; /**< bit: 4..6 Trigger Selection of Channel 0 */ 146 uint32_t :1; /**< bit: 7 Reserved */ 147 uint32_t TRGSEL1:3; /**< bit: 8..10 Trigger Selection of Channel 1 */ 148 uint32_t :5; /**< bit: 11..15 Reserved */ 149 uint32_t OSR0:3; /**< bit: 16..18 Over Sampling Ratio of Channel 0 */ 150 uint32_t :1; /**< bit: 19 Reserved */ 151 uint32_t OSR1:3; /**< bit: 20..22 Over Sampling Ratio of Channel 1 */ 152 uint32_t :9; /**< bit: 23..31 Reserved */ 153 } bit; /**< Structure used for bit access */ 154 struct { 155 uint32_t TRGEN:2; /**< bit: 0..1 Trigger Enable of Channel x */ 156 uint32_t :30; /**< bit: 2..31 Reserved */ 157 } vec; /**< Structure used for vec access */ 158 uint32_t reg; /**< Type used for register access */ 159 } DACC_TRIGR_Type; 160 #endif 161 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 #define DACC_TRIGR_OFFSET (0x08) /**< (DACC_TRIGR) Trigger Register Offset */ 164 165 #define DACC_TRIGR_TRGEN0_Pos 0 /**< (DACC_TRIGR) Trigger Enable of Channel 0 Position */ 166 #define DACC_TRIGR_TRGEN0_Msk (_U_(0x1) << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Mask */ 167 #define DACC_TRIGR_TRGEN0 DACC_TRIGR_TRGEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_TRIGR_TRGEN0_Msk instead */ 168 #define DACC_TRIGR_TRGEN0_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ 169 #define DACC_TRIGR_TRGEN0_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ 170 #define DACC_TRIGR_TRGEN0_DIS (DACC_TRIGR_TRGEN0_DIS_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ 171 #define DACC_TRIGR_TRGEN0_EN (DACC_TRIGR_TRGEN0_EN_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ 172 #define DACC_TRIGR_TRGEN1_Pos 1 /**< (DACC_TRIGR) Trigger Enable of Channel 1 Position */ 173 #define DACC_TRIGR_TRGEN1_Msk (_U_(0x1) << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Mask */ 174 #define DACC_TRIGR_TRGEN1 DACC_TRIGR_TRGEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_TRIGR_TRGEN1_Msk instead */ 175 #define DACC_TRIGR_TRGEN1_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ 176 #define DACC_TRIGR_TRGEN1_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ 177 #define DACC_TRIGR_TRGEN1_DIS (DACC_TRIGR_TRGEN1_DIS_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ 178 #define DACC_TRIGR_TRGEN1_EN (DACC_TRIGR_TRGEN1_EN_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ 179 #define DACC_TRIGR_TRGSEL0_Pos 4 /**< (DACC_TRIGR) Trigger Selection of Channel 0 Position */ 180 #define DACC_TRIGR_TRGSEL0_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Mask */ 181 #define DACC_TRIGR_TRGSEL0(value) (DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)) 182 #define DACC_TRIGR_TRGSEL0_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */ 183 #define DACC_TRIGR_TRGSEL0_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */ 184 #define DACC_TRIGR_TRGSEL0_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */ 185 #define DACC_TRIGR_TRGSEL0_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */ 186 #define DACC_TRIGR_TRGSEL0_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */ 187 #define DACC_TRIGR_TRGSEL0_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */ 188 #define DACC_TRIGR_TRGSEL0_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */ 189 #define DACC_TRIGR_TRGSEL0_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */ 190 #define DACC_TRIGR_TRGSEL0_TRGSEL0 (DACC_TRIGR_TRGSEL0_TRGSEL0_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) DATRG Position */ 191 #define DACC_TRIGR_TRGSEL0_TRGSEL1 (DACC_TRIGR_TRGSEL0_TRGSEL1_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 output Position */ 192 #define DACC_TRIGR_TRGSEL0_TRGSEL2 (DACC_TRIGR_TRGSEL0_TRGSEL2_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC1 output Position */ 193 #define DACC_TRIGR_TRGSEL0_TRGSEL3 (DACC_TRIGR_TRGSEL0_TRGSEL3_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC2 output Position */ 194 #define DACC_TRIGR_TRGSEL0_TRGSEL4 (DACC_TRIGR_TRGSEL0_TRGSEL4_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */ 195 #define DACC_TRIGR_TRGSEL0_TRGSEL5 (DACC_TRIGR_TRGSEL0_TRGSEL5_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */ 196 #define DACC_TRIGR_TRGSEL0_TRGSEL6 (DACC_TRIGR_TRGSEL0_TRGSEL6_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */ 197 #define DACC_TRIGR_TRGSEL0_TRGSEL7 (DACC_TRIGR_TRGSEL0_TRGSEL7_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */ 198 #define DACC_TRIGR_TRGSEL1_Pos 8 /**< (DACC_TRIGR) Trigger Selection of Channel 1 Position */ 199 #define DACC_TRIGR_TRGSEL1_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Mask */ 200 #define DACC_TRIGR_TRGSEL1(value) (DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)) 201 #define DACC_TRIGR_TRGSEL1_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */ 202 #define DACC_TRIGR_TRGSEL1_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */ 203 #define DACC_TRIGR_TRGSEL1_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */ 204 #define DACC_TRIGR_TRGSEL1_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */ 205 #define DACC_TRIGR_TRGSEL1_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */ 206 #define DACC_TRIGR_TRGSEL1_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */ 207 #define DACC_TRIGR_TRGSEL1_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */ 208 #define DACC_TRIGR_TRGSEL1_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */ 209 #define DACC_TRIGR_TRGSEL1_TRGSEL0 (DACC_TRIGR_TRGSEL1_TRGSEL0_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) DATRG Position */ 210 #define DACC_TRIGR_TRGSEL1_TRGSEL1 (DACC_TRIGR_TRGSEL1_TRGSEL1_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 output Position */ 211 #define DACC_TRIGR_TRGSEL1_TRGSEL2 (DACC_TRIGR_TRGSEL1_TRGSEL2_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC1 output Position */ 212 #define DACC_TRIGR_TRGSEL1_TRGSEL3 (DACC_TRIGR_TRGSEL1_TRGSEL3_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC2 output Position */ 213 #define DACC_TRIGR_TRGSEL1_TRGSEL4 (DACC_TRIGR_TRGSEL1_TRGSEL4_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */ 214 #define DACC_TRIGR_TRGSEL1_TRGSEL5 (DACC_TRIGR_TRGSEL1_TRGSEL5_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */ 215 #define DACC_TRIGR_TRGSEL1_TRGSEL6 (DACC_TRIGR_TRGSEL1_TRGSEL6_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */ 216 #define DACC_TRIGR_TRGSEL1_TRGSEL7 (DACC_TRIGR_TRGSEL1_TRGSEL7_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */ 217 #define DACC_TRIGR_OSR0_Pos 16 /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Position */ 218 #define DACC_TRIGR_OSR0_Msk (_U_(0x7) << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Mask */ 219 #define DACC_TRIGR_OSR0(value) (DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)) 220 #define DACC_TRIGR_OSR0_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ 221 #define DACC_TRIGR_OSR0_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ 222 #define DACC_TRIGR_OSR0_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ 223 #define DACC_TRIGR_OSR0_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ 224 #define DACC_TRIGR_OSR0_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ 225 #define DACC_TRIGR_OSR0_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ 226 #define DACC_TRIGR_OSR0_OSR_1 (DACC_TRIGR_OSR0_OSR_1_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ 227 #define DACC_TRIGR_OSR0_OSR_2 (DACC_TRIGR_OSR0_OSR_2_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ 228 #define DACC_TRIGR_OSR0_OSR_4 (DACC_TRIGR_OSR0_OSR_4_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ 229 #define DACC_TRIGR_OSR0_OSR_8 (DACC_TRIGR_OSR0_OSR_8_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ 230 #define DACC_TRIGR_OSR0_OSR_16 (DACC_TRIGR_OSR0_OSR_16_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ 231 #define DACC_TRIGR_OSR0_OSR_32 (DACC_TRIGR_OSR0_OSR_32_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ 232 #define DACC_TRIGR_OSR1_Pos 20 /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Position */ 233 #define DACC_TRIGR_OSR1_Msk (_U_(0x7) << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Mask */ 234 #define DACC_TRIGR_OSR1(value) (DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)) 235 #define DACC_TRIGR_OSR1_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ 236 #define DACC_TRIGR_OSR1_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ 237 #define DACC_TRIGR_OSR1_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ 238 #define DACC_TRIGR_OSR1_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ 239 #define DACC_TRIGR_OSR1_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ 240 #define DACC_TRIGR_OSR1_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ 241 #define DACC_TRIGR_OSR1_OSR_1 (DACC_TRIGR_OSR1_OSR_1_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ 242 #define DACC_TRIGR_OSR1_OSR_2 (DACC_TRIGR_OSR1_OSR_2_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ 243 #define DACC_TRIGR_OSR1_OSR_4 (DACC_TRIGR_OSR1_OSR_4_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ 244 #define DACC_TRIGR_OSR1_OSR_8 (DACC_TRIGR_OSR1_OSR_8_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ 245 #define DACC_TRIGR_OSR1_OSR_16 (DACC_TRIGR_OSR1_OSR_16_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ 246 #define DACC_TRIGR_OSR1_OSR_32 (DACC_TRIGR_OSR1_OSR_32_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ 247 #define DACC_TRIGR_MASK _U_(0x770773) /**< \deprecated (DACC_TRIGR) Register MASK (Use DACC_TRIGR_Msk instead) */ 248 #define DACC_TRIGR_Msk _U_(0x770773) /**< (DACC_TRIGR) Register Mask */ 249 250 #define DACC_TRIGR_TRGEN_Pos 0 /**< (DACC_TRIGR Position) Trigger Enable of Channel x */ 251 #define DACC_TRIGR_TRGEN_Msk (_U_(0x3) << DACC_TRIGR_TRGEN_Pos) /**< (DACC_TRIGR Mask) TRGEN */ 252 #define DACC_TRIGR_TRGEN(value) (DACC_TRIGR_TRGEN_Msk & ((value) << DACC_TRIGR_TRGEN_Pos)) 253 254 /* -------- DACC_CHER : (DACC Offset: 0x10) (/W 32) Channel Enable Register -------- */ 255 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 256 #if COMPONENT_TYPEDEF_STYLE == 'N' 257 typedef union { 258 struct { 259 uint32_t CH0:1; /**< bit: 0 Channel 0 Enable */ 260 uint32_t CH1:1; /**< bit: 1 Channel 1 Enable */ 261 uint32_t :30; /**< bit: 2..31 Reserved */ 262 } bit; /**< Structure used for bit access */ 263 struct { 264 uint32_t CH:2; /**< bit: 0..1 Channel x Enable */ 265 uint32_t :30; /**< bit: 2..31 Reserved */ 266 } vec; /**< Structure used for vec access */ 267 uint32_t reg; /**< Type used for register access */ 268 } DACC_CHER_Type; 269 #endif 270 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 #define DACC_CHER_OFFSET (0x10) /**< (DACC_CHER) Channel Enable Register Offset */ 273 274 #define DACC_CHER_CH0_Pos 0 /**< (DACC_CHER) Channel 0 Enable Position */ 275 #define DACC_CHER_CH0_Msk (_U_(0x1) << DACC_CHER_CH0_Pos) /**< (DACC_CHER) Channel 0 Enable Mask */ 276 #define DACC_CHER_CH0 DACC_CHER_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHER_CH0_Msk instead */ 277 #define DACC_CHER_CH1_Pos 1 /**< (DACC_CHER) Channel 1 Enable Position */ 278 #define DACC_CHER_CH1_Msk (_U_(0x1) << DACC_CHER_CH1_Pos) /**< (DACC_CHER) Channel 1 Enable Mask */ 279 #define DACC_CHER_CH1 DACC_CHER_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHER_CH1_Msk instead */ 280 #define DACC_CHER_MASK _U_(0x03) /**< \deprecated (DACC_CHER) Register MASK (Use DACC_CHER_Msk instead) */ 281 #define DACC_CHER_Msk _U_(0x03) /**< (DACC_CHER) Register Mask */ 282 283 #define DACC_CHER_CH_Pos 0 /**< (DACC_CHER Position) Channel x Enable */ 284 #define DACC_CHER_CH_Msk (_U_(0x3) << DACC_CHER_CH_Pos) /**< (DACC_CHER Mask) CH */ 285 #define DACC_CHER_CH(value) (DACC_CHER_CH_Msk & ((value) << DACC_CHER_CH_Pos)) 286 287 /* -------- DACC_CHDR : (DACC Offset: 0x14) (/W 32) Channel Disable Register -------- */ 288 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 289 #if COMPONENT_TYPEDEF_STYLE == 'N' 290 typedef union { 291 struct { 292 uint32_t CH0:1; /**< bit: 0 Channel 0 Disable */ 293 uint32_t CH1:1; /**< bit: 1 Channel 1 Disable */ 294 uint32_t :30; /**< bit: 2..31 Reserved */ 295 } bit; /**< Structure used for bit access */ 296 struct { 297 uint32_t CH:2; /**< bit: 0..1 Channel x Disable */ 298 uint32_t :30; /**< bit: 2..31 Reserved */ 299 } vec; /**< Structure used for vec access */ 300 uint32_t reg; /**< Type used for register access */ 301 } DACC_CHDR_Type; 302 #endif 303 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 304 305 #define DACC_CHDR_OFFSET (0x14) /**< (DACC_CHDR) Channel Disable Register Offset */ 306 307 #define DACC_CHDR_CH0_Pos 0 /**< (DACC_CHDR) Channel 0 Disable Position */ 308 #define DACC_CHDR_CH0_Msk (_U_(0x1) << DACC_CHDR_CH0_Pos) /**< (DACC_CHDR) Channel 0 Disable Mask */ 309 #define DACC_CHDR_CH0 DACC_CHDR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHDR_CH0_Msk instead */ 310 #define DACC_CHDR_CH1_Pos 1 /**< (DACC_CHDR) Channel 1 Disable Position */ 311 #define DACC_CHDR_CH1_Msk (_U_(0x1) << DACC_CHDR_CH1_Pos) /**< (DACC_CHDR) Channel 1 Disable Mask */ 312 #define DACC_CHDR_CH1 DACC_CHDR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHDR_CH1_Msk instead */ 313 #define DACC_CHDR_MASK _U_(0x03) /**< \deprecated (DACC_CHDR) Register MASK (Use DACC_CHDR_Msk instead) */ 314 #define DACC_CHDR_Msk _U_(0x03) /**< (DACC_CHDR) Register Mask */ 315 316 #define DACC_CHDR_CH_Pos 0 /**< (DACC_CHDR Position) Channel x Disable */ 317 #define DACC_CHDR_CH_Msk (_U_(0x3) << DACC_CHDR_CH_Pos) /**< (DACC_CHDR Mask) CH */ 318 #define DACC_CHDR_CH(value) (DACC_CHDR_CH_Msk & ((value) << DACC_CHDR_CH_Pos)) 319 320 /* -------- DACC_CHSR : (DACC Offset: 0x18) (R/ 32) Channel Status Register -------- */ 321 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 322 #if COMPONENT_TYPEDEF_STYLE == 'N' 323 typedef union { 324 struct { 325 uint32_t CH0:1; /**< bit: 0 Channel 0 Status */ 326 uint32_t CH1:1; /**< bit: 1 Channel 1 Status */ 327 uint32_t :6; /**< bit: 2..7 Reserved */ 328 uint32_t DACRDY0:1; /**< bit: 8 DAC Ready Flag */ 329 uint32_t DACRDY1:1; /**< bit: 9 DAC Ready Flag */ 330 uint32_t :22; /**< bit: 10..31 Reserved */ 331 } bit; /**< Structure used for bit access */ 332 struct { 333 uint32_t CH:2; /**< bit: 0..1 Channel x Status */ 334 uint32_t :6; /**< bit: 2..7 Reserved */ 335 uint32_t DACRDY:2; /**< bit: 8..9 DAC Ready Flag */ 336 uint32_t :22; /**< bit: 10..31 Reserved */ 337 } vec; /**< Structure used for vec access */ 338 uint32_t reg; /**< Type used for register access */ 339 } DACC_CHSR_Type; 340 #endif 341 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 342 343 #define DACC_CHSR_OFFSET (0x18) /**< (DACC_CHSR) Channel Status Register Offset */ 344 345 #define DACC_CHSR_CH0_Pos 0 /**< (DACC_CHSR) Channel 0 Status Position */ 346 #define DACC_CHSR_CH0_Msk (_U_(0x1) << DACC_CHSR_CH0_Pos) /**< (DACC_CHSR) Channel 0 Status Mask */ 347 #define DACC_CHSR_CH0 DACC_CHSR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_CH0_Msk instead */ 348 #define DACC_CHSR_CH1_Pos 1 /**< (DACC_CHSR) Channel 1 Status Position */ 349 #define DACC_CHSR_CH1_Msk (_U_(0x1) << DACC_CHSR_CH1_Pos) /**< (DACC_CHSR) Channel 1 Status Mask */ 350 #define DACC_CHSR_CH1 DACC_CHSR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_CH1_Msk instead */ 351 #define DACC_CHSR_DACRDY0_Pos 8 /**< (DACC_CHSR) DAC Ready Flag Position */ 352 #define DACC_CHSR_DACRDY0_Msk (_U_(0x1) << DACC_CHSR_DACRDY0_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ 353 #define DACC_CHSR_DACRDY0 DACC_CHSR_DACRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_DACRDY0_Msk instead */ 354 #define DACC_CHSR_DACRDY1_Pos 9 /**< (DACC_CHSR) DAC Ready Flag Position */ 355 #define DACC_CHSR_DACRDY1_Msk (_U_(0x1) << DACC_CHSR_DACRDY1_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ 356 #define DACC_CHSR_DACRDY1 DACC_CHSR_DACRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_DACRDY1_Msk instead */ 357 #define DACC_CHSR_MASK _U_(0x303) /**< \deprecated (DACC_CHSR) Register MASK (Use DACC_CHSR_Msk instead) */ 358 #define DACC_CHSR_Msk _U_(0x303) /**< (DACC_CHSR) Register Mask */ 359 360 #define DACC_CHSR_CH_Pos 0 /**< (DACC_CHSR Position) Channel x Status */ 361 #define DACC_CHSR_CH_Msk (_U_(0x3) << DACC_CHSR_CH_Pos) /**< (DACC_CHSR Mask) CH */ 362 #define DACC_CHSR_CH(value) (DACC_CHSR_CH_Msk & ((value) << DACC_CHSR_CH_Pos)) 363 #define DACC_CHSR_DACRDY_Pos 8 /**< (DACC_CHSR Position) DAC Ready Flag */ 364 #define DACC_CHSR_DACRDY_Msk (_U_(0x3) << DACC_CHSR_DACRDY_Pos) /**< (DACC_CHSR Mask) DACRDY */ 365 #define DACC_CHSR_DACRDY(value) (DACC_CHSR_DACRDY_Msk & ((value) << DACC_CHSR_DACRDY_Pos)) 366 367 /* -------- DACC_CDR : (DACC Offset: 0x1c) (/W 32) Conversion Data Register 0 -------- */ 368 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 369 #if COMPONENT_TYPEDEF_STYLE == 'N' 370 typedef union { 371 struct { 372 uint32_t DATA0:16; /**< bit: 0..15 Data to Convert for channel 0 */ 373 uint32_t DATA1:16; /**< bit: 16..31 Data to Convert for channel 1 */ 374 } bit; /**< Structure used for bit access */ 375 uint32_t reg; /**< Type used for register access */ 376 } DACC_CDR_Type; 377 #endif 378 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 379 380 #define DACC_CDR_OFFSET (0x1C) /**< (DACC_CDR) Conversion Data Register 0 Offset */ 381 382 #define DACC_CDR_DATA0_Pos 0 /**< (DACC_CDR) Data to Convert for channel 0 Position */ 383 #define DACC_CDR_DATA0_Msk (_U_(0xFFFF) << DACC_CDR_DATA0_Pos) /**< (DACC_CDR) Data to Convert for channel 0 Mask */ 384 #define DACC_CDR_DATA0(value) (DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)) 385 #define DACC_CDR_DATA1_Pos 16 /**< (DACC_CDR) Data to Convert for channel 1 Position */ 386 #define DACC_CDR_DATA1_Msk (_U_(0xFFFF) << DACC_CDR_DATA1_Pos) /**< (DACC_CDR) Data to Convert for channel 1 Mask */ 387 #define DACC_CDR_DATA1(value) (DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)) 388 #define DACC_CDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (DACC_CDR) Register MASK (Use DACC_CDR_Msk instead) */ 389 #define DACC_CDR_Msk _U_(0xFFFFFFFF) /**< (DACC_CDR) Register Mask */ 390 391 392 /* -------- DACC_IER : (DACC Offset: 0x24) (/W 32) Interrupt Enable Register -------- */ 393 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 394 #if COMPONENT_TYPEDEF_STYLE == 'N' 395 typedef union { 396 struct { 397 uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Enable of channel 0 */ 398 uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Enable of channel 1 */ 399 uint32_t :2; /**< bit: 2..3 Reserved */ 400 uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Enable of channel 0 */ 401 uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Enable of channel 1 */ 402 uint32_t :26; /**< bit: 6..31 Reserved */ 403 } bit; /**< Structure used for bit access */ 404 struct { 405 uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Enable of channel x */ 406 uint32_t :2; /**< bit: 2..3 Reserved */ 407 uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Enable of channel x */ 408 uint32_t :26; /**< bit: 6..31 Reserved */ 409 } vec; /**< Structure used for vec access */ 410 uint32_t reg; /**< Type used for register access */ 411 } DACC_IER_Type; 412 #endif 413 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 414 415 #define DACC_IER_OFFSET (0x24) /**< (DACC_IER) Interrupt Enable Register Offset */ 416 417 #define DACC_IER_TXRDY0_Pos 0 /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Position */ 418 #define DACC_IER_TXRDY0_Msk (_U_(0x1) << DACC_IER_TXRDY0_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Mask */ 419 #define DACC_IER_TXRDY0 DACC_IER_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_TXRDY0_Msk instead */ 420 #define DACC_IER_TXRDY1_Pos 1 /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Position */ 421 #define DACC_IER_TXRDY1_Msk (_U_(0x1) << DACC_IER_TXRDY1_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Mask */ 422 #define DACC_IER_TXRDY1 DACC_IER_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_TXRDY1_Msk instead */ 423 #define DACC_IER_EOC0_Pos 4 /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Position */ 424 #define DACC_IER_EOC0_Msk (_U_(0x1) << DACC_IER_EOC0_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Mask */ 425 #define DACC_IER_EOC0 DACC_IER_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_EOC0_Msk instead */ 426 #define DACC_IER_EOC1_Pos 5 /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Position */ 427 #define DACC_IER_EOC1_Msk (_U_(0x1) << DACC_IER_EOC1_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Mask */ 428 #define DACC_IER_EOC1 DACC_IER_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_EOC1_Msk instead */ 429 #define DACC_IER_MASK _U_(0x33) /**< \deprecated (DACC_IER) Register MASK (Use DACC_IER_Msk instead) */ 430 #define DACC_IER_Msk _U_(0x33) /**< (DACC_IER) Register Mask */ 431 432 #define DACC_IER_TXRDY_Pos 0 /**< (DACC_IER Position) Transmit Ready Interrupt Enable of channel x */ 433 #define DACC_IER_TXRDY_Msk (_U_(0x3) << DACC_IER_TXRDY_Pos) /**< (DACC_IER Mask) TXRDY */ 434 #define DACC_IER_TXRDY(value) (DACC_IER_TXRDY_Msk & ((value) << DACC_IER_TXRDY_Pos)) 435 #define DACC_IER_EOC_Pos 4 /**< (DACC_IER Position) End of Conversion Interrupt Enable of channel x */ 436 #define DACC_IER_EOC_Msk (_U_(0x3) << DACC_IER_EOC_Pos) /**< (DACC_IER Mask) EOC */ 437 #define DACC_IER_EOC(value) (DACC_IER_EOC_Msk & ((value) << DACC_IER_EOC_Pos)) 438 439 /* -------- DACC_IDR : (DACC Offset: 0x28) (/W 32) Interrupt Disable Register -------- */ 440 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 441 #if COMPONENT_TYPEDEF_STYLE == 'N' 442 typedef union { 443 struct { 444 uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Disable of channel 0 */ 445 uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Disable of channel 1 */ 446 uint32_t :2; /**< bit: 2..3 Reserved */ 447 uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Disable of channel 0 */ 448 uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Disable of channel 1 */ 449 uint32_t :26; /**< bit: 6..31 Reserved */ 450 } bit; /**< Structure used for bit access */ 451 struct { 452 uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Disable of channel x */ 453 uint32_t :2; /**< bit: 2..3 Reserved */ 454 uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Disable of channel x */ 455 uint32_t :26; /**< bit: 6..31 Reserved */ 456 } vec; /**< Structure used for vec access */ 457 uint32_t reg; /**< Type used for register access */ 458 } DACC_IDR_Type; 459 #endif 460 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 461 462 #define DACC_IDR_OFFSET (0x28) /**< (DACC_IDR) Interrupt Disable Register Offset */ 463 464 #define DACC_IDR_TXRDY0_Pos 0 /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Position */ 465 #define DACC_IDR_TXRDY0_Msk (_U_(0x1) << DACC_IDR_TXRDY0_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Mask */ 466 #define DACC_IDR_TXRDY0 DACC_IDR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_TXRDY0_Msk instead */ 467 #define DACC_IDR_TXRDY1_Pos 1 /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Position */ 468 #define DACC_IDR_TXRDY1_Msk (_U_(0x1) << DACC_IDR_TXRDY1_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Mask */ 469 #define DACC_IDR_TXRDY1 DACC_IDR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_TXRDY1_Msk instead */ 470 #define DACC_IDR_EOC0_Pos 4 /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Position */ 471 #define DACC_IDR_EOC0_Msk (_U_(0x1) << DACC_IDR_EOC0_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Mask */ 472 #define DACC_IDR_EOC0 DACC_IDR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_EOC0_Msk instead */ 473 #define DACC_IDR_EOC1_Pos 5 /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Position */ 474 #define DACC_IDR_EOC1_Msk (_U_(0x1) << DACC_IDR_EOC1_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Mask */ 475 #define DACC_IDR_EOC1 DACC_IDR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_EOC1_Msk instead */ 476 #define DACC_IDR_MASK _U_(0x33) /**< \deprecated (DACC_IDR) Register MASK (Use DACC_IDR_Msk instead) */ 477 #define DACC_IDR_Msk _U_(0x33) /**< (DACC_IDR) Register Mask */ 478 479 #define DACC_IDR_TXRDY_Pos 0 /**< (DACC_IDR Position) Transmit Ready Interrupt Disable of channel x */ 480 #define DACC_IDR_TXRDY_Msk (_U_(0x3) << DACC_IDR_TXRDY_Pos) /**< (DACC_IDR Mask) TXRDY */ 481 #define DACC_IDR_TXRDY(value) (DACC_IDR_TXRDY_Msk & ((value) << DACC_IDR_TXRDY_Pos)) 482 #define DACC_IDR_EOC_Pos 4 /**< (DACC_IDR Position) End of Conversion Interrupt Disable of channel x */ 483 #define DACC_IDR_EOC_Msk (_U_(0x3) << DACC_IDR_EOC_Pos) /**< (DACC_IDR Mask) EOC */ 484 #define DACC_IDR_EOC(value) (DACC_IDR_EOC_Msk & ((value) << DACC_IDR_EOC_Pos)) 485 486 /* -------- DACC_IMR : (DACC Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */ 487 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 488 #if COMPONENT_TYPEDEF_STYLE == 'N' 489 typedef union { 490 struct { 491 uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Mask of channel 0 */ 492 uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Mask of channel 1 */ 493 uint32_t :2; /**< bit: 2..3 Reserved */ 494 uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Mask of channel 0 */ 495 uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Mask of channel 1 */ 496 uint32_t :26; /**< bit: 6..31 Reserved */ 497 } bit; /**< Structure used for bit access */ 498 struct { 499 uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Mask of channel x */ 500 uint32_t :2; /**< bit: 2..3 Reserved */ 501 uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Mask of channel x */ 502 uint32_t :26; /**< bit: 6..31 Reserved */ 503 } vec; /**< Structure used for vec access */ 504 uint32_t reg; /**< Type used for register access */ 505 } DACC_IMR_Type; 506 #endif 507 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 508 509 #define DACC_IMR_OFFSET (0x2C) /**< (DACC_IMR) Interrupt Mask Register Offset */ 510 511 #define DACC_IMR_TXRDY0_Pos 0 /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Position */ 512 #define DACC_IMR_TXRDY0_Msk (_U_(0x1) << DACC_IMR_TXRDY0_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Mask */ 513 #define DACC_IMR_TXRDY0 DACC_IMR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_TXRDY0_Msk instead */ 514 #define DACC_IMR_TXRDY1_Pos 1 /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Position */ 515 #define DACC_IMR_TXRDY1_Msk (_U_(0x1) << DACC_IMR_TXRDY1_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Mask */ 516 #define DACC_IMR_TXRDY1 DACC_IMR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_TXRDY1_Msk instead */ 517 #define DACC_IMR_EOC0_Pos 4 /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Position */ 518 #define DACC_IMR_EOC0_Msk (_U_(0x1) << DACC_IMR_EOC0_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Mask */ 519 #define DACC_IMR_EOC0 DACC_IMR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_EOC0_Msk instead */ 520 #define DACC_IMR_EOC1_Pos 5 /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Position */ 521 #define DACC_IMR_EOC1_Msk (_U_(0x1) << DACC_IMR_EOC1_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Mask */ 522 #define DACC_IMR_EOC1 DACC_IMR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_EOC1_Msk instead */ 523 #define DACC_IMR_MASK _U_(0x33) /**< \deprecated (DACC_IMR) Register MASK (Use DACC_IMR_Msk instead) */ 524 #define DACC_IMR_Msk _U_(0x33) /**< (DACC_IMR) Register Mask */ 525 526 #define DACC_IMR_TXRDY_Pos 0 /**< (DACC_IMR Position) Transmit Ready Interrupt Mask of channel x */ 527 #define DACC_IMR_TXRDY_Msk (_U_(0x3) << DACC_IMR_TXRDY_Pos) /**< (DACC_IMR Mask) TXRDY */ 528 #define DACC_IMR_TXRDY(value) (DACC_IMR_TXRDY_Msk & ((value) << DACC_IMR_TXRDY_Pos)) 529 #define DACC_IMR_EOC_Pos 4 /**< (DACC_IMR Position) End of Conversion Interrupt Mask of channel x */ 530 #define DACC_IMR_EOC_Msk (_U_(0x3) << DACC_IMR_EOC_Pos) /**< (DACC_IMR Mask) EOC */ 531 #define DACC_IMR_EOC(value) (DACC_IMR_EOC_Msk & ((value) << DACC_IMR_EOC_Pos)) 532 533 /* -------- DACC_ISR : (DACC Offset: 0x30) (R/ 32) Interrupt Status Register -------- */ 534 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 535 #if COMPONENT_TYPEDEF_STYLE == 'N' 536 typedef union { 537 struct { 538 uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Flag of channel 0 */ 539 uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Flag of channel 1 */ 540 uint32_t :2; /**< bit: 2..3 Reserved */ 541 uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Flag of channel 0 */ 542 uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Flag of channel 1 */ 543 uint32_t :26; /**< bit: 6..31 Reserved */ 544 } bit; /**< Structure used for bit access */ 545 struct { 546 uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Flag of channel x */ 547 uint32_t :2; /**< bit: 2..3 Reserved */ 548 uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Flag of channel x */ 549 uint32_t :26; /**< bit: 6..31 Reserved */ 550 } vec; /**< Structure used for vec access */ 551 uint32_t reg; /**< Type used for register access */ 552 } DACC_ISR_Type; 553 #endif 554 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 555 556 #define DACC_ISR_OFFSET (0x30) /**< (DACC_ISR) Interrupt Status Register Offset */ 557 558 #define DACC_ISR_TXRDY0_Pos 0 /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Position */ 559 #define DACC_ISR_TXRDY0_Msk (_U_(0x1) << DACC_ISR_TXRDY0_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Mask */ 560 #define DACC_ISR_TXRDY0 DACC_ISR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_TXRDY0_Msk instead */ 561 #define DACC_ISR_TXRDY1_Pos 1 /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Position */ 562 #define DACC_ISR_TXRDY1_Msk (_U_(0x1) << DACC_ISR_TXRDY1_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Mask */ 563 #define DACC_ISR_TXRDY1 DACC_ISR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_TXRDY1_Msk instead */ 564 #define DACC_ISR_EOC0_Pos 4 /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Position */ 565 #define DACC_ISR_EOC0_Msk (_U_(0x1) << DACC_ISR_EOC0_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Mask */ 566 #define DACC_ISR_EOC0 DACC_ISR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_EOC0_Msk instead */ 567 #define DACC_ISR_EOC1_Pos 5 /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Position */ 568 #define DACC_ISR_EOC1_Msk (_U_(0x1) << DACC_ISR_EOC1_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Mask */ 569 #define DACC_ISR_EOC1 DACC_ISR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_EOC1_Msk instead */ 570 #define DACC_ISR_MASK _U_(0x33) /**< \deprecated (DACC_ISR) Register MASK (Use DACC_ISR_Msk instead) */ 571 #define DACC_ISR_Msk _U_(0x33) /**< (DACC_ISR) Register Mask */ 572 573 #define DACC_ISR_TXRDY_Pos 0 /**< (DACC_ISR Position) Transmit Ready Interrupt Flag of channel x */ 574 #define DACC_ISR_TXRDY_Msk (_U_(0x3) << DACC_ISR_TXRDY_Pos) /**< (DACC_ISR Mask) TXRDY */ 575 #define DACC_ISR_TXRDY(value) (DACC_ISR_TXRDY_Msk & ((value) << DACC_ISR_TXRDY_Pos)) 576 #define DACC_ISR_EOC_Pos 4 /**< (DACC_ISR Position) End of Conversion Interrupt Flag of channel x */ 577 #define DACC_ISR_EOC_Msk (_U_(0x3) << DACC_ISR_EOC_Pos) /**< (DACC_ISR Mask) EOC */ 578 #define DACC_ISR_EOC(value) (DACC_ISR_EOC_Msk & ((value) << DACC_ISR_EOC_Pos)) 579 580 /* -------- DACC_ACR : (DACC Offset: 0x94) (R/W 32) Analog Current Register -------- */ 581 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 582 #if COMPONENT_TYPEDEF_STYLE == 'N' 583 typedef union { 584 struct { 585 uint32_t IBCTLCH0:2; /**< bit: 0..1 Analog Output Current Control */ 586 uint32_t IBCTLCH1:2; /**< bit: 2..3 Analog Output Current Control */ 587 uint32_t :28; /**< bit: 4..31 Reserved */ 588 } bit; /**< Structure used for bit access */ 589 uint32_t reg; /**< Type used for register access */ 590 } DACC_ACR_Type; 591 #endif 592 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 593 594 #define DACC_ACR_OFFSET (0x94) /**< (DACC_ACR) Analog Current Register Offset */ 595 596 #define DACC_ACR_IBCTLCH0_Pos 0 /**< (DACC_ACR) Analog Output Current Control Position */ 597 #define DACC_ACR_IBCTLCH0_Msk (_U_(0x3) << DACC_ACR_IBCTLCH0_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ 598 #define DACC_ACR_IBCTLCH0(value) (DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)) 599 #define DACC_ACR_IBCTLCH1_Pos 2 /**< (DACC_ACR) Analog Output Current Control Position */ 600 #define DACC_ACR_IBCTLCH1_Msk (_U_(0x3) << DACC_ACR_IBCTLCH1_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ 601 #define DACC_ACR_IBCTLCH1(value) (DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)) 602 #define DACC_ACR_MASK _U_(0x0F) /**< \deprecated (DACC_ACR) Register MASK (Use DACC_ACR_Msk instead) */ 603 #define DACC_ACR_Msk _U_(0x0F) /**< (DACC_ACR) Register Mask */ 604 605 606 /* -------- DACC_WPMR : (DACC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 607 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 608 #if COMPONENT_TYPEDEF_STYLE == 'N' 609 typedef union { 610 struct { 611 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 612 uint32_t :7; /**< bit: 1..7 Reserved */ 613 uint32_t WPKEY:24; /**< bit: 8..31 Write Protect Key */ 614 } bit; /**< Structure used for bit access */ 615 uint32_t reg; /**< Type used for register access */ 616 } DACC_WPMR_Type; 617 #endif 618 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 619 620 #define DACC_WPMR_OFFSET (0xE4) /**< (DACC_WPMR) Write Protection Mode Register Offset */ 621 622 #define DACC_WPMR_WPEN_Pos 0 /**< (DACC_WPMR) Write Protection Enable Position */ 623 #define DACC_WPMR_WPEN_Msk (_U_(0x1) << DACC_WPMR_WPEN_Pos) /**< (DACC_WPMR) Write Protection Enable Mask */ 624 #define DACC_WPMR_WPEN DACC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_WPMR_WPEN_Msk instead */ 625 #define DACC_WPMR_WPKEY_Pos 8 /**< (DACC_WPMR) Write Protect Key Position */ 626 #define DACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Write Protect Key Mask */ 627 #define DACC_WPMR_WPKEY(value) (DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)) 628 #define DACC_WPMR_WPKEY_PASSWD_Val _U_(0x444143) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ 629 #define DACC_WPMR_WPKEY_PASSWD (DACC_WPMR_WPKEY_PASSWD_Val << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. Position */ 630 #define DACC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (DACC_WPMR) Register MASK (Use DACC_WPMR_Msk instead) */ 631 #define DACC_WPMR_Msk _U_(0xFFFFFF01) /**< (DACC_WPMR) Register Mask */ 632 633 634 /* -------- DACC_WPSR : (DACC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 635 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 636 #if COMPONENT_TYPEDEF_STYLE == 'N' 637 typedef union { 638 struct { 639 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 640 uint32_t :7; /**< bit: 1..7 Reserved */ 641 uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */ 642 uint32_t :16; /**< bit: 16..31 Reserved */ 643 } bit; /**< Structure used for bit access */ 644 uint32_t reg; /**< Type used for register access */ 645 } DACC_WPSR_Type; 646 #endif 647 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 648 649 #define DACC_WPSR_OFFSET (0xE8) /**< (DACC_WPSR) Write Protection Status Register Offset */ 650 651 #define DACC_WPSR_WPVS_Pos 0 /**< (DACC_WPSR) Write Protection Violation Status Position */ 652 #define DACC_WPSR_WPVS_Msk (_U_(0x1) << DACC_WPSR_WPVS_Pos) /**< (DACC_WPSR) Write Protection Violation Status Mask */ 653 #define DACC_WPSR_WPVS DACC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_WPSR_WPVS_Msk instead */ 654 #define DACC_WPSR_WPVSRC_Pos 8 /**< (DACC_WPSR) Write Protection Violation Source Position */ 655 #define DACC_WPSR_WPVSRC_Msk (_U_(0xFF) << DACC_WPSR_WPVSRC_Pos) /**< (DACC_WPSR) Write Protection Violation Source Mask */ 656 #define DACC_WPSR_WPVSRC(value) (DACC_WPSR_WPVSRC_Msk & ((value) << DACC_WPSR_WPVSRC_Pos)) 657 #define DACC_WPSR_MASK _U_(0xFF01) /**< \deprecated (DACC_WPSR) Register MASK (Use DACC_WPSR_Msk instead) */ 658 #define DACC_WPSR_Msk _U_(0xFF01) /**< (DACC_WPSR) Register Mask */ 659 660 661 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 662 #if COMPONENT_TYPEDEF_STYLE == 'R' 663 /** \brief DACC hardware registers */ 664 typedef struct { 665 __O uint32_t DACC_CR; /**< (DACC Offset: 0x00) Control Register */ 666 __IO uint32_t DACC_MR; /**< (DACC Offset: 0x04) Mode Register */ 667 __IO uint32_t DACC_TRIGR; /**< (DACC Offset: 0x08) Trigger Register */ 668 __I uint8_t Reserved1[4]; 669 __O uint32_t DACC_CHER; /**< (DACC Offset: 0x10) Channel Enable Register */ 670 __O uint32_t DACC_CHDR; /**< (DACC Offset: 0x14) Channel Disable Register */ 671 __I uint32_t DACC_CHSR; /**< (DACC Offset: 0x18) Channel Status Register */ 672 __O uint32_t DACC_CDR[2]; /**< (DACC Offset: 0x1C) Conversion Data Register 0 */ 673 __O uint32_t DACC_IER; /**< (DACC Offset: 0x24) Interrupt Enable Register */ 674 __O uint32_t DACC_IDR; /**< (DACC Offset: 0x28) Interrupt Disable Register */ 675 __I uint32_t DACC_IMR; /**< (DACC Offset: 0x2C) Interrupt Mask Register */ 676 __I uint32_t DACC_ISR; /**< (DACC Offset: 0x30) Interrupt Status Register */ 677 __I uint8_t Reserved2[96]; 678 __IO uint32_t DACC_ACR; /**< (DACC Offset: 0x94) Analog Current Register */ 679 __I uint8_t Reserved3[76]; 680 __IO uint32_t DACC_WPMR; /**< (DACC Offset: 0xE4) Write Protection Mode Register */ 681 __I uint32_t DACC_WPSR; /**< (DACC Offset: 0xE8) Write Protection Status Register */ 682 } Dacc; 683 684 #elif COMPONENT_TYPEDEF_STYLE == 'N' 685 /** \brief DACC hardware registers */ 686 typedef struct { 687 __O DACC_CR_Type DACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 688 __IO DACC_MR_Type DACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 689 __IO DACC_TRIGR_Type DACC_TRIGR; /**< Offset: 0x08 (R/W 32) Trigger Register */ 690 __I uint8_t Reserved1[4]; 691 __O DACC_CHER_Type DACC_CHER; /**< Offset: 0x10 ( /W 32) Channel Enable Register */ 692 __O DACC_CHDR_Type DACC_CHDR; /**< Offset: 0x14 ( /W 32) Channel Disable Register */ 693 __I DACC_CHSR_Type DACC_CHSR; /**< Offset: 0x18 (R/ 32) Channel Status Register */ 694 __O DACC_CDR_Type DACC_CDR[2]; /**< Offset: 0x1C ( /W 32) Conversion Data Register 0 */ 695 __O DACC_IER_Type DACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ 696 __O DACC_IDR_Type DACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ 697 __I DACC_IMR_Type DACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ 698 __I DACC_ISR_Type DACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ 699 __I uint8_t Reserved2[96]; 700 __IO DACC_ACR_Type DACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Current Register */ 701 __I uint8_t Reserved3[76]; 702 __IO DACC_WPMR_Type DACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 703 __I DACC_WPSR_Type DACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 704 } Dacc; 705 706 #else /* COMPONENT_TYPEDEF_STYLE */ 707 #error Unknown component typedef style 708 #endif /* COMPONENT_TYPEDEF_STYLE */ 709 710 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 711 /** @} end of Digital-to-Analog Converter Controller */ 712 713 #endif /* _SAME70_DACC_COMPONENT_H_ */ 714
