1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S2C_ 31 #define _SAM4S2C_ 32 33 /** \addtogroup SAM4S2C_definitions SAM4S2C definitions 34 This file defines all structures and symbols for SAM4S2C: 35 - registers and bitfields 36 - peripheral base address 37 - peripheral ID 38 - PIO definitions 39 */ 40 /*@{*/ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 #include <stdint.h> 48 #endif 49 50 /* ************************************************************************** */ 51 /* CMSIS DEFINITIONS FOR SAM4S2C */ 52 /* ************************************************************************** */ 53 /** \addtogroup SAM4S2C_cmsis CMSIS Definitions */ 54 /*@{*/ 55 56 /**< Interrupt Number Definition */ 57 typedef enum IRQn 58 { 59 /****** Cortex-M4 Processor Exceptions Numbers ******************************/ 60 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ 61 HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ 62 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ 63 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ 64 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ 65 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ 66 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ 67 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ 68 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ 69 /****** SAM4S2C specific Interrupt Numbers *********************************/ 70 71 SUPC_IRQn = 0, /**< 0 SAM4S2C Supply Controller (SUPC) */ 72 RSTC_IRQn = 1, /**< 1 SAM4S2C Reset Controller (RSTC) */ 73 RTC_IRQn = 2, /**< 2 SAM4S2C Real Time Clock (RTC) */ 74 RTT_IRQn = 3, /**< 3 SAM4S2C Real Time Timer (RTT) */ 75 WDT_IRQn = 4, /**< 4 SAM4S2C Watchdog Timer (WDT) */ 76 PMC_IRQn = 5, /**< 5 SAM4S2C Power Management Controller (PMC) */ 77 EFC0_IRQn = 6, /**< 6 SAM4S2C Enhanced Embedded Flash Controller 0 (EFC0) */ 78 UART0_IRQn = 8, /**< 8 SAM4S2C UART 0 (UART0) */ 79 UART1_IRQn = 9, /**< 9 SAM4S2C UART 1 (UART1) */ 80 PIOA_IRQn = 11, /**< 11 SAM4S2C Parallel I/O Controller A (PIOA) */ 81 PIOB_IRQn = 12, /**< 12 SAM4S2C Parallel I/O Controller B (PIOB) */ 82 PIOC_IRQn = 13, /**< 13 SAM4S2C Parallel I/O Controller C (PIOC) */ 83 USART0_IRQn = 14, /**< 14 SAM4S2C USART 0 (USART0) */ 84 USART1_IRQn = 15, /**< 15 SAM4S2C USART 1 (USART1) */ 85 HSMCI_IRQn = 18, /**< 18 SAM4S2C Multimedia Card Interface (HSMCI) */ 86 TWI0_IRQn = 19, /**< 19 SAM4S2C Two Wire Interface 0 (TWI0) */ 87 TWI1_IRQn = 20, /**< 20 SAM4S2C Two Wire Interface 1 (TWI1) */ 88 SPI_IRQn = 21, /**< 21 SAM4S2C Serial Peripheral Interface (SPI) */ 89 SSC_IRQn = 22, /**< 22 SAM4S2C Synchronous Serial Controller (SSC) */ 90 TC0_IRQn = 23, /**< 23 SAM4S2C Timer/Counter 0 (TC0) */ 91 TC1_IRQn = 24, /**< 24 SAM4S2C Timer/Counter 1 (TC1) */ 92 TC2_IRQn = 25, /**< 25 SAM4S2C Timer/Counter 2 (TC2) */ 93 TC3_IRQn = 26, /**< 26 SAM4S2C Timer/Counter 3 (TC3) */ 94 TC4_IRQn = 27, /**< 27 SAM4S2C Timer/Counter 4 (TC4) */ 95 TC5_IRQn = 28, /**< 28 SAM4S2C Timer/Counter 5 (TC5) */ 96 ADC_IRQn = 29, /**< 29 SAM4S2C Analog To Digital Converter (ADC) */ 97 DACC_IRQn = 30, /**< 30 SAM4S2C Digital To Analog Converter (DACC) */ 98 PWM_IRQn = 31, /**< 31 SAM4S2C Pulse Width Modulation (PWM) */ 99 CRCCU_IRQn = 32, /**< 32 SAM4S2C CRC Calculation Unit (CRCCU) */ 100 ACC_IRQn = 33, /**< 33 SAM4S2C Analog Comparator (ACC) */ 101 UDP_IRQn = 34, /**< 34 SAM4S2C USB Device Port (UDP) */ 102 103 PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ 104 } IRQn_Type; 105 106 typedef struct _DeviceVectors 107 { 108 /* Stack pointer */ 109 void* pvStack; 110 111 /* Cortex-M handlers */ 112 void* pfnReset_Handler; 113 void* pfnNMI_Handler; 114 void* pfnHardFault_Handler; 115 void* pfnMemManage_Handler; 116 void* pfnBusFault_Handler; 117 void* pfnUsageFault_Handler; 118 void* pfnReserved1_Handler; 119 void* pfnReserved2_Handler; 120 void* pfnReserved3_Handler; 121 void* pfnReserved4_Handler; 122 void* pfnSVC_Handler; 123 void* pfnDebugMon_Handler; 124 void* pfnReserved5_Handler; 125 void* pfnPendSV_Handler; 126 void* pfnSysTick_Handler; 127 128 /* Peripheral handlers */ 129 void* pfnSUPC_Handler; /* 0 Supply Controller */ 130 void* pfnRSTC_Handler; /* 1 Reset Controller */ 131 void* pfnRTC_Handler; /* 2 Real Time Clock */ 132 void* pfnRTT_Handler; /* 3 Real Time Timer */ 133 void* pfnWDT_Handler; /* 4 Watchdog Timer */ 134 void* pfnPMC_Handler; /* 5 Power Management Controller */ 135 void* pfnEFC0_Handler; /* 6 Enhanced Embedded Flash Controller 0 */ 136 void* pvReserved7; 137 void* pfnUART0_Handler; /* 8 UART 0 */ 138 void* pfnUART1_Handler; /* 9 UART 1 */ 139 void* pvReserved10; 140 void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ 141 void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ 142 void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ 143 void* pfnUSART0_Handler; /* 14 USART 0 */ 144 void* pfnUSART1_Handler; /* 15 USART 1 */ 145 void* pvReserved16; 146 void* pvReserved17; 147 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ 148 void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ 149 void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ 150 void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ 151 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ 152 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ 153 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ 154 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ 155 void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ 156 void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ 157 void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ 158 void* pfnADC_Handler; /* 29 Analog To Digital Converter */ 159 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ 160 void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ 161 void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ 162 void* pfnACC_Handler; /* 33 Analog Comparator */ 163 void* pfnUDP_Handler; /* 34 USB Device Port */ 164 } DeviceVectors; 165 166 /* Cortex-M4 core handlers */ 167 void Reset_Handler ( void ); 168 void NMI_Handler ( void ); 169 void HardFault_Handler ( void ); 170 void MemManage_Handler ( void ); 171 void BusFault_Handler ( void ); 172 void UsageFault_Handler ( void ); 173 void SVC_Handler ( void ); 174 void DebugMon_Handler ( void ); 175 void PendSV_Handler ( void ); 176 void SysTick_Handler ( void ); 177 178 /* Peripherals handlers */ 179 void ACC_Handler ( void ); 180 void ADC_Handler ( void ); 181 void CRCCU_Handler ( void ); 182 void DACC_Handler ( void ); 183 void EFC0_Handler ( void ); 184 void HSMCI_Handler ( void ); 185 void PIOA_Handler ( void ); 186 void PIOB_Handler ( void ); 187 void PIOC_Handler ( void ); 188 void PMC_Handler ( void ); 189 void PWM_Handler ( void ); 190 void RSTC_Handler ( void ); 191 void RTC_Handler ( void ); 192 void RTT_Handler ( void ); 193 void SPI_Handler ( void ); 194 void SSC_Handler ( void ); 195 void SUPC_Handler ( void ); 196 void TC0_Handler ( void ); 197 void TC1_Handler ( void ); 198 void TC2_Handler ( void ); 199 void TC3_Handler ( void ); 200 void TC4_Handler ( void ); 201 void TC5_Handler ( void ); 202 void TWI0_Handler ( void ); 203 void TWI1_Handler ( void ); 204 void UART0_Handler ( void ); 205 void UART1_Handler ( void ); 206 void UDP_Handler ( void ); 207 void USART0_Handler ( void ); 208 void USART1_Handler ( void ); 209 void WDT_Handler ( void ); 210 211 /** 212 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals 213 */ 214 215 #define __CM4_REV 0x0001 /**< SAM4S2C core revision number ([15:8] revision number, [7:0] patch number) */ 216 #define __MPU_PRESENT 1 /**< SAM4S2C does provide a MPU */ 217 #define __FPU_PRESENT 0 /**< SAM4S2C does not provide a FPU */ 218 #define __NVIC_PRIO_BITS 4 /**< SAM4S2C uses 4 Bits for the Priority Levels */ 219 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 220 221 /* 222 * \brief CMSIS includes 223 */ 224 225 #include <core_cm4.h> 226 #if !defined DONT_USE_CMSIS_INIT 227 #include "system_sam4s.h" 228 #endif /* DONT_USE_CMSIS_INIT */ 229 230 /*@}*/ 231 232 /* ************************************************************************** */ 233 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S2C */ 234 /* ************************************************************************** */ 235 /** \addtogroup SAM4S2C_api Peripheral Software API */ 236 /*@{*/ 237 238 #include "component/acc.h" 239 #include "component/adc.h" 240 #include "component/chipid.h" 241 #include "component/crccu.h" 242 #include "component/dacc.h" 243 #include "component/efc.h" 244 #include "component/gpbr.h" 245 #include "component/hsmci.h" 246 #include "component/matrix.h" 247 #include "component/pdc.h" 248 #include "component/pio.h" 249 #include "component/pmc.h" 250 #include "component/pwm.h" 251 #include "component/rstc.h" 252 #include "component/rtc.h" 253 #include "component/rtt.h" 254 #include "component/smc.h" 255 #include "component/spi.h" 256 #include "component/ssc.h" 257 #include "component/supc.h" 258 #include "component/tc.h" 259 #include "component/twi.h" 260 #include "component/uart.h" 261 #include "component/udp.h" 262 #include "component/usart.h" 263 #include "component/wdt.h" 264 /*@}*/ 265 266 /* ************************************************************************** */ 267 /* REGISTER ACCESS DEFINITIONS FOR SAM4S2C */ 268 /* ************************************************************************** */ 269 /** \addtogroup SAM4S2C_reg Registers Access Definitions */ 270 /*@{*/ 271 272 #include "instance/hsmci.h" 273 #include "instance/ssc.h" 274 #include "instance/spi.h" 275 #include "instance/tc0.h" 276 #include "instance/tc1.h" 277 #include "instance/twi0.h" 278 #include "instance/twi1.h" 279 #include "instance/pwm.h" 280 #include "instance/usart0.h" 281 #include "instance/usart1.h" 282 #include "instance/udp.h" 283 #include "instance/adc.h" 284 #include "instance/dacc.h" 285 #include "instance/acc.h" 286 #include "instance/crccu.h" 287 #include "instance/smc.h" 288 #include "instance/matrix.h" 289 #include "instance/pmc.h" 290 #include "instance/uart0.h" 291 #include "instance/chipid.h" 292 #include "instance/uart1.h" 293 #include "instance/efc0.h" 294 #include "instance/pioa.h" 295 #include "instance/piob.h" 296 #include "instance/pioc.h" 297 #include "instance/rstc.h" 298 #include "instance/supc.h" 299 #include "instance/rtt.h" 300 #include "instance/wdt.h" 301 #include "instance/rtc.h" 302 #include "instance/gpbr.h" 303 /*@}*/ 304 305 /* ************************************************************************** */ 306 /* PERIPHERAL ID DEFINITIONS FOR SAM4S2C */ 307 /* ************************************************************************** */ 308 /** \addtogroup SAM4S2C_id Peripheral Ids Definitions */ 309 /*@{*/ 310 311 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 312 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 313 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ 314 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ 315 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 316 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 317 #define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */ 318 #define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ 319 #define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ 320 #define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ 321 #define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ 322 #define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ 323 #define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ 324 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */ 325 #define ID_USART1 (15) /**< \brief USART 1 (USART1) */ 326 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ 327 #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ 328 #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ 329 #define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ 330 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ 331 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ 332 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ 333 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ 334 #define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ 335 #define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ 336 #define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ 337 #define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ 338 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ 339 #define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ 340 #define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ 341 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ 342 #define ID_UDP (34) /**< \brief USB Device Port (UDP) */ 343 344 #define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ 345 /*@}*/ 346 347 /* ************************************************************************** */ 348 /* BASE ADDRESS DEFINITIONS FOR SAM4S2C */ 349 /* ************************************************************************** */ 350 /** \addtogroup SAM4S2C_base Peripheral Base Address Definitions */ 351 /*@{*/ 352 353 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 354 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ 355 #define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ 356 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ 357 #define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ 358 #define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ 359 #define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 360 #define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ 361 #define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ 362 #define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ 363 #define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 364 #define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ 365 #define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ 366 #define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ 367 #define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ 368 #define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ 369 #define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ 370 #define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ 371 #define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ 372 #define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ 373 #define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ 374 #define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 375 #define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ 376 #define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ 377 #define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ 378 #define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ 379 #define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ 380 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ 381 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ 382 #define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ 383 #define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 384 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ 385 #define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ 386 #define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ 387 #define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ 388 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ 389 #define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 390 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ 391 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ 392 #define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ 393 #define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ 394 #define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ 395 #define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ 396 #define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ 397 #define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ 398 #else 399 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ 400 #define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ 401 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ 402 #define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ 403 #define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ 404 #define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 405 #define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ 406 #define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ 407 #define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ 408 #define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 409 #define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ 410 #define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ 411 #define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ 412 #define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ 413 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ 414 #define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ 415 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ 416 #define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ 417 #define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ 418 #define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ 419 #define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 420 #define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ 421 #define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ 422 #define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ 423 #define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ 424 #define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ 425 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ 426 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ 427 #define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ 428 #define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 429 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ 430 #define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ 431 #define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ 432 #define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ 433 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 434 #define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 435 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 436 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ 437 #define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ 438 #define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ 439 #define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ 440 #define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ 441 #define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ 442 #define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ 443 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 444 /*@}*/ 445 446 /* ************************************************************************** */ 447 /* PIO DEFINITIONS FOR SAM4S2C */ 448 /* ************************************************************************** */ 449 /** \addtogroup SAM4S2C_pio Peripheral Pio Definitions */ 450 /*@{*/ 451 452 #include "pio/sam4s2c.h" 453 /*@}*/ 454 455 /* ************************************************************************** */ 456 /* MEMORY MAPPING DEFINITIONS FOR SAM4S2C */ 457 /* ************************************************************************** */ 458 459 #define IFLASH0_SIZE (0x20000u) 460 #define IFLASH0_PAGE_SIZE (512u) 461 #define IFLASH0_LOCK_REGION_SIZE (8192u) 462 #define IFLASH0_NB_OF_PAGES (256u) 463 #define IFLASH0_NB_OF_LOCK_BITS (16u) 464 #define IRAM_SIZE (0x10000u) 465 #define IFLASH_SIZE (IFLASH0_SIZE) 466 467 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ 468 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ 469 #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ 470 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ 471 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ 472 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ 473 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ 474 475 /* ************************************************************************** */ 476 /* MISCELLANEOUS DEFINITIONS FOR SAM4S2C */ 477 /* ************************************************************************** */ 478 479 #define CHIP_JTAGID (0x05B3203FUL) 480 #define CHIP_CIDR (0x28AB07E0UL) 481 #define CHIP_EXID (0x0UL) 482 #define NB_CH_ADC (15UL) 483 #define NB_CH_DAC (2UL) 484 #define USB_DEVICE_MAX_EP (8UL) 485 486 /* ************************************************************************** */ 487 /* ELECTRICAL DEFINITIONS FOR SAM4S2C */ 488 /* ************************************************************************** */ 489 490 /* Device characteristics */ 491 #define CHIP_FREQ_SLCK_RC_MIN (20000UL) 492 #define CHIP_FREQ_SLCK_RC (32000UL) 493 #define CHIP_FREQ_SLCK_RC_MAX (44000UL) 494 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) 495 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) 496 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) 497 #define CHIP_FREQ_CPU_MAX (120000000UL) 498 #define CHIP_FREQ_XTAL_32K (32768UL) 499 500 /* Embedded Flash Write Wait State */ 501 #define CHIP_FLASH_WRITE_WAIT_STATE (6U) 502 503 #if defined __SAM4S2A__ || defined __SAM4S2B__ || defined __SAM4S2C__ || \ 504 defined __SAM4S4A__ || defined __SAM4S4B__ || defined __SAM4S4C__ 505 506 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V and VDDIO 3.3V) */ 507 #define CHIP_FREQ_FWS_0 (29000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 508 #define CHIP_FREQ_FWS_1 (58000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 509 #define CHIP_FREQ_FWS_2 (88000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 510 #define CHIP_FREQ_FWS_3 (10800000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 511 #define CHIP_FREQ_FWS_4 (120000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 512 513 #else /* SAM4S8/S16/SA16/SD16/SD32 */ 514 515 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V and VDDIO 3.3V) */ 516 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 517 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 518 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 519 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 520 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 521 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ 522 523 #endif 524 525 /* HYSTeresis levels: please refer to Electrical Characteristics */ 526 #define ACC_ACR_HYST_50MV_MAX (0x01UL) 527 #define ACC_ACR_HYST_90MV_MAX (0x11UL) 528 529 530 531 #ifdef __cplusplus 532 } 533 #endif 534 535 /*@}*/ 536 537 #endif /* _SAM4S2C_ */ 538
