1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S_DACC_COMPONENT_ 31 #define _SAM4S_DACC_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM4S_DACC Digital-to-Analog Converter Controller */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief Dacc hardware registers */ 41 typedef struct { 42 __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ 43 __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ 44 __I uint32_t Reserved1[2]; 45 __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ 46 __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ 47 __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ 48 __I uint32_t Reserved2[1]; 49 __O uint32_t DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ 50 __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ 51 __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ 52 __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ 53 __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ 54 __I uint32_t Reserved3[24]; 55 __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ 56 __I uint32_t Reserved4[19]; 57 __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ 58 __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ 59 __I uint32_t Reserved5[7]; 60 __IO uint32_t DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ 61 __IO uint32_t DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ 62 __I uint32_t Reserved6[2]; 63 __IO uint32_t DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ 64 __IO uint32_t DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ 65 __O uint32_t DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ 66 __I uint32_t DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ 67 } Dacc; 68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 /* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ 70 #define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ 71 /* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ 72 #define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */ 73 #define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free-running mode. */ 74 #define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */ 75 #define DACC_MR_TRGSEL_Pos 1 76 #define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */ 77 #define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos))) 78 #define DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) /**< \brief (DACC_MR) External trigger */ 79 #define DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 0 */ 80 #define DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 1 */ 81 #define DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 2 */ 82 #define DACC_MR_TRGSEL_TRGSEL4 (0x4u << 1) /**< \brief (DACC_MR) PWM Event Line 0 */ 83 #define DACC_MR_TRGSEL_TRGSEL5 (0x5u << 1) /**< \brief (DACC_MR) PWM Event Line 1 */ 84 #define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ 85 #define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-word transfer */ 86 #define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word transfer */ 87 #define DACC_MR_ONE (0x1u << 8) /**< \brief (DACC_MR) Must Be Set to 1 */ 88 #define DACC_MR_USER_SEL_Pos 16 89 #define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */ 90 #define DACC_MR_USER_SEL(value) ((DACC_MR_USER_SEL_Msk & ((value) << DACC_MR_USER_SEL_Pos))) 91 #define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */ 92 #define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */ 93 #define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */ 94 #define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */ 95 #define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */ 96 #define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Maximum Speed Mode */ 97 #define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal mode */ 98 #define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Maximum speed mode enabled */ 99 #define DACC_MR_STARTUP_Pos 24 100 #define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */ 101 #define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos))) 102 #define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of peripheral clock */ 103 #define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of peripheral clock */ 104 #define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of peripheral clock */ 105 #define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of peripheral clock */ 106 #define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of peripheral clock */ 107 #define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of peripheral clock */ 108 #define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of peripheral clock */ 109 #define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of peripheral clock */ 110 #define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of peripheral clock */ 111 #define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of peripheral clock */ 112 #define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of peripheral clock */ 113 #define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of peripheral clock */ 114 #define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of peripheral clock */ 115 #define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of peripheral clock */ 116 #define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of peripheral clock */ 117 #define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of peripheral clock */ 118 #define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of peripheral clock */ 119 #define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of peripheral clock */ 120 #define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of peripheral clock */ 121 #define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of peripheral clock */ 122 #define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of peripheral clock */ 123 #define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of peripheral clock */ 124 #define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of peripheral clock */ 125 #define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of peripheral clock */ 126 #define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of peripheral clock */ 127 #define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of peripheral clock */ 128 #define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of peripheral clock */ 129 #define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of peripheral clock */ 130 #define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of peripheral clock */ 131 #define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of peripheral clock */ 132 #define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of peripheral clock */ 133 #define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of peripheral clock */ 134 #define DACC_MR_STARTUP_2048 (0x20u << 24) /**< \brief (DACC_MR) 2048 periods of peripheral clock */ 135 #define DACC_MR_STARTUP_2112 (0x21u << 24) /**< \brief (DACC_MR) 2112 periods of peripheral clock */ 136 #define DACC_MR_STARTUP_2176 (0x22u << 24) /**< \brief (DACC_MR) 2176 periods of peripheral clock */ 137 #define DACC_MR_STARTUP_2240 (0x23u << 24) /**< \brief (DACC_MR) 2240 periods of peripheral clock */ 138 #define DACC_MR_STARTUP_2304 (0x24u << 24) /**< \brief (DACC_MR) 2304 periods of peripheral clock */ 139 #define DACC_MR_STARTUP_2368 (0x25u << 24) /**< \brief (DACC_MR) 2368 periods of peripheral clock */ 140 #define DACC_MR_STARTUP_2432 (0x26u << 24) /**< \brief (DACC_MR) 2432 periods of peripheral clock */ 141 #define DACC_MR_STARTUP_2496 (0x27u << 24) /**< \brief (DACC_MR) 2496 periods of peripheral clock */ 142 #define DACC_MR_STARTUP_2560 (0x28u << 24) /**< \brief (DACC_MR) 2560 periods of peripheral clock */ 143 #define DACC_MR_STARTUP_2624 (0x29u << 24) /**< \brief (DACC_MR) 2624 periods of peripheral clock */ 144 #define DACC_MR_STARTUP_2688 (0x2Au << 24) /**< \brief (DACC_MR) 2688 periods of peripheral clock */ 145 #define DACC_MR_STARTUP_2752 (0x2Bu << 24) /**< \brief (DACC_MR) 2752 periods of peripheral clock */ 146 #define DACC_MR_STARTUP_2816 (0x2Cu << 24) /**< \brief (DACC_MR) 2816 periods of peripheral clock */ 147 #define DACC_MR_STARTUP_2880 (0x2Du << 24) /**< \brief (DACC_MR) 2880 periods of peripheral clock */ 148 #define DACC_MR_STARTUP_2944 (0x2Eu << 24) /**< \brief (DACC_MR) 2944 periods of peripheral clock */ 149 #define DACC_MR_STARTUP_3008 (0x2Fu << 24) /**< \brief (DACC_MR) 3008 periods of peripheral clock */ 150 #define DACC_MR_STARTUP_3072 (0x30u << 24) /**< \brief (DACC_MR) 3072 periods of peripheral clock */ 151 #define DACC_MR_STARTUP_3136 (0x31u << 24) /**< \brief (DACC_MR) 3136 periods of peripheral clock */ 152 #define DACC_MR_STARTUP_3200 (0x32u << 24) /**< \brief (DACC_MR) 3200 periods of peripheral clock */ 153 #define DACC_MR_STARTUP_3264 (0x33u << 24) /**< \brief (DACC_MR) 3264 periods of peripheral clock */ 154 #define DACC_MR_STARTUP_3328 (0x34u << 24) /**< \brief (DACC_MR) 3328 periods of peripheral clock */ 155 #define DACC_MR_STARTUP_3392 (0x35u << 24) /**< \brief (DACC_MR) 3392 periods of peripheral clock */ 156 #define DACC_MR_STARTUP_3456 (0x36u << 24) /**< \brief (DACC_MR) 3456 periods of peripheral clock */ 157 #define DACC_MR_STARTUP_3520 (0x37u << 24) /**< \brief (DACC_MR) 3520 periods of peripheral clock */ 158 #define DACC_MR_STARTUP_3584 (0x38u << 24) /**< \brief (DACC_MR) 3584 periods of peripheral clock */ 159 #define DACC_MR_STARTUP_3648 (0x39u << 24) /**< \brief (DACC_MR) 3648 periods of peripheral clock */ 160 #define DACC_MR_STARTUP_3712 (0x3Au << 24) /**< \brief (DACC_MR) 3712 periods of peripheral clock */ 161 #define DACC_MR_STARTUP_3776 (0x3Bu << 24) /**< \brief (DACC_MR) 3776 periods of peripheral clock */ 162 #define DACC_MR_STARTUP_3840 (0x3Cu << 24) /**< \brief (DACC_MR) 3840 periods of peripheral clock */ 163 #define DACC_MR_STARTUP_3904 (0x3Du << 24) /**< \brief (DACC_MR) 3904 periods of peripheral clock */ 164 #define DACC_MR_STARTUP_3968 (0x3Eu << 24) /**< \brief (DACC_MR) 3968 periods of peripheral clock */ 165 #define DACC_MR_STARTUP_4032 (0x3Fu << 24) /**< \brief (DACC_MR) 4032 periods of peripheral clock */ 166 /* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ 167 #define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ 168 #define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ 169 /* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ 170 #define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ 171 #define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ 172 /* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ 173 #define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ 174 #define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ 175 /* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ 176 #define DACC_CDR_DATA_Pos 0 177 #define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */ 178 #define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) 179 /* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ 180 #define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ 181 #define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ 182 #define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ 183 #define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ 184 /* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ 185 #define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ 186 #define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ 187 #define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ 188 #define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ 189 /* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ 190 #define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ 191 #define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ 192 #define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ 193 #define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ 194 /* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ 195 #define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ 196 #define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ 197 #define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ 198 #define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ 199 /* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ 200 #define DACC_ACR_IBCTLCH0_Pos 0 201 #define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ 202 #define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) 203 #define DACC_ACR_IBCTLCH1_Pos 2 204 #define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ 205 #define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) 206 #define DACC_ACR_IBCTLDACCORE_Pos 8 207 #define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ 208 #define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos))) 209 /* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */ 210 #define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ 211 #define DACC_WPMR_WPKEY_Pos 8 212 #define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protection Key */ 213 #define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) 214 #define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 215 /* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */ 216 #define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ 217 #define DACC_WPSR_WPVSRC_Pos 8 218 #define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ 219 /* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ 220 #define DACC_TPR_TXPTR_Pos 0 221 #define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */ 222 #define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) 223 /* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ 224 #define DACC_TCR_TXCTR_Pos 0 225 #define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */ 226 #define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) 227 /* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ 228 #define DACC_TNPR_TXNPTR_Pos 0 229 #define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */ 230 #define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) 231 /* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ 232 #define DACC_TNCR_TXNCTR_Pos 0 233 #define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */ 234 #define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) 235 /* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ 236 #define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ 237 #define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ 238 #define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ 239 #define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ 240 /* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ 241 #define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ 242 #define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ 243 244 /*@}*/ 245 246 247 #endif /* _SAM4S_DACC_COMPONENT_ */ 248
