1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S_CRCCU_COMPONENT_ 31 #define _SAM4S_CRCCU_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM4S_CRCCU Cyclic Redundancy Check Calculation Unit */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief Crccu hardware registers */ 41 typedef struct { 42 __IO uint32_t CRCCU_DSCR; /**< \brief (Crccu Offset: 0x000) CRCCU Descriptor Base Register */ 43 __I uint32_t Reserved1[1]; 44 __O uint32_t CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x008) CRCCU DMA Enable Register */ 45 __O uint32_t CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x00C) CRCCU DMA Disable Register */ 46 __I uint32_t CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x010) CRCCU DMA Status Register */ 47 __O uint32_t CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x014) CRCCU DMA Interrupt Enable Register */ 48 __O uint32_t CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x018) CRCCU DMA Interrupt Disable Register */ 49 __I uint32_t CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x001C) CRCCU DMA Interrupt Mask Register */ 50 __I uint32_t CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x020) CRCCU DMA Interrupt Status Register */ 51 __I uint32_t Reserved2[4]; 52 __O uint32_t CRCCU_CR; /**< \brief (Crccu Offset: 0x034) CRCCU Control Register */ 53 __IO uint32_t CRCCU_MR; /**< \brief (Crccu Offset: 0x038) CRCCU Mode Register */ 54 __I uint32_t CRCCU_SR; /**< \brief (Crccu Offset: 0x03C) CRCCU Status Register */ 55 __O uint32_t CRCCU_IER; /**< \brief (Crccu Offset: 0x040) CRCCU Interrupt Enable Register */ 56 __O uint32_t CRCCU_IDR; /**< \brief (Crccu Offset: 0x044) CRCCU Interrupt Disable Register */ 57 __I uint32_t CRCCU_IMR; /**< \brief (Crccu Offset: 0x048) CRCCU Interrupt Mask Register */ 58 __I uint32_t CRCCU_ISR; /**< \brief (Crccu Offset: 0x004C) CRCCU Interrupt Status Register */ 59 } Crccu; 60 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 61 /* -------- CRCCU_DSCR : (CRCCU Offset: 0x000) CRCCU Descriptor Base Register -------- */ 62 #define CRCCU_DSCR_DSCR_Pos 9 63 #define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ 64 #define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos))) 65 /* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x008) CRCCU DMA Enable Register -------- */ 66 #define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable */ 67 /* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x00C) CRCCU DMA Disable Register -------- */ 68 #define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable */ 69 /* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x010) CRCCU DMA Status Register -------- */ 70 #define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status */ 71 /* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x014) CRCCU DMA Interrupt Enable Register -------- */ 72 #define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable */ 73 /* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x018) CRCCU DMA Interrupt Disable Register -------- */ 74 #define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable */ 75 /* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x001C) CRCCU DMA Interrupt Mask Register -------- */ 76 #define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask */ 77 /* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x020) CRCCU DMA Interrupt Status Register -------- */ 78 #define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status */ 79 /* -------- CRCCU_CR : (CRCCU Offset: 0x034) CRCCU Control Register -------- */ 80 #define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ 81 /* -------- CRCCU_MR : (CRCCU Offset: 0x038) CRCCU Mode Register -------- */ 82 #define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */ 83 #define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */ 84 #define CRCCU_MR_PTYPE_Pos 2 85 #define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */ 86 #define CRCCU_MR_PTYPE(value) ((CRCCU_MR_PTYPE_Msk & ((value) << CRCCU_MR_PTYPE_Pos))) 87 #define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ 88 #define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ 89 #define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ 90 #define CRCCU_MR_DIVIDER_Pos 4 91 #define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */ 92 #define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos))) 93 /* -------- CRCCU_SR : (CRCCU Offset: 0x03C) CRCCU Status Register -------- */ 94 #define CRCCU_SR_CRC_Pos 0 95 #define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ 96 /* -------- CRCCU_IER : (CRCCU Offset: 0x040) CRCCU Interrupt Enable Register -------- */ 97 #define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ 98 /* -------- CRCCU_IDR : (CRCCU Offset: 0x044) CRCCU Interrupt Disable Register -------- */ 99 #define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ 100 /* -------- CRCCU_IMR : (CRCCU Offset: 0x048) CRCCU Interrupt Mask Register -------- */ 101 #define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ 102 /* -------- CRCCU_ISR : (CRCCU Offset: 0x004C) CRCCU Interrupt Status Register -------- */ 103 #define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ 104 105 /*@}*/ 106 107 108 #endif /* _SAM4S_CRCCU_COMPONENT_ */ 109
