1 /** 2 * \file 3 * 4 * \brief Header file for SAM4LC8A 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4LC8A_ 30 #define _SAM4LC8A_ 31 32 /** 33 * \ingroup SAM4L_definitions 34 * \addtogroup SAM4LC8A_definitions SAM4LC8A definitions 35 * This file defines all structures and symbols for SAM4LC8A: 36 * - registers and bitfields 37 * - peripheral base address 38 * - peripheral ID 39 * - PIO definitions 40 */ 41 /*@{*/ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 #include <stdint.h> 49 #ifndef __cplusplus 50 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 51 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 52 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 53 #else 54 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 55 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 56 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 57 #endif 58 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 59 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 60 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 61 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 62 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 63 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 64 #if !defined(_UL) 65 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 66 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 67 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 68 #endif 69 #else 70 #if !defined(_UL) 71 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 72 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 73 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 74 #endif 75 #endif 76 77 /* ************************************************************************** */ 78 /** CMSIS DEFINITIONS FOR SAM4LC8A */ 79 /* ************************************************************************** */ 80 /** \defgroup SAM4LC8A_cmsis CMSIS Definitions */ 81 /*@{*/ 82 83 /** Interrupt Number Definition */ 84 typedef enum IRQn 85 { 86 /****** Cortex-M4 Processor Exceptions Numbers ******************************/ 87 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 88 HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ 89 MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ 90 BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ 91 UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ 92 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ 93 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ 94 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ 95 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ 96 /****** SAM4LC8A-specific Interrupt Numbers ***********************/ 97 HFLASHC_IRQn = 0, /**< 0 SAM4LC8A Flash Controller (HFLASHC) */ 98 PDCA_0_IRQn = 1, /**< 1 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_0 */ 99 PDCA_1_IRQn = 2, /**< 2 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_1 */ 100 PDCA_2_IRQn = 3, /**< 3 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_2 */ 101 PDCA_3_IRQn = 4, /**< 4 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_3 */ 102 PDCA_4_IRQn = 5, /**< 5 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_4 */ 103 PDCA_5_IRQn = 6, /**< 6 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_5 */ 104 PDCA_6_IRQn = 7, /**< 7 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_6 */ 105 PDCA_7_IRQn = 8, /**< 8 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_7 */ 106 PDCA_8_IRQn = 9, /**< 9 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_8 */ 107 PDCA_9_IRQn = 10, /**< 10 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_9 */ 108 PDCA_10_IRQn = 11, /**< 11 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_10 */ 109 PDCA_11_IRQn = 12, /**< 12 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_11 */ 110 PDCA_12_IRQn = 13, /**< 13 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_12 */ 111 PDCA_13_IRQn = 14, /**< 14 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_13 */ 112 PDCA_14_IRQn = 15, /**< 15 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_14 */ 113 PDCA_15_IRQn = 16, /**< 16 SAM4LC8A Peripheral DMA Controller (PDCA): PDCA_15 */ 114 CRCCU_IRQn = 17, /**< 17 SAM4LC8A CRC Calculation Unit (CRCCU) */ 115 USBC_IRQn = 18, /**< 18 SAM4LC8A USB 2.0 Interface (USBC) */ 116 PEVC_0_IRQn = 19, /**< 19 SAM4LC8A Peripheral Event Controller (PEVC): PEVC_TR */ 117 PEVC_1_IRQn = 20, /**< 20 SAM4LC8A Peripheral Event Controller (PEVC): PEVC_OV */ 118 AESA_IRQn = 21, /**< 21 SAM4LC8A Advanced Encryption Standard (AESA) */ 119 PM_IRQn = 22, /**< 22 SAM4LC8A Power Manager (PM) */ 120 SCIF_IRQn = 23, /**< 23 SAM4LC8A System Control Interface (SCIF) */ 121 FREQM_IRQn = 24, /**< 24 SAM4LC8A Frequency Meter (FREQM) */ 122 GPIO_0_IRQn = 25, /**< 25 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_0 */ 123 GPIO_1_IRQn = 26, /**< 26 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_1 */ 124 GPIO_2_IRQn = 27, /**< 27 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_2 */ 125 GPIO_3_IRQn = 28, /**< 28 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_3 */ 126 GPIO_4_IRQn = 29, /**< 29 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_4 */ 127 GPIO_5_IRQn = 30, /**< 30 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_5 */ 128 GPIO_6_IRQn = 31, /**< 31 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_6 */ 129 GPIO_7_IRQn = 32, /**< 32 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_7 */ 130 GPIO_8_IRQn = 33, /**< 33 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_8 */ 131 GPIO_9_IRQn = 34, /**< 34 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_9 */ 132 GPIO_10_IRQn = 35, /**< 35 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_10 */ 133 GPIO_11_IRQn = 36, /**< 36 SAM4LC8A General-Purpose Input/Output Controller (GPIO): GPIO_11 */ 134 BPM_IRQn = 37, /**< 37 SAM4LC8A Backup Power Manager (BPM) */ 135 BSCIF_IRQn = 38, /**< 38 SAM4LC8A Backup System Control Interface (BSCIF) */ 136 AST_0_IRQn = 39, /**< 39 SAM4LC8A Asynchronous Timer (AST): AST_ALARM */ 137 AST_1_IRQn = 40, /**< 40 SAM4LC8A Asynchronous Timer (AST): AST_PER */ 138 AST_2_IRQn = 41, /**< 41 SAM4LC8A Asynchronous Timer (AST): AST_OVF */ 139 AST_3_IRQn = 42, /**< 42 SAM4LC8A Asynchronous Timer (AST): AST_READY */ 140 AST_4_IRQn = 43, /**< 43 SAM4LC8A Asynchronous Timer (AST): AST_CLKREADY */ 141 WDT_IRQn = 44, /**< 44 SAM4LC8A Watchdog Timer (WDT) */ 142 EIC_0_IRQn = 45, /**< 45 SAM4LC8A External Interrupt Controller (EIC): EIC_1 */ 143 EIC_1_IRQn = 46, /**< 46 SAM4LC8A External Interrupt Controller (EIC): EIC_2 */ 144 EIC_2_IRQn = 47, /**< 47 SAM4LC8A External Interrupt Controller (EIC): EIC_3 */ 145 EIC_3_IRQn = 48, /**< 48 SAM4LC8A External Interrupt Controller (EIC): EIC_4 */ 146 EIC_4_IRQn = 49, /**< 49 SAM4LC8A External Interrupt Controller (EIC): EIC_5 */ 147 EIC_5_IRQn = 50, /**< 50 SAM4LC8A External Interrupt Controller (EIC): EIC_6 */ 148 EIC_6_IRQn = 51, /**< 51 SAM4LC8A External Interrupt Controller (EIC): EIC_7 */ 149 EIC_7_IRQn = 52, /**< 52 SAM4LC8A External Interrupt Controller (EIC): EIC_8 */ 150 IISC_IRQn = 53, /**< 53 SAM4LC8A Inter-IC Sound (I2S) Controller (IISC) */ 151 SPI_IRQn = 54, /**< 54 SAM4LC8A Serial Peripheral Interface (SPI) */ 152 TC0_0_IRQn = 55, /**< 55 SAM4LC8A Timer/Counter 0 (TC0): TC00 */ 153 TC0_1_IRQn = 56, /**< 56 SAM4LC8A Timer/Counter 0 (TC0): TC01 */ 154 TC0_2_IRQn = 57, /**< 57 SAM4LC8A Timer/Counter 0 (TC0): TC02 */ 155 TC1_0_IRQn = 58, /**< 58 SAM4LC8A Timer/Counter 1 (TC1): TC10 */ 156 TC1_1_IRQn = 59, /**< 59 SAM4LC8A Timer/Counter 1 (TC1): TC11 */ 157 TC1_2_IRQn = 60, /**< 60 SAM4LC8A Timer/Counter 1 (TC1): TC12 */ 158 TWIM0_IRQn = 61, /**< 61 SAM4LC8A Two-wire Master Interface 0 (TWIM0) */ 159 TWIS0_IRQn = 62, /**< 62 SAM4LC8A Two-wire Slave Interface 0 (TWIS0) */ 160 TWIM1_IRQn = 63, /**< 63 SAM4LC8A Two-wire Master Interface 1 (TWIM1) */ 161 TWIS1_IRQn = 64, /**< 64 SAM4LC8A Two-wire Slave Interface 1 (TWIS1) */ 162 USART0_IRQn = 65, /**< 65 SAM4LC8A Universal Synchronous Asynchronous Receiver Transmitter 0 (USART0) */ 163 USART1_IRQn = 66, /**< 66 SAM4LC8A Universal Synchronous Asynchronous Receiver Transmitter 1 (USART1) */ 164 USART2_IRQn = 67, /**< 67 SAM4LC8A Universal Synchronous Asynchronous Receiver Transmitter 2 (USART2) */ 165 USART3_IRQn = 68, /**< 68 SAM4LC8A Universal Synchronous Asynchronous Receiver Transmitter 3 (USART3) */ 166 ADCIFE_IRQn = 69, /**< 69 SAM4LC8A ADC controller interface (ADCIFE) */ 167 DACC_IRQn = 70, /**< 70 SAM4LC8A DAC Controller (DACC) */ 168 ACIFC_IRQn = 71, /**< 71 SAM4LC8A Analog Comparator Interface (ACIFC) */ 169 ABDACB_IRQn = 72, /**< 72 SAM4LC8A Audio Bitstream DAC (ABDACB) */ 170 TRNG_IRQn = 73, /**< 73 SAM4LC8A True Random Number Generator (TRNG) */ 171 PARC_IRQn = 74, /**< 74 SAM4LC8A Parallel Capture (PARC) */ 172 CATB_IRQn = 75, /**< 75 SAM4LC8A Capacitive Touch Module B (CATB) */ 173 TWIM2_IRQn = 77, /**< 77 SAM4LC8A Two-wire Master Interface 2 (TWIM2) */ 174 TWIM3_IRQn = 78, /**< 78 SAM4LC8A Two-wire Master Interface 3 (TWIM3) */ 175 LCDCA_IRQn = 79, /**< 79 SAM4LC8A LCD Controller (LCDCA) */ 176 177 PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ 178 } IRQn_Type; 179 180 typedef struct _DeviceVectors 181 { 182 /* Stack pointer */ 183 void* pvStack; 184 185 /* Cortex-M handlers */ 186 void* pfnReset_Handler; 187 void* pfnNMI_Handler; 188 void* pfnHardFault_Handler; 189 void* pfnMemManage_Handler; 190 void* pfnBusFault_Handler; 191 void* pfnUsageFault_Handler; 192 void* pvReservedM9; 193 void* pvReservedM8; 194 void* pvReservedM7; 195 void* pvReservedM6; 196 void* pfnSVC_Handler; 197 void* pfnDebugMon_Handler; 198 void* pvReservedM3; 199 void* pfnPendSV_Handler; 200 void* pfnSysTick_Handler; 201 202 /* Peripheral handlers */ 203 void* pfnHFLASHC_Handler; /* 0 Flash Controller */ 204 void* pfnPDCA_0_Handler; /* 1 Peripheral DMA Controller IRQ 0 */ 205 void* pfnPDCA_1_Handler; /* 2 Peripheral DMA Controller IRQ 1 */ 206 void* pfnPDCA_2_Handler; /* 3 Peripheral DMA Controller IRQ 2 */ 207 void* pfnPDCA_3_Handler; /* 4 Peripheral DMA Controller IRQ 3 */ 208 void* pfnPDCA_4_Handler; /* 5 Peripheral DMA Controller IRQ 4 */ 209 void* pfnPDCA_5_Handler; /* 6 Peripheral DMA Controller IRQ 5 */ 210 void* pfnPDCA_6_Handler; /* 7 Peripheral DMA Controller IRQ 6 */ 211 void* pfnPDCA_7_Handler; /* 8 Peripheral DMA Controller IRQ 7 */ 212 void* pfnPDCA_8_Handler; /* 9 Peripheral DMA Controller IRQ 8 */ 213 void* pfnPDCA_9_Handler; /* 10 Peripheral DMA Controller IRQ 9 */ 214 void* pfnPDCA_10_Handler; /* 11 Peripheral DMA Controller IRQ 10 */ 215 void* pfnPDCA_11_Handler; /* 12 Peripheral DMA Controller IRQ 11 */ 216 void* pfnPDCA_12_Handler; /* 13 Peripheral DMA Controller IRQ 12 */ 217 void* pfnPDCA_13_Handler; /* 14 Peripheral DMA Controller IRQ 13 */ 218 void* pfnPDCA_14_Handler; /* 15 Peripheral DMA Controller IRQ 14 */ 219 void* pfnPDCA_15_Handler; /* 16 Peripheral DMA Controller IRQ 15 */ 220 void* pfnCRCCU_Handler; /* 17 CRC Calculation Unit */ 221 void* pfnUSBC_Handler; /* 18 USB 2.0 Interface */ 222 void* pfnPEVC_0_Handler; /* 19 Peripheral Event Controller IRQ 0 */ 223 void* pfnPEVC_1_Handler; /* 20 Peripheral Event Controller IRQ 1 */ 224 void* pfnAESA_Handler; /* 21 Advanced Encryption Standard */ 225 void* pfnPM_Handler; /* 22 Power Manager */ 226 void* pfnSCIF_Handler; /* 23 System Control Interface */ 227 void* pfnFREQM_Handler; /* 24 Frequency Meter */ 228 void* pfnGPIO_0_Handler; /* 25 General-Purpose Input/Output Controller IRQ 0 */ 229 void* pfnGPIO_1_Handler; /* 26 General-Purpose Input/Output Controller IRQ 1 */ 230 void* pfnGPIO_2_Handler; /* 27 General-Purpose Input/Output Controller IRQ 2 */ 231 void* pfnGPIO_3_Handler; /* 28 General-Purpose Input/Output Controller IRQ 3 */ 232 void* pfnGPIO_4_Handler; /* 29 General-Purpose Input/Output Controller IRQ 4 */ 233 void* pfnGPIO_5_Handler; /* 30 General-Purpose Input/Output Controller IRQ 5 */ 234 void* pfnGPIO_6_Handler; /* 31 General-Purpose Input/Output Controller IRQ 6 */ 235 void* pfnGPIO_7_Handler; /* 32 General-Purpose Input/Output Controller IRQ 7 */ 236 void* pfnGPIO_8_Handler; /* 33 General-Purpose Input/Output Controller IRQ 8 */ 237 void* pfnGPIO_9_Handler; /* 34 General-Purpose Input/Output Controller IRQ 9 */ 238 void* pfnGPIO_10_Handler; /* 35 General-Purpose Input/Output Controller IRQ 10 */ 239 void* pfnGPIO_11_Handler; /* 36 General-Purpose Input/Output Controller IRQ 11 */ 240 void* pfnBPM_Handler; /* 37 Backup Power Manager */ 241 void* pfnBSCIF_Handler; /* 38 Backup System Control Interface */ 242 void* pfnAST_0_Handler; /* 39 Asynchronous Timer IRQ 0 */ 243 void* pfnAST_1_Handler; /* 40 Asynchronous Timer IRQ 1 */ 244 void* pfnAST_2_Handler; /* 41 Asynchronous Timer IRQ 2 */ 245 void* pfnAST_3_Handler; /* 42 Asynchronous Timer IRQ 3 */ 246 void* pfnAST_4_Handler; /* 43 Asynchronous Timer IRQ 4 */ 247 void* pfnWDT_Handler; /* 44 Watchdog Timer */ 248 void* pfnEIC_0_Handler; /* 45 External Interrupt Controller IRQ 0 */ 249 void* pfnEIC_1_Handler; /* 46 External Interrupt Controller IRQ 1 */ 250 void* pfnEIC_2_Handler; /* 47 External Interrupt Controller IRQ 2 */ 251 void* pfnEIC_3_Handler; /* 48 External Interrupt Controller IRQ 3 */ 252 void* pfnEIC_4_Handler; /* 49 External Interrupt Controller IRQ 4 */ 253 void* pfnEIC_5_Handler; /* 50 External Interrupt Controller IRQ 5 */ 254 void* pfnEIC_6_Handler; /* 51 External Interrupt Controller IRQ 6 */ 255 void* pfnEIC_7_Handler; /* 52 External Interrupt Controller IRQ 7 */ 256 void* pfnIISC_Handler; /* 53 Inter-IC Sound (I2S) Controller */ 257 void* pfnSPI_Handler; /* 54 Serial Peripheral Interface */ 258 void* pfnTC0_0_Handler; /* 55 Timer/Counter 0 IRQ 0 */ 259 void* pfnTC0_1_Handler; /* 56 Timer/Counter 0 IRQ 1 */ 260 void* pfnTC0_2_Handler; /* 57 Timer/Counter 0 IRQ 2 */ 261 void* pfnTC1_0_Handler; /* 58 Timer/Counter 1 IRQ 0 */ 262 void* pfnTC1_1_Handler; /* 59 Timer/Counter 1 IRQ 1 */ 263 void* pfnTC1_2_Handler; /* 60 Timer/Counter 1 IRQ 2 */ 264 void* pfnTWIM0_Handler; /* 61 Two-wire Master Interface 0 */ 265 void* pfnTWIS0_Handler; /* 62 Two-wire Slave Interface 0 */ 266 void* pfnTWIM1_Handler; /* 63 Two-wire Master Interface 1 */ 267 void* pfnTWIS1_Handler; /* 64 Two-wire Slave Interface 1 */ 268 void* pfnUSART0_Handler; /* 65 Universal Synchronous Asynchronous Receiver Transmitter 0 */ 269 void* pfnUSART1_Handler; /* 66 Universal Synchronous Asynchronous Receiver Transmitter 1 */ 270 void* pfnUSART2_Handler; /* 67 Universal Synchronous Asynchronous Receiver Transmitter 2 */ 271 void* pfnUSART3_Handler; /* 68 Universal Synchronous Asynchronous Receiver Transmitter 3 */ 272 void* pfnADCIFE_Handler; /* 69 ADC controller interface */ 273 void* pfnDACC_Handler; /* 70 DAC Controller */ 274 void* pfnACIFC_Handler; /* 71 Analog Comparator Interface */ 275 void* pfnABDACB_Handler; /* 72 Audio Bitstream DAC */ 276 void* pfnTRNG_Handler; /* 73 True Random Number Generator */ 277 void* pfnPARC_Handler; /* 74 Parallel Capture */ 278 void* pfnCATB_Handler; /* 75 Capacitive Touch Module B */ 279 void* pvReserved76; 280 void* pfnTWIM2_Handler; /* 77 Two-wire Master Interface 2 */ 281 void* pfnTWIM3_Handler; /* 78 Two-wire Master Interface 3 */ 282 void* pfnLCDCA_Handler; /* 79 LCD Controller */ 283 } DeviceVectors; 284 285 /* Cortex-M4 processor handlers */ 286 void Reset_Handler ( void ); 287 void NMI_Handler ( void ); 288 void HardFault_Handler ( void ); 289 void MemManage_Handler ( void ); 290 void BusFault_Handler ( void ); 291 void UsageFault_Handler ( void ); 292 void SVC_Handler ( void ); 293 void DebugMon_Handler ( void ); 294 void PendSV_Handler ( void ); 295 void SysTick_Handler ( void ); 296 297 /* Peripherals handlers */ 298 void HFLASHC_Handler ( void ); 299 void PDCA_0_Handler ( void ); 300 void PDCA_1_Handler ( void ); 301 void PDCA_2_Handler ( void ); 302 void PDCA_3_Handler ( void ); 303 void PDCA_4_Handler ( void ); 304 void PDCA_5_Handler ( void ); 305 void PDCA_6_Handler ( void ); 306 void PDCA_7_Handler ( void ); 307 void PDCA_8_Handler ( void ); 308 void PDCA_9_Handler ( void ); 309 void PDCA_10_Handler ( void ); 310 void PDCA_11_Handler ( void ); 311 void PDCA_12_Handler ( void ); 312 void PDCA_13_Handler ( void ); 313 void PDCA_14_Handler ( void ); 314 void PDCA_15_Handler ( void ); 315 void CRCCU_Handler ( void ); 316 void USBC_Handler ( void ); 317 void PEVC_0_Handler ( void ); 318 void PEVC_1_Handler ( void ); 319 void AESA_Handler ( void ); 320 void PM_Handler ( void ); 321 void SCIF_Handler ( void ); 322 void FREQM_Handler ( void ); 323 void GPIO_0_Handler ( void ); 324 void GPIO_1_Handler ( void ); 325 void GPIO_2_Handler ( void ); 326 void GPIO_3_Handler ( void ); 327 void GPIO_4_Handler ( void ); 328 void GPIO_5_Handler ( void ); 329 void GPIO_6_Handler ( void ); 330 void GPIO_7_Handler ( void ); 331 void GPIO_8_Handler ( void ); 332 void GPIO_9_Handler ( void ); 333 void GPIO_10_Handler ( void ); 334 void GPIO_11_Handler ( void ); 335 void BPM_Handler ( void ); 336 void BSCIF_Handler ( void ); 337 void AST_0_Handler ( void ); 338 void AST_1_Handler ( void ); 339 void AST_2_Handler ( void ); 340 void AST_3_Handler ( void ); 341 void AST_4_Handler ( void ); 342 void WDT_Handler ( void ); 343 void EIC_0_Handler ( void ); 344 void EIC_1_Handler ( void ); 345 void EIC_2_Handler ( void ); 346 void EIC_3_Handler ( void ); 347 void EIC_4_Handler ( void ); 348 void EIC_5_Handler ( void ); 349 void EIC_6_Handler ( void ); 350 void EIC_7_Handler ( void ); 351 void IISC_Handler ( void ); 352 void SPI_Handler ( void ); 353 void TC0_0_Handler ( void ); 354 void TC0_1_Handler ( void ); 355 void TC0_2_Handler ( void ); 356 void TC1_0_Handler ( void ); 357 void TC1_1_Handler ( void ); 358 void TC1_2_Handler ( void ); 359 void TWIM0_Handler ( void ); 360 void TWIS0_Handler ( void ); 361 void TWIM1_Handler ( void ); 362 void TWIS1_Handler ( void ); 363 void USART0_Handler ( void ); 364 void USART1_Handler ( void ); 365 void USART2_Handler ( void ); 366 void USART3_Handler ( void ); 367 void ADCIFE_Handler ( void ); 368 void DACC_Handler ( void ); 369 void ACIFC_Handler ( void ); 370 void ABDACB_Handler ( void ); 371 void TRNG_Handler ( void ); 372 void PARC_Handler ( void ); 373 void CATB_Handler ( void ); 374 void TWIM2_Handler ( void ); 375 void TWIM3_Handler ( void ); 376 void LCDCA_Handler ( void ); 377 378 /* 379 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals 380 */ 381 382 #define __BB_PRESENT 0 /*!< BIT_BANDING present or not */ 383 #define __CLKGATE_PRESENT 1 /*!< CLKGATE present or not */ 384 #define __CM4_REV 1 /*!< Core revision r0p1 */ 385 #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ 386 #define __FPU_PRESENT 0 /*!< FPU present or not */ 387 #define __JTAG_PRESENT 1 /*!< JTAG present or not */ 388 #define __MPU_PRESENT 1 /*!< MPU present or not */ 389 #define __NVIC_PRIO_BITS 4 /*!< Number of bits used for Priority Levels */ 390 #define __TRACE_LVL 1 /*!< Standard trace: ITM and DWT triggers and counters, but no ETM */ 391 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 392 #define __WIC_PRESENT 0 /*!< WIC present or not */ 393 394 /** 395 * \brief CMSIS includes 396 */ 397 398 #include <core_cm4.h> 399 #if !defined DONT_USE_CMSIS_INIT 400 #include "system_sam4l.h" 401 #endif /* DONT_USE_CMSIS_INIT */ 402 403 /*@}*/ 404 405 /* ************************************************************************** */ 406 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4LC8A */ 407 /* ************************************************************************** */ 408 /** \defgroup SAM4LC8A_api Peripheral Software API */ 409 /*@{*/ 410 411 #include "component/abdacb.h" 412 #include "component/acifc.h" 413 #include "component/adcife.h" 414 #include "component/aesa.h" 415 #include "component/ast.h" 416 #include "component/bpm.h" 417 #include "component/bscif.h" 418 #include "component/catb.h" 419 #include "component/chipid.h" 420 #include "component/crccu.h" 421 #include "component/dacc.h" 422 #include "component/eic.h" 423 #include "component/flashcalw.h" 424 #include "component/freqm.h" 425 #include "component/gloc.h" 426 #include "component/gpio.h" 427 #include "component/hcache.h" 428 #include "component/hmatrixb.h" 429 #include "component/iisc.h" 430 #include "component/lcdca.h" 431 #include "component/parc.h" 432 #include "component/pdca.h" 433 #include "component/pevc.h" 434 #include "component/picouart.h" 435 #include "component/pm.h" 436 #include "component/scif.h" 437 #include "component/smap.h" 438 #include "component/spi.h" 439 #include "component/tc.h" 440 #include "component/trng.h" 441 #include "component/twim.h" 442 #include "component/twis.h" 443 #include "component/usart.h" 444 #include "component/usbc.h" 445 #include "component/wdt.h" 446 /*@}*/ 447 448 /* ************************************************************************** */ 449 /** REGISTERS ACCESS DEFINITIONS FOR SAM4LC8A */ 450 /* ************************************************************************** */ 451 /** \defgroup SAM4LC8A_reg Registers Access Definitions */ 452 /*@{*/ 453 454 #include "instance/abdacb.h" 455 #include "instance/acifc.h" 456 #include "instance/adcife.h" 457 #include "instance/aesa.h" 458 #include "instance/ast.h" 459 #include "instance/bpm.h" 460 #include "instance/bscif.h" 461 #include "instance/catb.h" 462 #include "instance/chipid.h" 463 #include "instance/crccu.h" 464 #include "instance/dacc.h" 465 #include "instance/eic.h" 466 #include "instance/hflashc.h" 467 #include "instance/freqm.h" 468 #include "instance/gloc.h" 469 #include "instance/gpio.h" 470 #include "instance/hcache.h" 471 #include "instance/hmatrix.h" 472 #include "instance/iisc.h" 473 #include "instance/lcdca.h" 474 #include "instance/parc.h" 475 #include "instance/pdca.h" 476 #include "instance/pevc.h" 477 #include "instance/picouart.h" 478 #include "instance/pm.h" 479 #include "instance/scif.h" 480 #include "instance/smap.h" 481 #include "instance/spi.h" 482 #include "instance/tc0.h" 483 #include "instance/tc1.h" 484 #include "instance/trng.h" 485 #include "instance/twim0.h" 486 #include "instance/twim1.h" 487 #include "instance/twim2.h" 488 #include "instance/twim3.h" 489 #include "instance/twis0.h" 490 #include "instance/twis1.h" 491 #include "instance/usart0.h" 492 #include "instance/usart1.h" 493 #include "instance/usart2.h" 494 #include "instance/usart3.h" 495 #include "instance/usbc.h" 496 #include "instance/wdt.h" 497 /*@}*/ 498 499 /* ************************************************************************** */ 500 /** PERIPHERAL ID DEFINITIONS FOR SAM4LC8A */ 501 /* ************************************************************************** */ 502 /** \defgroup SAM4LC8A_id Peripheral Ids Definitions */ 503 /*@{*/ 504 505 // Peripheral instances on HTOP0 bridge 506 #define ID_IISC 0 /**< \brief Inter-IC Sound (I2S) Controller (IISC) */ 507 #define ID_SPI 1 /**< \brief Serial Peripheral Interface (SPI) */ 508 #define ID_TC0 2 /**< \brief Timer/Counter 0 (TC0) */ 509 #define ID_TC1 3 /**< \brief Timer/Counter 1 (TC1) */ 510 #define ID_TWIM0 4 /**< \brief Two-wire Master Interface 0 (TWIM0) */ 511 #define ID_TWIS0 5 /**< \brief Two-wire Slave Interface 0 (TWIS0) */ 512 #define ID_TWIM1 6 /**< \brief Two-wire Master Interface 1 (TWIM1) */ 513 #define ID_TWIS1 7 /**< \brief Two-wire Slave Interface 1 (TWIS1) */ 514 #define ID_USART0 8 /**< \brief Universal Synchronous Asynchronous Receiver Transmitter 0 (USART0) */ 515 #define ID_USART1 9 /**< \brief Universal Synchronous Asynchronous Receiver Transmitter 1 (USART1) */ 516 #define ID_USART2 10 /**< \brief Universal Synchronous Asynchronous Receiver Transmitter 2 (USART2) */ 517 #define ID_USART3 11 /**< \brief Universal Synchronous Asynchronous Receiver Transmitter 3 (USART3) */ 518 #define ID_ADCIFE 12 /**< \brief ADC controller interface (ADCIFE) */ 519 #define ID_DACC 13 /**< \brief DAC Controller (DACC) */ 520 #define ID_ACIFC 14 /**< \brief Analog Comparator Interface (ACIFC) */ 521 #define ID_GLOC 15 /**< \brief Glue Logic Controller (GLOC) */ 522 #define ID_ABDACB 16 /**< \brief Audio Bitstream DAC (ABDACB) */ 523 #define ID_TRNG 17 /**< \brief True Random Number Generator (TRNG) */ 524 #define ID_PARC 18 /**< \brief Parallel Capture (PARC) */ 525 #define ID_CATB 19 /**< \brief Capacitive Touch Module B (CATB) */ 526 #define ID_TWIM2 21 /**< \brief Two-wire Master Interface 2 (TWIM2) */ 527 #define ID_TWIM3 22 /**< \brief Two-wire Master Interface 3 (TWIM3) */ 528 #define ID_LCDCA 23 /**< \brief LCD Controller (LCDCA) */ 529 530 // Peripheral instances on HTOP1 bridge 531 #define ID_HFLASHC 32 /**< \brief Flash Controller (HFLASHC) */ 532 #define ID_HCACHE 33 /**< \brief Cortex M I&D Cache Controller (HCACHE) */ 533 #define ID_HMATRIX 34 /**< \brief HSB Matrix (HMATRIX) */ 534 #define ID_PDCA 35 /**< \brief Peripheral DMA Controller (PDCA) */ 535 #define ID_SMAP 36 /**< \brief System Manager Access Port (SMAP) */ 536 #define ID_CRCCU 37 /**< \brief CRC Calculation Unit (CRCCU) */ 537 #define ID_USBC 38 /**< \brief USB 2.0 Interface (USBC) */ 538 #define ID_PEVC 39 /**< \brief Peripheral Event Controller (PEVC) */ 539 540 // Peripheral instances on HTOP2 bridge 541 #define ID_PM 64 /**< \brief Power Manager (PM) */ 542 #define ID_CHIPID 65 /**< \brief Chip ID Registers (CHIPID) */ 543 #define ID_SCIF 66 /**< \brief System Control Interface (SCIF) */ 544 #define ID_FREQM 67 /**< \brief Frequency Meter (FREQM) */ 545 #define ID_GPIO 68 /**< \brief General-Purpose Input/Output Controller (GPIO) */ 546 547 // Peripheral instances on HTOP3 bridge 548 #define ID_BPM 96 /**< \brief Backup Power Manager (BPM) */ 549 #define ID_BSCIF 97 /**< \brief Backup System Control Interface (BSCIF) */ 550 #define ID_AST 98 /**< \brief Asynchronous Timer (AST) */ 551 #define ID_WDT 99 /**< \brief Watchdog Timer (WDT) */ 552 #define ID_EIC 100 /**< \brief External Interrupt Controller (EIC) */ 553 #define ID_PICOUART 101 /**< \brief Pico UART (PICOUART) */ 554 555 // Peripheral instances on AHB (as if on bridge 4) 556 #define ID_AESA 128 /**< \brief Advanced Encryption Standard (AESA) */ 557 558 #define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ 559 /*@}*/ 560 561 /* ************************************************************************** */ 562 /** BASE ADDRESS DEFINITIONS FOR SAM4LC8A */ 563 /* ************************************************************************** */ 564 /** \defgroup SAM4LC8A_base Peripheral Base Address Definitions */ 565 /*@{*/ 566 567 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 568 #define ABDACB (0x40064000) /**< \brief (ABDACB) APB Base Address */ 569 #define ACIFC (0x40040000) /**< \brief (ACIFC) APB Base Address */ 570 #define ADCIFE (0x40038000) /**< \brief (ADCIFE) APB Base Address */ 571 #define AESA (0x400B0000) /**< \brief (AESA) AHB Base Address */ 572 #define AST (0x400F0800) /**< \brief (AST) APB Base Address */ 573 #define BPM (0x400F0000) /**< \brief (BPM) APB Base Address */ 574 #define BSCIF (0x400F0400) /**< \brief (BSCIF) APB Base Address */ 575 #define CATB (0x40070000) /**< \brief (CATB) APB Base Address */ 576 #define CHIPID (0x400E0400) /**< \brief (CHIPID) APB Base Address */ 577 #define CRCCU (0x400A4000) /**< \brief (CRCCU) APB Base Address */ 578 #define DACC (0x4003C000) /**< \brief (DACC) APB Base Address */ 579 #define EIC (0x400F1000) /**< \brief (EIC) APB Base Address */ 580 #define HFLASHC (0x400A0000) /**< \brief (HFLASHC) APB Base Address */ 581 #define HFLASHC_FROW (0x00800200) /**< \brief (HFLASHC) FROW Base Address */ 582 #define HFLASHC_USER (0x00800000) /**< \brief (HFLASHC) USER Base Address */ 583 #define FREQM (0x400E0C00) /**< \brief (FREQM) APB Base Address */ 584 #define GLOC (0x40060000) /**< \brief (GLOC) APB Base Address */ 585 #define GPIO (0x400E1000) /**< \brief (GPIO) APB Base Address */ 586 #define HCACHE (0x400A0400) /**< \brief (HCACHE) APB Base Address */ 587 #define HMATRIX (0x400A1000) /**< \brief (HMATRIX) APB Base Address */ 588 #define IISC (0x40004000) /**< \brief (IISC) APB Base Address */ 589 #define LCDCA (0x40080000) /**< \brief (LCDCA) APB Base Address */ 590 #define PARC (0x4006C000) /**< \brief (PARC) APB Base Address */ 591 #define PDCA (0x400A2000) /**< \brief (PDCA) APB Base Address */ 592 #define PEVC (0x400A6000) /**< \brief (PEVC) APB Base Address */ 593 #define PICOUART (0x400F1400) /**< \brief (PICOUART) APB Base Address */ 594 #define PM (0x400E0000) /**< \brief (PM) APB Base Address */ 595 #define SCIF (0x400E0800) /**< \brief (SCIF) APB Base Address */ 596 #define SMAP (0x400A3000) /**< \brief (SMAP) APB Base Address */ 597 #define SPI (0x40008000) /**< \brief (SPI) APB Base Address */ 598 #define TC0 (0x40010000) /**< \brief (TC0) APB Base Address */ 599 #define TC1 (0x40014000) /**< \brief (TC1) APB Base Address */ 600 #define TRNG (0x40068000) /**< \brief (TRNG) APB Base Address */ 601 #define TWIM0 (0x40018000) /**< \brief (TWIM0) APB Base Address */ 602 #define TWIM1 (0x4001C000) /**< \brief (TWIM1) APB Base Address */ 603 #define TWIM2 (0x40078000) /**< \brief (TWIM2) APB Base Address */ 604 #define TWIM3 (0x4007C000) /**< \brief (TWIM3) APB Base Address */ 605 #define TWIS0 (0x40018400) /**< \brief (TWIS0) APB Base Address */ 606 #define TWIS1 (0x4001C400) /**< \brief (TWIS1) APB Base Address */ 607 #define USART0 (0x40024000) /**< \brief (USART0) APB Base Address */ 608 #define USART1 (0x40028000) /**< \brief (USART1) APB Base Address */ 609 #define USART2 (0x4002C000) /**< \brief (USART2) APB Base Address */ 610 #define USART3 (0x40030000) /**< \brief (USART3) APB Base Address */ 611 #define USBC (0x400A5000) /**< \brief (USBC) APB Base Address */ 612 #define WDT (0x400F0C00) /**< \brief (WDT) APB Base Address */ 613 #else 614 #define ABDACB ((Abdacb *)0x40064000UL) /**< \brief (ABDACB) APB Base Address */ 615 #define ABDACB_ADDR (0x40064000UL) /**< \brief (ABDACB) APB Base Address */ 616 #define ABDACB_INST_NUM 1 /**< \brief (ABDACB) Number of instances */ 617 #define ABDACB_INSTS { ABDACB } /**< \brief (ABDACB) Instances List */ 618 619 #define ACIFC ((Acifc *)0x40040000UL) /**< \brief (ACIFC) APB Base Address */ 620 #define ACIFC_ADDR (0x40040000UL) /**< \brief (ACIFC) APB Base Address */ 621 #define ACIFC_INST_NUM 1 /**< \brief (ACIFC) Number of instances */ 622 #define ACIFC_INSTS { ACIFC } /**< \brief (ACIFC) Instances List */ 623 624 #define ADCIFE ((Adcife *)0x40038000UL) /**< \brief (ADCIFE) APB Base Address */ 625 #define ADCIFE_ADDR (0x40038000UL) /**< \brief (ADCIFE) APB Base Address */ 626 #define ADCIFE_INST_NUM 1 /**< \brief (ADCIFE) Number of instances */ 627 #define ADCIFE_INSTS { ADCIFE } /**< \brief (ADCIFE) Instances List */ 628 629 #define AESA ((Aesa *)0x400B0000UL) /**< \brief (AESA) AHB Base Address */ 630 #define AESA_ADDR (0x400B0000UL) /**< \brief (AESA) AHB Base Address */ 631 #define AESA_INST_NUM 1 /**< \brief (AESA) Number of instances */ 632 #define AESA_INSTS { AESA } /**< \brief (AESA) Instances List */ 633 634 #define AST ((Ast *)0x400F0800UL) /**< \brief (AST) APB Base Address */ 635 #define AST_ADDR (0x400F0800UL) /**< \brief (AST) APB Base Address */ 636 #define AST_INST_NUM 1 /**< \brief (AST) Number of instances */ 637 #define AST_INSTS { AST } /**< \brief (AST) Instances List */ 638 639 #define BPM ((Bpm *)0x400F0000UL) /**< \brief (BPM) APB Base Address */ 640 #define BPM_ADDR (0x400F0000UL) /**< \brief (BPM) APB Base Address */ 641 #define BPM_INST_NUM 1 /**< \brief (BPM) Number of instances */ 642 #define BPM_INSTS { BPM } /**< \brief (BPM) Instances List */ 643 644 #define BSCIF ((Bscif *)0x400F0400UL) /**< \brief (BSCIF) APB Base Address */ 645 #define BSCIF_ADDR (0x400F0400UL) /**< \brief (BSCIF) APB Base Address */ 646 #define BSCIF_INST_NUM 1 /**< \brief (BSCIF) Number of instances */ 647 #define BSCIF_INSTS { BSCIF } /**< \brief (BSCIF) Instances List */ 648 649 #define CATB ((Catb *)0x40070000UL) /**< \brief (CATB) APB Base Address */ 650 #define CATB_ADDR (0x40070000UL) /**< \brief (CATB) APB Base Address */ 651 #define CATB_INST_NUM 1 /**< \brief (CATB) Number of instances */ 652 #define CATB_INSTS { CATB } /**< \brief (CATB) Instances List */ 653 654 #define CHIPID ((Chipid *)0x400E0400UL) /**< \brief (CHIPID) APB Base Address */ 655 #define CHIPID_ADDR (0x400E0400UL) /**< \brief (CHIPID) APB Base Address */ 656 #define CHIPID_INST_NUM 1 /**< \brief (CHIPID) Number of instances */ 657 #define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID) Instances List */ 658 659 #define CRCCU ((Crccu *)0x400A4000UL) /**< \brief (CRCCU) APB Base Address */ 660 #define CRCCU_ADDR (0x400A4000UL) /**< \brief (CRCCU) APB Base Address */ 661 #define CRCCU_INST_NUM 1 /**< \brief (CRCCU) Number of instances */ 662 #define CRCCU_INSTS { CRCCU } /**< \brief (CRCCU) Instances List */ 663 664 #define DACC ((Dacc *)0x4003C000UL) /**< \brief (DACC) APB Base Address */ 665 #define DACC_ADDR (0x4003C000UL) /**< \brief (DACC) APB Base Address */ 666 #define DACC_INST_NUM 1 /**< \brief (DACC) Number of instances */ 667 #define DACC_INSTS { DACC } /**< \brief (DACC) Instances List */ 668 669 #define EIC ((Eic *)0x400F1000UL) /**< \brief (EIC) APB Base Address */ 670 #define EIC_ADDR (0x400F1000UL) /**< \brief (EIC) APB Base Address */ 671 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 672 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 673 674 #define HFLASHC ((Flashcalw *)0x400A0000UL) /**< \brief (HFLASHC) APB Base Address */ 675 #define HFLASHC_ADDR (0x400A0000UL) /**< \brief (HFLASHC) APB Base Address */ 676 #define HFLASHC_FROW (0x00800200UL) /**< \brief (HFLASHC) FROW Base Address */ 677 #define HFLASHC_FROW_ADDR (0x00800200UL) /**< \brief (HFLASHC) FROW Base Address */ 678 #define HFLASHC_USER (0x00800000UL) /**< \brief (HFLASHC) USER Base Address */ 679 #define HFLASHC_USER_ADDR (0x00800000UL) /**< \brief (HFLASHC) USER Base Address */ 680 #define FLASHCALW_INST_NUM 1 /**< \brief (FLASHCALW) Number of instances */ 681 #define FLASHCALW_INSTS { HFLASHC } /**< \brief (FLASHCALW) Instances List */ 682 683 #define FREQM ((Freqm *)0x400E0C00UL) /**< \brief (FREQM) APB Base Address */ 684 #define FREQM_ADDR (0x400E0C00UL) /**< \brief (FREQM) APB Base Address */ 685 #define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ 686 #define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ 687 688 #define GLOC ((Gloc *)0x40060000UL) /**< \brief (GLOC) APB Base Address */ 689 #define GLOC_ADDR (0x40060000UL) /**< \brief (GLOC) APB Base Address */ 690 #define GLOC_INST_NUM 1 /**< \brief (GLOC) Number of instances */ 691 #define GLOC_INSTS { GLOC } /**< \brief (GLOC) Instances List */ 692 693 #define GPIO ((Gpio *)0x400E1000UL) /**< \brief (GPIO) APB Base Address */ 694 #define GPIO_ADDR (0x400E1000UL) /**< \brief (GPIO) APB Base Address */ 695 #define GPIO_INST_NUM 1 /**< \brief (GPIO) Number of instances */ 696 #define GPIO_INSTS { GPIO } /**< \brief (GPIO) Instances List */ 697 698 #define HCACHE ((Hcache *)0x400A0400UL) /**< \brief (HCACHE) APB Base Address */ 699 #define HCACHE_ADDR (0x400A0400UL) /**< \brief (HCACHE) APB Base Address */ 700 #define HCACHE_INST_NUM 1 /**< \brief (HCACHE) Number of instances */ 701 #define HCACHE_INSTS { HCACHE } /**< \brief (HCACHE) Instances List */ 702 703 #define HMATRIX ((Hmatrixb *)0x400A1000UL) /**< \brief (HMATRIX) APB Base Address */ 704 #define HMATRIX_ADDR (0x400A1000UL) /**< \brief (HMATRIX) APB Base Address */ 705 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ 706 #define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ 707 708 #define IISC ((Iisc *)0x40004000UL) /**< \brief (IISC) APB Base Address */ 709 #define IISC_ADDR (0x40004000UL) /**< \brief (IISC) APB Base Address */ 710 #define IISC_INST_NUM 1 /**< \brief (IISC) Number of instances */ 711 #define IISC_INSTS { IISC } /**< \brief (IISC) Instances List */ 712 713 #define LCDCA ((Lcdca *)0x40080000UL) /**< \brief (LCDCA) APB Base Address */ 714 #define LCDCA_ADDR (0x40080000UL) /**< \brief (LCDCA) APB Base Address */ 715 #define LCDCA_INST_NUM 1 /**< \brief (LCDCA) Number of instances */ 716 #define LCDCA_INSTS { LCDCA } /**< \brief (LCDCA) Instances List */ 717 718 #define PARC ((Parc *)0x4006C000UL) /**< \brief (PARC) APB Base Address */ 719 #define PARC_ADDR (0x4006C000UL) /**< \brief (PARC) APB Base Address */ 720 #define PARC_INST_NUM 1 /**< \brief (PARC) Number of instances */ 721 #define PARC_INSTS { PARC } /**< \brief (PARC) Instances List */ 722 723 #define PDCA ((Pdca *)0x400A2000UL) /**< \brief (PDCA) APB Base Address */ 724 #define PDCA_ADDR (0x400A2000UL) /**< \brief (PDCA) APB Base Address */ 725 #define PDCA_INST_NUM 1 /**< \brief (PDCA) Number of instances */ 726 #define PDCA_INSTS { PDCA } /**< \brief (PDCA) Instances List */ 727 728 #define PEVC ((Pevc *)0x400A6000UL) /**< \brief (PEVC) APB Base Address */ 729 #define PEVC_ADDR (0x400A6000UL) /**< \brief (PEVC) APB Base Address */ 730 #define PEVC_INST_NUM 1 /**< \brief (PEVC) Number of instances */ 731 #define PEVC_INSTS { PEVC } /**< \brief (PEVC) Instances List */ 732 733 #define PICOUART ((Picouart *)0x400F1400UL) /**< \brief (PICOUART) APB Base Address */ 734 #define PICOUART_ADDR (0x400F1400UL) /**< \brief (PICOUART) APB Base Address */ 735 #define PICOUART_INST_NUM 1 /**< \brief (PICOUART) Number of instances */ 736 #define PICOUART_INSTS { PICOUART } /**< \brief (PICOUART) Instances List */ 737 738 #define PM ((Pm *)0x400E0000UL) /**< \brief (PM) APB Base Address */ 739 #define PM_ADDR (0x400E0000UL) /**< \brief (PM) APB Base Address */ 740 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 741 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 742 743 #define SCIF ((Scif *)0x400E0800UL) /**< \brief (SCIF) APB Base Address */ 744 #define SCIF_ADDR (0x400E0800UL) /**< \brief (SCIF) APB Base Address */ 745 #define SCIF_INST_NUM 1 /**< \brief (SCIF) Number of instances */ 746 #define SCIF_INSTS { SCIF } /**< \brief (SCIF) Instances List */ 747 748 #define SMAP ((Smap *)0x400A3000UL) /**< \brief (SMAP) APB Base Address */ 749 #define SMAP_ADDR (0x400A3000UL) /**< \brief (SMAP) APB Base Address */ 750 #define SMAP_INST_NUM 1 /**< \brief (SMAP) Number of instances */ 751 #define SMAP_INSTS { SMAP } /**< \brief (SMAP) Instances List */ 752 753 #define SPI ((Spi *)0x40008000UL) /**< \brief (SPI) APB Base Address */ 754 #define SPI_ADDR (0x40008000UL) /**< \brief (SPI) APB Base Address */ 755 #define SPI_INST_NUM 1 /**< \brief (SPI) Number of instances */ 756 #define SPI_INSTS { SPI } /**< \brief (SPI) Instances List */ 757 758 #define TC0 ((Tc *)0x40010000UL) /**< \brief (TC0) APB Base Address */ 759 #define TC0_ADDR (0x40010000UL) /**< \brief (TC0) APB Base Address */ 760 #define TC1 ((Tc *)0x40014000UL) /**< \brief (TC1) APB Base Address */ 761 #define TC1_ADDR (0x40014000UL) /**< \brief (TC1) APB Base Address */ 762 #define TC_INST_NUM 2 /**< \brief (TC) Number of instances */ 763 #define TC_INSTS { TC0, TC1 } /**< \brief (TC) Instances List */ 764 765 #define TRNG ((Trng *)0x40068000UL) /**< \brief (TRNG) APB Base Address */ 766 #define TRNG_ADDR (0x40068000UL) /**< \brief (TRNG) APB Base Address */ 767 #define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ 768 #define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ 769 770 #define TWIM0 ((Twim *)0x40018000UL) /**< \brief (TWIM0) APB Base Address */ 771 #define TWIM0_ADDR (0x40018000UL) /**< \brief (TWIM0) APB Base Address */ 772 #define TWIM1 ((Twim *)0x4001C000UL) /**< \brief (TWIM1) APB Base Address */ 773 #define TWIM1_ADDR (0x4001C000UL) /**< \brief (TWIM1) APB Base Address */ 774 #define TWIM2 ((Twim *)0x40078000UL) /**< \brief (TWIM2) APB Base Address */ 775 #define TWIM2_ADDR (0x40078000UL) /**< \brief (TWIM2) APB Base Address */ 776 #define TWIM3 ((Twim *)0x4007C000UL) /**< \brief (TWIM3) APB Base Address */ 777 #define TWIM3_ADDR (0x4007C000UL) /**< \brief (TWIM3) APB Base Address */ 778 #define TWIM_INST_NUM 4 /**< \brief (TWIM) Number of instances */ 779 #define TWIM_INSTS { TWIM0, TWIM1, TWIM2, TWIM3 } /**< \brief (TWIM) Instances List */ 780 781 #define TWIS0 ((Twis *)0x40018400UL) /**< \brief (TWIS0) APB Base Address */ 782 #define TWIS0_ADDR (0x40018400UL) /**< \brief (TWIS0) APB Base Address */ 783 #define TWIS1 ((Twis *)0x4001C400UL) /**< \brief (TWIS1) APB Base Address */ 784 #define TWIS1_ADDR (0x4001C400UL) /**< \brief (TWIS1) APB Base Address */ 785 #define TWIS_INST_NUM 2 /**< \brief (TWIS) Number of instances */ 786 #define TWIS_INSTS { TWIS0, TWIS1 } /**< \brief (TWIS) Instances List */ 787 788 #define USART0 ((Usart *)0x40024000UL) /**< \brief (USART0) APB Base Address */ 789 #define USART0_ADDR (0x40024000UL) /**< \brief (USART0) APB Base Address */ 790 #define USART1 ((Usart *)0x40028000UL) /**< \brief (USART1) APB Base Address */ 791 #define USART1_ADDR (0x40028000UL) /**< \brief (USART1) APB Base Address */ 792 #define USART2 ((Usart *)0x4002C000UL) /**< \brief (USART2) APB Base Address */ 793 #define USART2_ADDR (0x4002C000UL) /**< \brief (USART2) APB Base Address */ 794 #define USART3 ((Usart *)0x40030000UL) /**< \brief (USART3) APB Base Address */ 795 #define USART3_ADDR (0x40030000UL) /**< \brief (USART3) APB Base Address */ 796 #define USART_INST_NUM 4 /**< \brief (USART) Number of instances */ 797 #define USART_INSTS { USART0, USART1, USART2, USART3 } /**< \brief (USART) Instances List */ 798 799 #define USBC ((Usbc *)0x400A5000UL) /**< \brief (USBC) APB Base Address */ 800 #define USBC_ADDR (0x400A5000UL) /**< \brief (USBC) APB Base Address */ 801 #define USBC_INST_NUM 1 /**< \brief (USBC) Number of instances */ 802 #define USBC_INSTS { USBC } /**< \brief (USBC) Instances List */ 803 804 #define WDT ((Wdt *)0x400F0C00UL) /**< \brief (WDT) APB Base Address */ 805 #define WDT_ADDR (0x400F0C00UL) /**< \brief (WDT) APB Base Address */ 806 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 807 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 808 809 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 810 /*@}*/ 811 812 /* ************************************************************************** */ 813 /** GPIO DEFINITIONS FOR SAM4LC8A */ 814 /* ************************************************************************** */ 815 /** \defgroup SAM4LC8A_gpio GPIO Definitions */ 816 /*@{*/ 817 818 #include "pio/sam4lc8a.h" 819 /*@}*/ 820 821 /* ************************************************************************** */ 822 /** ADDITIONAL DEFINITIONS FOR COMPATIBILITY */ 823 /* ************************************************************************** */ 824 /** \addtogroup SAM4LC8A_compat Definitions */ 825 /*@{*/ 826 // These defines are used to keep compatibility with existing 827 // sam/drivers/usart implementation from SAM3/4 products with SAM4L product. 828 #define US_MR_USART_MODE_HW_HANDSHAKING US_MR_USART_MODE_HARDWARE 829 #define US_MR_USART_MODE_IS07816_T_0 US_MR_USART_MODE_ISO7816_T0 830 #define US_MR_USART_MODE_IS07816_T_1 US_MR_USART_MODE_ISO7816_T1 831 #define US_MR_NBSTOP_2_BIT US_MR_NBSTOP_2 832 #define US_MR_NBSTOP_1_5_BIT US_MR_NBSTOP_1_5 833 #define US_MR_NBSTOP_1_BIT US_MR_NBSTOP_1 834 #define US_MR_CHRL_5_BIT US_MR_CHRL_5 835 #define US_MR_CHRL_6_BIT US_MR_CHRL_6 836 #define US_MR_CHRL_7_BIT US_MR_CHRL_7 837 #define US_MR_CHRL_8_BIT US_MR_CHRL_8 838 #define US_MR_PAR_NO US_MR_PAR_NONE 839 #define US_MR_PAR_MULTIDROP US_MR_PAR_MULTI 840 #define US_IF US_IFR 841 #define US_WPSR_WPVS US_WPSR_WPV_1 842 843 #define USBC_UPCFG0_PBK_Msk (0x1u << USBC_UPCFG0_PBK_Pos) 844 845 // These defines for homogeneity with other SAM header files. 846 #define CHIP_FREQ_FWS_0 (18000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 847 #define CHIP_FREQ_FWS_1 (36000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 848 // WARNING NOTE: these are preliminary values. 849 #define CHIP_FREQ_FLASH_HSEN_FWS_0 (18000000UL) /**< \brief Maximum operating frequency when FWS is 0 and the FLASH HS mode is enabled */ 850 #define CHIP_FREQ_FLASH_HSEN_FWS_1 (36000000UL) /**< \brief Maximum operating frequency when FWS is 1 and the FLASH HS mode is enabled */ 851 852 // These defines are used to keep compatibility with existing 853 // sam/drivers/tc implementation from SAM3/4 products with SAM4L product. 854 #define TC_CMR_LDRA_RISING TC_CMR_LDRA_POS_EDGE_TIOA 855 #define TC_CMR_LDRB_FALLING TC_CMR_LDRB_NEG_EDGE_TIOA 856 #define TC_CMR_ETRGEDG_FALLING TC_CMR_ETRGEDG_NEG_EDGE 857 858 // These defines are used to keep compatibility with existing 859 // sam/drivers/spi implementation from SAM3/4 products with SAM4L product. 860 #define SPI_CSR_BITS_8_BIT SPI_CSR_BITS_8_BPT 861 #define SPI_WPCR_SPIWPKEY_VALUE SPI_WPCR_WPKEY_VALUE 862 #define SPI_WPCR_SPIWPEN SPI_WPCR_WPEN 863 864 // These defines are used to keep compatibility with existing 865 // sam/drivers/crccu implementation from SAM3/4 products with SAM4L product. 866 #define CRCCU_DMA_EN CRCCU_DMAEN 867 #define CRCCU_DMA_DIS CRCCU_DMADIS 868 #define CRCCU_DMA_SR CRCCU_DMASR 869 #define CRCCU_DMA_IER CRCCU_DMAIER 870 #define CRCCU_DMA_IDR CRCCU_DMAIDR 871 #define CRCCU_DMA_IMR CRCCU_DMAIMR 872 #define CRCCU_DMA_ISR CRCCU_DMAISR 873 #define CRCCU_DMA_EN_DMAEN CRCCU_DMAEN_DMAEN 874 #define CRCCU_DMA_DIS_DMADIS CRCCU_DMADIS_DMADIS 875 #define CRCCU_DMA_SR_DMASR CRCCU_DMASR_DMASR 876 #define CRCCU_DMA_IER_DMAIER CRCCU_DMAIER_DMAIER 877 #define CRCCU_DMA_IDR_DMAIDR CRCCU_DMAIDR_DMAIDR 878 #define CRCCU_DMA_IMR_DMAIMR CRCCU_DMAIMR_DMAIMR 879 #define CRCCU_DMA_ISR_DMAISR CRCCU_DMAISR_DMAISR 880 /*@}*/ 881 882 /* ************************************************************************** */ 883 /** MEMORY MAPPING DEFINITIONS FOR SAM4LC8A */ 884 /* ************************************************************************** */ 885 886 #define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ 887 #define FLASH_PAGE_SIZE 512 888 #define FLASH_NB_OF_PAGES 1024 889 #define FLASH_USER_PAGE_SIZE 512 890 #define HRAMC0_SIZE _UL_(0x00010000) /* 64 kB */ 891 #define HRAMC1_SIZE _UL_(0x00000800) /* 2 kB */ 892 893 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 894 #define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ 895 #define HRAMC0_ADDR _UL_(0x20000000) /**< HRAMC0 base address */ 896 #define HRAMC1_ADDR _UL_(0x21000000) /**< HRAMC1 base address */ 897 #define HTOP0_ADDR _UL_(0x40000000) /**< HTOP0 base address */ 898 #define HTOP1_ADDR _UL_(0x400A0000) /**< HTOP1 base address */ 899 #define HTOP2_ADDR _UL_(0x400E0000) /**< HTOP2 base address */ 900 #define HTOP3_ADDR _UL_(0x400F0000) /**< HTOP3 base address */ 901 902 #define DSU_DID_RESETVALUE _UL_(0xAB0B0AE0) 903 904 /* ************************************************************************** */ 905 /** ELECTRICAL DEFINITIONS FOR SAM4LC8A */ 906 /* ************************************************************************** */ 907 908 909 #ifdef __cplusplus 910 } 911 #endif 912 913 /*@}*/ 914 915 #endif /* SAM4LC8A_H */ 916
