1 /** 2 * \file 3 * 4 * \brief Instance description for TC0 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_TC0_INSTANCE_ 30 #define _SAM4L_TC0_INSTANCE_ 31 32 /* ========== Register definition for TC0 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_TC0_CCR0 (0x40010000) /**< \brief (TC0) Channel Control Register Channel 0 */ 35 #define REG_TC0_CMR0 (0x40010004) /**< \brief (TC0) Channel Mode Register Channel 0 */ 36 #define REG_TC0_SMMR0 (0x40010008) /**< \brief (TC0) Stepper Motor Mode Register 0 */ 37 #define REG_TC0_CV0 (0x40010010) /**< \brief (TC0) Counter Value Channel 0 */ 38 #define REG_TC0_RA0 (0x40010014) /**< \brief (TC0) Register A Channel 0 */ 39 #define REG_TC0_RB0 (0x40010018) /**< \brief (TC0) Register B Channel 0 */ 40 #define REG_TC0_RC0 (0x4001001C) /**< \brief (TC0) Register C Channel 0 */ 41 #define REG_TC0_SR0 (0x40010020) /**< \brief (TC0) Status Register Channel 0 */ 42 #define REG_TC0_IER0 (0x40010024) /**< \brief (TC0) Interrupt Enable Register Channel 0 */ 43 #define REG_TC0_IDR0 (0x40010028) /**< \brief (TC0) Interrupt Disable Register Channel 0 */ 44 #define REG_TC0_IMR0 (0x4001002C) /**< \brief (TC0) Interrupt Mask Register Channel 0 */ 45 #define REG_TC0_CCR1 (0x40010040) /**< \brief (TC0) Channel Control Register Channel 1 */ 46 #define REG_TC0_CMR1 (0x40010044) /**< \brief (TC0) Channel Mode Register Channel 1 */ 47 #define REG_TC0_SMMR1 (0x40010048) /**< \brief (TC0) Stepper Motor Mode Register 1 */ 48 #define REG_TC0_CV1 (0x40010050) /**< \brief (TC0) Counter Value Channel 1 */ 49 #define REG_TC0_RA1 (0x40010054) /**< \brief (TC0) Register A Channel 1 */ 50 #define REG_TC0_RB1 (0x40010058) /**< \brief (TC0) Register B Channel 1 */ 51 #define REG_TC0_RC1 (0x4001005C) /**< \brief (TC0) Register C Channel 1 */ 52 #define REG_TC0_SR1 (0x40010060) /**< \brief (TC0) Status Register Channel 1 */ 53 #define REG_TC0_IER1 (0x40010064) /**< \brief (TC0) Interrupt Enable Register Channel 1 */ 54 #define REG_TC0_IDR1 (0x40010068) /**< \brief (TC0) Interrupt Disable Register Channel 1 */ 55 #define REG_TC0_IMR1 (0x4001006C) /**< \brief (TC0) Interrupt Mask Register Channel 1 */ 56 #define REG_TC0_CCR2 (0x40010080) /**< \brief (TC0) Channel Control Register Channel 2 */ 57 #define REG_TC0_CMR2 (0x40010084) /**< \brief (TC0) Channel Mode Register Channel 2 */ 58 #define REG_TC0_SMMR2 (0x40010088) /**< \brief (TC0) Stepper Motor Mode Register 2 */ 59 #define REG_TC0_CV2 (0x40010090) /**< \brief (TC0) Counter Value Channel 2 */ 60 #define REG_TC0_RA2 (0x40010094) /**< \brief (TC0) Register A Channel 2 */ 61 #define REG_TC0_RB2 (0x40010098) /**< \brief (TC0) Register B Channel 2 */ 62 #define REG_TC0_RC2 (0x4001009C) /**< \brief (TC0) Register C Channel 2 */ 63 #define REG_TC0_SR2 (0x400100A0) /**< \brief (TC0) Status Register Channel 2 */ 64 #define REG_TC0_IER2 (0x400100A4) /**< \brief (TC0) Interrupt Enable Register Channel 2 */ 65 #define REG_TC0_IDR2 (0x400100A8) /**< \brief (TC0) Interrupt Disable Register Channel 2 */ 66 #define REG_TC0_IMR2 (0x400100AC) /**< \brief (TC0) Interrupt Mask Register Channel 2 */ 67 #define REG_TC0_BCR (0x400100C0) /**< \brief (TC0) TC Block Control Register */ 68 #define REG_TC0_BMR (0x400100C4) /**< \brief (TC0) TC Block Mode Register */ 69 #define REG_TC0_WPMR (0x400100E4) /**< \brief (TC0) Write Protect Mode Register */ 70 #define REG_TC0_FEATURES (0x400100F8) /**< \brief (TC0) Features Register */ 71 #define REG_TC0_VERSION (0x400100FC) /**< \brief (TC0) Version Register */ 72 #else 73 #define REG_TC0_CCR0 (*(WoReg *)0x40010000UL) /**< \brief (TC0) Channel Control Register Channel 0 */ 74 #define REG_TC0_CMR0 (*(RwReg *)0x40010004UL) /**< \brief (TC0) Channel Mode Register Channel 0 */ 75 #define REG_TC0_SMMR0 (*(RwReg *)0x40010008UL) /**< \brief (TC0) Stepper Motor Mode Register 0 */ 76 #define REG_TC0_CV0 (*(RoReg *)0x40010010UL) /**< \brief (TC0) Counter Value Channel 0 */ 77 #define REG_TC0_RA0 (*(RwReg *)0x40010014UL) /**< \brief (TC0) Register A Channel 0 */ 78 #define REG_TC0_RB0 (*(RwReg *)0x40010018UL) /**< \brief (TC0) Register B Channel 0 */ 79 #define REG_TC0_RC0 (*(RwReg *)0x4001001CUL) /**< \brief (TC0) Register C Channel 0 */ 80 #define REG_TC0_SR0 (*(RoReg *)0x40010020UL) /**< \brief (TC0) Status Register Channel 0 */ 81 #define REG_TC0_IER0 (*(WoReg *)0x40010024UL) /**< \brief (TC0) Interrupt Enable Register Channel 0 */ 82 #define REG_TC0_IDR0 (*(WoReg *)0x40010028UL) /**< \brief (TC0) Interrupt Disable Register Channel 0 */ 83 #define REG_TC0_IMR0 (*(RoReg *)0x4001002CUL) /**< \brief (TC0) Interrupt Mask Register Channel 0 */ 84 #define REG_TC0_CCR1 (*(WoReg *)0x40010040UL) /**< \brief (TC0) Channel Control Register Channel 1 */ 85 #define REG_TC0_CMR1 (*(RwReg *)0x40010044UL) /**< \brief (TC0) Channel Mode Register Channel 1 */ 86 #define REG_TC0_SMMR1 (*(RwReg *)0x40010048UL) /**< \brief (TC0) Stepper Motor Mode Register 1 */ 87 #define REG_TC0_CV1 (*(RoReg *)0x40010050UL) /**< \brief (TC0) Counter Value Channel 1 */ 88 #define REG_TC0_RA1 (*(RwReg *)0x40010054UL) /**< \brief (TC0) Register A Channel 1 */ 89 #define REG_TC0_RB1 (*(RwReg *)0x40010058UL) /**< \brief (TC0) Register B Channel 1 */ 90 #define REG_TC0_RC1 (*(RwReg *)0x4001005CUL) /**< \brief (TC0) Register C Channel 1 */ 91 #define REG_TC0_SR1 (*(RoReg *)0x40010060UL) /**< \brief (TC0) Status Register Channel 1 */ 92 #define REG_TC0_IER1 (*(WoReg *)0x40010064UL) /**< \brief (TC0) Interrupt Enable Register Channel 1 */ 93 #define REG_TC0_IDR1 (*(WoReg *)0x40010068UL) /**< \brief (TC0) Interrupt Disable Register Channel 1 */ 94 #define REG_TC0_IMR1 (*(RoReg *)0x4001006CUL) /**< \brief (TC0) Interrupt Mask Register Channel 1 */ 95 #define REG_TC0_CCR2 (*(WoReg *)0x40010080UL) /**< \brief (TC0) Channel Control Register Channel 2 */ 96 #define REG_TC0_CMR2 (*(RwReg *)0x40010084UL) /**< \brief (TC0) Channel Mode Register Channel 2 */ 97 #define REG_TC0_SMMR2 (*(RwReg *)0x40010088UL) /**< \brief (TC0) Stepper Motor Mode Register 2 */ 98 #define REG_TC0_CV2 (*(RoReg *)0x40010090UL) /**< \brief (TC0) Counter Value Channel 2 */ 99 #define REG_TC0_RA2 (*(RwReg *)0x40010094UL) /**< \brief (TC0) Register A Channel 2 */ 100 #define REG_TC0_RB2 (*(RwReg *)0x40010098UL) /**< \brief (TC0) Register B Channel 2 */ 101 #define REG_TC0_RC2 (*(RwReg *)0x4001009CUL) /**< \brief (TC0) Register C Channel 2 */ 102 #define REG_TC0_SR2 (*(RoReg *)0x400100A0UL) /**< \brief (TC0) Status Register Channel 2 */ 103 #define REG_TC0_IER2 (*(WoReg *)0x400100A4UL) /**< \brief (TC0) Interrupt Enable Register Channel 2 */ 104 #define REG_TC0_IDR2 (*(WoReg *)0x400100A8UL) /**< \brief (TC0) Interrupt Disable Register Channel 2 */ 105 #define REG_TC0_IMR2 (*(RoReg *)0x400100ACUL) /**< \brief (TC0) Interrupt Mask Register Channel 2 */ 106 #define REG_TC0_BCR (*(WoReg *)0x400100C0UL) /**< \brief (TC0) TC Block Control Register */ 107 #define REG_TC0_BMR (*(RwReg *)0x400100C4UL) /**< \brief (TC0) TC Block Mode Register */ 108 #define REG_TC0_WPMR (*(RwReg *)0x400100E4UL) /**< \brief (TC0) Write Protect Mode Register */ 109 #define REG_TC0_FEATURES (*(RoReg *)0x400100F8UL) /**< \brief (TC0) Features Register */ 110 #define REG_TC0_VERSION (*(RoReg *)0x400100FCUL) /**< \brief (TC0) Version Register */ 111 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 112 113 /* ========== Instance parameters for TC0 peripheral ========== */ 114 #define TC0_CLK_DIV1 gen_clk_tc0 115 #define TC0_CLK_DIV2 2 116 #define TC0_CLK_DIV3 8 117 #define TC0_CLK_DIV4 32 118 #define TC0_CLK_DIV5 128 119 #define TC0_GCLK_NUM 5 120 121 #endif /* _SAM4L_TC0_INSTANCE_ */ 122
