1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4E_AES_INSTANCE_ 31 #define _SAM4E_AES_INSTANCE_ 32 33 /* ========== Register definition for AES peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_AES_CR (0x40004000U) /**< \brief (AES) Control Register */ 36 #define REG_AES_MR (0x40004004U) /**< \brief (AES) Mode Register */ 37 #define REG_AES_IER (0x40004010U) /**< \brief (AES) Interrupt Enable Register */ 38 #define REG_AES_IDR (0x40004014U) /**< \brief (AES) Interrupt Disable Register */ 39 #define REG_AES_IMR (0x40004018U) /**< \brief (AES) Interrupt Mask Register */ 40 #define REG_AES_ISR (0x4000401CU) /**< \brief (AES) Interrupt Status Register */ 41 #define REG_AES_KEYWR (0x40004020U) /**< \brief (AES) Key Word Register */ 42 #define REG_AES_IDATAR (0x40004040U) /**< \brief (AES) Input Data Register */ 43 #define REG_AES_ODATAR (0x40004050U) /**< \brief (AES) Output Data Register */ 44 #define REG_AES_IVR (0x40004060U) /**< \brief (AES) Initialization Vector Register */ 45 #else 46 #define REG_AES_CR (*(WoReg*)0x40004000U) /**< \brief (AES) Control Register */ 47 #define REG_AES_MR (*(RwReg*)0x40004004U) /**< \brief (AES) Mode Register */ 48 #define REG_AES_IER (*(WoReg*)0x40004010U) /**< \brief (AES) Interrupt Enable Register */ 49 #define REG_AES_IDR (*(WoReg*)0x40004014U) /**< \brief (AES) Interrupt Disable Register */ 50 #define REG_AES_IMR (*(RoReg*)0x40004018U) /**< \brief (AES) Interrupt Mask Register */ 51 #define REG_AES_ISR (*(RoReg*)0x4000401CU) /**< \brief (AES) Interrupt Status Register */ 52 #define REG_AES_KEYWR (*(WoReg*)0x40004020U) /**< \brief (AES) Key Word Register */ 53 #define REG_AES_IDATAR (*(WoReg*)0x40004040U) /**< \brief (AES) Input Data Register */ 54 #define REG_AES_ODATAR (*(RoReg*)0x40004050U) /**< \brief (AES) Output Data Register */ 55 #define REG_AES_IVR (*(WoReg*)0x40004060U) /**< \brief (AES) Initialization Vector Register */ 56 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #endif /* _SAM4E_AES_INSTANCE_ */ 59
