1 /** 2 * \file 3 * 4 * \brief Instance description for SERCOM1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME51_SERCOM1_INSTANCE_ 31 #define _SAME51_SERCOM1_INSTANCE_ 32 33 /* ========== Register definition for SERCOM1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SERCOM1_I2CM_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CM Control A */ 36 #define REG_SERCOM1_I2CM_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CM Control B */ 37 #define REG_SERCOM1_I2CM_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CM Control C */ 38 #define REG_SERCOM1_I2CM_BAUD (0x4000340C) /**< \brief (SERCOM1) I2CM Baud Rate */ 39 #define REG_SERCOM1_I2CM_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ 40 #define REG_SERCOM1_I2CM_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ 41 #define REG_SERCOM1_I2CM_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ 42 #define REG_SERCOM1_I2CM_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CM Status */ 43 #define REG_SERCOM1_I2CM_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CM Synchronization Busy */ 44 #define REG_SERCOM1_I2CM_ADDR (0x40003424) /**< \brief (SERCOM1) I2CM Address */ 45 #define REG_SERCOM1_I2CM_DATA (0x40003428) /**< \brief (SERCOM1) I2CM Data */ 46 #define REG_SERCOM1_I2CM_DBGCTRL (0x40003430) /**< \brief (SERCOM1) I2CM Debug Control */ 47 #define REG_SERCOM1_I2CS_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CS Control A */ 48 #define REG_SERCOM1_I2CS_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CS Control B */ 49 #define REG_SERCOM1_I2CS_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CS Control C */ 50 #define REG_SERCOM1_I2CS_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ 51 #define REG_SERCOM1_I2CS_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ 52 #define REG_SERCOM1_I2CS_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ 53 #define REG_SERCOM1_I2CS_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CS Status */ 54 #define REG_SERCOM1_I2CS_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CS Synchronization Busy */ 55 #define REG_SERCOM1_I2CS_LENGTH (0x40003422) /**< \brief (SERCOM1) I2CS Length */ 56 #define REG_SERCOM1_I2CS_ADDR (0x40003424) /**< \brief (SERCOM1) I2CS Address */ 57 #define REG_SERCOM1_I2CS_DATA (0x40003428) /**< \brief (SERCOM1) I2CS Data */ 58 #define REG_SERCOM1_SPI_CTRLA (0x40003400) /**< \brief (SERCOM1) SPI Control A */ 59 #define REG_SERCOM1_SPI_CTRLB (0x40003404) /**< \brief (SERCOM1) SPI Control B */ 60 #define REG_SERCOM1_SPI_CTRLC (0x40003408) /**< \brief (SERCOM1) SPI Control C */ 61 #define REG_SERCOM1_SPI_BAUD (0x4000340C) /**< \brief (SERCOM1) SPI Baud Rate */ 62 #define REG_SERCOM1_SPI_INTENCLR (0x40003414) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ 63 #define REG_SERCOM1_SPI_INTENSET (0x40003416) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ 64 #define REG_SERCOM1_SPI_INTFLAG (0x40003418) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ 65 #define REG_SERCOM1_SPI_STATUS (0x4000341A) /**< \brief (SERCOM1) SPI Status */ 66 #define REG_SERCOM1_SPI_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) SPI Synchronization Busy */ 67 #define REG_SERCOM1_SPI_LENGTH (0x40003422) /**< \brief (SERCOM1) SPI Length */ 68 #define REG_SERCOM1_SPI_ADDR (0x40003424) /**< \brief (SERCOM1) SPI Address */ 69 #define REG_SERCOM1_SPI_DATA (0x40003428) /**< \brief (SERCOM1) SPI Data */ 70 #define REG_SERCOM1_SPI_DBGCTRL (0x40003430) /**< \brief (SERCOM1) SPI Debug Control */ 71 #define REG_SERCOM1_USART_CTRLA (0x40003400) /**< \brief (SERCOM1) USART Control A */ 72 #define REG_SERCOM1_USART_CTRLB (0x40003404) /**< \brief (SERCOM1) USART Control B */ 73 #define REG_SERCOM1_USART_CTRLC (0x40003408) /**< \brief (SERCOM1) USART Control C */ 74 #define REG_SERCOM1_USART_BAUD (0x4000340C) /**< \brief (SERCOM1) USART Baud Rate */ 75 #define REG_SERCOM1_USART_RXPL (0x4000340E) /**< \brief (SERCOM1) USART Receive Pulse Length */ 76 #define REG_SERCOM1_USART_INTENCLR (0x40003414) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ 77 #define REG_SERCOM1_USART_INTENSET (0x40003416) /**< \brief (SERCOM1) USART Interrupt Enable Set */ 78 #define REG_SERCOM1_USART_INTFLAG (0x40003418) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ 79 #define REG_SERCOM1_USART_STATUS (0x4000341A) /**< \brief (SERCOM1) USART Status */ 80 #define REG_SERCOM1_USART_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) USART Synchronization Busy */ 81 #define REG_SERCOM1_USART_RXERRCNT (0x40003420) /**< \brief (SERCOM1) USART Receive Error Count */ 82 #define REG_SERCOM1_USART_LENGTH (0x40003422) /**< \brief (SERCOM1) USART Length */ 83 #define REG_SERCOM1_USART_DATA (0x40003428) /**< \brief (SERCOM1) USART Data */ 84 #define REG_SERCOM1_USART_DBGCTRL (0x40003430) /**< \brief (SERCOM1) USART Debug Control */ 85 #else 86 #define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CM Control A */ 87 #define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CM Control B */ 88 #define REG_SERCOM1_I2CM_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CM Control C */ 89 #define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4000340CUL) /**< \brief (SERCOM1) I2CM Baud Rate */ 90 #define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ 91 #define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ 92 #define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ 93 #define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CM Status */ 94 #define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */ 95 #define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CM Address */ 96 #define REG_SERCOM1_I2CM_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CM Data */ 97 #define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) I2CM Debug Control */ 98 #define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CS Control A */ 99 #define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CS Control B */ 100 #define REG_SERCOM1_I2CS_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CS Control C */ 101 #define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ 102 #define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ 103 #define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ 104 #define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CS Status */ 105 #define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */ 106 #define REG_SERCOM1_I2CS_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) I2CS Length */ 107 #define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CS Address */ 108 #define REG_SERCOM1_I2CS_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CS Data */ 109 #define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) SPI Control A */ 110 #define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) SPI Control B */ 111 #define REG_SERCOM1_SPI_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) SPI Control C */ 112 #define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4000340CUL) /**< \brief (SERCOM1) SPI Baud Rate */ 113 #define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ 114 #define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ 115 #define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ 116 #define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) SPI Status */ 117 #define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */ 118 #define REG_SERCOM1_SPI_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) SPI Length */ 119 #define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) SPI Address */ 120 #define REG_SERCOM1_SPI_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) SPI Data */ 121 #define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) SPI Debug Control */ 122 #define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) USART Control A */ 123 #define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) USART Control B */ 124 #define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) USART Control C */ 125 #define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4000340CUL) /**< \brief (SERCOM1) USART Baud Rate */ 126 #define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4000340EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */ 127 #define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ 128 #define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */ 129 #define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ 130 #define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) USART Status */ 131 #define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) USART Synchronization Busy */ 132 #define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x40003420UL) /**< \brief (SERCOM1) USART Receive Error Count */ 133 #define REG_SERCOM1_USART_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) USART Length */ 134 #define REG_SERCOM1_USART_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) USART Data */ 135 #define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) USART Debug Control */ 136 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 137 138 /* ========== Instance parameters for SERCOM1 peripheral ========== */ 139 #define SERCOM1_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART 140 #define SERCOM1_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns 141 #define SERCOM1_DMA 1 // DMA support implemented? 142 #define SERCOM1_DMAC_ID_RX 6 // Index of DMA RX trigger 143 #define SERCOM1_DMAC_ID_TX 7 // Index of DMA TX trigger 144 #define SERCOM1_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth. 145 #define SERCOM1_GCLK_ID_CORE 8 146 #define SERCOM1_GCLK_ID_SLOW 3 147 #define SERCOM1_INT_MSB 6 148 #define SERCOM1_I2CM 1 // I2C Master mode implemented? 149 #define SERCOM1_I2CS 1 // I2C Slave mode implemented? 150 #define SERCOM1_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented? 151 #define SERCOM1_I2CS_GROUP_CMD 1 // I2C slave group command implemented? 152 #define SERCOM1_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size 153 #define SERCOM1_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size 154 #define SERCOM1_I2CS_SUDAT 1 // I2C slave SDA setup implemented? 155 #define SERCOM1_I2C_FASTMP 1 // I2C fast mode plus implemented? 156 #define SERCOM1_I2C_HSMODE 1 // USART mode implemented? 157 #define SERCOM1_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented? 158 #define SERCOM1_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented? 159 #define SERCOM1_I2C_TENBIT_ADR 1 // I2C ten bit enabled? 160 #define SERCOM1_PMSB 3 161 #define SERCOM1_RETENTION_SUPPORT 0 // Retention supported? 162 #define SERCOM1_SE_CNT 1 // SE counter included? 163 #define SERCOM1_SPI 1 // SPI mode implemented? 164 #define SERCOM1_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented? 165 #define SERCOM1_SPI_ICSPACE_EXT 1 // SPI inter character space implemented? 166 #define SERCOM1_SPI_OZMO 0 // OZMO features implemented? 167 #define SERCOM1_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? 168 #define SERCOM1_TTBIT_EXTENSION 1 // 32-bit extension implemented? 169 #define SERCOM1_USART 1 // USART mode implemented? 170 #define SERCOM1_USART_AUTOBAUD 1 // USART autobaud implemented? 171 #define SERCOM1_USART_COLDET 1 // USART collision detection implemented? 172 #define SERCOM1_USART_FLOW_CTRL 1 // USART flow control implemented? 173 #define SERCOM1_USART_FRAC_BAUD 1 // USART fractional BAUD implemented? 174 #define SERCOM1_USART_IRDA 1 // USART IrDA implemented? 175 #define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented? 176 #define SERCOM1_USART_LIN_MASTER 1 // USART LIN Master mode implemented? 177 #define SERCOM1_USART_RS485 1 // USART RS485 mode implemented? 178 #define SERCOM1_USART_SAMPA_EXT 1 // USART sample adjust implemented? 179 #define SERCOM1_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented? 180 181 #endif /* _SAME51_SERCOM1_INSTANCE_ */ 182
