1 /** 2 * \file 3 * 4 * \brief Instance description for CAN1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME51_CAN1_INSTANCE_ 31 #define _SAME51_CAN1_INSTANCE_ 32 33 /* ========== Register definition for CAN1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_CAN1_CREL (0x42000400) /**< \brief (CAN1) Core Release */ 36 #define REG_CAN1_ENDN (0x42000404) /**< \brief (CAN1) Endian */ 37 #define REG_CAN1_MRCFG (0x42000408) /**< \brief (CAN1) Message RAM Configuration */ 38 #define REG_CAN1_DBTP (0x4200040C) /**< \brief (CAN1) Fast Bit Timing and Prescaler */ 39 #define REG_CAN1_TEST (0x42000410) /**< \brief (CAN1) Test */ 40 #define REG_CAN1_RWD (0x42000414) /**< \brief (CAN1) RAM Watchdog */ 41 #define REG_CAN1_CCCR (0x42000418) /**< \brief (CAN1) CC Control */ 42 #define REG_CAN1_NBTP (0x4200041C) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */ 43 #define REG_CAN1_TSCC (0x42000420) /**< \brief (CAN1) Timestamp Counter Configuration */ 44 #define REG_CAN1_TSCV (0x42000424) /**< \brief (CAN1) Timestamp Counter Value */ 45 #define REG_CAN1_TOCC (0x42000428) /**< \brief (CAN1) Timeout Counter Configuration */ 46 #define REG_CAN1_TOCV (0x4200042C) /**< \brief (CAN1) Timeout Counter Value */ 47 #define REG_CAN1_ECR (0x42000440) /**< \brief (CAN1) Error Counter */ 48 #define REG_CAN1_PSR (0x42000444) /**< \brief (CAN1) Protocol Status */ 49 #define REG_CAN1_TDCR (0x42000448) /**< \brief (CAN1) Extended ID Filter Configuration */ 50 #define REG_CAN1_IR (0x42000450) /**< \brief (CAN1) Interrupt */ 51 #define REG_CAN1_IE (0x42000454) /**< \brief (CAN1) Interrupt Enable */ 52 #define REG_CAN1_ILS (0x42000458) /**< \brief (CAN1) Interrupt Line Select */ 53 #define REG_CAN1_ILE (0x4200045C) /**< \brief (CAN1) Interrupt Line Enable */ 54 #define REG_CAN1_GFC (0x42000480) /**< \brief (CAN1) Global Filter Configuration */ 55 #define REG_CAN1_SIDFC (0x42000484) /**< \brief (CAN1) Standard ID Filter Configuration */ 56 #define REG_CAN1_XIDFC (0x42000488) /**< \brief (CAN1) Extended ID Filter Configuration */ 57 #define REG_CAN1_XIDAM (0x42000490) /**< \brief (CAN1) Extended ID AND Mask */ 58 #define REG_CAN1_HPMS (0x42000494) /**< \brief (CAN1) High Priority Message Status */ 59 #define REG_CAN1_NDAT1 (0x42000498) /**< \brief (CAN1) New Data 1 */ 60 #define REG_CAN1_NDAT2 (0x4200049C) /**< \brief (CAN1) New Data 2 */ 61 #define REG_CAN1_RXF0C (0x420004A0) /**< \brief (CAN1) Rx FIFO 0 Configuration */ 62 #define REG_CAN1_RXF0S (0x420004A4) /**< \brief (CAN1) Rx FIFO 0 Status */ 63 #define REG_CAN1_RXF0A (0x420004A8) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */ 64 #define REG_CAN1_RXBC (0x420004AC) /**< \brief (CAN1) Rx Buffer Configuration */ 65 #define REG_CAN1_RXF1C (0x420004B0) /**< \brief (CAN1) Rx FIFO 1 Configuration */ 66 #define REG_CAN1_RXF1S (0x420004B4) /**< \brief (CAN1) Rx FIFO 1 Status */ 67 #define REG_CAN1_RXF1A (0x420004B8) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */ 68 #define REG_CAN1_RXESC (0x420004BC) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */ 69 #define REG_CAN1_TXBC (0x420004C0) /**< \brief (CAN1) Tx Buffer Configuration */ 70 #define REG_CAN1_TXFQS (0x420004C4) /**< \brief (CAN1) Tx FIFO / Queue Status */ 71 #define REG_CAN1_TXESC (0x420004C8) /**< \brief (CAN1) Tx Buffer Element Size Configuration */ 72 #define REG_CAN1_TXBRP (0x420004CC) /**< \brief (CAN1) Tx Buffer Request Pending */ 73 #define REG_CAN1_TXBAR (0x420004D0) /**< \brief (CAN1) Tx Buffer Add Request */ 74 #define REG_CAN1_TXBCR (0x420004D4) /**< \brief (CAN1) Tx Buffer Cancellation Request */ 75 #define REG_CAN1_TXBTO (0x420004D8) /**< \brief (CAN1) Tx Buffer Transmission Occurred */ 76 #define REG_CAN1_TXBCF (0x420004DC) /**< \brief (CAN1) Tx Buffer Cancellation Finished */ 77 #define REG_CAN1_TXBTIE (0x420004E0) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */ 78 #define REG_CAN1_TXBCIE (0x420004E4) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */ 79 #define REG_CAN1_TXEFC (0x420004F0) /**< \brief (CAN1) Tx Event FIFO Configuration */ 80 #define REG_CAN1_TXEFS (0x420004F4) /**< \brief (CAN1) Tx Event FIFO Status */ 81 #define REG_CAN1_TXEFA (0x420004F8) /**< \brief (CAN1) Tx Event FIFO Acknowledge */ 82 #else 83 #define REG_CAN1_CREL (*(RoReg *)0x42000400UL) /**< \brief (CAN1) Core Release */ 84 #define REG_CAN1_ENDN (*(RoReg *)0x42000404UL) /**< \brief (CAN1) Endian */ 85 #define REG_CAN1_MRCFG (*(RwReg *)0x42000408UL) /**< \brief (CAN1) Message RAM Configuration */ 86 #define REG_CAN1_DBTP (*(RwReg *)0x4200040CUL) /**< \brief (CAN1) Fast Bit Timing and Prescaler */ 87 #define REG_CAN1_TEST (*(RwReg *)0x42000410UL) /**< \brief (CAN1) Test */ 88 #define REG_CAN1_RWD (*(RwReg *)0x42000414UL) /**< \brief (CAN1) RAM Watchdog */ 89 #define REG_CAN1_CCCR (*(RwReg *)0x42000418UL) /**< \brief (CAN1) CC Control */ 90 #define REG_CAN1_NBTP (*(RwReg *)0x4200041CUL) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */ 91 #define REG_CAN1_TSCC (*(RwReg *)0x42000420UL) /**< \brief (CAN1) Timestamp Counter Configuration */ 92 #define REG_CAN1_TSCV (*(RoReg *)0x42000424UL) /**< \brief (CAN1) Timestamp Counter Value */ 93 #define REG_CAN1_TOCC (*(RwReg *)0x42000428UL) /**< \brief (CAN1) Timeout Counter Configuration */ 94 #define REG_CAN1_TOCV (*(RwReg *)0x4200042CUL) /**< \brief (CAN1) Timeout Counter Value */ 95 #define REG_CAN1_ECR (*(RoReg *)0x42000440UL) /**< \brief (CAN1) Error Counter */ 96 #define REG_CAN1_PSR (*(RoReg *)0x42000444UL) /**< \brief (CAN1) Protocol Status */ 97 #define REG_CAN1_TDCR (*(RwReg *)0x42000448UL) /**< \brief (CAN1) Extended ID Filter Configuration */ 98 #define REG_CAN1_IR (*(RwReg *)0x42000450UL) /**< \brief (CAN1) Interrupt */ 99 #define REG_CAN1_IE (*(RwReg *)0x42000454UL) /**< \brief (CAN1) Interrupt Enable */ 100 #define REG_CAN1_ILS (*(RwReg *)0x42000458UL) /**< \brief (CAN1) Interrupt Line Select */ 101 #define REG_CAN1_ILE (*(RwReg *)0x4200045CUL) /**< \brief (CAN1) Interrupt Line Enable */ 102 #define REG_CAN1_GFC (*(RwReg *)0x42000480UL) /**< \brief (CAN1) Global Filter Configuration */ 103 #define REG_CAN1_SIDFC (*(RwReg *)0x42000484UL) /**< \brief (CAN1) Standard ID Filter Configuration */ 104 #define REG_CAN1_XIDFC (*(RwReg *)0x42000488UL) /**< \brief (CAN1) Extended ID Filter Configuration */ 105 #define REG_CAN1_XIDAM (*(RwReg *)0x42000490UL) /**< \brief (CAN1) Extended ID AND Mask */ 106 #define REG_CAN1_HPMS (*(RoReg *)0x42000494UL) /**< \brief (CAN1) High Priority Message Status */ 107 #define REG_CAN1_NDAT1 (*(RwReg *)0x42000498UL) /**< \brief (CAN1) New Data 1 */ 108 #define REG_CAN1_NDAT2 (*(RwReg *)0x4200049CUL) /**< \brief (CAN1) New Data 2 */ 109 #define REG_CAN1_RXF0C (*(RwReg *)0x420004A0UL) /**< \brief (CAN1) Rx FIFO 0 Configuration */ 110 #define REG_CAN1_RXF0S (*(RoReg *)0x420004A4UL) /**< \brief (CAN1) Rx FIFO 0 Status */ 111 #define REG_CAN1_RXF0A (*(RwReg *)0x420004A8UL) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */ 112 #define REG_CAN1_RXBC (*(RwReg *)0x420004ACUL) /**< \brief (CAN1) Rx Buffer Configuration */ 113 #define REG_CAN1_RXF1C (*(RwReg *)0x420004B0UL) /**< \brief (CAN1) Rx FIFO 1 Configuration */ 114 #define REG_CAN1_RXF1S (*(RoReg *)0x420004B4UL) /**< \brief (CAN1) Rx FIFO 1 Status */ 115 #define REG_CAN1_RXF1A (*(RwReg *)0x420004B8UL) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */ 116 #define REG_CAN1_RXESC (*(RwReg *)0x420004BCUL) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */ 117 #define REG_CAN1_TXBC (*(RwReg *)0x420004C0UL) /**< \brief (CAN1) Tx Buffer Configuration */ 118 #define REG_CAN1_TXFQS (*(RoReg *)0x420004C4UL) /**< \brief (CAN1) Tx FIFO / Queue Status */ 119 #define REG_CAN1_TXESC (*(RwReg *)0x420004C8UL) /**< \brief (CAN1) Tx Buffer Element Size Configuration */ 120 #define REG_CAN1_TXBRP (*(RoReg *)0x420004CCUL) /**< \brief (CAN1) Tx Buffer Request Pending */ 121 #define REG_CAN1_TXBAR (*(RwReg *)0x420004D0UL) /**< \brief (CAN1) Tx Buffer Add Request */ 122 #define REG_CAN1_TXBCR (*(RwReg *)0x420004D4UL) /**< \brief (CAN1) Tx Buffer Cancellation Request */ 123 #define REG_CAN1_TXBTO (*(RoReg *)0x420004D8UL) /**< \brief (CAN1) Tx Buffer Transmission Occurred */ 124 #define REG_CAN1_TXBCF (*(RoReg *)0x420004DCUL) /**< \brief (CAN1) Tx Buffer Cancellation Finished */ 125 #define REG_CAN1_TXBTIE (*(RwReg *)0x420004E0UL) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */ 126 #define REG_CAN1_TXBCIE (*(RwReg *)0x420004E4UL) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */ 127 #define REG_CAN1_TXEFC (*(RwReg *)0x420004F0UL) /**< \brief (CAN1) Tx Event FIFO Configuration */ 128 #define REG_CAN1_TXEFS (*(RoReg *)0x420004F4UL) /**< \brief (CAN1) Tx Event FIFO Status */ 129 #define REG_CAN1_TXEFA (*(RwReg *)0x420004F8UL) /**< \brief (CAN1) Tx Event FIFO Acknowledge */ 130 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 131 132 /* ========== Instance parameters for CAN1 peripheral ========== */ 133 #define CAN1_CLK_AHB_ID 18 // Index of AHB clock 134 #define CAN1_DMAC_ID_DEBUG 21 // DMA CAN Debug Req 135 #define CAN1_GCLK_ID 28 // Index of Generic Clock 136 #define CAN1_MSG_RAM_ADDR 0x20000000 137 #define CAN1_QOS_RESET_VAL 1 // QOS reset value 138 139 #endif /* _SAME51_CAN1_INSTANCE_ */ 140
