1 /** 2 * \file 3 * 4 * \brief Component description for TRNG 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_TRNG_COMPONENT_ 30 #define _SAM4L_TRNG_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TRNG */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_TRNG True Random Number Generator */ 36 /*@{*/ 37 38 #define TRNG_I7643 39 #define REV_TRNG 0x103 40 41 /* -------- TRNG_CR : (TRNG Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t ENABLE:1; /*!< bit: 0 Enables the TRNG to provide random values */ 46 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 47 uint32_t KEY:24; /*!< bit: 8..31 Security Key */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } TRNG_CR_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define TRNG_CR_OFFSET 0x00 /**< \brief (TRNG_CR offset) Control Register */ 54 #define TRNG_CR_RESETVALUE _U_(0x00000000); /**< \brief (TRNG_CR reset_value) Control Register */ 55 56 #define TRNG_CR_ENABLE_Pos 0 /**< \brief (TRNG_CR) Enables the TRNG to provide random values */ 57 #define TRNG_CR_ENABLE (_U_(0x1) << TRNG_CR_ENABLE_Pos) 58 #define TRNG_CR_KEY_Pos 8 /**< \brief (TRNG_CR) Security Key */ 59 #define TRNG_CR_KEY_Msk (_U_(0xFFFFFF) << TRNG_CR_KEY_Pos) 60 #define TRNG_CR_KEY(value) (TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)) 61 #define TRNG_CR_KEY_PASSWD_Val _U_(0x524E47) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. */ 62 #define TRNG_CR_KEY_PASSWD (TRNG_CR_KEY_PASSWD_Val << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. Position */ 63 #define TRNG_CR_MASK _U_(0xFFFFFF01) /**< \deprecated (TRNG_CR) Register MASK (Use TRNG_CR_Msk instead) */ 64 #define TRNG_CR_Msk _U_(0xFFFFFF01) /**< (TRNG_CR) Register Mask */ 65 66 /* -------- TRNG_IER : (TRNG Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint32_t DATRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ 71 uint32_t :31; /*!< bit: 1..31 Reserved */ 72 } bit; /*!< Structure used for bit access */ 73 uint32_t reg; /*!< Type used for register access */ 74 } TRNG_IER_Type; 75 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 76 77 #define TRNG_IER_OFFSET 0x10 /**< \brief (TRNG_IER offset) Interrupt Enable Register */ 78 #define TRNG_IER_RESETVALUE _U_(0x00000000); /**< \brief (TRNG_IER reset_value) Interrupt Enable Register */ 79 80 #define TRNG_IER_DATRDY_Pos 0 /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ 81 #define TRNG_IER_DATRDY (_U_(0x1) << TRNG_IER_DATRDY_Pos) 82 #define TRNG_IER_MASK _U_(0x00000001) /**< \brief (TRNG_IER) MASK Register */ 83 84 /* -------- TRNG_IDR : (TRNG Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ 85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 86 typedef union { 87 struct { 88 uint32_t DATRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */ 89 uint32_t :31; /*!< bit: 1..31 Reserved */ 90 } bit; /*!< Structure used for bit access */ 91 uint32_t reg; /*!< Type used for register access */ 92 } TRNG_IDR_Type; 93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 94 95 #define TRNG_IDR_OFFSET 0x14 /**< \brief (TRNG_IDR offset) Interrupt Disable Register */ 96 #define TRNG_IDR_RESETVALUE _U_(0x00000000); /**< \brief (TRNG_IDR reset_value) Interrupt Disable Register */ 97 98 #define TRNG_IDR_DATRDY_Pos 0 /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ 99 #define TRNG_IDR_DATRDY (_U_(0x1) << TRNG_IDR_DATRDY_Pos) 100 #define TRNG_IDR_MASK _U_(0x00000001) /**< \brief (TRNG_IDR) MASK Register */ 101 102 /* -------- TRNG_IMR : (TRNG Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ 103 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 104 typedef union { 105 struct { 106 uint32_t DATRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */ 107 uint32_t :31; /*!< bit: 1..31 Reserved */ 108 } bit; /*!< Structure used for bit access */ 109 uint32_t reg; /*!< Type used for register access */ 110 } TRNG_IMR_Type; 111 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 112 113 #define TRNG_IMR_OFFSET 0x18 /**< \brief (TRNG_IMR offset) Interrupt Mask Register */ 114 #define TRNG_IMR_RESETVALUE _U_(0x00000000); /**< \brief (TRNG_IMR reset_value) Interrupt Mask Register */ 115 116 #define TRNG_IMR_DATRDY_Pos 0 /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ 117 #define TRNG_IMR_DATRDY (_U_(0x1) << TRNG_IMR_DATRDY_Pos) 118 #define TRNG_IMR_MASK _U_(0x00000001) /**< \brief (TRNG_IMR) MASK Register */ 119 120 /* -------- TRNG_ISR : (TRNG Offset: 0x1C) (R/ 32) Interrupt Status Register -------- */ 121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 122 typedef union { 123 struct { 124 uint32_t DATRDY:1; /*!< bit: 0 Data Ready Interrupt Status */ 125 uint32_t :31; /*!< bit: 1..31 Reserved */ 126 } bit; /*!< Structure used for bit access */ 127 uint32_t reg; /*!< Type used for register access */ 128 } TRNG_ISR_Type; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 #define TRNG_ISR_OFFSET 0x1C /**< \brief (TRNG_ISR offset) Interrupt Status Register */ 132 #define TRNG_ISR_RESETVALUE _U_(0x00000000); /**< \brief (TRNG_ISR reset_value) Interrupt Status Register */ 133 134 #define TRNG_ISR_DATRDY_Pos 0 /**< \brief (TRNG_ISR) Data Ready Interrupt Status */ 135 #define TRNG_ISR_DATRDY (_U_(0x1) << TRNG_ISR_DATRDY_Pos) 136 #define TRNG_ISR_MASK _U_(0x00000001) /**< \brief (TRNG_ISR) MASK Register */ 137 138 /* -------- TRNG_ODATA : (TRNG Offset: 0x50) (R/ 32) Output Data Register -------- */ 139 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 140 typedef union { 141 struct { 142 uint32_t ODATA:1; /*!< bit: 0 Output Data */ 143 uint32_t :31; /*!< bit: 1..31 Reserved */ 144 } bit; /*!< Structure used for bit access */ 145 uint32_t reg; /*!< Type used for register access */ 146 } TRNG_ODATA_Type; 147 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 148 149 #define TRNG_ODATA_OFFSET 0x50 /**< \brief (TRNG_ODATA offset) Output Data Register */ 150 #define TRNG_ODATA_RESETVALUE _U_(0x00000000); /**< \brief (TRNG_ODATA reset_value) Output Data Register */ 151 152 #define TRNG_ODATA_ODATA_Pos 0 /**< \brief (TRNG_ODATA) Output Data */ 153 #define TRNG_ODATA_ODATA (_U_(0x1) << TRNG_ODATA_ODATA_Pos) 154 #define TRNG_ODATA_MASK _U_(0x00000001) /**< \brief (TRNG_ODATA) MASK Register */ 155 156 /* -------- TRNG_VERSION : (TRNG Offset: 0xFC) (R/ 32) Version Register -------- */ 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 158 typedef union { 159 struct { 160 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 161 uint32_t :4; /*!< bit: 12..15 Reserved */ 162 uint32_t VARIANT:3; /*!< bit: 16..18 Variant Number */ 163 uint32_t :13; /*!< bit: 19..31 Reserved */ 164 } bit; /*!< Structure used for bit access */ 165 uint32_t reg; /*!< Type used for register access */ 166 } TRNG_VERSION_Type; 167 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 168 169 #define TRNG_VERSION_OFFSET 0xFC /**< \brief (TRNG_VERSION offset) Version Register */ 170 #define TRNG_VERSION_RESETVALUE _U_(0x00000103); /**< \brief (TRNG_VERSION reset_value) Version Register */ 171 172 #define TRNG_VERSION_VERSION_Pos 0 /**< \brief (TRNG_VERSION) Version Number */ 173 #define TRNG_VERSION_VERSION_Msk (_U_(0xFFF) << TRNG_VERSION_VERSION_Pos) 174 #define TRNG_VERSION_VERSION(value) (TRNG_VERSION_VERSION_Msk & ((value) << TRNG_VERSION_VERSION_Pos)) 175 #define TRNG_VERSION_VARIANT_Pos 16 /**< \brief (TRNG_VERSION) Variant Number */ 176 #define TRNG_VERSION_VARIANT_Msk (_U_(0x7) << TRNG_VERSION_VARIANT_Pos) 177 #define TRNG_VERSION_VARIANT(value) (TRNG_VERSION_VARIANT_Msk & ((value) << TRNG_VERSION_VARIANT_Pos)) 178 #define TRNG_VERSION_MASK _U_(0x00070FFF) /**< \brief (TRNG_VERSION) MASK Register */ 179 180 /** \brief TRNG hardware registers */ 181 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 182 typedef struct { 183 __O uint32_t TRNG_CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 184 RoReg8 Reserved1[0xC]; 185 __O uint32_t TRNG_IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable Register */ 186 __O uint32_t TRNG_IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable Register */ 187 __I uint32_t TRNG_IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask Register */ 188 __I uint32_t TRNG_ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status Register */ 189 RoReg8 Reserved2[0x30]; 190 __I uint32_t TRNG_ODATA; /**< \brief Offset: 0x50 (R/ 32) Output Data Register */ 191 RoReg8 Reserved3[0xA8]; 192 __I uint32_t TRNG_VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 193 } Trng; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 /*@}*/ 197 198 #endif /* _SAM4L_TRNG_COMPONENT_ */ 199
