1 /** 2 * \file 3 * 4 * \brief Component description for ADCIFE 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_ADCIFE_COMPONENT_ 30 #define _SAM4L_ADCIFE_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR ADCIFE */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_ADCIFE ADC controller interface */ 36 /*@{*/ 37 38 #define ADCIFE_I7569 39 #define REV_ADCIFE 0x100 40 41 /* -------- ADCIFE_CR : (ADCIFE Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SWRST:1; /*!< bit: 0 Software reset */ 46 uint32_t TSTOP:1; /*!< bit: 1 Internal timer stop bit */ 47 uint32_t TSTART:1; /*!< bit: 2 Internal timer start bit */ 48 uint32_t STRIG:1; /*!< bit: 3 Sequencer trigger */ 49 uint32_t REFBUFEN:1; /*!< bit: 4 Reference buffer enable */ 50 uint32_t REFBUFDIS:1; /*!< bit: 5 Reference buffer disable */ 51 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 52 uint32_t EN:1; /*!< bit: 8 ADCIFD enable */ 53 uint32_t DIS:1; /*!< bit: 9 ADCIFD disable */ 54 uint32_t BGREQEN:1; /*!< bit: 10 Bandgap buffer request enable */ 55 uint32_t BGREQDIS:1; /*!< bit: 11 Bandgap buffer request disable */ 56 uint32_t :20; /*!< bit: 12..31 Reserved */ 57 } bit; /*!< Structure used for bit access */ 58 uint32_t reg; /*!< Type used for register access */ 59 } ADCIFE_CR_Type; 60 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 61 62 #define ADCIFE_CR_OFFSET 0x00 /**< \brief (ADCIFE_CR offset) Control Register */ 63 #define ADCIFE_CR_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_CR reset_value) Control Register */ 64 65 #define ADCIFE_CR_SWRST_Pos 0 /**< \brief (ADCIFE_CR) Software reset */ 66 #define ADCIFE_CR_SWRST (_U_(0x1) << ADCIFE_CR_SWRST_Pos) 67 #define ADCIFE_CR_TSTOP_Pos 1 /**< \brief (ADCIFE_CR) Internal timer stop bit */ 68 #define ADCIFE_CR_TSTOP (_U_(0x1) << ADCIFE_CR_TSTOP_Pos) 69 #define ADCIFE_CR_TSTART_Pos 2 /**< \brief (ADCIFE_CR) Internal timer start bit */ 70 #define ADCIFE_CR_TSTART (_U_(0x1) << ADCIFE_CR_TSTART_Pos) 71 #define ADCIFE_CR_STRIG_Pos 3 /**< \brief (ADCIFE_CR) Sequencer trigger */ 72 #define ADCIFE_CR_STRIG (_U_(0x1) << ADCIFE_CR_STRIG_Pos) 73 #define ADCIFE_CR_REFBUFEN_Pos 4 /**< \brief (ADCIFE_CR) Reference buffer enable */ 74 #define ADCIFE_CR_REFBUFEN (_U_(0x1) << ADCIFE_CR_REFBUFEN_Pos) 75 #define ADCIFE_CR_REFBUFDIS_Pos 5 /**< \brief (ADCIFE_CR) Reference buffer disable */ 76 #define ADCIFE_CR_REFBUFDIS (_U_(0x1) << ADCIFE_CR_REFBUFDIS_Pos) 77 #define ADCIFE_CR_EN_Pos 8 /**< \brief (ADCIFE_CR) ADCIFD enable */ 78 #define ADCIFE_CR_EN (_U_(0x1) << ADCIFE_CR_EN_Pos) 79 #define ADCIFE_CR_DIS_Pos 9 /**< \brief (ADCIFE_CR) ADCIFD disable */ 80 #define ADCIFE_CR_DIS (_U_(0x1) << ADCIFE_CR_DIS_Pos) 81 #define ADCIFE_CR_BGREQEN_Pos 10 /**< \brief (ADCIFE_CR) Bandgap buffer request enable */ 82 #define ADCIFE_CR_BGREQEN (_U_(0x1) << ADCIFE_CR_BGREQEN_Pos) 83 #define ADCIFE_CR_BGREQDIS_Pos 11 /**< \brief (ADCIFE_CR) Bandgap buffer request disable */ 84 #define ADCIFE_CR_BGREQDIS (_U_(0x1) << ADCIFE_CR_BGREQDIS_Pos) 85 #define ADCIFE_CR_MASK _U_(0x00000F3F) /**< \brief (ADCIFE_CR) MASK Register */ 86 87 /* -------- ADCIFE_CFG : (ADCIFE Offset: 0x04) (R/W 32) Configuration Register -------- */ 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 89 typedef union { 90 struct { 91 uint32_t :1; /*!< bit: 0 Reserved */ 92 uint32_t REFSEL:3; /*!< bit: 1.. 3 ADC Reference Selection */ 93 uint32_t SPEED:2; /*!< bit: 4.. 5 ADC current reduction */ 94 uint32_t CLKSEL:1; /*!< bit: 6 Clock Selection for sequencer/ADC cell */ 95 uint32_t :1; /*!< bit: 7 Reserved */ 96 uint32_t PRESCAL:3; /*!< bit: 8..10 Prescaler Rate Selection */ 97 uint32_t :21; /*!< bit: 11..31 Reserved */ 98 } bit; /*!< Structure used for bit access */ 99 uint32_t reg; /*!< Type used for register access */ 100 } ADCIFE_CFG_Type; 101 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 #define ADCIFE_CFG_OFFSET 0x04 /**< \brief (ADCIFE_CFG offset) Configuration Register */ 104 #define ADCIFE_CFG_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_CFG reset_value) Configuration Register */ 105 106 #define ADCIFE_CFG_REFSEL_Pos 1 /**< \brief (ADCIFE_CFG) ADC Reference Selection */ 107 #define ADCIFE_CFG_REFSEL_Msk (_U_(0x7) << ADCIFE_CFG_REFSEL_Pos) 108 #define ADCIFE_CFG_REFSEL(value) (ADCIFE_CFG_REFSEL_Msk & ((value) << ADCIFE_CFG_REFSEL_Pos)) 109 #define ADCIFE_CFG_SPEED_Pos 4 /**< \brief (ADCIFE_CFG) ADC current reduction */ 110 #define ADCIFE_CFG_SPEED_Msk (_U_(0x3) << ADCIFE_CFG_SPEED_Pos) 111 #define ADCIFE_CFG_SPEED(value) (ADCIFE_CFG_SPEED_Msk & ((value) << ADCIFE_CFG_SPEED_Pos)) 112 #define ADCIFE_CFG_CLKSEL_Pos 6 /**< \brief (ADCIFE_CFG) Clock Selection for sequencer/ADC cell */ 113 #define ADCIFE_CFG_CLKSEL (_U_(0x1) << ADCIFE_CFG_CLKSEL_Pos) 114 #define ADCIFE_CFG_PRESCAL_Pos 8 /**< \brief (ADCIFE_CFG) Prescaler Rate Selection */ 115 #define ADCIFE_CFG_PRESCAL_Msk (_U_(0x7) << ADCIFE_CFG_PRESCAL_Pos) 116 #define ADCIFE_CFG_PRESCAL(value) (ADCIFE_CFG_PRESCAL_Msk & ((value) << ADCIFE_CFG_PRESCAL_Pos)) 117 #define ADCIFE_CFG_MASK _U_(0x0000077E) /**< \brief (ADCIFE_CFG) MASK Register */ 118 119 /* -------- ADCIFE_SR : (ADCIFE Offset: 0x08) (R/ 32) Status Register -------- */ 120 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 121 typedef union { 122 struct { 123 uint32_t SEOC:1; /*!< bit: 0 Sequencer end of conversion */ 124 uint32_t LOVR:1; /*!< bit: 1 Sequencer last converted value overrun */ 125 uint32_t WM:1; /*!< bit: 2 Window monitor */ 126 uint32_t SMTRG:1; /*!< bit: 3 Sequencer missed trigger event */ 127 uint32_t SUTD:1; /*!< bit: 4 Start-up time done */ 128 uint32_t TTO:1; /*!< bit: 5 Timer time-out */ 129 uint32_t :18; /*!< bit: 6..23 Reserved */ 130 uint32_t EN:1; /*!< bit: 24 Enable Status */ 131 uint32_t TBUSY:1; /*!< bit: 25 Timer busy */ 132 uint32_t SBUSY:1; /*!< bit: 26 Sequencer busy */ 133 uint32_t CBUSY:1; /*!< bit: 27 Conversion busy */ 134 uint32_t REFBUF:1; /*!< bit: 28 Reference buffer status */ 135 uint32_t :3; /*!< bit: 29..31 Reserved */ 136 } bit; /*!< Structure used for bit access */ 137 uint32_t reg; /*!< Type used for register access */ 138 } ADCIFE_SR_Type; 139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #define ADCIFE_SR_OFFSET 0x08 /**< \brief (ADCIFE_SR offset) Status Register */ 142 #define ADCIFE_SR_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_SR reset_value) Status Register */ 143 144 #define ADCIFE_SR_SEOC_Pos 0 /**< \brief (ADCIFE_SR) Sequencer end of conversion */ 145 #define ADCIFE_SR_SEOC (_U_(0x1) << ADCIFE_SR_SEOC_Pos) 146 #define ADCIFE_SR_LOVR_Pos 1 /**< \brief (ADCIFE_SR) Sequencer last converted value overrun */ 147 #define ADCIFE_SR_LOVR (_U_(0x1) << ADCIFE_SR_LOVR_Pos) 148 #define ADCIFE_SR_WM_Pos 2 /**< \brief (ADCIFE_SR) Window monitor */ 149 #define ADCIFE_SR_WM (_U_(0x1) << ADCIFE_SR_WM_Pos) 150 #define ADCIFE_SR_SMTRG_Pos 3 /**< \brief (ADCIFE_SR) Sequencer missed trigger event */ 151 #define ADCIFE_SR_SMTRG (_U_(0x1) << ADCIFE_SR_SMTRG_Pos) 152 #define ADCIFE_SR_SUTD_Pos 4 /**< \brief (ADCIFE_SR) Start-up time done */ 153 #define ADCIFE_SR_SUTD (_U_(0x1) << ADCIFE_SR_SUTD_Pos) 154 #define ADCIFE_SR_TTO_Pos 5 /**< \brief (ADCIFE_SR) Timer time-out */ 155 #define ADCIFE_SR_TTO (_U_(0x1) << ADCIFE_SR_TTO_Pos) 156 #define ADCIFE_SR_EN_Pos 24 /**< \brief (ADCIFE_SR) Enable Status */ 157 #define ADCIFE_SR_EN (_U_(0x1) << ADCIFE_SR_EN_Pos) 158 #define ADCIFE_SR_TBUSY_Pos 25 /**< \brief (ADCIFE_SR) Timer busy */ 159 #define ADCIFE_SR_TBUSY (_U_(0x1) << ADCIFE_SR_TBUSY_Pos) 160 #define ADCIFE_SR_SBUSY_Pos 26 /**< \brief (ADCIFE_SR) Sequencer busy */ 161 #define ADCIFE_SR_SBUSY (_U_(0x1) << ADCIFE_SR_SBUSY_Pos) 162 #define ADCIFE_SR_CBUSY_Pos 27 /**< \brief (ADCIFE_SR) Conversion busy */ 163 #define ADCIFE_SR_CBUSY (_U_(0x1) << ADCIFE_SR_CBUSY_Pos) 164 #define ADCIFE_SR_REFBUF_Pos 28 /**< \brief (ADCIFE_SR) Reference buffer status */ 165 #define ADCIFE_SR_REFBUF (_U_(0x1) << ADCIFE_SR_REFBUF_Pos) 166 #define ADCIFE_SR_MASK _U_(0x1F00003F) /**< \brief (ADCIFE_SR) MASK Register */ 167 168 /* -------- ADCIFE_SCR : (ADCIFE Offset: 0x0C) ( /W 32) Status Clear Register -------- */ 169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 170 typedef union { 171 struct { 172 uint32_t SEOC:1; /*!< bit: 0 Sequencer end of conversion */ 173 uint32_t LOVR:1; /*!< bit: 1 Sequencer last converted value overrun */ 174 uint32_t WM:1; /*!< bit: 2 Window monitor */ 175 uint32_t SMTRG:1; /*!< bit: 3 Sequencer missed trigger event */ 176 uint32_t SUTD:1; /*!< bit: 4 Start-up time done */ 177 uint32_t TTO:1; /*!< bit: 5 Timer time-out */ 178 uint32_t :26; /*!< bit: 6..31 Reserved */ 179 } bit; /*!< Structure used for bit access */ 180 uint32_t reg; /*!< Type used for register access */ 181 } ADCIFE_SCR_Type; 182 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 183 184 #define ADCIFE_SCR_OFFSET 0x0C /**< \brief (ADCIFE_SCR offset) Status Clear Register */ 185 #define ADCIFE_SCR_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_SCR reset_value) Status Clear Register */ 186 187 #define ADCIFE_SCR_SEOC_Pos 0 /**< \brief (ADCIFE_SCR) Sequencer end of conversion */ 188 #define ADCIFE_SCR_SEOC (_U_(0x1) << ADCIFE_SCR_SEOC_Pos) 189 #define ADCIFE_SCR_LOVR_Pos 1 /**< \brief (ADCIFE_SCR) Sequencer last converted value overrun */ 190 #define ADCIFE_SCR_LOVR (_U_(0x1) << ADCIFE_SCR_LOVR_Pos) 191 #define ADCIFE_SCR_WM_Pos 2 /**< \brief (ADCIFE_SCR) Window monitor */ 192 #define ADCIFE_SCR_WM (_U_(0x1) << ADCIFE_SCR_WM_Pos) 193 #define ADCIFE_SCR_SMTRG_Pos 3 /**< \brief (ADCIFE_SCR) Sequencer missed trigger event */ 194 #define ADCIFE_SCR_SMTRG (_U_(0x1) << ADCIFE_SCR_SMTRG_Pos) 195 #define ADCIFE_SCR_SUTD_Pos 4 /**< \brief (ADCIFE_SCR) Start-up time done */ 196 #define ADCIFE_SCR_SUTD (_U_(0x1) << ADCIFE_SCR_SUTD_Pos) 197 #define ADCIFE_SCR_TTO_Pos 5 /**< \brief (ADCIFE_SCR) Timer time-out */ 198 #define ADCIFE_SCR_TTO (_U_(0x1) << ADCIFE_SCR_TTO_Pos) 199 #define ADCIFE_SCR_MASK _U_(0x0000003F) /**< \brief (ADCIFE_SCR) MASK Register */ 200 201 /* -------- ADCIFE_RTS : (ADCIFE Offset: 0x10) (R/W 32) Resistive Touch Screen Register -------- */ 202 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 203 typedef union { 204 uint32_t reg; /*!< Type used for register access */ 205 } ADCIFE_RTS_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 #define ADCIFE_RTS_OFFSET 0x10 /**< \brief (ADCIFE_RTS offset) Resistive Touch Screen Register */ 209 #define ADCIFE_RTS_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_RTS reset_value) Resistive Touch Screen Register */ 210 211 #define ADCIFE_RTS_MASK _U_(0x00000000) /**< \brief (ADCIFE_RTS) MASK Register */ 212 213 /* -------- ADCIFE_SEQCFG : (ADCIFE Offset: 0x14) (R/W 32) Sequencer Configuration Register -------- */ 214 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 215 typedef union { 216 struct { 217 uint32_t HWLA:1; /*!< bit: 0 Half word left adjust */ 218 uint32_t :1; /*!< bit: 1 Reserved */ 219 uint32_t BIPOLAR:1; /*!< bit: 2 Bipolar Mode */ 220 uint32_t :1; /*!< bit: 3 Reserved */ 221 uint32_t GAIN:3; /*!< bit: 4.. 6 Gain factor */ 222 uint32_t GCOMP:1; /*!< bit: 7 Gain Compensation */ 223 uint32_t TRGSEL:3; /*!< bit: 8..10 Trigger selection */ 224 uint32_t :1; /*!< bit: 11 Reserved */ 225 uint32_t RES:1; /*!< bit: 12 Resolution */ 226 uint32_t :1; /*!< bit: 13 Reserved */ 227 uint32_t INTERNAL:2; /*!< bit: 14..15 Internal Voltage Source Selection */ 228 uint32_t MUXPOS:4; /*!< bit: 16..19 MUX selection on Positive ADC input channel */ 229 uint32_t MUXNEG:3; /*!< bit: 20..22 MUX selection on Negative ADC input channel */ 230 uint32_t :5; /*!< bit: 23..27 Reserved */ 231 uint32_t ZOOMRANGE:3; /*!< bit: 28..30 Zoom shift/unipolar reference source selection */ 232 uint32_t :1; /*!< bit: 31 Reserved */ 233 } bit; /*!< Structure used for bit access */ 234 uint32_t reg; /*!< Type used for register access */ 235 } ADCIFE_SEQCFG_Type; 236 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 237 238 #define ADCIFE_SEQCFG_OFFSET 0x14 /**< \brief (ADCIFE_SEQCFG offset) Sequencer Configuration Register */ 239 #define ADCIFE_SEQCFG_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_SEQCFG reset_value) Sequencer Configuration Register */ 240 241 #define ADCIFE_SEQCFG_HWLA_Pos 0 /**< \brief (ADCIFE_SEQCFG) Half word left adjust */ 242 #define ADCIFE_SEQCFG_HWLA (_U_(0x1) << ADCIFE_SEQCFG_HWLA_Pos) 243 #define ADCIFE_SEQCFG_BIPOLAR_Pos 2 /**< \brief (ADCIFE_SEQCFG) Bipolar Mode */ 244 #define ADCIFE_SEQCFG_BIPOLAR (_U_(0x1) << ADCIFE_SEQCFG_BIPOLAR_Pos) 245 #define ADCIFE_SEQCFG_GAIN_Pos 4 /**< \brief (ADCIFE_SEQCFG) Gain factor */ 246 #define ADCIFE_SEQCFG_GAIN_Msk (_U_(0x7) << ADCIFE_SEQCFG_GAIN_Pos) 247 #define ADCIFE_SEQCFG_GAIN(value) (ADCIFE_SEQCFG_GAIN_Msk & ((value) << ADCIFE_SEQCFG_GAIN_Pos)) 248 #define ADCIFE_SEQCFG_GCOMP_Pos 7 /**< \brief (ADCIFE_SEQCFG) Gain Compensation */ 249 #define ADCIFE_SEQCFG_GCOMP (_U_(0x1) << ADCIFE_SEQCFG_GCOMP_Pos) 250 #define ADCIFE_SEQCFG_TRGSEL_Pos 8 /**< \brief (ADCIFE_SEQCFG) Trigger selection */ 251 #define ADCIFE_SEQCFG_TRGSEL_Msk (_U_(0x7) << ADCIFE_SEQCFG_TRGSEL_Pos) 252 #define ADCIFE_SEQCFG_TRGSEL(value) (ADCIFE_SEQCFG_TRGSEL_Msk & ((value) << ADCIFE_SEQCFG_TRGSEL_Pos)) 253 #define ADCIFE_SEQCFG_RES_Pos 12 /**< \brief (ADCIFE_SEQCFG) Resolution */ 254 #define ADCIFE_SEQCFG_RES (_U_(0x1) << ADCIFE_SEQCFG_RES_Pos) 255 #define ADCIFE_SEQCFG_INTERNAL_Pos 14 /**< \brief (ADCIFE_SEQCFG) Internal Voltage Source Selection */ 256 #define ADCIFE_SEQCFG_INTERNAL_Msk (_U_(0x3) << ADCIFE_SEQCFG_INTERNAL_Pos) 257 #define ADCIFE_SEQCFG_INTERNAL(value) (ADCIFE_SEQCFG_INTERNAL_Msk & ((value) << ADCIFE_SEQCFG_INTERNAL_Pos)) 258 #define ADCIFE_SEQCFG_MUXPOS_Pos 16 /**< \brief (ADCIFE_SEQCFG) MUX selection on Positive ADC input channel */ 259 #define ADCIFE_SEQCFG_MUXPOS_Msk (_U_(0xF) << ADCIFE_SEQCFG_MUXPOS_Pos) 260 #define ADCIFE_SEQCFG_MUXPOS(value) (ADCIFE_SEQCFG_MUXPOS_Msk & ((value) << ADCIFE_SEQCFG_MUXPOS_Pos)) 261 #define ADCIFE_SEQCFG_MUXNEG_Pos 20 /**< \brief (ADCIFE_SEQCFG) MUX selection on Negative ADC input channel */ 262 #define ADCIFE_SEQCFG_MUXNEG_Msk (_U_(0x7) << ADCIFE_SEQCFG_MUXNEG_Pos) 263 #define ADCIFE_SEQCFG_MUXNEG(value) (ADCIFE_SEQCFG_MUXNEG_Msk & ((value) << ADCIFE_SEQCFG_MUXNEG_Pos)) 264 #define ADCIFE_SEQCFG_ZOOMRANGE_Pos 28 /**< \brief (ADCIFE_SEQCFG) Zoom shift/unipolar reference source selection */ 265 #define ADCIFE_SEQCFG_ZOOMRANGE_Msk (_U_(0x7) << ADCIFE_SEQCFG_ZOOMRANGE_Pos) 266 #define ADCIFE_SEQCFG_ZOOMRANGE(value) (ADCIFE_SEQCFG_ZOOMRANGE_Msk & ((value) << ADCIFE_SEQCFG_ZOOMRANGE_Pos)) 267 #define ADCIFE_SEQCFG_MASK _U_(0x707FD7F5) /**< \brief (ADCIFE_SEQCFG) MASK Register */ 268 269 /* -------- ADCIFE_CDMA : (ADCIFE Offset: 0x18) ( /W 32) Configuration Direct Memory Access Register -------- */ 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 271 typedef union { 272 struct { // FIRST_DMA_WORD mode 273 uint32_t HWLA:1; /*!< bit: 0 Half word left adjust */ 274 uint32_t :1; /*!< bit: 1 Reserved */ 275 uint32_t BIPOLAR:1; /*!< bit: 2 Bipolar Mode */ 276 uint32_t STRIG:1; /*!< bit: 3 Sequencer Trigger Event */ 277 uint32_t GAIN:3; /*!< bit: 4.. 6 Gain factor */ 278 uint32_t GCOMP:1; /*!< bit: 7 Gain Compensation */ 279 uint32_t ENSTUP:1; /*!< bit: 8 Enable Start-Up Time */ 280 uint32_t :3; /*!< bit: 9..11 Reserved */ 281 uint32_t RES:1; /*!< bit: 12 Resolution */ 282 uint32_t TSS:1; /*!< bit: 13 Internal timer start or stop bit */ 283 uint32_t INTERNAL:2; /*!< bit: 14..15 Internal Voltage Source Selection */ 284 uint32_t MUXPOS:4; /*!< bit: 16..19 MUX selection on Positive ADC input channel */ 285 uint32_t MUXNEG:3; /*!< bit: 20..22 MUX selection on Negative ADC input channel */ 286 uint32_t :5; /*!< bit: 23..27 Reserved */ 287 uint32_t ZOOMRANGE:3; /*!< bit: 28..30 Zoom shift/unipolar reference source selection */ 288 uint32_t DW:1; /*!< bit: 31 Double Word transmitting */ 289 } FIRST_DMA_WORD; /*!< Structure used for FIRST_DMA_WORD */ 290 struct { // SECOND_DMA_WORD mode 291 uint32_t LT:12; /*!< bit: 0..11 Low Threshold */ 292 uint32_t WM:3; /*!< bit: 12..14 Window Monitor Mode */ 293 uint32_t :1; /*!< bit: 15 Reserved */ 294 uint32_t HT:12; /*!< bit: 16..27 High Threshold */ 295 uint32_t :3; /*!< bit: 28..30 Reserved */ 296 uint32_t DW:1; /*!< bit: 31 Double Word transmitting */ 297 } SECOND_DMA_WORD; /*!< Structure used for SECOND_DMA_WORD */ 298 uint32_t reg; /*!< Type used for register access */ 299 } ADCIFE_CDMA_Type; 300 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 301 302 #define ADCIFE_CDMA_OFFSET 0x18 /**< \brief (ADCIFE_CDMA offset) Configuration Direct Memory Access Register */ 303 #define ADCIFE_CDMA_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_CDMA reset_value) Configuration Direct Memory Access Register */ 304 305 // FIRST_DMA_WORD mode 306 #define ADCIFE_CDMA_FIRST_DMA_WORD_HWLA_Pos 0 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Half word left adjust */ 307 #define ADCIFE_CDMA_FIRST_DMA_WORD_HWLA (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_HWLA_Pos) 308 #define ADCIFE_CDMA_FIRST_DMA_WORD_BIPOLAR_Pos 2 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Bipolar Mode */ 309 #define ADCIFE_CDMA_FIRST_DMA_WORD_BIPOLAR (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_BIPOLAR_Pos) 310 #define ADCIFE_CDMA_FIRST_DMA_WORD_STRIG_Pos 3 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Sequencer Trigger Event */ 311 #define ADCIFE_CDMA_FIRST_DMA_WORD_STRIG (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_STRIG_Pos) 312 #define ADCIFE_CDMA_FIRST_DMA_WORD_GAIN_Pos 4 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Gain factor */ 313 #define ADCIFE_CDMA_FIRST_DMA_WORD_GAIN_Msk (_U_(0x7) << ADCIFE_CDMA_FIRST_DMA_WORD_GAIN_Pos) 314 #define ADCIFE_CDMA_FIRST_DMA_WORD_GAIN(value) (ADCIFE_CDMA_FIRST_DMA_WORD_GAIN_Msk & ((value) << ADCIFE_CDMA_FIRST_DMA_WORD_GAIN_Pos)) 315 #define ADCIFE_CDMA_FIRST_DMA_WORD_GCOMP_Pos 7 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Gain Compensation */ 316 #define ADCIFE_CDMA_FIRST_DMA_WORD_GCOMP (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_GCOMP_Pos) 317 #define ADCIFE_CDMA_FIRST_DMA_WORD_ENSTUP_Pos 8 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Enable Start-Up Time */ 318 #define ADCIFE_CDMA_FIRST_DMA_WORD_ENSTUP (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_ENSTUP_Pos) 319 #define ADCIFE_CDMA_FIRST_DMA_WORD_RES_Pos 12 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Resolution */ 320 #define ADCIFE_CDMA_FIRST_DMA_WORD_RES (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_RES_Pos) 321 #define ADCIFE_CDMA_FIRST_DMA_WORD_TSS_Pos 13 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Internal timer start or stop bit */ 322 #define ADCIFE_CDMA_FIRST_DMA_WORD_TSS (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_TSS_Pos) 323 #define ADCIFE_CDMA_FIRST_DMA_WORD_INTERNAL_Pos 14 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Internal Voltage Source Selection */ 324 #define ADCIFE_CDMA_FIRST_DMA_WORD_INTERNAL_Msk (_U_(0x3) << ADCIFE_CDMA_FIRST_DMA_WORD_INTERNAL_Pos) 325 #define ADCIFE_CDMA_FIRST_DMA_WORD_INTERNAL(value) (ADCIFE_CDMA_FIRST_DMA_WORD_INTERNAL_Msk & ((value) << ADCIFE_CDMA_FIRST_DMA_WORD_INTERNAL_Pos)) 326 #define ADCIFE_CDMA_FIRST_DMA_WORD_MUXPOS_Pos 16 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) MUX selection on Positive ADC input channel */ 327 #define ADCIFE_CDMA_FIRST_DMA_WORD_MUXPOS_Msk (_U_(0xF) << ADCIFE_CDMA_FIRST_DMA_WORD_MUXPOS_Pos) 328 #define ADCIFE_CDMA_FIRST_DMA_WORD_MUXPOS(value) (ADCIFE_CDMA_FIRST_DMA_WORD_MUXPOS_Msk & ((value) << ADCIFE_CDMA_FIRST_DMA_WORD_MUXPOS_Pos)) 329 #define ADCIFE_CDMA_FIRST_DMA_WORD_MUXNEG_Pos 20 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) MUX selection on Negative ADC input channel */ 330 #define ADCIFE_CDMA_FIRST_DMA_WORD_MUXNEG_Msk (_U_(0x7) << ADCIFE_CDMA_FIRST_DMA_WORD_MUXNEG_Pos) 331 #define ADCIFE_CDMA_FIRST_DMA_WORD_MUXNEG(value) (ADCIFE_CDMA_FIRST_DMA_WORD_MUXNEG_Msk & ((value) << ADCIFE_CDMA_FIRST_DMA_WORD_MUXNEG_Pos)) 332 #define ADCIFE_CDMA_FIRST_DMA_WORD_ZOOMRANGE_Pos 28 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Zoom shift/unipolar reference source selection */ 333 #define ADCIFE_CDMA_FIRST_DMA_WORD_ZOOMRANGE_Msk (_U_(0x7) << ADCIFE_CDMA_FIRST_DMA_WORD_ZOOMRANGE_Pos) 334 #define ADCIFE_CDMA_FIRST_DMA_WORD_ZOOMRANGE(value) (ADCIFE_CDMA_FIRST_DMA_WORD_ZOOMRANGE_Msk & ((value) << ADCIFE_CDMA_FIRST_DMA_WORD_ZOOMRANGE_Pos)) 335 #define ADCIFE_CDMA_FIRST_DMA_WORD_DW_Pos 31 /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) Double Word transmitting */ 336 #define ADCIFE_CDMA_FIRST_DMA_WORD_DW (_U_(0x1) << ADCIFE_CDMA_FIRST_DMA_WORD_DW_Pos) 337 #define ADCIFE_CDMA_FIRST_DMA_WORD_MASK _U_(0xF07FF1FD) /**< \brief (ADCIFE_CDMA_FIRST_DMA_WORD) MASK Register */ 338 339 // SECOND_DMA_WORD mode 340 #define ADCIFE_CDMA_SECOND_DMA_WORD_LT_Pos 0 /**< \brief (ADCIFE_CDMA_SECOND_DMA_WORD) Low Threshold */ 341 #define ADCIFE_CDMA_SECOND_DMA_WORD_LT_Msk (_U_(0xFFF) << ADCIFE_CDMA_SECOND_DMA_WORD_LT_Pos) 342 #define ADCIFE_CDMA_SECOND_DMA_WORD_LT(value) (ADCIFE_CDMA_SECOND_DMA_WORD_LT_Msk & ((value) << ADCIFE_CDMA_SECOND_DMA_WORD_LT_Pos)) 343 #define ADCIFE_CDMA_SECOND_DMA_WORD_WM_Pos 12 /**< \brief (ADCIFE_CDMA_SECOND_DMA_WORD) Window Monitor Mode */ 344 #define ADCIFE_CDMA_SECOND_DMA_WORD_WM_Msk (_U_(0x7) << ADCIFE_CDMA_SECOND_DMA_WORD_WM_Pos) 345 #define ADCIFE_CDMA_SECOND_DMA_WORD_WM(value) (ADCIFE_CDMA_SECOND_DMA_WORD_WM_Msk & ((value) << ADCIFE_CDMA_SECOND_DMA_WORD_WM_Pos)) 346 #define ADCIFE_CDMA_SECOND_DMA_WORD_HT_Pos 16 /**< \brief (ADCIFE_CDMA_SECOND_DMA_WORD) High Threshold */ 347 #define ADCIFE_CDMA_SECOND_DMA_WORD_HT_Msk (_U_(0xFFF) << ADCIFE_CDMA_SECOND_DMA_WORD_HT_Pos) 348 #define ADCIFE_CDMA_SECOND_DMA_WORD_HT(value) (ADCIFE_CDMA_SECOND_DMA_WORD_HT_Msk & ((value) << ADCIFE_CDMA_SECOND_DMA_WORD_HT_Pos)) 349 #define ADCIFE_CDMA_SECOND_DMA_WORD_DW_Pos 31 /**< \brief (ADCIFE_CDMA_SECOND_DMA_WORD) Double Word transmitting */ 350 #define ADCIFE_CDMA_SECOND_DMA_WORD_DW (_U_(0x1) << ADCIFE_CDMA_SECOND_DMA_WORD_DW_Pos) 351 #define ADCIFE_CDMA_SECOND_DMA_WORD_MASK _U_(0x8FFF7FFF) /**< \brief (ADCIFE_CDMA_SECOND_DMA_WORD) MASK Register */ 352 353 // Any mode 354 #define ADCIFE_CDMA_HWLA_Pos 0 /**< \brief (ADCIFE_CDMA) Half word left adjust */ 355 #define ADCIFE_CDMA_HWLA (_U_(0x1) << ADCIFE_CDMA_HWLA_Pos) 356 #define ADCIFE_CDMA_LT_Pos 0 /**< \brief (ADCIFE_CDMA) Low Threshold */ 357 #define ADCIFE_CDMA_LT_Msk (_U_(0xFFF) << ADCIFE_CDMA_LT_Pos) 358 #define ADCIFE_CDMA_LT(value) (ADCIFE_CDMA_LT_Msk & ((value) << ADCIFE_CDMA_LT_Pos)) 359 #define ADCIFE_CDMA_BIPOLAR_Pos 2 /**< \brief (ADCIFE_CDMA) Bipolar Mode */ 360 #define ADCIFE_CDMA_BIPOLAR (_U_(0x1) << ADCIFE_CDMA_BIPOLAR_Pos) 361 #define ADCIFE_CDMA_STRIG_Pos 3 /**< \brief (ADCIFE_CDMA) Sequencer Trigger Event */ 362 #define ADCIFE_CDMA_STRIG (_U_(0x1) << ADCIFE_CDMA_STRIG_Pos) 363 #define ADCIFE_CDMA_GAIN_Pos 4 /**< \brief (ADCIFE_CDMA) Gain factor */ 364 #define ADCIFE_CDMA_GAIN_Msk (_U_(0x7) << ADCIFE_CDMA_GAIN_Pos) 365 #define ADCIFE_CDMA_GAIN(value) (ADCIFE_CDMA_GAIN_Msk & ((value) << ADCIFE_CDMA_GAIN_Pos)) 366 #define ADCIFE_CDMA_GCOMP_Pos 7 /**< \brief (ADCIFE_CDMA) Gain Compensation */ 367 #define ADCIFE_CDMA_GCOMP (_U_(0x1) << ADCIFE_CDMA_GCOMP_Pos) 368 #define ADCIFE_CDMA_ENSTUP_Pos 8 /**< \brief (ADCIFE_CDMA) Enable Start-Up Time */ 369 #define ADCIFE_CDMA_ENSTUP (_U_(0x1) << ADCIFE_CDMA_ENSTUP_Pos) 370 #define ADCIFE_CDMA_RES_Pos 12 /**< \brief (ADCIFE_CDMA) Resolution */ 371 #define ADCIFE_CDMA_RES (_U_(0x1) << ADCIFE_CDMA_RES_Pos) 372 #define ADCIFE_CDMA_WM_Pos 12 /**< \brief (ADCIFE_CDMA) Window Monitor Mode */ 373 #define ADCIFE_CDMA_WM_Msk (_U_(0x7) << ADCIFE_CDMA_WM_Pos) 374 #define ADCIFE_CDMA_WM(value) (ADCIFE_CDMA_WM_Msk & ((value) << ADCIFE_CDMA_WM_Pos)) 375 #define ADCIFE_CDMA_TSS_Pos 13 /**< \brief (ADCIFE_CDMA) Internal timer start or stop bit */ 376 #define ADCIFE_CDMA_TSS (_U_(0x1) << ADCIFE_CDMA_TSS_Pos) 377 #define ADCIFE_CDMA_INTERNAL_Pos 14 /**< \brief (ADCIFE_CDMA) Internal Voltage Source Selection */ 378 #define ADCIFE_CDMA_INTERNAL_Msk (_U_(0x3) << ADCIFE_CDMA_INTERNAL_Pos) 379 #define ADCIFE_CDMA_INTERNAL(value) (ADCIFE_CDMA_INTERNAL_Msk & ((value) << ADCIFE_CDMA_INTERNAL_Pos)) 380 #define ADCIFE_CDMA_MUXPOS_Pos 16 /**< \brief (ADCIFE_CDMA) MUX selection on Positive ADC input channel */ 381 #define ADCIFE_CDMA_MUXPOS_Msk (_U_(0xF) << ADCIFE_CDMA_MUXPOS_Pos) 382 #define ADCIFE_CDMA_MUXPOS(value) (ADCIFE_CDMA_MUXPOS_Msk & ((value) << ADCIFE_CDMA_MUXPOS_Pos)) 383 #define ADCIFE_CDMA_HT_Pos 16 /**< \brief (ADCIFE_CDMA) High Threshold */ 384 #define ADCIFE_CDMA_HT_Msk (_U_(0xFFF) << ADCIFE_CDMA_HT_Pos) 385 #define ADCIFE_CDMA_HT(value) (ADCIFE_CDMA_HT_Msk & ((value) << ADCIFE_CDMA_HT_Pos)) 386 #define ADCIFE_CDMA_MUXNEG_Pos 20 /**< \brief (ADCIFE_CDMA) MUX selection on Negative ADC input channel */ 387 #define ADCIFE_CDMA_MUXNEG_Msk (_U_(0x7) << ADCIFE_CDMA_MUXNEG_Pos) 388 #define ADCIFE_CDMA_MUXNEG(value) (ADCIFE_CDMA_MUXNEG_Msk & ((value) << ADCIFE_CDMA_MUXNEG_Pos)) 389 #define ADCIFE_CDMA_ZOOMRANGE_Pos 28 /**< \brief (ADCIFE_CDMA) Zoom shift/unipolar reference source selection */ 390 #define ADCIFE_CDMA_ZOOMRANGE_Msk (_U_(0x7) << ADCIFE_CDMA_ZOOMRANGE_Pos) 391 #define ADCIFE_CDMA_ZOOMRANGE(value) (ADCIFE_CDMA_ZOOMRANGE_Msk & ((value) << ADCIFE_CDMA_ZOOMRANGE_Pos)) 392 #define ADCIFE_CDMA_DW_Pos 31 /**< \brief (ADCIFE_CDMA) Double Word transmitting */ 393 #define ADCIFE_CDMA_DW (_U_(0x1) << ADCIFE_CDMA_DW_Pos) 394 #define ADCIFE_CDMA_MASK _U_(0xFFFFFFFF) /**< \brief (ADCIFE_CDMA) MASK Register */ 395 396 /* -------- ADCIFE_TIM : (ADCIFE Offset: 0x1C) (R/W 32) Timing Configuration Register -------- */ 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 398 typedef union { 399 struct { 400 uint32_t STARTUP:5; /*!< bit: 0.. 4 Startup time */ 401 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 402 uint32_t ENSTUP:1; /*!< bit: 8 Enable Startup */ 403 uint32_t :23; /*!< bit: 9..31 Reserved */ 404 } bit; /*!< Structure used for bit access */ 405 uint32_t reg; /*!< Type used for register access */ 406 } ADCIFE_TIM_Type; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 #define ADCIFE_TIM_OFFSET 0x1C /**< \brief (ADCIFE_TIM offset) Timing Configuration Register */ 410 #define ADCIFE_TIM_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_TIM reset_value) Timing Configuration Register */ 411 412 #define ADCIFE_TIM_STARTUP_Pos 0 /**< \brief (ADCIFE_TIM) Startup time */ 413 #define ADCIFE_TIM_STARTUP_Msk (_U_(0x1F) << ADCIFE_TIM_STARTUP_Pos) 414 #define ADCIFE_TIM_STARTUP(value) (ADCIFE_TIM_STARTUP_Msk & ((value) << ADCIFE_TIM_STARTUP_Pos)) 415 #define ADCIFE_TIM_ENSTUP_Pos 8 /**< \brief (ADCIFE_TIM) Enable Startup */ 416 #define ADCIFE_TIM_ENSTUP (_U_(0x1) << ADCIFE_TIM_ENSTUP_Pos) 417 #define ADCIFE_TIM_MASK _U_(0x0000011F) /**< \brief (ADCIFE_TIM) MASK Register */ 418 419 /* -------- ADCIFE_ITIMER : (ADCIFE Offset: 0x20) (R/W 32) Internal Timer Register -------- */ 420 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 421 typedef union { 422 struct { 423 uint32_t ITMC:16; /*!< bit: 0..15 Internal timer max counter */ 424 uint32_t :16; /*!< bit: 16..31 Reserved */ 425 } bit; /*!< Structure used for bit access */ 426 uint32_t reg; /*!< Type used for register access */ 427 } ADCIFE_ITIMER_Type; 428 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 429 430 #define ADCIFE_ITIMER_OFFSET 0x20 /**< \brief (ADCIFE_ITIMER offset) Internal Timer Register */ 431 #define ADCIFE_ITIMER_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_ITIMER reset_value) Internal Timer Register */ 432 433 #define ADCIFE_ITIMER_ITMC_Pos 0 /**< \brief (ADCIFE_ITIMER) Internal timer max counter */ 434 #define ADCIFE_ITIMER_ITMC_Msk (_U_(0xFFFF) << ADCIFE_ITIMER_ITMC_Pos) 435 #define ADCIFE_ITIMER_ITMC(value) (ADCIFE_ITIMER_ITMC_Msk & ((value) << ADCIFE_ITIMER_ITMC_Pos)) 436 #define ADCIFE_ITIMER_MASK _U_(0x0000FFFF) /**< \brief (ADCIFE_ITIMER) MASK Register */ 437 438 /* -------- ADCIFE_WCFG : (ADCIFE Offset: 0x24) (R/W 32) Window Monitor Configuration Register -------- */ 439 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 440 typedef union { 441 struct { 442 uint32_t :12; /*!< bit: 0..11 Reserved */ 443 uint32_t WM:3; /*!< bit: 12..14 Window Monitor Mode */ 444 uint32_t :17; /*!< bit: 15..31 Reserved */ 445 } bit; /*!< Structure used for bit access */ 446 uint32_t reg; /*!< Type used for register access */ 447 } ADCIFE_WCFG_Type; 448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 449 450 #define ADCIFE_WCFG_OFFSET 0x24 /**< \brief (ADCIFE_WCFG offset) Window Monitor Configuration Register */ 451 #define ADCIFE_WCFG_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_WCFG reset_value) Window Monitor Configuration Register */ 452 453 #define ADCIFE_WCFG_WM_Pos 12 /**< \brief (ADCIFE_WCFG) Window Monitor Mode */ 454 #define ADCIFE_WCFG_WM_Msk (_U_(0x7) << ADCIFE_WCFG_WM_Pos) 455 #define ADCIFE_WCFG_WM(value) (ADCIFE_WCFG_WM_Msk & ((value) << ADCIFE_WCFG_WM_Pos)) 456 #define ADCIFE_WCFG_MASK _U_(0x00007000) /**< \brief (ADCIFE_WCFG) MASK Register */ 457 458 /* -------- ADCIFE_WTH : (ADCIFE Offset: 0x28) (R/W 32) Window Monitor Threshold Configuration Register -------- */ 459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 460 typedef union { 461 struct { 462 uint32_t LT:12; /*!< bit: 0..11 Low threshold */ 463 uint32_t :4; /*!< bit: 12..15 Reserved */ 464 uint32_t HT:12; /*!< bit: 16..27 High Threshold */ 465 uint32_t :4; /*!< bit: 28..31 Reserved */ 466 } bit; /*!< Structure used for bit access */ 467 uint32_t reg; /*!< Type used for register access */ 468 } ADCIFE_WTH_Type; 469 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 470 471 #define ADCIFE_WTH_OFFSET 0x28 /**< \brief (ADCIFE_WTH offset) Window Monitor Threshold Configuration Register */ 472 #define ADCIFE_WTH_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_WTH reset_value) Window Monitor Threshold Configuration Register */ 473 474 #define ADCIFE_WTH_LT_Pos 0 /**< \brief (ADCIFE_WTH) Low threshold */ 475 #define ADCIFE_WTH_LT_Msk (_U_(0xFFF) << ADCIFE_WTH_LT_Pos) 476 #define ADCIFE_WTH_LT(value) (ADCIFE_WTH_LT_Msk & ((value) << ADCIFE_WTH_LT_Pos)) 477 #define ADCIFE_WTH_HT_Pos 16 /**< \brief (ADCIFE_WTH) High Threshold */ 478 #define ADCIFE_WTH_HT_Msk (_U_(0xFFF) << ADCIFE_WTH_HT_Pos) 479 #define ADCIFE_WTH_HT(value) (ADCIFE_WTH_HT_Msk & ((value) << ADCIFE_WTH_HT_Pos)) 480 #define ADCIFE_WTH_MASK _U_(0x0FFF0FFF) /**< \brief (ADCIFE_WTH) MASK Register */ 481 482 /* -------- ADCIFE_LCV : (ADCIFE Offset: 0x2C) (R/ 32) Sequencer Last Converted Value Register -------- */ 483 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 484 typedef union { 485 struct { 486 uint32_t LCV:16; /*!< bit: 0..15 Last converted value */ 487 uint32_t LCPC:4; /*!< bit: 16..19 Last converted positive channel */ 488 uint32_t LCNC:3; /*!< bit: 20..22 Last converted negative channel */ 489 uint32_t :9; /*!< bit: 23..31 Reserved */ 490 } bit; /*!< Structure used for bit access */ 491 uint32_t reg; /*!< Type used for register access */ 492 } ADCIFE_LCV_Type; 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 494 495 #define ADCIFE_LCV_OFFSET 0x2C /**< \brief (ADCIFE_LCV offset) Sequencer Last Converted Value Register */ 496 #define ADCIFE_LCV_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_LCV reset_value) Sequencer Last Converted Value Register */ 497 498 #define ADCIFE_LCV_LCV_Pos 0 /**< \brief (ADCIFE_LCV) Last converted value */ 499 #define ADCIFE_LCV_LCV_Msk (_U_(0xFFFF) << ADCIFE_LCV_LCV_Pos) 500 #define ADCIFE_LCV_LCV(value) (ADCIFE_LCV_LCV_Msk & ((value) << ADCIFE_LCV_LCV_Pos)) 501 #define ADCIFE_LCV_LCPC_Pos 16 /**< \brief (ADCIFE_LCV) Last converted positive channel */ 502 #define ADCIFE_LCV_LCPC_Msk (_U_(0xF) << ADCIFE_LCV_LCPC_Pos) 503 #define ADCIFE_LCV_LCPC(value) (ADCIFE_LCV_LCPC_Msk & ((value) << ADCIFE_LCV_LCPC_Pos)) 504 #define ADCIFE_LCV_LCNC_Pos 20 /**< \brief (ADCIFE_LCV) Last converted negative channel */ 505 #define ADCIFE_LCV_LCNC_Msk (_U_(0x7) << ADCIFE_LCV_LCNC_Pos) 506 #define ADCIFE_LCV_LCNC(value) (ADCIFE_LCV_LCNC_Msk & ((value) << ADCIFE_LCV_LCNC_Pos)) 507 #define ADCIFE_LCV_MASK _U_(0x007FFFFF) /**< \brief (ADCIFE_LCV) MASK Register */ 508 509 /* -------- ADCIFE_IER : (ADCIFE Offset: 0x30) ( /W 32) Interrupt Enable Register -------- */ 510 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 511 typedef union { 512 struct { 513 uint32_t SEOC:1; /*!< bit: 0 Sequencer end of conversion Interrupt Enable */ 514 uint32_t LOVR:1; /*!< bit: 1 Sequencer last converted value overrun Interrupt Enable */ 515 uint32_t WM:1; /*!< bit: 2 Window monitor Interrupt Enable */ 516 uint32_t SMTRG:1; /*!< bit: 3 Sequencer missed trigger event Interrupt Enable */ 517 uint32_t :1; /*!< bit: 4 Reserved */ 518 uint32_t TTO:1; /*!< bit: 5 Timer time-out Interrupt Enable */ 519 uint32_t :26; /*!< bit: 6..31 Reserved */ 520 } bit; /*!< Structure used for bit access */ 521 uint32_t reg; /*!< Type used for register access */ 522 } ADCIFE_IER_Type; 523 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 524 525 #define ADCIFE_IER_OFFSET 0x30 /**< \brief (ADCIFE_IER offset) Interrupt Enable Register */ 526 #define ADCIFE_IER_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_IER reset_value) Interrupt Enable Register */ 527 528 #define ADCIFE_IER_SEOC_Pos 0 /**< \brief (ADCIFE_IER) Sequencer end of conversion Interrupt Enable */ 529 #define ADCIFE_IER_SEOC (_U_(0x1) << ADCIFE_IER_SEOC_Pos) 530 #define ADCIFE_IER_LOVR_Pos 1 /**< \brief (ADCIFE_IER) Sequencer last converted value overrun Interrupt Enable */ 531 #define ADCIFE_IER_LOVR (_U_(0x1) << ADCIFE_IER_LOVR_Pos) 532 #define ADCIFE_IER_WM_Pos 2 /**< \brief (ADCIFE_IER) Window monitor Interrupt Enable */ 533 #define ADCIFE_IER_WM (_U_(0x1) << ADCIFE_IER_WM_Pos) 534 #define ADCIFE_IER_SMTRG_Pos 3 /**< \brief (ADCIFE_IER) Sequencer missed trigger event Interrupt Enable */ 535 #define ADCIFE_IER_SMTRG (_U_(0x1) << ADCIFE_IER_SMTRG_Pos) 536 #define ADCIFE_IER_TTO_Pos 5 /**< \brief (ADCIFE_IER) Timer time-out Interrupt Enable */ 537 #define ADCIFE_IER_TTO (_U_(0x1) << ADCIFE_IER_TTO_Pos) 538 #define ADCIFE_IER_MASK _U_(0x0000002F) /**< \brief (ADCIFE_IER) MASK Register */ 539 540 /* -------- ADCIFE_IDR : (ADCIFE Offset: 0x34) ( /W 32) Interrupt Disable Register -------- */ 541 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 542 typedef union { 543 struct { 544 uint32_t SEOC:1; /*!< bit: 0 Sequencer end of conversion Interrupt Disable */ 545 uint32_t LOVR:1; /*!< bit: 1 Sequencer last converted value overrun Interrupt Disable */ 546 uint32_t WM:1; /*!< bit: 2 Window monitor Interrupt Disable */ 547 uint32_t SMTRG:1; /*!< bit: 3 Sequencer missed trigger event Interrupt Disable */ 548 uint32_t :1; /*!< bit: 4 Reserved */ 549 uint32_t TTO:1; /*!< bit: 5 Timer time-out Interrupt Disable */ 550 uint32_t :26; /*!< bit: 6..31 Reserved */ 551 } bit; /*!< Structure used for bit access */ 552 uint32_t reg; /*!< Type used for register access */ 553 } ADCIFE_IDR_Type; 554 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 555 556 #define ADCIFE_IDR_OFFSET 0x34 /**< \brief (ADCIFE_IDR offset) Interrupt Disable Register */ 557 #define ADCIFE_IDR_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_IDR reset_value) Interrupt Disable Register */ 558 559 #define ADCIFE_IDR_SEOC_Pos 0 /**< \brief (ADCIFE_IDR) Sequencer end of conversion Interrupt Disable */ 560 #define ADCIFE_IDR_SEOC (_U_(0x1) << ADCIFE_IDR_SEOC_Pos) 561 #define ADCIFE_IDR_LOVR_Pos 1 /**< \brief (ADCIFE_IDR) Sequencer last converted value overrun Interrupt Disable */ 562 #define ADCIFE_IDR_LOVR (_U_(0x1) << ADCIFE_IDR_LOVR_Pos) 563 #define ADCIFE_IDR_WM_Pos 2 /**< \brief (ADCIFE_IDR) Window monitor Interrupt Disable */ 564 #define ADCIFE_IDR_WM (_U_(0x1) << ADCIFE_IDR_WM_Pos) 565 #define ADCIFE_IDR_SMTRG_Pos 3 /**< \brief (ADCIFE_IDR) Sequencer missed trigger event Interrupt Disable */ 566 #define ADCIFE_IDR_SMTRG (_U_(0x1) << ADCIFE_IDR_SMTRG_Pos) 567 #define ADCIFE_IDR_TTO_Pos 5 /**< \brief (ADCIFE_IDR) Timer time-out Interrupt Disable */ 568 #define ADCIFE_IDR_TTO (_U_(0x1) << ADCIFE_IDR_TTO_Pos) 569 #define ADCIFE_IDR_MASK _U_(0x0000002F) /**< \brief (ADCIFE_IDR) MASK Register */ 570 571 /* -------- ADCIFE_IMR : (ADCIFE Offset: 0x38) (R/ 32) Interrupt Mask Register -------- */ 572 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 573 typedef union { 574 struct { 575 uint32_t SEOC:1; /*!< bit: 0 Sequencer end of conversion Interrupt Mask */ 576 uint32_t LOVR:1; /*!< bit: 1 Sequencer last converted value overrun Interrupt Mask */ 577 uint32_t WM:1; /*!< bit: 2 Window monitor Interrupt Mask */ 578 uint32_t SMTRG:1; /*!< bit: 3 Sequencer missed trigger event Interrupt Mask */ 579 uint32_t :1; /*!< bit: 4 Reserved */ 580 uint32_t TTO:1; /*!< bit: 5 Timer time-out Interrupt Mask */ 581 uint32_t :26; /*!< bit: 6..31 Reserved */ 582 } bit; /*!< Structure used for bit access */ 583 uint32_t reg; /*!< Type used for register access */ 584 } ADCIFE_IMR_Type; 585 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 586 587 #define ADCIFE_IMR_OFFSET 0x38 /**< \brief (ADCIFE_IMR offset) Interrupt Mask Register */ 588 #define ADCIFE_IMR_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_IMR reset_value) Interrupt Mask Register */ 589 590 #define ADCIFE_IMR_SEOC_Pos 0 /**< \brief (ADCIFE_IMR) Sequencer end of conversion Interrupt Mask */ 591 #define ADCIFE_IMR_SEOC (_U_(0x1) << ADCIFE_IMR_SEOC_Pos) 592 #define ADCIFE_IMR_LOVR_Pos 1 /**< \brief (ADCIFE_IMR) Sequencer last converted value overrun Interrupt Mask */ 593 #define ADCIFE_IMR_LOVR (_U_(0x1) << ADCIFE_IMR_LOVR_Pos) 594 #define ADCIFE_IMR_WM_Pos 2 /**< \brief (ADCIFE_IMR) Window monitor Interrupt Mask */ 595 #define ADCIFE_IMR_WM (_U_(0x1) << ADCIFE_IMR_WM_Pos) 596 #define ADCIFE_IMR_SMTRG_Pos 3 /**< \brief (ADCIFE_IMR) Sequencer missed trigger event Interrupt Mask */ 597 #define ADCIFE_IMR_SMTRG (_U_(0x1) << ADCIFE_IMR_SMTRG_Pos) 598 #define ADCIFE_IMR_TTO_Pos 5 /**< \brief (ADCIFE_IMR) Timer time-out Interrupt Mask */ 599 #define ADCIFE_IMR_TTO (_U_(0x1) << ADCIFE_IMR_TTO_Pos) 600 #define ADCIFE_IMR_MASK _U_(0x0000002F) /**< \brief (ADCIFE_IMR) MASK Register */ 601 602 /* -------- ADCIFE_CALIB : (ADCIFE Offset: 0x3C) (R/W 32) Calibration Register -------- */ 603 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 604 typedef union { 605 struct { 606 uint32_t CALIB:8; /*!< bit: 0.. 7 Calibration Value */ 607 uint32_t BIASSEL:1; /*!< bit: 8 Select bias mode */ 608 uint32_t :3; /*!< bit: 9..11 Reserved */ 609 uint32_t BIASCAL:4; /*!< bit: 12..15 Bias Calibration */ 610 uint32_t FCD:1; /*!< bit: 16 Flash Calibration Done */ 611 uint32_t :15; /*!< bit: 17..31 Reserved */ 612 } bit; /*!< Structure used for bit access */ 613 uint32_t reg; /*!< Type used for register access */ 614 } ADCIFE_CALIB_Type; 615 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 616 617 #define ADCIFE_CALIB_OFFSET 0x3C /**< \brief (ADCIFE_CALIB offset) Calibration Register */ 618 #define ADCIFE_CALIB_RESETVALUE _U_(0x00000000); /**< \brief (ADCIFE_CALIB reset_value) Calibration Register */ 619 620 #define ADCIFE_CALIB_CALIB_Pos 0 /**< \brief (ADCIFE_CALIB) Calibration Value */ 621 #define ADCIFE_CALIB_CALIB_Msk (_U_(0xFF) << ADCIFE_CALIB_CALIB_Pos) 622 #define ADCIFE_CALIB_CALIB(value) (ADCIFE_CALIB_CALIB_Msk & ((value) << ADCIFE_CALIB_CALIB_Pos)) 623 #define ADCIFE_CALIB_BIASSEL_Pos 8 /**< \brief (ADCIFE_CALIB) Select bias mode */ 624 #define ADCIFE_CALIB_BIASSEL (_U_(0x1) << ADCIFE_CALIB_BIASSEL_Pos) 625 #define ADCIFE_CALIB_BIASCAL_Pos 12 /**< \brief (ADCIFE_CALIB) Bias Calibration */ 626 #define ADCIFE_CALIB_BIASCAL_Msk (_U_(0xF) << ADCIFE_CALIB_BIASCAL_Pos) 627 #define ADCIFE_CALIB_BIASCAL(value) (ADCIFE_CALIB_BIASCAL_Msk & ((value) << ADCIFE_CALIB_BIASCAL_Pos)) 628 #define ADCIFE_CALIB_FCD_Pos 16 /**< \brief (ADCIFE_CALIB) Flash Calibration Done */ 629 #define ADCIFE_CALIB_FCD (_U_(0x1) << ADCIFE_CALIB_FCD_Pos) 630 #define ADCIFE_CALIB_MASK _U_(0x0001F1FF) /**< \brief (ADCIFE_CALIB) MASK Register */ 631 632 /* -------- ADCIFE_VERSION : (ADCIFE Offset: 0x40) (R/ 32) Version Register -------- */ 633 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 634 typedef union { 635 struct { 636 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 637 uint32_t :4; /*!< bit: 12..15 Reserved */ 638 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 639 uint32_t :12; /*!< bit: 20..31 Reserved */ 640 } bit; /*!< Structure used for bit access */ 641 uint32_t reg; /*!< Type used for register access */ 642 } ADCIFE_VERSION_Type; 643 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 644 645 #define ADCIFE_VERSION_OFFSET 0x40 /**< \brief (ADCIFE_VERSION offset) Version Register */ 646 #define ADCIFE_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (ADCIFE_VERSION reset_value) Version Register */ 647 648 #define ADCIFE_VERSION_VERSION_Pos 0 /**< \brief (ADCIFE_VERSION) Version number */ 649 #define ADCIFE_VERSION_VERSION_Msk (_U_(0xFFF) << ADCIFE_VERSION_VERSION_Pos) 650 #define ADCIFE_VERSION_VERSION(value) (ADCIFE_VERSION_VERSION_Msk & ((value) << ADCIFE_VERSION_VERSION_Pos)) 651 #define ADCIFE_VERSION_VARIANT_Pos 16 /**< \brief (ADCIFE_VERSION) Variant number */ 652 #define ADCIFE_VERSION_VARIANT_Msk (_U_(0xF) << ADCIFE_VERSION_VARIANT_Pos) 653 #define ADCIFE_VERSION_VARIANT(value) (ADCIFE_VERSION_VARIANT_Msk & ((value) << ADCIFE_VERSION_VARIANT_Pos)) 654 #define ADCIFE_VERSION_MASK _U_(0x000F0FFF) /**< \brief (ADCIFE_VERSION) MASK Register */ 655 656 /* -------- ADCIFE_PARAMETER : (ADCIFE Offset: 0x44) (R/ 32) Parameter Register -------- */ 657 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 658 typedef union { 659 struct { 660 uint32_t N:8; /*!< bit: 0.. 7 Number of channels */ 661 uint32_t :24; /*!< bit: 8..31 Reserved */ 662 } bit; /*!< Structure used for bit access */ 663 uint32_t reg; /*!< Type used for register access */ 664 } ADCIFE_PARAMETER_Type; 665 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 666 667 #define ADCIFE_PARAMETER_OFFSET 0x44 /**< \brief (ADCIFE_PARAMETER offset) Parameter Register */ 668 669 #define ADCIFE_PARAMETER_N_Pos 0 /**< \brief (ADCIFE_PARAMETER) Number of channels */ 670 #define ADCIFE_PARAMETER_N_Msk (_U_(0xFF) << ADCIFE_PARAMETER_N_Pos) 671 #define ADCIFE_PARAMETER_N(value) (ADCIFE_PARAMETER_N_Msk & ((value) << ADCIFE_PARAMETER_N_Pos)) 672 #define ADCIFE_PARAMETER_MASK _U_(0x000000FF) /**< \brief (ADCIFE_PARAMETER) MASK Register */ 673 674 /** \brief ADCIFE hardware registers */ 675 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 676 typedef struct { 677 __O uint32_t CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 678 __IO uint32_t CFG; /**< \brief Offset: 0x04 (R/W 32) Configuration Register */ 679 __I uint32_t SR; /**< \brief Offset: 0x08 (R/ 32) Status Register */ 680 __O uint32_t SCR; /**< \brief Offset: 0x0C ( /W 32) Status Clear Register */ 681 __IO uint32_t RTS; /**< \brief Offset: 0x10 (R/W 32) Resistive Touch Screen Register */ 682 __IO uint32_t SEQCFG; /**< \brief Offset: 0x14 (R/W 32) Sequencer Configuration Register */ 683 __O uint32_t CDMA; /**< \brief Offset: 0x18 ( /W 32) Configuration Direct Memory Access Register */ 684 __IO uint32_t TIM; /**< \brief Offset: 0x1C (R/W 32) Timing Configuration Register */ 685 __IO uint32_t ITIMER; /**< \brief Offset: 0x20 (R/W 32) Internal Timer Register */ 686 __IO uint32_t WCFG; /**< \brief Offset: 0x24 (R/W 32) Window Monitor Configuration Register */ 687 __IO uint32_t WTH; /**< \brief Offset: 0x28 (R/W 32) Window Monitor Threshold Configuration Register */ 688 __I uint32_t LCV; /**< \brief Offset: 0x2C (R/ 32) Sequencer Last Converted Value Register */ 689 __O uint32_t IER; /**< \brief Offset: 0x30 ( /W 32) Interrupt Enable Register */ 690 __O uint32_t IDR; /**< \brief Offset: 0x34 ( /W 32) Interrupt Disable Register */ 691 __I uint32_t IMR; /**< \brief Offset: 0x38 (R/ 32) Interrupt Mask Register */ 692 __IO uint32_t CALIB; /**< \brief Offset: 0x3C (R/W 32) Calibration Register */ 693 __I uint32_t VERSION; /**< \brief Offset: 0x40 (R/ 32) Version Register */ 694 __I uint32_t PARAMETER; /**< \brief Offset: 0x44 (R/ 32) Parameter Register */ 695 } Adcife; 696 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 697 698 /*@}*/ 699 700 #endif /* _SAM4L_ADCIFE_COMPONENT_ */ 701
