1 /** 2 * \file 3 * 4 * \brief Component description for ACIFC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_ACIFC_COMPONENT_ 30 #define _SAM4L_ACIFC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR ACIFC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_ACIFC Analog Comparator Interface */ 36 /*@{*/ 37 38 #define ACIFC_I7564 39 #define REV_ACIFC 0x101 40 41 /* -------- ACIFC_CTRL : (ACIFC Offset: 0x00) (R/W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t EN:1; /*!< bit: 0 ACIFC Enable */ 46 uint32_t EVENTEN:1; /*!< bit: 1 Peripheral Event Trigger Enable */ 47 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 48 uint32_t USTART:1; /*!< bit: 4 User Start Single Comparison */ 49 uint32_t ESTART:1; /*!< bit: 5 Peripheral Event Start Single Comparison */ 50 uint32_t :1; /*!< bit: 6 Reserved */ 51 uint32_t ACTEST:1; /*!< bit: 7 Analog Comparator Test Mode */ 52 uint32_t :24; /*!< bit: 8..31 Reserved */ 53 } bit; /*!< Structure used for bit access */ 54 uint32_t reg; /*!< Type used for register access */ 55 } ACIFC_CTRL_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define ACIFC_CTRL_OFFSET 0x00 /**< \brief (ACIFC_CTRL offset) Control Register */ 59 #define ACIFC_CTRL_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_CTRL reset_value) Control Register */ 60 61 #define ACIFC_CTRL_EN_Pos 0 /**< \brief (ACIFC_CTRL) ACIFC Enable */ 62 #define ACIFC_CTRL_EN (_U_(0x1) << ACIFC_CTRL_EN_Pos) 63 #define ACIFC_CTRL_EVENTEN_Pos 1 /**< \brief (ACIFC_CTRL) Peripheral Event Trigger Enable */ 64 #define ACIFC_CTRL_EVENTEN (_U_(0x1) << ACIFC_CTRL_EVENTEN_Pos) 65 #define ACIFC_CTRL_USTART_Pos 4 /**< \brief (ACIFC_CTRL) User Start Single Comparison */ 66 #define ACIFC_CTRL_USTART (_U_(0x1) << ACIFC_CTRL_USTART_Pos) 67 #define ACIFC_CTRL_ESTART_Pos 5 /**< \brief (ACIFC_CTRL) Peripheral Event Start Single Comparison */ 68 #define ACIFC_CTRL_ESTART (_U_(0x1) << ACIFC_CTRL_ESTART_Pos) 69 #define ACIFC_CTRL_ACTEST_Pos 7 /**< \brief (ACIFC_CTRL) Analog Comparator Test Mode */ 70 #define ACIFC_CTRL_ACTEST (_U_(0x1) << ACIFC_CTRL_ACTEST_Pos) 71 #define ACIFC_CTRL_MASK _U_(0x000000B3) /**< \brief (ACIFC_CTRL) MASK Register */ 72 73 /* -------- ACIFC_SR : (ACIFC Offset: 0x04) (R/ 32) Status Register -------- */ 74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 75 typedef union { 76 struct { 77 uint32_t ACCS0:1; /*!< bit: 0 AC0 Current Comparison Status */ 78 uint32_t ACRDY0:1; /*!< bit: 1 AC0 Ready */ 79 uint32_t ACCS1:1; /*!< bit: 2 AC1 Current Comparison Status */ 80 uint32_t ACRDY1:1; /*!< bit: 3 AC1 Ready */ 81 uint32_t ACCS2:1; /*!< bit: 4 AC2 Current Comparison Status */ 82 uint32_t ACRDY2:1; /*!< bit: 5 AC2 Ready */ 83 uint32_t ACCS3:1; /*!< bit: 6 AC3 Current Comparison Status */ 84 uint32_t ACRDY3:1; /*!< bit: 7 AC3 Ready */ 85 uint32_t ACCS4:1; /*!< bit: 8 AC4 Current Comparison Status */ 86 uint32_t ACRDY4:1; /*!< bit: 9 AC4 Ready */ 87 uint32_t ACCS5:1; /*!< bit: 10 AC5 Current Comparison Status */ 88 uint32_t ACRDY5:1; /*!< bit: 11 AC5 Ready */ 89 uint32_t ACCS6:1; /*!< bit: 12 AC6 Current Comparison Status */ 90 uint32_t ACRDY6:1; /*!< bit: 13 AC6 Ready */ 91 uint32_t ACCS7:1; /*!< bit: 14 AC7 Current Comparison Status */ 92 uint32_t ACRDY7:1; /*!< bit: 15 AC7 Ready */ 93 uint32_t :8; /*!< bit: 16..23 Reserved */ 94 uint32_t WFCS0:1; /*!< bit: 24 Window0 Mode Current Status */ 95 uint32_t WFCS1:1; /*!< bit: 25 Window1 Mode Current Status */ 96 uint32_t WFCS2:1; /*!< bit: 26 Window2 Mode Current Status */ 97 uint32_t WFCS3:1; /*!< bit: 27 Window3 Mode Current Status */ 98 uint32_t :4; /*!< bit: 28..31 Reserved */ 99 } bit; /*!< Structure used for bit access */ 100 uint32_t reg; /*!< Type used for register access */ 101 } ACIFC_SR_Type; 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define ACIFC_SR_OFFSET 0x04 /**< \brief (ACIFC_SR offset) Status Register */ 105 #define ACIFC_SR_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_SR reset_value) Status Register */ 106 107 #define ACIFC_SR_ACCS0_Pos 0 /**< \brief (ACIFC_SR) AC0 Current Comparison Status */ 108 #define ACIFC_SR_ACCS0 (_U_(0x1) << ACIFC_SR_ACCS0_Pos) 109 #define ACIFC_SR_ACRDY0_Pos 1 /**< \brief (ACIFC_SR) AC0 Ready */ 110 #define ACIFC_SR_ACRDY0 (_U_(0x1) << ACIFC_SR_ACRDY0_Pos) 111 #define ACIFC_SR_ACCS1_Pos 2 /**< \brief (ACIFC_SR) AC1 Current Comparison Status */ 112 #define ACIFC_SR_ACCS1 (_U_(0x1) << ACIFC_SR_ACCS1_Pos) 113 #define ACIFC_SR_ACRDY1_Pos 3 /**< \brief (ACIFC_SR) AC1 Ready */ 114 #define ACIFC_SR_ACRDY1 (_U_(0x1) << ACIFC_SR_ACRDY1_Pos) 115 #define ACIFC_SR_ACCS2_Pos 4 /**< \brief (ACIFC_SR) AC2 Current Comparison Status */ 116 #define ACIFC_SR_ACCS2 (_U_(0x1) << ACIFC_SR_ACCS2_Pos) 117 #define ACIFC_SR_ACRDY2_Pos 5 /**< \brief (ACIFC_SR) AC2 Ready */ 118 #define ACIFC_SR_ACRDY2 (_U_(0x1) << ACIFC_SR_ACRDY2_Pos) 119 #define ACIFC_SR_ACCS3_Pos 6 /**< \brief (ACIFC_SR) AC3 Current Comparison Status */ 120 #define ACIFC_SR_ACCS3 (_U_(0x1) << ACIFC_SR_ACCS3_Pos) 121 #define ACIFC_SR_ACRDY3_Pos 7 /**< \brief (ACIFC_SR) AC3 Ready */ 122 #define ACIFC_SR_ACRDY3 (_U_(0x1) << ACIFC_SR_ACRDY3_Pos) 123 #define ACIFC_SR_ACCS4_Pos 8 /**< \brief (ACIFC_SR) AC4 Current Comparison Status */ 124 #define ACIFC_SR_ACCS4 (_U_(0x1) << ACIFC_SR_ACCS4_Pos) 125 #define ACIFC_SR_ACRDY4_Pos 9 /**< \brief (ACIFC_SR) AC4 Ready */ 126 #define ACIFC_SR_ACRDY4 (_U_(0x1) << ACIFC_SR_ACRDY4_Pos) 127 #define ACIFC_SR_ACCS5_Pos 10 /**< \brief (ACIFC_SR) AC5 Current Comparison Status */ 128 #define ACIFC_SR_ACCS5 (_U_(0x1) << ACIFC_SR_ACCS5_Pos) 129 #define ACIFC_SR_ACRDY5_Pos 11 /**< \brief (ACIFC_SR) AC5 Ready */ 130 #define ACIFC_SR_ACRDY5 (_U_(0x1) << ACIFC_SR_ACRDY5_Pos) 131 #define ACIFC_SR_ACCS6_Pos 12 /**< \brief (ACIFC_SR) AC6 Current Comparison Status */ 132 #define ACIFC_SR_ACCS6 (_U_(0x1) << ACIFC_SR_ACCS6_Pos) 133 #define ACIFC_SR_ACRDY6_Pos 13 /**< \brief (ACIFC_SR) AC6 Ready */ 134 #define ACIFC_SR_ACRDY6 (_U_(0x1) << ACIFC_SR_ACRDY6_Pos) 135 #define ACIFC_SR_ACCS7_Pos 14 /**< \brief (ACIFC_SR) AC7 Current Comparison Status */ 136 #define ACIFC_SR_ACCS7 (_U_(0x1) << ACIFC_SR_ACCS7_Pos) 137 #define ACIFC_SR_ACRDY7_Pos 15 /**< \brief (ACIFC_SR) AC7 Ready */ 138 #define ACIFC_SR_ACRDY7 (_U_(0x1) << ACIFC_SR_ACRDY7_Pos) 139 #define ACIFC_SR_WFCS0_Pos 24 /**< \brief (ACIFC_SR) Window0 Mode Current Status */ 140 #define ACIFC_SR_WFCS0 (_U_(0x1) << ACIFC_SR_WFCS0_Pos) 141 #define ACIFC_SR_WFCS1_Pos 25 /**< \brief (ACIFC_SR) Window1 Mode Current Status */ 142 #define ACIFC_SR_WFCS1 (_U_(0x1) << ACIFC_SR_WFCS1_Pos) 143 #define ACIFC_SR_WFCS2_Pos 26 /**< \brief (ACIFC_SR) Window2 Mode Current Status */ 144 #define ACIFC_SR_WFCS2 (_U_(0x1) << ACIFC_SR_WFCS2_Pos) 145 #define ACIFC_SR_WFCS3_Pos 27 /**< \brief (ACIFC_SR) Window3 Mode Current Status */ 146 #define ACIFC_SR_WFCS3 (_U_(0x1) << ACIFC_SR_WFCS3_Pos) 147 #define ACIFC_SR_MASK _U_(0x0F00FFFF) /**< \brief (ACIFC_SR) MASK Register */ 148 149 /* -------- ACIFC_IER : (ACIFC Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 151 typedef union { 152 struct { 153 uint32_t ACINT0:1; /*!< bit: 0 AC0 Interrupt Enable */ 154 uint32_t SUTINT0:1; /*!< bit: 1 AC0 Startup Time Interrupt Enable */ 155 uint32_t ACINT1:1; /*!< bit: 2 AC1 Interrupt Enable */ 156 uint32_t SUTINT1:1; /*!< bit: 3 AC1 Startup Time Interrupt Enable */ 157 uint32_t ACINT2:1; /*!< bit: 4 AC2 Interrupt Enable */ 158 uint32_t SUTINT2:1; /*!< bit: 5 AC2 Startup Time Interrupt Enable */ 159 uint32_t ACINT3:1; /*!< bit: 6 AC3 Interrupt Enable */ 160 uint32_t SUTINT3:1; /*!< bit: 7 AC3 Startup Time Interrupt Enable */ 161 uint32_t ACINT4:1; /*!< bit: 8 AC4 Interrupt Enable */ 162 uint32_t SUTINT4:1; /*!< bit: 9 AC4 Startup Time Interrupt Enable */ 163 uint32_t ACINT5:1; /*!< bit: 10 AC5 Interrupt Enable */ 164 uint32_t SUTINT5:1; /*!< bit: 11 AC5 Startup Time Interrupt Enable */ 165 uint32_t ACINT6:1; /*!< bit: 12 AC6 Interrupt Enable */ 166 uint32_t SUTINT6:1; /*!< bit: 13 AC6 Startup Time Interrupt Enable */ 167 uint32_t ACINT7:1; /*!< bit: 14 AC7 Interrupt Enable */ 168 uint32_t SUTINT7:1; /*!< bit: 15 AC7 Startup Time Interrupt Enable */ 169 uint32_t :8; /*!< bit: 16..23 Reserved */ 170 uint32_t WFINT0:1; /*!< bit: 24 Window0 Mode Interrupt Enable */ 171 uint32_t WFINT1:1; /*!< bit: 25 Window1 Mode Interrupt Enable */ 172 uint32_t WFINT2:1; /*!< bit: 26 Window2 Mode Interrupt Enable */ 173 uint32_t WFINT3:1; /*!< bit: 27 Window3 Mode Interrupt Enable */ 174 uint32_t :4; /*!< bit: 28..31 Reserved */ 175 } bit; /*!< Structure used for bit access */ 176 uint32_t reg; /*!< Type used for register access */ 177 } ACIFC_IER_Type; 178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 179 180 #define ACIFC_IER_OFFSET 0x10 /**< \brief (ACIFC_IER offset) Interrupt Enable Register */ 181 #define ACIFC_IER_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_IER reset_value) Interrupt Enable Register */ 182 183 #define ACIFC_IER_ACINT0_Pos 0 /**< \brief (ACIFC_IER) AC0 Interrupt Enable */ 184 #define ACIFC_IER_ACINT0 (_U_(0x1) << ACIFC_IER_ACINT0_Pos) 185 #define ACIFC_IER_SUTINT0_Pos 1 /**< \brief (ACIFC_IER) AC0 Startup Time Interrupt Enable */ 186 #define ACIFC_IER_SUTINT0 (_U_(0x1) << ACIFC_IER_SUTINT0_Pos) 187 #define ACIFC_IER_ACINT1_Pos 2 /**< \brief (ACIFC_IER) AC1 Interrupt Enable */ 188 #define ACIFC_IER_ACINT1 (_U_(0x1) << ACIFC_IER_ACINT1_Pos) 189 #define ACIFC_IER_SUTINT1_Pos 3 /**< \brief (ACIFC_IER) AC1 Startup Time Interrupt Enable */ 190 #define ACIFC_IER_SUTINT1 (_U_(0x1) << ACIFC_IER_SUTINT1_Pos) 191 #define ACIFC_IER_ACINT2_Pos 4 /**< \brief (ACIFC_IER) AC2 Interrupt Enable */ 192 #define ACIFC_IER_ACINT2 (_U_(0x1) << ACIFC_IER_ACINT2_Pos) 193 #define ACIFC_IER_SUTINT2_Pos 5 /**< \brief (ACIFC_IER) AC2 Startup Time Interrupt Enable */ 194 #define ACIFC_IER_SUTINT2 (_U_(0x1) << ACIFC_IER_SUTINT2_Pos) 195 #define ACIFC_IER_ACINT3_Pos 6 /**< \brief (ACIFC_IER) AC3 Interrupt Enable */ 196 #define ACIFC_IER_ACINT3 (_U_(0x1) << ACIFC_IER_ACINT3_Pos) 197 #define ACIFC_IER_SUTINT3_Pos 7 /**< \brief (ACIFC_IER) AC3 Startup Time Interrupt Enable */ 198 #define ACIFC_IER_SUTINT3 (_U_(0x1) << ACIFC_IER_SUTINT3_Pos) 199 #define ACIFC_IER_ACINT4_Pos 8 /**< \brief (ACIFC_IER) AC4 Interrupt Enable */ 200 #define ACIFC_IER_ACINT4 (_U_(0x1) << ACIFC_IER_ACINT4_Pos) 201 #define ACIFC_IER_SUTINT4_Pos 9 /**< \brief (ACIFC_IER) AC4 Startup Time Interrupt Enable */ 202 #define ACIFC_IER_SUTINT4 (_U_(0x1) << ACIFC_IER_SUTINT4_Pos) 203 #define ACIFC_IER_ACINT5_Pos 10 /**< \brief (ACIFC_IER) AC5 Interrupt Enable */ 204 #define ACIFC_IER_ACINT5 (_U_(0x1) << ACIFC_IER_ACINT5_Pos) 205 #define ACIFC_IER_SUTINT5_Pos 11 /**< \brief (ACIFC_IER) AC5 Startup Time Interrupt Enable */ 206 #define ACIFC_IER_SUTINT5 (_U_(0x1) << ACIFC_IER_SUTINT5_Pos) 207 #define ACIFC_IER_ACINT6_Pos 12 /**< \brief (ACIFC_IER) AC6 Interrupt Enable */ 208 #define ACIFC_IER_ACINT6 (_U_(0x1) << ACIFC_IER_ACINT6_Pos) 209 #define ACIFC_IER_SUTINT6_Pos 13 /**< \brief (ACIFC_IER) AC6 Startup Time Interrupt Enable */ 210 #define ACIFC_IER_SUTINT6 (_U_(0x1) << ACIFC_IER_SUTINT6_Pos) 211 #define ACIFC_IER_ACINT7_Pos 14 /**< \brief (ACIFC_IER) AC7 Interrupt Enable */ 212 #define ACIFC_IER_ACINT7 (_U_(0x1) << ACIFC_IER_ACINT7_Pos) 213 #define ACIFC_IER_SUTINT7_Pos 15 /**< \brief (ACIFC_IER) AC7 Startup Time Interrupt Enable */ 214 #define ACIFC_IER_SUTINT7 (_U_(0x1) << ACIFC_IER_SUTINT7_Pos) 215 #define ACIFC_IER_WFINT0_Pos 24 /**< \brief (ACIFC_IER) Window0 Mode Interrupt Enable */ 216 #define ACIFC_IER_WFINT0 (_U_(0x1) << ACIFC_IER_WFINT0_Pos) 217 #define ACIFC_IER_WFINT1_Pos 25 /**< \brief (ACIFC_IER) Window1 Mode Interrupt Enable */ 218 #define ACIFC_IER_WFINT1 (_U_(0x1) << ACIFC_IER_WFINT1_Pos) 219 #define ACIFC_IER_WFINT2_Pos 26 /**< \brief (ACIFC_IER) Window2 Mode Interrupt Enable */ 220 #define ACIFC_IER_WFINT2 (_U_(0x1) << ACIFC_IER_WFINT2_Pos) 221 #define ACIFC_IER_WFINT3_Pos 27 /**< \brief (ACIFC_IER) Window3 Mode Interrupt Enable */ 222 #define ACIFC_IER_WFINT3 (_U_(0x1) << ACIFC_IER_WFINT3_Pos) 223 #define ACIFC_IER_MASK _U_(0x0F00FFFF) /**< \brief (ACIFC_IER) MASK Register */ 224 225 /* -------- ACIFC_IDR : (ACIFC Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ 226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 227 typedef union { 228 struct { 229 uint32_t ACINT0:1; /*!< bit: 0 AC0 Interrupt Disable */ 230 uint32_t SUTINT0:1; /*!< bit: 1 AC0 Startup Time Interrupt Disable */ 231 uint32_t ACINT1:1; /*!< bit: 2 AC1 Interrupt Disable */ 232 uint32_t SUTINT1:1; /*!< bit: 3 AC1 Startup Time Interrupt Disable */ 233 uint32_t ACINT2:1; /*!< bit: 4 AC2 Interrupt Disable */ 234 uint32_t SUTINT2:1; /*!< bit: 5 AC2 Startup Time Interrupt Disable */ 235 uint32_t ACINT3:1; /*!< bit: 6 AC3 Interrupt Disable */ 236 uint32_t SUTINT3:1; /*!< bit: 7 AC3 Startup Time Interrupt Disable */ 237 uint32_t ACINT4:1; /*!< bit: 8 AC4 Interrupt Disable */ 238 uint32_t SUTINT4:1; /*!< bit: 9 AC4 Startup Time Interrupt Disable */ 239 uint32_t ACINT5:1; /*!< bit: 10 AC5 Interrupt Disable */ 240 uint32_t SUTINT5:1; /*!< bit: 11 AC5 Startup Time Interrupt Disable */ 241 uint32_t ACINT6:1; /*!< bit: 12 AC6 Interrupt Disable */ 242 uint32_t SUTINT6:1; /*!< bit: 13 AC6 Startup Time Interrupt Disable */ 243 uint32_t ACINT7:1; /*!< bit: 14 AC7 Interrupt Disable */ 244 uint32_t SUTINT7:1; /*!< bit: 15 AC7 Startup Time Interrupt Disable */ 245 uint32_t :8; /*!< bit: 16..23 Reserved */ 246 uint32_t WFINT0:1; /*!< bit: 24 Window0 Mode Interrupt Disable */ 247 uint32_t WFINT1:1; /*!< bit: 25 Window1 Mode Interrupt Disable */ 248 uint32_t WFINT2:1; /*!< bit: 26 Window2 Mode Interrupt Disable */ 249 uint32_t WFINT3:1; /*!< bit: 27 Window3 Mode Interrupt Disable */ 250 uint32_t :4; /*!< bit: 28..31 Reserved */ 251 } bit; /*!< Structure used for bit access */ 252 uint32_t reg; /*!< Type used for register access */ 253 } ACIFC_IDR_Type; 254 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 255 256 #define ACIFC_IDR_OFFSET 0x14 /**< \brief (ACIFC_IDR offset) Interrupt Disable Register */ 257 #define ACIFC_IDR_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_IDR reset_value) Interrupt Disable Register */ 258 259 #define ACIFC_IDR_ACINT0_Pos 0 /**< \brief (ACIFC_IDR) AC0 Interrupt Disable */ 260 #define ACIFC_IDR_ACINT0 (_U_(0x1) << ACIFC_IDR_ACINT0_Pos) 261 #define ACIFC_IDR_SUTINT0_Pos 1 /**< \brief (ACIFC_IDR) AC0 Startup Time Interrupt Disable */ 262 #define ACIFC_IDR_SUTINT0 (_U_(0x1) << ACIFC_IDR_SUTINT0_Pos) 263 #define ACIFC_IDR_ACINT1_Pos 2 /**< \brief (ACIFC_IDR) AC1 Interrupt Disable */ 264 #define ACIFC_IDR_ACINT1 (_U_(0x1) << ACIFC_IDR_ACINT1_Pos) 265 #define ACIFC_IDR_SUTINT1_Pos 3 /**< \brief (ACIFC_IDR) AC1 Startup Time Interrupt Disable */ 266 #define ACIFC_IDR_SUTINT1 (_U_(0x1) << ACIFC_IDR_SUTINT1_Pos) 267 #define ACIFC_IDR_ACINT2_Pos 4 /**< \brief (ACIFC_IDR) AC2 Interrupt Disable */ 268 #define ACIFC_IDR_ACINT2 (_U_(0x1) << ACIFC_IDR_ACINT2_Pos) 269 #define ACIFC_IDR_SUTINT2_Pos 5 /**< \brief (ACIFC_IDR) AC2 Startup Time Interrupt Disable */ 270 #define ACIFC_IDR_SUTINT2 (_U_(0x1) << ACIFC_IDR_SUTINT2_Pos) 271 #define ACIFC_IDR_ACINT3_Pos 6 /**< \brief (ACIFC_IDR) AC3 Interrupt Disable */ 272 #define ACIFC_IDR_ACINT3 (_U_(0x1) << ACIFC_IDR_ACINT3_Pos) 273 #define ACIFC_IDR_SUTINT3_Pos 7 /**< \brief (ACIFC_IDR) AC3 Startup Time Interrupt Disable */ 274 #define ACIFC_IDR_SUTINT3 (_U_(0x1) << ACIFC_IDR_SUTINT3_Pos) 275 #define ACIFC_IDR_ACINT4_Pos 8 /**< \brief (ACIFC_IDR) AC4 Interrupt Disable */ 276 #define ACIFC_IDR_ACINT4 (_U_(0x1) << ACIFC_IDR_ACINT4_Pos) 277 #define ACIFC_IDR_SUTINT4_Pos 9 /**< \brief (ACIFC_IDR) AC4 Startup Time Interrupt Disable */ 278 #define ACIFC_IDR_SUTINT4 (_U_(0x1) << ACIFC_IDR_SUTINT4_Pos) 279 #define ACIFC_IDR_ACINT5_Pos 10 /**< \brief (ACIFC_IDR) AC5 Interrupt Disable */ 280 #define ACIFC_IDR_ACINT5 (_U_(0x1) << ACIFC_IDR_ACINT5_Pos) 281 #define ACIFC_IDR_SUTINT5_Pos 11 /**< \brief (ACIFC_IDR) AC5 Startup Time Interrupt Disable */ 282 #define ACIFC_IDR_SUTINT5 (_U_(0x1) << ACIFC_IDR_SUTINT5_Pos) 283 #define ACIFC_IDR_ACINT6_Pos 12 /**< \brief (ACIFC_IDR) AC6 Interrupt Disable */ 284 #define ACIFC_IDR_ACINT6 (_U_(0x1) << ACIFC_IDR_ACINT6_Pos) 285 #define ACIFC_IDR_SUTINT6_Pos 13 /**< \brief (ACIFC_IDR) AC6 Startup Time Interrupt Disable */ 286 #define ACIFC_IDR_SUTINT6 (_U_(0x1) << ACIFC_IDR_SUTINT6_Pos) 287 #define ACIFC_IDR_ACINT7_Pos 14 /**< \brief (ACIFC_IDR) AC7 Interrupt Disable */ 288 #define ACIFC_IDR_ACINT7 (_U_(0x1) << ACIFC_IDR_ACINT7_Pos) 289 #define ACIFC_IDR_SUTINT7_Pos 15 /**< \brief (ACIFC_IDR) AC7 Startup Time Interrupt Disable */ 290 #define ACIFC_IDR_SUTINT7 (_U_(0x1) << ACIFC_IDR_SUTINT7_Pos) 291 #define ACIFC_IDR_WFINT0_Pos 24 /**< \brief (ACIFC_IDR) Window0 Mode Interrupt Disable */ 292 #define ACIFC_IDR_WFINT0 (_U_(0x1) << ACIFC_IDR_WFINT0_Pos) 293 #define ACIFC_IDR_WFINT1_Pos 25 /**< \brief (ACIFC_IDR) Window1 Mode Interrupt Disable */ 294 #define ACIFC_IDR_WFINT1 (_U_(0x1) << ACIFC_IDR_WFINT1_Pos) 295 #define ACIFC_IDR_WFINT2_Pos 26 /**< \brief (ACIFC_IDR) Window2 Mode Interrupt Disable */ 296 #define ACIFC_IDR_WFINT2 (_U_(0x1) << ACIFC_IDR_WFINT2_Pos) 297 #define ACIFC_IDR_WFINT3_Pos 27 /**< \brief (ACIFC_IDR) Window3 Mode Interrupt Disable */ 298 #define ACIFC_IDR_WFINT3 (_U_(0x1) << ACIFC_IDR_WFINT3_Pos) 299 #define ACIFC_IDR_MASK _U_(0x0F00FFFF) /**< \brief (ACIFC_IDR) MASK Register */ 300 301 /* -------- ACIFC_IMR : (ACIFC Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ 302 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 303 typedef union { 304 struct { 305 uint32_t ACINT0:1; /*!< bit: 0 AC0 Interrupt Mask */ 306 uint32_t SUTINT0:1; /*!< bit: 1 AC0 Startup Time Interrupt Mask */ 307 uint32_t ACINT1:1; /*!< bit: 2 AC1 Interrupt Mask */ 308 uint32_t SUTINT1:1; /*!< bit: 3 AC1 Startup Time Interrupt Mask */ 309 uint32_t ACINT2:1; /*!< bit: 4 AC2 Interrupt Mask */ 310 uint32_t SUTINT2:1; /*!< bit: 5 AC2 Startup Time Interrupt Mask */ 311 uint32_t ACINT3:1; /*!< bit: 6 AC3 Interrupt Mask */ 312 uint32_t SUTINT3:1; /*!< bit: 7 AC3 Startup Time Interrupt Mask */ 313 uint32_t ACINT4:1; /*!< bit: 8 AC4 Interrupt Mask */ 314 uint32_t SUTINT4:1; /*!< bit: 9 AC4 Startup Time Interrupt Mask */ 315 uint32_t ACINT5:1; /*!< bit: 10 AC5 Interrupt Mask */ 316 uint32_t SUTINT5:1; /*!< bit: 11 AC5 Startup Time Interrupt Mask */ 317 uint32_t ACINT6:1; /*!< bit: 12 AC6 Interrupt Mask */ 318 uint32_t SUTINT6:1; /*!< bit: 13 AC6 Startup Time Interrupt Mask */ 319 uint32_t ACINT7:1; /*!< bit: 14 AC7 Interrupt Mask */ 320 uint32_t SUTINT7:1; /*!< bit: 15 AC7 Startup Time Interrupt Mask */ 321 uint32_t :8; /*!< bit: 16..23 Reserved */ 322 uint32_t WFINT0:1; /*!< bit: 24 Window0 Mode Interrupt Mask */ 323 uint32_t WFINT1:1; /*!< bit: 25 Window1 Mode Interrupt Mask */ 324 uint32_t WFINT2:1; /*!< bit: 26 Window2 Mode Interrupt Mask */ 325 uint32_t WFINT3:1; /*!< bit: 27 Window3 Mode Interrupt Mask */ 326 uint32_t :4; /*!< bit: 28..31 Reserved */ 327 } bit; /*!< Structure used for bit access */ 328 uint32_t reg; /*!< Type used for register access */ 329 } ACIFC_IMR_Type; 330 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 331 332 #define ACIFC_IMR_OFFSET 0x18 /**< \brief (ACIFC_IMR offset) Interrupt Mask Register */ 333 #define ACIFC_IMR_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_IMR reset_value) Interrupt Mask Register */ 334 335 #define ACIFC_IMR_ACINT0_Pos 0 /**< \brief (ACIFC_IMR) AC0 Interrupt Mask */ 336 #define ACIFC_IMR_ACINT0 (_U_(0x1) << ACIFC_IMR_ACINT0_Pos) 337 #define ACIFC_IMR_SUTINT0_Pos 1 /**< \brief (ACIFC_IMR) AC0 Startup Time Interrupt Mask */ 338 #define ACIFC_IMR_SUTINT0 (_U_(0x1) << ACIFC_IMR_SUTINT0_Pos) 339 #define ACIFC_IMR_ACINT1_Pos 2 /**< \brief (ACIFC_IMR) AC1 Interrupt Mask */ 340 #define ACIFC_IMR_ACINT1 (_U_(0x1) << ACIFC_IMR_ACINT1_Pos) 341 #define ACIFC_IMR_SUTINT1_Pos 3 /**< \brief (ACIFC_IMR) AC1 Startup Time Interrupt Mask */ 342 #define ACIFC_IMR_SUTINT1 (_U_(0x1) << ACIFC_IMR_SUTINT1_Pos) 343 #define ACIFC_IMR_ACINT2_Pos 4 /**< \brief (ACIFC_IMR) AC2 Interrupt Mask */ 344 #define ACIFC_IMR_ACINT2 (_U_(0x1) << ACIFC_IMR_ACINT2_Pos) 345 #define ACIFC_IMR_SUTINT2_Pos 5 /**< \brief (ACIFC_IMR) AC2 Startup Time Interrupt Mask */ 346 #define ACIFC_IMR_SUTINT2 (_U_(0x1) << ACIFC_IMR_SUTINT2_Pos) 347 #define ACIFC_IMR_ACINT3_Pos 6 /**< \brief (ACIFC_IMR) AC3 Interrupt Mask */ 348 #define ACIFC_IMR_ACINT3 (_U_(0x1) << ACIFC_IMR_ACINT3_Pos) 349 #define ACIFC_IMR_SUTINT3_Pos 7 /**< \brief (ACIFC_IMR) AC3 Startup Time Interrupt Mask */ 350 #define ACIFC_IMR_SUTINT3 (_U_(0x1) << ACIFC_IMR_SUTINT3_Pos) 351 #define ACIFC_IMR_ACINT4_Pos 8 /**< \brief (ACIFC_IMR) AC4 Interrupt Mask */ 352 #define ACIFC_IMR_ACINT4 (_U_(0x1) << ACIFC_IMR_ACINT4_Pos) 353 #define ACIFC_IMR_SUTINT4_Pos 9 /**< \brief (ACIFC_IMR) AC4 Startup Time Interrupt Mask */ 354 #define ACIFC_IMR_SUTINT4 (_U_(0x1) << ACIFC_IMR_SUTINT4_Pos) 355 #define ACIFC_IMR_ACINT5_Pos 10 /**< \brief (ACIFC_IMR) AC5 Interrupt Mask */ 356 #define ACIFC_IMR_ACINT5 (_U_(0x1) << ACIFC_IMR_ACINT5_Pos) 357 #define ACIFC_IMR_SUTINT5_Pos 11 /**< \brief (ACIFC_IMR) AC5 Startup Time Interrupt Mask */ 358 #define ACIFC_IMR_SUTINT5 (_U_(0x1) << ACIFC_IMR_SUTINT5_Pos) 359 #define ACIFC_IMR_ACINT6_Pos 12 /**< \brief (ACIFC_IMR) AC6 Interrupt Mask */ 360 #define ACIFC_IMR_ACINT6 (_U_(0x1) << ACIFC_IMR_ACINT6_Pos) 361 #define ACIFC_IMR_SUTINT6_Pos 13 /**< \brief (ACIFC_IMR) AC6 Startup Time Interrupt Mask */ 362 #define ACIFC_IMR_SUTINT6 (_U_(0x1) << ACIFC_IMR_SUTINT6_Pos) 363 #define ACIFC_IMR_ACINT7_Pos 14 /**< \brief (ACIFC_IMR) AC7 Interrupt Mask */ 364 #define ACIFC_IMR_ACINT7 (_U_(0x1) << ACIFC_IMR_ACINT7_Pos) 365 #define ACIFC_IMR_SUTINT7_Pos 15 /**< \brief (ACIFC_IMR) AC7 Startup Time Interrupt Mask */ 366 #define ACIFC_IMR_SUTINT7 (_U_(0x1) << ACIFC_IMR_SUTINT7_Pos) 367 #define ACIFC_IMR_WFINT0_Pos 24 /**< \brief (ACIFC_IMR) Window0 Mode Interrupt Mask */ 368 #define ACIFC_IMR_WFINT0 (_U_(0x1) << ACIFC_IMR_WFINT0_Pos) 369 #define ACIFC_IMR_WFINT1_Pos 25 /**< \brief (ACIFC_IMR) Window1 Mode Interrupt Mask */ 370 #define ACIFC_IMR_WFINT1 (_U_(0x1) << ACIFC_IMR_WFINT1_Pos) 371 #define ACIFC_IMR_WFINT2_Pos 26 /**< \brief (ACIFC_IMR) Window2 Mode Interrupt Mask */ 372 #define ACIFC_IMR_WFINT2 (_U_(0x1) << ACIFC_IMR_WFINT2_Pos) 373 #define ACIFC_IMR_WFINT3_Pos 27 /**< \brief (ACIFC_IMR) Window3 Mode Interrupt Mask */ 374 #define ACIFC_IMR_WFINT3 (_U_(0x1) << ACIFC_IMR_WFINT3_Pos) 375 #define ACIFC_IMR_MASK _U_(0x0F00FFFF) /**< \brief (ACIFC_IMR) MASK Register */ 376 377 /* -------- ACIFC_ISR : (ACIFC Offset: 0x1C) (R/ 32) Interrupt Status Register -------- */ 378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 379 typedef union { 380 struct { 381 uint32_t ACINT0:1; /*!< bit: 0 AC0 Interrupt Status */ 382 uint32_t SUTINT0:1; /*!< bit: 1 AC0 Startup Time Interrupt Status */ 383 uint32_t ACINT1:1; /*!< bit: 2 AC1 Interrupt Status */ 384 uint32_t SUTINT1:1; /*!< bit: 3 AC1 Startup Time Interrupt Status */ 385 uint32_t ACINT2:1; /*!< bit: 4 AC2 Interrupt Status */ 386 uint32_t SUTINT2:1; /*!< bit: 5 AC2 Startup Time Interrupt Status */ 387 uint32_t ACINT3:1; /*!< bit: 6 AC3 Interrupt Status */ 388 uint32_t SUTINT3:1; /*!< bit: 7 AC3 Startup Time Interrupt Status */ 389 uint32_t ACINT4:1; /*!< bit: 8 AC4 Interrupt Status */ 390 uint32_t SUTINT4:1; /*!< bit: 9 AC4 Startup Time Interrupt Status */ 391 uint32_t ACINT5:1; /*!< bit: 10 AC5 Interrupt Status */ 392 uint32_t SUTINT5:1; /*!< bit: 11 AC5 Startup Time Interrupt Status */ 393 uint32_t ACINT6:1; /*!< bit: 12 AC6 Interrupt Status */ 394 uint32_t SUTINT6:1; /*!< bit: 13 AC6 Startup Time Interrupt Status */ 395 uint32_t ACINT7:1; /*!< bit: 14 AC7 Interrupt Status */ 396 uint32_t SUTINT7:1; /*!< bit: 15 AC7 Startup Time Interrupt Status */ 397 uint32_t :8; /*!< bit: 16..23 Reserved */ 398 uint32_t WFINT0:1; /*!< bit: 24 Window0 Mode Interrupt Status */ 399 uint32_t WFINT1:1; /*!< bit: 25 Window1 Mode Interrupt Status */ 400 uint32_t WFINT2:1; /*!< bit: 26 Window2 Mode Interrupt Status */ 401 uint32_t WFINT3:1; /*!< bit: 27 Window3 Mode Interrupt Status */ 402 uint32_t :4; /*!< bit: 28..31 Reserved */ 403 } bit; /*!< Structure used for bit access */ 404 uint32_t reg; /*!< Type used for register access */ 405 } ACIFC_ISR_Type; 406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 407 408 #define ACIFC_ISR_OFFSET 0x1C /**< \brief (ACIFC_ISR offset) Interrupt Status Register */ 409 #define ACIFC_ISR_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_ISR reset_value) Interrupt Status Register */ 410 411 #define ACIFC_ISR_ACINT0_Pos 0 /**< \brief (ACIFC_ISR) AC0 Interrupt Status */ 412 #define ACIFC_ISR_ACINT0 (_U_(0x1) << ACIFC_ISR_ACINT0_Pos) 413 #define ACIFC_ISR_SUTINT0_Pos 1 /**< \brief (ACIFC_ISR) AC0 Startup Time Interrupt Status */ 414 #define ACIFC_ISR_SUTINT0 (_U_(0x1) << ACIFC_ISR_SUTINT0_Pos) 415 #define ACIFC_ISR_ACINT1_Pos 2 /**< \brief (ACIFC_ISR) AC1 Interrupt Status */ 416 #define ACIFC_ISR_ACINT1 (_U_(0x1) << ACIFC_ISR_ACINT1_Pos) 417 #define ACIFC_ISR_SUTINT1_Pos 3 /**< \brief (ACIFC_ISR) AC1 Startup Time Interrupt Status */ 418 #define ACIFC_ISR_SUTINT1 (_U_(0x1) << ACIFC_ISR_SUTINT1_Pos) 419 #define ACIFC_ISR_ACINT2_Pos 4 /**< \brief (ACIFC_ISR) AC2 Interrupt Status */ 420 #define ACIFC_ISR_ACINT2 (_U_(0x1) << ACIFC_ISR_ACINT2_Pos) 421 #define ACIFC_ISR_SUTINT2_Pos 5 /**< \brief (ACIFC_ISR) AC2 Startup Time Interrupt Status */ 422 #define ACIFC_ISR_SUTINT2 (_U_(0x1) << ACIFC_ISR_SUTINT2_Pos) 423 #define ACIFC_ISR_ACINT3_Pos 6 /**< \brief (ACIFC_ISR) AC3 Interrupt Status */ 424 #define ACIFC_ISR_ACINT3 (_U_(0x1) << ACIFC_ISR_ACINT3_Pos) 425 #define ACIFC_ISR_SUTINT3_Pos 7 /**< \brief (ACIFC_ISR) AC3 Startup Time Interrupt Status */ 426 #define ACIFC_ISR_SUTINT3 (_U_(0x1) << ACIFC_ISR_SUTINT3_Pos) 427 #define ACIFC_ISR_ACINT4_Pos 8 /**< \brief (ACIFC_ISR) AC4 Interrupt Status */ 428 #define ACIFC_ISR_ACINT4 (_U_(0x1) << ACIFC_ISR_ACINT4_Pos) 429 #define ACIFC_ISR_SUTINT4_Pos 9 /**< \brief (ACIFC_ISR) AC4 Startup Time Interrupt Status */ 430 #define ACIFC_ISR_SUTINT4 (_U_(0x1) << ACIFC_ISR_SUTINT4_Pos) 431 #define ACIFC_ISR_ACINT5_Pos 10 /**< \brief (ACIFC_ISR) AC5 Interrupt Status */ 432 #define ACIFC_ISR_ACINT5 (_U_(0x1) << ACIFC_ISR_ACINT5_Pos) 433 #define ACIFC_ISR_SUTINT5_Pos 11 /**< \brief (ACIFC_ISR) AC5 Startup Time Interrupt Status */ 434 #define ACIFC_ISR_SUTINT5 (_U_(0x1) << ACIFC_ISR_SUTINT5_Pos) 435 #define ACIFC_ISR_ACINT6_Pos 12 /**< \brief (ACIFC_ISR) AC6 Interrupt Status */ 436 #define ACIFC_ISR_ACINT6 (_U_(0x1) << ACIFC_ISR_ACINT6_Pos) 437 #define ACIFC_ISR_SUTINT6_Pos 13 /**< \brief (ACIFC_ISR) AC6 Startup Time Interrupt Status */ 438 #define ACIFC_ISR_SUTINT6 (_U_(0x1) << ACIFC_ISR_SUTINT6_Pos) 439 #define ACIFC_ISR_ACINT7_Pos 14 /**< \brief (ACIFC_ISR) AC7 Interrupt Status */ 440 #define ACIFC_ISR_ACINT7 (_U_(0x1) << ACIFC_ISR_ACINT7_Pos) 441 #define ACIFC_ISR_SUTINT7_Pos 15 /**< \brief (ACIFC_ISR) AC7 Startup Time Interrupt Status */ 442 #define ACIFC_ISR_SUTINT7 (_U_(0x1) << ACIFC_ISR_SUTINT7_Pos) 443 #define ACIFC_ISR_WFINT0_Pos 24 /**< \brief (ACIFC_ISR) Window0 Mode Interrupt Status */ 444 #define ACIFC_ISR_WFINT0 (_U_(0x1) << ACIFC_ISR_WFINT0_Pos) 445 #define ACIFC_ISR_WFINT1_Pos 25 /**< \brief (ACIFC_ISR) Window1 Mode Interrupt Status */ 446 #define ACIFC_ISR_WFINT1 (_U_(0x1) << ACIFC_ISR_WFINT1_Pos) 447 #define ACIFC_ISR_WFINT2_Pos 26 /**< \brief (ACIFC_ISR) Window2 Mode Interrupt Status */ 448 #define ACIFC_ISR_WFINT2 (_U_(0x1) << ACIFC_ISR_WFINT2_Pos) 449 #define ACIFC_ISR_WFINT3_Pos 27 /**< \brief (ACIFC_ISR) Window3 Mode Interrupt Status */ 450 #define ACIFC_ISR_WFINT3 (_U_(0x1) << ACIFC_ISR_WFINT3_Pos) 451 #define ACIFC_ISR_MASK _U_(0x0F00FFFF) /**< \brief (ACIFC_ISR) MASK Register */ 452 453 /* -------- ACIFC_ICR : (ACIFC Offset: 0x20) ( /W 32) Interrupt Status Clear Register -------- */ 454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 455 typedef union { 456 struct { 457 uint32_t ACINT0:1; /*!< bit: 0 AC0 Interrupt Status Clear */ 458 uint32_t SUTINT0:1; /*!< bit: 1 AC0 Startup Time Interrupt Status Clear */ 459 uint32_t ACINT1:1; /*!< bit: 2 AC1 Interrupt Status Clear */ 460 uint32_t SUTINT1:1; /*!< bit: 3 AC1 Startup Time Interrupt Status Clear */ 461 uint32_t ACINT2:1; /*!< bit: 4 AC2 Interrupt Status Clear */ 462 uint32_t SUTINT2:1; /*!< bit: 5 AC2 Startup Time Interrupt Status Clear */ 463 uint32_t ACINT3:1; /*!< bit: 6 AC3 Interrupt Status Clear */ 464 uint32_t SUTINT3:1; /*!< bit: 7 AC3 Startup Time Interrupt Status Clear */ 465 uint32_t ACINT4:1; /*!< bit: 8 AC4 Interrupt Status Clear */ 466 uint32_t SUTINT4:1; /*!< bit: 9 AC4 Startup Time Interrupt Status Clear */ 467 uint32_t ACINT5:1; /*!< bit: 10 AC5 Interrupt Status Clear */ 468 uint32_t SUTINT5:1; /*!< bit: 11 AC5 Startup Time Interrupt Status Clear */ 469 uint32_t ACINT6:1; /*!< bit: 12 AC6 Interrupt Status Clear */ 470 uint32_t SUTINT6:1; /*!< bit: 13 AC6 Startup Time Interrupt Status Clear */ 471 uint32_t ACINT7:1; /*!< bit: 14 AC7 Interrupt Status Clear */ 472 uint32_t SUTINT7:1; /*!< bit: 15 AC7 Startup Time Interrupt Status Clear */ 473 uint32_t :8; /*!< bit: 16..23 Reserved */ 474 uint32_t WFINT0:1; /*!< bit: 24 Window0 Mode Interrupt Status Clear */ 475 uint32_t WFINT1:1; /*!< bit: 25 Window1 Mode Interrupt Status Clear */ 476 uint32_t WFINT2:1; /*!< bit: 26 Window2 Mode Interrupt Status Clear */ 477 uint32_t WFINT3:1; /*!< bit: 27 Window3 Mode Interrupt Status Clear */ 478 uint32_t :4; /*!< bit: 28..31 Reserved */ 479 } bit; /*!< Structure used for bit access */ 480 uint32_t reg; /*!< Type used for register access */ 481 } ACIFC_ICR_Type; 482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 483 484 #define ACIFC_ICR_OFFSET 0x20 /**< \brief (ACIFC_ICR offset) Interrupt Status Clear Register */ 485 #define ACIFC_ICR_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_ICR reset_value) Interrupt Status Clear Register */ 486 487 #define ACIFC_ICR_ACINT0_Pos 0 /**< \brief (ACIFC_ICR) AC0 Interrupt Status Clear */ 488 #define ACIFC_ICR_ACINT0 (_U_(0x1) << ACIFC_ICR_ACINT0_Pos) 489 #define ACIFC_ICR_SUTINT0_Pos 1 /**< \brief (ACIFC_ICR) AC0 Startup Time Interrupt Status Clear */ 490 #define ACIFC_ICR_SUTINT0 (_U_(0x1) << ACIFC_ICR_SUTINT0_Pos) 491 #define ACIFC_ICR_ACINT1_Pos 2 /**< \brief (ACIFC_ICR) AC1 Interrupt Status Clear */ 492 #define ACIFC_ICR_ACINT1 (_U_(0x1) << ACIFC_ICR_ACINT1_Pos) 493 #define ACIFC_ICR_SUTINT1_Pos 3 /**< \brief (ACIFC_ICR) AC1 Startup Time Interrupt Status Clear */ 494 #define ACIFC_ICR_SUTINT1 (_U_(0x1) << ACIFC_ICR_SUTINT1_Pos) 495 #define ACIFC_ICR_ACINT2_Pos 4 /**< \brief (ACIFC_ICR) AC2 Interrupt Status Clear */ 496 #define ACIFC_ICR_ACINT2 (_U_(0x1) << ACIFC_ICR_ACINT2_Pos) 497 #define ACIFC_ICR_SUTINT2_Pos 5 /**< \brief (ACIFC_ICR) AC2 Startup Time Interrupt Status Clear */ 498 #define ACIFC_ICR_SUTINT2 (_U_(0x1) << ACIFC_ICR_SUTINT2_Pos) 499 #define ACIFC_ICR_ACINT3_Pos 6 /**< \brief (ACIFC_ICR) AC3 Interrupt Status Clear */ 500 #define ACIFC_ICR_ACINT3 (_U_(0x1) << ACIFC_ICR_ACINT3_Pos) 501 #define ACIFC_ICR_SUTINT3_Pos 7 /**< \brief (ACIFC_ICR) AC3 Startup Time Interrupt Status Clear */ 502 #define ACIFC_ICR_SUTINT3 (_U_(0x1) << ACIFC_ICR_SUTINT3_Pos) 503 #define ACIFC_ICR_ACINT4_Pos 8 /**< \brief (ACIFC_ICR) AC4 Interrupt Status Clear */ 504 #define ACIFC_ICR_ACINT4 (_U_(0x1) << ACIFC_ICR_ACINT4_Pos) 505 #define ACIFC_ICR_SUTINT4_Pos 9 /**< \brief (ACIFC_ICR) AC4 Startup Time Interrupt Status Clear */ 506 #define ACIFC_ICR_SUTINT4 (_U_(0x1) << ACIFC_ICR_SUTINT4_Pos) 507 #define ACIFC_ICR_ACINT5_Pos 10 /**< \brief (ACIFC_ICR) AC5 Interrupt Status Clear */ 508 #define ACIFC_ICR_ACINT5 (_U_(0x1) << ACIFC_ICR_ACINT5_Pos) 509 #define ACIFC_ICR_SUTINT5_Pos 11 /**< \brief (ACIFC_ICR) AC5 Startup Time Interrupt Status Clear */ 510 #define ACIFC_ICR_SUTINT5 (_U_(0x1) << ACIFC_ICR_SUTINT5_Pos) 511 #define ACIFC_ICR_ACINT6_Pos 12 /**< \brief (ACIFC_ICR) AC6 Interrupt Status Clear */ 512 #define ACIFC_ICR_ACINT6 (_U_(0x1) << ACIFC_ICR_ACINT6_Pos) 513 #define ACIFC_ICR_SUTINT6_Pos 13 /**< \brief (ACIFC_ICR) AC6 Startup Time Interrupt Status Clear */ 514 #define ACIFC_ICR_SUTINT6 (_U_(0x1) << ACIFC_ICR_SUTINT6_Pos) 515 #define ACIFC_ICR_ACINT7_Pos 14 /**< \brief (ACIFC_ICR) AC7 Interrupt Status Clear */ 516 #define ACIFC_ICR_ACINT7 (_U_(0x1) << ACIFC_ICR_ACINT7_Pos) 517 #define ACIFC_ICR_SUTINT7_Pos 15 /**< \brief (ACIFC_ICR) AC7 Startup Time Interrupt Status Clear */ 518 #define ACIFC_ICR_SUTINT7 (_U_(0x1) << ACIFC_ICR_SUTINT7_Pos) 519 #define ACIFC_ICR_WFINT0_Pos 24 /**< \brief (ACIFC_ICR) Window0 Mode Interrupt Status Clear */ 520 #define ACIFC_ICR_WFINT0 (_U_(0x1) << ACIFC_ICR_WFINT0_Pos) 521 #define ACIFC_ICR_WFINT1_Pos 25 /**< \brief (ACIFC_ICR) Window1 Mode Interrupt Status Clear */ 522 #define ACIFC_ICR_WFINT1 (_U_(0x1) << ACIFC_ICR_WFINT1_Pos) 523 #define ACIFC_ICR_WFINT2_Pos 26 /**< \brief (ACIFC_ICR) Window2 Mode Interrupt Status Clear */ 524 #define ACIFC_ICR_WFINT2 (_U_(0x1) << ACIFC_ICR_WFINT2_Pos) 525 #define ACIFC_ICR_WFINT3_Pos 27 /**< \brief (ACIFC_ICR) Window3 Mode Interrupt Status Clear */ 526 #define ACIFC_ICR_WFINT3 (_U_(0x1) << ACIFC_ICR_WFINT3_Pos) 527 #define ACIFC_ICR_MASK _U_(0x0F00FFFF) /**< \brief (ACIFC_ICR) MASK Register */ 528 529 /* -------- ACIFC_TR : (ACIFC Offset: 0x24) (R/W 32) Test Register -------- */ 530 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 531 typedef union { 532 struct { 533 uint32_t ACTEST0:1; /*!< bit: 0 AC0 Output Override Value */ 534 uint32_t ACTEST1:1; /*!< bit: 1 AC1 Output Override Value */ 535 uint32_t ACTEST2:1; /*!< bit: 2 AC2 Output Override Value */ 536 uint32_t ACTEST3:1; /*!< bit: 3 AC3 Output Override Value */ 537 uint32_t ACTEST4:1; /*!< bit: 4 AC4 Output Override Value */ 538 uint32_t ACTEST5:1; /*!< bit: 5 AC5 Output Override Value */ 539 uint32_t ACTEST6:1; /*!< bit: 6 AC6 Output Override Value */ 540 uint32_t ACTEST7:1; /*!< bit: 7 AC7 Output Override Value */ 541 uint32_t :24; /*!< bit: 8..31 Reserved */ 542 } bit; /*!< Structure used for bit access */ 543 uint32_t reg; /*!< Type used for register access */ 544 } ACIFC_TR_Type; 545 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 546 547 #define ACIFC_TR_OFFSET 0x24 /**< \brief (ACIFC_TR offset) Test Register */ 548 #define ACIFC_TR_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_TR reset_value) Test Register */ 549 550 #define ACIFC_TR_ACTEST0_Pos 0 /**< \brief (ACIFC_TR) AC0 Output Override Value */ 551 #define ACIFC_TR_ACTEST0 (_U_(0x1) << ACIFC_TR_ACTEST0_Pos) 552 #define ACIFC_TR_ACTEST1_Pos 1 /**< \brief (ACIFC_TR) AC1 Output Override Value */ 553 #define ACIFC_TR_ACTEST1 (_U_(0x1) << ACIFC_TR_ACTEST1_Pos) 554 #define ACIFC_TR_ACTEST2_Pos 2 /**< \brief (ACIFC_TR) AC2 Output Override Value */ 555 #define ACIFC_TR_ACTEST2 (_U_(0x1) << ACIFC_TR_ACTEST2_Pos) 556 #define ACIFC_TR_ACTEST3_Pos 3 /**< \brief (ACIFC_TR) AC3 Output Override Value */ 557 #define ACIFC_TR_ACTEST3 (_U_(0x1) << ACIFC_TR_ACTEST3_Pos) 558 #define ACIFC_TR_ACTEST4_Pos 4 /**< \brief (ACIFC_TR) AC4 Output Override Value */ 559 #define ACIFC_TR_ACTEST4 (_U_(0x1) << ACIFC_TR_ACTEST4_Pos) 560 #define ACIFC_TR_ACTEST5_Pos 5 /**< \brief (ACIFC_TR) AC5 Output Override Value */ 561 #define ACIFC_TR_ACTEST5 (_U_(0x1) << ACIFC_TR_ACTEST5_Pos) 562 #define ACIFC_TR_ACTEST6_Pos 6 /**< \brief (ACIFC_TR) AC6 Output Override Value */ 563 #define ACIFC_TR_ACTEST6 (_U_(0x1) << ACIFC_TR_ACTEST6_Pos) 564 #define ACIFC_TR_ACTEST7_Pos 7 /**< \brief (ACIFC_TR) AC7 Output Override Value */ 565 #define ACIFC_TR_ACTEST7 (_U_(0x1) << ACIFC_TR_ACTEST7_Pos) 566 #define ACIFC_TR_MASK _U_(0x000000FF) /**< \brief (ACIFC_TR) MASK Register */ 567 568 /* -------- ACIFC_PARAMETER : (ACIFC Offset: 0x30) (R/ 32) Parameter Register -------- */ 569 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 570 typedef union { 571 struct { 572 uint32_t ACIMPL0:1; /*!< bit: 0 Analog Comparator 0 Implemented */ 573 uint32_t ACIMPL1:1; /*!< bit: 1 Analog Comparator 1 Implemented */ 574 uint32_t ACIMPL2:1; /*!< bit: 2 Analog Comparator 2 Implemented */ 575 uint32_t ACIMPL3:1; /*!< bit: 3 Analog Comparator 3 Implemented */ 576 uint32_t ACIMPL4:1; /*!< bit: 4 Analog Comparator 4 Implemented */ 577 uint32_t ACIMPL5:1; /*!< bit: 5 Analog Comparator 5 Implemented */ 578 uint32_t ACIMPL6:1; /*!< bit: 6 Analog Comparator 6 Implemented */ 579 uint32_t ACIMPL7:1; /*!< bit: 7 Analog Comparator 7 Implemented */ 580 uint32_t :8; /*!< bit: 8..15 Reserved */ 581 uint32_t WIMPL0:1; /*!< bit: 16 Window0 Mode Implemented */ 582 uint32_t WIMPL1:1; /*!< bit: 17 Window1 Mode Implemented */ 583 uint32_t WIMPL2:1; /*!< bit: 18 Window2 Mode Implemented */ 584 uint32_t WIMPL3:1; /*!< bit: 19 Window3 Mode Implemented */ 585 uint32_t :12; /*!< bit: 20..31 Reserved */ 586 } bit; /*!< Structure used for bit access */ 587 uint32_t reg; /*!< Type used for register access */ 588 } ACIFC_PARAMETER_Type; 589 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 590 591 #define ACIFC_PARAMETER_OFFSET 0x30 /**< \brief (ACIFC_PARAMETER offset) Parameter Register */ 592 593 #define ACIFC_PARAMETER_ACIMPL0_Pos 0 /**< \brief (ACIFC_PARAMETER) Analog Comparator 0 Implemented */ 594 #define ACIFC_PARAMETER_ACIMPL0 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL0_Pos) 595 #define ACIFC_PARAMETER_ACIMPL1_Pos 1 /**< \brief (ACIFC_PARAMETER) Analog Comparator 1 Implemented */ 596 #define ACIFC_PARAMETER_ACIMPL1 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL1_Pos) 597 #define ACIFC_PARAMETER_ACIMPL2_Pos 2 /**< \brief (ACIFC_PARAMETER) Analog Comparator 2 Implemented */ 598 #define ACIFC_PARAMETER_ACIMPL2 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL2_Pos) 599 #define ACIFC_PARAMETER_ACIMPL3_Pos 3 /**< \brief (ACIFC_PARAMETER) Analog Comparator 3 Implemented */ 600 #define ACIFC_PARAMETER_ACIMPL3 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL3_Pos) 601 #define ACIFC_PARAMETER_ACIMPL4_Pos 4 /**< \brief (ACIFC_PARAMETER) Analog Comparator 4 Implemented */ 602 #define ACIFC_PARAMETER_ACIMPL4 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL4_Pos) 603 #define ACIFC_PARAMETER_ACIMPL5_Pos 5 /**< \brief (ACIFC_PARAMETER) Analog Comparator 5 Implemented */ 604 #define ACIFC_PARAMETER_ACIMPL5 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL5_Pos) 605 #define ACIFC_PARAMETER_ACIMPL6_Pos 6 /**< \brief (ACIFC_PARAMETER) Analog Comparator 6 Implemented */ 606 #define ACIFC_PARAMETER_ACIMPL6 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL6_Pos) 607 #define ACIFC_PARAMETER_ACIMPL7_Pos 7 /**< \brief (ACIFC_PARAMETER) Analog Comparator 7 Implemented */ 608 #define ACIFC_PARAMETER_ACIMPL7 (_U_(0x1) << ACIFC_PARAMETER_ACIMPL7_Pos) 609 #define ACIFC_PARAMETER_WIMPL0_Pos 16 /**< \brief (ACIFC_PARAMETER) Window0 Mode Implemented */ 610 #define ACIFC_PARAMETER_WIMPL0 (_U_(0x1) << ACIFC_PARAMETER_WIMPL0_Pos) 611 #define ACIFC_PARAMETER_WIMPL1_Pos 17 /**< \brief (ACIFC_PARAMETER) Window1 Mode Implemented */ 612 #define ACIFC_PARAMETER_WIMPL1 (_U_(0x1) << ACIFC_PARAMETER_WIMPL1_Pos) 613 #define ACIFC_PARAMETER_WIMPL2_Pos 18 /**< \brief (ACIFC_PARAMETER) Window2 Mode Implemented */ 614 #define ACIFC_PARAMETER_WIMPL2 (_U_(0x1) << ACIFC_PARAMETER_WIMPL2_Pos) 615 #define ACIFC_PARAMETER_WIMPL3_Pos 19 /**< \brief (ACIFC_PARAMETER) Window3 Mode Implemented */ 616 #define ACIFC_PARAMETER_WIMPL3 (_U_(0x1) << ACIFC_PARAMETER_WIMPL3_Pos) 617 #define ACIFC_PARAMETER_MASK _U_(0x000F00FF) /**< \brief (ACIFC_PARAMETER) MASK Register */ 618 619 /* -------- ACIFC_VERSION : (ACIFC Offset: 0x34) (R/ 32) Version Register -------- */ 620 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 621 typedef union { 622 struct { 623 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 624 uint32_t :4; /*!< bit: 12..15 Reserved */ 625 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 626 uint32_t :12; /*!< bit: 20..31 Reserved */ 627 } bit; /*!< Structure used for bit access */ 628 uint32_t reg; /*!< Type used for register access */ 629 } ACIFC_VERSION_Type; 630 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 631 632 #define ACIFC_VERSION_OFFSET 0x34 /**< \brief (ACIFC_VERSION offset) Version Register */ 633 #define ACIFC_VERSION_RESETVALUE _U_(0x00000101); /**< \brief (ACIFC_VERSION reset_value) Version Register */ 634 635 #define ACIFC_VERSION_VERSION_Pos 0 /**< \brief (ACIFC_VERSION) Version Number */ 636 #define ACIFC_VERSION_VERSION_Msk (_U_(0xFFF) << ACIFC_VERSION_VERSION_Pos) 637 #define ACIFC_VERSION_VERSION(value) (ACIFC_VERSION_VERSION_Msk & ((value) << ACIFC_VERSION_VERSION_Pos)) 638 #define ACIFC_VERSION_VARIANT_Pos 16 /**< \brief (ACIFC_VERSION) Variant Number */ 639 #define ACIFC_VERSION_VARIANT_Msk (_U_(0xF) << ACIFC_VERSION_VARIANT_Pos) 640 #define ACIFC_VERSION_VARIANT(value) (ACIFC_VERSION_VARIANT_Msk & ((value) << ACIFC_VERSION_VARIANT_Pos)) 641 #define ACIFC_VERSION_MASK _U_(0x000F0FFF) /**< \brief (ACIFC_VERSION) MASK Register */ 642 643 /* -------- ACIFC_CONFW : (ACIFC Offset: 0x80) (R/W 32) CONFW Window configuration Register -------- */ 644 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 645 typedef union { 646 struct { 647 uint32_t WIS:3; /*!< bit: 0.. 2 Window Mode Interrupt Settings */ 648 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 649 uint32_t WEVSRC:3; /*!< bit: 8..10 Peripheral Event Sourse Selection for Window Mode */ 650 uint32_t WEVEN:1; /*!< bit: 11 Window Peripheral Event Enable */ 651 uint32_t :4; /*!< bit: 12..15 Reserved */ 652 uint32_t WFEN:1; /*!< bit: 16 Window Mode Enable */ 653 uint32_t :15; /*!< bit: 17..31 Reserved */ 654 } bit; /*!< Structure used for bit access */ 655 uint32_t reg; /*!< Type used for register access */ 656 } ACIFC_CONFW_Type; 657 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 658 659 #define ACIFC_CONFW_OFFSET 0x80 /**< \brief (ACIFC_CONFW offset) Window configuration Register */ 660 #define ACIFC_CONFW_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_CONFW reset_value) Window configuration Register */ 661 662 #define ACIFC_CONFW_WIS_Pos 0 /**< \brief (ACIFC_CONFW) Window Mode Interrupt Settings */ 663 #define ACIFC_CONFW_WIS_Msk (_U_(0x7) << ACIFC_CONFW_WIS_Pos) 664 #define ACIFC_CONFW_WIS(value) (ACIFC_CONFW_WIS_Msk & ((value) << ACIFC_CONFW_WIS_Pos)) 665 #define ACIFC_CONFW_WEVSRC_Pos 8 /**< \brief (ACIFC_CONFW) Peripheral Event Sourse Selection for Window Mode */ 666 #define ACIFC_CONFW_WEVSRC_Msk (_U_(0x7) << ACIFC_CONFW_WEVSRC_Pos) 667 #define ACIFC_CONFW_WEVSRC(value) (ACIFC_CONFW_WEVSRC_Msk & ((value) << ACIFC_CONFW_WEVSRC_Pos)) 668 #define ACIFC_CONFW_WEVEN_Pos 11 /**< \brief (ACIFC_CONFW) Window Peripheral Event Enable */ 669 #define ACIFC_CONFW_WEVEN (_U_(0x1) << ACIFC_CONFW_WEVEN_Pos) 670 #define ACIFC_CONFW_WFEN_Pos 16 /**< \brief (ACIFC_CONFW) Window Mode Enable */ 671 #define ACIFC_CONFW_WFEN (_U_(0x1) << ACIFC_CONFW_WFEN_Pos) 672 #define ACIFC_CONFW_MASK _U_(0x00010F07) /**< \brief (ACIFC_CONFW) MASK Register */ 673 674 /* -------- ACIFC_CONF : (ACIFC Offset: 0xD0) (R/W 32) CONF AC Configuration Register -------- */ 675 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 676 typedef union { 677 struct { 678 uint32_t IS:2; /*!< bit: 0.. 1 Interupt Settings */ 679 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 680 uint32_t MODE:2; /*!< bit: 4.. 5 Analog Comparator Mode */ 681 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 682 uint32_t INSELN:2; /*!< bit: 8.. 9 Negative Input Select */ 683 uint32_t :6; /*!< bit: 10..15 Reserved */ 684 uint32_t EVENN:1; /*!< bit: 16 Peripheral Event Enable Negative */ 685 uint32_t EVENP:1; /*!< bit: 17 Peripheral Event Enable Positive */ 686 uint32_t :6; /*!< bit: 18..23 Reserved */ 687 uint32_t HYS:2; /*!< bit: 24..25 Hysteresis Voltage Value */ 688 uint32_t FAST:1; /*!< bit: 26 Fast Mode Enable */ 689 uint32_t ALWAYSON:1; /*!< bit: 27 Always On */ 690 uint32_t :4; /*!< bit: 28..31 Reserved */ 691 } bit; /*!< Structure used for bit access */ 692 uint32_t reg; /*!< Type used for register access */ 693 } ACIFC_CONF_Type; 694 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 695 696 #define ACIFC_CONF_OFFSET 0xD0 /**< \brief (ACIFC_CONF offset) AC Configuration Register */ 697 #define ACIFC_CONF_RESETVALUE _U_(0x00000000); /**< \brief (ACIFC_CONF reset_value) AC Configuration Register */ 698 699 #define ACIFC_CONF_IS_Pos 0 /**< \brief (ACIFC_CONF) Interupt Settings */ 700 #define ACIFC_CONF_IS_Msk (_U_(0x3) << ACIFC_CONF_IS_Pos) 701 #define ACIFC_CONF_IS(value) (ACIFC_CONF_IS_Msk & ((value) << ACIFC_CONF_IS_Pos)) 702 #define ACIFC_CONF_MODE_Pos 4 /**< \brief (ACIFC_CONF) Analog Comparator Mode */ 703 #define ACIFC_CONF_MODE_Msk (_U_(0x3) << ACIFC_CONF_MODE_Pos) 704 #define ACIFC_CONF_MODE(value) (ACIFC_CONF_MODE_Msk & ((value) << ACIFC_CONF_MODE_Pos)) 705 #define ACIFC_CONF_INSELN_Pos 8 /**< \brief (ACIFC_CONF) Negative Input Select */ 706 #define ACIFC_CONF_INSELN_Msk (_U_(0x3) << ACIFC_CONF_INSELN_Pos) 707 #define ACIFC_CONF_INSELN(value) (ACIFC_CONF_INSELN_Msk & ((value) << ACIFC_CONF_INSELN_Pos)) 708 #define ACIFC_CONF_EVENN_Pos 16 /**< \brief (ACIFC_CONF) Peripheral Event Enable Negative */ 709 #define ACIFC_CONF_EVENN (_U_(0x1) << ACIFC_CONF_EVENN_Pos) 710 #define ACIFC_CONF_EVENP_Pos 17 /**< \brief (ACIFC_CONF) Peripheral Event Enable Positive */ 711 #define ACIFC_CONF_EVENP (_U_(0x1) << ACIFC_CONF_EVENP_Pos) 712 #define ACIFC_CONF_HYS_Pos 24 /**< \brief (ACIFC_CONF) Hysteresis Voltage Value */ 713 #define ACIFC_CONF_HYS_Msk (_U_(0x3) << ACIFC_CONF_HYS_Pos) 714 #define ACIFC_CONF_HYS(value) (ACIFC_CONF_HYS_Msk & ((value) << ACIFC_CONF_HYS_Pos)) 715 #define ACIFC_CONF_FAST_Pos 26 /**< \brief (ACIFC_CONF) Fast Mode Enable */ 716 #define ACIFC_CONF_FAST (_U_(0x1) << ACIFC_CONF_FAST_Pos) 717 #define ACIFC_CONF_ALWAYSON_Pos 27 /**< \brief (ACIFC_CONF) Always On */ 718 #define ACIFC_CONF_ALWAYSON (_U_(0x1) << ACIFC_CONF_ALWAYSON_Pos) 719 #define ACIFC_CONF_MASK _U_(0x0F030333) /**< \brief (ACIFC_CONF) MASK Register */ 720 721 /** \brief AcifcConf hardware registers */ 722 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 723 typedef union { 724 struct { 725 __IO ACIFC_CONF_Type CONF; /**< \brief Offset: 0x00 (R/W 32) AC Configuration Register */ 726 } bf; 727 struct { 728 RwReg ACIFC_CONF; /**< \brief (ACIFC Offset: 0x00) AC Configuration Register */ 729 } reg; 730 } AcifcConf; 731 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 732 733 /** \brief AcifcConfw hardware registers */ 734 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 735 typedef union { 736 struct { 737 __IO ACIFC_CONFW_Type CONFW; /**< \brief Offset: 0x00 (R/W 32) Window configuration Register */ 738 } bf; 739 struct { 740 RwReg ACIFC_CONFW; /**< \brief (ACIFC Offset: 0x00) Window configuration Register */ 741 } reg; 742 } AcifcConfw; 743 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 744 745 /** \brief ACIFC hardware registers */ 746 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 747 typedef struct { 748 __IO uint32_t CTRL; /**< \brief Offset: 0x00 (R/W 32) Control Register */ 749 __I uint32_t SR; /**< \brief Offset: 0x04 (R/ 32) Status Register */ 750 RoReg8 Reserved1[0x8]; 751 __O uint32_t IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable Register */ 752 __O uint32_t IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable Register */ 753 __I uint32_t IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask Register */ 754 __I uint32_t ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status Register */ 755 __O uint32_t ICR; /**< \brief Offset: 0x20 ( /W 32) Interrupt Status Clear Register */ 756 __IO uint32_t TR; /**< \brief Offset: 0x24 (R/W 32) Test Register */ 757 RoReg8 Reserved2[0x8]; 758 __I uint32_t PARAMETER; /**< \brief Offset: 0x30 (R/ 32) Parameter Register */ 759 __I uint32_t VERSION; /**< \brief Offset: 0x34 (R/ 32) Version Register */ 760 RoReg8 Reserved3[0x48]; 761 __IO uint32_t Confw[4]; /**< \brief Offset: 0x80 AcifcConfw groups */ 762 RoReg8 Reserved4[0x40]; 763 __IO uint32_t Conf[8]; /**< \brief Offset: 0xD0 AcifcConf groups */ 764 } Acifc; 765 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 766 767 /*@}*/ 768 769 #endif /* _SAM4L_ACIFC_COMPONENT_ */ 770
