1 /**
2 *
3 * \file
4 *
5 * \brief This module contains NMC1000 UART protocol bus APIs implementation.
6 *
7 * Copyright (c) 2016 Atmel Corporation. All rights reserved.
8 *
9 * \asf_license_start
10 *
11 * \page License
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * 2. Redistributions in binary form must reproduce the above copyright notice,
20 * this list of conditions and the following disclaimer in the documentation
21 * and/or other materials provided with the distribution.
22 *
23 * 3. The name of Atmel may not be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 *
38 * \asf_license_stop
39 *
40 */
41
42 #include "common/include/nm_common.h"
43
44 #ifdef CONF_WINC_USE_UART
45
46 #include "driver/source/nmuart.h"
47 #include "bus_wrapper/include/nm_bus_wrapper.h"
48
49 #define HDR_SZ 12
50
get_cs(uint8 * b,uint8 sz)51 static uint8 get_cs(uint8* b, uint8 sz){
52 int i;
53 uint8 cs = 0;
54 for(i = 0; i < sz; i++)
55 cs ^= b[i];
56 return cs;
57 }
58
59 /*
60 * @fn nm_uart_sync_cmd
61 * @brief Check COM Port
62 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
63 * @author Dina El Sissy
64 * @date 13 AUG 2012
65 * @version 1.0
66 */
nm_uart_sync_cmd(void)67 sint8 nm_uart_sync_cmd(void)
68 {
69 tstrNmUartDefault strUart;
70 sint8 s8Ret = -1;
71 uint8 b [HDR_SZ+1];
72 uint8 rsz;
73 uint8 onchip = 0;
74
75 /*read reg*/
76 b[0] = 0x12;
77
78 rsz = 1;
79 strUart.pu8Buf = b;
80 strUart.u16Sz = 1;
81
82 if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
83 {
84 strUart.u16Sz = rsz;
85 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
86 {
87 s8Ret = M2M_ERR_BUS_FAIL;
88 }
89 }
90 else
91 {
92 M2M_ERR("failed to send cfg bytes\n");
93 s8Ret = M2M_ERR_BUS_FAIL;
94 }
95 if (b[0] == 0x5a)
96 {
97 s8Ret = 0;
98 onchip = 1;
99 M2M_INFO("Built-in WINC1500 UART Found\n");
100 }
101 else if(b[0] == 0x5b)
102 {
103 s8Ret = 0;
104 onchip = 0;
105 M2M_INFO("WINC1500 Serial Bridge Found\n");
106 }
107 /*TODO: this should be the way we read the register since the cortus is little endian*/
108 /**pu32RetVal = b[0] | ((uint32)b[1] << 8) | ((uint32)b[2] << 16) | ((uint32)b[3] << 24);*/
109 if(s8Ret == M2M_SUCCESS)
110 s8Ret = (sint8)onchip;
111 return s8Ret;
112 }
nm_uart_read_reg_with_ret(uint32 u32Addr,uint32 * pu32RetVal)113 sint8 nm_uart_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal)
114 {
115 tstrNmUartDefault strUart;
116 sint8 s8Ret = M2M_SUCCESS;
117 uint8 b [HDR_SZ+1];
118 uint8 rsz;
119
120 /*read reg*/
121 b[0] = 0xa5;
122 b[1] = 0;
123 b[2] = 0;
124 b[3] = 0;
125 b[4] = 0;
126 b[5] = (uint8)(u32Addr & 0x000000ff);
127 b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
128 b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
129 b[8] = (uint8)((u32Addr & 0xff000000)>>24);
130 b[9] = 0;
131 b[10] = 0;
132 b[11] = 0;
133 b[12] = 0;
134
135 b[2] = get_cs(&b[1],HDR_SZ);
136
137 rsz = 4;
138 strUart.pu8Buf = b;
139 strUart.u16Sz = sizeof(b);
140
141 if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
142 {
143 if(!nm_bus_get_chip_type())
144 {
145 strUart.u16Sz = 1;
146 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
147 {
148 s8Ret = M2M_ERR_BUS_FAIL;
149 }
150 if(b[0] == 0xAC)
151 {
152 M2M_DBG("Successfully sent the command\n");
153 strUart.u16Sz = rsz;
154 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
155 {
156 s8Ret = M2M_ERR_BUS_FAIL;
157 }
158 }
159 else
160 {
161 s8Ret = M2M_ERR_BUS_FAIL;
162 }
163 }
164 else
165 {
166 strUart.u16Sz = rsz;
167 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
168 {
169 s8Ret = M2M_ERR_BUS_FAIL;
170 }
171 }
172 }
173 else
174 {
175 M2M_ERR("failed to send cfg bytes\n");
176 s8Ret = M2M_ERR_BUS_FAIL;
177 }
178 /*TODO: this should be the way we read the register since the cortus is little endian*/
179 /**pu32RetVal = b[0] | ((uint32)b[1] << 8) | ((uint32)b[2] << 16) | ((uint32)b[3] << 24);*/
180
181 *pu32RetVal = ((uint32)b[0] << 24) | ((uint32)b[1] << 16) | ((uint32)b[2] << 8) | b[3];
182
183 return s8Ret;
184 }
185
186 /*
187 * @fn nm_uart_read_reg
188 * @brief Read register
189 * @param [in] u32Addr
190 * Register address
191 * @return Register value
192 * @author Dina El Sissy
193 * @date 13 AUG 2012
194 * @version 1.0
195 */
nm_uart_read_reg(uint32 u32Addr)196 uint32 nm_uart_read_reg(uint32 u32Addr)
197 {
198 uint32 val;
199 nm_uart_read_reg_with_ret(u32Addr , &val);
200 return val;
201 }
202
203 /*
204 * @fn nm_uart_write_reg
205 * @brief write register
206 * @param [in] u32Addr
207 * Register address
208 * @param [in] u32Val
209 * Value to be written to the register
210 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
211 * @author Dina El Sissy
212 * @date 13 AUG 2012
213 * @version 1.0
214 */
nm_uart_write_reg(uint32 u32Addr,uint32 u32Val)215 sint8 nm_uart_write_reg(uint32 u32Addr, uint32 u32Val)
216 {
217 tstrNmUartDefault strUart;
218 sint8 s8Ret = M2M_SUCCESS;
219 uint8 b[HDR_SZ+1];
220
221 /*write reg*/
222 b[0] = 0xa5;
223 b[1] = 1;
224 b[2] = 0;
225 b[3] = 0;
226 b[4] = 0;
227 b[5] = (uint8)(u32Addr & 0x000000ff);
228 b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
229 b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
230 b[8] = (uint8)((u32Addr & 0xff000000)>>24);
231 b[9] = (uint8)(u32Val & 0x000000ff);
232 b[10] = (uint8)((u32Val & 0x0000ff00)>>8);
233 b[11] = (uint8)((u32Val & 0x00ff0000)>>16);
234 b[12] = (uint8)((u32Val & 0xff000000)>>24);
235
236 b[2] = get_cs(&b[1],HDR_SZ);
237
238 get_cs(&b[1],HDR_SZ);
239
240 strUart.pu8Buf = b;
241 strUart.u16Sz = sizeof(b);
242
243 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
244 {
245 M2M_ERR("write error\n");
246 s8Ret = M2M_ERR_BUS_FAIL;
247 }
248 else
249 {
250 if(!nm_bus_get_chip_type())
251 {
252 //check for the ack from the SAMD21 for the packet reception.
253 strUart.u16Sz = 1;
254 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
255 {
256 s8Ret = M2M_ERR_BUS_FAIL;
257 }
258 if(b[0] == 0xAC)
259 {
260 M2M_DBG("Successfully sent the reg write command\n");
261 }
262 else
263 {
264 M2M_ERR("write error\n");
265 s8Ret = M2M_ERR_BUS_FAIL;
266 }
267 }
268 }
269
270 return s8Ret;
271 }
272
273
274 /**
275 * @fn nm_uart_read_block
276 * @brief Read block of data
277 * @param [in] u32Addr
278 * Start address
279 * @param [out] puBuf
280 * Pointer to a buffer used to return the read data
281 * @param [in] u16Sz
282 * Number of bytes to read. The buffer size must be >= u16Sz
283 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
284 * @author Dina El Sissy
285 * @date 13 AUG 2012
286 * @version 1.0
287 */
nm_uart_read_block(uint32 u32Addr,uint8 * pu8Buf,uint16 u16Sz)288 sint8 nm_uart_read_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz)
289 {
290 tstrNmUartDefault strUart;
291 sint8 s8Ret = M2M_SUCCESS;
292 uint8 au8Buf[HDR_SZ+1];
293
294 au8Buf[0] = 0xa5;
295 au8Buf[1] = 2;
296 au8Buf[2] = 0;
297 au8Buf[3] = (uint8)(u16Sz & 0x00ff);
298 au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
299 au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
300 au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
301 au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
302 au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
303 au8Buf[9] = 0;
304 au8Buf[10] = 0;
305 au8Buf[11] = 0;
306 au8Buf[12] = 0;
307
308 au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
309
310 strUart.pu8Buf = au8Buf;
311 strUart.u16Sz = sizeof(au8Buf);
312
313 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
314 {
315 M2M_ERR("write error\n");
316 s8Ret = M2M_ERR_BUS_FAIL;
317 }
318 else
319 {
320 if(!nm_bus_get_chip_type())
321 {
322 //check for the ack from the SAMD21 for the packet reception.
323 strUart.u16Sz = 1;
324 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
325 {
326 s8Ret = M2M_ERR_BUS_FAIL;
327 }
328 if(au8Buf[0] == 0xAC)
329 {
330 M2M_DBG("Successfully sent the block read command\n");
331 strUart.pu8Buf = pu8Buf;
332 strUart.u16Sz = u16Sz;
333
334 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
335 {
336 M2M_ERR("read error\n");
337 s8Ret = M2M_ERR_BUS_FAIL;
338 }
339 }
340 else
341 {
342 M2M_ERR("write error (Error sending the block read command)\n");
343 s8Ret = M2M_ERR_BUS_FAIL;
344 }
345 }
346 else
347 {
348 strUart.pu8Buf = pu8Buf;
349 strUart.u16Sz = u16Sz;
350
351 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
352 {
353 M2M_ERR("read error\n");
354 s8Ret = M2M_ERR_BUS_FAIL;
355 }
356 }
357 }
358
359 return s8Ret;
360 }
361
362 /**
363 * @fn nm_uart_write_block
364 * @brief Write block of data
365 * @param [in] u32Addr
366 * Start address
367 * @param [in] puBuf
368 * Pointer to the buffer holding the data to be written
369 * @param [in] u16Sz
370 * Number of bytes to write. The buffer size must be >= u16Sz
371 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
372 * @author Dina El Sissy
373 * @date 13 AUG 2012
374 * @version 1.0
375 */
nm_uart_write_block(uint32 u32Addr,uint8 * puBuf,uint16 u16Sz)376 sint8 nm_uart_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
377 {
378 tstrNmUartDefault strUart;
379 sint8 s8Ret = M2M_SUCCESS;
380 static uint8 au8Buf[HDR_SZ+1];
381
382 au8Buf[0] = 0xa5;
383 au8Buf[1] = 3;
384 au8Buf[2] = 0;
385 au8Buf[3] = (uint8)(u16Sz & 0x00ff);
386 au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
387 au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
388 au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
389 au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
390 au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
391 au8Buf[9] = 0;
392 au8Buf[10] = 0;
393 au8Buf[11] = 0;
394 au8Buf[12] = 0;
395
396 au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
397
398 strUart.pu8Buf = au8Buf;
399 strUart.u16Sz = sizeof(au8Buf);
400
401 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
402 {
403 M2M_ERR("write error\n");
404 s8Ret = M2M_ERR_BUS_FAIL;
405 }
406 else
407 {
408 if(!nm_bus_get_chip_type())
409 {
410 //check for the ack from the SAMD21 for the packet reception.
411 strUart.u16Sz = 1;
412 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
413 {
414 s8Ret = M2M_ERR_BUS_FAIL;
415 }
416 if(au8Buf[0] == 0xAC)
417 {
418 M2M_DBG("Successfully sent the block Write command\n");
419 strUart.pu8Buf = puBuf;
420 strUart.u16Sz = u16Sz;
421
422 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
423 {
424 M2M_ERR("write error\n");
425 s8Ret = M2M_ERR_BUS_FAIL;
426 }
427 else
428 {
429 //check for the ack from the SAMD21 for the payload reception.
430 strUart.pu8Buf = au8Buf;
431 strUart.u16Sz = 1;
432 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
433 {
434 s8Ret = M2M_ERR_BUS_FAIL;
435 }
436 if(au8Buf[0] == 0xAC)
437 {
438 M2M_DBG("Successfully sent the data payload\n");
439 }
440 else
441 {
442 M2M_ERR("write error\n");
443 s8Ret = M2M_ERR_BUS_FAIL;
444 }
445 }
446 }
447 else
448 {
449 M2M_ERR("write error (Error sending the block write command)\n");
450 s8Ret = M2M_ERR_BUS_FAIL;
451 }
452 }
453 else
454 {
455 strUart.pu8Buf = puBuf;
456 strUart.u16Sz = u16Sz;
457
458 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
459 {
460 M2M_ERR("write error\n");
461 s8Ret = M2M_ERR_BUS_FAIL;
462 }
463 }
464 }
465 return s8Ret;
466 }
467
468 /**
469 * @fn nm_uart_reconfigure
470 * @brief Reconfigures the UART interface
471 * @param [in] ptr
472 * Pointer to a DWORD containing baudrate at this moment.
473 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
474 * @author Viswanathan Murugesan
475 * @date 22 OCT 2014
476 * @version 1.0
477 */
nm_uart_reconfigure(void * ptr)478 sint8 nm_uart_reconfigure(void *ptr)
479 {
480 tstrNmUartDefault strUart;
481 sint8 s8Ret = M2M_SUCCESS;
482 uint8 b[HDR_SZ+1];
483
484 /*write reg*/
485 b[0] = 0xa5;
486 b[1] = 5;
487 b[2] = 0;
488 b[3] = 0;
489 b[4] = 0;
490 b[5] = 0;
491 b[6] = 0;
492 b[7] = 0;
493 b[8] = 0;
494 b[9] = (uint8)((*(unsigned long *)ptr) & 0x000000ff);
495 b[10] = (uint8)(((*(unsigned long *)ptr) & 0x0000ff00)>>8);
496 b[11] = (uint8)(((*(unsigned long *)ptr) & 0x00ff0000)>>16);
497 b[12] = (uint8)(((*(unsigned long *)ptr) & 0xff000000)>>24);
498
499 b[2] = get_cs(&b[1],HDR_SZ);
500
501 get_cs(&b[1],HDR_SZ);
502
503 strUart.pu8Buf = b;
504 strUart.u16Sz = sizeof(b);
505
506 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
507 {
508 M2M_ERR("write error\n");
509 s8Ret = M2M_ERR_BUS_FAIL;
510 }
511 else
512 {
513 if(!nm_bus_get_chip_type())
514 {
515 //check for the ack from the SAMD21 for the packet reception.
516 strUart.u16Sz = 1;
517 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
518 {
519 s8Ret = M2M_ERR_BUS_FAIL;
520 }
521 if(b[0] == 0xAC)
522 {
523 M2M_DBG("Successfully sent the UART reconfigure command\n");
524 }
525 else
526 {
527 M2M_ERR("write error\n");
528 s8Ret = M2M_ERR_BUS_FAIL;
529 }
530 }
531 }
532
533 return s8Ret;
534 }
535 #endif
536 /* EOF */
537
