1 //*****************************************************************************
2 //
3 //! @file am_hal_mcuctrl.c
4 //!
5 //! @brief Functions for Interfacing with the MCUCTRL.
6 //!
7 //! @addtogroup mcuctrl3p MCUCTRL - MCU Control
8 //! @ingroup apollo3p_hal
9 //! @{
10 //
11 //*****************************************************************************
12
13 //*****************************************************************************
14 //
15 // Copyright (c) 2024, Ambiq Micro, Inc.
16 // All rights reserved.
17 //
18 // Redistribution and use in source and binary forms, with or without
19 // modification, are permitted provided that the following conditions are met:
20 //
21 // 1. Redistributions of source code must retain the above copyright notice,
22 // this list of conditions and the following disclaimer.
23 //
24 // 2. Redistributions in binary form must reproduce the above copyright
25 // notice, this list of conditions and the following disclaimer in the
26 // documentation and/or other materials provided with the distribution.
27 //
28 // 3. Neither the name of the copyright holder nor the names of its
29 // contributors may be used to endorse or promote products derived from this
30 // software without specific prior written permission.
31 //
32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 // POSSIBILITY OF SUCH DAMAGE.
43 //
44 // This is part of revision release_sdk_3_2_0-dd5f40c14b of the AmbiqSuite Development Package.
45 //
46 //*****************************************************************************
47
48 #include <stdint.h>
49 #include <stdbool.h>
50 #include "am_mcu_apollo.h"
51
52 //*****************************************************************************
53 //
54 // Global Variables.
55 //
56 //*****************************************************************************
57 //
58 // Define the flash sizes from CHIPPN.
59 //
60 const uint32_t
61 g_am_hal_mcuctrl_flash_size[AM_HAL_MCUCTRL_CHIPPN_FLASH_SIZE_N] =
62 {
63 16 * 1024, /* 0x0 0x00004000 16 KB */
64 32 * 1024, /* 0x1 0x00008000 32 KB */
65 64 * 1024, /* 0x2 0x00010000 64 KB */
66 128 * 1024, /* 0x3 0x00020000 128 KB */
67 256 * 1024, /* 0x4 0x00040000 256 KB */
68 512 * 1024, /* 0x5 0x00080000 512 KB */
69 1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */
70 2 * 1024 * 1024, /* 0x7 0x00200000 2 MB */
71 3 * 1024 * 1024 / 2, /* 0x8 0x00600000 1.5 MB */
72 0, 0, 0, 0, 0, 0, 0
73 };
74
75 const uint32_t
76 g_am_hal_mcuctrl_sram_size[AM_HAL_MCUCTRL_CHIPPN_SRAM_SIZE_N] =
77 {
78 16 * 1024, /* 0x0 0x00004000 16 KB */
79 32 * 1024, /* 0x1 0x00008000 32 KB */
80 64 * 1024, /* 0x2 0x00010000 64 KB */
81 128 * 1024, /* 0x3 0x00020000 128 KB */
82 256 * 1024, /* 0x4 0x00040000 256 KB */
83 512 * 1024, /* 0x5 0x00080000 512 KB */
84 1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */
85 384 * 1024, /* 0x7 0x00200000 384 KB */
86 768 * 1024, /* 0x8 0x000C0000 768 KB */
87 0, 0, 0, 0, 0, 0, 0
88 };
89
90 // ****************************************************************************
91 //
92 // device_info_get()
93 // Gets all relevant device information.
94 //
95 // ****************************************************************************
96 static void
device_info_get(am_hal_mcuctrl_device_t * psDevice)97 device_info_get(am_hal_mcuctrl_device_t *psDevice)
98 {
99 //
100 // Read the Part Number.
101 //
102 psDevice->ui32ChipPN = MCUCTRL->CHIPPN;
103
104 //
105 // Read the Chip ID0.
106 //
107 psDevice->ui32ChipID0 = MCUCTRL->CHIPID0;
108
109 //
110 // Read the Chip ID1.
111 //
112 psDevice->ui32ChipID1 = MCUCTRL->CHIPID1;
113
114 //
115 // Read the Chip Revision.
116 //
117 psDevice->ui32ChipRev = MCUCTRL->CHIPREV;
118
119 //
120 // Read the Chip VENDOR ID.
121 //
122 psDevice->ui32VendorID = MCUCTRL->VENDORID;
123
124 //
125 // Read the SKU (new for Apollo3).
126 //
127 psDevice->ui32SKU = MCUCTRL->SKU;
128
129 //
130 // Qualified from Part Number.
131 //
132 psDevice->ui32Qualified = 1;
133
134 //
135 // Flash size from Part Number.
136 //
137 psDevice->ui32FlashSize =
138 g_am_hal_mcuctrl_flash_size[
139 (psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M) >>
140 MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S];
141
142 //
143 // SRAM size from Part Number.
144 //
145 psDevice->ui32SRAMSize =
146 g_am_hal_mcuctrl_sram_size[
147 (psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M) >>
148 MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S];
149
150 //
151 // Now, let's look at the JEDEC info.
152 // The full partnumber is 12 bits total, but is scattered across 2 registers.
153 // Bits [11:8] are 0xE.
154 // Bits [7:4] are 0xE for Apollo, 0xD for Apollo2, 0xC for Apollo3.
155 // Bits [3:0] are defined differently for Apollo and Apollo2/Apollo3.
156 // For Apollo, the low nibble is 0x0.
157 // For Apollo2/Apollo3, the low nibble indicates flash and SRAM size.
158 //
159 psDevice->ui32JedecPN = JEDEC->PID0_b.PNL8 << 0;
160 psDevice->ui32JedecPN |= JEDEC->PID1_b.PNH4 << 8;
161
162 //
163 // JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as
164 // 0x1B, with parity bit is 0x9B. It is 8 bits located across 2 registers.
165 //
166 psDevice->ui32JedecJEPID = JEDEC->PID1_b.JEPIDL << 0;
167 psDevice->ui32JedecJEPID |= JEDEC->PID2_b.JEPIDH << 4;
168
169 //
170 // CHIPREV is 8 bits located across 2 registers.
171 //
172 psDevice->ui32JedecCHIPREV = JEDEC->PID2_b.CHIPREVH4 << 4;
173 psDevice->ui32JedecCHIPREV |= JEDEC->PID3_b.CHIPREVL4 << 0;
174
175 //
176 // Let's get the Coresight ID (32-bits across 4 registers)
177 // For Apollo and Apollo2, it's expected to be 0xB105100D.
178 //
179 psDevice->ui32JedecCID = JEDEC->CID3_b.CID << 24;
180 psDevice->ui32JedecCID |= JEDEC->CID2_b.CID << 16;
181 psDevice->ui32JedecCID |= JEDEC->CID1_b.CID << 8;
182 psDevice->ui32JedecCID |= JEDEC->CID0_b.CID << 0;
183 } // device_info_get()
184
185 //*****************************************************************************
186 //
187 // mcuctrl_fault_status()
188 // Gets the fault status and capture registers.
189 //
190 //*****************************************************************************
191 static void
mcuctrl_fault_status(am_hal_mcuctrl_fault_t * psFault)192 mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault)
193 {
194 uint32_t ui32FaultStat;
195
196 //
197 // Read the Fault Status Register.
198 //
199 ui32FaultStat = MCUCTRL->FAULTSTATUS;
200 psFault->bICODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk);
201 psFault->bDCODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk);
202 psFault->bSYS = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_SYSFAULT_Msk);
203
204 //
205 // Read the DCODE fault capture address register.
206 //
207 psFault->ui32DCODE = MCUCTRL->DCODEFAULTADDR;
208
209 //
210 // Read the ICODE fault capture address register.
211 //
212 psFault->ui32ICODE |= MCUCTRL->ICODEFAULTADDR;
213
214 //
215 // Read the ICODE fault capture address register.
216 //
217 psFault->ui32SYS |= MCUCTRL->SYSFAULTADDR;
218 } // mcuctrl_fault_status()
219
220 // ****************************************************************************
221 //
222 // am_hal_mcuctrl_control()
223 // Apply various specific commands/controls on the MCUCTRL module.
224 //
225 // ****************************************************************************
226 uint32_t
am_hal_mcuctrl_control(am_hal_mcuctrl_control_e eControl,void * pArgs)227 am_hal_mcuctrl_control(am_hal_mcuctrl_control_e eControl, void *pArgs)
228 {
229 uint32_t ui32Tbl;
230
231 switch ( eControl )
232 {
233 case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE:
234 //
235 // Enable the Fault Capture registers.
236 //
237 MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 1;
238 break;
239
240 case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE:
241 //
242 // Disable the Fault Capture registers.
243 //
244 MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 0;
245 break;
246
247 case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE:
248 //
249 // Configure the bits in XTALCTRL that enable external 32KHz clock.
250 //
251 MCUCTRL->XTALCTRL &=
252 ~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk |
253 MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk |
254 MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk |
255 MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk |
256 MCUCTRL_XTALCTRL_XTALSWE_Msk);
257
258 MCUCTRL->XTALCTRL |=
259 _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP) |
260 _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE) |
261 _VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP) |
262 _VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS) |
263 _VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN);
264 break;
265
266 case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE:
267 //
268 // Configure the bits in XTALCTRL that disable external 32KHz
269 // clock, thus re-configuring for the crystal.
270 //
271 MCUCTRL->XTALCTRL &=
272 ~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk |
273 MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk |
274 MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk |
275 MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk |
276 MCUCTRL_XTALCTRL_XTALSWE_Msk);
277
278 MCUCTRL->XTALCTRL |=
279 _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP) |
280 _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE) |
281 _VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP) |
282 _VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN) |
283 _VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS);
284 break;
285
286 case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH:
287 {
288 uint32_t ui32SramPrefetch = *(uint32_t*)pArgs;
289 uint32_t ui32SetMsk, ui32ClrMsk, ui32SRAMreg;
290
291 //
292 // Validate the input flags.
293 //
294 if ( ui32SramPrefetch &
295 ~(AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR |
296 AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE |
297 AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA |
298 AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE |
299 AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR |
300 AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE |
301 AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA |
302 AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) )
303 {
304 return AM_HAL_STATUS_INVALID_ARG;
305 }
306
307
308 //
309 // Given the rule that NOxxx overrides xxx, and keeping in mind
310 // that the cache settings cannot be set unless the regular
311 // prefetch is also being set or is already set, the following
312 // truth table results.
313
314 // Note - this same TT also applies to data settings.
315 // nc=no change.
316 // I IC NI NIC: I IC
317 // 0x0: 0 0 0 0 : nc nc
318 // 0x1: 0 0 0 1 : nc 0
319 // 0x2: 0 0 1 0 : 0 0
320 // 0x3: 0 0 1 1 : 0 0
321 // 0x4: 0 1 0 0 : INVALID
322 // 0x5: 0 1 0 1 : nc nc
323 // 0x6: 0 1 1 0 : INVALID
324 // 0x7: 0 1 1 1 : 0 0
325 // 0x8: 1 0 0 0 : 1 0
326 // 0x9: 1 0 0 1 : 1 0
327 // 0xA: 1 0 1 0 : 0 0
328 // 0xB: 1 0 1 1 : 0 0
329 // 0xC: 1 1 0 0 : 1 1
330 // 0xD: 1 1 0 1 : 1 0
331 // 0xE: 1 1 1 0 : INVALID
332 // 0xF: 1 1 1 1 : 0 0
333 //
334
335 ui32Tbl = 0;
336 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR) ? (1 << 3) : 0;
337 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE) ? (1 << 2) : 0;
338 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR) ? (1 << 1) : 0;
339 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE) ? (1 << 0) : 0;
340
341 //
342 // Now augment the table entries with current register settings.
343 //
344 ui32SRAMreg = MCUCTRL->SRAMMODE;
345
346 ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_Msk ? (1 << 3) : 0;
347 ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk ? (1 << 2) : 0;
348
349 ui32SetMsk = ui32ClrMsk = 0;
350 switch ( ui32Tbl )
351 {
352 case 0x0:
353 case 0x5:
354 break;
355 case 0x1:
356 ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
357 break;
358 case 0x2:
359 case 0x3:
360 case 0x7:
361 case 0xA:
362 case 0xB:
363 case 0xF:
364 ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
365 break;
366 case 0x4:
367 case 0x6:
368 case 0xE:
369 return AM_HAL_STATUS_INVALID_OPERATION;
370 case 0x8:
371 case 0x9:
372 case 0xD:
373 ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk;
374 ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
375 break;
376 case 0xC:
377 ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk;
378 break;
379 default:
380 return AM_HAL_STATUS_INVALID_ARG;
381 } // switch()
382
383 //
384 // Now, repeat with data settings.
385 //
386 ui32Tbl = 0;
387 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA) ? (1 << 3) : 0;
388 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE) ? (1 << 2) : 0;
389 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA) ? (1 << 1) : 0;
390 ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) ? (1 << 0) : 0;
391
392 //
393 // Now augment the table entries with current register settings.
394 //
395 ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_Msk ? (1 << 3) : 0;
396 ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk ? (1 << 2) : 0;
397
398 switch ( ui32Tbl )
399 {
400 case 0x0:
401 case 0x5:
402 break;
403 case 0x1:
404 ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
405 break;
406 case 0x2:
407 case 0x3:
408 case 0x7:
409 case 0xA:
410 case 0xB:
411 case 0xF:
412 ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
413 break;
414 case 0x4:
415 case 0x6:
416 case 0xE:
417 return AM_HAL_STATUS_INVALID_OPERATION;
418 case 0x8:
419 case 0x9:
420 case 0xD:
421 ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk;
422 ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
423 break;
424 case 0xC:
425 ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk;
426 break;
427 default:
428 return AM_HAL_STATUS_INVALID_ARG;
429 } // switch()
430
431
432 //
433 // Arrange the register update such that clrmsk will have precedence
434 // over setmsk.
435 //
436 AM_CRITICAL_BEGIN
437 ui32SRAMreg = MCUCTRL->SRAMMODE;
438 ui32SRAMreg |= ui32SetMsk;
439 ui32SRAMreg &= ~ui32ClrMsk;
440 MCUCTRL->SRAMMODE = ui32SRAMreg;
441 AM_CRITICAL_END
442 } // case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH
443 break;
444
445 default:
446 return AM_HAL_STATUS_INVALID_ARG;
447 }
448
449 //
450 // Return success status.
451 //
452 return AM_HAL_STATUS_SUCCESS;
453
454 } // am_hal_mcuctrl_control()
455
456 // ****************************************************************************
457 //
458 // am_hal_mcuctrl_status_get()
459 // This function returns current status of the MCUCTRL as obtained from
460 // various registers of the MCUCTRL block.
461 //
462 // ****************************************************************************
463 uint32_t
am_hal_mcuctrl_status_get(am_hal_mcuctrl_status_t * psStatus)464 am_hal_mcuctrl_status_get(am_hal_mcuctrl_status_t *psStatus)
465 {
466 uint32_t ui32Status;
467
468 if ( psStatus == NULL )
469 {
470 return AM_HAL_STATUS_INVALID_ARG;
471 }
472
473 MCUCTRL->FEATUREENABLE_b.BLEREQ = 1;
474 MCUCTRL->FEATUREENABLE_b.BURSTREQ = 1;
475
476 ui32Status = MCUCTRL->FEATUREENABLE;
477 psStatus->bBurstAck =
478 _FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTACK, ui32Status);
479 psStatus->bBLEAck =
480 _FLD2VAL(MCUCTRL_FEATUREENABLE_BLEACK, ui32Status);
481
482 psStatus->bDebuggerLockout =
483 _FLD2VAL(MCUCTRL_DEBUGGER_LOCKOUT, MCUCTRL->DEBUGGER);
484
485 psStatus->bADCcalibrated =
486 _FLD2VAL(MCUCTRL_ADCCAL_ADCCALIBRATED, MCUCTRL->ADCCAL);
487
488 psStatus->bBattLoadEnabled =
489 _FLD2VAL(MCUCTRL_ADCBATTLOAD_BATTLOAD, MCUCTRL->ADCBATTLOAD);
490
491 ui32Status = MCUCTRL->BOOTLOADER;
492 psStatus->bSecBootOnColdRst =
493 _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOT, ui32Status);
494 psStatus->bSecBootOnWarmRst =
495 _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTONRST, ui32Status);
496
497 return AM_HAL_STATUS_SUCCESS;
498
499 } // am_hal_mcuctrl_status_get()
500
501 // ****************************************************************************
502 //
503 // am_hal_mcuctrl_info_get()
504 // Get information of the given MCUCTRL item.
505 //
506 // ****************************************************************************
507 uint32_t
am_hal_mcuctrl_info_get(am_hal_mcuctrl_infoget_e eInfoGet,void * pInfo)508 am_hal_mcuctrl_info_get(am_hal_mcuctrl_infoget_e eInfoGet, void *pInfo)
509 {
510 am_hal_mcuctrl_feature_t *psFeature;
511 uint32_t ui32Feature;
512
513 if ( pInfo == NULL )
514 {
515 return AM_HAL_STATUS_INVALID_ARG;
516 }
517
518 switch ( eInfoGet )
519 {
520 case AM_HAL_MCUCTRL_INFO_FEATURES_AVAIL:
521 psFeature = (am_hal_mcuctrl_feature_t*)pInfo;
522 ui32Feature = MCUCTRL->FEATUREENABLE;
523 psFeature->bBurstAvail =
524 _FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTAVAIL, ui32Feature);
525 psFeature->bBLEavail =
526 _FLD2VAL(MCUCTRL_FEATUREENABLE_BLEAVAIL, ui32Feature);
527
528 ui32Feature = MCUCTRL->BOOTLOADER;
529 psFeature->ui8SecBootFeature =
530 _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTFEATURE, ui32Feature);
531
532 ui32Feature = MCUCTRL->SKU;
533 psFeature->bBLEFeature =
534 _FLD2VAL(MCUCTRL_SKU_ALLOWBLE, ui32Feature);
535 psFeature->bBurstFeature =
536 _FLD2VAL(MCUCTRL_SKU_ALLOWBURST, ui32Feature);
537 break;
538
539 case AM_HAL_MCUCTRL_INFO_DEVICEID:
540 device_info_get((am_hal_mcuctrl_device_t *)pInfo);
541 break;
542
543 case AM_HAL_MCUCTRL_INFO_FAULT_STATUS:
544 mcuctrl_fault_status((am_hal_mcuctrl_fault_t*)pInfo);
545 break;
546
547 default:
548 return AM_HAL_STATUS_INVALID_ARG;
549 }
550 //
551 // Return success status.
552 //
553 return AM_HAL_STATUS_SUCCESS;
554
555 } // am_hal_mcuctrl_info_get()
556
557 //*****************************************************************************
558 //
559 // End Doxygen group.
560 //! @}
561 //
562 //*****************************************************************************
563
