1 //***************************************************************************** 2 // 3 // am_reg_jedec.h 4 //! @file 5 //! 6 //! @brief Register macros for the ARM JEDEC module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2024, Ambiq Micro, Inc. 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision release_sdk_3_2_0-dd5f40c14b of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_JEDEC_H 45 #define AM_REG_JEDEC_H 46 47 //***************************************************************************** 48 // 49 // JEDEC 50 // Instance finder. (1 instance(s) available) 51 // 52 //***************************************************************************** 53 #define AM_REG_JEDEC_NUM_MODULES 1 54 #define AM_REG_JEDECn(n) \ 55 (REG_JEDEC_BASEADDR + 0x00000000 * n) 56 57 /* ======================================== Start of section using anonymous unions ======================================== */ 58 #if defined (__CC_ARM) 59 #pragma push 60 #pragma anon_unions 61 #elif defined (__ICCARM__) 62 #pragma language = extended 63 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 64 #pragma clang diagnostic push 65 #pragma clang diagnostic ignored "-Wc11-extensions" 66 #pragma clang diagnostic ignored "-Wreserved-id-macro" 67 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 68 #pragma clang diagnostic ignored "-Wnested-anon-types" 69 #elif defined (__GNUC__) 70 /* anonymous unions are enabled by default */ 71 #elif defined (__TMS470__) 72 /* anonymous unions are enabled by default */ 73 #elif defined (__TASKING__) 74 #pragma warning 586 75 #elif defined (__CSMC__) 76 /* anonymous unions are enabled by default */ 77 #else 78 #warning Not supported compiler type 79 #endif 80 81 /** 82 \brief Structure type to access the Apollo CM4 JEDEC registers. 83 */ 84 typedef struct 85 { 86 uint32_t RESERVED0[52U]; /* 0xF00 - 0xFCF */ 87 88 union 89 { 90 __IM uint32_t PID4; /*!< 0xF0000FD0 (R/ ) PID4 Register */ 91 92 struct 93 { 94 __IM uint32_t JEPCONT : 4; /* [3..0] Contains the JEP Continuation bits. */ 95 } PID4_b; 96 }; 97 98 union 99 { 100 __IM uint32_t PID5; /*!< 0xF0000FD4 (R/ ) PID5 Register */ 101 102 struct 103 { 104 __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ 105 } PID5_b; 106 }; 107 108 union 109 { 110 __IM uint32_t PID6; /*!< 0xF0000FD8 (R/ ) PID6 Register */ 111 112 struct 113 { 114 __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ 115 } PID6_b; 116 }; 117 118 union 119 { 120 __IM uint32_t PID7; /*!< 0xF0000FDC (R/ ) PID7 Register */ 121 122 struct 123 { 124 __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ 125 } PID7_b; 126 }; 127 128 union 129 { 130 __IM uint32_t PID0; /*!< 0xF0000FE0 (R/ ) PID0 Register */ 131 132 struct 133 { 134 __IM uint32_t PNL8 : 8; /* [7..0] Contains the low 8 bits of the Ambiq Micro device part number. */ 135 } PID0_b; 136 }; 137 138 union 139 { 140 __IM uint32_t PID1; /*!< 0xF0000FE4 (R/ ) PID1 Register */ 141 142 struct 143 { 144 __IM uint32_t PNH4 : 4; /* [3..0] Contains the high 4 bits of the Ambiq Micro device part number. */ 145 __IM uint32_t JEPIDL : 4; /* [7..4] Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID is therefore 0x9B. */ 146 } PID1_b; 147 }; 148 149 union 150 { 151 __IM uint32_t PID2; /*!< 0xF0000FE8 (R/ ) PID2 Register */ 152 153 struct 154 { 155 __IM uint32_t JEPIDH : 4; /* [3..0] Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this field is hard-coded to 1. The full JEPID is therefore 0x9B. */ 156 __IM uint32_t CHIPREVH4 : 4; /* [7..4] Contains the high 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */ 157 } PID2_b; 158 }; 159 160 union 161 { 162 __IM uint32_t PID3; /*!< 0xF0000FEC (R/ ) PID3 Register */ 163 164 struct 165 { 166 __IM uint32_t ZERO : 4; /* [3..0] This field is hard-coded to 0x0. */ 167 __IM uint32_t CHIPREVL4 : 4; /* [7..0] Contains the low 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */ 168 } PID3_b; 169 }; 170 171 union 172 { 173 __IM uint32_t CID0; /*!< 0xF0000FF0 (R/ ) CID0 Register */ 174 175 struct 176 { 177 __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID0. */ 178 } CID0_b; 179 }; 180 181 union 182 { 183 __IM uint32_t CID1; /*!< 0xF0000FF4 (R/ ) CID1 Register */ 184 185 struct 186 { 187 __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID1. */ 188 } CID1_b; 189 }; 190 191 union 192 { 193 __IM uint32_t CID2; /*!< 0xF0000FF8 (R/ ) CID2 Register */ 194 195 struct 196 { 197 __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID2. */ 198 } CID2_b; 199 }; 200 201 union 202 { 203 __IM uint32_t CID3; /*!< 0xF0000FFC (R/ ) CID3 Register */ 204 205 struct 206 { 207 __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID3. */ 208 } CID3_b; 209 }; 210 } JEDEC_Type; 211 212 213 //***************************************************************************** 214 // 215 // JEDEC_PID4 - JEP Continuation Register 216 // 217 //***************************************************************************** 218 // Contains the JEP Continuation bits. 219 #define JEDEC_PID4_JEPCONT_Pos 0U 220 #define JEDEC_PID4_JEPCONT_Msk (0x0000000FUL) 221 222 //***************************************************************************** 223 // 224 // JEDEC_PID5 - JEP reserved Register 225 // 226 //***************************************************************************** 227 // Contains the value of 0x00000000. 228 #define JEDEC_PID5_VALUE_Pos 0U 229 #define JEDEC_PID5_VALUE_Msk (0xFFFFFFFFUL) 230 231 //***************************************************************************** 232 // 233 // JEDEC_PID6 - JEP reserved Register 234 // 235 //***************************************************************************** 236 // Contains the value of 0x00000000. 237 #define JEDEC_PID6_VALUE_Pos 0U 238 #define JEDEC_PID6_VALUE_Msk (0xFFFFFFFFUL) 239 240 //***************************************************************************** 241 // 242 // JEDEC_PID7 - JEP reserved Register 243 // 244 //***************************************************************************** 245 // Contains the value of 0x00000000. 246 #define JEDEC_PID7_VALUE_Pos 0U 247 #define JEDEC_PID7_VALUE_Msk (0xFFFFFFFFUL) 248 249 //***************************************************************************** 250 // 251 // JEDEC_PID0 - Ambiq Partnum low byte 252 // 253 //***************************************************************************** 254 // Contains the low 8 bits of the Ambiq Micro device part number. 255 #define JEDEC_PID0_PNL8_Pos 0U 256 #define JEDEC_PID0_PNL8_Msk (0x000000FFUL) 257 258 //***************************************************************************** 259 // 260 // JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble. 261 // 262 //***************************************************************************** 263 // Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID 264 // is therefore 0x9B. 265 #define JEDEC_PID1_JEPIDL_Pos 4U 266 #define JEDEC_PID1_JEPIDL_Msk (0x000000F0UL) 267 268 // Contains the high 4 bits of the Ambiq Micro device part number. 269 #define JEDEC_PID1_PNH4_Pos 0U 270 #define JEDEC_PID1_PNH4_Msk (0x0000000FUL) 271 272 //***************************************************************************** 273 // 274 // JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble 275 // 276 //***************************************************************************** 277 // Contains the high 4 bits of the Ambiq Micro CHIPREV (see also 278 // MCUCTRL.CHIPREV). Note that this field will change with each revision of the 279 // chip. 280 #define JEDEC_PID2_CHIPREVH4_Pos 4U 281 #define JEDEC_PID2_CHIPREVH4_Msk (0x000000F0UL) 282 283 // Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this 284 // field is hard-coded to 1. The full JEPID is therefore 0x9B. 285 #define JEDEC_PID2_JEPIDH_Pos 0U 286 #define JEDEC_PID2_JEPIDH_Msk (0x0000000FUL) 287 288 //***************************************************************************** 289 // 290 // JEDEC_PID3 - Ambiq chip revision high-nibble. 291 // 292 //***************************************************************************** 293 // Contains the low 4 bits of the Ambiq Micro CHIPREV (see also 294 // MCUCTRL.CHIPREV). Note that this field will change with each revision of the 295 // chip. 296 #define JEDEC_PID3_CHIPREVL4_Pos 4U 297 #define JEDEC_PID3_CHIPREVL4_Msk (0x000000F0UL) 298 299 // This field is hard-coded to 0x0. 300 #define JEDEC_PID3_ZERO_Pos 0U 301 #define JEDEC_PID3_ZERO_Msk (0x0000000FUL) 302 303 //***************************************************************************** 304 // 305 // JEDEC_CID0 - Coresight ROM Table. 306 // 307 //***************************************************************************** 308 // Coresight ROM Table, CID0. 309 #define JEDEC_CID0_CID_Pos 0U 310 #define JEDEC_CID0_CID_Msk (0x000000FFUL) 311 312 //***************************************************************************** 313 // 314 // JEDEC_CID1 - Coresight ROM Table. 315 // 316 //***************************************************************************** 317 // Coresight ROM Table, CID1. 318 #define JEDEC_CID1_CID_Pos 0U 319 #define JEDEC_CID1_CID_Msk (0x000000FFUL) 320 321 //***************************************************************************** 322 // 323 // JEDEC_CID2 - Coresight ROM Table. 324 // 325 //***************************************************************************** 326 // Coresight ROM Table, CID2. 327 #define JEDEC_CID2_CID_Pos 0U 328 #define JEDEC_CID2_CID_Msk (0x000000FFUL) 329 330 //***************************************************************************** 331 // 332 // JEDEC_CID3 - Coresight ROM Table. 333 // 334 //***************************************************************************** 335 // Coresight ROM Table, CID3. 336 #define JEDEC_CID3_CID_Pos 0U 337 #define JEDEC_CID3_CID_Msk (0x000000FFUL) 338 339 340 341 342 #define JEDEC_BASE (0xF0000F00UL) /*!< JEDEC Base Address */ 343 344 #define JEDEC ((JEDEC_Type *) JEDEC_BASE ) /*!< JEDEC configuration struct */ 345 346 347 /* ========================================= End of section using anonymous unions ========================================= */ 348 #if defined (__CC_ARM) 349 #pragma pop 350 #elif defined (__ICCARM__) 351 /* leave anonymous unions enabled */ 352 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 353 #pragma clang diagnostic pop 354 #elif defined (__GNUC__) 355 /* anonymous unions are enabled by default */ 356 #elif defined (__TMS470__) 357 /* anonymous unions are enabled by default */ 358 #elif defined (__TASKING__) 359 #pragma warning restore 360 #elif defined (__CSMC__) 361 /* anonymous unions are enabled by default */ 362 #endif 363 364 365 366 #endif // AM_REG_JEDEC_H 367
