1 //***************************************************************************** 2 // 3 //! @file am_hal_ios.h 4 //! 5 //! @brief Functions for Interfacing with the IO Slave module 6 //! 7 //! @addtogroup ios3 IOS - IO Slave (SPI/I2C) 8 //! @ingroup apollo3_hal 9 //! @{ 10 // 11 //***************************************************************************** 12 13 //***************************************************************************** 14 // 15 // Copyright (c) 2024, Ambiq Micro, Inc. 16 // All rights reserved. 17 // 18 // Redistribution and use in source and binary forms, with or without 19 // modification, are permitted provided that the following conditions are met: 20 // 21 // 1. Redistributions of source code must retain the above copyright notice, 22 // this list of conditions and the following disclaimer. 23 // 24 // 2. Redistributions in binary form must reproduce the above copyright 25 // notice, this list of conditions and the following disclaimer in the 26 // documentation and/or other materials provided with the distribution. 27 // 28 // 3. Neither the name of the copyright holder nor the names of its 29 // contributors may be used to endorse or promote products derived from this 30 // software without specific prior written permission. 31 // 32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 // POSSIBILITY OF SUCH DAMAGE. 43 // 44 // This is part of revision release_sdk_3_2_0-dd5f40c14b of the AmbiqSuite Development Package. 45 // 46 //***************************************************************************** 47 #ifndef AM_HAL_IOS_H 48 #define AM_HAL_IOS_H 49 50 #ifdef __cplusplus 51 extern "C" 52 { 53 #endif 54 55 //***************************************************************************** 56 // 57 //! CMSIS-style macro for handling a variable IOS module number. 58 // 59 #define IOSLAVEn(n) ((IOSLAVE_Type*)(IOSLAVE_BASE + (n * (IOSLAVE_BASE - IOSLAVE_BASE)))) 60 //***************************************************************************** 61 62 //***************************************************************************** 63 // 64 //! @name Interface Configuration 65 //! @brief Macro definitions for configuring the physical interface of the IO 66 //! Slave 67 //! 68 //! These macros may be used with the am_hal_ios_config_t structure to set the 69 //! physical parameters of the SPI/I2C slave module. 70 //! 71 //! @{ 72 // 73 //***************************************************************************** 74 #define AM_HAL_IOS_USE_SPI _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_SPI) 75 #define AM_HAL_IOS_SPIMODE_0 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3) 76 #define AM_HAL_IOS_SPIMODE_1 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2) 77 #define AM_HAL_IOS_SPIMODE_2 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2) 78 #define AM_HAL_IOS_SPIMODE_3 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3) 79 80 #define AM_HAL_IOS_USE_I2C _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_I2C) 81 #define AM_HAL_IOS_I2C_ADDRESS(n) _VAL2FLD(IOSLAVE_CFG_I2CADDR, n) 82 83 #define AM_HAL_IOS_LSB_FIRST _VAL2FLD(IOSLAVE_CFG_LSB, 1) 84 //! @} 85 86 //***************************************************************************** 87 // 88 //! @name Register Access Interrupts 89 //! @brief Macro definitions for register access interrupts. 90 //! 91 //! These macros may be used with any of the 92 //! 93 //! @{ 94 // 95 //***************************************************************************** 96 #define AM_HAL_IOS_ACCESS_INT_00 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 31) 97 #define AM_HAL_IOS_ACCESS_INT_01 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 30) 98 #define AM_HAL_IOS_ACCESS_INT_02 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 29) 99 #define AM_HAL_IOS_ACCESS_INT_03 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 28) 100 #define AM_HAL_IOS_ACCESS_INT_04 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 27) 101 #define AM_HAL_IOS_ACCESS_INT_05 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 26) 102 #define AM_HAL_IOS_ACCESS_INT_06 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 25) 103 #define AM_HAL_IOS_ACCESS_INT_07 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 24) 104 #define AM_HAL_IOS_ACCESS_INT_08 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 23) 105 #define AM_HAL_IOS_ACCESS_INT_09 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 22) 106 #define AM_HAL_IOS_ACCESS_INT_0A _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 21) 107 #define AM_HAL_IOS_ACCESS_INT_0B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 20) 108 #define AM_HAL_IOS_ACCESS_INT_0C _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 19) 109 #define AM_HAL_IOS_ACCESS_INT_0D _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 18) 110 #define AM_HAL_IOS_ACCESS_INT_0E _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 17) 111 #define AM_HAL_IOS_ACCESS_INT_0F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 16) 112 #define AM_HAL_IOS_ACCESS_INT_13 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 15) 113 #define AM_HAL_IOS_ACCESS_INT_17 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 14) 114 #define AM_HAL_IOS_ACCESS_INT_1B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 13) 115 #define AM_HAL_IOS_ACCESS_INT_1F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 12) 116 #define AM_HAL_IOS_ACCESS_INT_23 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 11) 117 #define AM_HAL_IOS_ACCESS_INT_27 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 10) 118 #define AM_HAL_IOS_ACCESS_INT_2B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 9) 119 #define AM_HAL_IOS_ACCESS_INT_2F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 8) 120 #define AM_HAL_IOS_ACCESS_INT_33 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 7) 121 #define AM_HAL_IOS_ACCESS_INT_37 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 6) 122 #define AM_HAL_IOS_ACCESS_INT_3B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 5) 123 #define AM_HAL_IOS_ACCESS_INT_3F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 4) 124 #define AM_HAL_IOS_ACCESS_INT_43 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 3) 125 #define AM_HAL_IOS_ACCESS_INT_47 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 2) 126 #define AM_HAL_IOS_ACCESS_INT_4B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 1) 127 #define AM_HAL_IOS_ACCESS_INT_4F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 0) 128 #define AM_HAL_IOS_ACCESS_INT_ALL 0xFFFFFFFF 129 //! @} 130 131 //***************************************************************************** 132 // 133 //! @name I/O Slave Interrupts 134 //! @brief Macro definitions for I/O slave (IOS) interrupts. 135 //! 136 //! These macros may be used with any of the 137 //! 138 //! @{ 139 // 140 //***************************************************************************** 141 #define AM_HAL_IOS_INT_FSIZE IOSLAVE_INTEN_FSIZE_Msk 142 #define AM_HAL_IOS_INT_FOVFL IOSLAVE_INTEN_FOVFL_Msk 143 #define AM_HAL_IOS_INT_FUNDFL IOSLAVE_INTEN_FUNDFL_Msk 144 #define AM_HAL_IOS_INT_FRDERR IOSLAVE_INTEN_FRDERR_Msk 145 #define AM_HAL_IOS_INT_GENAD IOSLAVE_INTEN_GENAD_Msk 146 #define AM_HAL_IOS_INT_IOINTW IOSLAVE_INTEN_IOINTW_Msk 147 #define AM_HAL_IOS_INT_XCMPWR IOSLAVE_INTEN_XCMPWR_Msk 148 #define AM_HAL_IOS_INT_XCMPWF IOSLAVE_INTEN_XCMPWF_Msk 149 #define AM_HAL_IOS_INT_XCMPRR IOSLAVE_INTEN_XCMPRR_Msk 150 #define AM_HAL_IOS_INT_XCMPRF IOSLAVE_INTEN_XCMPRF_Msk 151 #define AM_HAL_IOS_INT_ALL 0xFFFFFFFF 152 //! @} 153 154 //***************************************************************************** 155 // 156 //! @name I/O Slave Interrupts triggers 157 //! @brief Macro definitions for I/O slave (IOS) interrupts. 158 //! 159 //! These macros may be used with am_hal_ios_interrupt_set and am_hal_ios_interrupt_clear 160 //! 161 //! @{ 162 // 163 //***************************************************************************** 164 #define AM_HAL_IOS_IOINTCTL_INT0 (0x01) 165 #define AM_HAL_IOS_IOINTCTL_INT1 (0x02) 166 #define AM_HAL_IOS_IOINTCTL_INT2 (0x04) 167 #define AM_HAL_IOS_IOINTCTL_INT3 (0x08) 168 #define AM_HAL_IOS_IOINTCTL_INT4 (0x10) 169 #define AM_HAL_IOS_IOINTCTL_INT5 (0x20) 170 //! @} 171 172 //***************************************************************************** 173 // 174 // External variable definitions 175 // 176 //***************************************************************************** 177 178 //***************************************************************************** 179 // 180 //! @brief LRAM pointer 181 //! 182 //! Pointer to the base of the IO Slave LRAM. 183 // 184 //***************************************************************************** 185 extern volatile uint8_t * const am_hal_ios_pui8LRAM; 186 187 //***************************************************************************** 188 // 189 //! @brief Configuration structure for the IO slave module. 190 //! 191 //! This structure may be used along with the am_hal_ios_config() function to 192 //! select key parameters of the IO Slave module. See the descriptions of each 193 //! parameter within this structure for more information on what they control. 194 // 195 //***************************************************************************** 196 typedef struct 197 { 198 // 199 //! Interface Selection 200 //! 201 //! This word selects the physical behavior of the IO Slave port. For SPI 202 //! mode, this word should be the logical OR of one or more of the 203 //! following: 204 //! 205 //! - AM_HAL_IOS_USE_SPI 206 //! - AM_HAL_IOS_SPIMODE_0 207 //! - AM_HAL_IOS_SPIMODE_1 208 //! - AM_HAL_IOS_SPIMODE_2 209 //! - AM_HAL_IOS_SPIMODE_3 210 //! 211 //! For I2C mode, use the logical OR of one or more of these values instead 212 //! (where n is the 7 or 10-bit I2C address to use): 213 //! 214 //! - AM_HAL_IOS_USE_I2C 215 //! - AM_HAL_IOS_I2C_ADDRESS(n) 216 //! 217 //! Also, in any mode, you may OR in this value to reverse the order of 218 //! incoming data bits. 219 //! 220 //! - AM_HAL_IOS_LSB_FIRST 221 // 222 uint32_t ui32InterfaceSelect; 223 224 // 225 //! Read-Only section 226 //! 227 //! The IO Slave LRAM is split into three main sections. The first section 228 //! is a "Direct Write" section, which may be accessed for reads or write 229 //! either directly through the Apollo CPU, or over the SPI/I2C bus. The 230 //! "Direct Write" section always begins at LRAM offset 0x0. At the end of 231 //! the normal "Direct Write" space, there is a "Read Only" space, which is 232 //! read/write accessible to the Apollo CPU, but read-only over the I2C/SPI 233 //! Bus. This word selects the base address of this "Read Only" space. 234 //! 235 //! This value may be set to any multiple of 8 between 0x0 and 0x78, 236 //! inclusive. For the configuration to be valid, \e ui32ROBase must also 237 //! be less than or equal to \e ui32FIFOBase 238 //! 239 //! @note The address given here is in units of BYTES. Since the location 240 //! of the "Read Only" space may only be set in 8-byte increments, this 241 //! value must be a multiple of 8. 242 //! 243 //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions 244 //! will shift right by 8 internally. 245 // 246 uint32_t ui32ROBase; 247 248 // 249 //! FIFO section 250 //! 251 //! After the "Direct Access" and "Read Only" sections is a section of LRAM 252 //! allocated to a FIFO. This section is accessible by the Apollo CPU 253 //! through the FIFO control registers, and accessible on the SPI/I2C bus 254 //! through the 0x7F address. This word selects the base address of the 255 //! FIFO space. The FIFO will extend from the address specified here to the 256 //! address specified in \e ui32RAMBase. 257 //! 258 //! This value may be set to any multiple of 8 between 0x0 and 0x78, 259 //! inclusive. For the configuration to be valid, \e ui32FIFOBase must also 260 //! be greater than or equal to \e ui32ROBase. 261 //! 262 //! @note The address given here is in units of BYTES. Since the location 263 //! of the "FIFO" space may only be set in 8-byte increments, this value 264 //! must be a multiple of 8. 265 //! 266 //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions 267 //! will shift right by 8 internally. 268 // 269 uint32_t ui32FIFOBase; 270 271 // 272 //! RAM section 273 //! 274 //! At the end of the IOS LRAM, the user may allocate a "RAM" space that 275 //! can only be accessed by the Apollo CPU. This space will not interact 276 //! with the SPI/I2C bus at all, and may be used as general-purpose memory. 277 //! Unlike normal SRAM, this section of LRAM will retain its state through 278 //! Deep Sleep, so it may be used as a data retention space for 279 //! ultra-low-power applications. 280 //! 281 //! This value may be set to any multiple of 8 between 0x0 and 0x100, 282 //! inclusive. For the configuration to be valid, \e ui32RAMBase must also 283 //! be greater than or equal to \e ui32FIFOBase. 284 //! 285 //! @note The address given here is in units of BYTES. Since the location 286 //! of the "FIFO" space may only be set in 8-byte increments, this value 287 //! must be a multiple of 8. 288 //! 289 //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions 290 //! will shift right by 8 internally. 291 // 292 uint32_t ui32RAMBase; 293 294 // 295 //! FIFO threshold 296 //! 297 //! The IO Slave module will trigger an interrupt when the number of 298 //! entries in the FIFO drops below this number of bytes. 299 // 300 uint32_t ui32FIFOThreshold; 301 302 // 303 //! Pointer to an SRAM 304 // 305 uint8_t *pui8SRAMBuffer; 306 uint32_t ui32SRAMBufferCap; 307 } 308 am_hal_ios_config_t; 309 310 typedef enum 311 { 312 //! Request with arg 313 AM_HAL_IOS_REQ_HOST_INTSET = 0, 314 AM_HAL_IOS_REQ_HOST_INTCLR, 315 AM_HAL_IOS_REQ_HOST_INTGET, 316 AM_HAL_IOS_REQ_HOST_INTEN_GET, 317 AM_HAL_IOS_REQ_READ_GADATA, 318 AM_HAL_IOS_REQ_ARG_MAX, 319 320 //! Request without arg 321 AM_HAL_IOS_REQ_READ_POLL = AM_HAL_IOS_REQ_ARG_MAX, 322 AM_HAL_IOS_REQ_FIFO_UPDATE_CTR, 323 AM_HAL_IOS_REQ_FIFO_BUF_CLR, 324 AM_HAL_IOS_REQ_MAX 325 } am_hal_ios_request_e; 326 327 typedef struct 328 { 329 uint8_t *pui8Data; 330 volatile uint32_t ui32WriteIndex; 331 volatile uint32_t ui32ReadIndex; 332 volatile uint32_t ui32Length; 333 uint32_t ui32Capacity; 334 }am_hal_ios_buffer_t; 335 336 //***************************************************************************** 337 // 338 // External function definitions 339 // 340 //***************************************************************************** 341 342 //***************************************************************************** 343 // 344 //! @brief IOS uninitialize function 345 //! 346 //! @param pHandle 347 //! @return uint32_t 348 // 349 //***************************************************************************** 350 extern uint32_t am_hal_ios_uninitialize(void *pHandle); 351 352 //***************************************************************************** 353 // 354 //! @brief IOS initialization function 355 //! 356 //! @param ui32Module 357 //! @param ppHandle 358 //! @return uint32_t 359 // 360 //***************************************************************************** 361 extern uint32_t am_hal_ios_initialize(uint32_t ui32Module, void **ppHandle); 362 363 //***************************************************************************** 364 // 365 //! @brief IOS enable function 366 //! 367 //! @param pHandle 368 //! @return uint32_t 369 // 370 //***************************************************************************** 371 extern uint32_t am_hal_ios_enable(void *pHandle); 372 373 //***************************************************************************** 374 // 375 //! @brief IOS disable function 376 //! 377 //! @param pHandle 378 //! @return uint32_t 379 // 380 //***************************************************************************** 381 extern uint32_t am_hal_ios_disable(void *pHandle); 382 383 // the following interrupts go back to the NVIC 384 385 //***************************************************************************** 386 // 387 //! @brief 388 //! 389 //! @param pHandle 390 //! @param psConfig 391 //! @return uint32_t 392 // 393 //***************************************************************************** 394 extern uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig); 395 396 //***************************************************************************** 397 // 398 //! @brief IOS enable interrupts function 399 //! 400 //! @param pHandle 401 //! @param ui32IntMask 402 //! @return uint32_t 403 // 404 //***************************************************************************** 405 extern uint32_t am_hal_ios_interrupt_enable(void *pHandle, uint32_t ui32IntMask); 406 407 //***************************************************************************** 408 // 409 //! @brief IOS disable interrupts function 410 //! 411 //! @param pHandle 412 //! @param ui32IntMask 413 //! @return uint32_t 414 // 415 //***************************************************************************** 416 extern uint32_t am_hal_ios_interrupt_disable(void *pHandle, uint32_t ui32IntMask); 417 418 //***************************************************************************** 419 // 420 //! @brief IOS interrupt clear 421 //! 422 //! @param pHandle 423 //! @param ui32IntMask 424 //! @return uint32_t 425 // 426 //***************************************************************************** 427 extern uint32_t am_hal_ios_interrupt_clear(void *pHandle, uint32_t ui32IntMask); 428 429 //***************************************************************************** 430 // 431 //! @brief IOS get interrupt status 432 //! 433 //! @param pHandle 434 //! @param bEnabledOnly 435 //! @param pui32IntStatus 436 //! @return uint32_t 437 // 438 //***************************************************************************** 439 extern uint32_t am_hal_ios_interrupt_status_get(void *pHandle, bool bEnabledOnly, uint32_t *pui32IntStatus); 440 441 //***************************************************************************** 442 // 443 //! @brief IOS interrupt service routine 444 //! 445 //! @param pHandle 446 //! @param ui32IntMask 447 //! @return uint32_t 448 // 449 //***************************************************************************** 450 extern uint32_t am_hal_ios_interrupt_service(void *pHandle, uint32_t ui32IntMask); 451 452 //***************************************************************************** 453 // 454 //! @brief Writes the specified number of bytes to the IOS fifo. 455 //! 456 //! @param pHandle - IOS handle 457 //! @param pui8Data - pointer to the data to be written to the fifo. 458 //! @param ui32NumBytes - the number of bytes to send. 459 //! @param pui32WrittenBytes -number of bytes written (could be less than ui32NumBytes, if not enough space) 460 //! 461 //! This function will write data from the caller-provided array to the IOS 462 //! LRAM FIFO. If there is no space in the LRAM FIFO, the data will be copied 463 //! to a temporary SRAM buffer instead. 464 //! 465 //! The maximum message size for the IO Slave is 1023 bytes. 466 //! 467 //! @note In order for SRAM copy operations in the function to work correctly, 468 //! the \e am_hal_ios_buffer_service() function must be called in the ISR for 469 //! the ioslave module. 470 //! 471 //! @return success or error code 472 // 473 //***************************************************************************** 474 extern uint32_t am_hal_ios_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32WrittenBytes); 475 476 //***************************************************************************** 477 // 478 //! @brief Check the amount of space used in the FIFO 479 //! 480 //! @param pHandle - IOS handle 481 //! @param pui32UsedSpace is bytes used in the Overall FIFO. 482 //! 483 //! This function returns the available data in the overall FIFO yet to be 484 //! read by the host. This takes into account the SRAM buffer and hardware FIFO 485 //! 486 //! @return success or error code 487 // 488 //***************************************************************************** 489 extern uint32_t am_hal_ios_fifo_space_used(void *pHandle, uint32_t *pui32UsedSpace); 490 491 //***************************************************************************** 492 // 493 //! @brief Check the amount of space left in the FIFO 494 //! 495 //! @param pHandle - IOS handle 496 //! @param pui32LeftSpace is bytes left in the Overall FIFO. 497 //! 498 //! This function returns the available space in the overall FIFO to accept 499 //! new data. This takes into account the SRAM buffer and hardware FIFO 500 //! 501 //! @return success or error code 502 // 503 //***************************************************************************** 504 extern uint32_t am_hal_ios_fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace); 505 506 //***************************************************************************** 507 // 508 //! @brief IOS power control function 509 //! 510 //! @param pHandle 511 //! @param ePowerState 512 //! @param bRetainState 513 //! @return uint32_t 514 // 515 //***************************************************************************** 516 extern uint32_t am_hal_ios_power_ctrl(void *pHandle, am_hal_sysctrl_power_state_e ePowerState, bool bRetainState); 517 518 //***************************************************************************** 519 // 520 //! @brief IOS control function 521 //! 522 //! @param pHandle - handle for the IOS. 523 //! @param eReq - device specific special request code. 524 //! @param pArgs - pointer to the request specific arguments. 525 //! 526 //! This function allows advanced settings 527 //! 528 //! @return success or error code 529 // 530 //***************************************************************************** 531 extern uint32_t am_hal_ios_control(void *pHandle, am_hal_ios_request_e eReq, void *pArgs); 532 533 534 #ifdef __cplusplus 535 } 536 #endif 537 538 #endif // AM_HAL_IOS_H 539 540 //***************************************************************************** 541 // 542 // End Doxygen group. 543 //! @} 544 // 545 //***************************************************************************** 546
