1 //*****************************************************************************
2 //
3 //! @file am_util_regdump.c
4 //!
5 //! @brief Dump specified registers for debug purposes.
6 //!
7 //! This module contains functions for real time (debug) printing of registers
8 //! from peripherals specified in a given bitmask.
9 //!
10 //! @addtogroup regdump RegDump - Debug Functionality
11 //! @ingroup utils
12 //! @{
13 //
14 //*****************************************************************************
15
16 //*****************************************************************************
17 //
18 // Copyright (c) 2023, Ambiq Micro, Inc.
19 // All rights reserved.
20 //
21 // Redistribution and use in source and binary forms, with or without
22 // modification, are permitted provided that the following conditions are met:
23 //
24 // 1. Redistributions of source code must retain the above copyright notice,
25 // this list of conditions and the following disclaimer.
26 //
27 // 2. Redistributions in binary form must reproduce the above copyright
28 // notice, this list of conditions and the following disclaimer in the
29 // documentation and/or other materials provided with the distribution.
30 //
31 // 3. Neither the name of the copyright holder nor the names of its
32 // contributors may be used to endorse or promote products derived from this
33 // software without specific prior written permission.
34 //
35 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
36 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
39 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
40 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
41 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
42 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
43 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
44 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
45 // POSSIBILITY OF SUCH DAMAGE.
46 //
47 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package.
48 //
49 //*****************************************************************************
50 #include <stdint.h>
51 #include <stdbool.h>
52
53 #include "am_util_regdump.h"
54 #include "am_util_stdio.h"
55
56
57 //*****************************************************************************
58 //
59 // Register dump structure.
60 //
61 //*****************************************************************************
62 typedef struct
63 {
64 //
65 //! Set to 1 to operate this timer as a 32-bit timer instead of two 16-bit
66 //! timers.
67 //
68 uint32_t ui32Offset;
69
70 //
71 //! Configuration options for TIMERA
72 //
73 char *pi8RegName;
74 //uint8_t *puiRegName;
75 }
76 am_util_regdump_t;
77
78
79 //*****************************************************************************
80 //
81 // Globals.
82 //
83 //*****************************************************************************
84 static uint8_t g_ui8Fmt[64];
85
86 am_util_regdump_t g_sRegdumpADC[] =
87 {
88 {0x000, "CFG"},
89 {0x004, "STAT"},
90 {0x008, "SWT"},
91 {0x00C, "SL0CFG"},
92 {0x010, "SL1CFG"},
93 {0x014, "SL2CFG"},
94 {0x018, "SL3CFG"},
95 {0x01C, "SL4CFG"},
96 {0x020, "SL5CFG"},
97 {0x024, "SL6CFG"},
98 {0x028, "SL7CFG"},
99 {0x02C, "WULIM"},
100 {0x030, "WLLIM"},
101 #if INCLUDE_REGS_WITH_SIDE_EFFECT
102 {0x038, "FIFO"},
103 #endif // INCLUDE_REGS_WITH_SIDE_EFFECT
104 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
105 {0x03C, "FIFOPR"},
106 #endif // AM_PART_APOLLO3
107 {0x200, "INTEN"},
108 {0x204, "INTSTAT"},
109 {0x208, "INTCLR"},
110 {0x20C, "INTSET"},
111 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
112 {0x280, "DMACFG"},
113 {0x288, "DMATOTCOUNT"},
114 {0x28C, "DMATARGADDR"},
115 {0x290, "DMASTAT"},
116 #endif // AM_PART_APOLLO3
117 {0xFFFFFFFF, NULL}
118 };
119
120 am_util_regdump_t g_sRegdumpCACHECTRL[] =
121 {
122 {0x000, "CACHECFG"},
123 {0x004, "FLASHCFG"},
124 {0x008, "CTRL"},
125 {0x010, "NCR0START"},
126 {0x014, "NCR0END"},
127 {0x018, "NCR1START"},
128 {0x01C, "NCR1END"},
129 {0x030, "CACHEMODE"},
130 {0x040, "DMON0"},
131 {0x044, "DMON1"},
132 {0x048, "DMON2"},
133 {0x04C, "DMON3"},
134 {0x050, "IMON0"},
135 {0x054, "IMON1"},
136 {0x058, "IMON2"},
137 {0x05C, "IMON3"},
138 {0xFFFFFFFF, NULL}
139 };
140
141 am_util_regdump_t g_sRegdumpCLKGEN[] =
142 {
143 {0x000, "CALXT"},
144 {0x004, "CALRC"},
145 {0x008, "ACALCTR"},
146 {0x00C, "OCTRL"},
147 {0x010, "CLKOUT"},
148 {0x014, "CLKKEY"},
149 {0x018, "CCTRL"},
150 {0x01C, "STATUS"},
151 {0x020, "HFADJ"},
152 {0x024, "HFVAL"},
153 {0x028, "CLOCKEN"},
154 {0x02C, "CLOCKEN2"},
155 {0x030, "CLOCKEN3"},
156 {0x034, "UARTEN"},
157 {0x100, "INTEN"},
158 {0x104, "INTSTAT"},
159 {0x108, "INTCLR"},
160 {0x10C, "INTSET"},
161 {0xFFFFFFFF, NULL}
162 };
163
164 am_util_regdump_t g_sRegdumpCTIMER[] =
165 {
166 {0x000, "TMR0"},
167 {0x004, "CMPRA0"},
168 {0x008, "CMPRB0"},
169 {0x00C, "CTRL0"},
170 {0x010, "TMR1"},
171 {0x014, "CMPRA1"},
172 {0x018, "CMPRB1"},
173 {0x01C, "CTRL1"},
174 {0x020, "TMR2"},
175 {0x024, "CMPRA2"},
176 {0x028, "CMPRB2"},
177 {0x02C, "CTRL2"},
178 {0x030, "TMR3"},
179 {0x034, "CMPRA3"},
180 {0x038, "CMPRB3"},
181 {0x03C, "CTRL3"},
182 {0x100, "STCFG"},
183 {0x104, "STTMR"},
184 {0x108, "CAPTURE_CONTROL"},
185 {0x110, "SCMPR0"},
186 {0x114, "SCMPR1"},
187 {0x118, "SCMPR2"},
188 {0x11C, "SCMPR3"},
189 {0x120, "SCMPR4"},
190 {0x124, "SCMPR5"},
191 {0x128, "SCMPR6"},
192 {0x12C, "SCMPR7"},
193 {0x1E0, "SCAPT0"},
194 {0x1E4, "SCAPT1"},
195 {0x1E8, "SCAPT2"},
196 {0x1EC, "SCAPT3"},
197 {0x1F0, "SNVR0"},
198 {0x1F4, "SNVR1"},
199 {0x1F8, "SNVR2"},
200 {0x200, "INTEN"},
201 {0x204, "INTSTAT"},
202 {0x208, "INTCLR"},
203 {0x20C, "INTSET"},
204 {0x300, "STMINTEN"},
205 {0x304, "STMINTSTAT"},
206 {0x308, "STMINTCLR"},
207 {0x30C, "STMINTSET"},
208 {0xFFFFFFFF, NULL}
209 };
210
211
212 am_util_regdump_t g_sRegdumpIOS[] =
213 {
214 #if INCLUDE_REGS_WITH_SIDE_EFFECT
215 {0x000, "FIFO"},
216 #endif // INCLUDE_REGS_WITH_SIDE_EFFECT
217 {0x100, "FIFOPTR"},
218 {0x104, "FIFOCFG"},
219 {0x108, "FIFOTHR"},
220 {0x10C, "FUPD"},
221 {0x110, "FIFOCTR"},
222 {0x114, "FIFOINC"},
223 {0x118, "CFG"},
224 {0x11C, "PRENC"},
225 {0x120, "INTCTLC"},
226 {0x124, "GENADD"},
227 {0x200, "INTEN"},
228 {0x204, "INTSTAT"},
229 {0x208, "INTCLR"},
230 {0x20C, "INTSET"},
231 {0x210, "REGACCINTEN"},
232 {0x214, "REGACCINTSTAT"},
233 {0x218, "REGACCINTCLR"},
234 {0x21C, "REGACCINTSET"},
235 {0xFFFFFFFF, NULL}
236 };
237
238 am_util_regdump_t g_sRegdumpGPIO[] =
239 {
240 {0x000, "PADREGA"},
241 {0x004, "PADREGB"},
242 {0x008, "PADREGC"},
243 {0x00C, "PADREGD"},
244 {0x010, "PADREGE"},
245 {0x014, "PADREGF"},
246 {0x018, "PADREGG"},
247 {0x01C, "PADREGH"},
248 {0x020, "PADREGI"},
249 {0x024, "PADREGJ"},
250 {0x028, "PADREGK"},
251 {0x02C, "PADREGL"},
252 {0x030, "PADREGM"},
253 {0x040, "CFGA"},
254 {0x044, "CFGB"},
255 {0x048, "CFGC"},
256 {0x04C, "CFGD"},
257 {0x050, "CFGE"},
258 {0x054, "CFGF"},
259 {0x058, "CFGG"},
260 {0x060, "PADKEY"},
261 {0x080, "RDA"},
262 {0x084, "RDB"},
263 {0x088, "WTA"},
264 {0x08C, "WTB"},
265 {0x090, "WTSA"},
266 {0x094, "WTSB"},
267 {0x098, "WTCA"},
268 {0x09C, "WTCB"},
269 {0x0A0, "ENA"},
270 {0x0A4, "ENB"},
271 {0x0A8, "ENSA"},
272 {0x0Ac, "ENSB"},
273 {0x0B4, "ENCA"},
274 {0x0B8, "ENCB"},
275 {0x0BC, "STMRCAP"},
276 {0x0C0, "IOM0IRQ"},
277 {0x0C4, "IOM1IRQ"},
278 {0x0C8, "IOM2IRQ"},
279 {0x0CC, "IOM3IRQ"},
280 {0x0D0, "IOM4IRQ"},
281 {0x0D4, "IOM5IRQ"},
282 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
283 {0x0D8, "BLEIFIRQ"},
284 #else
285 {0x0D8, "LOOPBACK"},
286 #endif // AM_PART_APOLLO3
287 {0x0DC, "OBS"},
288 {0x0E0, "ALTPADCFGA"},
289 {0x0E4, "ALTPADCFGB"},
290 {0x0E8, "ALTPADCFGC"},
291 {0x0EC, "ALTPADCFGD"},
292 {0x0F0, "ALTPADCFGE"},
293 {0x0F4, "ALTPADCFGF"},
294 {0x0F8, "ALTPADCFGG"},
295 {0x0FC, "ALTPADCFGH"},
296 {0x100, "ALTPADCFGI"},
297 {0x104, "ALTPADCFGJ"},
298 {0x108, "ALTPADCFGK"},
299 {0x10C, "ALTPADCFGL"},
300 {0x110, "ALTPADCFGM"},
301 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
302 {0x114, "SCDET"},
303 {0x118, "CTENCFG"},
304 #endif // AM_PART_APOLLO3
305 {0x200, "INT0EN"},
306 {0x204, "INT0STAT"},
307 {0x208, "INT0CLR"},
308 {0x20C, "INT0SET"},
309 {0x210, "INT1EN"},
310 {0x214, "INT1STAT"},
311 {0x218, "INT1CLR"},
312 {0x21C, "INT1SET"},
313 {0xFFFFFFFF, NULL}
314 };
315
316 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
317 am_util_regdump_t g_sRegdumpIOM[] =
318 {
319 #if INCLUDE_REGS_WITH_SIDE_EFFECT
320 {0x000, "FIFO"},
321 #endif // INCLUDE_REGS_WITH_SIDE_EFFECT
322 {0x100, "FIFOPTR"},
323 {0x104, "FIFOTHR"},
324 {0x108, "FIFOPOP"},
325 {0x10C, "FIFOPUSH"},
326 {0x110, "FIFOCFG"},
327 {0x114, "FIFOLOC"},
328 {0x200, "INTEN"},
329 {0x204, "INTSTAT"},
330 {0x208, "INTCLR"},
331 {0x20C, "INTSET"},
332 {0x210, "CLKCFG"},
333 {0x214, "SUBMODCTRL"},
334 {0x218, "CMD"},
335 {0x21C, "CMDRPT"},
336 {0x220, "OFFSETHI"},
337 {0x224, "CMDSTAT"},
338 {0x240, "DMATRIGEN"},
339 {0x244, "DMATRIGSTAT"},
340 {0x280, "DMACFG"},
341 {0x288, "DMATOTCOUNT"},
342 {0x28C, "DMATARGADDR"},
343 {0x290, "DMASTAT"},
344 {0x294, "CQCFG"},
345 {0x298, "CQADDR"},
346 {0x29C, "CQSTAT"},
347 {0x2A0, "CQFLAGS"},
348 {0x2A4, "CQSETCLEAR"},
349 {0x2A8, "CQPAUSEEN"},
350 {0x2AC, "CQCURIDX"},
351 {0x2B0, "CQENDIDX"},
352 {0x2B4, "STATUS"},
353 {0x300, "MSPICFG"},
354 {0x400, "MI2CCFG"},
355 {0x404, "DEVCFG"},
356 {0x410, "IOMDBG"},
357 {0xFFFFFFFF, NULL} // 36 registers visible (including FIFO)
358 };
359
360 am_util_regdump_t g_sRegdumpPDM[] =
361 {
362 {0x000, "PCFG"},
363 {0x004, "VCFG"},
364 {0x008, "VOICESTAT"},
365 #if INCLUDE_REGS_WITH_SIDE_EFFECT
366 {0x00C, "FIFOREAD"},
367 #endif // INCLUDE_REGS_WITH_SIDE_EFFECT
368 {0x010, "FIFOFLUSH"},
369 {0x014, "FIFOFTHR"},
370 {0x200, "INTEN"},
371 {0x204, "INTSTAT"},
372 {0x208, "INTCLR"},
373 {0x20C, "INTSET"},
374 {0x240, "DMATRIGEN"},
375 {0x280, "DMACFG"},
376 {0x288, "DMATOTCOUNT"},
377 {0x28C, "DMATARGADDR"},
378 {0x290, "DMASTAT"},
379 {0xFFFFFFFF, NULL}
380 };
381
382 am_util_regdump_t g_sRegdumpPWRCTRL[] =
383 {
384 {0x000, "SUPPLYSRC"},
385 {0x004, "SUPPLYSTATUS"},
386 {0x008, "DEVPWREN"},
387 {0x00C, "MEMPWRDININSLEEP"},
388 {0x010, "MEMPWREN"},
389 {0x014, "MEMPWRSTATUS"},
390 {0x018, "DEVPWRSTATUS"},
391 {0x01C, "SRAMCTRL"},
392 {0x020, "ADCSTATUS"},
393 {0x024, "MISC"},
394 {0x028, "DEVPWREVENTEN"},
395 {0x02C, "MEMPWREVENTEN"},
396 {0xFFFFFFFF, NULL}
397 };
398
399 am_util_regdump_t g_sRegdumpMCUCTRL[] =
400 {
401 {0x000, "CHIPPN"},
402 {0x004, "CHIPID0"},
403 {0x008, "CHIPID1"},
404 {0x00C, "CHIPREV"},
405 {0x010, "VENDORID"},
406 {0x014, "SKU"},
407 {0x018, "FEATUREENABLE"},
408 {0x020, "DEBUGGER"},
409 {0x100, "BODCTRL"},
410 {0x104, "ADCPWRDLY"},
411 {0x10C, "ADCCAL"},
412 {0x110, "ADCBATTLOAD"},
413 {0x118, "ADCTRIM"},
414 {0x11C, "REFCOMP"},
415 {0x120, "XTALCTRL"},
416 {0x124, "XTALGENCTRL"},
417 {0x198, "MISCCTRL"},
418 {0x1A0, "BOOTLOADER"},
419 {0x1A4, "SHADOWVALID"},
420 {0x1B0, "SCRATCH0"},
421 {0x1B4, "SCRATCH1"},
422 {0x1C0, "ICODEFAULTADDR"},
423 {0x1C4, "DCODEFAULTADDR"},
424 {0x1C8, "SYSFAULTADDR"},
425 {0x1CC, "FAULTSTATUS"},
426 {0x1D0, "FAULTCAPTUREEN"},
427 {0x200, "DBGR1"},
428 {0x204, "DBGR2"},
429 {0x220, "PMUENABLE"},
430 {0x250, "TPIUCTRL"},
431 {0x264, "OTAPOINTER"},
432 {0x280, "APBDMACTRL"},
433 {0x284, "SRAMMODE"},
434 {0x348, "KEXTCLKSEL"},
435 {0x35C, "SIMOBUCK4"},
436 {0x368, "BLEBUCK2"},
437 {0x3A0, "FLASHWPROT0"},
438 {0x3A4, "FLASHWPROT1"},
439 {0x3B0, "FLASHRPROT0"},
440 {0x3B4, "FLASHRPROT0"},
441 {0x3C0, "DMASRAMWRITEPROT0"},
442 {0x3C4, "DMASRAMWRITEPROT1"},
443 {0x3D0, "DMASRAMREADPROT0"},
444 {0x3D4, "DMASRAMREADPROT1"},
445 {0xFFFFFFFF, NULL} // 44 registers visible
446 };
447
448 am_util_regdump_t g_sRegdumpBLE[] =
449 {
450 #if INCLUDE_REGS_WITH_SIDE_EFFECT
451 {0x000, "FIFO"},
452 #endif
453 {0x100, "FIFOPTR"},
454 {0x104, "FIFOTHR"},
455 #if INCLUDE_REGS_WITH_SIDE_EFFECT
456 {0x108, "FIFOPOP"},
457 #endif
458 {0x10C, "FIFOPUSH"},
459 {0x110, "FIFOCTRL"},
460 {0x114, "FIFOLOC"},
461 {0x200, "CLKCFG"},
462 {0x20C, "CMD"},
463 {0x210, "CMDRPT"},
464 {0x214, "OFFSETHI"},
465 {0x218, "CMDSTAT"},
466 {0x220, "INTEN"},
467 {0x224, "INTSTAT"},
468 {0x228, "INTCLR"},
469 {0x22C, "INTSET"},
470 {0x230, "DMATRIGEN"},
471 {0x234, "DMATRIGSTAT"},
472 {0x238, "DMACFG"},
473 {0x23C, "DMATOTCOUNT"},
474 {0x240, "DMATARGADDR"},
475 {0x244, "DMASTAT"},
476 {0x248, "CQCFG"},
477 {0x24C, "CQADDR"},
478 {0x250, "CQSTAT"},
479 {0x254, "CQFLAGS"},
480 {0x258, "CQSETCLEAR"},
481 {0x25C, "CQPAUSEEN"},
482 {0x260, "CQCURIDX"},
483 {0x264, "CQENDIDX"},
484 {0x268, "STATUS"},
485 {0x300, "MSPICFG"},
486 {0x304, "BLECFG"},
487 {0x308, "PWRCMD"},
488 {0x30C, "BSTATUS"},
489 {0x410, "BLEDBG"},
490 {0xFFFFFFFF, NULL}
491 };
492
493 am_util_regdump_t g_sRegdumpMSPI[] =
494 {
495 {0x000, "CTRL"},
496 {0x004, "CFG"},
497 {0x008, "ADDR"},
498 {0x00C, "INSTR"},
499 #if INCLUDE_REGS_WITH_SIDE_EFFECT
500 {0x010, "TXFIFO"},
501 {0x014, "RXFIFO"},
502 #endif
503 {0x018, "TXENTRIES"},
504 {0x01C, "RXENTRIES"},
505 {0x020, "THRESHOLD"},
506 {0x100, "MSPICFG"},
507 {0x104, "PADCFG"},
508 {0x108, "PADOUTEN"},
509 {0x10C, "FLASH"},
510 {0x120, "SCRAMBLING"},
511 {0x200, "INTEN"},
512 {0x204, "INTSTAT"},
513 {0x208, "INTCLR"},
514 {0x20C, "INTSET"},
515 {0x250, "DMACFG"},
516 {0x254, "DMASTAT"},
517 {0x258, "DMATARGADDR"},
518 {0x25C, "DMADEVADDR"},
519 {0x260, "DMATOTCOUNT"},
520 {0x264, "DMABCOUNT"},
521 {0x278, "DMATHRESH"},
522 {0x2A0, "CQCFG"},
523 {0x2A8, "CQADDR"},
524 {0x2AC, "CQSTAT"},
525 {0x2B0, "CQFLAGS"},
526 {0x2B4, "CQSETCLEAR"},
527 {0x2B8, "CQPAUSE"},
528 {0x2C0, "CQCURIDX"},
529 {0x2C4, "CQENDIDX"},
530 {0xFFFFFFFF, NULL} // 33 registers are public
531 };
532 #endif // AM_PART_APOLLO3
533
534
535 #if AM_PART_APOLLO2 || AM_PART_APOLLO
536 am_util_regdump_t g_sRegdumpIOM[] =
537 {
538 #if INCLUDE_REGS_WITH_SIDE_EFFECT
539 {0x000, "FIFO"},
540 #endif // INCLUDE_REGS_WITH_SIDE_EFFECT
541 {0x100, "FIFOPTR"},
542 {0x104, "TLNGTH"},
543 {0x108, "FIFOTHR"},
544 {0x10C, "CLKCFG"},
545 {0x110, "CMD"},
546 {0x114, "CMDRPT"},
547 {0x118, "STATUS"},
548 {0x11C, "CFG"},
549 {0x200, "INTEN"},
550 {0x204, "INTSTAT"},
551 {0x208, "INTCLR"},
552 {0x20C, "INTSET"},
553 {0xFFFFFFFF, NULL}
554 };
555 #endif // AM_PART_APOLLO2 || AM_PART_APOLLO
556
557
558 #if AM_PART_APOLLO2
559 am_util_regdump_t g_sRegdumpPDM[] =
560 {
561 {0x000, "PCFG"},
562 {0x004, "VCFG"},
563 {0x008, "FR"},
564 #if INCLUDE_REGS_WITH_SIDE_EFFECT
565 {0x00C, "FRD"},
566 #endif // INCLUDE_REGS_WITH_SIDE_EFFECT
567 {0x010, "FLUSH"},
568 {0x014, "FTHR"},
569 {0x200, "INTEN"},
570 {0x204, "INTSTAT"},
571 {0x208, "INTCLR"},
572 {0x20C, "INTSET"},
573 {0xFFFFFFFF, NULL}
574 };
575
576 am_util_regdump_t g_sRegdumpPWRCTRL[] =
577 {
578 {0x000, "SUPPLYSRC"},
579 {0x004, "POWERSTATUS"},
580 {0x008, "DEVICEEN"},
581 {0x00C, "SRAMPWDINSLEEP"},
582 {0x010, "MEMEN"},
583 {0x014, "PWRONSTATUS"},
584 {0x018, "SRAMCTRL"},
585 {0x01C, "ADCSTATUS"},
586 {0x020, "MISCOPT"},
587 {0xFFFFFFFF, NULL}
588 };
589
590 am_util_regdump_t g_sRegdumpMCUCTRL[] =
591 {
592 {0x000, "CHIPINFO"},
593 {0x004, "CHIPID0"},
594 {0x008, "CHIPID1"},
595 {0x00C, "CHIPREV"},
596 {0x010, "VENDORID"},
597 {0x014, "DEBUGGER"},
598 {0x060, "BUCK"},
599 {0x068, "BUCK3"},
600 {0x080, "LDOREG1"},
601 {0x088, "LDOREG3"},
602 {0x100, "BODCTRL"},
603 {0x104, "ADCPWRDLY"},
604 {0x10C, "ADCCAL"},
605 {0x110, "ADCBATTLOAD"},
606 {0x114, "BUCKTRIM"},
607 {0x1A0, "BOOTLOADER"},
608 {0x1A4, "SHADOWVALID"},
609 {0x1C0, "ICODEFAULTADDR"},
610 {0x1C4, "DCODEFAULTADDR"},
611 {0x1C8, "SYSFAULTADDR"},
612 {0x1CC, "FAULTSTATUS"},
613 {0x1D0, "FAULTCAPTUREEN"},
614 {0x200, "DBGR1"},
615 {0x204, "DBGR2"},
616 {0x220, "PMUENABLE"},
617 {0x250, "TPIUCTRL"},
618 {0xFFFFFFFF, NULL} // 26 registers are public
619 };
620 #endif // AM_PART_APOLLO2
621
622
623 #if AM_PART_APOLLO
624 am_util_regdump_t g_sRegdumpMCUCTRL[] =
625 {
626 {0x000, "CHIPPN"},
627 {0x004, "CHIPID0"},
628 {0x008, "CHIPID1"},
629 {0x00C, "CHIPREV"},
630 {0x010, "SUPPLYSRC"},
631 {0x014, "SUPPLYSTATUS"},
632 {0x0FC, "BANDGAPEN"},
633 {0x140, "SRAMPWDINSLEEP"},
634 {0x144, "SRAMPWRDIS"},
635 {0x148, "FLASHPWRDIS"},
636 {0x1C0, "ICODEFAULTADDR"},
637 {0x1C4, "DCODEFAULTADDR"},
638 {0x1C8, "SYSFAULTADDR"},
639 {0x1CC, "FAULTSTATUS"},
640 {0x1D0, "FAULTCAPTUREEN"},
641 {0x250, "TPIUCTRL"},
642 {0xFFFFFFFF, NULL} // 16 registers are public
643 };
644 #endif // AM_PART_APOLLO
645
646 am_util_regdump_t g_sRegdumpRSTGEN[] =
647 {
648 {0x000, "CFG"},
649 {0x004, "SWPOI"},
650 {0x008, "SWPOR"},
651 {0x00C, "RSTSTAT"},
652 {0x010, "CLRSTAT"},
653 {0x014, "TPIURST"},
654 {0x200, "INTEN"},
655 {0x204, "INTSTAT"},
656 {0x208, "INTCLR"},
657 {0x20C, "INTSET"},
658 {0x0FFFF000, "STAT"},
659 {0xFFFFFFFF, NULL}
660 };
661
662 am_util_regdump_t g_sRegdumpRTC[] =
663 {
664 {0x040, "CTRLOW"},
665 {0x044, "CTRUP"},
666 {0x048, "ALMLOW"},
667 {0x04C, "ALMUP"},
668 {0x050, "RTCCTL"},
669 //
670 // The interrupt regs are actually duplicates of CLKGEN
671 //
672 {0x100, "INTEN"},
673 {0x104, "INTSTAT"},
674 {0x108, "INTCLR"},
675 {0x10C, "INTSET"},
676 {0xFFFFFFFF, NULL}
677 };
678
679 am_util_regdump_t g_sRegdumpUART[] =
680 {
681 #if INCLUDE_REGS_WITH_SIDE_EFFECT
682 {0x000, "DR (data)"},
683 #endif // INCLUDE_REGS_WITH_SIDE_EFFECT
684 {0x004, "RSR (status)"},
685 {0x018, "FR (flag)"},
686 {0x020, "ILPR (IrDA Counter)"},
687 {0x024, "IBRD (Baud Div)"},
688 {0x028, "FBRD (Frac Baud Div)"},
689 {0x02C, "LCRH (Line Ctrl)"},
690 {0x030, "CR (Ctrl)"},
691 {0x034, "IFLS"},
692 {0x038, "IER"},
693 {0x03C, "IES"},
694 {0x040, "MIS"},
695 {0x044, "IEC"},
696 {0xFFFFFFFF, NULL}
697 };
698
699 am_util_regdump_t g_sRegdumpVCOMP[] =
700 {
701 {0x000, "CFG"},
702 {0x004, "STAT"},
703 {0x008, "PWDKEY"},
704 {0x200, "INTEN"},
705 {0x204, "INTSTAT"},
706 {0x208, "INTCLR"},
707 {0x20C, "INTSET"},
708 {0xFFFFFFFF, NULL}
709 };
710
711 am_util_regdump_t g_sRegdumpWDT[] =
712 {
713 {0x000, "CFG"},
714 {0x004, "RSTRT"},
715 {0x008, "LOCK"},
716 {0x00C, "COUNT"},
717 {0x200, "INTEN"},
718 {0x204, "INTSTAT"},
719 {0x208, "INTCLR"},
720 {0x20C, "INTSET"},
721 {0xFFFFFFFF, NULL}
722 };
723
724 am_util_regdump_t g_sRegdumpITM[] =
725 {
726 {0xE0000000, "STIM0"},
727 {0xE0000004, "STIM1"},
728 {0xE0000008, "STIM2"},
729 {0xE000000C, "STIM3"},
730 {0xE0000010, "STIM4"},
731 {0xE0000014, "STIM5"},
732 {0xE0000018, "STIM6"},
733 {0xE000001C, "STIM7"},
734 {0xE0000020, "STIM8"},
735 {0xE0000024, "STIM9"},
736 {0xE0000028, "STIM10"},
737 {0xE000002C, "STIM11"},
738 {0xE0000030, "STIM12"},
739 {0xE0000034, "STIM13"},
740 {0xE0000038, "STIM14"},
741 {0xE000003C, "STIM15"},
742 {0xE0000040, "STIM16"},
743 {0xE0000044, "STIM17"},
744 {0xE0000048, "STIM18"},
745 {0xE000004C, "STIM19"},
746 {0xE0000050, "STIM20"},
747 {0xE0000054, "STIM21"},
748 {0xE0000058, "STIM22"},
749 {0xE000005C, "STIM23"},
750 {0xE0000060, "STIM24"},
751 {0xE0000064, "STIM25"},
752 {0xE0000068, "STIM26"},
753 {0xE000006C, "STIM27"},
754 {0xE0000070, "STIM28"},
755 {0xE0000074, "STIM29"},
756 {0xE0000078, "STIM30"},
757 {0xE000007C, "STIM31"},
758 {0xE0000E00, "TER"},
759 {0xE0000E40, "TPR"},
760 {0xE0000E80, "TCR"},
761 {0xE0000FB4, "LOCKSREG"},
762 {0xE0000FD0, "PID4"},
763 {0xE0000FD4, "PID5"},
764 {0xE0000FD8, "PID6"},
765 {0xE0000FDC, "PID7"},
766 {0xE0000FE0, "PID0"},
767 {0xE0000FE4, "PID1"},
768 {0xE0000FE8, "PID2"},
769 {0xE0000FEC, "PID3"},
770 {0xE0000FF0, "CID0"},
771 {0xE0000FF4, "CID1"},
772 {0xE0000FF8, "CID2"},
773 {0xE0000FFC, "CID3"},
774 {0xE0000FB0, "LOCKAREG"},
775 {0xFFFFFFFF, NULL}
776 };
777
778 am_util_regdump_t g_sRegdumpNVIC[] =
779 {
780 {0xE000E100, "ISER0"},
781 {0xE000E180, "ICER0"},
782 {0xE000E200, "ISPR0"},
783 {0xE000E280, "ICPR0"},
784 {0xE000E300, "IABR0"},
785 {0xE000E400, "IPR0"},
786 {0xE000E404, "IPR1"},
787 {0xE000E408, "IPR2"},
788 {0xE000E40C, "IPR3"},
789 {0xE000E410, "IPR4"},
790 {0xE000E414, "IPR5"},
791 {0xE000E418, "IPR6"},
792 {0xE000E41C, "IPR7"},
793 {0xFFFFFFFF, NULL}
794 };
795
796 am_util_regdump_t g_sRegdumpSYSCTRL[] =
797 {
798 {0xE000E004, "ICTR"},
799 {0xE000E008, "ACTLR"},
800 {0xE000ED04, "ICSR"},
801 {0xE000ED08, "VTOR"},
802 {0xE000ED0C, "AIRCR"},
803 {0xE000ED10, "SCR"},
804 {0xE000ED14, "CCR"},
805 {0xE000ED18, "SHPR1"},
806 {0xE000ED1C, "SHPR2"},
807 {0xE000ED20, "SHPR3"},
808 {0xE000ED24, "SHCSR"},
809 {0xE000ED28, "CFSR"},
810 {0xE000ED2C, "HFSR"},
811 {0xE000ED34, "MMFAR"},
812 {0xE000ED38, "BFAR"},
813 {0xE000ED88, "CPACR"},
814 {0xE000EDFC, "DEMCR"},
815 {0xE000EF00, "STIR"},
816 {0xE000EF34, "FPCCR"},
817 {0xE000EF38, "FPCAR"},
818 {0xE000EF3C, "FPDSCR"},
819 {0xFFFFFFFF, NULL}
820 };
821
822 am_util_regdump_t g_sRegdumpSYSTICK[] =
823 {
824 {0xE000E010, "SYSTCSR"},
825 {0xE000E014, "SYSTRVR"},
826 {0xE000E018, "SYSTCVR"},
827 {0xE000E01C, "SYSTCALIB"},
828 {0xFFFFFFFF, NULL}
829 };
830
831 am_util_regdump_t g_sRegdumpTPIU[] =
832 {
833 {0xE0040000, "SSPSR"},
834 {0xE0040004, "CSPSR"},
835 {0xE0040010, "ACPR"},
836 {0xE00400F0, "SPPR"},
837 {0xE0040304, "FFCR"},
838 {0xE0040F00, "ITCTRL"},
839 {0xE0040FC8, "DEVID"},
840 {0xE0040FCC, "DEVTYPE"},
841 {0xFFFFFFFF, NULL}
842 };
843
844
845 //*****************************************************************************
846 //
847 // Support functions.
848 //
849 //*****************************************************************************
850 //*****************************************************************************
851 //
852 // regdump_newline_print() - print a newline character
853 //
854 //*****************************************************************************
855 static void
regdump_newline_print(uint32_t ui32Num)856 regdump_newline_print(uint32_t ui32Num)
857 {
858 while ( ui32Num-- )
859 {
860 am_util_stdio_printf("\n");
861 }
862 }
863
864 //*****************************************************************************
865 //
866 // regdump_strlen() - calculate length of string
867 //
868 //*****************************************************************************
869 static uint32_t
regdump_strlen(char * pcStr)870 regdump_strlen(char *pcStr)
871 {
872 char *pcS;
873
874 //
875 // Loop through the string.
876 //
877 for ( pcS = pcStr; *pcS; ++pcS );
878
879 //
880 // Return the length.
881 //
882 return (pcS - pcStr);
883 }
884
885 //*****************************************************************************
886 //
887 // block_print() - print a block of addresses in hex
888 //
889 //*****************************************************************************
890 static void
block_print(am_util_regdump_t * psDump,uint32_t ui32BaseAddr)891 block_print(am_util_regdump_t *psDump, uint32_t ui32BaseAddr)
892 {
893 uint32_t ui32RegAddr;
894 uint32_t ux, ui32Len, ui32MaxLen;
895
896 //
897 // First, get the maximum register name length.
898 //
899 ui32MaxLen = ux = 0;
900 while ( psDump[ux].ui32Offset != 0xFFFFFFFF )
901 {
902 ui32Len = regdump_strlen(psDump[ux].pi8RegName);
903 if ( ui32Len > ui32MaxLen )
904 {
905 ui32MaxLen = ui32Len;
906 }
907 ux++;
908 }
909
910 //
911 // Create the format string
912 //
913 am_util_stdio_sprintf((char*)g_ui8Fmt, " %%-%ds (0x%%08X) = 0x%%08X\n", ui32MaxLen + 1);
914
915 //
916 // Now, get the value of each register and print it.
917 //
918 ux = 0;
919 while ( psDump[ux].ui32Offset != 0xFFFFFFFF )
920 {
921 //
922 // Format string is of the form: " %8s (0x%08X) = 0x%08X\n"
923 //
924 ui32RegAddr = ui32BaseAddr + psDump[ux].ui32Offset;
925 am_util_stdio_printf((char*)g_ui8Fmt, psDump[ux].pi8RegName, ui32RegAddr, AM_REGVAL(ui32RegAddr));
926 ux++;
927 }
928 }
929
930 uint32_t g_ui32PwrStatAdc = 0;
931 uint32_t g_ui32PwrStatBle = 0;
932 uint32_t g_ui32PwrStatIom02 = 0;
933 uint32_t g_ui32PwrStatIom35 = 0;
934 uint32_t g_ui32PwrStatIos = 0;
935 uint32_t g_ui32PwrStatMspi = 0;
936 uint32_t g_ui32PwrStatPdm = 0;
937 uint32_t g_ui32PwrStatUart0 = 0;
938 uint32_t g_ui32PwrStatUart1 = 0;
939
940 //*****************************************************************************
941 //
942 // regdump_pwr_enable() - Power enable
943 //
944 //*****************************************************************************
945 void
regdump_pwr_enable(uint32_t ui32Block)946 regdump_pwr_enable(uint32_t ui32Block)
947 {
948 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
949 switch ( ui32Block )
950 {
951 case AM_UTIL_REGDUMP_ADC:
952 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_ADC, &g_ui32PwrStatAdc);
953 if ( g_ui32PwrStatAdc == 0 )
954 {
955 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_ADC);
956 }
957 break;
958 case AM_UTIL_REGDUMP_BLE:
959 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_BLEL, &g_ui32PwrStatBle);
960 if ( g_ui32PwrStatBle == 0 )
961 {
962 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_BLEL);
963 }
964 break;
965 case AM_UTIL_REGDUMP_IOM:
966 //
967 // Apollo3: IOM0 - IOM2 are on the same power domain
968 // IOM3 - IOM5 are on the same power domain
969 //
970 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_IOM0, &g_ui32PwrStatIom02);
971 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_IOM3, &g_ui32PwrStatIom35);
972 if ( g_ui32PwrStatIom02 == 0 )
973 {
974 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_IOM0);
975 }
976 if ( g_ui32PwrStatIom35 == 0 )
977 {
978 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_IOM3);
979 }
980 break;
981 case AM_UTIL_REGDUMP_IOS:
982 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_IOS, &g_ui32PwrStatIos);
983 if ( g_ui32PwrStatIos == 0 )
984 {
985 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_IOS);
986 }
987 break;
988 case AM_UTIL_REGDUMP_MSPI:
989 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_MSPI, &g_ui32PwrStatMspi);
990 if ( g_ui32PwrStatMspi == 0 )
991 {
992 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_MSPI);
993 }
994 break;
995 case AM_UTIL_REGDUMP_PDM:
996 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_PDM, &g_ui32PwrStatPdm);
997 if ( g_ui32PwrStatPdm == 0 )
998 {
999 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_PDM);
1000 }
1001 break;
1002 case AM_UTIL_REGDUMP_UART:
1003 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_UART0, &g_ui32PwrStatUart0);
1004 am_hal_pwrctrl_periph_enabled(AM_HAL_PWRCTRL_PERIPH_UART1, &g_ui32PwrStatUart1);
1005 if ( g_ui32PwrStatUart0 == 0 )
1006 {
1007 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_UART0);
1008 }
1009 if ( g_ui32PwrStatUart1 == 0 )
1010 {
1011 am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_UART1);
1012 }
1013 break;
1014
1015 default:
1016 break;
1017 }
1018 #endif // AM_PART_APOLLO3
1019 } // regdump_pwr_enable()
1020
1021 //*****************************************************************************
1022 //
1023 // regdump_pwr_disable() - Power disable
1024 //
1025 //*****************************************************************************
1026 void
regdump_pwr_disable(uint32_t ui32Block)1027 regdump_pwr_disable(uint32_t ui32Block)
1028 {
1029 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
1030 switch ( ui32Block )
1031 {
1032 case AM_UTIL_REGDUMP_ADC:
1033 if ( g_ui32PwrStatAdc == 0 )
1034 {
1035 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_ADC);
1036 }
1037 g_ui32PwrStatAdc = 0;
1038 break;
1039 case AM_UTIL_REGDUMP_BLE:
1040 if ( g_ui32PwrStatBle == 0 )
1041 {
1042 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_BLEL);
1043 }
1044 g_ui32PwrStatBle = 0;
1045 break;
1046 case AM_UTIL_REGDUMP_IOM:
1047 if ( g_ui32PwrStatIom02 == 0 )
1048 {
1049 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_IOM0);
1050 }
1051
1052 if ( g_ui32PwrStatIom35 == 0 )
1053 {
1054 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_IOM3);
1055 }
1056 g_ui32PwrStatIom02 = g_ui32PwrStatIom35 = 0;
1057 break;
1058 case AM_UTIL_REGDUMP_IOS:
1059 if ( g_ui32PwrStatIos == 0 )
1060 {
1061 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_IOS);
1062 }
1063 g_ui32PwrStatIos = 0;
1064 break;
1065 case AM_UTIL_REGDUMP_MSPI:
1066 if ( g_ui32PwrStatMspi == 0 )
1067 {
1068 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_MSPI);
1069 }
1070 g_ui32PwrStatMspi = 0;
1071 break;
1072 case AM_UTIL_REGDUMP_PDM:
1073 if ( g_ui32PwrStatPdm == 0 )
1074 {
1075 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_PDM);
1076 }
1077 g_ui32PwrStatPdm = 0;
1078 break;
1079 case AM_UTIL_REGDUMP_UART:
1080 if ( g_ui32PwrStatUart0 == 0 )
1081 {
1082 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_UART0);
1083 }
1084 if ( g_ui32PwrStatUart1 == 0 )
1085 {
1086 am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_UART1);
1087 }
1088 g_ui32PwrStatUart0 = g_ui32PwrStatUart1 = 0;
1089 break;
1090 default:
1091 break;
1092 }
1093 #endif // AM_PART_APOLLO3
1094 } // regdump_pwr_disable()
1095
1096
1097 //*****************************************************************************
1098 //
1099 // printDump() - Print the registers for a given block.
1100 //
1101 // ui32NumModules = Number of modules in this block
1102 // e.g. AM_REG_xxx_NUM_MODULES.
1103 // ui32BlockBaseAddr = Base address of this block.
1104 // ui32ModuleOffset = Offset, in bytes, between modules in the block
1105 // e.g. AM_REG_IOMSTRn(1) - AM_REG_IOMSTRn(0).
1106 // ui32ModuleMask = Mask of the desired block modules to be printed.
1107 // Each lower bit indicates a module.
1108 // pui8BlockName = Name of the block (e.g "IOM").
1109 // psDump = ptr to regdump structure for this block.
1110 //
1111 //*****************************************************************************
1112 static void
dump_reg(uint32_t ui32NumModules,uint32_t ui32BlockBaseAddr,uint32_t ui32ModuleOffset,uint32_t ui32ModuleMask,char * pui8BlockName,am_util_regdump_t * psDump)1113 dump_reg(uint32_t ui32NumModules,
1114 uint32_t ui32BlockBaseAddr,
1115 uint32_t ui32ModuleOffset,
1116 uint32_t ui32ModuleMask,
1117 char *pui8BlockName,
1118 am_util_regdump_t *psDump)
1119 {
1120 uint32_t ui32Module;
1121
1122 am_util_stdio_printf("%s registers:\n", pui8BlockName);
1123
1124 ui32Module = 0;
1125
1126 while ( ui32Module < ui32NumModules )
1127 {
1128 if ( (ui32NumModules > 1) &&
1129 !(ui32ModuleMask & (1 << ui32Module)) )
1130 {
1131 ui32Module++;
1132 continue;
1133 }
1134 else
1135 {
1136 if ( ui32NumModules > 1 )
1137 {
1138 am_util_stdio_printf(" %s Module %d\n", pui8BlockName, ui32Module);
1139 }
1140 }
1141
1142 block_print(psDump, ui32BlockBaseAddr + (ui32ModuleOffset * ui32Module));
1143
1144 ui32Module++;
1145 regdump_newline_print(1);
1146 }
1147
1148 regdump_newline_print(1);
1149 }
1150
1151 //*****************************************************************************
1152 //
1153 //! @brief Register dumping for debug purposes.
1154 //!
1155 //! This function dumps register values to the print port for debug purposes.
1156 //!
1157 //! @param ui32PeriphMask = an OR of the mask values to be printed. e.g.
1158 //! AM_UTIL_REGDUMP_IOM | AM_UTIL_REGDUMP_GPIO
1159 //!
1160 //! @param ui32ModuleMask = A mask representing the modules (for a multi-module
1161 //! block such as IOM) to be dumped. Bit0 represents module 0, etc.
1162 //! This parameter is ignored for single-module blocks such as GPIO.
1163 //! Pre-defined macros can be used to generate this mask, e.g.
1164 //! REGDUMP_MOD0 | REGDUMP_MOD1 | REGDUMP_MOD2
1165 //! or equivalently
1166 //! REGDUMP_MOD_MAS(0,2)
1167 //!
1168 //*****************************************************************************
1169 void
am_util_regdump_print(uint32_t ui32PeriphMask,uint32_t ui32ModuleMask)1170 am_util_regdump_print(uint32_t ui32PeriphMask, uint32_t ui32ModuleMask)
1171 {
1172 uint32_t ux, ui32RegAddr;
1173
1174 if ( ui32PeriphMask & AM_UTIL_REGDUMP_INFO0 )
1175 {
1176 #define REGDUMP_INFO0_WDS 20
1177 am_util_stdio_printf("INFO0 space (first %d words):\n", REGDUMP_INFO0_WDS);
1178 for ( ux = 0; ux < REGDUMP_INFO0_WDS * 4; ux += 4 )
1179 {
1180 ui32RegAddr = AM_HAL_FLASH_INFO_ADDR + ux;
1181 am_util_stdio_printf("INFO0 0x%08X = 0x%08X\n",
1182 ui32RegAddr, AM_REGVAL(ui32RegAddr));
1183 }
1184 }
1185
1186 if ( ui32PeriphMask & AM_UTIL_REGDUMP_ADC )
1187 {
1188 regdump_pwr_enable(AM_UTIL_REGDUMP_ADC);
1189 dump_reg(AM_REG_ADC_NUM_MODULES, AM_REG_ADCn(0),
1190 AM_REG_ADCn(1) - AM_REG_ADCn(0),
1191 ui32ModuleMask, "ADC", &g_sRegdumpADC[0]);
1192 regdump_pwr_disable(AM_UTIL_REGDUMP_ADC);
1193 }
1194
1195 if ( ui32PeriphMask & AM_UTIL_REGDUMP_CLKGEN )
1196 {
1197 dump_reg(AM_REG_CLKGEN_NUM_MODULES, AM_REG_CLKGENn(0),
1198 AM_REG_CLKGENn(1) - AM_REG_CLKGENn(0),
1199 ui32ModuleMask, "CLKGEN", &g_sRegdumpCLKGEN[0]);
1200 }
1201
1202 if ( ui32PeriphMask & AM_UTIL_REGDUMP_CTIMER )
1203 {
1204 dump_reg(AM_REG_CTIMER_NUM_MODULES, AM_REG_CTIMERn(0),
1205 AM_REG_CTIMERn(1) - AM_REG_CTIMERn(0),
1206 ui32ModuleMask, "CTIMER", &g_sRegdumpCTIMER[0]);
1207 }
1208
1209 if ( ui32PeriphMask & AM_UTIL_REGDUMP_GPIO )
1210 {
1211 dump_reg(AM_REG_GPIO_NUM_MODULES, AM_REG_GPIOn(0),
1212 AM_REG_GPIOn(1) - AM_REG_GPIOn(0),
1213 ui32ModuleMask, "GPIO", &g_sRegdumpGPIO[0]);
1214 }
1215
1216 if ( ui32PeriphMask & AM_UTIL_REGDUMP_IOM )
1217 {
1218 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
1219 regdump_pwr_enable(AM_UTIL_REGDUMP_IOM);
1220 dump_reg(AM_REG_IOM_NUM_MODULES, AM_REG_IOMn(0),
1221 AM_REG_IOMn(1) - AM_REG_IOMn(0),
1222 ui32ModuleMask, "IOM", &g_sRegdumpIOM[0]);
1223 regdump_pwr_disable(AM_UTIL_REGDUMP_IOM);
1224 #else
1225 dump_reg(AM_REG_IOMSTR_NUM_MODULES, AM_REG_IOMSTRn(0),
1226 AM_REG_IOMSTRn(1) - AM_REG_IOMSTRn(0),
1227 ui32ModuleMask, "IOM", &g_sRegdumpIOM[0]);
1228 #endif
1229 }
1230
1231 if ( ui32PeriphMask & AM_UTIL_REGDUMP_IOS )
1232 {
1233 regdump_pwr_enable(AM_UTIL_REGDUMP_IOS);
1234 dump_reg(AM_REG_IOSLAVE_NUM_MODULES, AM_REG_IOSLAVEn(0),
1235 AM_REG_IOSLAVEn(1) - AM_REG_IOSLAVEn(0),
1236 ui32ModuleMask, "IOS", &g_sRegdumpIOS[0]);
1237 regdump_pwr_disable(AM_UTIL_REGDUMP_IOS);
1238 }
1239
1240 if ( ui32PeriphMask & AM_UTIL_REGDUMP_RSTGEN )
1241 {
1242 dump_reg(AM_REG_RSTGEN_NUM_MODULES, AM_REG_RSTGENn(0),
1243 AM_REG_RSTGENn(1) - AM_REG_RSTGENn(0),
1244 ui32ModuleMask, "RSTGEN", &g_sRegdumpRSTGEN[0]);
1245 }
1246
1247 if ( ui32PeriphMask & AM_UTIL_REGDUMP_RTC )
1248 {
1249 dump_reg(AM_REG_RTC_NUM_MODULES, AM_REG_RTCn(0),
1250 AM_REG_RTCn(1) - AM_REG_RTCn(0),
1251 ui32ModuleMask, "RTC", &g_sRegdumpRTC[0]);
1252 }
1253
1254 if ( ui32PeriphMask & AM_UTIL_REGDUMP_UART )
1255 {
1256 regdump_pwr_enable(AM_UTIL_REGDUMP_UART);
1257 dump_reg(AM_REG_UART_NUM_MODULES, AM_REG_UARTn(0),
1258 AM_REG_UARTn(1) - AM_REG_UARTn(0),
1259 ui32ModuleMask, "UART", &g_sRegdumpUART[0]);
1260 regdump_pwr_disable(AM_UTIL_REGDUMP_UART);
1261 }
1262
1263 if ( ui32PeriphMask & AM_UTIL_REGDUMP_VCOMP )
1264 {
1265 dump_reg(AM_REG_VCOMP_NUM_MODULES, AM_REG_VCOMPn(0),
1266 AM_REG_VCOMPn(1) - AM_REG_VCOMPn(0),
1267 ui32ModuleMask, "VCOMP", &g_sRegdumpVCOMP[0]);
1268 }
1269
1270 if ( ui32PeriphMask & AM_UTIL_REGDUMP_WDT )
1271 {
1272 dump_reg(AM_REG_WDT_NUM_MODULES, AM_REG_WDTn(0),
1273 AM_REG_WDTn(1) - AM_REG_WDTn(0),
1274 ui32ModuleMask, "WDT", &g_sRegdumpWDT[0]);
1275 }
1276
1277 if ( ui32PeriphMask & AM_UTIL_REGDUMP_ITM )
1278 {
1279 dump_reg(1, 0, 0, ui32ModuleMask, "ITM", &g_sRegdumpITM[0]);
1280 }
1281
1282 if ( ui32PeriphMask & AM_UTIL_REGDUMP_NVIC )
1283 {
1284 dump_reg(1, 0, 0, ui32ModuleMask, "NVIC", &g_sRegdumpNVIC[0]);
1285 }
1286
1287 if ( ui32PeriphMask & AM_UTIL_REGDUMP_SYSCTRL )
1288 {
1289 dump_reg(1, 0, 0, ui32ModuleMask, "SYSCTRL", &g_sRegdumpSYSCTRL[0]);
1290 }
1291
1292 if ( ui32PeriphMask & AM_UTIL_REGDUMP_SYSTICK )
1293 {
1294 dump_reg(1, 0, 0, ui32ModuleMask, "SYSTICK", &g_sRegdumpSYSTICK[0]);
1295 }
1296
1297 if ( ui32PeriphMask & AM_UTIL_REGDUMP_TPIU )
1298 {
1299 dump_reg(1, 0, 0, ui32ModuleMask, "TPIU", &g_sRegdumpTPIU[0]);
1300 }
1301
1302 if ( ui32PeriphMask & AM_UTIL_REGDUMP_MCUCTRL )
1303 {
1304 dump_reg(AM_REG_MCUCTRL_NUM_MODULES, AM_REG_MCUCTRLn(0),
1305 AM_REG_MCUCTRLn(1) - AM_REG_MCUCTRLn(0),
1306 ui32ModuleMask, "MCUCTRL", &g_sRegdumpMCUCTRL[0]);
1307 }
1308
1309 #if AM_PART_APOLLO2 || AM_PART_APOLLO3 || AM_PART_APOLLO3P
1310 am_util_stdio_printf("Apollo2/3 specific registers:\n\n");
1311
1312 if ( ui32PeriphMask & AM_UTIL_REGDUMP_CACHE )
1313 {
1314 dump_reg(AM_REG_CACHECTRL_NUM_MODULES, AM_REG_CACHECTRLn(0),
1315 AM_REG_CACHECTRLn(1) - AM_REG_CACHECTRLn(0),
1316 ui32ModuleMask, "CACHE", &g_sRegdumpCACHECTRL[0]);
1317 }
1318
1319 if ( ui32PeriphMask & AM_UTIL_REGDUMP_PDM )
1320 {
1321 regdump_pwr_enable(AM_UTIL_REGDUMP_PDM);
1322 dump_reg(AM_REG_PDM_NUM_MODULES, AM_REG_PDMn(0),
1323 AM_REG_PDMn(1) - AM_REG_PDMn(0),
1324 ui32ModuleMask, "PDM", &g_sRegdumpPDM[0]);
1325 regdump_pwr_disable(AM_UTIL_REGDUMP_PDM);
1326 }
1327
1328 if ( ui32PeriphMask & AM_UTIL_REGDUMP_PWRCTRL )
1329 {
1330 dump_reg(AM_REG_PWRCTRL_NUM_MODULES, AM_REG_PWRCTRLn(0),
1331 AM_REG_PWRCTRLn(1) - AM_REG_PWRCTRLn(0),
1332 ui32ModuleMask, "PWRCTRL", &g_sRegdumpPWRCTRL[0]);
1333 }
1334 #endif // AM_PART_APOLLO2 || AM_PART_APOLLO3
1335
1336 #if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P)
1337 am_util_stdio_printf("Apollo3 specific registers:\n\n");
1338
1339 if ( ui32PeriphMask & AM_UTIL_REGDUMP_BLE )
1340 {
1341 regdump_pwr_enable(AM_UTIL_REGDUMP_BLE);
1342 dump_reg(AM_REG_BLEIF_NUM_MODULES, AM_REG_BLEIFn(0),
1343 AM_REG_BLEIFn(1) - AM_REG_BLEIFn(0),
1344 ui32ModuleMask, "BLEIF", &g_sRegdumpBLE[0]);
1345 regdump_pwr_disable(AM_UTIL_REGDUMP_BLE);
1346 }
1347
1348 if ( ui32PeriphMask & AM_UTIL_REGDUMP_MSPI )
1349 {
1350 regdump_pwr_enable(AM_UTIL_REGDUMP_MSPI);
1351 dump_reg(AM_REG_MSPI_NUM_MODULES, AM_REG_MSPIn(0),
1352 AM_REG_MSPIn(1) - AM_REG_MSPIn(0),
1353 ui32ModuleMask, "MSPI", &g_sRegdumpMSPI[0]);
1354 regdump_pwr_disable(AM_UTIL_REGDUMP_MSPI);
1355 }
1356 #endif //AM_PART_APOLLO3
1357
1358
1359 am_util_stdio_printf("Register dump completed.\n");
1360
1361 } // am_util_regdump_print()
1362
1363 //*****************************************************************************
1364 //
1365 // End Doxygen group.
1366 //! @}
1367 //
1368 //*****************************************************************************
1369
1370
