1 /*
2  * Copyright (c) 2023, Ambiq Micro, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  * @file     apollo4b.h
32  * @brief    CMSIS HeaderFile
33  * @version  1.0
34  * @date     01. June 2023
35  * @note     Generated by SVDConv V3.3.42 on Thursday, 01.06.2023 11:17:32
36  *           from File './apollo4b.svd',
37  *           last modified on Thursday, 01.06.2023 16:17:31
38  */
39 
40 
41 
42 /** @addtogroup Ambiq Micro
43   * @{
44   */
45 
46 
47 /** @addtogroup apollo4b
48   * @{
49   */
50 
51 
52 #ifndef APOLLO4B_H
53 #define APOLLO4B_H
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 
60 /** @addtogroup Configuration_of_CMSIS
61   * @{
62   */
63 
64 
65 
66 /* =========================================================================================================================== */
67 /* ================                                Interrupt Number Definition                                ================ */
68 /* =========================================================================================================================== */
69 
70 typedef enum {
71 /* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
72   Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
73   NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
74   HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
75   MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
76                                                      and No Match                                                              */
77   BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
78                                                      related Fault                                                             */
79   UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
80   SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
81   DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
82   PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
83   SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
84 /* ==========================================  apollo4b Specific Interrupt Numbers  ========================================== */
85   BROWNOUT_IRQn             =   0,              /*!< 0  BROWNOUT_IRQ                                                           */
86   WDT_IRQn                  =   1,              /*!< 1  WDT_IRQ                                                                */
87   RTC_IRQn                  =   2,              /*!< 2  RTC_IRQ                                                                */
88   VCOMP_IRQn                =   3,              /*!< 3  VCOMP_IRQ                                                              */
89   IOSLAVE_IRQn              =   4,              /*!< 4  IOSLAVE_IRQ                                                            */
90   IOSLAVEACC_IRQn           =   5,              /*!< 5  IOSLAVEACC_IRQ                                                         */
91   IOMSTR0_IRQn              =   6,              /*!< 6  IOMSTR0_IRQ                                                            */
92   IOMSTR1_IRQn              =   7,              /*!< 7  IOMSTR1_IRQ                                                            */
93   IOMSTR2_IRQn              =   8,              /*!< 8  IOMSTR2_IRQ                                                            */
94   IOMSTR3_IRQn              =   9,              /*!< 9  IOMSTR3_IRQ                                                            */
95   IOMSTR4_IRQn              =  10,              /*!< 10 IOMSTR4_IRQ                                                            */
96   IOMSTR5_IRQn              =  11,              /*!< 11 IOMSTR5_IRQ                                                            */
97   IOMSTR6_IRQn              =  12,              /*!< 12 IOMSTR6_IRQ                                                            */
98   IOMSTR7_IRQn              =  13,              /*!< 13 IOMSTR7_IRQ                                                            */
99   TIMER_IRQn                =  14,              /*!< 14 TIMER_IRQ                                                              */
100   UART0_IRQn                =  15,              /*!< 15 UART0_IRQ                                                              */
101   UART1_IRQn                =  16,              /*!< 16 UART1_IRQ                                                              */
102   UART2_IRQn                =  17,              /*!< 17 UART2_IRQ                                                              */
103   UART3_IRQn                =  18,              /*!< 18 UART3_IRQ                                                              */
104   ADC_IRQn                  =  19,              /*!< 19 ADC_IRQ                                                                */
105   MSPI0_IRQn                =  20,              /*!< 20 MSPI0_IRQ                                                              */
106   MSPI1_IRQn                =  21,              /*!< 21 MSPI1_IRQ                                                              */
107   MSPI2_IRQn                =  22,              /*!< 22 MSPI2_IRQ                                                              */
108   CLKGEN_IRQn               =  23,              /*!< 23 CLKGEN_IRQ                                                             */
109   CRYPTOSEC_IRQn            =  24,              /*!< 24 CRYPTOSEC_IRQ                                                          */
110   SDIO_IRQn                 =  26,              /*!< 26 SDIO_IRQ                                                               */
111   USB0_IRQn                 =  27,              /*!< 27 USB0_IRQ                                                               */
112   GPU_IRQn                  =  28,              /*!< 28 GPU_IRQ                                                                */
113   DC_IRQn                   =  29,              /*!< 29 DC_IRQ                                                                 */
114   DSI_IRQn                  =  30,              /*!< 30 DSI_IRQ                                                                */
115   STIMER_CMPR0_IRQn         =  32,              /*!< 32 STIMER_CMPR0_IRQ                                                       */
116   STIMER_CMPR1_IRQn         =  33,              /*!< 33 STIMER_CMPR1_IRQ                                                       */
117   STIMER_CMPR2_IRQn         =  34,              /*!< 34 STIMER_CMPR2_IRQ                                                       */
118   STIMER_CMPR3_IRQn         =  35,              /*!< 35 STIMER_CMPR3_IRQ                                                       */
119   STIMER_CMPR4_IRQn         =  36,              /*!< 36 STIMER_CMPR4_IRQ                                                       */
120   STIMER_CMPR5_IRQn         =  37,              /*!< 37 STIMER_CMPR5_IRQ                                                       */
121   STIMER_CMPR6_IRQn         =  38,              /*!< 38 STIMER_CMPR6_IRQ                                                       */
122   STIMER_CMPR7_IRQn         =  39,              /*!< 39 STIMER_CMPR7_IRQ                                                       */
123   STIMER_OVF_IRQn           =  40,              /*!< 40 STIMER_OVF_IRQ                                                         */
124   AUDADC0_IRQn              =  42,              /*!< 42 AUDADC0_IRQ                                                            */
125   I2S0_IRQn                 =  44,              /*!< 44 I2S0_IRQ                                                               */
126   I2S1_IRQn                 =  45,              /*!< 45 I2S1_IRQ                                                               */
127   PDM0_IRQn                 =  48,              /*!< 48 PDM0_IRQ                                                               */
128   PDM1_IRQn                 =  49,              /*!< 49 PDM1_IRQ                                                               */
129   PDM2_IRQn                 =  50,              /*!< 50 PDM2_IRQ                                                               */
130   PDM3_IRQn                 =  51,              /*!< 51 PDM3_IRQ                                                               */
131   GPIO0_001F_IRQn           =  56,              /*!< 56 GPIO0_001F_IRQ                                                         */
132   GPIO0_203F_IRQn           =  57,              /*!< 57 GPIO0_203F_IRQ                                                         */
133   GPIO0_405F_IRQn           =  58,              /*!< 58 GPIO0_405F_IRQ                                                         */
134   GPIO0_607F_IRQn           =  59,              /*!< 59 GPIO0_607F_IRQ                                                         */
135   GPIO1_001F_IRQn           =  60,              /*!< 60 GPIO1_001F_IRQ                                                         */
136   GPIO1_203F_IRQn           =  61,              /*!< 61 GPIO1_203F_IRQ                                                         */
137   GPIO1_405F_IRQn           =  62,              /*!< 62 GPIO1_405F_IRQ                                                         */
138   GPIO1_607F_IRQn           =  63,              /*!< 63 GPIO1_607F_IRQ                                                         */
139   TIMER0_IRQn               =  67,              /*!< 67 TIMER0_IRQ                                                             */
140   TIMER1_IRQn               =  68,              /*!< 68 TIMER1_IRQ                                                             */
141   TIMER2_IRQn               =  69,              /*!< 69 TIMER2_IRQ                                                             */
142   TIMER3_IRQn               =  70,              /*!< 70 TIMER3_IRQ                                                             */
143   TIMER4_IRQn               =  71,              /*!< 71 TIMER4_IRQ                                                             */
144   TIMER5_IRQn               =  72,              /*!< 72 TIMER5_IRQ                                                             */
145   TIMER6_IRQn               =  73,              /*!< 73 TIMER6_IRQ                                                             */
146   TIMER7_IRQn               =  74,              /*!< 74 TIMER7_IRQ                                                             */
147   TIMER8_IRQn               =  75,              /*!< 75 TIMER8_IRQ                                                             */
148   TIMER9_IRQn               =  76,              /*!< 76 TIMER9_IRQ                                                             */
149   TIMER10_IRQn              =  77,              /*!< 77 TIMER10_IRQ                                                            */
150   TIMER11_IRQn              =  78,              /*!< 78 TIMER11_IRQ                                                            */
151   TIMER12_IRQn              =  79,              /*!< 79 TIMER12_IRQ                                                            */
152   TIMER13_IRQn              =  80,              /*!< 80 TIMER13_IRQ                                                            */
153   TIMER14_IRQn              =  81,              /*!< 81 TIMER14_IRQ                                                            */
154   TIMER15_IRQn              =  82,              /*!< 82 TIMER15_IRQ                                                            */
155   CACHE_IRQn                =  83,              /*!< 83 CACHE_IRQ                                                              */
156   MAX_IRQn                  =  84               /*!< 84 Not a valid IRQ. The maximum IRQ is this value - 1.                    */
157 } IRQn_Type;
158 
159 
160 
161 /* =========================================================================================================================== */
162 /* ================                           Processor and Core Peripheral Section                           ================ */
163 /* =========================================================================================================================== */
164 
165 /* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
166 #define __CM4_REV                 0x0100U       /*!< CM4 Core Revision                                                         */
167 #define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
168 #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
169 #define __MPU_PRESENT                  1        /*!< MPU present                                                               */
170 #define __FPU_PRESENT                  1        /*!< FPU present                                                               */
171 
172 
173 /** @} */ /* End of group Configuration_of_CMSIS */
174 
175 #if 1 // xtensa
176 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
177 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
178 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
179 #else // xtensa
180 #include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
181 #include "system_apollo4b.h"                    /*!< apollo4b System                                                           */
182 
183 #ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
184   #define __IM   __I
185 #endif
186 #ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
187   #define __OM   __O
188 #endif
189 #ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
190   #define __IOM  __IO
191 #endif
192 
193 
194 /* ========================================  Start of section using anonymous unions  ======================================== */
195 #if defined (__CC_ARM)
196   #pragma push
197   #pragma anon_unions
198 #elif defined (__ICCARM__)
199   #pragma language=extended
200 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
201   #pragma clang diagnostic push
202   #pragma clang diagnostic ignored "-Wc11-extensions"
203   #pragma clang diagnostic ignored "-Wreserved-id-macro"
204   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
205   #pragma clang diagnostic ignored "-Wnested-anon-types"
206 #elif defined (__GNUC__)
207   /* anonymous unions are enabled by default */
208 #elif defined (__TMS470__)
209   /* anonymous unions are enabled by default */
210 #elif defined (__TASKING__)
211   #pragma warning 586
212 #elif defined (__CSMC__)
213   /* anonymous unions are enabled by default */
214 #else
215   #warning Not supported compiler type
216 #endif
217 
218 
219 /* =========================================================================================================================== */
220 /* ================                            Device Specific Peripheral Section                             ================ */
221 /* =========================================================================================================================== */
222 
223 
224 /** @addtogroup Device_Peripheral_peripherals
225   * @{
226   */
227 
228 
229 
230 /* =========================================================================================================================== */
231 /* ================                                            ADC                                            ================ */
232 /* =========================================================================================================================== */
233 
234 
235 /**
236   * @brief Analog Digital Converter Control (ADC)
237   */
238 
239 typedef struct {                                /*!< (@ 0x40038000) ADC Structure                                              */
240 
241   union {
242     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The ADC Configuration Register contains the software
243                                                                     control for selecting the clock frequency
244                                                                     used for the SAR conversions, the trigger
245                                                                     polarity, the trigger select, the reference
246                                                                     voltage select, the low power mode, the
247                                                                     operating mode (single scan per trigger
248                                                                     vs. repeating mode) and ADC enable.                        */
249 
250     struct {
251       __IOM uint32_t ADCEN      : 1;            /*!< [0..0] This bit enables the ADC module. While the ADC is enabled,
252                                                      the ADCCFG and SLOT Configuration regsiter settings must
253                                                      remain stable and unchanged. All configuration register
254                                                      settings, slot configuration settings and window comparison
255                                                      settings should be written prior to setting the ADCEN bit
256                                                      to '1'.                                                                   */
257             uint32_t            : 1;
258       __IOM uint32_t RPTEN      : 1;            /*!< [2..2] This bit enables Repeating Scan Mode.                              */
259       __IOM uint32_t LPMODE     : 1;            /*!< [3..3] Select power mode to enter between active scans.                   */
260       __IOM uint32_t CKMODE     : 1;            /*!< [4..4] Clock mode register                                                */
261             uint32_t            : 7;
262       __IOM uint32_t DFIFORDEN  : 1;            /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
263                                                      FIFO pop upon reading the FIFOPR register.                                */
264             uint32_t            : 3;
265       __IOM uint32_t TRIGSEL    : 3;            /*!< [18..16] Select the ADC trigger source.                                   */
266       __IOM uint32_t TRIGPOL    : 1;            /*!< [19..19] This bit selects the ADC trigger polarity for external
267                                                      off chip triggers.                                                        */
268       __IOM uint32_t RPTTRIGSEL : 1;            /*!< [20..20] This bit selects which periodic trigger to use with
269                                                      RPTEN = 1.                                                                */
270             uint32_t            : 3;
271       __IOM uint32_t CLKSEL     : 2;            /*!< [25..24] Select the source and frequency for the general purpose
272                                                      ADC clock. HFRC_24MHZ is the only valid GP ADC clock selection
273                                                      and must be configured for proper operation.                              */
274             uint32_t            : 6;
275     } CFG_b;
276   } ;
277 
278   union {
279     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) This register indicates the basic power status
280                                                                     for the ADC. For detailed power status,
281                                                                     see the power control power status register.
282                                                                     ADC power mode 0 indicates the ADC is in
283                                                                     its full power state and is ready to process
284                                                                     scans. ADC Power mode 1 indicates the ADC
285                                                                     enabled and in a low power state.                          */
286 
287     struct {
288       __IOM uint32_t PWDSTAT    : 1;            /*!< [0..0] Indicates the power-status of the ADC.                             */
289             uint32_t            : 31;
290     } STAT_b;
291   } ;
292 
293   union {
294     __IOM uint32_t SWT;                         /*!< (@ 0x00000008) This register enables initiating an ADC scan
295                                                                     through software.                                          */
296 
297     struct {
298       __IOM uint32_t SWT        : 8;            /*!< [7..0] Writing 0x37 to this register generates a software trigger.        */
299             uint32_t            : 24;
300     } SWT_b;
301   } ;
302 
303   union {
304     __IOM uint32_t SL0CFG;                      /*!< (@ 0x0000000C) Slot 0 Configuration                                       */
305 
306     struct {
307       __IOM uint32_t SLEN0      : 1;            /*!< [0..0] This bit enables slot 0 for ADC conversions.                       */
308       __IOM uint32_t WCEN0      : 1;            /*!< [1..1] This bit enables the window compare function for slot
309                                                      0.                                                                        */
310             uint32_t            : 6;
311       __IOM uint32_t CHSEL0     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
312             uint32_t            : 4;
313       __IOM uint32_t PRMODE0    : 2;            /*!< [17..16] Set the Precision Mode For Slot 0.                               */
314       __IOM uint32_t TRKCYC0    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
315                                                      to the specified number of ADC clock cycles. (Note that
316                                                      a value of 0 in this register specifies the minimum required
317                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
318       __IOM uint32_t ADSEL0     : 3;            /*!< [26..24] Select the number of measurements to average in the
319                                                      accumulate divide module for this slot.                                   */
320             uint32_t            : 5;
321     } SL0CFG_b;
322   } ;
323 
324   union {
325     __IOM uint32_t SL1CFG;                      /*!< (@ 0x00000010) Slot 1 Configuration                                       */
326 
327     struct {
328       __IOM uint32_t SLEN1      : 1;            /*!< [0..0] This bit enables slot 1 for ADC conversions.                       */
329       __IOM uint32_t WCEN1      : 1;            /*!< [1..1] This bit enables the window compare function for slot
330                                                      1.                                                                        */
331             uint32_t            : 6;
332       __IOM uint32_t CHSEL1     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
333             uint32_t            : 4;
334       __IOM uint32_t PRMODE1    : 2;            /*!< [17..16] Set the Precision Mode For Slot 1.                               */
335       __IOM uint32_t TRKCYC1    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
336                                                      to the specified number of ADC clock cycles. (Note that
337                                                      a value of 0 in this register specifies the minimum required
338                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
339       __IOM uint32_t ADSEL1     : 3;            /*!< [26..24] Select the number of measurements to average in the
340                                                      accumulate divide module for this slot.                                   */
341             uint32_t            : 5;
342     } SL1CFG_b;
343   } ;
344 
345   union {
346     __IOM uint32_t SL2CFG;                      /*!< (@ 0x00000014) Slot 2 Configuration                                       */
347 
348     struct {
349       __IOM uint32_t SLEN2      : 1;            /*!< [0..0] This bit enables slot 2 for ADC conversions.                       */
350       __IOM uint32_t WCEN2      : 1;            /*!< [1..1] This bit enables the window compare function for slot
351                                                      2.                                                                        */
352             uint32_t            : 6;
353       __IOM uint32_t CHSEL2     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
354             uint32_t            : 4;
355       __IOM uint32_t PRMODE2    : 2;            /*!< [17..16] Set the Precision Mode For Slot 2.                               */
356       __IOM uint32_t TRKCYC2    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
357                                                      to the specified number of ADC clock cycles. (Note that
358                                                      a value of 0 in this register specifies the minimum required
359                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
360       __IOM uint32_t ADSEL2     : 3;            /*!< [26..24] Select the number of measurements to average in the
361                                                      accumulate divide module for this slot.                                   */
362             uint32_t            : 5;
363     } SL2CFG_b;
364   } ;
365 
366   union {
367     __IOM uint32_t SL3CFG;                      /*!< (@ 0x00000018) Slot 3 Configuration                                       */
368 
369     struct {
370       __IOM uint32_t SLEN3      : 1;            /*!< [0..0] This bit enables slot 3 for ADC conversions.                       */
371       __IOM uint32_t WCEN3      : 1;            /*!< [1..1] This bit enables the window compare function for slot
372                                                      3.                                                                        */
373             uint32_t            : 6;
374       __IOM uint32_t CHSEL3     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
375             uint32_t            : 4;
376       __IOM uint32_t PRMODE3    : 2;            /*!< [17..16] Set the Precision Mode For Slot 3.                               */
377       __IOM uint32_t TRKCYC3    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
378                                                      to the specified number of ADC clock cycles. (Note that
379                                                      a value of 0 in this register specifies the minimum required
380                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
381       __IOM uint32_t ADSEL3     : 3;            /*!< [26..24] Select the number of measurements to average in the
382                                                      accumulate divide module for this slot.                                   */
383             uint32_t            : 5;
384     } SL3CFG_b;
385   } ;
386 
387   union {
388     __IOM uint32_t SL4CFG;                      /*!< (@ 0x0000001C) Slot 4 Configuration                                       */
389 
390     struct {
391       __IOM uint32_t SLEN4      : 1;            /*!< [0..0] This bit enables slot 4 for ADC conversions.                       */
392       __IOM uint32_t WCEN4      : 1;            /*!< [1..1] This bit enables the window compare function for slot
393                                                      4.                                                                        */
394             uint32_t            : 6;
395       __IOM uint32_t CHSEL4     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
396             uint32_t            : 4;
397       __IOM uint32_t PRMODE4    : 2;            /*!< [17..16] Set the Precision Mode For Slot 4.                               */
398       __IOM uint32_t TRKCYC4    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
399                                                      to the specified number of ADC clock cycles. (Note that
400                                                      a value of 0 in this register specifies the minimum required
401                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
402       __IOM uint32_t ADSEL4     : 3;            /*!< [26..24] Select the number of measurements to average in the
403                                                      accumulate divide module for this slot.                                   */
404             uint32_t            : 5;
405     } SL4CFG_b;
406   } ;
407 
408   union {
409     __IOM uint32_t SL5CFG;                      /*!< (@ 0x00000020) Slot 5 Configuration                                       */
410 
411     struct {
412       __IOM uint32_t SLEN5      : 1;            /*!< [0..0] This bit enables slot 5 for ADC conversions.                       */
413       __IOM uint32_t WCEN5      : 1;            /*!< [1..1] This bit enables the window compare function for slot
414                                                      5.                                                                        */
415             uint32_t            : 6;
416       __IOM uint32_t CHSEL5     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
417             uint32_t            : 4;
418       __IOM uint32_t PRMODE5    : 2;            /*!< [17..16] Set the Precision Mode For Slot 5.                               */
419       __IOM uint32_t TRKCYC5    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
420                                                      to the specified number of ADC clock cycles. (Note that
421                                                      a value of 0 in this register specifies the minimum required
422                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
423       __IOM uint32_t ADSEL5     : 3;            /*!< [26..24] Select the number of measurements to average in the
424                                                      accumulate divide module for this slot.                                   */
425             uint32_t            : 5;
426     } SL5CFG_b;
427   } ;
428 
429   union {
430     __IOM uint32_t SL6CFG;                      /*!< (@ 0x00000024) Slot 6 Configuration                                       */
431 
432     struct {
433       __IOM uint32_t SLEN6      : 1;            /*!< [0..0] This bit enables slot 6 for ADC conversions.                       */
434       __IOM uint32_t WCEN6      : 1;            /*!< [1..1] This bit enables the window compare function for slot
435                                                      6.                                                                        */
436             uint32_t            : 6;
437       __IOM uint32_t CHSEL6     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
438             uint32_t            : 4;
439       __IOM uint32_t PRMODE6    : 2;            /*!< [17..16] Set the Precision Mode For Slot 6.                               */
440       __IOM uint32_t TRKCYC6    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
441                                                      to the specified number of ADC clock cycles. (Note that
442                                                      a value of 0 in this register specifies the minimum required
443                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
444       __IOM uint32_t ADSEL6     : 3;            /*!< [26..24] Select the number of measurements to average in the
445                                                      accumulate divide module for this slot.                                   */
446             uint32_t            : 5;
447     } SL6CFG_b;
448   } ;
449 
450   union {
451     __IOM uint32_t SL7CFG;                      /*!< (@ 0x00000028) Slot 7 Configuration                                       */
452 
453     struct {
454       __IOM uint32_t SLEN7      : 1;            /*!< [0..0] This bit enables slot 7 for ADC conversions.                       */
455       __IOM uint32_t WCEN7      : 1;            /*!< [1..1] This bit enables the window compare function for slot
456                                                      7.                                                                        */
457             uint32_t            : 6;
458       __IOM uint32_t CHSEL7     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
459             uint32_t            : 4;
460       __IOM uint32_t PRMODE7    : 2;            /*!< [17..16] Set the Precision Mode For Slot 7.                               */
461       __IOM uint32_t TRKCYC7    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
462                                                      to the specified number of ADC clock cycles. (Note that
463                                                      a value of 0 in this register specifies the minimum required
464                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
465       __IOM uint32_t ADSEL7     : 3;            /*!< [26..24] Select the number of measurements to average in the
466                                                      accumulate divide module for this slot.                                   */
467             uint32_t            : 5;
468     } SL7CFG_b;
469   } ;
470 
471   union {
472     __IOM uint32_t WULIM;                       /*!< (@ 0x0000002C) Window Comparator Upper Limits                             */
473 
474     struct {
475       __IOM uint32_t ULIM       : 20;           /*!< [19..0] Sets the upper limit for the window comparator.                   */
476             uint32_t            : 12;
477     } WULIM_b;
478   } ;
479 
480   union {
481     __IOM uint32_t WLLIM;                       /*!< (@ 0x00000030) Window Comparator Lower Limits                             */
482 
483     struct {
484       __IOM uint32_t LLIM       : 20;           /*!< [19..0] Sets the lower limit for the window comparator.                   */
485             uint32_t            : 12;
486     } WLLIM_b;
487   } ;
488 
489   union {
490     __IOM uint32_t SCWLIM;                      /*!< (@ 0x00000034) Scale Window Comparator Limits                             */
491 
492     struct {
493       __IOM uint32_t SCWLIMEN   : 1;            /*!< [0..0] Scale the window limits compare values per precision
494                                                      mode. When set to 0x0 (default), the values in the 20-bit
495                                                      limits registers will compare directly with the FIFO values
496                                                      regardless of the precision mode the slot is configured
497                                                      to. When set to 0x1, the compare values will be divided
498                                                      by the difference in precision bits while performing the
499                                                      window limit comparisons.                                                 */
500             uint32_t            : 31;
501     } SCWLIM_b;
502   } ;
503 
504   union {
505     __IOM uint32_t FIFO;                        /*!< (@ 0x00000038) The ADC FIFO Register contains the slot number
506                                                                     and fifo data for the oldest conversion
507                                                                     data in the FIFO. The COUNT field indicates
508                                                                     the total number of valid entries in the
509                                                                     FIFO. A write to this register will pop
510                                                                     one of the FIFO entries off the FIFO and
511                                                                     decrease the COUNT by 1 if the COUNT is
512                                                                     greater than zero.                                         */
513 
514     struct {
515       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
516       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
517       __IOM uint32_t SLOTNUM    : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
518       __IOM uint32_t RSVD       : 1;            /*!< [31..31] RESERVED.                                                        */
519     } FIFO_b;
520   } ;
521 
522   union {
523     __IOM uint32_t FIFOPR;                      /*!< (@ 0x0000003C) This is a Pop Read mirrored copy of the ADCFIFO
524                                                                     register with the only difference being
525                                                                     that reading this register will result in
526                                                                     a simultaneous FIFO POP which is also achieved
527                                                                     by writing to the ADCFIFO Register. Note:
528                                                                     The DFIFORDEN bit must be set in the CFG
529                                                                     register for the the destructive read to
530                                                                     be enabled.                                                */
531 
532     struct {
533       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
534       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
535       __IOM uint32_t SLOTNUMPR  : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
536       __IOM uint32_t RSVDPR     : 1;            /*!< [31..31] RESERVED.                                                        */
537     } FIFOPR_b;
538   } ;
539 
540   union {
541     __IOM uint32_t INTTRIGTIMER;                /*!< (@ 0x00000040) ADC-Internal Repeating Trigger Timer Configuration         */
542 
543     struct {
544       __IOM uint32_t TIMERMAX   : 10;           /*!< [9..0] Trigger counter count max, used as initial condition
545                                                      to trigger. Also used repeatedly each time counter reaches
546                                                      it to restart trigger timer at zero. To update this value,
547                                                      first disable the INTTRIGTIMER by setting TIMEREN to DIS,
548                                                      change TIMERMAX, and then reenable it INTTRIGTIMER by setting
549                                                      TIMEREN to EN again.                                                      */
550             uint32_t            : 6;
551       __IOM uint32_t CLKDIV     : 3;            /*!< [18..16] Configure number of divide-by-2 of clock source as
552                                                      input to trigger counter. (Max value of 5.) A value of
553                                                      0 in this register would not divide down the ADC input
554                                                      clock. A value of 1 would divide the ADC input clock frequency
555                                                      by 2. A value of 5 would divide the ADC input clock frequency
556                                                      by 2^5 = 32. To update this value, first disable the INTTRIGTIMER
557                                                      by setting TIMEREN to DIS, change CLKDIV, and then reenable
558                                                      it INTTRIGTIMER by setting TIMEREN to EN again.                           */
559             uint32_t            : 12;
560       __IOM uint32_t TIMEREN    : 1;            /*!< [31..31] ADC-internal trigger timer enable.                               */
561     } INTTRIGTIMER_b;
562   } ;
563   __IM  uint32_t  RESERVED[7];
564 
565   union {
566     __IOM uint32_t ZXCFG;                       /*!< (@ 0x00000060) Zero Crossing Comparator Configuration                     */
567 
568     struct {
569       __IOM uint32_t ZXEN       : 1;            /*!< [0..0] Enable the ZX comparator                                           */
570             uint32_t            : 3;
571       __IOM uint32_t ZXCHANSEL  : 1;            /*!< [4..4] Select which slots to use for zero crossing measurement.
572                                                      0 enables zero crossing detection on slots 0 and 2. 1 enables
573                                                      zero crossing detection on slots 1 and 3.                                 */
574             uint32_t            : 27;
575     } ZXCFG_b;
576   } ;
577 
578   union {
579     __IOM uint32_t ZXLIM;                       /*!< (@ 0x00000064) Zero Crossing Comparator Limits                            */
580 
581     struct {
582       __IOM uint32_t LZXC       : 12;           /*!< [11..0] Sets the lower integer sample limit for the ZX comparator.
583                                                      Note that these values are raw ADC values whose bounds
584                                                      are specified by PRMODE but not maniupulated by accumulate/divide
585                                                      logic. Therefore, there is no oversampling and no binary
586                                                      point in this value. Samples must enter the range between
587                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
588             uint32_t            : 4;
589       __IOM uint32_t UZXC       : 12;           /*!< [27..16] Sets the upper integer sample limit for the ZX comparator.
590                                                      Note that these values are raw ADC values whose bounds
591                                                      are specified by PRMODE but not maniupulated by accumulate/divide
592                                                      logic. Therefore, there is no oversampling and no binary
593                                                      point in this value. Samples must enter the range between
594                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
595             uint32_t            : 4;
596     } ZXLIM_b;
597   } ;
598 
599   union {
600     __IOM uint32_t GAINCFG;                     /*!< (@ 0x00000068) PGA Gain Configuration                                     */
601 
602     struct {
603       __IOM uint32_t PGACTRLEN  : 1;            /*!< [0..0] Enable PGA gain updates.                                           */
604             uint32_t            : 3;
605       __IOM uint32_t UPDATEMODE : 1;            /*!< [4..4] PGA update mode                                                    */
606             uint32_t            : 27;
607     } GAINCFG_b;
608   } ;
609 
610   union {
611     __IOM uint32_t GAIN;                        /*!< (@ 0x0000006C) PGA Gain Codes                                             */
612 
613     struct {
614       __IOM uint32_t LGA        : 7;            /*!< [6..0] Specifies the low gain code (0 to 102 decimal specifies
615                                                      -6.0 dB to 45.0 dB in half-dB increments) for channel A
616                                                      (slot 0).                                                                 */
617             uint32_t            : 1;
618       __IOM uint32_t HGADELTA   : 7;            /*!< [14..8] Specifies the high gain code as an delta from the LGA
619                                                      field for channel A (slot 1).                                             */
620             uint32_t            : 1;
621       __IOM uint32_t LGB        : 7;            /*!< [22..16] Specifies the low gain code (0 to 102 decimal specifies
622                                                      -6.0 dB to 45.0 dB in half-dB increments) for channel B
623                                                      (slot 2).                                                                 */
624             uint32_t            : 1;
625       __IOM uint32_t HGBDELTA   : 7;            /*!< [30..24] Specifies the high gain code as an delta from the LGB
626                                                      field for channel B (slot 3).                                             */
627             uint32_t            : 1;
628     } GAIN_b;
629   } ;
630   __IM  uint32_t  RESERVED1[13];
631 
632   union {
633     __IOM uint32_t SATCFG;                      /*!< (@ 0x000000A4) Saturation Comparator Configuration                        */
634 
635     struct {
636       __IOM uint32_t SATEN      : 1;            /*!< [0..0] Enable the saturation comparator                                   */
637             uint32_t            : 3;
638       __IOM uint32_t SATCHANSEL : 1;            /*!< [4..4] Select which slots to use for saturation measurement.
639                                                      0 enables saturation on slots 0 and 2. 1 enables saturation
640                                                      on slots 1 and 3.                                                         */
641             uint32_t            : 27;
642     } SATCFG_b;
643   } ;
644 
645   union {
646     __IOM uint32_t SATLIM;                      /*!< (@ 0x000000A8) Saturation Comparator Limits                               */
647 
648     struct {
649       __IOM uint32_t LSATC      : 12;           /*!< [11..0] Sets the lower integer sample limit for the saturation
650                                                      comparator. Note that these values are raw ADC values whose
651                                                      bounds are specified by PRMODE but not manipulated by accumulate/divide
652                                                      logic. Therefore, there is no oversampling and no binary
653                                                      point in this value.                                                      */
654             uint32_t            : 4;
655       __IOM uint32_t USATC      : 12;           /*!< [27..16] Sets the upper integer sample limit for the saturation
656                                                      comparator. Note that these values are raw ADC values whose
657                                                      bounds are specified by PRMODE but not manipulated by accumulate/divide
658                                                      logic. Therefore, there is no oversampling and no binary
659                                                      point in this value.                                                      */
660             uint32_t            : 4;
661     } SATLIM_b;
662   } ;
663 
664   union {
665     __IOM uint32_t SATMAX;                      /*!< (@ 0x000000AC) Saturation Comparator Event Counter Limits                 */
666 
667     struct {
668       __IOM uint32_t SATCAMAX   : 12;           /*!< [11..0] Sets the number of saturation events that may occur
669                                                      before a SATCA interrupt occurs. Once this interrupt occurs,
670                                                      the saturation event counter must be cleared by writing
671                                                      the SATCLR register. A value of 0 is invalid and will cause
672                                                      the saturation interrupt to assert immediately.                           */
673             uint32_t            : 4;
674       __IOM uint32_t SATCBMAX   : 12;           /*!< [27..16] Sets the number of saturation events that may occur
675                                                      before a SATCB interrupt occurs. Once this interrupt occurs,
676                                                      the saturation event counter must be cleared by writing
677                                                      the SATCLR register. A value of 0 is invalid and will cause
678                                                      the saturation interrupt to assert immediately.                           */
679             uint32_t            : 4;
680     } SATMAX_b;
681   } ;
682 
683   union {
684     __IOM uint32_t SATCLR;                      /*!< (@ 0x000000B0) Clears the saturation event counter registers              */
685 
686     struct {
687       __IOM uint32_t SATCACLR   : 1;            /*!< [0..0] Clear saturation event counter register for channel A
688                                                      (slots 0 or 1, depending on SATCHANSEL)                                   */
689       __IOM uint32_t SATCBCLR   : 1;            /*!< [1..1] Clear saturation event counter register for channel B
690                                                      (slots 2 or 3, depending on SATCHANSEL)                                   */
691             uint32_t            : 30;
692     } SATCLR_b;
693   } ;
694   __IM  uint32_t  RESERVED2[83];
695 
696   union {
697     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
698                                                                     to generate the corresponding interrupt.                   */
699 
700     struct {
701       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
702       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
703       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
704       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
705       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
706       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
707       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
708       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
709       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
710       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
711       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
712       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
713             uint32_t            : 20;
714     } INTEN_b;
715   } ;
716 
717   union {
718     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
719                                                                     cause of a recent interrupt.                               */
720 
721     struct {
722       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
723       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
724       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
725       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
726       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
727       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
728       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
729       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
730       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
731       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
732       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
733       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
734             uint32_t            : 20;
735     } INTSTAT_b;
736   } ;
737 
738   union {
739     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
740                                                                     the interrupt status associated with that
741                                                                     bit.                                                       */
742 
743     struct {
744       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
745       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
746       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
747       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
748       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
749       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
750       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
751       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
752       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
753       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
754       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
755       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
756             uint32_t            : 20;
757     } INTCLR_b;
758   } ;
759 
760   union {
761     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
762                                                                     generate an interrupt from this module.
763                                                                     (Generally used for testing purposes).                     */
764 
765     struct {
766       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
767       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
768       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
769       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
770       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
771       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
772       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
773       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
774       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
775       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
776       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
777       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
778             uint32_t            : 20;
779     } INTSET_b;
780   } ;
781   __IM  uint32_t  RESERVED3[12];
782 
783   union {
784     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable                                         */
785 
786     struct {
787       __IOM uint32_t DFIFO75    : 1;            /*!< [0..0] Trigger DMA upon FIFO 75 percent Full                              */
788       __IOM uint32_t DFIFOFULL  : 1;            /*!< [1..1] Trigger DMA upon FIFO 100 percent Full                             */
789             uint32_t            : 30;
790     } DMATRIGEN_b;
791   } ;
792 
793   union {
794     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status                                         */
795 
796     struct {
797       __IOM uint32_t D75STAT    : 1;            /*!< [0..0] Triggered DMA from FIFO 75 percent Full                            */
798       __IOM uint32_t DFULLSTAT  : 1;            /*!< [1..1] Triggered DMA from FIFO 100 percent Full                           */
799             uint32_t            : 30;
800     } DMATRIGSTAT_b;
801   } ;
802   __IM  uint32_t  RESERVED4[14];
803 
804   union {
805     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration                                          */
806 
807     struct {
808       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
809             uint32_t            : 1;
810       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
811             uint32_t            : 5;
812       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
813       __IOM uint32_t DMADYNPRI  : 1;            /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
814                                                      FIFO is full, priority is automatically set to HIGH. Otherwise,
815                                                      DMAPRI is used.                                                           */
816             uint32_t            : 7;
817       __IOM uint32_t DMAMSK     : 1;            /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO
818                                                      contents to memory                                                        */
819       __IOM uint32_t DPWROFF    : 1;            /*!< [18..18] Power Off the ADC System upon DMACPL.                            */
820             uint32_t            : 13;
821     } DMACFG_b;
822   } ;
823   __IM  uint32_t  RESERVED5;
824 
825   union {
826     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
827 
828     struct {
829             uint32_t            : 2;
830       __IOM uint32_t TOTCOUNT   : 16;           /*!< [17..2] Total Transfer Count                                              */
831             uint32_t            : 14;
832     } DMATOTCOUNT_b;
833   } ;
834 
835   union {
836     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address                                         */
837 
838     struct {
839       __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address                                                */
840       __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
841     } DMATARGADDR_b;
842   } ;
843 
844   union {
845     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status                                                 */
846 
847     struct {
848       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
849       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
850       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
851             uint32_t            : 29;
852     } DMASTAT_b;
853   } ;
854 } ADC_Type;                                     /*!< Size = 660 (0x294)                                                        */
855 
856 
857 
858 /* =========================================================================================================================== */
859 /* ================                                          APBDMA                                           ================ */
860 /* =========================================================================================================================== */
861 
862 
863 /**
864   * @brief APB DMA Register Interfaces (APBDMA)
865   */
866 
867 typedef struct {                                /*!< (@ 0x40011000) APBDMA Structure                                           */
868 
869   union {
870     __IOM uint32_t BBVALUE;                     /*!< (@ 0x00000000) Control                                                    */
871 
872     struct {
873       __IOM uint32_t DATAOUT    : 8;            /*!< [7..0] Data Output Values                                                 */
874             uint32_t            : 8;
875       __IOM uint32_t PIN        : 8;            /*!< [23..16] PIO values                                                       */
876             uint32_t            : 8;
877     } BBVALUE_b;
878   } ;
879 
880   union {
881     __IOM uint32_t BBSETCLEAR;                  /*!< (@ 0x00000004) Set/Clear                                                  */
882 
883     struct {
884       __IOM uint32_t SET        : 8;            /*!< [7..0] Write 1 to Set PIO value (set hier priority than clear
885                                                      if both bit set)                                                          */
886             uint32_t            : 8;
887       __IOM uint32_t CLEAR      : 8;            /*!< [23..16] Write 1 to Clear PIO value                                       */
888             uint32_t            : 8;
889     } BBSETCLEAR_b;
890   } ;
891 
892   union {
893     __IOM uint32_t BBINPUT;                     /*!< (@ 0x00000008) PIO Input Values                                           */
894 
895     struct {
896       __IOM uint32_t DATAIN     : 8;            /*!< [7..0] PIO values                                                         */
897             uint32_t            : 24;
898     } BBINPUT_b;
899   } ;
900   __IM  uint32_t  RESERVED[5];
901 
902   union {
903     __IOM uint32_t DEBUGDATA;                   /*!< (@ 0x00000020) PIO Input Values                                           */
904 
905     struct {
906       __IOM uint32_t DEBUGDATA  : 32;           /*!< [31..0] Debug Data                                                        */
907     } DEBUGDATA_b;
908   } ;
909   __IM  uint32_t  RESERVED1[7];
910 
911   union {
912     __IOM uint32_t DEBUG;                       /*!< (@ 0x00000040) PIO Input Values                                           */
913 
914     struct {
915       __IOM uint32_t DEBUGEN    : 4;            /*!< [3..0] Debug Enable                                                       */
916             uint32_t            : 28;
917     } DEBUG_b;
918   } ;
919 } APBDMA_Type;                                  /*!< Size = 68 (0x44)                                                          */
920 
921 
922 
923 /* =========================================================================================================================== */
924 /* ================                                          AUDADC                                           ================ */
925 /* =========================================================================================================================== */
926 
927 
928 /**
929   * @brief Audio Analog Digital Converter Control (AUDADC)
930   */
931 
932 typedef struct {                                /*!< (@ 0x40210000) AUDADC Structure                                           */
933 
934   union {
935     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The Audio ADC Configuration Register contains
936                                                                     the software control for selecting the clock
937                                                                     frequency used for the SAR conversions,
938                                                                     the trigger polarity, the trigger select,
939                                                                     the reference voltage select, the low power
940                                                                     mode, the operating mode (single scan per
941                                                                     trigger vs. repeating mode) and AUDADC enable.             */
942 
943     struct {
944       __IOM uint32_t ADCEN      : 1;            /*!< [0..0] This bit enables the AUDADC module. While the AUDADC
945                                                      is enabled, the ADCCFG and SLOT Configuration regsiter
946                                                      settings must remain stable and unchanged. All configuration
947                                                      register settings, slot configuration settings and window
948                                                      comparison settings should be written prior to setting
949                                                      the ADCEN bit to '1'.                                                     */
950             uint32_t            : 1;
951       __IOM uint32_t RPTEN      : 1;            /*!< [2..2] This bit enables Repeating Scan Mode.                              */
952       __IOM uint32_t LPMODE     : 1;            /*!< [3..3] Select power mode to enter between active scans.                   */
953       __IOM uint32_t CKMODE     : 1;            /*!< [4..4] Clock mode register                                                */
954             uint32_t            : 7;
955       __IOM uint32_t DFIFORDEN  : 1;            /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
956                                                      FIFO pop upon reading the FIFOPR register.                                */
957       __IOM uint32_t SAMPMODE   : 1;            /*!< [13..13] Audio ADC sampling mode. Changes to this control bit
958                                                      are applied when the audio ADC is not performing conversions.
959                                                      This is the only control bit which is properly synchronized
960                                                      to AUDADC operation.                                                      */
961             uint32_t            : 2;
962       __IOM uint32_t TRIGSEL    : 3;            /*!< [18..16] Select the AUDADC trigger source.                                */
963       __IOM uint32_t TRIGPOL    : 1;            /*!< [19..19] This bit selects the AUDADC trigger polarity for external
964                                                      off chip triggers.                                                        */
965       __IOM uint32_t RPTTRIGSEL : 1;            /*!< [20..20] This bit selects which periodic trigger to use with
966                                                      RPTEN = 1.                                                                */
967             uint32_t            : 3;
968       __IOM uint32_t CLKSEL     : 2;            /*!< [25..24] Select the source and frequency for the AUDADC clock.
969                                                      All values not enumerated below are undefined.Whenever
970                                                      changing the clock source to HFRC2, the MISC_HFRC2FRC bit
971                                                      in the CLKGEN module must first be set. The sequence for
972                                                      changing the clock source to HFRC2 is to first force HFRC2
973                                                      on by setting the CLKGEN_MISC_HFRC2FRC bit, select the
974                                                      HFRC2 clock in this field, and then engage the peripheral.
975                                                      The HFRC2FRC bit should remain set while the HFRC2 is being
976                                                      used.If HFRC2 is the current clock source, then shutti                    */
977             uint32_t            : 6;
978     } CFG_b;
979   } ;
980 
981   union {
982     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) This register indicates the basic power status
983                                                                     for the AUDADC. For detailed power status,
984                                                                     see the power control power status register.
985                                                                     AUDADC power mode 0 indicates the AUDADC
986                                                                     is in its full power state and is ready
987                                                                     to process scans. AUDADC Power mode 1 indicates
988                                                                     the AUDADC enabled and in a low power state.               */
989 
990     struct {
991       __IOM uint32_t PWDSTAT    : 1;            /*!< [0..0] Indicates the power-status of the AUDADC.                          */
992             uint32_t            : 31;
993     } STAT_b;
994   } ;
995 
996   union {
997     __IOM uint32_t SWT;                         /*!< (@ 0x00000008) This register enables initiating an AUDADC scan
998                                                                     through software.                                          */
999 
1000     struct {
1001       __IOM uint32_t SWT        : 8;            /*!< [7..0] Writing 0x37 to this register generates a software trigger.        */
1002             uint32_t            : 24;
1003     } SWT_b;
1004   } ;
1005 
1006   union {
1007     __IOM uint32_t SL0CFG;                      /*!< (@ 0x0000000C) Slot 0 Configuration                                       */
1008 
1009     struct {
1010       __IOM uint32_t SLEN0      : 1;            /*!< [0..0] This bit enables slot 0 for AUDADC conversions.                    */
1011       __IOM uint32_t WCEN0      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1012                                                      0.                                                                        */
1013             uint32_t            : 6;
1014       __IOM uint32_t CHSEL0     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1015             uint32_t            : 4;
1016       __IOM uint32_t PRMODE0    : 2;            /*!< [17..16] Set the Precision Mode For Slot 0.                               */
1017       __IOM uint32_t TRKCYC0    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1018                                                      to the specified number of AUDADC clock cycles. (Note that
1019                                                      a value of 0 in this register specifies the minimum required
1020                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1021       __IOM uint32_t ADSEL0     : 3;            /*!< [26..24] Select the number of measurements to average in the
1022                                                      accumulate divide module for this slot.                                   */
1023             uint32_t            : 5;
1024     } SL0CFG_b;
1025   } ;
1026 
1027   union {
1028     __IOM uint32_t SL1CFG;                      /*!< (@ 0x00000010) Slot 1 Configuration                                       */
1029 
1030     struct {
1031       __IOM uint32_t SLEN1      : 1;            /*!< [0..0] This bit enables slot 1 for AUDADC conversions.                    */
1032       __IOM uint32_t WCEN1      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1033                                                      1.                                                                        */
1034             uint32_t            : 6;
1035       __IOM uint32_t CHSEL1     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1036             uint32_t            : 4;
1037       __IOM uint32_t PRMODE1    : 2;            /*!< [17..16] Set the Precision Mode For Slot 1.                               */
1038       __IOM uint32_t TRKCYC1    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1039                                                      to the specified number of AUDADC clock cycles. (Note that
1040                                                      a value of 0 in this register specifies the minimum required
1041                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1042       __IOM uint32_t ADSEL1     : 3;            /*!< [26..24] Select the number of measurements to average in the
1043                                                      accumulate divide module for this slot.                                   */
1044             uint32_t            : 5;
1045     } SL1CFG_b;
1046   } ;
1047 
1048   union {
1049     __IOM uint32_t SL2CFG;                      /*!< (@ 0x00000014) Slot 2 Configuration                                       */
1050 
1051     struct {
1052       __IOM uint32_t SLEN2      : 1;            /*!< [0..0] This bit enables slot 2 for AUDADC conversions.                    */
1053       __IOM uint32_t WCEN2      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1054                                                      2.                                                                        */
1055             uint32_t            : 6;
1056       __IOM uint32_t CHSEL2     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1057             uint32_t            : 4;
1058       __IOM uint32_t PRMODE2    : 2;            /*!< [17..16] Set the Precision Mode For Slot 2.                               */
1059       __IOM uint32_t TRKCYC2    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1060                                                      to the specified number of AUDADC clock cycles. (Note that
1061                                                      a value of 0 in this register specifies the minimum required
1062                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1063       __IOM uint32_t ADSEL2     : 3;            /*!< [26..24] Select the number of measurements to average in the
1064                                                      accumulate divide module for this slot.                                   */
1065             uint32_t            : 5;
1066     } SL2CFG_b;
1067   } ;
1068 
1069   union {
1070     __IOM uint32_t SL3CFG;                      /*!< (@ 0x00000018) Slot 3 Configuration                                       */
1071 
1072     struct {
1073       __IOM uint32_t SLEN3      : 1;            /*!< [0..0] This bit enables slot 3 for AUDADC conversions.                    */
1074       __IOM uint32_t WCEN3      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1075                                                      3.                                                                        */
1076             uint32_t            : 6;
1077       __IOM uint32_t CHSEL3     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1078             uint32_t            : 4;
1079       __IOM uint32_t PRMODE3    : 2;            /*!< [17..16] Set the Precision Mode For Slot 3.                               */
1080       __IOM uint32_t TRKCYC3    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1081                                                      to the specified number of AUDADC clock cycles. (Note that
1082                                                      a value of 0 in this register specifies the minimum required
1083                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1084       __IOM uint32_t ADSEL3     : 3;            /*!< [26..24] Select the number of measurements to average in the
1085                                                      accumulate divide module for this slot.                                   */
1086             uint32_t            : 5;
1087     } SL3CFG_b;
1088   } ;
1089 
1090   union {
1091     __IOM uint32_t SL4CFG;                      /*!< (@ 0x0000001C) Slot 4 Configuration                                       */
1092 
1093     struct {
1094       __IOM uint32_t SLEN4      : 1;            /*!< [0..0] This bit enables slot 4 for AUDADC conversions.                    */
1095       __IOM uint32_t WCEN4      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1096                                                      4.                                                                        */
1097             uint32_t            : 6;
1098       __IOM uint32_t CHSEL4     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1099             uint32_t            : 4;
1100       __IOM uint32_t PRMODE4    : 2;            /*!< [17..16] Set the Precision Mode For Slot 4.                               */
1101       __IOM uint32_t TRKCYC4    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1102                                                      to the specified number of AUDADC clock cycles. (Note that
1103                                                      a value of 0 in this register specifies the minimum required
1104                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1105       __IOM uint32_t ADSEL4     : 3;            /*!< [26..24] Select the number of measurements to average in the
1106                                                      accumulate divide module for this slot.                                   */
1107             uint32_t            : 5;
1108     } SL4CFG_b;
1109   } ;
1110 
1111   union {
1112     __IOM uint32_t SL5CFG;                      /*!< (@ 0x00000020) Slot 5 Configuration                                       */
1113 
1114     struct {
1115       __IOM uint32_t SLEN5      : 1;            /*!< [0..0] This bit enables slot 5 for AUDADC conversions.                    */
1116       __IOM uint32_t WCEN5      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1117                                                      5.                                                                        */
1118             uint32_t            : 6;
1119       __IOM uint32_t CHSEL5     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1120             uint32_t            : 4;
1121       __IOM uint32_t PRMODE5    : 2;            /*!< [17..16] Set the Precision Mode For Slot 5.                               */
1122       __IOM uint32_t TRKCYC5    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1123                                                      to the specified number of AUDADC clock cycles. (Note that
1124                                                      a value of 0 in this register specifies the minimum required
1125                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1126       __IOM uint32_t ADSEL5     : 3;            /*!< [26..24] Select the number of measurements to average in the
1127                                                      accumulate divide module for this slot.                                   */
1128             uint32_t            : 5;
1129     } SL5CFG_b;
1130   } ;
1131 
1132   union {
1133     __IOM uint32_t SL6CFG;                      /*!< (@ 0x00000024) Slot 6 Configuration                                       */
1134 
1135     struct {
1136       __IOM uint32_t SLEN6      : 1;            /*!< [0..0] This bit enables slot 6 for AUDADC conversions.                    */
1137       __IOM uint32_t WCEN6      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1138                                                      6.                                                                        */
1139             uint32_t            : 6;
1140       __IOM uint32_t CHSEL6     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1141             uint32_t            : 4;
1142       __IOM uint32_t PRMODE6    : 2;            /*!< [17..16] Set the Precision Mode For Slot 6.                               */
1143       __IOM uint32_t TRKCYC6    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1144                                                      to the specified number of AUDADC clock cycles. (Note that
1145                                                      a value of 0 in this register specifies the minimum required
1146                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1147       __IOM uint32_t ADSEL6     : 3;            /*!< [26..24] Select the number of measurements to average in the
1148                                                      accumulate divide module for this slot.                                   */
1149             uint32_t            : 5;
1150     } SL6CFG_b;
1151   } ;
1152 
1153   union {
1154     __IOM uint32_t SL7CFG;                      /*!< (@ 0x00000028) Slot 7 Configuration                                       */
1155 
1156     struct {
1157       __IOM uint32_t SLEN7      : 1;            /*!< [0..0] This bit enables slot 7 for AUDADC conversions.                    */
1158       __IOM uint32_t WCEN7      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1159                                                      7.                                                                        */
1160             uint32_t            : 6;
1161       __IOM uint32_t CHSEL7     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1162             uint32_t            : 4;
1163       __IOM uint32_t PRMODE7    : 2;            /*!< [17..16] Set the Precision Mode For Slot 7.                               */
1164       __IOM uint32_t TRKCYC7    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1165                                                      to the specified number of AUDADC clock cycles. (Note that
1166                                                      a value of 0 in this register specifies the minimum required
1167                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1168       __IOM uint32_t ADSEL7     : 3;            /*!< [26..24] Select the number of measurements to average in the
1169                                                      accumulate divide module for this slot.                                   */
1170             uint32_t            : 5;
1171     } SL7CFG_b;
1172   } ;
1173 
1174   union {
1175     __IOM uint32_t WULIM;                       /*!< (@ 0x0000002C) Window Comparator Upper Limits                             */
1176 
1177     struct {
1178       __IOM uint32_t ULIM       : 20;           /*!< [19..0] Sets the upper limit for the window comparator.                   */
1179             uint32_t            : 12;
1180     } WULIM_b;
1181   } ;
1182 
1183   union {
1184     __IOM uint32_t WLLIM;                       /*!< (@ 0x00000030) Window Comparator Lower Limits                             */
1185 
1186     struct {
1187       __IOM uint32_t LLIM       : 20;           /*!< [19..0] Sets the lower limit for the window comparator.                   */
1188             uint32_t            : 12;
1189     } WLLIM_b;
1190   } ;
1191 
1192   union {
1193     __IOM uint32_t SCWLIM;                      /*!< (@ 0x00000034) Scale Window Comparator Limits                             */
1194 
1195     struct {
1196       __IOM uint32_t SCWLIMEN   : 1;            /*!< [0..0] Scale the window limits compare values per precision
1197                                                      mode. When set to 0x0 (default), the values in the 20-bit
1198                                                      limits registers will compare directly with the FIFO values
1199                                                      regardless of the precision mode the slot is configured
1200                                                      to. When set to 0x1, the compare values will be divided
1201                                                      by the difference in precision bits while performing the
1202                                                      window limit comparisons.                                                 */
1203             uint32_t            : 31;
1204     } SCWLIM_b;
1205   } ;
1206 
1207   union {
1208     __IOM uint32_t FIFO;                        /*!< (@ 0x00000038) The AUDADC FIFO Register contains up to 2 samples
1209                                                                     for a single channel (high and low gain
1210                                                                     PGA samples), each sample up to 12-bits.
1211                                                                     It also contains meta data in the form of
1212                                                                     which audio channel the sample(s) are from
1213                                                                     along with the PGA gain code for that sample
1214                                                                     pair. When no data is present, FIFO entry
1215                                                                     reads back as all 1s (0xFFFFFFFF).                         */
1216 
1217     struct {
1218       __IOM uint32_t METALO     : 4;            /*!< [3..0] Meta data about this sample which represents the lower
1219                                                      4 bits of the PGA gain code                                               */
1220       __IOM uint32_t LGDATA     : 12;           /*!< [15..4] Low-gain PGA sample data                                          */
1221       __IOM uint32_t METAHI     : 3;            /*!< [18..16] Meta data about this sample which represents the upper
1222                                                      3 bits of the PGA gain code                                               */
1223       __IOM uint32_t MIC        : 1;            /*!< [19..19] Which audio channel this data is from encoded as int(slot
1224                                                      number/2). In other words, this is 1 if data is from slots
1225                                                      2 or 3, or 0 if from slots 0 or 1.                                        */
1226       __IOM uint32_t HGDATA     : 12;           /*!< [31..20] High-gain PGA sample data                                        */
1227     } FIFO_b;
1228   } ;
1229 
1230   union {
1231     __IOM uint32_t FIFOPR;                      /*!< (@ 0x0000003C) This is a pop-on-read mirrored copy of the ADCFIFO
1232                                                                     register with the only difference being
1233                                                                     that reading this register will result in
1234                                                                     a simultaneous FIFO POP which is also achieved
1235                                                                     by writing to the ADCFIFO Register. Note:
1236                                                                     The DFIFORDEN bit must be set in the CFG
1237                                                                     register for the the destructive read to
1238                                                                     be enabled.                                                */
1239 
1240     struct {
1241       __IOM uint32_t METALOPR   : 4;            /*!< [3..0] Meta data about this sample which represents the lower
1242                                                      4 bits of the PGA gain code                                               */
1243       __IOM uint32_t LGDATAPR   : 12;           /*!< [15..4] Low-gain PGA sample data                                          */
1244       __IOM uint32_t METAHIPR   : 3;            /*!< [18..16] Meta data about this sample which represents the upper
1245                                                      3 bits of the PGA gain code                                               */
1246       __IOM uint32_t MICPR      : 1;            /*!< [19..19] Which audio channel this data is from encoded as int(slot
1247                                                      number/2). In other words, this is 1 if data is from slots
1248                                                      2 or 3, or 0 if from slots 0 or 1.                                        */
1249       __IOM uint32_t HGDATAPR   : 12;           /*!< [31..20] High-gain PGA sample data                                        */
1250     } FIFOPR_b;
1251   } ;
1252 
1253   union {
1254     __IOM uint32_t INTTRIGTIMER;                /*!< (@ 0x00000040) AUDADC-Internal Repeating Trigger Timer Configuration      */
1255 
1256     struct {
1257       __IOM uint32_t TIMERMAX   : 10;           /*!< [9..0] Trigger counter count max, used as initial condition
1258                                                      to trigger. Also used repeatedly each time counter reaches
1259                                                      it to restart trigger timer at zero. To update this value,
1260                                                      first disable the INTTRIGTIMER by setting TIMEREN to DIS,
1261                                                      change TIMERMAX, and then reenable it INTTRIGTIMER by setting
1262                                                      TIMEREN to EN again.                                                      */
1263             uint32_t            : 6;
1264       __IOM uint32_t CLKDIV     : 3;            /*!< [18..16] Configure number of divide-by-2 of clock source as
1265                                                      input to trigger counter. (Max value of 5.) A value of
1266                                                      0 in this register would not divide down the AUDADC input
1267                                                      clock. A value of 1 would divide the AUDADC input clock
1268                                                      frequency by 2. A value of 5 would divide the AUDADC input
1269                                                      clock frequency by 2^5 = 32. To update this value, first
1270                                                      disable the INTTRIGTIMER by setting TIMEREN to DIS, change
1271                                                      CLKDIV, and then reenable it INTTRIGTIMER by setting TIMEREN
1272                                                      to EN again.                                                              */
1273             uint32_t            : 12;
1274       __IOM uint32_t TIMEREN    : 1;            /*!< [31..31] AUDADC-internal trigger timer enable.                            */
1275     } INTTRIGTIMER_b;
1276   } ;
1277 
1278   union {
1279     __IOM uint32_t FIFOSTAT;                    /*!< (@ 0x00000044) This register contains status of the data FIFO.            */
1280 
1281     struct {
1282       __IOM uint32_t FIFOCNT    : 8;            /*!< [7..0] Number of valid entries in the AUDADC FIFO.                        */
1283             uint32_t            : 24;
1284     } FIFOSTAT_b;
1285   } ;
1286 
1287   union {
1288     __IOM uint32_t DATAOFFSET;                  /*!< (@ 0x00000048) ERROR: reg_brief VALUE MISSING                             */
1289 
1290     struct {
1291       __IOM uint32_t OFFSET     : 13;           /*!< [12..0] Add this signed offset to data before being written
1292                                                      to the FIFO. This enables the user to convert unsigned
1293                                                      samples to signed or remove a DC offset on the samples.
1294                                                      Note that this does NOT affect the comparator limits, which
1295                                                      still operate on original unsigned samples.                               */
1296             uint32_t            : 19;
1297     } DATAOFFSET_b;
1298   } ;
1299   __IM  uint32_t  RESERVED[5];
1300 
1301   union {
1302     __IOM uint32_t ZXCFG;                       /*!< (@ 0x00000060) Zero Crossing Comparator Configuration                     */
1303 
1304     struct {
1305       __IOM uint32_t ZXEN       : 1;            /*!< [0..0] Enable the ZX comparator                                           */
1306             uint32_t            : 3;
1307       __IOM uint32_t ZXCHANSEL  : 1;            /*!< [4..4] Select which slots to use for zero crossing measurement.
1308                                                      0 enables zero crossing detection on slots 0 and 2. 1 enables
1309                                                      zero crossing detection on slots 1 and 3.                                 */
1310             uint32_t            : 27;
1311     } ZXCFG_b;
1312   } ;
1313 
1314   union {
1315     __IOM uint32_t ZXLIM;                       /*!< (@ 0x00000064) Zero Crossing Comparator Limits                            */
1316 
1317     struct {
1318       __IOM uint32_t LZXC       : 12;           /*!< [11..0] Sets the lower integer sample limit for the ZX comparator.
1319                                                      Note that these values are raw AUDADC values whose bounds
1320                                                      are specified by PRMODE but not maniupulated by accumulate/divide
1321                                                      logic. Therefore, there is no oversampling and no binary
1322                                                      point in this value. Samples must enter the range between
1323                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
1324             uint32_t            : 4;
1325       __IOM uint32_t UZXC       : 12;           /*!< [27..16] Sets the upper integer sample limit for the ZX comparator.
1326                                                      Note that these values are raw AUDADC values whose bounds
1327                                                      are specified by PRMODE but not maniupulated by accumulate/divide
1328                                                      logic. Therefore, there is no oversampling and no binary
1329                                                      point in this value. Samples must enter the range between
1330                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
1331             uint32_t            : 4;
1332     } ZXLIM_b;
1333   } ;
1334 
1335   union {
1336     __IOM uint32_t GAINCFG;                     /*!< (@ 0x00000068) PGA Gain Configuration                                     */
1337 
1338     struct {
1339       __IOM uint32_t PGACTRLEN  : 1;            /*!< [0..0] Enable PGA gain updates.                                           */
1340             uint32_t            : 3;
1341       __IOM uint32_t UPDATEMODE : 1;            /*!< [4..4] PGA update mode                                                    */
1342             uint32_t            : 27;
1343     } GAINCFG_b;
1344   } ;
1345 
1346   union {
1347     __IOM uint32_t GAIN;                        /*!< (@ 0x0000006C) PGA Gain Codes                                             */
1348 
1349     struct {
1350       __IOM uint32_t LGA        : 7;            /*!< [6..0] Specifies the low gain code (0 to 60 decimal specifies
1351                                                      -6.0 dB to 24.0 dB in half-dB increments) for channel A
1352                                                      (slot 0).                                                                 */
1353             uint32_t            : 1;
1354       __IOM uint32_t HGADELTA   : 7;            /*!< [14..8] Specifies the high gain code (0 to 60 decimal specifies
1355                                                      0 dB to 30.0 dB in half-dB increments) as the delta from
1356                                                      the LGA field for channel A (slot 1). Note that HGADELTA
1357                                                      must be LE (24 - LGA) dB.                                                 */
1358             uint32_t            : 1;
1359       __IOM uint32_t LGB        : 7;            /*!< [22..16] Specifies the low gain code (0 to 60 decimal specifies
1360                                                      -6.0 dB to 24.0 dB in half-dB increments) for channel B
1361                                                      (slot 2).                                                                 */
1362             uint32_t            : 1;
1363       __IOM uint32_t HGBDELTA   : 7;            /*!< [30..24] Specifies the high gain code (0 to 60 decimal specifies
1364                                                      0 dB to 30.0 dB in half-dB increments) as the delta from
1365                                                      the LGB field for channel B (slot 3). Note that HGBDELTA
1366                                                      must be LE (24 - LGB) dB.                                                 */
1367             uint32_t            : 1;
1368     } GAIN_b;
1369   } ;
1370   __IM  uint32_t  RESERVED1[13];
1371 
1372   union {
1373     __IOM uint32_t SATCFG;                      /*!< (@ 0x000000A4) Saturation Comparator Configuration                        */
1374 
1375     struct {
1376       __IOM uint32_t SATEN      : 1;            /*!< [0..0] Enable the saturation comparator                                   */
1377             uint32_t            : 3;
1378       __IOM uint32_t SATCHANSEL : 1;            /*!< [4..4] Select which slots to use for saturation measurement.
1379                                                      0 enables saturation on slots 0 and 2. 1 enables saturation
1380                                                      on slots 1 and 3.                                                         */
1381             uint32_t            : 27;
1382     } SATCFG_b;
1383   } ;
1384 
1385   union {
1386     __IOM uint32_t SATLIM;                      /*!< (@ 0x000000A8) Saturation Comparator Limits                               */
1387 
1388     struct {
1389       __IOM uint32_t LSATC      : 12;           /*!< [11..0] Sets the lower integer sample limit for the saturation
1390                                                      comparator. Note that these values are raw AUDADC values
1391                                                      whose bounds are specified by PRMODE but not manipulated
1392                                                      by accumulate/divide logic. Therefore, there is no oversampling
1393                                                      and no binary point in this value.                                        */
1394             uint32_t            : 4;
1395       __IOM uint32_t USATC      : 12;           /*!< [27..16] Sets the upper integer sample limit for the saturation
1396                                                      comparator. Note that these values are raw AUDADC values
1397                                                      whose bounds are specified by PRMODE but not manipulated
1398                                                      by accumulate/divide logic. Therefore, there is no oversampling
1399                                                      and no binary point in this value.                                        */
1400             uint32_t            : 4;
1401     } SATLIM_b;
1402   } ;
1403 
1404   union {
1405     __IOM uint32_t SATMAX;                      /*!< (@ 0x000000AC) Saturation Comparator Event Counter Limits                 */
1406 
1407     struct {
1408       __IOM uint32_t SATCAMAX   : 12;           /*!< [11..0] Sets the number of saturation events that may occur
1409                                                      before a SATCA interrupt occurs. Once this interrupt occurs,
1410                                                      the saturation event counter must be cleared by writing
1411                                                      the SATCLR register. A value of 0 is invalid and will cause
1412                                                      the saturation interrupt to assert immediately.                           */
1413             uint32_t            : 4;
1414       __IOM uint32_t SATCBMAX   : 12;           /*!< [27..16] Sets the number of saturation events that may occur
1415                                                      before a SATCB interrupt occurs. Once this interrupt occurs,
1416                                                      the saturation event counter must be cleared by writing
1417                                                      the SATCLR register. A value of 0 is invalid and will cause
1418                                                      the saturation interrupt to assert immediately.                           */
1419             uint32_t            : 4;
1420     } SATMAX_b;
1421   } ;
1422 
1423   union {
1424     __IOM uint32_t SATCLR;                      /*!< (@ 0x000000B0) Clears the saturation event counter registers              */
1425 
1426     struct {
1427       __IOM uint32_t SATCACLR   : 1;            /*!< [0..0] Clear saturation event counter register for channel A
1428                                                      (slots 0 or 1, depending on SATCHANSEL)                                   */
1429       __IOM uint32_t SATCBCLR   : 1;            /*!< [1..1] Clear saturation event counter register for channel B
1430                                                      (slots 2 or 3, depending on SATCHANSEL)                                   */
1431             uint32_t            : 30;
1432     } SATCLR_b;
1433   } ;
1434   __IM  uint32_t  RESERVED2[83];
1435 
1436   union {
1437     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
1438                                                                     to generate the corresponding interrupt.                   */
1439 
1440     struct {
1441       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1442       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1443       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1444       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1445       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1446       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1447       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1448       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1449       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1450       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1451       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1452       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1453             uint32_t            : 20;
1454     } INTEN_b;
1455   } ;
1456 
1457   union {
1458     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
1459                                                                     cause of a recent interrupt.                               */
1460 
1461     struct {
1462       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1463       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1464       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1465       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1466       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1467       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1468       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1469       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1470       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1471       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1472       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1473       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1474             uint32_t            : 20;
1475     } INTSTAT_b;
1476   } ;
1477 
1478   union {
1479     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
1480                                                                     the interrupt status associated with that
1481                                                                     bit.                                                       */
1482 
1483     struct {
1484       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1485       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1486       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1487       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1488       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1489       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1490       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1491       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1492       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1493       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1494       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1495       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1496             uint32_t            : 20;
1497     } INTCLR_b;
1498   } ;
1499 
1500   union {
1501     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
1502                                                                     generate an interrupt from this module.
1503                                                                     (Generally used for testing purposes).                     */
1504 
1505     struct {
1506       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1507       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1508       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1509       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1510       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1511       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1512       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1513       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1514       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1515       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1516       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1517       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1518             uint32_t            : 20;
1519     } INTSET_b;
1520   } ;
1521   __IM  uint32_t  RESERVED3[12];
1522 
1523   union {
1524     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable                                         */
1525 
1526     struct {
1527       __IOM uint32_t DFIFO75    : 1;            /*!< [0..0] Trigger DMA upon FIFO 75 percent Full                              */
1528       __IOM uint32_t DFIFOFULL  : 1;            /*!< [1..1] Trigger DMA upon FIFO 100 percent Full                             */
1529             uint32_t            : 30;
1530     } DMATRIGEN_b;
1531   } ;
1532 
1533   union {
1534     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status                                         */
1535 
1536     struct {
1537       __IOM uint32_t D75STAT    : 1;            /*!< [0..0] Triggered DMA from FIFO 75 percent Full                            */
1538       __IOM uint32_t DFULLSTAT  : 1;            /*!< [1..1] Triggered DMA from FIFO 100 percent Full                           */
1539             uint32_t            : 30;
1540     } DMATRIGSTAT_b;
1541   } ;
1542   __IM  uint32_t  RESERVED4[14];
1543 
1544   union {
1545     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration                                          */
1546 
1547     struct {
1548       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
1549             uint32_t            : 1;
1550       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
1551             uint32_t            : 5;
1552       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
1553       __IOM uint32_t DMADYNPRI  : 1;            /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
1554                                                      FIFO is full, priority is automatically set to HIGH. Otherwise,
1555                                                      DMAPRI is used.                                                           */
1556             uint32_t            : 8;
1557       __IOM uint32_t DPWROFF    : 1;            /*!< [18..18] Power Off the AUDADC System upon DMACPL.                         */
1558             uint32_t            : 13;
1559     } DMACFG_b;
1560   } ;
1561   __IM  uint32_t  RESERVED5;
1562 
1563   union {
1564     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
1565 
1566     struct {
1567             uint32_t            : 2;
1568       __IOM uint32_t TOTCOUNT   : 16;           /*!< [17..2] Total Transfer Count                                              */
1569             uint32_t            : 14;
1570     } DMATOTCOUNT_b;
1571   } ;
1572 
1573   union {
1574     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address                                         */
1575 
1576     struct {
1577       __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address                                                */
1578       __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
1579     } DMATARGADDR_b;
1580   } ;
1581 
1582   union {
1583     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status                                                 */
1584 
1585     struct {
1586       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
1587       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
1588       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
1589             uint32_t            : 29;
1590     } DMASTAT_b;
1591   } ;
1592 } AUDADC_Type;                                  /*!< Size = 660 (0x294)                                                        */
1593 
1594 
1595 
1596 /* =========================================================================================================================== */
1597 /* ================                                          CLKGEN                                           ================ */
1598 /* =========================================================================================================================== */
1599 
1600 
1601 /**
1602   * @brief Clock Generator (CLKGEN)
1603   */
1604 
1605 typedef struct {                                /*!< (@ 0x40004000) CLKGEN Structure                                           */
1606   __IM  uint32_t  RESERVED[3];
1607 
1608   union {
1609     __IOM uint32_t OCTRL;                       /*!< (@ 0x0000000C) This register includes controls for autocalibration
1610                                                                     in addition to the RTC oscillator controls.                */
1611 
1612     struct {
1613             uint32_t            : 7;
1614       __IOM uint32_t OSEL       : 1;            /*!< [7..7] Selects the RTC oscillator (1=LFRC, 0=XT)This selection
1615                                                      bit and clocking the RTC with the external crystal (XT)
1616                                                      are inoperable in silicon revisions A and B0.                             */
1617             uint32_t            : 24;
1618     } OCTRL_b;
1619   } ;
1620 
1621   union {
1622     __IOM uint32_t CLKOUT;                      /*!< (@ 0x00000010) This register enables the CLKOUT to the GPIOs,
1623                                                                     and selects the clock source to that.                      */
1624 
1625     struct {
1626       __IOM uint32_t CKSEL      : 6;            /*!< [5..0] CLKOUT signal select                                               */
1627             uint32_t            : 1;
1628       __IOM uint32_t CKEN       : 1;            /*!< [7..7] Enable the CLKOUT signal                                           */
1629             uint32_t            : 24;
1630     } CLKOUT_b;
1631   } ;
1632   __IM  uint32_t  RESERVED1[3];
1633 
1634   union {
1635     __IOM uint32_t HFADJ;                       /*!< (@ 0x00000020) This register controls the HFRC adjustment. The
1636                                                                     HFRC clock can change with temperature and
1637                                                                     process corners, and this register controls
1638                                                                     the HFRC adjustment logic which reduces
1639                                                                     the fluctuations to the clock.                             */
1640 
1641     struct {
1642       __IOM uint32_t HFADJEN    : 1;            /*!< [0..0] HFRC adjustment control                                            */
1643       __IOM uint32_t HFADJCK    : 3;            /*!< [3..1] Repeat period for HFRC adjustment                                  */
1644             uint32_t            : 4;
1645       __IOM uint32_t HFXTADJ    : 12;           /*!< [19..8] Target HFRC adjustment value.                                     */
1646       __IOM uint32_t HFWARMUP   : 1;            /*!< [20..20] XT warmup period for HFRC adjustment                             */
1647       __IOM uint32_t HFADJGAIN  : 3;            /*!< [23..21] Gain control for HFRC adjustment                                 */
1648       __IOM uint32_t HFADJMAXDELTA : 5;         /*!< [28..24] Maximum delta for HF Adjustments. 0=Disabled, 1-31=maximum
1649                                                      delta step                                                                */
1650             uint32_t            : 3;
1651     } HFADJ_b;
1652   } ;
1653   __IM  uint32_t  RESERVED2[3];
1654 
1655   union {
1656     __IOM uint32_t CLOCKENSTAT;                 /*!< (@ 0x00000030) This register provides the enable status to all
1657                                                                     the peripheral clocks.                                     */
1658 
1659     struct {
1660       __IOM uint32_t CLOCKENSTAT : 32;          /*!< [31..0] Clock enable status                                               */
1661     } CLOCKENSTAT_b;
1662   } ;
1663 
1664   union {
1665     __IOM uint32_t CLOCKEN2STAT;                /*!< (@ 0x00000034) This is a continuation of the clock enable status.         */
1666 
1667     struct {
1668       __IOM uint32_t CLOCKEN2STAT : 32;         /*!< [31..0] Clock enable status 2                                             */
1669     } CLOCKEN2STAT_b;
1670   } ;
1671 
1672   union {
1673     __IOM uint32_t CLOCKEN3STAT;                /*!< (@ 0x00000038) This is a continuation of the clock enable status.         */
1674 
1675     struct {
1676       __IOM uint32_t CLOCKEN3STAT : 32;         /*!< [31..0] Clock enable status 3                                             */
1677     } CLOCKEN3STAT_b;
1678   } ;
1679   __IM  uint32_t  RESERVED3[2];
1680 
1681   union {
1682     __IOM uint32_t MISC;                        /*!< (@ 0x00000044) This register controls a 'safe' mode for burst,
1683                                                                     which disables the clock when burst transition
1684                                                                     is happening. It also includes a register
1685                                                                     to force the HFRC during deep sleep. It
1686                                                                     is mainly used for debug and testing.                      */
1687 
1688     struct {
1689       __IOM uint32_t FRCHFRC    : 1;            /*!< [0..0] Force HFRC On .                                                    */
1690             uint32_t            : 2;
1691       __IOM uint32_t USEHFRC2FQ96MHZ : 1;       /*!< [3..3] Use HFRC-96MHz or HFRC2-96MHz for DSP                              */
1692       __IOM uint32_t USEHFRC2FQ192MHZ : 1;      /*!< [4..4] Use HFRC-192MHz or HFRC2-192MHz for MCU                            */
1693       __IOM uint32_t FRCHFRC2   : 1;            /*!< [5..5] Force HFRC2 On.Setting this bit forces HFRC2 to remain
1694                                                      on, including in deep sleep. When changing a module's clock
1695                                                      source to HFRC2, this bit must be set and remain set when
1696                                                      any module is using HFRC2 as its clock.                                   */
1697       __IOM uint32_t PWRONCLKENDISP : 1;        /*!< [6..6] For Apollo4 revB, disables display clock enable during
1698                                                      reset basically reverting to revA behavior.                               */
1699             uint32_t            : 11;
1700       __IOM uint32_t CLKGENMISCSPARES : 8;      /*!< [25..18] This field is used for the clock gating workaround.              */
1701             uint32_t            : 6;
1702     } MISC_b;
1703   } ;
1704 
1705   union {
1706     __IOM uint32_t HF2ADJ0;                     /*!< (@ 0x00000048) This register controls hf2adj enable, fast_start
1707                                                                     enable, fast_start_delay setting and counter
1708                                                                     input offset.                                              */
1709 
1710     struct {
1711       __IOM uint32_t HF2ADJEN   : 1;            /*!< [0..0] HF2ADJ control                                                     */
1712       __IOM uint32_t HF2ADJFASTSTREN : 1;       /*!< [1..1] Fast_start_delay control                                           */
1713       __IOM uint32_t HF2ADJFASTSTRDLY : 13;     /*!< [14..2] Fast_start_delay value setting                                    */
1714       __IOM uint32_t HF2ADJCNTINOFFSET : 14;    /*!< [28..15] Counter input offset                                             */
1715       __IOM uint32_t HF2ADJXTHSMUXSEL : 1;      /*!< [29..29] 0=XTHS 1=EXTREF select                                           */
1716             uint32_t            : 2;
1717     } HF2ADJ0_b;
1718   } ;
1719 
1720   union {
1721     __IOM uint32_t HF2ADJ1;                     /*!< (@ 0x0000004C) This register controls hf2adj trimming enable
1722                                                                     and trimming offset.                                       */
1723 
1724     struct {
1725       __IOM uint32_t HF2ADJTRIMEN : 3;          /*!< [2..0] HF2ADJ output selection                                            */
1726       __IOM uint32_t HF2ADJTRIMOFFSET : 11;     /*!< [13..3] HF2ADJ trimming offset. (signed number)                           */
1727             uint32_t            : 18;
1728     } HF2ADJ1_b;
1729   } ;
1730 
1731   union {
1732     __IOM uint32_t HF2ADJ2;                     /*!< (@ 0x00000050) This register controls xtal32m divider ratio
1733                                                                     and HF2ADJ ration setting.                                 */
1734 
1735     struct {
1736       __IOM uint32_t HF2ADJXTALDIVRATIO : 2;    /*!< [1..0] XTAL32MHz divider ratio for HF2ADJ.                                */
1737       __IOM uint32_t HF2ADJRATIO : 29;          /*!< [30..2] HF2ADJ ratio setting.                                             */
1738             uint32_t            : 1;
1739     } HF2ADJ2_b;
1740   } ;
1741 
1742   union {
1743     __IOM uint32_t HF2VAL;                      /*!< (@ 0x00000054) This register provides the read back of the HF2TUNE        */
1744 
1745     struct {
1746       __IOM uint32_t HF2ADJTRIMOUT : 11;        /*!< [10..0] HF2ADJ trimming output                                            */
1747             uint32_t            : 21;
1748     } HF2VAL_b;
1749   } ;
1750   __IM  uint32_t  RESERVED4[8];
1751 
1752   union {
1753     __IOM uint32_t LFRCCTRL;                    /*!< (@ 0x00000078) LFRC control                                               */
1754 
1755     struct {
1756       __IOM uint32_t LFRCOUT    : 1;            /*!< [0..0] Disable LFRC output                                                */
1757       __IOM uint32_t LFRCPWD    : 1;            /*!< [1..1] Power down LFRC                                                    */
1758             uint32_t            : 30;
1759     } LFRCCTRL_b;
1760   } ;
1761   __IM  uint32_t  RESERVED5[2];
1762 
1763   union {
1764     __IOM uint32_t DISPCLKCTRL;                 /*!< (@ 0x00000084) Provides ability to select the PLL reference
1765                                                                     clock, and derivative of the display clock                 */
1766 
1767     struct {
1768       __IOM uint32_t PLLCLKSEL  : 2;            /*!< [1..0] Selection for PLL reference clock.                                 */
1769             uint32_t            : 1;
1770       __IOM uint32_t PLLCLKEN   : 1;            /*!< [3..3] Enable for the PLL clock through clkgen                            */
1771       __IOM uint32_t DISPCLKSEL : 2;            /*!< [5..4] Selection for PLL reference clock.                                 */
1772             uint32_t            : 1;
1773       __IOM uint32_t DCCLKEN    : 1;            /*!< [7..7] Enable for the PLL clock through clkgen                            */
1774             uint32_t            : 24;
1775     } DISPCLKCTRL_b;
1776   } ;
1777 } CLKGEN_Type;                                  /*!< Size = 136 (0x88)                                                         */
1778 
1779 
1780 
1781 /* =========================================================================================================================== */
1782 /* ================                                            CPU                                            ================ */
1783 /* =========================================================================================================================== */
1784 
1785 
1786 /**
1787   * @brief CM4 Complex Registers (Cache, TCM, DAXI) (CPU)
1788   */
1789 
1790 typedef struct {                                /*!< (@ 0x48000000) CPU Structure                                              */
1791 
1792   union {
1793     __IOM uint32_t CACHECFG;                    /*!< (@ 0x00000000) CM4 Cache Control                                          */
1794 
1795     struct {
1796       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Enables the CM4 cache controller and enables power to
1797                                                      the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should
1798                                                      be set to enable caching for each type of access.                         */
1799       __IOM uint32_t LRU        : 1;            /*!< [1..1] Sets the cache repleacment policy. 0=LRR (least recently
1800                                                      replaced), 1=LRU (least recently used). LRR minimizes writes
1801                                                      to the TAG SRAM.                                                          */
1802       __IOM uint32_t NC0ENABLE  : 1;            /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to
1803                                                      define the region.                                                        */
1804       __IOM uint32_t NC1ENABLE  : 1;            /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to
1805                                                      define the region.                                                        */
1806       __IOM uint32_t CONFIG     : 4;            /*!< [7..4] Sets the cache configuration                                       */
1807       __IOM uint32_t IENABLE    : 1;            /*!< [8..8] Enable CM4 Instruction Caching                                     */
1808       __IOM uint32_t DENABLE    : 1;            /*!< [9..9] Enable CM4 Data Caching.                                           */
1809       __IOM uint32_t CLKGATE    : 1;            /*!< [10..10] Enable clock gating of cache TAG RAM. Software should
1810                                                      enable this bit for optimal power efficiency.                             */
1811       __IOM uint32_t LS         : 1;            /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should
1812                                                      DISABLE this bit since cache activity is too high to benefit
1813                                                      from LS usage.                                                            */
1814       __IOM uint32_t NC1CACHELOCK : 1;          /*!< [12..12] Only valid when Cache Mode D is set. When high sets
1815                                                      the mode of the the NC1 region such that all accesse to
1816                                                      this region are cached in to the upper half of the cache.
1817                                                      When set low then NCR1 is non cacheable.                                  */
1818       __IOM uint32_t NC0CACHELOCK : 1;          /*!< [13..13] Only valid when Cache Mode D is set. When high sets
1819                                                      the mode of the the NC0 region such that all accesse to
1820                                                      this region are cached in to the lower half of the cache.
1821                                                      When set low then NCR0 is non cacheable.                                  */
1822             uint32_t            : 6;
1823       __IOM uint32_t DATACLKGATE : 1;           /*!< [20..20] Enable aggressive clock gating of entire data array.
1824                                                      This bit should be set to 1 for optimal power efficiency.                 */
1825             uint32_t            : 3;
1826       __IOM uint32_t ENABLEMONITOR : 1;         /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes
1827                                                      additional power and should only be enabled when profiling
1828                                                      code and counters will increment when this bit is set.
1829                                                      Counter values will be retained when this is set to 0,
1830                                                      allowing software to enable/disable counting for multiple
1831                                                      code segments.                                                            */
1832             uint32_t            : 7;
1833     } CACHECFG_b;
1834   } ;
1835   __IM  uint32_t  RESERVED;
1836 
1837   union {
1838     __IOM uint32_t CACHECTRL;                   /*!< (@ 0x00000008) Cache Control                                              */
1839 
1840     struct {
1841       __IOM uint32_t INVALIDATE : 1;            /*!< [0..0] Writing a 1 to this bitfield invalidates the CM4 cache
1842                                                      contents.                                                                 */
1843       __IOM uint32_t RESETSTAT  : 1;            /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache
1844                                                      monitor counters will be cleared. The monitor counters
1845                                                      can be reset only when the CACHECFG.ENABLE_MONITOR bit
1846                                                      is set.                                                                   */
1847       __IOM uint32_t CACHEREADY : 1;            /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate
1848                                                      operation)                                                                */
1849             uint32_t            : 29;
1850     } CACHECTRL_b;
1851   } ;
1852   __IM  uint32_t  RESERVED1;
1853 
1854   union {
1855     __IOM uint32_t NCR0START;                   /*!< (@ 0x00000010) CM4 Cache Noncachable Region 0 Start                       */
1856 
1857     struct {
1858             uint32_t            : 4;
1859       __IOM uint32_t ADDR       : 25;           /*!< [28..4] Start address for non-cacheable region 0                          */
1860             uint32_t            : 3;
1861     } NCR0START_b;
1862   } ;
1863 
1864   union {
1865     __IOM uint32_t NCR0END;                     /*!< (@ 0x00000014) CM4 Cache Noncachable Region 0 End                         */
1866 
1867     struct {
1868             uint32_t            : 4;
1869       __IOM uint32_t ADDR       : 25;           /*!< [28..4] End address for non-cacheable region 0                            */
1870             uint32_t            : 3;
1871     } NCR0END_b;
1872   } ;
1873 
1874   union {
1875     __IOM uint32_t NCR1START;                   /*!< (@ 0x00000018) CM4 Cache Noncachable Region 1 Start                       */
1876 
1877     struct {
1878             uint32_t            : 4;
1879       __IOM uint32_t ADDR       : 25;           /*!< [28..4] Start address for non-cacheable region 1                          */
1880             uint32_t            : 3;
1881     } NCR1START_b;
1882   } ;
1883 
1884   union {
1885     __IOM uint32_t NCR1END;                     /*!< (@ 0x0000001C) CM4 Cache Noncachable Region 1 End                         */
1886 
1887     struct {
1888             uint32_t            : 4;
1889       __IOM uint32_t ADDR       : 25;           /*!< [28..4] End address for non-cacheable region 1                            */
1890             uint32_t            : 3;
1891     } NCR1END_b;
1892   } ;
1893   __IM  uint32_t  RESERVED2[12];
1894 
1895   union {
1896     __IOM uint32_t DAXICFG;                     /*!< (@ 0x00000050) DAXI Config                                                */
1897 
1898     struct {
1899       __IOM uint32_t FLUSHLEVEL : 1;            /*!< [0..0] When set to 0 and 3 or 4 buffers are enabled, the DAXI
1900                                                      will attempt to maintain two free buffers. When set to
1901                                                      1 and 3 or 4 buffers are enabled, the DAXI will attempt
1902                                                      to maintain three free buffers. When set to 0 and 2 buffers
1903                                                      are enabled, the DAXI will attempt to maintain one free
1904                                                      buffer. When set to 1 and 2 buffers are enabled, the DAXI
1905                                                      will attempt to maintain two free buffers. Not applicable
1906                                                      when only 1 buffer is enabled.                                            */
1907             uint32_t            : 7;
1908       __IOM uint32_t BUFFERENABLE : 2;          /*!< [9..8] Enables DAXI buffers                                               */
1909             uint32_t            : 6;
1910       __IOM uint32_t AGINGCOUNTER : 8;          /*!< [23..16] Specifies the relative time that DAXI buffers may remain
1911                                                      unused before being flushed. Counter is based on CPU clock
1912                                                      cycles and buffers will generally be flushed in 1-2 AGINGCOUNTER
1913                                                      timesteps.                                                                */
1914             uint32_t            : 8;
1915     } DAXICFG_b;
1916   } ;
1917 
1918   union {
1919     __IOM uint32_t DAXICTRL;                    /*!< (@ 0x00000054) DAXI Control                                               */
1920 
1921     struct {
1922       __IOM uint32_t DAXIFLUSHWRITE : 1;        /*!< [0..0] Writing a 1 to this bitfield forces a flush of WRITE
1923                                                      or MODIFIED buffers                                                       */
1924       __IOM uint32_t DAXIINVALIDATE : 1;        /*!< [1..1] Writing a 1 to this bitfield invalidates any SHARED data
1925                                                      buffers                                                                   */
1926             uint32_t            : 30;
1927     } DAXICTRL_b;
1928   } ;
1929   __IM  uint32_t  RESERVED3[10];
1930 
1931   union {
1932     __IOM uint32_t ICODEFAULTADDR;              /*!< (@ 0x00000080) ICODE bus address which was present when a bus
1933                                                                     fault occurred.                                            */
1934 
1935     struct {
1936       __IOM uint32_t ICODEFAULTADDR : 32;       /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred.
1937                                                      Once an address is captured in this field, it is held until
1938                                                      the corresponding Fault Observed bit is cleared in the
1939                                                      FAULTSTATUS register.                                                     */
1940     } ICODEFAULTADDR_b;
1941   } ;
1942 
1943   union {
1944     __IOM uint32_t DCODEFAULTADDR;              /*!< (@ 0x00000084) DCODE bus address which was present when a bus
1945                                                                     fault occurred.                                            */
1946 
1947     struct {
1948       __IOM uint32_t DCODEFAULTADDR : 32;       /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred.
1949                                                      Once an address is captured in this field, it is held until
1950                                                      the corresponding Fault Observed bit is cleared in the
1951                                                      FAULTSTATUS register.                                                     */
1952     } DCODEFAULTADDR_b;
1953   } ;
1954 
1955   union {
1956     __IOM uint32_t SYSFAULTADDR;                /*!< (@ 0x00000088) System bus address which was present when a bus
1957                                                                     fault occurred.                                            */
1958 
1959     struct {
1960       __IOM uint32_t SYSFAULTADDR : 32;         /*!< [31..0] SYS bus address observed when a Bus Fault occurred.
1961                                                      Once an address is captured in this field, it is held until
1962                                                      the corresponding Fault Observed bit is cleared in the
1963                                                      FAULTSTATUS register.                                                     */
1964     } SYSFAULTADDR_b;
1965   } ;
1966 
1967   union {
1968     __IOM uint32_t FAULTSTATUS;                 /*!< (@ 0x0000008C) Reflects the status of the bus decoders' fault
1969                                                                     detection. Any write to this register will
1970                                                                     clear all of the status bits within the
1971                                                                     register.                                                  */
1972 
1973     struct {
1974       __IOM uint32_t ICODEFAULT : 1;            /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a
1975                                                      fault has been detected, and the ICODEFAULTADDR register
1976                                                      will contain the bus address which generated the fault.                   */
1977       __IOM uint32_t DCODEFAULT : 1;            /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault
1978                                                      has been detected, and the DCODEFAULTADDR register will
1979                                                      contain the bus address which generated the fault.                        */
1980       __IOM uint32_t SYSFAULT   : 1;            /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault
1981                                                      has been detected, and the SYSFAULTADDR register will contain
1982                                                      the bus address which generated the fault.                                */
1983             uint32_t            : 29;
1984     } FAULTSTATUS_b;
1985   } ;
1986 
1987   union {
1988     __IOM uint32_t FAULTCAPTUREEN;              /*!< (@ 0x00000090) Enable the fault capture registers                         */
1989 
1990     struct {
1991       __IOM uint32_t FAULTCAPTUREEN : 1;        /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture
1992                                                      monitors are enabled and addresses which generate a hard
1993                                                      fault are captured into the FAULTADDR registers.                          */
1994             uint32_t            : 31;
1995     } FAULTCAPTUREEN_b;
1996   } ;
1997   __IM  uint32_t  RESERVED4[11];
1998 
1999   union {
2000     __IOM uint32_t INTEN;                       /*!< (@ 0x000000C0) Set bits in this register to allow this module
2001                                                                     to generate the corresponding interrupt.                   */
2002 
2003     struct {
2004       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2005             uint32_t            : 31;
2006     } INTEN_b;
2007   } ;
2008 
2009   union {
2010     __IOM uint32_t INTSTAT;                     /*!< (@ 0x000000C4) Read bits from this register to discover the
2011                                                                     cause of a recent interrupt.                               */
2012 
2013     struct {
2014       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2015             uint32_t            : 31;
2016     } INTSTAT_b;
2017   } ;
2018 
2019   union {
2020     __IOM uint32_t INTCLR;                      /*!< (@ 0x000000C8) Write a 1 to a bit in this register to clear
2021                                                                     the interrupt status associated with that
2022                                                                     bit.                                                       */
2023 
2024     struct {
2025       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2026             uint32_t            : 31;
2027     } INTCLR_b;
2028   } ;
2029 
2030   union {
2031     __IOM uint32_t INTSET;                      /*!< (@ 0x000000CC) Write a 1 to a bit in this register to instantly
2032                                                                     generate an interrupt from this module.
2033                                                                     (Generally used for testing purposes).                     */
2034 
2035     struct {
2036       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2037             uint32_t            : 31;
2038     } INTSET_b;
2039   } ;
2040 
2041   union {
2042     __IOM uint32_t WRITEERRADDR;                /*!< (@ 0x000000D0) DAXI Write Error Address                                   */
2043 
2044     struct {
2045       __IOM uint32_t WERRADDR   : 32;           /*!< [31..0] This address will be approximate since multiple write
2046                                                      transactions might be in flight at any given time. However,
2047                                                      it should be accurate when debugging/single-stepping                      */
2048     } WRITEERRADDR_b;
2049   } ;
2050   __IM  uint32_t  RESERVED5[11];
2051 
2052   union {
2053     __IOM uint32_t DMON0;                       /*!< (@ 0x00000100) Data Cache Total Accesses                                  */
2054 
2055     struct {
2056       __IOM uint32_t DACCESS    : 32;           /*!< [31..0] Total accesses to data cache. All performance metrics
2057                                                      should be relative to the number of accesses performed.                   */
2058     } DMON0_b;
2059   } ;
2060 
2061   union {
2062     __IOM uint32_t DMON1;                       /*!< (@ 0x00000104) Data Cache Tag Lookups                                     */
2063 
2064     struct {
2065       __IOM uint32_t DLOOKUP    : 32;           /*!< [31..0] Total tag lookups from data cache.                                */
2066     } DMON1_b;
2067   } ;
2068 
2069   union {
2070     __IOM uint32_t DMON2;                       /*!< (@ 0x00000108) Data Cache Hits                                            */
2071 
2072     struct {
2073       __IOM uint32_t DHIT       : 32;           /*!< [31..0] Cache hits from lookup operations.                                */
2074     } DMON2_b;
2075   } ;
2076 
2077   union {
2078     __IOM uint32_t DMON3;                       /*!< (@ 0x0000010C) Data Cache Line Hits                                       */
2079 
2080     struct {
2081       __IOM uint32_t DLINE      : 32;           /*!< [31..0] Cache hits from line cache                                        */
2082     } DMON3_b;
2083   } ;
2084 
2085   union {
2086     __IOM uint32_t IMON0;                       /*!< (@ 0x00000110) Instruction Cache Total Accesses                           */
2087 
2088     struct {
2089       __IOM uint32_t IACCESS    : 32;           /*!< [31..0] Total accesses to Instruction cache                               */
2090     } IMON0_b;
2091   } ;
2092 
2093   union {
2094     __IOM uint32_t IMON1;                       /*!< (@ 0x00000114) Instruction Cache Tag Lookups                              */
2095 
2096     struct {
2097       __IOM uint32_t ILOOKUP    : 32;           /*!< [31..0] Total tag lookups from Instruction cache                          */
2098     } IMON1_b;
2099   } ;
2100 
2101   union {
2102     __IOM uint32_t IMON2;                       /*!< (@ 0x00000118) Instruction Cache Hits                                     */
2103 
2104     struct {
2105       __IOM uint32_t IHIT       : 32;           /*!< [31..0] Cache hits from lookup operations                                 */
2106     } IMON2_b;
2107   } ;
2108 
2109   union {
2110     __IOM uint32_t IMON3;                       /*!< (@ 0x0000011C) Instruction Cache Line Hits                                */
2111 
2112     struct {
2113       __IOM uint32_t ILINE      : 32;           /*!< [31..0] Cache hits from line cache                                        */
2114     } IMON3_b;
2115   } ;
2116 } CPU_Type;                                     /*!< Size = 288 (0x120)                                                        */
2117 
2118 
2119 
2120 /* =========================================================================================================================== */
2121 /* ================                                          CRYPTO                                           ================ */
2122 /* =========================================================================================================================== */
2123 
2124 
2125 /**
2126   * @brief Embedded security and cryptographic services (CRYPTO)
2127   */
2128 
2129 typedef struct {                                /*!< (@ 0x400C0000) CRYPTO Structure                                           */
2130 
2131   union {
2132     __IOM uint32_t MEMORYMAP0;                  /*!< (@ 0x00000000) This register maps the virtual register R0 to
2133                                                                     a physical address in memory.                              */
2134 
2135     struct {
2136             uint32_t            : 1;
2137       __IOM uint32_t PHYSADDRMAP0 : 10;         /*!< [10..1] Contains the physical address in memory to map the R0
2138                                                      register.                                                                 */
2139             uint32_t            : 21;
2140     } MEMORYMAP0_b;
2141   } ;
2142 
2143   union {
2144     __IOM uint32_t MEMORYMAP1;                  /*!< (@ 0x00000004) This register maps the virtual register R1 to
2145                                                                     a physical address in memory.                              */
2146 
2147     struct {
2148             uint32_t            : 1;
2149       __IOM uint32_t PHYSADDRMAP1 : 10;         /*!< [10..1] Contains the physical address in memory to map the R1
2150                                                      register.                                                                 */
2151             uint32_t            : 21;
2152     } MEMORYMAP1_b;
2153   } ;
2154 
2155   union {
2156     __IOM uint32_t MEMORYMAP2;                  /*!< (@ 0x00000008) This register maps the virtual register R2 to
2157                                                                     a physical address in memory.                              */
2158 
2159     struct {
2160             uint32_t            : 1;
2161       __IOM uint32_t PHYSADDRMAP2 : 10;         /*!< [10..1] Contains the physical address in memory to map the R2
2162                                                      register.                                                                 */
2163             uint32_t            : 21;
2164     } MEMORYMAP2_b;
2165   } ;
2166 
2167   union {
2168     __IOM uint32_t MEMORYMAP3;                  /*!< (@ 0x0000000C) This register maps the virtual register R3 to
2169                                                                     a physical address in memory.                              */
2170 
2171     struct {
2172             uint32_t            : 1;
2173       __IOM uint32_t PHYSADDRMAP3 : 10;         /*!< [10..1] Contains the physical address in memory to map the R3
2174                                                      register.                                                                 */
2175             uint32_t            : 21;
2176     } MEMORYMAP3_b;
2177   } ;
2178 
2179   union {
2180     __IOM uint32_t MEMORYMAP4;                  /*!< (@ 0x00000010) This register maps the virtual register R4 to
2181                                                                     a physical address in memory.                              */
2182 
2183     struct {
2184             uint32_t            : 1;
2185       __IOM uint32_t PHYSADDRMAP4 : 10;         /*!< [10..1] Contains the physical address in memory to map the R4
2186                                                      register.                                                                 */
2187             uint32_t            : 21;
2188     } MEMORYMAP4_b;
2189   } ;
2190 
2191   union {
2192     __IOM uint32_t MEMORYMAP5;                  /*!< (@ 0x00000014) This register maps the virtual register R5 to
2193                                                                     a physical address in memory.                              */
2194 
2195     struct {
2196             uint32_t            : 1;
2197       __IOM uint32_t PHYSADDRMAP5 : 10;         /*!< [10..1] Contains the physical address in memory to map the R5
2198                                                      register.                                                                 */
2199             uint32_t            : 21;
2200     } MEMORYMAP5_b;
2201   } ;
2202 
2203   union {
2204     __IOM uint32_t MEMORYMAP6;                  /*!< (@ 0x00000018) This register maps the virtual register R6 to
2205                                                                     a physical address in memory.                              */
2206 
2207     struct {
2208             uint32_t            : 1;
2209       __IOM uint32_t PHYSADDRMAP6 : 10;         /*!< [10..1] Contains the physical address in memory to map the R6
2210                                                      register.                                                                 */
2211             uint32_t            : 21;
2212     } MEMORYMAP6_b;
2213   } ;
2214 
2215   union {
2216     __IOM uint32_t MEMORYMAP7;                  /*!< (@ 0x0000001C) This register maps the virtual register R7 to
2217                                                                     a physical address in memory.                              */
2218 
2219     struct {
2220             uint32_t            : 1;
2221       __IOM uint32_t PHYSADDRMAP7 : 10;         /*!< [10..1] Contains the physical address in memory to map the R7
2222                                                      register.                                                                 */
2223             uint32_t            : 21;
2224     } MEMORYMAP7_b;
2225   } ;
2226 
2227   union {
2228     __IOM uint32_t MEMORYMAP8;                  /*!< (@ 0x00000020) This register maps the virtual register R8 to
2229                                                                     a physical address in memory.                              */
2230 
2231     struct {
2232             uint32_t            : 1;
2233       __IOM uint32_t PHYSADDRMAP8 : 10;         /*!< [10..1] Contains the physical address in memory to map the R8
2234                                                      register.                                                                 */
2235             uint32_t            : 21;
2236     } MEMORYMAP8_b;
2237   } ;
2238 
2239   union {
2240     __IOM uint32_t MEMORYMAP9;                  /*!< (@ 0x00000024) This register maps the virtual register R9 to
2241                                                                     a physical address in memory.                              */
2242 
2243     struct {
2244             uint32_t            : 1;
2245       __IOM uint32_t PHYSADDRMAP9 : 10;         /*!< [10..1] Contains the physical address in memory to map the R9
2246                                                      register.                                                                 */
2247             uint32_t            : 21;
2248     } MEMORYMAP9_b;
2249   } ;
2250 
2251   union {
2252     __IOM uint32_t MEMORYMAP10;                 /*!< (@ 0x00000028) This register maps the virtual register R10 to
2253                                                                     a physical address in memory.                              */
2254 
2255     struct {
2256             uint32_t            : 1;
2257       __IOM uint32_t PHYSADDRMAP10 : 10;        /*!< [10..1] Contains the physical address in memory to map the R10
2258                                                      register.                                                                 */
2259             uint32_t            : 21;
2260     } MEMORYMAP10_b;
2261   } ;
2262 
2263   union {
2264     __IOM uint32_t MEMORYMAP11;                 /*!< (@ 0x0000002C) This register maps the virtual register R11 to
2265                                                                     a physical address in memory.                              */
2266 
2267     struct {
2268             uint32_t            : 1;
2269       __IOM uint32_t PHYSADDRMAP11 : 10;        /*!< [10..1] Contains the physical address in memory to map the R11
2270                                                      register.                                                                 */
2271             uint32_t            : 21;
2272     } MEMORYMAP11_b;
2273   } ;
2274 
2275   union {
2276     __IOM uint32_t MEMORYMAP12;                 /*!< (@ 0x00000030) This register maps the virtual register R12 to
2277                                                                     a physical address in memory.                              */
2278 
2279     struct {
2280             uint32_t            : 1;
2281       __IOM uint32_t PHYSADDRMAP12 : 10;        /*!< [10..1] Contains the physical address in memory to map the R12
2282                                                      register.                                                                 */
2283             uint32_t            : 21;
2284     } MEMORYMAP12_b;
2285   } ;
2286 
2287   union {
2288     __IOM uint32_t MEMORYMAP13;                 /*!< (@ 0x00000034) This register maps the virtual register R13 to
2289                                                                     a physical address in memory.                              */
2290 
2291     struct {
2292             uint32_t            : 1;
2293       __IOM uint32_t PHYSADDRMAP13 : 10;        /*!< [10..1] Contains the physical address in memory to map the R13
2294                                                      register.                                                                 */
2295             uint32_t            : 21;
2296     } MEMORYMAP13_b;
2297   } ;
2298 
2299   union {
2300     __IOM uint32_t MEMORYMAP14;                 /*!< (@ 0x00000038) This register maps the virtual register R14 to
2301                                                                     a physical address in memory.                              */
2302 
2303     struct {
2304             uint32_t            : 1;
2305       __IOM uint32_t PHYSADDRMAP14 : 10;        /*!< [10..1] Contains the physical address in memory to map the R14
2306                                                      register.                                                                 */
2307             uint32_t            : 21;
2308     } MEMORYMAP14_b;
2309   } ;
2310 
2311   union {
2312     __IOM uint32_t MEMORYMAP15;                 /*!< (@ 0x0000003C) This register maps the virtual register R15 to
2313                                                                     a physical address in memory.                              */
2314 
2315     struct {
2316             uint32_t            : 1;
2317       __IOM uint32_t PHYSADDRMAP15 : 10;        /*!< [10..1] Contains the physical address in memory to map the R15
2318                                                      registero.                                                                */
2319             uint32_t            : 21;
2320     } MEMORYMAP15_b;
2321   } ;
2322 
2323   union {
2324     __IOM uint32_t MEMORYMAP16;                 /*!< (@ 0x00000040) This register maps the virtual register R16 to
2325                                                                     a physical address in memory.                              */
2326 
2327     struct {
2328             uint32_t            : 1;
2329       __IOM uint32_t PHYSADDRMAP16 : 10;        /*!< [10..1] Contains the physical address in memory to map the R16
2330                                                      register.                                                                 */
2331             uint32_t            : 21;
2332     } MEMORYMAP16_b;
2333   } ;
2334 
2335   union {
2336     __IOM uint32_t MEMORYMAP17;                 /*!< (@ 0x00000044) This register maps the virtual register R17 to
2337                                                                     a physical address in memory.                              */
2338 
2339     struct {
2340             uint32_t            : 1;
2341       __IOM uint32_t PHYSADDRMAP17 : 10;        /*!< [10..1] Contains the physical address in memory to map the R17
2342                                                      registero.                                                                */
2343             uint32_t            : 21;
2344     } MEMORYMAP17_b;
2345   } ;
2346 
2347   union {
2348     __IOM uint32_t MEMORYMAP18;                 /*!< (@ 0x00000048) This register maps the virtual register R18 to
2349                                                                     a physical address in memory.                              */
2350 
2351     struct {
2352             uint32_t            : 1;
2353       __IOM uint32_t PHYSADDRMAP18 : 10;        /*!< [10..1] Contains the physical address in memory to map the R18
2354                                                      register.                                                                 */
2355             uint32_t            : 21;
2356     } MEMORYMAP18_b;
2357   } ;
2358 
2359   union {
2360     __IOM uint32_t MEMORYMAP19;                 /*!< (@ 0x0000004C) This register maps the virtual register R19 to
2361                                                                     a physical address in memory.                              */
2362 
2363     struct {
2364             uint32_t            : 1;
2365       __IOM uint32_t PHYSADDRMAP19 : 10;        /*!< [10..1] Contains the physical address in memory to map the R19
2366                                                      register to.                                                              */
2367             uint32_t            : 21;
2368     } MEMORYMAP19_b;
2369   } ;
2370 
2371   union {
2372     __IOM uint32_t MEMORYMAP20;                 /*!< (@ 0x00000050) This register maps the virtual register R20 to
2373                                                                     a physical address in memory.                              */
2374 
2375     struct {
2376             uint32_t            : 1;
2377       __IOM uint32_t PHYSADDRMAP20 : 10;        /*!< [10..1] Contains the physical address in memory to map the R20
2378                                                      register to.                                                              */
2379             uint32_t            : 21;
2380     } MEMORYMAP20_b;
2381   } ;
2382 
2383   union {
2384     __IOM uint32_t MEMORYMAP21;                 /*!< (@ 0x00000054) This register maps the virtual register R21 to
2385                                                                     a physical address in memory.                              */
2386 
2387     struct {
2388             uint32_t            : 1;
2389       __IOM uint32_t PHYSADDRMAP21 : 10;        /*!< [10..1] Contains the physical address in memory to map the R21
2390                                                      register to.                                                              */
2391             uint32_t            : 21;
2392     } MEMORYMAP21_b;
2393   } ;
2394 
2395   union {
2396     __IOM uint32_t MEMORYMAP22;                 /*!< (@ 0x00000058) This register maps the virtual register R22 to
2397                                                                     a physical address in memory.                              */
2398 
2399     struct {
2400             uint32_t            : 1;
2401       __IOM uint32_t PHYSADDRMAP22 : 10;        /*!< [10..1] Contains the physical address in memory to map the R22
2402                                                      register to.                                                              */
2403             uint32_t            : 21;
2404     } MEMORYMAP22_b;
2405   } ;
2406 
2407   union {
2408     __IOM uint32_t MEMORYMAP23;                 /*!< (@ 0x0000005C) This register maps the virtual register R23 to
2409                                                                     a physical address in memory.                              */
2410 
2411     struct {
2412             uint32_t            : 1;
2413       __IOM uint32_t PHYSADDRMAP23 : 10;        /*!< [10..1] Contains the physical address in memory to map the R23
2414                                                      register to.                                                              */
2415             uint32_t            : 21;
2416     } MEMORYMAP23_b;
2417   } ;
2418 
2419   union {
2420     __IOM uint32_t MEMORYMAP24;                 /*!< (@ 0x00000060) This register maps the virtual register R24 to
2421                                                                     a physical address in memory.                              */
2422 
2423     struct {
2424             uint32_t            : 1;
2425       __IOM uint32_t PHYSADDRMAP24 : 10;        /*!< [10..1] Contains the physical address in memory to map the R24
2426                                                      register to.                                                              */
2427             uint32_t            : 21;
2428     } MEMORYMAP24_b;
2429   } ;
2430 
2431   union {
2432     __IOM uint32_t MEMORYMAP25;                 /*!< (@ 0x00000064) This register maps the virtual register R25 to
2433                                                                     a physical address in memory.                              */
2434 
2435     struct {
2436             uint32_t            : 1;
2437       __IOM uint32_t PHYSADDRMAP25 : 10;        /*!< [10..1] Contains the physical address in memory to map the R25
2438                                                      register to.                                                              */
2439             uint32_t            : 21;
2440     } MEMORYMAP25_b;
2441   } ;
2442 
2443   union {
2444     __IOM uint32_t MEMORYMAP26;                 /*!< (@ 0x00000068) This register maps the virtual register R26 to
2445                                                                     a physical address in memory.                              */
2446 
2447     struct {
2448             uint32_t            : 1;
2449       __IOM uint32_t PHYSADDRMAP26 : 10;        /*!< [10..1] Contains the physical address in memory to map the R26
2450                                                      register to.                                                              */
2451             uint32_t            : 21;
2452     } MEMORYMAP26_b;
2453   } ;
2454 
2455   union {
2456     __IOM uint32_t MEMORYMAP27;                 /*!< (@ 0x0000006C) This register maps the virtual register R27 to
2457                                                                     a physical address in memory.                              */
2458 
2459     struct {
2460             uint32_t            : 1;
2461       __IOM uint32_t PHYSADDRMAP27 : 10;        /*!< [10..1] Contains the physical address in memory to map the R27
2462                                                      register to.                                                              */
2463             uint32_t            : 21;
2464     } MEMORYMAP27_b;
2465   } ;
2466 
2467   union {
2468     __IOM uint32_t MEMORYMAP28;                 /*!< (@ 0x00000070) This register maps the virtual register R28 to
2469                                                                     a physical address in memory.                              */
2470 
2471     struct {
2472             uint32_t            : 1;
2473       __IOM uint32_t PHYSADDRMAP28 : 10;        /*!< [10..1] Contains the physical address in memory to map the R28
2474                                                      register.                                                                 */
2475             uint32_t            : 21;
2476     } MEMORYMAP28_b;
2477   } ;
2478 
2479   union {
2480     __IOM uint32_t MEMORYMAP29;                 /*!< (@ 0x00000074) This register maps the virtual register R29 to
2481                                                                     a physical address in memory.                              */
2482 
2483     struct {
2484             uint32_t            : 1;
2485       __IOM uint32_t PHYSADDRMAP29 : 10;        /*!< [10..1] Contains the physical address in memory to map the R29
2486                                                      register.                                                                 */
2487             uint32_t            : 21;
2488     } MEMORYMAP29_b;
2489   } ;
2490 
2491   union {
2492     __IOM uint32_t MEMORYMAP30;                 /*!< (@ 0x00000078) This register maps the virtual register R30 to
2493                                                                     a physical address in memory.                              */
2494 
2495     struct {
2496             uint32_t            : 1;
2497       __IOM uint32_t PHYSADDRMAP30 : 10;        /*!< [10..1] Contains the physical address in memory to map the R30
2498                                                      register.                                                                 */
2499             uint32_t            : 21;
2500     } MEMORYMAP30_b;
2501   } ;
2502 
2503   union {
2504     __IOM uint32_t MEMORYMAP31;                 /*!< (@ 0x0000007C) This register maps the virtual register R31 to
2505                                                                     a physical address in memory.                              */
2506 
2507     struct {
2508             uint32_t            : 1;
2509       __IOM uint32_t PHYSADDRMAP31 : 10;        /*!< [10..1] Contains the physical address in memory to map the R31
2510                                                      register.                                                                 */
2511             uint32_t            : 21;
2512     } MEMORYMAP31_b;
2513   } ;
2514 
2515   union {
2516     __IOM uint32_t OPCODE;                      /*!< (@ 0x00000080) This register holds the PKAs OPCODE.                       */
2517 
2518     struct {
2519       __IOM uint32_t TAG        : 6;            /*!< [5..0] Holds the operations tag or the operand C virtual address.         */
2520       __IOM uint32_t REGR       : 6;            /*!< [11..6] Result register virtual address 0-15.                             */
2521       __IOM uint32_t REGB       : 6;            /*!< [17..12] Operand B virtual address 0-15.                                  */
2522       __IOM uint32_t REGA       : 6;            /*!< [23..18] Operand A virtual address 0-15.                                  */
2523       __IOM uint32_t LEN        : 3;            /*!< [26..24] The length of the operation. The value serves as a
2524                                                      pointer to PKA length register, for example, if the value
2525                                                      is 0, PKA_L0 holds the size of the operation.                             */
2526       __IOM uint32_t OPCODE     : 5;            /*!< [31..27] Defines the PKA operation:                                       */
2527     } OPCODE_b;
2528   } ;
2529 
2530   union {
2531     __IOM uint32_t NNPT0T1ADDR;                 /*!< (@ 0x00000084) This register maps N_NP_T0_T1 to a virtual address.        */
2532 
2533     struct {
2534       __IOM uint32_t NVIRTUALADDR : 5;          /*!< [4..0] Virtual address of register N.                                     */
2535       __IOM uint32_t NPVIRTUALADDR : 5;         /*!< [9..5] Virtual address of register NP.                                    */
2536       __IOM uint32_t T0VIRTUALADDR : 5;         /*!< [14..10] Virtual address of temporary register number 0                   */
2537       __IOM uint32_t T1VIRTUALADDR : 5;         /*!< [19..15] Virtual address of temporary register number 1                   */
2538             uint32_t            : 12;
2539     } NNPT0T1ADDR_b;
2540   } ;
2541 
2542   union {
2543     __IOM uint32_t PKASTATUS;                   /*!< (@ 0x00000088) This register holds the PKA pipe status.                   */
2544 
2545     struct {
2546       __IOM uint32_t ALUMSB4BITS : 4;           /*!< [3..0] The most significant 4-bits of the operand updated in
2547                                                      shift operation.                                                          */
2548       __IOM uint32_t ALULSB4BITS : 4;           /*!< [7..4] The least significant 4-bits of the operand updated in
2549                                                      shift operation.                                                          */
2550       __IOM uint32_t ALUSIGNOUT : 1;            /*!< [8..8] Indicates the last operations sign (MSB).                          */
2551       __IOM uint32_t ALUCARRY   : 1;            /*!< [9..9] Holds the carry of the last ALU operation.                         */
2552       __IOM uint32_t ALUCARRYMOD : 1;           /*!< [10..10] holds the carry of the last Modular operation.                   */
2553       __IOM uint32_t ALUSUBISZERO : 1;          /*!< [11..11] Indicates the last subtraction operations sign .                 */
2554       __IOM uint32_t ALUOUTZERO : 1;            /*!< [12..12] Indicates if the result of ALU OUT is zero.                      */
2555       __IOM uint32_t ALUMODOVRFLW : 1;          /*!< [13..13] Modular overflow flag.                                           */
2556       __IOM uint32_t DIVBYZERO  : 1;            /*!< [14..14] Indication if the division is done by zero.                      */
2557       __IOM uint32_t MODINVOFZERO : 1;          /*!< [15..15] Indicates the Modular inverse of zero.                           */
2558       __IOM uint32_t OPCODE     : 5;            /*!< [20..16] Opcode of the last operation                                     */
2559             uint32_t            : 11;
2560     } PKASTATUS_b;
2561   } ;
2562 
2563   union {
2564     __IOM uint32_t PKASWRESET;                  /*!< (@ 0x0000008C) Writing to this register triggers a software
2565                                                                     reset of the PKA.                                          */
2566 
2567     struct {
2568       __IOM uint32_t PKASWRESET : 1;            /*!< [0..0] The reset mechanism takes about four PKA clock cycles
2569                                                      until the reset line is deasserted                                        */
2570             uint32_t            : 31;
2571     } PKASWRESET_b;
2572   } ;
2573 
2574   union {
2575     __IOM uint32_t PKAL0;                       /*!< (@ 0x00000090) This register holds one of the optional size
2576                                                                     of the operation.                                          */
2577 
2578     struct {
2579       __IOM uint32_t PKAL0      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2580             uint32_t            : 19;
2581     } PKAL0_b;
2582   } ;
2583 
2584   union {
2585     __IOM uint32_t PKAL1;                       /*!< (@ 0x00000094) This register holds one of the optional size
2586                                                                     of the operation.                                          */
2587 
2588     struct {
2589       __IOM uint32_t PKAL1      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2590             uint32_t            : 19;
2591     } PKAL1_b;
2592   } ;
2593 
2594   union {
2595     __IOM uint32_t PKAL2;                       /*!< (@ 0x00000098) This register holds one of the optional size
2596                                                                     of the operation.                                          */
2597 
2598     struct {
2599       __IOM uint32_t PKAL2      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2600             uint32_t            : 19;
2601     } PKAL2_b;
2602   } ;
2603 
2604   union {
2605     __IOM uint32_t PKAL3;                       /*!< (@ 0x0000009C) This register holds one of the optional size
2606                                                                     of the operation.                                          */
2607 
2608     struct {
2609       __IOM uint32_t PKAL3      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2610             uint32_t            : 19;
2611     } PKAL3_b;
2612   } ;
2613 
2614   union {
2615     __IOM uint32_t PKAL4;                       /*!< (@ 0x000000A0) This register holds one of the optional size
2616                                                                     of the operation.                                          */
2617 
2618     struct {
2619       __IOM uint32_t PKAL4      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2620             uint32_t            : 19;
2621     } PKAL4_b;
2622   } ;
2623 
2624   union {
2625     __IOM uint32_t PKAL5;                       /*!< (@ 0x000000A4) This register holds one of the optional size
2626                                                                     of the operation.                                          */
2627 
2628     struct {
2629       __IOM uint32_t PKAL5      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2630             uint32_t            : 19;
2631     } PKAL5_b;
2632   } ;
2633 
2634   union {
2635     __IOM uint32_t PKAL6;                       /*!< (@ 0x000000A8) This register holds one of the optional size
2636                                                                     of the operation.                                          */
2637 
2638     struct {
2639       __IOM uint32_t PKAL6      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2640             uint32_t            : 19;
2641     } PKAL6_b;
2642   } ;
2643 
2644   union {
2645     __IOM uint32_t PKAL7;                       /*!< (@ 0x000000AC) This register holds one of the optional size
2646                                                                     of the operation.                                          */
2647 
2648     struct {
2649       __IOM uint32_t PKAL7      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2650             uint32_t            : 19;
2651     } PKAL7_b;
2652   } ;
2653 
2654   union {
2655     __IOM uint32_t PKAPIPERDY;                  /*!< (@ 0x000000B0) This register indicates whether the PKA pipe
2656                                                                     is ready to receive a new OPCODE.                          */
2657 
2658     struct {
2659       __IOM uint32_t PKAPIPERDY : 1;            /*!< [0..0] Indication whether PKA pipe is ready for new OPCODE.               */
2660             uint32_t            : 31;
2661     } PKAPIPERDY_b;
2662   } ;
2663 
2664   union {
2665     __IOM uint32_t PKADONE;                     /*!< (@ 0x000000B4) This register indicates whether PKA operation
2666                                                                     is completed.                                              */
2667 
2668     struct {
2669       __IOM uint32_t PKADONE    : 1;            /*!< [0..0] Indicates if PKA operation is completed, and pipe is
2670                                                      empty.                                                                    */
2671             uint32_t            : 31;
2672     } PKADONE_b;
2673   } ;
2674 
2675   union {
2676     __IOM uint32_t PKAMONSELECT;                /*!< (@ 0x000000B8) This register defines which PKA FSM monitor is
2677                                                                     being output.                                              */
2678 
2679     struct {
2680       __IOM uint32_t PKAMONSELECT : 4;          /*!< [3..0] Defines which PKA FSM monitor is being output.                     */
2681             uint32_t            : 28;
2682     } PKAMONSELECT_b;
2683   } ;
2684   __IM  uint32_t  RESERVED[2];
2685 
2686   union {
2687     __IOM uint32_t PKAVERSION;                  /*!< (@ 0x000000C4) This register holds the pka version                        */
2688 
2689     struct {
2690       __IOM uint32_t PKAVERSION : 32;           /*!< [31..0] This is the PKA version                                           */
2691     } PKAVERSION_b;
2692   } ;
2693   __IM  uint32_t  RESERVED1[2];
2694 
2695   union {
2696     __IOM uint32_t PKAMONREAD;                  /*!< (@ 0x000000D0) The PKA monitor bus register.                              */
2697 
2698     struct {
2699       __IOM uint32_t PKAMONREAD : 32;           /*!< [31..0] This is the PKA monitor bus register output                       */
2700     } PKAMONREAD_b;
2701   } ;
2702 
2703   union {
2704     __IOM uint32_t PKASRAMADDR;                 /*!< (@ 0x000000D4) first address given to PKA SRAM for write transactions.    */
2705 
2706     struct {
2707       __IOM uint32_t PKASRAMADDR : 32;          /*!< [31..0] PKA SRAM write starting address                                   */
2708     } PKASRAMADDR_b;
2709   } ;
2710 
2711   union {
2712     __IOM uint32_t PKASRAMWDATA;                /*!< (@ 0x000000D8) Write data to PKA SRAM.                                    */
2713 
2714     struct {
2715       __IOM uint32_t PKASRAMWDATA : 32;         /*!< [31..0] 32 bit write to PKA SRAM: triggers the SRAM write DMA
2716                                                      address automatically incremented                                         */
2717     } PKASRAMWDATA_b;
2718   } ;
2719 
2720   union {
2721     __IOM uint32_t PKASRAMRDATA;                /*!< (@ 0x000000DC) Read data from PKA SRAM.                                   */
2722 
2723     struct {
2724       __IOM uint32_t PKASRAMRDATA : 32;         /*!< [31..0] 32 bit read from PKA SRAM: read - triggers the SRAM
2725                                                      read DMA address automatically incremented                                */
2726     } PKASRAMRDATA_b;
2727   } ;
2728 
2729   union {
2730     __IOM uint32_t PKASRAMWRCLR;                /*!< (@ 0x000000E0) Write buffer clean.                                        */
2731 
2732     struct {
2733       __IOM uint32_t PKASRAMWRCLR : 32;         /*!< [31..0] Clear the write buffer.                                           */
2734     } PKASRAMWRCLR_b;
2735   } ;
2736 
2737   union {
2738     __IOM uint32_t PKASRAMRADDR;                /*!< (@ 0x000000E4) first address given to PKA SRAM for read transactions.     */
2739 
2740     struct {
2741       __IOM uint32_t PKASRAMRADDR : 32;         /*!< [31..0] PKA SRAM read starting address                                    */
2742     } PKASRAMRADDR_b;
2743   } ;
2744   __IM  uint32_t  RESERVED2[2];
2745 
2746   union {
2747     __IOM uint32_t PKAWORDACCESS;               /*!< (@ 0x000000F0) This register holds the data written to PKA memory
2748                                                                     using the wop opcode.                                      */
2749 
2750     struct {
2751       __IOM uint32_t PKAWORDACCESS : 32;        /*!< [31..0] 32 bit read_write data.                                           */
2752     } PKAWORDACCESS_b;
2753   } ;
2754   __IM  uint32_t  RESERVED3;
2755 
2756   union {
2757     __IOM uint32_t PKABUFFADDR;                 /*!< (@ 0x000000F8) This register maps the virtual buffer registers
2758                                                                     to a physical address in memory.                           */
2759 
2760     struct {
2761       __IOM uint32_t PKABUFADDR : 12;           /*!< [11..0] Contains the physical address in memory to map the buffer
2762                                                      registers.                                                                */
2763             uint32_t            : 20;
2764     } PKABUFFADDR_b;
2765   } ;
2766   __IM  uint32_t  RESERVED4;
2767 
2768   union {
2769     __IOM uint32_t RNGIMR;                      /*!< (@ 0x00000100) Interrupt masking register. Consists of {prng_imr
2770                                                                     trng_imr} bit[31-16] - PRNG_IMR bit[15-0]
2771                                                                     - TRNG_IMR(Ws - PRNG bit exists only if
2772                                                                     PRNG_EXISTS flag)                                          */
2773 
2774     struct {
2775       __IOM uint32_t EHRVALIDINTMASK : 1;       /*!< [0..0] 0x1 - masks the EHR interrupt. No interrupt is generated.          */
2776       __IOM uint32_t AUTOCORRERRINTMASK : 1;    /*!< [1..1] 0x1 - masks the autocorrelation interrupt. No interrupt
2777                                                      is generated.                                                             */
2778       __IOM uint32_t CRNGTERRINTMASK : 1;       /*!< [2..2] 0x1 - masks the CRNGT error interrupt. No interrupt is
2779                                                      generated.                                                                */
2780       __IOM uint32_t VNERRINTMASK : 1;          /*!< [3..3] 0x1 - masks the Von-Neumann error interrupt. No interrupt
2781                                                      is generated.                                                             */
2782       __IOM uint32_t WATCHDOGINTMASK : 1;       /*!< [4..4] 0x1 - masks the watchdog interrupt. No interrupt is generated.     */
2783       __IOM uint32_t RNGDMADONEINT : 1;         /*!< [5..5] 0x1 - masks the RNG DMA completion interrupt. No interrupt
2784                                                      is generated.                                                             */
2785             uint32_t            : 26;
2786     } RNGIMR_b;
2787   } ;
2788 
2789   union {
2790     __IOM uint32_t RNGISR;                      /*!< (@ 0x00000104) Status register. If corresponding RNG_IMR bit
2791                                                                     is unmasked, an interrupt is generated.Consists
2792                                                                     of trng_isr and prng_isr bit[15-0] - TRNG
2793                                                                     bit[31-16] - PRNG                                          */
2794 
2795     struct {
2796       __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] 0x1 indicates that 192 bits have been collected in the
2797                                                      TRNG and are ready to be read.                                            */
2798       __IOM uint32_t AUTOCORRERR : 1;           /*!< [1..1] 0x1 indicates Autocorrelation test failed four times
2799                                                      in a row. When it set ,TRNG ceases to function until next
2800                                                      reset.                                                                    */
2801       __IOM uint32_t CRNGTERR   : 1;            /*!< [2..2] 0x1 indicates CRNGT in the TRNG test failed. Failure
2802                                                      occurs when two consecutive blocks of 16 collected bits
2803                                                      are equal.                                                                */
2804       __IOM uint32_t VNERR      : 1;            /*!< [3..3] 0x1 indicates Von Neumann error. Error in von Neumann
2805                                                      occurs if 32 consecutive collected bits are identical,
2806                                                      ZERO, or ONE.                                                             */
2807             uint32_t            : 1;
2808       __IOM uint32_t RNGDMADONE : 1;            /*!< [5..5] 0x1 indicates RNG DMA to SRAM is completed.                        */
2809             uint32_t            : 10;
2810       __IOM uint32_t RESEEDINGDONE : 1;         /*!< [16..16] 0x1 indicates completion of reseeding algorithm with
2811                                                      no errors.                                                                */
2812       __IOM uint32_t INSTANTIATIONDONE : 1;     /*!< [17..17] 0x1 indicates completion of instantiation algorithm
2813                                                      with no errors.                                                           */
2814       __IOM uint32_t FINALUPDATEDONE : 1;       /*!< [18..18] 0x1 indicates completion of final update algorithm.              */
2815       __IOM uint32_t OUTPUTREADY : 1;           /*!< [19..19] 0x1 indicates that the result of PRNG is valid and
2816                                                      ready to be read. The result can be read from the RNG_READOUT
2817                                                      register.                                                                 */
2818       __IOM uint32_t RESEEDCNTRFULL : 1;        /*!< [20..20] 0x1 indicates that the reseed counter has reached 2^48,
2819                                                      requiring to run the reseed algorithm before generating
2820                                                      new random numbers.                                                       */
2821       __IOM uint32_t RESEEDCNTRTOP40 : 1;       /*!< [21..21] 0x1 indicates that the top 40 bits of the reseed counter
2822                                                      are set (that is the reseed counter is larger than 2^48-2^8).
2823                                                      This is a recommendation for running the reseed algorithm
2824                                                      before the counter reaches its max value.                                 */
2825       __IOM uint32_t PRNGCRNGTERR : 1;          /*!< [22..22] 0x1 indicates CRNGT in the PRNG test failed. Failure
2826                                                      occurs when two consecutive results of AES are equal                      */
2827       __IOM uint32_t REQSIZE    : 1;            /*!< [23..23] 0x1 indicates that the request size counter (which
2828                                                      represents how many generations of random bits in the PRNG
2829                                                      have been produced) has reached 2^12, thus requiring a
2830                                                      working state update before generating new random numbers.                */
2831       __IOM uint32_t KATERR     : 1;            /*!< [24..24] 0x1 indicates that one of the KAT (Known Answer Tests)
2832                                                      tests has failed. When set, the entire engine ceases to
2833                                                      function.                                                                 */
2834       __IOM uint32_t WHICHKATERR : 2;           /*!< [26..25] When the KAT_ERR bit is set, these bits represent which
2835                                                      Known Answer Test had failed:                                             */
2836             uint32_t            : 5;
2837     } RNGISR_b;
2838   } ;
2839 
2840   union {
2841     __IOM uint32_t RNGICR;                      /*!< (@ 0x00000108) Interrupt_status bit clear Register. Consists
2842                                                                     of trng_icr and prng_icr bit[15-0] - TRNG
2843                                                                     bit[31-16] - PRNG                                          */
2844 
2845     struct {
2846       __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] Writing value 0x1 - clears corresponding bit in RNGISR             */
2847       __IOM uint32_t AUTOCORRERR : 1;           /*!< [1..1] Cannot be cleared by SW! Only RNG reset clears this bit.           */
2848       __IOM uint32_t CRNGTERR   : 1;            /*!< [2..2] Writing value 0x1 - clears corresponding bit in RNGISR             */
2849       __IOM uint32_t VNERR      : 1;            /*!< [3..3] Writing value 0x1 - clears corresponding bit in RNGISR             */
2850       __IOM uint32_t RNGWATCHDOG : 1;           /*!< [4..4] Writing value 0x1 - clears corresponding bit in RNGISR             */
2851       __IOM uint32_t RNGDMADONE : 1;            /*!< [5..5] Writing value 0x1 - clears corresponding bit in RNGISR             */
2852             uint32_t            : 10;
2853       __IOM uint32_t RESEEDINGDONE : 1;         /*!< [16..16] Writing value 0x1 - clears corresponding bit in RNGISR           */
2854       __IOM uint32_t INSTANTIATIONDONE : 1;     /*!< [17..17] Writing value 0x1 - clears corresponding bit in RNGISR           */
2855       __IOM uint32_t FINALUPDATEDONE : 1;       /*!< [18..18] Writing value 0x1 - clears corresponding bit in RNGISR           */
2856       __IOM uint32_t OUTPUTREADY : 1;           /*!< [19..19] Writing value 0x1 - clears corresponding bit in RNGISR           */
2857       __IOM uint32_t RESEEDCNTRFULL : 1;        /*!< [20..20] Writing value 0x1 - clears corresponding bit in RNGISR           */
2858       __IOM uint32_t RESEEDCNTRTOP40 : 1;       /*!< [21..21] Writing value 0x1 - clears corresponding bit in RNGISR           */
2859       __IOM uint32_t PRNGCRNGTERR : 1;          /*!< [22..22] Writing value 0x1 - clears corresponding bit in RNGISR           */
2860       __IOM uint32_t REQSIZE    : 1;            /*!< [23..23] Writing value 0x1 - clears corresponding bit in RNGISR           */
2861       __IOM uint32_t KATERR     : 1;            /*!< [24..24] Cannot be cleared by SW! Only RNG reset clears this
2862                                                      bit.                                                                      */
2863       __IOM uint32_t WHICHKATERR : 2;           /*!< [26..25] Cannot be cleared by SW! Only RNG reset clears this
2864                                                      bit.                                                                      */
2865             uint32_t            : 5;
2866     } RNGICR_b;
2867   } ;
2868 
2869   union {
2870     __IOM uint32_t TRNGCONFIG;                  /*!< (@ 0x0000010C) This register handles TRNG configuration                   */
2871 
2872     struct {
2873       __IOM uint32_t RNDSRCSEL  : 2;            /*!< [1..0] Defines the length of the oscillator ring (= the number
2874                                                      of inverters) out of four possible selections.                            */
2875       __IOM uint32_t SOPSEL     : 1;            /*!< [2..2] Secure Output Port selection:                                      */
2876             uint32_t            : 29;
2877     } TRNGCONFIG_b;
2878   } ;
2879 
2880   union {
2881     __IOM uint32_t TRNGVALID;                   /*!< (@ 0x00000110) This register indicates that the TRNG data is
2882                                                                     valid.                                                     */
2883 
2884     struct {
2885       __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] 0x1 indicates that collection of bits in the TRNG is
2886                                                      completed, and data can be read from the EHR_DATA register.               */
2887             uint32_t            : 31;
2888     } TRNGVALID_b;
2889   } ;
2890 
2891   union {
2892     __IOM uint32_t EHRDATA0;                    /*!< (@ 0x00000114) This register contains the data collected in
2893                                                                     the TRNG[31_0]. Note: can only be set while
2894                                                                     in debug mode (rng_debug_enable input is
2895                                                                     set).                                                      */
2896 
2897     struct {
2898       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[31_0]. Note:
2899                                                      can only be set while in debug mode (rng_debug_enable input
2900                                                      is set).                                                                  */
2901     } EHRDATA0_b;
2902   } ;
2903 
2904   union {
2905     __IOM uint32_t EHRDATA1;                    /*!< (@ 0x00000118) This register contains the data collected in
2906                                                                     the TRNG[63_32]. Note: can only be set while
2907                                                                     in debug mode (rng_debug_enable input is
2908                                                                     set).                                                      */
2909 
2910     struct {
2911       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[63_32]. Note:
2912                                                      can only be set while in debug mode (rng_debug_enable input
2913                                                      is set).                                                                  */
2914     } EHRDATA1_b;
2915   } ;
2916 
2917   union {
2918     __IOM uint32_t EHRDATA2;                    /*!< (@ 0x0000011C) This register contains the data collected in
2919                                                                     the TRNG[95_64]. Note: can only be set while
2920                                                                     in debug mode (rng_debug_enable input is
2921                                                                     set).                                                      */
2922 
2923     struct {
2924       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[95_64]. Note:
2925                                                      can only be set while in debug mode (rng_debug_enable input
2926                                                      is set).                                                                  */
2927     } EHRDATA2_b;
2928   } ;
2929 
2930   union {
2931     __IOM uint32_t EHRDATA3;                    /*!< (@ 0x00000120) This register contains the data collected in
2932                                                                     the TRNG[127_96]. Note: can only be set
2933                                                                     while in debug mode (rng_debug_enable input
2934                                                                     is set).                                                   */
2935 
2936     struct {
2937       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[127_96]. Note:
2938                                                      can only be set while in debug mode (rng_debug_enable input
2939                                                      is set).                                                                  */
2940     } EHRDATA3_b;
2941   } ;
2942 
2943   union {
2944     __IOM uint32_t EHRDATA4;                    /*!< (@ 0x00000124) This register contains the data collected in
2945                                                                     the TRNG[159_128]. Note: can only be set
2946                                                                     while in debug mode (rng_debug_enable input
2947                                                                     is set).                                                   */
2948 
2949     struct {
2950       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[159_128]. Note:
2951                                                      can only be set while in debug mode (rng_debug_enable input
2952                                                      is set).                                                                  */
2953     } EHRDATA4_b;
2954   } ;
2955 
2956   union {
2957     __IOM uint32_t EHRDATA5;                    /*!< (@ 0x00000128) This register contains the data collected in
2958                                                                     the TRNG[191_160]. Note: can only be set
2959                                                                     while in debug mode (rng_debug_enable input
2960                                                                     is set).                                                   */
2961 
2962     struct {
2963       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[191_160]. Note:
2964                                                      can only be set while in debug mode (rng_debug_enable input
2965                                                      is set).                                                                  */
2966     } EHRDATA5_b;
2967   } ;
2968 
2969   union {
2970     __IOM uint32_t RNDSOURCEENABLE;             /*!< (@ 0x0000012C) This register holds the enable signal for the
2971                                                                     random source.                                             */
2972 
2973     struct {
2974       __IOM uint32_t RNDSRCEN   : 1;            /*!< [0..0] Enable signal for the random source.                               */
2975             uint32_t            : 31;
2976     } RNDSOURCEENABLE_b;
2977   } ;
2978 
2979   union {
2980     __IOM uint32_t SAMPLECNT1;                  /*!< (@ 0x00000130) Counts clocks between sampling of random bit.              */
2981 
2982     struct {
2983       __IOM uint32_t SAMPLECNTR1 : 32;          /*!< [31..0] Sets the number of rng_clk cycles between two consecutive
2984                                                      ring oscillator samples. Note: If the Von-Neumann is bypassed,
2985                                                      the minimum value for sample counter must not be less than
2986                                                      decimal seventeen.                                                        */
2987     } SAMPLECNT1_b;
2988   } ;
2989 
2990   union {
2991     __IOM uint32_t AUTOCORRSTATISTIC;           /*!< (@ 0x00000134) Statistics about autocorrelation test activations.         */
2992 
2993     struct {
2994       __IOM uint32_t AUTOCORRTRYS : 14;         /*!< [13..0] Count each time an autocorrelation test starts. Any
2995                                                      write to the register resets the counter. Stops collecting
2996                                                      statistics if one of the counters has reached the limit.                  */
2997       __IOM uint32_t AUTOCORRFAILS : 8;         /*!< [21..14] Count each time an autocorrelation test fails. Any
2998                                                      write to the register resets the counter. Stops collecting
2999                                                      statistics if one of the counters has reached the limit.                  */
3000             uint32_t            : 10;
3001     } AUTOCORRSTATISTIC_b;
3002   } ;
3003 
3004   union {
3005     __IOM uint32_t TRNGDEBUGCONTROL;            /*!< (@ 0x00000138) This register is used to debug the TRNG                    */
3006 
3007     struct {
3008             uint32_t            : 1;
3009       __IOM uint32_t VNCBYPASS  : 1;            /*!< [1..1] When this bit is set, the Von-Neumann balancer is bypassed
3010                                                      (including the 32 consecutive bits test). Note: Can only
3011                                                      be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW
3012                                                      flag is defined, this bit can be set while not in debug
3013                                                      mode.                                                                     */
3014       __IOM uint32_t TRNGCRNGTBYPASS : 1;       /*!< [2..2] When this bit is set, the CRNGT test in the TRNG is bypassed.
3015                                                      Note: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN
3016                                                      HW flag is defined, this bit can be set while not in debug
3017                                                      mode.                                                                     */
3018       __IOM uint32_t AUTOCORRELATEBYPASS : 1;   /*!< [3..3] When this bit is set, the autocorrelation test in the
3019                                                      TRNG module is bypassed. Note: Can only be set while in
3020                                                      debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined,
3021                                                      this bit can be set while not in debug mode.                              */
3022             uint32_t            : 28;
3023     } TRNGDEBUGCONTROL_b;
3024   } ;
3025   __IM  uint32_t  RESERVED5;
3026 
3027   union {
3028     __IOM uint32_t RNGSWRESET;                  /*!< (@ 0x00000140) Generate SW reset solely to RNG block.                     */
3029 
3030     struct {
3031       __IOM uint32_t RNGSWRESET : 1;            /*!< [0..0] Any value written (0x0 or 0x1) causes a reset cycle to
3032                                                      the TRNG block.                                                           */
3033             uint32_t            : 31;
3034     } RNGSWRESET_b;
3035   } ;
3036   __IM  uint32_t  RESERVED6[28];
3037 
3038   union {
3039     __IOM uint32_t RNGDEBUGENINPUT;             /*!< (@ 0x000001B4) Defines the RNG in debug mode                              */
3040 
3041     struct {
3042       __IOM uint32_t RNGDEBUGEN : 1;            /*!< [0..0] Reflects the rng_debug_enable input port                           */
3043             uint32_t            : 31;
3044     } RNGDEBUGENINPUT_b;
3045   } ;
3046 
3047   union {
3048     __IOM uint32_t RNGBUSY;                     /*!< (@ 0x000001B8) RNG busy indication                                        */
3049 
3050     struct {
3051       __IOM uint32_t RNGBUSY    : 1;            /*!< [0..0] Reflects rng_busy output port which Consists of trng_busy
3052                                                      and prng_busy.                                                            */
3053       __IOM uint32_t TRNGBUSY   : 1;            /*!< [1..1] Reflects trng_busy.                                                */
3054       __IOM uint32_t PRNGBUSY   : 1;            /*!< [2..2] Reflects prng_busy.                                                */
3055             uint32_t            : 29;
3056     } RNGBUSY_b;
3057   } ;
3058 
3059   union {
3060     __IOM uint32_t RSTBITSCOUNTER;              /*!< (@ 0x000001BC) Resets the counter of collected bits in the TRNG           */
3061 
3062     struct {
3063       __IOM uint32_t RSTBITSCOUNTER : 1;        /*!< [0..0] Writing any value to this address resets the bits counter
3064                                                      and trng valid registers.                                                 */
3065             uint32_t            : 31;
3066     } RSTBITSCOUNTER_b;
3067   } ;
3068 
3069   union {
3070     __IOM uint32_t RNGVERSION;                  /*!< (@ 0x000001C0) This register holds the RNG version                        */
3071 
3072     struct {
3073       __IOM uint32_t EHRWIDTH192 : 1;           /*!< [0..0] EHR width selection.                                               */
3074       __IOM uint32_t CRNGTEXISTS : 1;           /*!< [1..1] CRNGT exists.                                                      */
3075       __IOM uint32_t AUTOCORREXISTS : 1;        /*!< [2..2] Auto correct exists.                                               */
3076       __IOM uint32_t TRNGTESTSBYPASSEN : 1;     /*!< [3..3] TRNG tests bypass enable.                                          */
3077       __IOM uint32_t PRNGEXISTS : 1;            /*!< [4..4] PRNG Exists.                                                       */
3078       __IOM uint32_t KATEXISTS  : 1;            /*!< [5..5] KAT exists.                                                        */
3079       __IOM uint32_t RESEEDINGEXISTS : 1;       /*!< [6..6] Reseeding exists.                                                  */
3080       __IOM uint32_t RNGUSE5SBOXES : 1;         /*!< [7..7] RNG use 5 (or 20) SBOX AES                                         */
3081             uint32_t            : 24;
3082     } RNGVERSION_b;
3083   } ;
3084 
3085   union {
3086     __IOM uint32_t RNGCLKENABLE;                /*!< (@ 0x000001C4) Writing to this register enables_disables the
3087                                                                     RNG clock.                                                 */
3088 
3089     struct {
3090       __IOM uint32_t EN         : 1;            /*!< [0..0] Writing value 0x1 enables RNG clock.                               */
3091             uint32_t            : 31;
3092     } RNGCLKENABLE_b;
3093   } ;
3094 
3095   union {
3096     __IOM uint32_t RNGDMAENABLE;                /*!< (@ 0x000001C8) Writing to this register enables_disables the
3097                                                                     RNG DMA.                                                   */
3098 
3099     struct {
3100       __IOM uint32_t EN         : 1;            /*!< [0..0] Writing value 0x1 enables RNG DMA to SRAM. The Value
3101                                                      is cleared when DMA completes its operation.                              */
3102             uint32_t            : 31;
3103     } RNGDMAENABLE_b;
3104   } ;
3105 
3106   union {
3107     __IOM uint32_t RNGDMASRCMASK;               /*!< (@ 0x000001CC) This register defines which ring-oscillator length
3108                                                                     should be used when using the RNG DMA.                     */
3109 
3110     struct {
3111       __IOM uint32_t ENSRCSEL0  : 1;            /*!< [0..0] Writing value 0x1 enables SRC_SEL 0.                               */
3112       __IOM uint32_t ENSRCSEL1  : 1;            /*!< [1..1] Writing value 0x1 enables SRC_SEL 1.                               */
3113       __IOM uint32_t ENSRCSEL2  : 1;            /*!< [2..2] Writing value 0x1 enables SRC_SEL 2.                               */
3114       __IOM uint32_t ENSRCSEL3  : 1;            /*!< [3..3] Writing value 0x1 enables SRC_SEL 3.                               */
3115             uint32_t            : 28;
3116     } RNGDMASRCMASK_b;
3117   } ;
3118 
3119   union {
3120     __IOM uint32_t RNGDMASRAMADDR;              /*!< (@ 0x000001D0) This register defines the start address of the
3121                                                                     DMA for the TRNG data.                                     */
3122 
3123     struct {
3124       __IOM uint32_t RNGSRAMDMAADDR : 11;       /*!< [10..0] Defines the start address of the DMA for the TRNG data.           */
3125             uint32_t            : 21;
3126     } RNGDMASRAMADDR_b;
3127   } ;
3128   __IM  uint32_t  RESERVED7;
3129 
3130   union {
3131     __IOM uint32_t RNGWATCHDOGVAL;              /*!< (@ 0x000001D8) This register defines the number of 192-bits
3132                                                                     samples that the DMA collects per RNG configuration.bitfie
3133                                                                     d 7:0 RNG_SAMPLES_NUM rw 0x0 Defines the
3134                                                                     number of 192-bits samples that the DMA
3135                                                                     collects per RNG configuration.bitfield
3136                                                                     31:8 RESERVED rw 0x0 ReservedThis register
3137                                                                     defines the maximum number of clock cycles
3138                                                                     per TRNG collection of 192 samples. If the
3139                                                                     number of cycles for a collection exceeds
3140                                                                     this threshold, TRNG signals an interrupt.                 */
3141 
3142     struct {
3143       __IOM uint32_t RNGWATCHDOGVAL : 32;       /*!< [31..0] Defines the maximum number of clock cycles per TRNG
3144                                                      collection of 192 samples. If the number of cycles for
3145                                                      a collection exceeds this threshold, TRNG signals an interrupt.           */
3146     } RNGWATCHDOGVAL_b;
3147   } ;
3148 
3149   union {
3150     __IOM uint32_t RNGDMASTATUS;                /*!< (@ 0x000001DC) This register holds the RNG DMA status.                    */
3151 
3152     struct {
3153       __IOM uint32_t RNGDMABUSY : 1;            /*!< [0..0] Indicates whether DMA is busy.                                     */
3154       __IOM uint32_t DMASRCSEL  : 2;            /*!< [2..1] The active ring oscillator length using by DMA                     */
3155       __IOM uint32_t NUMOFSAMPLES : 8;          /*!< [10..3] Number of samples already collected in the current ring
3156                                                      oscillator chain length.                                                  */
3157             uint32_t            : 21;
3158     } RNGDMASTATUS_b;
3159   } ;
3160   __IM  uint32_t  RESERVED8[104];
3161 
3162   union {
3163     __IOM uint32_t CHACHACONTROLREG;            /*!< (@ 0x00000380) CHACHA general configuration.                              */
3164 
3165     struct {
3166       __IOM uint32_t CHACHAORSALSA : 1;         /*!< [0..0] Core:                                                              */
3167       __IOM uint32_t INITFROMHOST : 1;          /*!< [1..1] Start init for new Message:                                        */
3168       __IOM uint32_t CALCKEYFORPOLY1305 : 1;    /*!< [2..2] Only if ChaCha core:                                               */
3169       __IOM uint32_t KEYLEN     : 1;            /*!< [3..3] For All Core:                                                      */
3170       __IOM uint32_t NUMOFROUNDS : 2;           /*!< [5..4] The core of ChaCha is a hash function which based on
3171                                                      rotation operations. The hash function consist in application
3172                                                      of 20 rounds (default value). In additional, ChaCha have
3173                                                      two variants (they work exactly as the original algorithm):
3174                                                      ChaCha20_8 and ChaCha20_12 (using 8 and 12 rounds).                       */
3175             uint32_t            : 3;
3176       __IOM uint32_t RESETBLOCKCNT : 1;         /*!< [9..9] For new message                                                    */
3177       __IOM uint32_t USEIV96BIT : 1;            /*!< [10..10] If use 96bit IV                                                  */
3178             uint32_t            : 21;
3179     } CHACHACONTROLREG_b;
3180   } ;
3181 
3182   union {
3183     __IOM uint32_t CHACHAVERSION;               /*!< (@ 0x00000384) CHACHA Version                                             */
3184 
3185     struct {
3186       __IOM uint32_t CHACHAVERSION : 32;        /*!< [31..0] CHACHA version.                                                   */
3187     } CHACHAVERSION_b;
3188   } ;
3189 
3190   union {
3191     __IOM uint32_t CHACHAKEY0;                  /*!< (@ 0x00000388) bits 255:224 of CHACHA Key                                 */
3192 
3193     struct {
3194       __IOM uint32_t CHACHAKEY0 : 32;           /*!< [31..0] bits 255:224 of CHACHA Key                                        */
3195     } CHACHAKEY0_b;
3196   } ;
3197 
3198   union {
3199     __IOM uint32_t CHACHAKEY1;                  /*!< (@ 0x0000038C) bits 223:192 of CHACHA Key                                 */
3200 
3201     struct {
3202       __IOM uint32_t CHACHAKEY1 : 32;           /*!< [31..0] bits 223:192 of CHACHA Key                                        */
3203     } CHACHAKEY1_b;
3204   } ;
3205 
3206   union {
3207     __IOM uint32_t CHACHAKEY2;                  /*!< (@ 0x00000390) bits 191:160 of CHACHA Key                                 */
3208 
3209     struct {
3210       __IOM uint32_t CHACHAKEY2 : 32;           /*!< [31..0] bits191:160 of CHACHA Key                                         */
3211     } CHACHAKEY2_b;
3212   } ;
3213 
3214   union {
3215     __IOM uint32_t CHACHAKEY3;                  /*!< (@ 0x00000394) bits159:128 of CHACHA Key                                  */
3216 
3217     struct {
3218       __IOM uint32_t CHACHAKEY3 : 32;           /*!< [31..0] bits 159:128 of CHACHA Key                                        */
3219     } CHACHAKEY3_b;
3220   } ;
3221 
3222   union {
3223     __IOM uint32_t CHACHAKEY4;                  /*!< (@ 0x00000398) bits 127:96 of CHACHA Key                                  */
3224 
3225     struct {
3226       __IOM uint32_t CHACHAKEY4 : 32;           /*!< [31..0] bits 127:96 of CHACHA Key                                         */
3227     } CHACHAKEY4_b;
3228   } ;
3229 
3230   union {
3231     __IOM uint32_t CHACHAKEY5;                  /*!< (@ 0x0000039C) bits 95:64 of CHACHA Key                                   */
3232 
3233     struct {
3234       __IOM uint32_t CHACHAKEY5 : 32;           /*!< [31..0] bits 95:64 of CHACHA Key                                          */
3235     } CHACHAKEY5_b;
3236   } ;
3237 
3238   union {
3239     __IOM uint32_t CHACHAKEY6;                  /*!< (@ 0x000003A0) bits 63:32 of CHACHA Key                                   */
3240 
3241     struct {
3242       __IOM uint32_t CHACHAKEY6 : 32;           /*!< [31..0] bits 63:32 of CHACHA Key                                          */
3243     } CHACHAKEY6_b;
3244   } ;
3245 
3246   union {
3247     __IOM uint32_t CHACHAKEY7;                  /*!< (@ 0x000003A4) bits 31:0 of CHACHA Key                                    */
3248 
3249     struct {
3250       __IOM uint32_t CHACHAKEY7 : 32;           /*!< [31..0] bits 31:0 of CHACHA Key                                           */
3251     } CHACHAKEY7_b;
3252   } ;
3253 
3254   union {
3255     __IOM uint32_t CHACHAIV0;                   /*!< (@ 0x000003A8) bits 31:0 of CHACHA_IV0 register                           */
3256 
3257     struct {
3258       __IOM uint32_t CHACHAIV0  : 32;           /*!< [31..0] bits 31:0 of CHACHA_IV0 register                                  */
3259     } CHACHAIV0_b;
3260   } ;
3261 
3262   union {
3263     __IOM uint32_t CHACHAIV1;                   /*!< (@ 0x000003AC) bits 31:0 of CHACHA_IV1 register                           */
3264 
3265     struct {
3266       __IOM uint32_t CHACHAIV1  : 32;           /*!< [31..0] bits 31:0 of CHACHA_IV1 register                                  */
3267     } CHACHAIV1_b;
3268   } ;
3269 
3270   union {
3271     __IOM uint32_t CHACHABUSY;                  /*!< (@ 0x000003B0) This register is set when the CHACHA_SALSA core
3272                                                                     is active                                                  */
3273 
3274     struct {
3275       __IOM uint32_t CHACHABUSY : 1;            /*!< [0..0] CHACHA_BUSY Register. This register is set when the CHACHA_SALSA
3276                                                      core is active.                                                           */
3277             uint32_t            : 31;
3278     } CHACHABUSY_b;
3279   } ;
3280 
3281   union {
3282     __IOM uint32_t CHACHAHWFLAGS;               /*!< (@ 0x000003B4) This register holds the pre-synthesis HW flag
3283                                                                     configuration of the CHACHA_SALSA engine                   */
3284 
3285     struct {
3286       __IOM uint32_t CHACHAEXISTS : 1;          /*!< [0..0] If this flag is set, the Salsa_ChaCha engine include
3287                                                      ChaCha implementation:                                                    */
3288       __IOM uint32_t SALSAEXISTS : 1;           /*!< [1..1] If this flag is set, the Salsa_ChaCha engine include
3289                                                      Salsa implementation:                                                     */
3290       __IOM uint32_t FASTCHACHA : 1;            /*!< [2..2] If this flag is set, the next matrix calculated when
3291                                                      the current one is written to data output path (same flag
3292                                                      for Salsa core):                                                          */
3293             uint32_t            : 29;
3294     } CHACHAHWFLAGS_b;
3295   } ;
3296 
3297   union {
3298     __IOM uint32_t CHACHABLOCKCNTLSB;           /*!< (@ 0x000003B8) The two first words (n) in the last row of the
3299                                                                     cipher matrix are the block counter. At
3300                                                                     the end of each block (512b), the block_cnt
3301                                                                     for the next block is written by HW to the
3302                                                                     block_cnt_lsb and block_cnt_msb registers.
3303                                                                     Need reset block counter , if start new
3304                                                                     message.                                                   */
3305 
3306     struct {
3307       __IOM uint32_t CHACHABLOCKCNTLSB : 32;    /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_LSB register.                       */
3308     } CHACHABLOCKCNTLSB_b;
3309   } ;
3310 
3311   union {
3312     __IOM uint32_t CHACHABLOCKCNTMSB;           /*!< (@ 0x000003BC) The two first words (n) in the last row of the
3313                                                                     cipher matrix are the block counter. At
3314                                                                     the end of each block (512b), the block_cnt
3315                                                                     for the next block is written by HW to the
3316                                                                     block_cnt_lsb and block_cnt_msb registers.
3317                                                                     Need reset block counter , if start new
3318                                                                     message.                                                   */
3319 
3320     struct {
3321       __IOM uint32_t CHACHABLOCKCNTMSB : 32;    /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_MSB register.                       */
3322     } CHACHABLOCKCNTMSB_b;
3323   } ;
3324 
3325   union {
3326     __IOM uint32_t CHACHASWRESET;               /*!< (@ 0x000003C0) Resets CHACHA_SALSA engine.                                */
3327 
3328     struct {
3329       __IOM uint32_t CHACHSWRESET : 1;          /*!< [0..0] Writing to this address resets the only FSM of CHACHA
3330                                                      engine. The reset takes 4 CORE_CLK cycles.                                */
3331             uint32_t            : 31;
3332     } CHACHASWRESET_b;
3333   } ;
3334 
3335   union {
3336     __IOM uint32_t CHACHAFORPOLYKEY0;           /*!< (@ 0x000003C4) bits 255:224 of CHACHA_FOR_POLY_KEY                        */
3337 
3338     struct {
3339       __IOM uint32_t CHACHAFORPOLYKEY0 : 32;    /*!< [31..0] bits 255:224 of CHACHA_FOR_POLY_KEY                               */
3340     } CHACHAFORPOLYKEY0_b;
3341   } ;
3342 
3343   union {
3344     __IOM uint32_t CHACHAFORPOLYKEY1;           /*!< (@ 0x000003C8) bits 223:192 of CHACHA_FOR_POLY_KEY                        */
3345 
3346     struct {
3347       __IOM uint32_t CHACHAFORPOLYKEY1 : 32;    /*!< [31..0] bits 223:192 of CHACHA_FOR_POLY_KEY                               */
3348     } CHACHAFORPOLYKEY1_b;
3349   } ;
3350 
3351   union {
3352     __IOM uint32_t CHACHAFORPOLYKEY2;           /*!< (@ 0x000003CC) bits191:160 of CHACHA_FOR_POLY_KEY                         */
3353 
3354     struct {
3355       __IOM uint32_t CHACHAFORPOLYKEY2 : 32;    /*!< [31..0] bits191:160 of CHACHA_FOR_POLY_KEY                                */
3356     } CHACHAFORPOLYKEY2_b;
3357   } ;
3358 
3359   union {
3360     __IOM uint32_t CHACHAFORPOLYKEY3;           /*!< (@ 0x000003D0) bits159:128 of CHACHA_FOR_POLY_KEY                         */
3361 
3362     struct {
3363       __IOM uint32_t CHACHAFORPOLYKEY3 : 32;    /*!< [31..0] bits 159:128 of CHACHA_FOR_POLY_KEY                               */
3364     } CHACHAFORPOLYKEY3_b;
3365   } ;
3366 
3367   union {
3368     __IOM uint32_t CHACHAFORPOLYKEY4;           /*!< (@ 0x000003D4) bits 127:96 of CHACHA_FOR_POLY_KEY                         */
3369 
3370     struct {
3371       __IOM uint32_t CHACHAFORPOLYKEY4 : 32;    /*!< [31..0] bits 127:96 of CHACHA_FOR_POLY_KEY                                */
3372     } CHACHAFORPOLYKEY4_b;
3373   } ;
3374 
3375   union {
3376     __IOM uint32_t CHACHAFORPOLYKEY5;           /*!< (@ 0x000003D8) bits 95:64 of CHACHA_FOR_POLY_KEY                          */
3377 
3378     struct {
3379       __IOM uint32_t CHACHAFORPOLYKEY5 : 32;    /*!< [31..0] bits 95:64 of CHACHA_FOR_POLY_KEY                                 */
3380     } CHACHAFORPOLYKEY5_b;
3381   } ;
3382 
3383   union {
3384     __IOM uint32_t CHACHAFORPOLYKEY6;           /*!< (@ 0x000003DC) bits 63:32 of CHACHA_FOR_POLY_KEY                          */
3385 
3386     struct {
3387       __IOM uint32_t CHACHAFORPOLYKEY6 : 32;    /*!< [31..0] bits 63:32 of CHACHA_FOR_POLY_KEY                                 */
3388     } CHACHAFORPOLYKEY6_b;
3389   } ;
3390 
3391   union {
3392     __IOM uint32_t CHACHAFORPOLYKEY7;           /*!< (@ 0x000003E0) bits 31:0 of CHACHA_FOR_POLY_KEY                           */
3393 
3394     struct {
3395       __IOM uint32_t CHACHAFORPOLYKEY7 : 32;    /*!< [31..0] bits 31:0 of CHACHA_FOR_POLY_KEY                                  */
3396     } CHACHAFORPOLYKEY7_b;
3397   } ;
3398 
3399   union {
3400     __IOM uint32_t CHACHABYTEWORDORDERCNTLREG;  /*!< (@ 0x000003E4) CHACHA_SALSA DATA ORDER configuration.                     */
3401 
3402     struct {
3403       __IOM uint32_t CHACHADINWORDORDER : 1;    /*!< [0..0] Change the words order of the input data.                          */
3404       __IOM uint32_t CHACHADINBYTEORDER : 1;    /*!< [1..1] Change the byte order of the input data.                           */
3405       __IOM uint32_t CHACHACOREMATRIXLBEORDER : 1;/*!< [2..2] Change the quarter of a matrix order in core                     */
3406       __IOM uint32_t CHACHADOUTWORDORDER : 1;   /*!< [3..3] Change the words order of the output data.                         */
3407       __IOM uint32_t CHACHADOUTBYTEORDER : 1;   /*!< [4..4] Change the byte order of the output data.                          */
3408             uint32_t            : 27;
3409     } CHACHABYTEWORDORDERCNTLREG_b;
3410   } ;
3411 
3412   union {
3413     __IOM uint32_t CHACHADEBUGREG;              /*!< (@ 0x000003E8) This register is used to debug the CHACHA engine           */
3414 
3415     struct {
3416       __IOM uint32_t CHACHADEBUGFSMSTATE : 2;   /*!< [1..0] CHACHA_DEBUG_FSM_STATE                                             */
3417             uint32_t            : 30;
3418     } CHACHADEBUGREG_b;
3419   } ;
3420   __IM  uint32_t  RESERVED9[5];
3421 
3422   union {
3423     __IOM uint32_t AESKEY00;                    /*!< (@ 0x00000400) bits 31:0 of AES Key0 (used as the AES key in
3424                                                                     non-tunneling operations, and as the first
3425                                                                     tunnel stage key in tunneling operations).                 */
3426 
3427     struct {
3428       __IOM uint32_t AESKEY00   : 32;           /*!< [31..0] bits 31:0 of AES Key0.                                            */
3429     } AESKEY00_b;
3430   } ;
3431 
3432   union {
3433     __IOM uint32_t AESKEY01;                    /*!< (@ 0x00000404) bits 63:32 of AES Key0 (used as the AES key in
3434                                                                     non-tunneling operations, and as the first
3435                                                                     tunnel stage key in tunneling operations).                 */
3436 
3437     struct {
3438       __IOM uint32_t AESKEY01   : 32;           /*!< [31..0] bits 63:32 of AES Key0.                                           */
3439     } AESKEY01_b;
3440   } ;
3441 
3442   union {
3443     __IOM uint32_t AESKEY02;                    /*!< (@ 0x00000408) bits 95:64 of AES Key0 (used as the AES key in
3444                                                                     non-tunneling operations, and as the first
3445                                                                     tunnel stage key in tunneling operations).                 */
3446 
3447     struct {
3448       __IOM uint32_t AESKEY02   : 32;           /*!< [31..0] bits 95:64 of AES Key0.                                           */
3449     } AESKEY02_b;
3450   } ;
3451 
3452   union {
3453     __IOM uint32_t AESKEY03;                    /*!< (@ 0x0000040C) bits 127:96 of AES Key0 (used as the AES key
3454                                                                     in non-tunneling operations, and as the
3455                                                                     first tunnel stage key in tunneling operations).           */
3456 
3457     struct {
3458       __IOM uint32_t AESKEY03   : 32;           /*!< [31..0] bits 127:96 of AES Key0.                                          */
3459     } AESKEY03_b;
3460   } ;
3461 
3462   union {
3463     __IOM uint32_t AESKEY04;                    /*!< (@ 0x00000410) bits 159:128 of AES Key0 (used as the AES key
3464                                                                     in non-tunneling operations, and as the
3465                                                                     first tunnel stage key in tunneling operations).           */
3466 
3467     struct {
3468       __IOM uint32_t AESKEY04   : 32;           /*!< [31..0] bits 159:128 of AES Key0 .                                        */
3469     } AESKEY04_b;
3470   } ;
3471 
3472   union {
3473     __IOM uint32_t AESKEY05;                    /*!< (@ 0x00000414) bits 191:160 of AES Key0 (used as the AES key
3474                                                                     in non-tunneling operations, and as the
3475                                                                     first tunnel stage key in tunneling operations).           */
3476 
3477     struct {
3478       __IOM uint32_t AESKEY05   : 32;           /*!< [31..0] bits 191:160 of AES Key0.                                         */
3479     } AESKEY05_b;
3480   } ;
3481 
3482   union {
3483     __IOM uint32_t AESKEY06;                    /*!< (@ 0x00000418) bits 223:192 of AES Key0 (used as the AES key
3484                                                                     in non-tunneling operations, and as the
3485                                                                     first tunnel stage key in tunneling operations).           */
3486 
3487     struct {
3488       __IOM uint32_t AESKEY06   : 32;           /*!< [31..0] bits 223:192 of AES Key0.                                         */
3489     } AESKEY06_b;
3490   } ;
3491 
3492   union {
3493     __IOM uint32_t AESKEY07;                    /*!< (@ 0x0000041C) bits 255:224 of AES Key0 (used as the AES key
3494                                                                     in non-tunneling operations, and as the
3495                                                                     first tunnel stage key in tunneling operations).           */
3496 
3497     struct {
3498       __IOM uint32_t AESKEY07   : 32;           /*!< [31..0] bits 255:224 of AES Key0.                                         */
3499     } AESKEY07_b;
3500   } ;
3501 
3502   union {
3503     __IOM uint32_t AESKEY10;                    /*!< (@ 0x00000420) bits 31:0 of AES Key1 (used as the second AES
3504                                                                     tunnel stage key in tunneling operations).                 */
3505 
3506     struct {
3507       __IOM uint32_t AESKEY10   : 32;           /*!< [31..0] bits 31:0 of AES Key1.                                            */
3508     } AESKEY10_b;
3509   } ;
3510 
3511   union {
3512     __IOM uint32_t AESKEY11;                    /*!< (@ 0x00000424) bits 63:32 of AES Key1 (used as the second AES
3513                                                                     tunnel stage key in tunneling operations).                 */
3514 
3515     struct {
3516       __IOM uint32_t AESKEY11   : 32;           /*!< [31..0] bits 63:32 of AES Key1.                                           */
3517     } AESKEY11_b;
3518   } ;
3519 
3520   union {
3521     __IOM uint32_t AESKEY12;                    /*!< (@ 0x00000428) bits 95:64 of AES Key1 (used as the second AES
3522                                                                     tunnel stage key in tunneling operations).                 */
3523 
3524     struct {
3525       __IOM uint32_t AESKEY12   : 32;           /*!< [31..0] bits 95:64 of AES Key1.                                           */
3526     } AESKEY12_b;
3527   } ;
3528 
3529   union {
3530     __IOM uint32_t AESKEY13;                    /*!< (@ 0x0000042C) bits 127:96 of AES Key1 (used as the second AES
3531                                                                     tunnel stage key in tunneling operations).                 */
3532 
3533     struct {
3534       __IOM uint32_t AESKEY13   : 32;           /*!< [31..0] bits 127:96 of AES Key1.                                          */
3535     } AESKEY13_b;
3536   } ;
3537 
3538   union {
3539     __IOM uint32_t AESKEY14;                    /*!< (@ 0x00000430) bits 159:128 of AES Key1 (used as the second
3540                                                                     AES tunnel stage key in tunneling operations).             */
3541 
3542     struct {
3543       __IOM uint32_t AESKEY14   : 32;           /*!< [31..0] bits 159:128 of AES Key1.                                         */
3544     } AESKEY14_b;
3545   } ;
3546 
3547   union {
3548     __IOM uint32_t AESKEY15;                    /*!< (@ 0x00000434) bits 191:160 of AES Key1 (used as the second
3549                                                                     AES tunnel stage key in tunneling operations).             */
3550 
3551     struct {
3552       __IOM uint32_t AESKEY15   : 32;           /*!< [31..0] bits 191:160 of AES Key1.                                         */
3553     } AESKEY15_b;
3554   } ;
3555 
3556   union {
3557     __IOM uint32_t AESKEY16;                    /*!< (@ 0x00000438) bits 223:192 of AES Key1 (used as the second
3558                                                                     AES tunnel stage key in tunneling operations).             */
3559 
3560     struct {
3561       __IOM uint32_t AESKEY16   : 32;           /*!< [31..0] bits 223:192 of AES Key1.                                         */
3562     } AESKEY16_b;
3563   } ;
3564 
3565   union {
3566     __IOM uint32_t AESKEY17;                    /*!< (@ 0x0000043C) bits 255:224 of AES Key1 (used as the second
3567                                                                     AES tunnel stage key in tunneling operations).             */
3568 
3569     struct {
3570       __IOM uint32_t AESKEY17   : 32;           /*!< [31..0] bits 255:224 of AES Key1.                                         */
3571     } AESKEY17_b;
3572   } ;
3573 
3574   union {
3575     __IOM uint32_t AESIV00;                     /*!< (@ 0x00000440) bits 31:0 of AES_IV0 register. AES IV0 is used
3576                                                                     as the AES IV (Initialization Value) register
3577                                                                     in non-tunneling operations,and as the first
3578                                                                     tunnel stage IV register in tunneling operations.The
3579                                                                     IV register should be loaded according to
3580                                                                     the AES mode:in AES CBC_CBC-MAC - the AES
3581                                                                     IV register should be loaded with the IV
3582                                                                     (initialization vector).in XTS-AES - the
3583                                                                     AES IV register should be loaded with the
3584                                                                     T value (unless the HW T calculation mode
3585                                                                     is active, in which the T value is calculated
3586                                                                     by the HW                                                  */
3587 
3588     struct {
3589       __IOM uint32_t AESIV00    : 32;           /*!< [31..0] bits 31:0 of AES_IV0 register.                                    */
3590     } AESIV00_b;
3591   } ;
3592 
3593   union {
3594     __IOM uint32_t AESIV01;                     /*!< (@ 0x00000444) bits 63:32 of AES_IV0 128b register.For the description
3595                                                                     of AES_IV0, see the AES_IV_0_0 register
3596                                                                     description                                                */
3597 
3598     struct {
3599       __IOM uint32_t AESIV01    : 32;           /*!< [31..0] bits 63:32 of AES_IV0 register.                                   */
3600     } AESIV01_b;
3601   } ;
3602 
3603   union {
3604     __IOM uint32_t AESIV02;                     /*!< (@ 0x00000448) bits 95:64 of AES_IV0 128b register.For the description
3605                                                                     of AES_IV0, see the AES_IV_0_0 register
3606                                                                     description                                                */
3607 
3608     struct {
3609       __IOM uint32_t AESIV02    : 32;           /*!< [31..0] bits 95:64 of AES_IV0 register.                                   */
3610     } AESIV02_b;
3611   } ;
3612 
3613   union {
3614     __IOM uint32_t AESIV03;                     /*!< (@ 0x0000044C) bits 127:96 of AES_IV0 128b register.For the
3615                                                                     description of AES_IV0, see the AES_IV_0_0
3616                                                                     register description                                       */
3617 
3618     struct {
3619       __IOM uint32_t AESIV03    : 32;           /*!< [31..0] bits 127:96 of AES_IV0 register.                                  */
3620     } AESIV03_b;
3621   } ;
3622 
3623   union {
3624     __IOM uint32_t AESIV10;                     /*!< (@ 0x00000450) bits 31:0 of AES_IV1 128b register.AES IV1 is
3625                                                                     used as the AES IV (Initialization Value)
3626                                                                     register as the second tunnel stage IV register
3627                                                                     in tunneling operations.The IV register
3628                                                                     should be loaded according to the AES mode:in
3629                                                                     AES CBC_CBC-MAC - the AES IV register should
3630                                                                     be loaded with the IV (initialization vector).in
3631                                                                     XTS-AES - the AES IV register should be
3632                                                                     loaded with the T value (unless the HW T
3633                                                                     calculation mode is active, in which the
3634                                                                     T value is calculated by the HW.                           */
3635 
3636     struct {
3637       __IOM uint32_t AESIV10    : 32;           /*!< [31..0] bits 31:0 of AES_IV1 register.                                    */
3638     } AESIV10_b;
3639   } ;
3640 
3641   union {
3642     __IOM uint32_t AESIV11;                     /*!< (@ 0x00000454) bits 63:32 of AES_IV1 128b register.For the description
3643                                                                     of AES_IV1, see the AES_IV_1_0 register
3644                                                                     description                                                */
3645 
3646     struct {
3647       __IOM uint32_t AESIV11    : 32;           /*!< [31..0] bits 63:32 of AES_IV1 register.                                   */
3648     } AESIV11_b;
3649   } ;
3650 
3651   union {
3652     __IOM uint32_t AESIV12;                     /*!< (@ 0x00000458) bits 95:64 of AES_IV1 128b register.For the description
3653                                                                     of AES_IV1, see the AES_IV_1_0 register
3654                                                                     description                                                */
3655 
3656     struct {
3657       __IOM uint32_t AESIV12    : 32;           /*!< [31..0] bits 95:64 of AES_IV1 register.                                   */
3658     } AESIV12_b;
3659   } ;
3660 
3661   union {
3662     __IOM uint32_t AESIV13;                     /*!< (@ 0x0000045C) bits 127:96 of AES_IV1 128b register.For the
3663                                                                     description of AES_IV1, see the AES_IV_1_0
3664                                                                     register description                                       */
3665 
3666     struct {
3667       __IOM uint32_t AESIV13    : 32;           /*!< [31..0] bits 127:96 of AES_IV1 register.                                  */
3668     } AESIV13_b;
3669   } ;
3670 
3671   union {
3672     __IOM uint32_t AESCTR00;                    /*!< (@ 0x00000460) bits 31:0 of AES_CTR0 128b register.AES CTR0
3673                                                                     is used as the AES CTR (counter) register
3674                                                                     in non-tunneling operations, and as the
3675                                                                     first tunnel stage CTR register in tunneling
3676                                                                     operations.The CTR register should be loaded
3677                                                                     according to the AES mode:in AES CTR_GCTR
3678                                                                     - the AES CTR register should be loaded
3679                                                                     with the counter value.in XTS-AES - the
3680                                                                     AES CTR register should be loaded with the
3681                                                                     i value (in order to calculate the T value
3682                                                                     from it, if HW T calculation is supported).                */
3683 
3684     struct {
3685       __IOM uint32_t AESCTR00   : 32;           /*!< [31..0] bits 31:0 of AES_CTR0 register.                                   */
3686     } AESCTR00_b;
3687   } ;
3688 
3689   union {
3690     __IOM uint32_t AESCTR01;                    /*!< (@ 0x00000464) bits 63:32 of AES_CTR0 128b register.For the
3691                                                                     description of AES_CTR0, see the AES_CTR_0_0
3692                                                                     register description.                                      */
3693 
3694     struct {
3695       __IOM uint32_t AESCTR01   : 32;           /*!< [31..0] bits 63:32 of AES_CTR0 register.                                  */
3696     } AESCTR01_b;
3697   } ;
3698 
3699   union {
3700     __IOM uint32_t AESCTR02;                    /*!< (@ 0x00000468) bits 95:64 of AES_CTR0 128b register.For the
3701                                                                     description of AES_CTR0, see the AES_CTR_0_0
3702                                                                     register description.                                      */
3703 
3704     struct {
3705       __IOM uint32_t AESCTR02   : 32;           /*!< [31..0] bits 95:64 of AES_CTR0 register.                                  */
3706     } AESCTR02_b;
3707   } ;
3708 
3709   union {
3710     __IOM uint32_t AESCTR03;                    /*!< (@ 0x0000046C) bits 127:96 of AES_CTR0 128b register.For the
3711                                                                     description of AES_CTR0, see the AES_CTR_0_0
3712                                                                     register description.                                      */
3713 
3714     struct {
3715       __IOM uint32_t AESCTR03   : 32;           /*!< [31..0] bits 127:96 of AES_CTR0 register.                                 */
3716     } AESCTR03_b;
3717   } ;
3718 
3719   union {
3720     __IOM uint32_t AESBUSY;                     /*!< (@ 0x00000470) This register is set when the AES core is active           */
3721 
3722     struct {
3723       __IOM uint32_t AESBUSY    : 1;            /*!< [0..0] AES_BUSY register. This register is set when the AES
3724                                                      core is active                                                            */
3725             uint32_t            : 31;
3726     } AESBUSY_b;
3727   } ;
3728   __IM  uint32_t  RESERVED10;
3729 
3730   union {
3731     __IOM uint32_t AESSK;                       /*!< (@ 0x00000478) writing to this address causes sampling of the
3732                                                                     HW key to the AES_KEY0 register                            */
3733 
3734     struct {
3735       __IOM uint32_t AESSK      : 1;            /*!< [0..0] writing to this address causes sampling of the HW key
3736                                                      to the AES_KEY0 register                                                  */
3737             uint32_t            : 31;
3738     } AESSK_b;
3739   } ;
3740 
3741   union {
3742     __IOM uint32_t AESCMACINIT;                 /*!< (@ 0x0000047C) Writing to this address triggers the AES engine
3743                                                                     generating of K1 and K2 for AES CMAC operations.
3744                                                                     Note: This is a special register, affected
3745                                                                     by internal logic. Test result of this register
3746                                                                     is NA.                                                     */
3747 
3748     struct {
3749       __IOM uint32_t AESCMACINIT : 1;           /*!< [0..0] Writing to this address starts the generating of K1 and
3750                                                      K2 for AES CMAC operations                                                */
3751             uint32_t            : 31;
3752     } AESCMACINIT_b;
3753   } ;
3754   __IM  uint32_t  RESERVED11[13];
3755 
3756   union {
3757     __IOM uint32_t AESSK1;                      /*!< (@ 0x000004B4) writing to this address causes sampling of the
3758                                                                     HW key to the AES_KEY1 register                            */
3759 
3760     struct {
3761       __IOM uint32_t AESSK1     : 1;            /*!< [0..0] writing to this address causes sampling of the HW key
3762                                                      to the AES_KEY1 register                                                  */
3763             uint32_t            : 31;
3764     } AESSK1_b;
3765   } ;
3766   __IM  uint32_t  RESERVED12;
3767 
3768   union {
3769     __IOM uint32_t AESREMAININGBYTES;           /*!< (@ 0x000004BC) This register should be set with the amount of
3770                                                                     remaining bytes until the end of the current
3771                                                                     AES operation. The AES engine counts down
3772                                                                     from this value to determine the last _
3773                                                                     one before last blocks in AES CMAC, XTS
3774                                                                     AES and AES CCM.                                           */
3775 
3776     struct {
3777       __IOM uint32_t AESREMAININGBYTES : 32;    /*!< [31..0] This register should be set with the amount of remaining
3778                                                      bytes until the end of the current AES operation. The AES
3779                                                      engine counts down from this value to determine the last
3780                                                      _ one before last blocks in AES CMAC, XTS AES and AES CCM.                */
3781     } AESREMAININGBYTES_b;
3782   } ;
3783 
3784   union {
3785     __IOM uint32_t AESCONTROL;                  /*!< (@ 0x000004C0) This register holds the configuration of the
3786                                                                     AES engine. Note: This is a special register,
3787                                                                     affected by internal logic. Test result
3788                                                                     of this register is NA.                                    */
3789 
3790     struct {
3791       __IOM uint32_t DECKEY0    : 1;            /*!< [0..0] This field determines whether the AES performs Decrypt_Encrypt
3792                                                      operations, in non-tunneling operations:                                  */
3793       __IOM uint32_t MODE0ISCBCCTS : 1;         /*!< [1..1] If MODE_KEY0 is set to 3b001 (CBC), and this field is
3794                                                      set - the mode is CBC-CTS. In addition, If MODE_KEY0 is
3795                                                      set to 3b010 (CTR), and this field is set - the mode is
3796                                                      GCTR.                                                                     */
3797       __IOM uint32_t MODEKEY0   : 3;            /*!< [4..2] This field determines the AES mode in non tunneling operations,
3798                                                      and the AES mode of the first stage in tunneling operations:              */
3799       __IOM uint32_t MODEKEY1   : 3;            /*!< [7..5] This field determines the AES mode of the second stage
3800                                                      operation in tunneling operations:                                        */
3801       __IOM uint32_t CBCISESSIV : 1;            /*!< [8..8] If MODE_KEY0 is set to 3b001 (CBC), and this field is
3802                                                      set - the mode is CBC with ESSIV.                                         */
3803             uint32_t            : 1;
3804       __IOM uint32_t AESTUNNELISON : 1;         /*!< [10..10] This field determines whether the AES performs dual-tunnel
3805                                                      operations or standard non-tunneling operations:                          */
3806       __IOM uint32_t CBCISBITLOCKER : 1;        /*!< [11..11] If MODE_KEY0 is set to 3b001 (CBC), and this field
3807                                                      is set - the mode isBITLOCKER.                                            */
3808       __IOM uint32_t NKKEY0     : 2;            /*!< [13..12] This field determines the AES Key length in non tunneling
3809                                                      operations, and the AES key length of the first stage in
3810                                                      tunneling operations:                                                     */
3811       __IOM uint32_t NKKEY1     : 2;            /*!< [15..14] This field determines the AES key length of the second
3812                                                      stage operation in tunneling operations:                                  */
3813             uint32_t            : 6;
3814       __IOM uint32_t AESTUNNEL1DECRYPT : 1;     /*!< [22..22] This field determines whether the second tunnel stage
3815                                                      performs encrypt or decrypt operation :                                   */
3816       __IOM uint32_t AESTUNB1USESPADDEDDATAIN : 1;/*!< [23..23] This field determines, for tunneling operations, the
3817                                                      data that is fed to the second tunneling stage:                           */
3818       __IOM uint32_t AESTUNNEL0ENCRYPT : 1;     /*!< [24..24] This field determines whether the first tunnel stage
3819                                                      performs encrypt or decrypt operation :                                   */
3820       __IOM uint32_t AESOUTPUTMIDTUNNELDATA : 1;/*!< [25..25] This fields determines whether the AES output is the
3821                                                      result of the first or second tunneling stage:                            */
3822       __IOM uint32_t AESTUNNELB1PADEN : 1;      /*!< [26..26] This field determines whether the input data to the
3823                                                      second tunnel stage is padded with zeroes (according to
3824                                                      the remaining_bytes value) or not:                                        */
3825             uint32_t            : 1;
3826       __IOM uint32_t AESOUTMIDTUNTOHASH : 1;    /*!< [28..28] This field determines for AES-TO-HASH-AND-DOUT tunneling
3827                                                      operations, whether the AES outputs to the HASH the result
3828                                                      of the first or the second tunneling stage:                               */
3829       __IOM uint32_t AESXORCRYPTOKEY : 1;       /*!< [29..29] This field determines the value that is written to
3830                                                      AES_KEY0, when AES_SK is kicked:                                          */
3831             uint32_t            : 1;
3832       __IOM uint32_t DIRECTACCESS : 1;          /*!< [31..31] Using direct access and not the din-dout interface               */
3833     } AESCONTROL_b;
3834   } ;
3835   __IM  uint32_t  RESERVED13;
3836 
3837   union {
3838     __IOM uint32_t AESHWFLAGS;                  /*!< (@ 0x000004C8) This register holds the pre-synthesis HW flag
3839                                                                     configuration of the AES engine                            */
3840 
3841     struct {
3842       __IOM uint32_t SUPPORT256192KEY : 1;      /*!< [0..0] the SUPPORT_256_192_KEY flag                                       */
3843       __IOM uint32_t AESLARGERKEK : 1;          /*!< [1..1] the AES_LARGE_RKEK flag                                            */
3844       __IOM uint32_t DPACNTRMSREXIST : 1;       /*!< [2..2] the DPA_CNTRMSR_EXIST flag                                         */
3845       __IOM uint32_t CTREXIST   : 1;            /*!< [3..3] the CTR_EXIST flag                                                 */
3846       __IOM uint32_t ONLYENCRYPT : 1;           /*!< [4..4] the ONLY_ENCRYPT flag                                              */
3847       __IOM uint32_t USESBOXTABLE : 1;          /*!< [5..5] the USE_SBOX_TABLE flag                                            */
3848             uint32_t            : 2;
3849       __IOM uint32_t USE5SBOXES : 1;            /*!< [8..8] the USE_5_SBOXES flag                                              */
3850       __IOM uint32_t AESSUPPORTPREVIV : 1;      /*!< [9..9] the AES_SUPPORT_PREV_IV flag                                       */
3851       __IOM uint32_t aestunnelexists : 1;       /*!< [10..10] the aes_tunnel_exists flag                                       */
3852       __IOM uint32_t SECONDREGSSETEXIST : 1;    /*!< [11..11] the SECOND_REGS_SET_EXIST flag                                   */
3853       __IOM uint32_t DFACNTRMSREXIST : 1;       /*!< [12..12] the DFA_CNTRMSR_EXIST flag                                       */
3854             uint32_t            : 19;
3855     } AESHWFLAGS_b;
3856   } ;
3857   __IM  uint32_t  RESERVED14[3];
3858 
3859   union {
3860     __IOM uint32_t AESCTRNOINCREMENT;           /*!< (@ 0x000004D8) This register enables the AES CTR no increment
3861                                                                     mode (in which the counter mode is not incremented
3862                                                                     between 2 blocks)                                          */
3863 
3864     struct {
3865       __IOM uint32_t AESCTRNOINCREMENT : 1;     /*!< [0..0] This field enables the AES CTR 'no increment' mode (in
3866                                                      which the counter mode is not incremented between 2 blocks)               */
3867             uint32_t            : 31;
3868     } AESCTRNOINCREMENT_b;
3869   } ;
3870   __IM  uint32_t  RESERVED15[5];
3871 
3872   union {
3873     __IOM uint32_t AESDFAISON;                  /*!< (@ 0x000004F0) This register disable_enable the AES dfa. Note:
3874                                                                     This is a special register, affected by
3875                                                                     internal logic. Test result of this register
3876                                                                     is NA.                                                     */
3877 
3878     struct {
3879       __IOM uint32_t AESDFAISON : 1;            /*!< [0..0] writing to this register turns the DFA counter-measures
3880                                                      on. this register exists only if DFA countermeasures are
3881                                                      supported                                                                 */
3882             uint32_t            : 31;
3883     } AESDFAISON_b;
3884   } ;
3885   __IM  uint32_t  RESERVED16;
3886 
3887   union {
3888     __IOM uint32_t AESDFAERRSTATUS;             /*!< (@ 0x000004F8) dfa error status register.                                 */
3889 
3890     struct {
3891       __IOM uint32_t AESDFAERRSTATUS : 1;       /*!< [0..0] after a DFA violation this register is set and the AES
3892                                                      block is disabled) until the next reset. this register
3893                                                      only exists if DFA countermeasures is are supported                       */
3894             uint32_t            : 31;
3895     } AESDFAERRSTATUS_b;
3896   } ;
3897   __IM  uint32_t  RESERVED17[10];
3898 
3899   union {
3900     __IOM uint32_t AESCMACSIZE0KICK;            /*!< (@ 0x00000524) writing to this address triggers the AES engine
3901                                                                     to perform a CMAC operation with size 0.
3902                                                                     The CMAC result can be read from the AES_IV0
3903                                                                     register.                                                  */
3904 
3905     struct {
3906       __IOM uint32_t AESCMACSIZE0KICK : 1;      /*!< [0..0] writing to this address triggers the AES engine to perform
3907                                                      a CMAC operation with size 0. The CMAC result can be read
3908                                                      from the AES_IV0 register.                                                */
3909             uint32_t            : 31;
3910     } AESCMACSIZE0KICK_b;
3911   } ;
3912   __IM  uint32_t  RESERVED18[70];
3913 
3914   union {
3915     __IOM uint32_t HASHH0;                      /*!< (@ 0x00000640) H0 data. can only be written in the following
3916                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
3917                                                                     SHA384 SHA512                                              */
3918 
3919     struct {
3920       __IOM uint32_t HASHH0     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3921     } HASHH0_b;
3922   } ;
3923 
3924   union {
3925     __IOM uint32_t HASHH1;                      /*!< (@ 0x00000644) H1 data. can only be written in the following
3926                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
3927                                                                     SHA384 SHA512                                              */
3928 
3929     struct {
3930       __IOM uint32_t HASHH1     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3931     } HASHH1_b;
3932   } ;
3933 
3934   union {
3935     __IOM uint32_t HASHH2;                      /*!< (@ 0x00000648) H2 data. can only be written in the following
3936                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
3937                                                                     SHA384 SHA512                                              */
3938 
3939     struct {
3940       __IOM uint32_t HASHH2     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3941     } HASHH2_b;
3942   } ;
3943 
3944   union {
3945     __IOM uint32_t HASHH3;                      /*!< (@ 0x0000064C) H3 data. can only be written in the following
3946                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
3947                                                                     SHA384 SHA512                                              */
3948 
3949     struct {
3950       __IOM uint32_t HASHH3     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3951     } HASHH3_b;
3952   } ;
3953 
3954   union {
3955     __IOM uint32_t HASHH4;                      /*!< (@ 0x00000650) H4 data. can only be written in the following
3956                                                                     HASH_CONTROL modes: SHA1 SHA224 SHA256 SHA384
3957                                                                     SHA512                                                     */
3958 
3959     struct {
3960       __IOM uint32_t HASHH4     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3961     } HASHH4_b;
3962   } ;
3963 
3964   union {
3965     __IOM uint32_t HASHH5;                      /*!< (@ 0x00000654) H5 data. can only be written in the following
3966                                                                     HASH_CONTROL modes: SHA224 SHA256 SHA384
3967                                                                     SHA512                                                     */
3968 
3969     struct {
3970       __IOM uint32_t HASHH5     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3971     } HASHH5_b;
3972   } ;
3973 
3974   union {
3975     __IOM uint32_t HASHH6;                      /*!< (@ 0x00000658) H6 data. can only be written in the following
3976                                                                     HASH_CONTROL modes: SHA224 SHA256 SHA384
3977                                                                     SHA512                                                     */
3978 
3979     struct {
3980       __IOM uint32_t HASHH6     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3981     } HASHH6_b;
3982   } ;
3983 
3984   union {
3985     __IOM uint32_t HASHH7;                      /*!< (@ 0x0000065C) H7 data. can only be written in the following
3986                                                                     HASH_CONTROL modes: SHA224 SHA256 SHA384
3987                                                                     SHA512                                                     */
3988 
3989     struct {
3990       __IOM uint32_t HASHH7     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
3991     } HASHH7_b;
3992   } ;
3993 
3994   union {
3995     __IOM uint32_t HASHH8;                      /*!< (@ 0x00000660) H8 data. can only be written in the following
3996                                                                     HASH_CONTROL modes: SHA384 SHA512                          */
3997 
3998     struct {
3999       __IOM uint32_t HASHH8     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4000     } HASHH8_b;
4001   } ;
4002   __IM  uint32_t  RESERVED19[8];
4003 
4004   union {
4005     __IOM uint32_t AUTOHWPADDING;               /*!< (@ 0x00000684) HW padding automatically activated by engine.
4006                                                                     For the special case of ZERO bytes data
4007                                                                     vector this register should not be used!
4008                                                                     instead use HASH_PAD_CFG                                   */
4009 
4010     struct {
4011       __IOM uint32_t EN         : 1;            /*!< [0..0] 0x1 - Enable Automatic HW padding (No need for SW intervention
4012                                                      by writing PAD_CFG). Note: Not supported for 0 bytes !
4013                                                      Note: Disable this register when HASH op is done                          */
4014             uint32_t            : 31;
4015     } AUTOHWPADDING_b;
4016   } ;
4017 
4018   union {
4019     __IOM uint32_t HASHXORDIN;                  /*!< (@ 0x00000688) This register is always xored with the input
4020                                                                     to the hash engine,it should be 0 if xored
4021                                                                     is not reqiured .                                          */
4022 
4023     struct {
4024       __IOM uint32_t HASHXORDATA : 32;          /*!< [31..0] This register holds the value to be xor-ed with hash
4025                                                      input data.                                                               */
4026     } HASHXORDIN_b;
4027   } ;
4028   __IM  uint32_t  RESERVED20[2];
4029 
4030   union {
4031     __IOM uint32_t LOADINITSTATE;               /*!< (@ 0x00000694) Indication to HASH that the following data is
4032                                                                     to be loaded into initial value registers
4033                                                                     in HASH(H0:H15) or IV to AES MAC                           */
4034 
4035     struct {
4036       __IOM uint32_t LOAD       : 1;            /*!< [0..0] Load data to initial state registers. digest_iv for hash_aes_mac.
4037                                                      When done loading data this bit should be reset                           */
4038             uint32_t            : 31;
4039     } LOADINITSTATE_b;
4040   } ;
4041   __IM  uint32_t  RESERVED21[3];
4042 
4043   union {
4044     __IOM uint32_t HASHSELAESMAC;               /*!< (@ 0x000006A4) select the AES MAC module rather than the hash
4045                                                                     module                                                     */
4046 
4047     struct {
4048       __IOM uint32_t HASHSELAESMAC : 1;         /*!< [0..0] Hash or AES MAC module select.                                     */
4049       __IOM uint32_t GHASHSEL   : 1;            /*!< [1..1] GHASH select.                                                      */
4050             uint32_t            : 30;
4051     } HASHSELAESMAC_b;
4052   } ;
4053   __IM  uint32_t  RESERVED22[66];
4054 
4055   union {
4056     __IOM uint32_t HASHVERSION;                 /*!< (@ 0x000007B0) HASH VERSION Register                                      */
4057 
4058     struct {
4059       __IOM uint32_t FIXES      : 8;            /*!< [7..0] Fixes field.                                                       */
4060       __IOM uint32_t MINORVERSIONNUMBER : 4;    /*!< [11..8] minor version number                                              */
4061       __IOM uint32_t MAJORVERSIONNUMBER : 4;    /*!< [15..12] major version number                                             */
4062             uint32_t            : 16;
4063     } HASHVERSION_b;
4064   } ;
4065   __IM  uint32_t  RESERVED23[3];
4066 
4067   union {
4068     __IOM uint32_t HASHCONTROL;                 /*!< (@ 0x000007C0) Selects which HASH mode to run                             */
4069 
4070     struct {
4071       __IOM uint32_t MODE01     : 2;            /*!< [1..0] bits 1:0 of the HASH mode field. The hash mode field
4072                                                      possible values are:                                                      */
4073             uint32_t            : 1;
4074       __IOM uint32_t MODE3      : 1;            /*!< [3..3] bit 3 of the HASH mode field. The hash mode field possible
4075                                                      values are:4b0000 - MD5 if present 0x0001 SHA 1 4b0010
4076                                                      - SHA-256 4b1010 - SHA-224                                                */
4077             uint32_t            : 28;
4078     } HASHCONTROL_b;
4079   } ;
4080 
4081   union {
4082     __IOM uint32_t HASHPADEN;                   /*!< (@ 0x000007C4) Enables the hash hw padding.                               */
4083 
4084     struct {
4085       __IOM uint32_t EN         : 1;            /*!< [0..0] 0x1 : Enable generation of padding by HW Pad block. 0x0
4086                                                      : Disable generation of padding by HW Pad block.                          */
4087             uint32_t            : 31;
4088     } HASHPADEN_b;
4089   } ;
4090 
4091   union {
4092     __IOM uint32_t HASHPADCFG;                  /*!< (@ 0x000007C8) This is a special register, affected by internal
4093                                                                     logic. Test result of this register is NA.                 */
4094 
4095     struct {
4096             uint32_t            : 2;
4097       __IOM uint32_t DOPAD      : 1;            /*!< [2..2] Enable Padding generation. must be reset upon completion
4098                                                      of padding.                                                               */
4099             uint32_t            : 29;
4100     } HASHPADCFG_b;
4101   } ;
4102 
4103   union {
4104     __IOM uint32_t HASHCURLEN0;                 /*!< (@ 0x000007CC) This register holds the length of current hash
4105                                                                     operation bit 31:0.                                        */
4106 
4107     struct {
4108       __IOM uint32_t Length     : 32;           /*!< [31..0] Represent the current length of valid bits where digest
4109                                                      need to be computed In Bytes.                                             */
4110     } HASHCURLEN0_b;
4111   } ;
4112 
4113   union {
4114     __IOM uint32_t HASHCURLEN1;                 /*!< (@ 0x000007D0) This register holds the length of current hash
4115                                                                     operation bit 63:32.                                       */
4116 
4117     struct {
4118       __IOM uint32_t Length     : 32;           /*!< [31..0] Represent the current length of valid bits where digest
4119                                                      need to be computed In Bytes.                                             */
4120     } HASHCURLEN1_b;
4121   } ;
4122   __IM  uint32_t  RESERVED24[2];
4123 
4124   union {
4125     __IOM uint32_t HASHPARAM;                   /*!< (@ 0x000007DC) HASH_PARAM Register.                                       */
4126 
4127     struct {
4128       __IOM uint32_t CW         : 4;            /*!< [3..0] Indicates the number of concurrent words the hash is
4129                                                      using to compute signature. 1 - One concurrent w(t). 2
4130                                                      - Two concurrent w(t).                                                    */
4131       __IOM uint32_t CH         : 4;            /*!< [7..4] Indicate if Hi adders are present for each Hi value or
4132                                                      1 adder is shared for all Hi. 0 - One Hi value is updated
4133                                                      at a time 1 - All Hi values are updated at the same time.                 */
4134       __IOM uint32_t DW         : 4;            /*!< [11..8] Determine the granularity of word size. 0 - 32 bit word
4135                                                      data. 1 - 64 bit word data.                                               */
4136       __IOM uint32_t SHA512EXISTS : 1;          /*!< [12..12] Indicate if SHA-512 is present in the design. By default
4137                                                      SHA-1 and SHA-256 are present. 0 - SHA-1 and SHA-256 are
4138                                                      present only 1 - SHA-1 and all SHA-2 are present (SHA-256
4139                                                      SHA-512).                                                                 */
4140       __IOM uint32_t PADEXISTS  : 1;            /*!< [13..13] Indicate if pad block is present in the design. 0 -
4141                                                      pad function is not supported by hardware. 1 - pad function
4142                                                      is supported by hardware.                                                 */
4143       __IOM uint32_t MD5EXISTS  : 1;            /*!< [14..14] Indicate if MD5 is present in HW                                 */
4144       __IOM uint32_t HMACEXISTS : 1;            /*!< [15..15] Indicate if HMAC logic is present in the design                  */
4145       __IOM uint32_t SHA256EXISTS : 1;          /*!< [16..16] Indicate if SHA-256 is present in the design                     */
4146       __IOM uint32_t HASHCOMPAREEXISTS : 1;     /*!< [17..17] Indicate if COMPARE digest logic is present in the
4147                                                      design                                                                    */
4148       __IOM uint32_t DUMPHASHTODOUTEXISTS : 1;  /*!< [18..18] Indicate if HASH to dout is present in the design                */
4149             uint32_t            : 13;
4150     } HASHPARAM_b;
4151   } ;
4152   __IM  uint32_t  RESERVED25;
4153 
4154   union {
4155     __IOM uint32_t HASHAESSWRESET;              /*!< (@ 0x000007E4) Software reset of the AES.                                 */
4156 
4157     struct {
4158       __IOM uint32_t HASHAESSWRESET : 1;        /*!< [0..0] Hash receive reset internally.                                     */
4159             uint32_t            : 31;
4160     } HASHAESSWRESET_b;
4161   } ;
4162 
4163   union {
4164     __IOM uint32_t HASHENDIANESS;               /*!< (@ 0x000007E8) This register holds the HASH_ENDIANESS configuration.      */
4165 
4166     struct {
4167       __IOM uint32_t ENDIAN     : 1;            /*!< [0..0] The default value is little-endian. The data and generation
4168                                                      of padding can be swapped to be big-endian.                               */
4169             uint32_t            : 31;
4170     } HASHENDIANESS_b;
4171   } ;
4172   __IM  uint32_t  RESERVED26[9];
4173 
4174   union {
4175     __IOM uint32_t AESCLKENABLE;                /*!< (@ 0x00000810) This is a special register, affected by internal
4176                                                                     logic. Test result of this register is NA.                 */
4177 
4178     struct {
4179       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the AES clock.                                              */
4180             uint32_t            : 31;
4181     } AESCLKENABLE_b;
4182   } ;
4183   __IM  uint32_t  RESERVED27;
4184 
4185   union {
4186     __IOM uint32_t HASHCLKENABLE;               /*!< (@ 0x00000818) The HASH clock enable register. Note: This is
4187                                                                     a special register, affected by internal
4188                                                                     logic. Test result of this register is NA.                 */
4189 
4190     struct {
4191       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the hash clock.                                             */
4192             uint32_t            : 31;
4193     } HASHCLKENABLE_b;
4194   } ;
4195 
4196   union {
4197     __IOM uint32_t PKACLKENABLE;                /*!< (@ 0x0000081C) The PKA clock enable register. Note: This is
4198                                                                     a special register, affected by internal
4199                                                                     logic. Test result of this register is NA.                 */
4200 
4201     struct {
4202       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the PKA clock.                                              */
4203             uint32_t            : 31;
4204     } PKACLKENABLE_b;
4205   } ;
4206 
4207   union {
4208     __IOM uint32_t DMACLKENABLE;                /*!< (@ 0x00000820) DMA_CLK enable register. Note: This is a special
4209                                                                     register, affected by internal logic. Test
4210                                                                     result of this register is NA.                             */
4211 
4212     struct {
4213       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the DMA clock.                                              */
4214             uint32_t            : 31;
4215     } DMACLKENABLE_b;
4216   } ;
4217 
4218   union {
4219     __IOM uint32_t CLKSTATUS;                   /*!< (@ 0x00000824) The CryptoCell clocks status register. Note:
4220                                                                     This is a special register, affected by
4221                                                                     internal logic. Test result of this register
4222                                                                     is NA.                                                     */
4223 
4224     struct {
4225       __IOM uint32_t AESCLKSTATUS : 1;          /*!< [0..0] Status of AES clock enable.                                        */
4226             uint32_t            : 1;
4227       __IOM uint32_t HASHCLKSTATUS : 1;         /*!< [2..2] Status of HASH clock clock enable.                                 */
4228       __IOM uint32_t PKACLKSTATUS : 1;          /*!< [3..3] Status of PKA clock enable.                                        */
4229             uint32_t            : 3;
4230       __IOM uint32_t CHACHACLKSTATUS : 1;       /*!< [7..7] Status of CHACHA clock enable.                                     */
4231       __IOM uint32_t DMACLKSTATUS : 1;          /*!< [8..8] Status of DMA clock enable.                                        */
4232             uint32_t            : 23;
4233     } CLKSTATUS_b;
4234   } ;
4235   __IM  uint32_t  RESERVED28[12];
4236 
4237   union {
4238     __IOM uint32_t CHACHACLKENABLE;             /*!< (@ 0x00000858) CHACHA _SALSA clock enable register. Note: This
4239                                                                     is a special register, affected by internal
4240                                                                     logic. Test result of this register is NA.                 */
4241 
4242     struct {
4243       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the CHACHA SALSA clock enable.                              */
4244             uint32_t            : 31;
4245     } CHACHACLKENABLE_b;
4246   } ;
4247   __IM  uint32_t  RESERVED29[41];
4248 
4249   union {
4250     __IOM uint32_t CRYPTOCTL;                   /*!< (@ 0x00000900) Defines the cryptographic flow.                            */
4251 
4252     struct {
4253       __IOM uint32_t MODE       : 5;            /*!< [4..0] Determines the active cryptographic engine:                        */
4254             uint32_t            : 27;
4255     } CRYPTOCTL_b;
4256   } ;
4257   __IM  uint32_t  RESERVED30[3];
4258 
4259   union {
4260     __IOM uint32_t CRYPTOBUSY;                  /*!< (@ 0x00000910) This register is set when the cryptographic core
4261                                                                     is busy.                                                   */
4262 
4263     struct {
4264       __IOM uint32_t CRYPTOBUSY : 1;            /*!< [0..0] Crypto busy status.                                                */
4265             uint32_t            : 31;
4266     } CRYPTOBUSY_b;
4267   } ;
4268   __IM  uint32_t  RESERVED31[2];
4269 
4270   union {
4271     __IOM uint32_t HASHBUSY;                    /*!< (@ 0x0000091C) This register is set when the Hash engine is
4272                                                                     busy.                                                      */
4273 
4274     struct {
4275       __IOM uint32_t HASHBUSY   : 1;            /*!< [0..0] Hash busy status.                                                  */
4276             uint32_t            : 31;
4277     } HASHBUSY_b;
4278   } ;
4279   __IM  uint32_t  RESERVED32[4];
4280 
4281   union {
4282     __IOM uint32_t CONTEXTID;                   /*!< (@ 0x00000930) A general RD_WR register. For Firmware use.                */
4283 
4284     struct {
4285       __IOM uint32_t CONTEXTID  : 8;            /*!< [7..0] Context ID                                                         */
4286             uint32_t            : 24;
4287     } CONTEXTID_b;
4288   } ;
4289   __IM  uint32_t  RESERVED33[11];
4290 
4291   union {
4292     __IOM uint32_t GHASHSUBKEY00;               /*!< (@ 0x00000960) Bits 31:0 of GHASH Key0 (used as the GHASH module
4293                                                                     key).                                                      */
4294 
4295     struct {
4296       __IOM uint32_t GHASHSUBKEY00 : 32;        /*!< [31..0] Bits 31:0 of GHASH Key0.                                          */
4297     } GHASHSUBKEY00_b;
4298   } ;
4299 
4300   union {
4301     __IOM uint32_t GHASHSUBKEY01;               /*!< (@ 0x00000964) Bits 63:32 of GHASH Key0 (used as the GHASH module
4302                                                                     key).                                                      */
4303 
4304     struct {
4305       __IOM uint32_t GHASHSUBKEY01 : 32;        /*!< [31..0] Bits 63:32 of GHASH Key0.                                         */
4306     } GHASHSUBKEY01_b;
4307   } ;
4308 
4309   union {
4310     __IOM uint32_t GHASHSUBKEY02;               /*!< (@ 0x00000968) Bits 95:64 of GHASH Key0 (used as the GHASH module
4311                                                                     key).                                                      */
4312 
4313     struct {
4314       __IOM uint32_t GHASHSUBKEY02 : 32;        /*!< [31..0] Bits 95:64 of GHASH Key0.                                         */
4315     } GHASHSUBKEY02_b;
4316   } ;
4317 
4318   union {
4319     __IOM uint32_t GHASHSUBKEY03;               /*!< (@ 0x0000096C) Bits 127:96 of GHASH Key0 (used as the GHASH
4320                                                                     module key).                                               */
4321 
4322     struct {
4323       __IOM uint32_t GHASHSUBKEY03 : 32;        /*!< [31..0] Bits 127:96 of GHASH Key0.                                        */
4324     } GHASHSUBKEY03_b;
4325   } ;
4326 
4327   union {
4328     __IOM uint32_t GHASHIV00;                   /*!< (@ 0x00000970) Bits 31:0 of GHASH_IV0 register. GHASH IV0 is
4329                                                                     used as the GHASH IV (Initialization Value)
4330                                                                     register.                                                  */
4331 
4332     struct {
4333       __IOM uint32_t GHASHIV00  : 32;           /*!< [31..0] Bits 31:0 of GHASH_IV0 register of the GHASH module.
4334                                                      For the description of GHASH_IV0, see the GHASH_0_0 register
4335                                                      description                                                               */
4336     } GHASHIV00_b;
4337   } ;
4338 
4339   union {
4340     __IOM uint32_t GHASHIV01;                   /*!< (@ 0x00000974) Bits 63:32 of GHASH_IV0 register. GHASH IV0 is
4341                                                                     used as the GHASH IV (Initialization Value)
4342                                                                     register.                                                  */
4343 
4344     struct {
4345       __IOM uint32_t GHASHIV01  : 32;           /*!< [31..0] Bits 63:32 of GHASH_IV0 register of the GHASH module.             */
4346     } GHASHIV01_b;
4347   } ;
4348 
4349   union {
4350     __IOM uint32_t GHASHIV02;                   /*!< (@ 0x00000978) Bits 95:64 of GHASH_IV0 register. GHASH IV0 is
4351                                                                     used as the GHASH IV (Initialization Value)
4352                                                                     register.                                                  */
4353 
4354     struct {
4355       __IOM uint32_t GHASHIV02  : 32;           /*!< [31..0] Bits 95:64 of GHASH_IV0 register of the GHASH module.             */
4356     } GHASHIV02_b;
4357   } ;
4358 
4359   union {
4360     __IOM uint32_t GHASHIV03;                   /*!< (@ 0x0000097C) Bits 127:96 of GHASH_IV0 register.GHASH IV0 is
4361                                                                     used as the GHASH IV (Initialization Value)
4362                                                                     register.                                                  */
4363 
4364     struct {
4365       __IOM uint32_t GHASHIV03  : 32;           /*!< [31..0] Bits 127:96 of GHASH_IV0 register of the GHASH module.            */
4366     } GHASHIV03_b;
4367   } ;
4368 
4369   union {
4370     __IOM uint32_t GHASHBUSY;                   /*!< (@ 0x00000980) The GHASH module GHASH_BUSY Register. This register
4371                                                                     is set when the GHASH core is active.                      */
4372 
4373     struct {
4374       __IOM uint32_t GHASHBUSY  : 1;            /*!< [0..0] GHASH_BUSY Register. This register is set when the GHASH
4375                                                      core is active                                                            */
4376             uint32_t            : 31;
4377     } GHASHBUSY_b;
4378   } ;
4379 
4380   union {
4381     __IOM uint32_t GHASHINIT;                   /*!< (@ 0x00000984) Writing to this address sets the GHASH engine
4382                                                                     to be ready to a new GHASH operation.                      */
4383 
4384     struct {
4385       __IOM uint32_t GHASHINIT  : 1;            /*!< [0..0] Writing to this address sets the GHASH engine to be ready
4386                                                      to a new GHASH operation.                                                 */
4387             uint32_t            : 31;
4388     } GHASHINIT_b;
4389   } ;
4390   __IM  uint32_t  RESERVED34[30];
4391 
4392   union {
4393     __IOM uint32_t HOSTRGFIRR;                  /*!< (@ 0x00000A00) The Interrupt Request register. Each bit of this
4394                                                                     register holds the interrupt status of a
4395                                                                     single interrupt source.                                   */
4396 
4397     struct {
4398             uint32_t            : 4;
4399       __IOM uint32_t SRAMTODININT : 1;          /*!< [4..4] The SRAM to DIN DMA done interrupt status. This interrupt
4400                                                      is asserted when all data was delivered to DIN buffer from
4401                                                      SRAM.                                                                     */
4402       __IOM uint32_t DOUTTOSRAMINT : 1;         /*!< [5..5] The DOUT to SRAM DMA done interrupt status. This interrupt
4403                                                      is asserted when all data was delivered to SRAM buffer
4404                                                      from DOUT.                                                                */
4405       __IOM uint32_t MEMTODININT : 1;           /*!< [6..6] The memory to DIN DMA done interrupt status. This interrupt
4406                                                      is asserted when all data was delivered to DIN buffer from
4407                                                      memory.                                                                   */
4408       __IOM uint32_t DOUTTOMEMINT : 1;          /*!< [7..7] The DOUT to memory DMA done interrupt status. This interrupt
4409                                                      is asserted when all data was delivered to memory buffer
4410                                                      from DOUT.                                                                */
4411       __IOM uint32_t AHBERRINT  : 1;            /*!< [8..8] The AXI error interrupt status.                                    */
4412       __IOM uint32_t PKAEXPINT  : 1;            /*!< [9..9] The PKA end of operation interrupt status.                         */
4413       __IOM uint32_t RNGINT     : 1;            /*!< [10..10] The RNG interrupt status.                                        */
4414       __IOM uint32_t SYMDMACOMPLETED : 1;       /*!< [11..11] The GPR interrupt status.                                        */
4415             uint32_t            : 20;
4416     } HOSTRGFIRR_b;
4417   } ;
4418 
4419   union {
4420     __IOM uint32_t HOSTRGFIMR;                  /*!< (@ 0x00000A04) The Interrupt Mask register. Each bit of this
4421                                                                     register holds the mask of a single interrupt
4422                                                                     source.                                                    */
4423 
4424     struct {
4425             uint32_t            : 4;
4426       __IOM uint32_t SRAMTODINMASK : 1;         /*!< [4..4] The SRAM to DIN DMA done interrupt mask.                           */
4427       __IOM uint32_t DOUTTOSRAMMASK : 1;        /*!< [5..5] The DOUT to SRAM DMA done interrupt mask.                          */
4428       __IOM uint32_t MEMTODINMASK : 1;          /*!< [6..6] The memory to DIN DMA done interrupt mask.                         */
4429       __IOM uint32_t DOUTTOMEMMASK : 1;         /*!< [7..7] The DOUT to memory DMA done interrupt mask.                        */
4430       __IOM uint32_t AXIERRMASK : 1;            /*!< [8..8] The AXI error interrupt mask.                                      */
4431       __IOM uint32_t PKAEXPMASK : 1;            /*!< [9..9] The PKA end of operation interrupt mask.                           */
4432       __IOM uint32_t RNGINTMASK : 1;            /*!< [10..10] The RNG interrupt mask.                                          */
4433       __IOM uint32_t SYMDMACOMPLETEDMASK : 1;   /*!< [11..11] The GPR interrupt mask.                                          */
4434             uint32_t            : 20;
4435     } HOSTRGFIMR_b;
4436   } ;
4437 
4438   union {
4439     __IOM uint32_t HOSTRGFICR;                  /*!< (@ 0x00000A08) Interrupt Clear Register.                                  */
4440 
4441     struct {
4442             uint32_t            : 4;
4443       __IOM uint32_t SRAMTODINCLEAR : 1;        /*!< [4..4] The SRAM to DIN DMA done interrupt clear.                          */
4444       __IOM uint32_t DOUTTOSRAMCLEAR : 1;       /*!< [5..5] The DOUT to SRAM DMA done interrupt clear.                         */
4445       __IOM uint32_t MEMTODINCLEAR : 1;         /*!< [6..6] The memory to DIN DMA done interrupt clear.                        */
4446       __IOM uint32_t DOUTTOMEMCLEAR : 1;        /*!< [7..7] The DOUT to memory DMA done interrupt clear.                       */
4447       __IOM uint32_t AXIERRCLEAR : 1;           /*!< [8..8] The AXI error interrupt clear.                                     */
4448       __IOM uint32_t PKAEXPCLEAR : 1;           /*!< [9..9] The PKA end of operation interrupt clear.                          */
4449       __IOM uint32_t RNGINTCLEAR : 1;           /*!< [10..10] The RNG interrupt clear.                                         */
4450       __IOM uint32_t SYMDMACOMPLETEDCLEAR : 1;  /*!< [11..11] The GPR interrupt clear.                                         */
4451             uint32_t            : 20;
4452     } HOSTRGFICR_b;
4453   } ;
4454 
4455   union {
4456     __IOM uint32_t HOSTRGFENDIAN;               /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible
4457                                                                     registers. Note: This is a special register,
4458                                                                     affected by internal logic. Test result
4459                                                                     of this register is NA.                                    */
4460 
4461     struct {
4462             uint32_t            : 3;
4463       __IOM uint32_t DOUTWRBG   : 1;            /*!< [3..3] DOUT write endianness:                                             */
4464             uint32_t            : 3;
4465       __IOM uint32_t DINRDBG    : 1;            /*!< [7..7] DIN write endianness:                                              */
4466             uint32_t            : 3;
4467       __IOM uint32_t DOUTWRWBG  : 1;            /*!< [11..11] DOUT write word endianness:                                      */
4468             uint32_t            : 3;
4469       __IOM uint32_t DINRDWBG   : 1;            /*!< [15..15] DIN write word endianness:                                       */
4470             uint32_t            : 16;
4471     } HOSTRGFENDIAN_b;
4472   } ;
4473   __IM  uint32_t  RESERVED35[5];
4474 
4475   union {
4476     __IOM uint32_t HOSTRGFSIGNATURE;            /*!< (@ 0x00000A24) This register holds the CryptoCell product signature.      */
4477 
4478     struct {
4479       __IOM uint32_t HOSTSIGNATURE : 32;        /*!< [31..0] Identification 'signature': always returns a fixed value,
4480                                                      used by Host driver to verify CryptoCell presence at this
4481                                                      address.                                                                  */
4482     } HOSTRGFSIGNATURE_b;
4483   } ;
4484 
4485   union {
4486     __IOM uint32_t HOSTBOOT;                    /*!< (@ 0x00000A28) This register holds the values of CryptoCells
4487                                                                     pre-synthesis flags                                        */
4488 
4489     struct {
4490       __IOM uint32_t SYNTHESISCONFIG : 1;       /*!< [0..0] POWER_GATING_EXISTS_LOCAL                                          */
4491       __IOM uint32_t LARGERKEKLOCAL : 1;        /*!< [1..1] LARGE_RKEK_LOCAL                                                   */
4492       __IOM uint32_t HASHINFUSESLOCAL : 1;      /*!< [2..2] HASH_IN_FUSES_LOCAL                                                */
4493       __IOM uint32_t EXTMEMSECUREDLOCAL : 1;    /*!< [3..3] EXT_MEM_SECURED_LOCAL                                              */
4494             uint32_t            : 1;
4495       __IOM uint32_t RKEKECCEXISTSLOCALN : 1;   /*!< [5..5] RKEK_ECC_EXISTS_LOCAL_N                                            */
4496       __IOM uint32_t SRAMSIZELOCAL : 3;         /*!< [8..6] SRAM_SIZE_LOCAL                                                    */
4497       __IOM uint32_t DSCRPTREXISTSLOCAL : 1;    /*!< [9..9] DSCRPTR_EXISTS_LOCAL                                               */
4498       __IOM uint32_t PAUEXISTSLOCAL : 1;        /*!< [10..10] PAU_EXISTS_LOCAL                                                 */
4499       __IOM uint32_t RNGEXISTSLOCAL : 1;        /*!< [11..11] RNG_EXISTS_LOCAL                                                 */
4500       __IOM uint32_t PKAEXISTSLOCAL : 1;        /*!< [12..12] PKA_EXISTS_LOCAL                                                 */
4501       __IOM uint32_t RC4EXISTSLOCAL : 1;        /*!< [13..13] RC4_EXISTS_LOCAL                                                 */
4502       __IOM uint32_t SHA512PRSNTLOCAL : 1;      /*!< [14..14] SHA_512_PRSNT_LOCAL                                              */
4503       __IOM uint32_t SHA256PRSNTLOCAL : 1;      /*!< [15..15] SHA_256_PRSNT_LOCAL                                              */
4504       __IOM uint32_t MD5PRSNTLOCAL : 1;         /*!< [16..16] MD5_PRSNT_LOCAL                                                  */
4505       __IOM uint32_t HASHEXISTSLOCAL : 1;       /*!< [17..17] HASH_EXISTS_LOCAL                                                */
4506       __IOM uint32_t C2EXISTSLOCAL : 1;         /*!< [18..18] C2_EXISTS_LOCAL                                                  */
4507       __IOM uint32_t DESEXISTSLOCAL : 1;        /*!< [19..19] DES_EXISTS_LOCAL                                                 */
4508       __IOM uint32_t AESXCBCMACEXISTSLOCAL : 1; /*!< [20..20] AES_XCBC_MAC_EXISTS_LOCAL                                        */
4509       __IOM uint32_t AESCMACEXISTSLOCAL : 1;    /*!< [21..21] AES_CMAC_EXISTS_LOCAL                                            */
4510       __IOM uint32_t AESCCMEXISTSLOCAL : 1;     /*!< [22..22] AES_CCM_EXISTS_LOCAL                                             */
4511       __IOM uint32_t AESXEXHWTCALCLOCAL : 1;    /*!< [23..23] AES_XEX_HW_T_CALC_LOCAL                                          */
4512       __IOM uint32_t AESXEXEXISTSLOCAL : 1;     /*!< [24..24] AES_XEX_EXISTS_LOCAL                                             */
4513       __IOM uint32_t CTREXISTSLOCAL : 1;        /*!< [25..25] CTR_EXISTS_LOCAL                                                 */
4514       __IOM uint32_t AESDINBYTERESOLUTIONLOCAL : 1;/*!< [26..26] AES_DIN_BYTE_RESOLUTION_LOCAL                                 */
4515       __IOM uint32_t TUNNELINGENBLOCAL : 1;     /*!< [27..27] TUNNELING_ENB_LOCAL                                              */
4516       __IOM uint32_t SUPPORT256192KEYLOCAL : 1; /*!< [28..28] SUPPORT_256_192_KEY_LOCAL                                        */
4517       __IOM uint32_t ONLYENCRYPTLOCAL : 1;      /*!< [29..29] ONLY_ENCRYPT_LOCAL                                               */
4518       __IOM uint32_t AESEXISTSLOCAL : 1;        /*!< [30..30] AES_EXISTS_LOCAL                                                 */
4519             uint32_t            : 1;
4520     } HOSTBOOT_b;
4521   } ;
4522   __IM  uint32_t  RESERVED36[3];
4523 
4524   union {
4525     __IOM uint32_t HOSTCRYPTOKEYSEL;            /*!< (@ 0x00000A38) AES hardware key select. Note: This is a special
4526                                                                     register, affected by internal logic. Test
4527                                                                     result of this register is NA.                             */
4528 
4529     struct {
4530       __IOM uint32_t SELCRYPTOKEY : 3;          /*!< [2..0] Select the source of the HW key that is used by the AES
4531                                                      engine:                                                                   */
4532             uint32_t            : 29;
4533     } HOSTCRYPTOKEYSEL_b;
4534   } ;
4535   __IM  uint32_t  RESERVED37[15];
4536 
4537   union {
4538     __IOM uint32_t HOSTCORECLKGATINGENABLE;     /*!< (@ 0x00000A78) This register enables the core clk gating by
4539                                                                     masking_enabling the cc_idle_state output
4540                                                                     signal.                                                    */
4541 
4542     struct {
4543       __IOM uint32_t HOSTCORECLKGATINGENABLE : 1;/*!< [0..0] Enable the core clk gating,                                       */
4544             uint32_t            : 31;
4545     } HOSTCORECLKGATINGENABLE_b;
4546   } ;
4547 
4548   union {
4549     __IOM uint32_t HOSTCCISIDLE;                /*!< (@ 0x00000A7C) This register holds the idle indication of CC
4550                                                                     . Note: This is a special register, affected
4551                                                                     by internal logic. Test result of this register
4552                                                                     is NA.                                                     */
4553 
4554     struct {
4555       __IOM uint32_t HOSTCCISIDLE : 1;          /*!< [0..0] Read if CC is idle.                                                */
4556       __IOM uint32_t HOSTCCISIDLEEVENT : 1;     /*!< [1..1] The event that indicates that CC is idle.                          */
4557       __IOM uint32_t SYMISBUSY  : 1;            /*!< [2..2] symetric flow is busy                                              */
4558       __IOM uint32_t AHBISIDLE  : 1;            /*!< [3..3] ahb stste machine is idle                                          */
4559       __IOM uint32_t NVMARBISIDLE : 1;          /*!< [4..4] nvm arbiter is idle                                                */
4560       __IOM uint32_t NVMISIDLE  : 1;            /*!< [5..5] nvm is idle                                                        */
4561       __IOM uint32_t FATALWR    : 1;            /*!< [6..6] fatal write                                                        */
4562       __IOM uint32_t RNGISIDLE  : 1;            /*!< [7..7] rng is idle                                                        */
4563       __IOM uint32_t PKAISIDLE  : 1;            /*!< [8..8] pka is idle                                                        */
4564       __IOM uint32_t CRYPTOISIDLE : 1;          /*!< [9..9] crypto flow is done                                                */
4565             uint32_t            : 22;
4566     } HOSTCCISIDLE_b;
4567   } ;
4568 
4569   union {
4570     __IOM uint32_t HOSTPOWERDOWN;               /*!< (@ 0x00000A80) This register start the power-down sequence.
4571                                                                     Note: This is a special register, affected
4572                                                                     by internal logic. Test result of this register
4573                                                                     is NA.                                                     */
4574 
4575     struct {
4576       __IOM uint32_t HOSTPOWERDOWN : 1;         /*!< [0..0] Power down enable register.                                        */
4577             uint32_t            : 31;
4578     } HOSTPOWERDOWN_b;
4579   } ;
4580 
4581   union {
4582     __IOM uint32_t HOSTREMOVEGHASHENGINE;       /*!< (@ 0x00000A84) These inputs are to be statically tied to 0 or
4583                                                                     1 by the customers. When such an input is
4584                                                                     set, the matching engines inputs are tied
4585                                                                     to zero and its outputs are disconnected,
4586                                                                     so that the engine will be entirely removed
4587                                                                     by Synthesis                                               */
4588 
4589     struct {
4590       __IOM uint32_t HOSTREMOVEGHASHENGINE : 1; /*!< [0..0] Read the Remove_chacha_engine input                                */
4591             uint32_t            : 31;
4592     } HOSTREMOVEGHASHENGINE_b;
4593   } ;
4594 
4595   union {
4596     __IOM uint32_t HOSTREMOVECHACHAENGINE;      /*!< (@ 0x00000A88) These inputs are to be statically tied to 0 or
4597                                                                     1 by the customers. When such an input is
4598                                                                     set, the matching engines inputs are tied
4599                                                                     to zero and its outputs are disconnected,
4600                                                                     so that the engine will be entirely removed
4601                                                                     by Synthesis                                               */
4602 
4603     struct {
4604       __IOM uint32_t HOSTREMOVECHACHAENGINE : 1;/*!< [0..0] Read the Remove_ghash_engine input                                 */
4605             uint32_t            : 31;
4606     } HOSTREMOVECHACHAENGINE_b;
4607   } ;
4608   __IM  uint32_t  RESERVED38[29];
4609 
4610   union {
4611     __IOM uint32_t AHBMSINGLES;                 /*!< (@ 0x00000B00) This register forces the ahb transactions to
4612                                                                     be always singles.                                         */
4613 
4614     struct {
4615       __IOM uint32_t AHBSINGLES : 1;            /*!< [0..0] Force ahb singles                                                  */
4616             uint32_t            : 31;
4617     } AHBMSINGLES_b;
4618   } ;
4619 
4620   union {
4621     __IOM uint32_t AHBMHPROT;                   /*!< (@ 0x00000B04) This register holds the ahb prot value                     */
4622 
4623     struct {
4624       __IOM uint32_t AHBPROT    : 4;            /*!< [3..0] The ahb prot value                                                 */
4625             uint32_t            : 28;
4626     } AHBMHPROT_b;
4627   } ;
4628 
4629   union {
4630     __IOM uint32_t AHBMHMASTLOCK;               /*!< (@ 0x00000B08) This register holds ahb hmastlock value                    */
4631 
4632     struct {
4633       __IOM uint32_t AHBHMASTLOCK : 1;          /*!< [0..0] The hmastlock value.                                               */
4634             uint32_t            : 31;
4635     } AHBMHMASTLOCK_b;
4636   } ;
4637 
4638   union {
4639     __IOM uint32_t AHBMHNONSEC;                 /*!< (@ 0x00000B0C) This register holds ahb hnonsec value                      */
4640 
4641     struct {
4642       __IOM uint32_t AHBWRITEHNONSEC : 1;       /*!< [0..0] The hnonsec value for write transaction.                           */
4643       __IOM uint32_t AHBREADHNONSEC : 1;        /*!< [1..1] The hnonsec value for read transaction.                            */
4644             uint32_t            : 30;
4645     } AHBMHNONSEC_b;
4646   } ;
4647   __IM  uint32_t  RESERVED39[60];
4648 
4649   union {
4650     __IOM uint32_t DINBUFFER;                   /*!< (@ 0x00000C00) This address can be used by the CPU to write
4651                                                                     data directly to the DIN buffer to be sent
4652                                                                     to engines.                                                */
4653 
4654     struct {
4655       __IOM uint32_t DINBUFFERDATA : 32;        /*!< [31..0] This register is mapped into 8 addresses in order to
4656                                                      enable a CPU burst.                                                       */
4657     } DINBUFFER_b;
4658   } ;
4659   __IM  uint32_t  RESERVED40[7];
4660 
4661   union {
4662     __IOM uint32_t DINMEMDMABUSY;               /*!< (@ 0x00000C20) Indicates whether memory (AXI) source DMA (DIN)
4663                                                                     is busy.                                                   */
4664 
4665     struct {
4666       __IOM uint32_t DINMEMDMABUSY : 1;         /*!< [0..0] DIN memory DMA busy                                                */
4667             uint32_t            : 31;
4668     } DINMEMDMABUSY_b;
4669   } ;
4670   __IM  uint32_t  RESERVED41;
4671 
4672   union {
4673     __IOM uint32_t SRCLLIWORD0;                 /*!< (@ 0x00000C28) This register is used in direct LLI mode - holds
4674                                                                     the location of the data source in the memory
4675                                                                     (AXI).                                                     */
4676 
4677     struct {
4678       __IOM uint32_t SRCLLIWORD0 : 32;          /*!< [31..0] Source address within memory.                                     */
4679     } SRCLLIWORD0_b;
4680   } ;
4681 
4682   union {
4683     __IOM uint32_t SRCLLIWORD1;                 /*!< (@ 0x00000C2C) This register is used in direct LLI mode - holds
4684                                                                     the number of bytes to be read from the
4685                                                                     memory (AXI). Writing to this register triggers
4686                                                                     the DMA. Note: This is a special register,
4687                                                                     affected by internal logic. Test result
4688                                                                     of this register is NA.                                    */
4689 
4690     struct {
4691       __IOM uint32_t BYTESNUM   : 30;           /*!< [29..0] Total number of bytes to read using DMA in this entry             */
4692       __IOM uint32_t FIRST      : 1;            /*!< [30..30] 0x1 - Indicates the first LLI entry                              */
4693       __IOM uint32_t LAST       : 1;            /*!< [31..31] 0x1 - Indicates the last LLI entry                               */
4694     } SRCLLIWORD1_b;
4695   } ;
4696 
4697   union {
4698     __IOM uint32_t SRAMSRCADDR;                 /*!< (@ 0x00000C30) Location of data (start address) to be read from
4699                                                                     SRAM. Note: This is a special register,
4700                                                                     affected by internal logic. Test result
4701                                                                     of this register is NA.                                    */
4702 
4703     struct {
4704       __IOM uint32_t SRAMSOURCE : 32;           /*!< [31..0] SRAM source base address of data                                  */
4705     } SRAMSRCADDR_b;
4706   } ;
4707 
4708   union {
4709     __IOM uint32_t DINSRAMBYTESLEN;             /*!< (@ 0x00000C34) This register holds the size of the data (in
4710                                                                     bytes) to be read from the SRAM. Note: This
4711                                                                     is a special register, affected by internal
4712                                                                     logic. Test result of this register is NA.                 */
4713 
4714     struct {
4715       __IOM uint32_t BYTESLEN   : 32;           /*!< [31..0] Size of data to read from SRAM (bytes). This is the
4716                                                      trigger to the SRAM SRC DMA.                                              */
4717     } DINSRAMBYTESLEN_b;
4718   } ;
4719 
4720   union {
4721     __IOM uint32_t DINSRAMDMABUSY;              /*!< (@ 0x00000C38) This register holds the status of the SRAM DMA
4722                                                                     DIN.                                                       */
4723 
4724     struct {
4725       __IOM uint32_t BUSY       : 1;            /*!< [0..0] DIN SRAM DMA busy:                                                 */
4726             uint32_t            : 31;
4727     } DINSRAMDMABUSY_b;
4728   } ;
4729 
4730   union {
4731     __IOM uint32_t DINSRAMENDIANNESS;           /*!< (@ 0x00000C3C) This register defines the endianness of the DIN
4732                                                                     interface to SRAM.                                         */
4733 
4734     struct {
4735       __IOM uint32_t SRAMDINENDIANNESS : 1;     /*!< [0..0] Defines the endianness of DIN interface to SRAM:                   */
4736             uint32_t            : 31;
4737     } DINSRAMENDIANNESS_b;
4738   } ;
4739   __IM  uint32_t  RESERVED42[2];
4740 
4741   union {
4742     __IOM uint32_t DINCPUDATASIZE;              /*!< (@ 0x00000C48) This register hold the number of bytes to be
4743                                                                     transmited using external DMA. Note: This
4744                                                                     is a special register, affected by internal
4745                                                                     logic. Test result of this register is NA.                 */
4746 
4747     struct {
4748       __IOM uint32_t CPUDINSIZE : 16;           /*!< [15..0] When using external DMA, the size of transmited data
4749                                                      in bytes should be written to this register.                              */
4750             uint32_t            : 16;
4751     } DINCPUDATASIZE_b;
4752   } ;
4753   __IM  uint32_t  RESERVED43;
4754 
4755   union {
4756     __IOM uint32_t FIFOINEMPTY;                 /*!< (@ 0x00000C50) DIN FIFO empty indication                                  */
4757 
4758     struct {
4759       __IOM uint32_t EMPTY      : 1;            /*!< [0..0] 0x1 - FIFO empty                                                   */
4760             uint32_t            : 31;
4761     } FIFOINEMPTY_b;
4762   } ;
4763   __IM  uint32_t  RESERVED44;
4764 
4765   union {
4766     __IOM uint32_t DINFIFORSTPNTR;              /*!< (@ 0x00000C58) Writing to this register resets the DIN_FIFO
4767                                                                     pointers.                                                  */
4768 
4769     struct {
4770       __IOM uint32_t RST        : 1;            /*!< [0..0] Writing any value to this address resets the DIN_FIFO
4771                                                      pointers.                                                                 */
4772             uint32_t            : 31;
4773     } DINFIFORSTPNTR_b;
4774   } ;
4775   __IM  uint32_t  RESERVED45[41];
4776 
4777   union {
4778     __IOM uint32_t DOUTBUFFER;                  /*!< (@ 0x00000D00) Cryptographic result - CPU can directly access
4779                                                                     it. Note: This is a special register, affected
4780                                                                     by internal logic. Test result of this register
4781                                                                     is NA.                                                     */
4782 
4783     struct {
4784       __IOM uint32_t DATA       : 32;           /*!< [31..0] DOUT This address can be used by the CPU to read data
4785                                                      directly from the DOUT buffer.                                            */
4786     } DOUTBUFFER_b;
4787   } ;
4788   __IM  uint32_t  RESERVED46[7];
4789 
4790   union {
4791     __IOM uint32_t DOUTMEMDMABUSY;              /*!< (@ 0x00000D20) DOUT memory DMA busy - Indicates that memory
4792                                                                     (AXI) destination DMA (DOUT) is busy,                      */
4793 
4794     struct {
4795       __IOM uint32_t DOUTMEMDMABUSY : 1;        /*!< [0..0] DOUT memory DMA busy:                                              */
4796             uint32_t            : 31;
4797     } DOUTMEMDMABUSY_b;
4798   } ;
4799   __IM  uint32_t  RESERVED47;
4800 
4801   union {
4802     __IOM uint32_t DSTLLIWORD0;                 /*!< (@ 0x00000D28) This register is used in direct LLI mode - holds
4803                                                                     the location of the data destination in
4804                                                                     the memory (AXI)                                           */
4805 
4806     struct {
4807       __IOM uint32_t DSTLLIWORD0 : 32;          /*!< [31..0] Destination address within memory                                 */
4808     } DSTLLIWORD0_b;
4809   } ;
4810 
4811   union {
4812     __IOM uint32_t DSTLLIWORD1;                 /*!< (@ 0x00000D2C) This register is used in direct LLI mode - holds
4813                                                                     the number of bytes to be written to the
4814                                                                     memory (AXI). Note: This is a special register,
4815                                                                     affected by internal logic. Test result
4816                                                                     of this register is NA.                                    */
4817 
4818     struct {
4819       __IOM uint32_t BYTESNUM   : 30;           /*!< [29..0] Total byte number to be written by DMA in this entry              */
4820       __IOM uint32_t FIRST      : 1;            /*!< [30..30] 0x1 - Indicates the first LLI entry                              */
4821       __IOM uint32_t LAST       : 1;            /*!< [31..31] 0x1 - Indicates the last LLI entry                               */
4822     } DSTLLIWORD1_b;
4823   } ;
4824 
4825   union {
4826     __IOM uint32_t SRAMDESTADDR;                /*!< (@ 0x00000D30) Location of result to be sent to in SRAM. Note:
4827                                                                     This is a special register, affected by
4828                                                                     internal logic. Test result of this register
4829                                                                     is NA.                                                     */
4830 
4831     struct {
4832       __IOM uint32_t SRAMDEST   : 32;           /*!< [31..0] SRAM destination base address for data.                           */
4833     } SRAMDESTADDR_b;
4834   } ;
4835 
4836   union {
4837     __IOM uint32_t DOUTSRAMBYTESLEN;            /*!< (@ 0x00000D34) This register holds the size of the data (in
4838                                                                     bytes) to be written to the SRAM. Note:
4839                                                                     This is a special register, affected by
4840                                                                     internal logic. Test result of this register
4841                                                                     is NA.                                                     */
4842 
4843     struct {
4844       __IOM uint32_t BYTESLEN   : 32;           /*!< [31..0] Size of data to write to SRAM (bytes). This is the trigger
4845                                                      to the SRAM DST DMA.                                                      */
4846     } DOUTSRAMBYTESLEN_b;
4847   } ;
4848 
4849   union {
4850     __IOM uint32_t DOUTSRAMDMABUSY;             /*!< (@ 0x00000D38) This register holds the status of the SRAM DMA
4851                                                                     DOUT.                                                      */
4852 
4853     struct {
4854       __IOM uint32_t BUSY       : 1;            /*!< [0..0] DOUT SRAM DMA busy status.                                         */
4855             uint32_t            : 31;
4856     } DOUTSRAMDMABUSY_b;
4857   } ;
4858 
4859   union {
4860     __IOM uint32_t DOUTSRAMENDIANNESS;          /*!< (@ 0x00000D3C) This register defines the endianness of the DOUT
4861                                                                     interface from SRAM.                                       */
4862 
4863     struct {
4864       __IOM uint32_t DOUTSRAMENDIANNESS : 1;    /*!< [0..0] Defines the endianness of DOUT interface from SRAM:                */
4865             uint32_t            : 31;
4866     } DOUTSRAMENDIANNESS_b;
4867   } ;
4868   __IM  uint32_t  RESERVED48;
4869 
4870   union {
4871     __IOM uint32_t READALIGNLAST;               /*!< (@ 0x00000D44) Indication that the next read from the CPU is
4872                                                                     the last one. This is needed only when the
4873                                                                     data size is NOT modulo 4 (e.g. HASH padding).             */
4874 
4875     struct {
4876       __IOM uint32_t LAST       : 1;            /*!< [0..0] 0x1 - Flush the read aligner content (used for reading
4877                                                      the last data).                                                           */
4878             uint32_t            : 31;
4879     } READALIGNLAST_b;
4880   } ;
4881   __IM  uint32_t  RESERVED49[2];
4882 
4883   union {
4884     __IOM uint32_t DOUTFIFOEMPTY;               /*!< (@ 0x00000D50) DOUT_FIFO_EMPTY Register.                                  */
4885 
4886     struct {
4887       __IOM uint32_t DOUTFIFOEMPTY : 1;         /*!< [0..0] DOUT FIFO empty status.                                            */
4888             uint32_t            : 31;
4889     } DOUTFIFOEMPTY_b;
4890   } ;
4891   __IM  uint32_t  RESERVED50[107];
4892 
4893   union {
4894     __IOM uint32_t SRAMDATA;                    /*!< (@ 0x00000F00) READ WRITE DATA FROM SRAM. Note: This is a special
4895                                                                     register, affected by internal logic. Test
4896                                                                     result of this register is NA.                             */
4897 
4898     struct {
4899       __IOM uint32_t SRAMDATA   : 32;           /*!< [31..0] 32 bit write or read from SRAM: read - triggers the
4900                                                      SRAM read DMA address automatically incremented write -
4901                                                      triggers the SRAM write DMA address automatically incremented             */
4902     } SRAMDATA_b;
4903   } ;
4904 
4905   union {
4906     __IOM uint32_t SRAMADDR;                    /*!< (@ 0x00000F04) first address given to SRAM DMA for read_write
4907                                                                     transactions from SRAM                                     */
4908 
4909     struct {
4910       __IOM uint32_t SRAMADDR   : 15;           /*!< [14..0] SRAM starting address                                             */
4911             uint32_t            : 17;
4912     } SRAMADDR_b;
4913   } ;
4914 
4915   union {
4916     __IOM uint32_t SRAMDATAREADY;               /*!< (@ 0x00000F08) The SRAM content is ready for read in SRAM_DATA.           */
4917 
4918     struct {
4919       __IOM uint32_t SRAMREADY  : 1;            /*!< [0..0] SRAM content is ready for read in SRAM_DATA.                       */
4920             uint32_t            : 31;
4921     } SRAMDATAREADY_b;
4922   } ;
4923   __IM  uint32_t  RESERVED51[49];
4924 
4925   union {
4926     __IOM uint32_t PERIPHERALID4;               /*!< (@ 0x00000FD0) Peripheral ID 4 (PID4).                                    */
4927 
4928     struct {
4929       __IOM uint32_t DES2JEP106 : 4;            /*!< [3..0] for ARM products.                                                  */
4930             uint32_t            : 28;
4931     } PERIPHERALID4_b;
4932   } ;
4933   __IM  uint32_t  RESERVED52[3];
4934 
4935   union {
4936     __IOM uint32_t PERIPHERALID0;               /*!< (@ 0x00000FE0) Peripheral ID 0 (PID0).                                    */
4937 
4938     struct {
4939       __IOM uint32_t PART0      : 8;            /*!< [7..0] Identification register part number, bits[7:0]                     */
4940             uint32_t            : 24;
4941     } PERIPHERALID0_b;
4942   } ;
4943 
4944   union {
4945     __IOM uint32_t PERIPHERALID1;               /*!< (@ 0x00000FE4) Peripheral ID 1 (PID1).                                    */
4946 
4947     struct {
4948       __IOM uint32_t PART1      : 4;            /*!< [3..0] Identification register part number, bits[11:8]                    */
4949       __IOM uint32_t DES0JEP106 : 4;            /*!< [7..4] for ARM products.                                                  */
4950             uint32_t            : 24;
4951     } PERIPHERALID1_b;
4952   } ;
4953 
4954   union {
4955     __IOM uint32_t PERIPHERALID2;               /*!< (@ 0x00000FE8) Peripheral ID 2 (PID2).                                    */
4956 
4957     struct {
4958       __IOM uint32_t DES1JEP106 : 3;            /*!< [2..0] for ARM products.                                                  */
4959       __IOM uint32_t JEDEC      : 1;            /*!< [3..3] constant 0x1. Indicates that a JEDEC assigned value is
4960                                                      used.                                                                     */
4961       __IOM uint32_t REVISION   : 4;            /*!< [7..4] starts at zero and increments for every new IP release.            */
4962             uint32_t            : 24;
4963     } PERIPHERALID2_b;
4964   } ;
4965 
4966   union {
4967     __IOM uint32_t PERIPHERALID3;               /*!< (@ 0x00000FEC) Peripheral ID 3 (PID3).                                    */
4968 
4969     struct {
4970       __IOM uint32_t CMOD       : 4;            /*!< [3..0] Customer Modified, normally zero, but if a partner applies
4971                                                      any changes themselves, they must change this value.                      */
4972       __IOM uint32_t REVAND     : 4;            /*!< [7..4] starts at zero for every Revision, and increments if
4973                                                      metal fixes are applied between 2 IP releases.                            */
4974             uint32_t            : 24;
4975     } PERIPHERALID3_b;
4976   } ;
4977 
4978   union {
4979     __IOM uint32_t COMPONENTID0;                /*!< (@ 0x00000FF0) Component ID0.                                             */
4980 
4981     struct {
4982       __IOM uint32_t PRMBL0     : 8;            /*!< [7..0] constant 0xD                                                       */
4983             uint32_t            : 24;
4984     } COMPONENTID0_b;
4985   } ;
4986 
4987   union {
4988     __IOM uint32_t COMPONENTID1;                /*!< (@ 0x00000FF4) Component ID1.                                             */
4989 
4990     struct {
4991       __IOM uint32_t PRMBL1     : 4;            /*!< [3..0] constant 0x0                                                       */
4992       __IOM uint32_t CLASS      : 4;            /*!< [7..4] component type 0 0xF for Cryptocell                                */
4993             uint32_t            : 24;
4994     } COMPONENTID1_b;
4995   } ;
4996 
4997   union {
4998     __IOM uint32_t COMPONENTID2;                /*!< (@ 0x00000FF8) Component ID2.                                             */
4999 
5000     struct {
5001       __IOM uint32_t PRMBL2     : 8;            /*!< [7..0] constant 0x5                                                       */
5002             uint32_t            : 24;
5003     } COMPONENTID2_b;
5004   } ;
5005 
5006   union {
5007     __IOM uint32_t COMPONENTID3;                /*!< (@ 0x00000FFC) Component ID3.                                             */
5008 
5009     struct {
5010       __IOM uint32_t PRMBL3     : 8;            /*!< [7..0] constant 0xB1                                                      */
5011             uint32_t            : 24;
5012     } COMPONENTID3_b;
5013   } ;
5014   __IM  uint32_t  RESERVED53[896];
5015 
5016   union {
5017     __IOM uint32_t HOSTDCUEN0;                  /*!< (@ 0x00001E00) The DCU [31:0] enable register. Note: This is
5018                                                                     a special register, affected by internal
5019                                                                     logic. Test result of this register is NA.                 */
5020 
5021     struct {
5022       __IOM uint32_t HOSTDCUEN0 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5023     } HOSTDCUEN0_b;
5024   } ;
5025 
5026   union {
5027     __IOM uint32_t HOSTDCUEN1;                  /*!< (@ 0x00001E04) The DCU [63:32] enable register. Note: This is
5028                                                                     a special register, affected by internal
5029                                                                     logic. Test result of this register is NA.                 */
5030 
5031     struct {
5032       __IOM uint32_t HOSTDCUEN1 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5033     } HOSTDCUEN1_b;
5034   } ;
5035 
5036   union {
5037     __IOM uint32_t HOSTDCUEN2;                  /*!< (@ 0x00001E08) The DCU [95:64] enable register. Note: This is
5038                                                                     a special register, affected by internal
5039                                                                     logic. Test result of this register is NA.                 */
5040 
5041     struct {
5042       __IOM uint32_t HOSTDCUEN2 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5043     } HOSTDCUEN2_b;
5044   } ;
5045 
5046   union {
5047     __IOM uint32_t HOSTDCUEN3;                  /*!< (@ 0x00001E0C) The DCU [1271:96] enable register. Note: This
5048                                                                     is a special register, affected by internal
5049                                                                     logic. Test result of this register is NA.                 */
5050 
5051     struct {
5052       __IOM uint32_t HOSTDCUEN3 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5053     } HOSTDCUEN3_b;
5054   } ;
5055 
5056   union {
5057     __IOM uint32_t HOSTDCULOCK0;                /*!< (@ 0x00001E10) The DCU lock register. Note: This is a special
5058                                                                     register, affected by internal logic. Test
5059                                                                     result of this register is NA.                             */
5060 
5061     struct {
5062       __IOM uint32_t HOSTDCULOCK0 : 32;         /*!< [31..0] DCU_lock [31:0] register (a dedicated lock register
5063                                                      per DCU bit).                                                             */
5064     } HOSTDCULOCK0_b;
5065   } ;
5066 
5067   union {
5068     __IOM uint32_t HOSTDCULOCK1;                /*!< (@ 0x00001E14) The DCU lock register. Note: This is a special
5069                                                                     register, affected by internal logic. Test
5070                                                                     result of this register is NA.                             */
5071 
5072     struct {
5073       __IOM uint32_t HOSTDCULOCK1 : 32;         /*!< [31..0] DCU_lock [63:32] register (a dedicated lock register
5074                                                      per DCU bit).                                                             */
5075     } HOSTDCULOCK1_b;
5076   } ;
5077 
5078   union {
5079     __IOM uint32_t HOSTDCULOCK2;                /*!< (@ 0x00001E18) The DCU lock register. Note: This is a special
5080                                                                     register, affected by internal logic. Test
5081                                                                     result of this register is NA.                             */
5082 
5083     struct {
5084       __IOM uint32_t HOSTDCULOCK2 : 32;         /*!< [31..0] DCU_lock [95:64] register (a dedicated lock register
5085                                                      per DCU bit).                                                             */
5086     } HOSTDCULOCK2_b;
5087   } ;
5088 
5089   union {
5090     __IOM uint32_t HOSTDCULOCK3;                /*!< (@ 0x00001E1C) The DCU lock register. Note: This is a special
5091                                                                     register, affected by internal logic. Test
5092                                                                     result of this register is NA.                             */
5093 
5094     struct {
5095       __IOM uint32_t HOSTDCULOCK3 : 32;         /*!< [31..0] DCU_lock [127:96] register (a dedicated lock register
5096                                                      per DCU bit).                                                             */
5097     } HOSTDCULOCK3_b;
5098   } ;
5099 
5100   union {
5101     __IOM uint32_t AOICVDCURESTRICTIONMASK0;    /*!< (@ 0x00001E20) The DCU lock register.                                     */
5102 
5103     struct {
5104       __IOM uint32_t AOICVDCURESTRICTIONMASK0 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [31:0] parameter, that will
5105                                                      be a customer modifiable.                                                 */
5106     } AOICVDCURESTRICTIONMASK0_b;
5107   } ;
5108 
5109   union {
5110     __IOM uint32_t AOICVDCURESTRICTIONMASK1;    /*!< (@ 0x00001E24) The 'ICV_DCU_restriction_mask' parameter is read
5111                                                                     by FW during the secure debug verification
5112                                                                     to prevent OEM from setting specific DCUs
5113                                                                     that protect ICV secrets                                   */
5114 
5115     struct {
5116       __IOM uint32_t AOICVDCURESTRICTIONMASK1 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [63:32] parameter, that
5117                                                      will be a customer modifiable.                                            */
5118     } AOICVDCURESTRICTIONMASK1_b;
5119   } ;
5120 
5121   union {
5122     __IOM uint32_t AOICVDCURESTRICTIONMASK2;    /*!< (@ 0x00001E28) The 'ICV_DCU_restriction_mask' parameter is read
5123                                                                     by FW during the secure debug verification
5124                                                                     to prevent OEM from setting specific DCUs
5125                                                                     that protect ICV secrets                                   */
5126 
5127     struct {
5128       __IOM uint32_t AOICVDCURESTRICTIONMASK2 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [95:64] parameter, that
5129                                                      will be a customer modifiable.                                            */
5130     } AOICVDCURESTRICTIONMASK2_b;
5131   } ;
5132 
5133   union {
5134     __IOM uint32_t AOICVDCURESTRICTIONMASK3;    /*!< (@ 0x00001E2C) The 'ICV_DCU_restriction_mask' parameter is read
5135                                                                     by FW during the secure debug verification
5136                                                                     to prevent OEM from setting specific DCUs
5137                                                                     that protect ICV secrets                                   */
5138 
5139     struct {
5140       __IOM uint32_t AOICVDCURESTRICTIONMASK3 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [127:96] parameter, that
5141                                                      will be a customer modifiable.                                            */
5142     } AOICVDCURESTRICTIONMASK3_b;
5143   } ;
5144 
5145   union {
5146     __IOM uint32_t AOCCSECDEBUGRESET;           /*!< (@ 0x00001E30) The reset-upon-debug indication                            */
5147 
5148     struct {
5149       __IOM uint32_t AOCCSECDEBUGRESET : 1;     /*!< [0..0] For resets Cerberus, and prevents loading the HW keys
5150                                                      after that reset                                                          */
5151             uint32_t            : 31;
5152     } AOCCSECDEBUGRESET_b;
5153   } ;
5154 
5155   union {
5156     __IOM uint32_t HOSTAOLOCKBITS;              /*!< (@ 0x00001E34) These masks will define, per LCS, which DCU bits
5157                                                                     will be tied to zero, even if the Host tries
5158                                                                     to set them. Note: This is a special register,
5159                                                                     affected by internal logic. Test result
5160                                                                     of this register is NA.                                    */
5161 
5162     struct {
5163       __IOM uint32_t HOSTFATALERR : 1;          /*!< [0..0] When the 'FATAL_ERROR' register is asserted - HW keys
5164                                                      will not be copied from OTP                                               */
5165       __IOM uint32_t HOSTKPICVLOCK : 1;         /*!< [1..1] When this FW controlled register is set, the Kpicv HW
5166                                                      key is masked (to zero).                                                  */
5167       __IOM uint32_t HOSTKCEICVLOCK : 1;        /*!< [2..2] When this FW controlled register is set, the Kceicv HW
5168                                                      key is masked (to zero).                                                  */
5169       __IOM uint32_t HOSTKCPLOCK : 1;           /*!< [3..3] When this FW controlled register is set, the Kcp HW key
5170                                                      is masked (to zero).                                                      */
5171       __IOM uint32_t HOSTKCELOCK : 1;           /*!< [4..4] When this FW controlled register is set, the Kce HW key
5172                                                      is masked (to zero).                                                      */
5173       __IOM uint32_t HOSTICVRMALOCK : 1;        /*!< [5..5] The ICV_RMA_LOCK register is set-once (per POR).                   */
5174       __IOM uint32_t RESETUPONDEBUGDISABLE : 1; /*!< [6..6] The RESET_UPON_DEBUG_DISABLE register is set-once (per
5175                                                      POR).                                                                     */
5176       __IOM uint32_t HOSTFORCEDFAENABLE : 1;    /*!< [7..7] When this FW controlled register is set, the AES DFA
5177                                                      countermeasures are enabled_disabled (regardless of the
5178                                                      AES_DFA_IS_ON register value).                                            */
5179       __IOM uint32_t HOSTDFAENABLELOCK : 1;     /*!< [8..8] When this FW control is set, the DFA_ENABLE register
5180                                                      cant be written until the next POR. The DFA_ENABLE_LOCK
5181                                                      register is set-once (per POR).                                           */
5182             uint32_t            : 23;
5183     } HOSTAOLOCKBITS_b;
5184   } ;
5185 
5186   union {
5187     __IOM uint32_t AOAPBFILTERING;              /*!< (@ 0x00001E38) This register holds the AO_APB_FILTERING data.
5188                                                                     Note: This is a special register, affected
5189                                                                     by internal logic. Test result of this register
5190                                                                     is NA.                                                     */
5191 
5192     struct {
5193       __IOM uint32_t ONLYSECACCESSALLOW : 1;    /*!< [0..0] when this FW controlled register is set, the APB slave
5194                                                      accepts only secure accesses                                              */
5195       __IOM uint32_t ONLYSECACCESSALLOWLOCK : 1;/*!< [1..1] when this FW controlled register is set, the ONLY_SEC_ACCESS_ALLOWED
5196                                                      register cant be modified (until the next POR).                           */
5197       __IOM uint32_t ONLYPRIVACCESSALLOW : 1;   /*!< [2..2] when this FW controlled register is set, the APB slave
5198                                                      accepts only privileged accesses                                          */
5199       __IOM uint32_t ONLYPRIVACCESSALLOWLOCK : 1;/*!< [3..3] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO
5200                                                      ED register cant be modified (until the next POR)                         */
5201       __IOM uint32_t APBCONLYSECACCESSALLOW : 1;/*!< [4..4] when this FW controlled register is set, the APB-C slave
5202                                                      accepts only secure accesses                                              */
5203       __IOM uint32_t APBCONLYSECACCESSALLOWLOCK : 1;/*!< [5..5] when this FW controlled register is set, the APBC_ONLY_SEC_ACCESS_ALLOW
5204                                                      D register cant be modified (until the next POR).                         */
5205       __IOM uint32_t APBCONLYPRIVACCESSALLOW : 1;/*!< [6..6] when this FW controlled register is set, the APB-C slave
5206                                                      accepts only privileged accesses                                          */
5207       __IOM uint32_t APBCONLYPRIVACCESSALLOWLOCK : 1;/*!< [7..7] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO
5208                                                      ED register cant be modified (until the next POR)                         */
5209       __IOM uint32_t APBCONLYINSTACCESSALLOW : 1;/*!< [8..8] when this FW controlled register is set, the APB-C slave
5210                                                      accepts only instruction accesses                                         */
5211       __IOM uint32_t APBCONLYINSTACCESSALLOWLOCK : 1;/*!< [9..9] when this FW controlled register is set, the APBC_ONLY_INST_ACCESS_ALLO
5212                                                      ED register cant be modified (until the next POR)                         */
5213             uint32_t            : 22;
5214     } AOAPBFILTERING_b;
5215   } ;
5216 
5217   union {
5218     __IOM uint32_t AOCCGPPC;                    /*!< (@ 0x00001E3C) holds the AO_CC_GPPC value from AONote: This
5219                                                                     is a special register, affected by internal
5220                                                                     logic. Test result of this register is NA.                 */
5221 
5222     struct {
5223       __IOM uint32_t AOCCGPPC   : 8;            /*!< [7..0] The AO_CC_GPPC value                                               */
5224             uint32_t            : 24;
5225     } AOCCGPPC_b;
5226   } ;
5227 
5228   union {
5229     __IOM uint32_t HOSTRGFCCSWRST;              /*!< (@ 0x00001E40) Writing to this register generates a general
5230                                                                     reset to CryptoCell. This reset takes about
5231                                                                     4 core clock cycles.Note: This is a special
5232                                                                     register, affected by internal logic. Test
5233                                                                     result of this register is NA.                             */
5234 
5235     struct {
5236       __IOM uint32_t HOSTRGFCCSWRST : 1;        /*!< [0..0] Writing 1 to this field generates a general reset to
5237                                                      CryptoCell.                                                               */
5238             uint32_t            : 31;
5239     } HOSTRGFCCSWRST_b;
5240   } ;
5241   __IM  uint32_t  RESERVED54[48];
5242 
5243   union {
5244     __IOM uint32_t AIBFUSEPROGCOMPLETED;        /*!< (@ 0x00001F04) This register reflects the fuse_aib_prog_completed
5245                                                                     input, which indicates that the fuse programming
5246                                                                     was completed.Note: This is a special register,
5247                                                                     affected by internal logic. Test result
5248                                                                     of this register is NA.                                    */
5249 
5250     struct {
5251       __IOM uint32_t AIBFUSEPROGCOMPLETED : 1;  /*!< [0..0] Indicates if the fuse programming operation has been
5252                                                      completed.                                                                */
5253             uint32_t            : 31;
5254     } AIBFUSEPROGCOMPLETED_b;
5255   } ;
5256 
5257   union {
5258     __IOM uint32_t NVMDEBUGSTATUS;              /*!< (@ 0x00001F08) AIB debug status register. Note: This is a special
5259                                                                     register, affected by internal logic. Test
5260                                                                     result of this register is NA.                             */
5261 
5262     struct {
5263             uint32_t            : 1;
5264       __IOM uint32_t NVMSM      : 3;            /*!< [3..1] Main nvm fsm                                                       */
5265             uint32_t            : 28;
5266     } NVMDEBUGSTATUS_b;
5267   } ;
5268 
5269   union {
5270     __IOM uint32_t LCSISVALID;                  /*!< (@ 0x00001F0C) Indicates that the LCS register holds a valid
5271                                                                     value.Note: This is a special register,
5272                                                                     affected by internal logic. Test result
5273                                                                     of this register is NA.                                    */
5274 
5275     struct {
5276       __IOM uint32_t LCSISVALIDREG : 1;         /*!< [0..0] Indicates whether LCS is valid.                                    */
5277             uint32_t            : 31;
5278     } LCSISVALID_b;
5279   } ;
5280 
5281   union {
5282     __IOM uint32_t NVMISIDLE;                   /*!< (@ 0x00001F10) Indicates that the LCS register holds a valid
5283                                                                     value.Note: This is a special register,
5284                                                                     affected by internal logic. Test result
5285                                                                     of this register is NA.                                    */
5286 
5287     struct {
5288       __IOM uint32_t NVMISIDLEREG : 1;          /*!< [0..0] Indicates whether the NVM manager finishes its operation,
5289                                                      calculates the LCS, reads the HW keys, compares the number
5290                                                      of zeros and clears the keys                                              */
5291             uint32_t            : 31;
5292     } NVMISIDLE_b;
5293   } ;
5294 
5295   union {
5296     __IOM uint32_t LCSREG;                      /*!< (@ 0x00001F14) The lifecycle state register. Note: This is a
5297                                                                     special register, affected by internal logic.
5298                                                                     Test result of this register is NA.                        */
5299 
5300     struct {
5301       __IOM uint32_t LCSREG     : 3;            /*!< [2..0] Indicates the LCS (Lifecycle State) value.                         */
5302             uint32_t            : 5;
5303       __IOM uint32_t ERRORKDRZEROCNT : 1;       /*!< [8..8] Indication that the number of zeroes in the loaded KDR
5304                                                      is not equal to the value set in the manufacture flag.                    */
5305       __IOM uint32_t ERRORPROVZEROCNT : 1;      /*!< [9..9] Indication that the number of zeroes in the loaded KCP
5306                                                      is not equal to the value set in the OEM flag.                            */
5307       __IOM uint32_t ERRORKCEZEROCNT : 1;       /*!< [10..10] Indication that the number of zeroes in the loaded
5308                                                      KCE is not equal to the value set in the OEM flag.                        */
5309       __IOM uint32_t ERRORKPICVZEROCNT : 1;     /*!< [11..11] Indication that the number of zeroes in the loaded
5310                                                      KPICV is not equal to the value set in the manufacture
5311                                                      flag.                                                                     */
5312       __IOM uint32_t ERRORKCEICVZEROCNT : 1;    /*!< [12..12] Indication that the number of zeroes in the loaded
5313                                                      KCEICV is not equal to the value set in the manufacture
5314                                                      flag.                                                                     */
5315             uint32_t            : 19;
5316     } LCSREG_b;
5317   } ;
5318 
5319   union {
5320     __IOM uint32_t HOSTSHADOWKDRREG;            /*!< (@ 0x00001F18) This register interface is used to update the
5321                                                                     RKEK(KDR) registers when the device is in
5322                                                                     CM or DM mode , it is Write-once (per warm
5323                                                                     boot) in RMA LCS, The RKEK is updated by
5324                                                                     shifting .                                                 */
5325 
5326     struct {
5327       __IOM uint32_t HOSTSHADOWKDRREG : 1;      /*!< [0..0] This field is used to update the KDR registers when the
5328                                                      device is in CM , DM or RMA mode, The KDR is updated by
5329                                                      shifting .                                                                */
5330             uint32_t            : 31;
5331     } HOSTSHADOWKDRREG_b;
5332   } ;
5333 
5334   union {
5335     __IOM uint32_t HOSTSHADOWKCPREG;            /*!< (@ 0x00001F1C) This register interface is used to update the
5336                                                                     KCP registers when the device is in CM or
5337                                                                     DM mode, The KCP is updated by shifting                    */
5338 
5339     struct {
5340       __IOM uint32_t HOSTSHADOWKCPREG : 1;      /*!< [0..0] This field is used to update the KCP registers when the
5341                                                      device is in CM or DM mode, The KCP is updated by shifting                */
5342             uint32_t            : 31;
5343     } HOSTSHADOWKCPREG_b;
5344   } ;
5345 
5346   union {
5347     __IOM uint32_t HOSTSHADOWKCEREG;            /*!< (@ 0x00001F20) This register interface is used to update the
5348                                                                     KCE registers when the device is in CM or
5349                                                                     DM mode, The KCE is updated by shifting                    */
5350 
5351     struct {
5352       __IOM uint32_t HOSTSHADOWKCEREG : 1;      /*!< [0..0] This field is used to update the KCE registers when the
5353                                                      device is in CM or DM mode, The KCE is updated by shifting                */
5354             uint32_t            : 31;
5355     } HOSTSHADOWKCEREG_b;
5356   } ;
5357 
5358   union {
5359     __IOM uint32_t HOSTSHADOWKPICVREG;          /*!< (@ 0x00001F24) This register interface is used to update the
5360                                                                     KPICV registers when the device is in CM
5361                                                                     or DM mode, The KPICV is updated by shifting               */
5362 
5363     struct {
5364       __IOM uint32_t HOSTSHADOWKPICVREG : 1;    /*!< [0..0] This field is used to update the KPICV registers when
5365                                                      the device is in CM or DM mode, The KPICV is updated by
5366                                                      shifting                                                                  */
5367             uint32_t            : 31;
5368     } HOSTSHADOWKPICVREG_b;
5369   } ;
5370 
5371   union {
5372     __IOM uint32_t HOSTSHADOWKCEICVREG;         /*!< (@ 0x00001F28) This register interface is used to update the
5373                                                                     KCEICV registers when the device is in CM
5374                                                                     or DM mode, The KCEICV is updated by shifting              */
5375 
5376     struct {
5377       __IOM uint32_t HOSTSHADOWKCEICVREG : 1;   /*!< [0..0] This field is used to update the KCEICV registers when
5378                                                      the device is in CM or DM mode, The KCEICV is updated by
5379                                                      shifting                                                                  */
5380             uint32_t            : 31;
5381     } HOSTSHADOWKCEICVREG_b;
5382   } ;
5383 
5384   union {
5385     __IOM uint32_t OTPADDRWIDTHDEF;             /*!< (@ 0x00001F2C) OTP_ADDR_WIDTH parameter, that will define the
5386                                                                     integrated OTP address width (address in
5387                                                                     words). The supported sizes are 6 (for 2
5388                                                                     Kbits),7,8,9,11 (for 64 Kbits). The default
5389                                                                     value in the provided RTL will be 6.Note:
5390                                                                     This is a special register, affected by
5391                                                                     internal logic. Test result of this register
5392                                                                     is NA.                                                     */
5393 
5394     struct {
5395       __IOM uint32_t OTPADDRWIDTHDEF : 4;       /*!< [3..0] Holds the OTP_ADDR_WIDTH_DEF value.                                */
5396             uint32_t            : 28;
5397     } OTPADDRWIDTHDEF_b;
5398   } ;
5399 } CRYPTO_Type;                                  /*!< Size = 7984 (0x1f30)                                                      */
5400 
5401 
5402 
5403 /* =========================================================================================================================== */
5404 /* ================                                            DC                                             ================ */
5405 /* =========================================================================================================================== */
5406 
5407 
5408 /**
5409   * @brief Display Controller (DC)
5410   */
5411 
5412 typedef struct {                                /*!< (@ 0x400A0000) DC Structure                                               */
5413 
5414   union {
5415     __IOM uint32_t MODE;                        /*!< (@ 0x00000000) General control register that activates the NEMAp|dc400
5416                                                                     controller and various parameters, sets
5417                                                                     the timing signals' polarity, activates
5418                                                                     the global look-up table for gamma correction
5419                                                                     and chooses the output display formats to
5420                                                                     meet LCD color specifications.                             */
5421 
5422     struct {
5423       __IOM uint32_t TSTMODEN   : 1;            /*!< [0..0] When set to 1, test mode is enabled                                */
5424       __IOM uint32_t DBLHORSCANEN : 1;          /*!< [1..1] When set to 1, double horizontal scan is enabled                   */
5425       __IOM uint32_t LVDSINTEN  : 1;            /*!< [2..2] When set to 1, LVDS interface is enabled                           */
5426       __IOM uint32_t YUYVEN     : 1;            /*!< [3..3] When set to 1, the following output color formats are
5427                                                      enabled : Byte-3 beat Interface enabled, Byte-4 beat (RGBX)
5428                                                      Interface enabled, Two phase serial 12-bit enabled, YUYV
5429                                                      (16-bit mode) enabled, BT.656 enabled, JDI MIP enabled                    */
5430       __IOM uint32_t DBITYPEBEN : 1;            /*!< [4..4] When set to 1, DBI Type-B interface is enabled                     */
5431       __IOM uint32_t DISPFMT    : 4;            /*!< [8..5] Display data format                                                */
5432       __IOM uint32_t COLFMT     : 1;            /*!< [9..9] Output color format:                                               */
5433       __IOM uint32_t LVDSPADSEN : 1;            /*!< [10..10] When set to 1, LVDS output pads are enabled                      */
5434       __IOM uint32_t PLLCLKNDIV : 1;            /*!< [11..11] When set to 1, PLL_CLK is not divided                            */
5435       __IOM uint32_t RSVD0      : 5;            /*!< [16..12] This field is reserved.                                          */
5436       __IOM uint32_t FRAMEUPDTEN : 1;           /*!< [17..17] When set to 1, single frame update is enabled                    */
5437       __IOM uint32_t RSVD1      : 1;            /*!< [18..18] This field is reserved.                                          */
5438       __IOM uint32_t BLANKFRC   : 1;            /*!< [19..19] When set to 1, forces output to blank                            */
5439       __IOM uint32_t GAMARAMPEN : 1;            /*!< [20..20] When set to 1, gamma ramp is enabled                             */
5440       __IOM uint32_t RSVD2      : 1;            /*!< [21..21] This field is reserved.                                          */
5441       __IOM uint32_t PIXCLKPOL  : 1;            /*!< [22..22] Defines Pixel Clock out polarity                                 */
5442       __IOM uint32_t VSYNCEN    : 1;            /*!< [23..23] When set to 1, VSYNC for a single cycle per line is
5443                                                      enabled                                                                   */
5444       __IOM uint32_t DITHEREN   : 1;            /*!< [24..24] When set to 1, dithering is enabled                              */
5445       __IOM uint32_t RSVD3      : 1;            /*!< [25..25] This field is reserved.                                          */
5446       __IOM uint32_t DEPOL      : 1;            /*!< [26..26] Defines DE polarity                                              */
5447       __IOM uint32_t HSYNCPOL   : 1;            /*!< [27..27] Defines HSYNC polarity                                           */
5448       __IOM uint32_t VSYNCPOL   : 1;            /*!< [28..28] Defines VSYNC polarity                                           */
5449       __IOM uint32_t RSVD4      : 1;            /*!< [29..29] This field is reserved.                                          */
5450       __IOM uint32_t CUSOREN    : 1;            /*!< [30..30] When set to 1, programmable cursor is enabled                    */
5451       __IOM uint32_t DC400ACT   : 1;            /*!< [31..31] When set to 1, the dc400 controller is activated                 */
5452     } MODE_b;
5453   } ;
5454 
5455   union {
5456     __IOM uint32_t CLKCTRL;                     /*!< (@ 0x00000004) Setup proper timing with divisor control bits
5457                                                                     and specify the number of lines to be prefetched
5458                                                                     before the start of frame.                                 */
5459 
5460     struct {
5461       __IOM uint32_t DIVIDEVALUE : 6;           /*!< [5..0] Value of first clock divider                                       */
5462       __IOM uint32_t RSVD0      : 2;            /*!< [7..6] This field is reserved.                                            */
5463       __IOM uint32_t LINENUM    : 6;            /*!< [13..8] Number of lines to be prefetched before starting the
5464                                                      frame through DMA. Maximum value is 32                                    */
5465       __IOM uint32_t RSVD1      : 2;            /*!< [15..14] This field is reserved.                                          */
5466       __IOM uint32_t PLL        : 8;            /*!< [23..16] Select PLL Clock                                                 */
5467       __IOM uint32_t LVDS       : 3;            /*!< [26..24] Clock phase shift value for LVDS operation                       */
5468       __IOM uint32_t SECCLKDIV  : 5;            /*!< [31..27] Value of secondary clock divider                                 */
5469     } CLKCTRL_b;
5470   } ;
5471 
5472   union {
5473     __IOM uint32_t BGCOLOR;                     /*!< (@ 0x00000008) Specifies the main background color.                       */
5474 
5475     struct {
5476       __IOM uint32_t ALPHACOLOR : 8;            /*!< [7..0] Color alpha is used as background color                            */
5477       __IOM uint32_t BLUECOLOR  : 8;            /*!< [15..8] Color blue is used as background color                            */
5478       __IOM uint32_t GREENCOLOR : 8;            /*!< [23..16] Color green is used as background color                          */
5479       __IOM uint32_t REDCOLOR   : 8;            /*!< [31..24] Color red is used as background color                            */
5480     } BGCOLOR_b;
5481   } ;
5482 
5483   union {
5484     __IOM uint32_t RESXY;                       /*!< (@ 0x0000000C) Specifies the main X and Y resolutions.                    */
5485 
5486     struct {
5487       __IOM uint32_t YRES       : 16;           /*!< [15..0] Value of Y resolution in pixels                                   */
5488       __IOM uint32_t XRES       : 16;           /*!< [31..16] Value of X resolution in pixels                                  */
5489     } RESXY_b;
5490   } ;
5491   __IM  uint32_t  RESERVED;
5492 
5493   union {
5494     __IOM uint32_t FRONTPORCHXY;                /*!< (@ 0x00000014) Specifies the X and Y dimensions for the Front
5495                                                                     Porch.                                                     */
5496 
5497     struct {
5498       __IOM uint32_t FLINES     : 16;           /*!< [15..0] Specify the number of lines for the front porch Y dimension       */
5499       __IOM uint32_t FPCLKCYCLES : 16;          /*!< [31..16] Specify the pixel clock cycles for the front porch
5500                                                      X dimension                                                               */
5501     } FRONTPORCHXY_b;
5502   } ;
5503 
5504   union {
5505     __IOM uint32_t BLANKINGXY;                  /*!< (@ 0x00000018) Specifies the X and Y dimensions for the Blanking
5506                                                                     Period.                                                    */
5507 
5508     struct {
5509       __IOM uint32_t VSYNCLINES : 16;           /*!< [15..0] Specify the VSYNC lines for the Y dimension blanking
5510                                                      period                                                                    */
5511       __IOM uint32_t HSYNCPULSE : 16;           /*!< [31..16] Specify the HSYNC pulse length for the X dimension
5512                                                      blanking period                                                           */
5513     } BLANKINGXY_b;
5514   } ;
5515 
5516   union {
5517     __IOM uint32_t BACKPORCHXY;                 /*!< (@ 0x0000001C) Specifies the X and Y dimensions for the Back
5518                                                                     Porch.                                                     */
5519 
5520     struct {
5521       __IOM uint32_t BLINES     : 16;           /*!< [15..0] Specify the number of lines for the back porch Y dimension        */
5522       __IOM uint32_t BPCLKCYCLES : 16;          /*!< [31..16] Specify the pixel clock cycles for the back porch X
5523                                                      dimension                                                                 */
5524     } BACKPORCHXY_b;
5525   } ;
5526 
5527   union {
5528     __IOM uint32_t CURSORXY;                    /*!< (@ 0x00000020) Specifies the cursor's start X and Y coordinates.          */
5529 
5530     struct {
5531       __IOM uint32_t CURSORY    : 16;           /*!< [15..0] Specify cursor's Y dimension                                      */
5532       __IOM uint32_t CURSORX    : 16;           /*!< [31..16] Specify cursor's X dimension                                     */
5533     } CURSORXY_b;
5534   } ;
5535   __IM  uint32_t  RESERVED1;
5536 
5537   union {
5538     __IOM uint32_t DBICFG;                      /*!< (@ 0x00000028) Register for the configuration DBI Type-B interface
5539                                                                     and the activation of SPI 3-/4-wire interfaces.            */
5540 
5541     struct {
5542       __IOM uint32_t DBICOLORFMT : 3;           /*!< [2..0] Set the color format for DBI interface                             */
5543       __IOM uint32_t DATAWDORDER : 3;           /*!< [5..3] Set the data order of the 8-bit data word:                         */
5544       __IOM uint32_t TYPEBWIDTH : 2;            /*!< [7..6] Set DBI Type-B interface width (8, 9 or 16 bits) and
5545                                                      the serial interface:                                                     */
5546       __IOM uint32_t RSVD0      : 3;            /*!< [10..8] This field is reserved.                                           */
5547       __IOM uint32_t BACKPRESSUREEN : 1;        /*!< [11..11] When set to 1, back pressure support is enabled (not
5548                                                      currently supported)                                                      */
5549       __IOM uint32_t RSVD1      : 4;            /*!< [15..12] This field is reserved.                                          */
5550       __IOM uint32_t INVHRZLINE : 1;            /*!< [16..16] When set to 1, inverts the bit-order of the horizontal
5551                                                      line address (used along with DBI_CFG[17] register bit)                   */
5552       __IOM uint32_t BINDCMDS   : 1;            /*!< [17..17] When set to 1, binds the store commands with the RGB
5553                                                      data and two-byte address is sent with each horizontal
5554                                                      line                                                                      */
5555       __IOM uint32_t RSVD2      : 4;            /*!< [21..18] This field is reserved.                                          */
5556       __IOM uint32_t SPI4       : 1;            /*!< [22..22] When set to 1, SPI 4-wire interface is enabled                   */
5557       __IOM uint32_t SPI3       : 1;            /*!< [23..23] When set to 1, SPI 3-wire interface is enabled                   */
5558       __IOM uint32_t RSVD3      : 1;            /*!< [24..24] This field is reserved.                                          */
5559       __IOM uint32_t RESXLOW    : 1;            /*!< [25..25] When set to 1, drives RESX signal low to reset DBI
5560                                                      Type-B interface                                                          */
5561       __IOM uint32_t RSVD4      : 2;            /*!< [27..26] This field is reserved.                                          */
5562       __IOM uint32_t DBIBTEDIS  : 1;            /*!< [28..28] When set to 1, the DBIB_TE signal is disabled                    */
5563       __IOM uint32_t CSXSET     : 1;            /*!< [29..29] Sets the value of DBIB_CSX signal:                               */
5564       __IOM uint32_t CSXCFG     : 1;            /*!< [30..30] When set to 1, the value of the CSX signal of the DBI
5565                                                      interface can be configured from the DBI_CFG[29] register
5566                                                      bit                                                                       */
5567       __IOM uint32_t DBIINTACT  : 1;            /*!< [31..31] When set to 1, the DBI interface is activated                    */
5568     } DBICFG_b;
5569   } ;
5570 
5571   union {
5572     __IOM uint32_t DCGPIO;                      /*!< (@ 0x0000002C) General Purpose register: read/write GPIO external
5573                                                                     pins. This is accumulated as- {CGBYPASS_in,13'd0,ADVANCE_A
5574                                                                     YWAY_in,5'd0,GPIO_in}                                      */
5575 
5576     struct {
5577       __IOM uint32_t RWPINS     : 2;            /*!< [1..0] These are not implemented                                          */
5578       __IOM uint32_t RSVD0      : 5;            /*!< [6..2] This field is reserved.                                            */
5579       __IOM uint32_t ADVANCEANYWAY : 2;         /*!< [8..7] No idea what this is                                               */
5580       __IOM uint32_t RSVD1      : 13;           /*!< [21..9] This field is reserved.                                           */
5581       __IOM uint32_t CGBYPASS   : 10;           /*!< [31..22] No idea what this is                                             */
5582     } DCGPIO_b;
5583   } ;
5584 
5585   union {
5586     __IOM uint32_t LAYER0MODE;                  /*!< (@ 0x00000030) LAYER0_MODE: Activate and set-up layer 0.                  */
5587 
5588     struct {
5589       __IOM uint32_t LAYER0COLMODE : 5;         /*!< [4..0] Color mode                                                         */
5590       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5591       __IOM uint32_t LAYER0SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5592       __IOM uint32_t LAYER0DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5593       __IOM uint32_t LAYER0ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5594       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5595       __IOM uint32_t LAYER0GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5596       __IOM uint32_t LAYER0HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5597       __IOM uint32_t LAYER0PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5598       __IOM uint32_t LAYER0BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5599       __IOM uint32_t LAYER0FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5600       __IOM uint32_t LAYER0EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5601     } LAYER0MODE_b;
5602   } ;
5603 
5604   union {
5605     __IOM uint32_t LAYER0STARTXY;               /*!< (@ 0x00000034) X and Y start dimensions of layer 0.                       */
5606 
5607     struct {
5608       __IOM uint32_t LAYER0YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5609                                                      of layer 0                                                                */
5610       __IOM uint32_t LAYER0XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5611                                                      of layer 0                                                                */
5612     } LAYER0STARTXY_b;
5613   } ;
5614 
5615   union {
5616     __IOM uint32_t LAYER0SIZEXY;                /*!< (@ 0x00000038) X and Y size of layer 0.                                   */
5617 
5618     struct {
5619       __IOM uint32_t LAYER0PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 0 in the Y dimension          */
5620       __IOM uint32_t LAYER0PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 0 in the X dimension         */
5621     } LAYER0SIZEXY_b;
5622   } ;
5623 
5624   union {
5625     __IOM uint32_t LAYER0ADDR;                  /*!< (@ 0x0000003C) The start address of the framebuffer to be accessed
5626                                                                     by layer 0.                                                */
5627 
5628     struct {
5629       __IOM uint32_t LAYER0STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
5630                                                      0.                                                                        */
5631     } LAYER0ADDR_b;
5632   } ;
5633 
5634   union {
5635     __IOM uint32_t LAYER0STRIDE;                /*!< (@ 0x00000040) Specify the stride and the AXI bus burst of layer
5636                                                                     0.                                                         */
5637 
5638     struct {
5639       __IOM uint32_t LAYER0STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
5640                                                      to line in bytes for each layer 0 memory                                  */
5641       __IOM uint32_t LAYER0AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 0                        */
5642       __IOM uint32_t LAYER0AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
5643                                                      0                                                                         */
5644       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
5645     } LAYER0STRIDE_b;
5646   } ;
5647 
5648   union {
5649     __IOM uint32_t LAYER0RESXY;                 /*!< (@ 0x00000044) X and Y dimensions for the resolution of layer
5650                                                                     0.                                                         */
5651 
5652     struct {
5653       __IOM uint32_t LAYER0PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
5654       __IOM uint32_t LAYER0PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
5655     } LAYER0RESXY_b;
5656   } ;
5657 
5658   union {
5659     __IOM uint32_t LAYER0SCALEX;                /*!< (@ 0x00000048) Scale X factor of layer 0.                                 */
5660 
5661     struct {
5662       __IOM uint32_t LAYER0XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
5663                                                      number)                                                                   */
5664     } LAYER0SCALEX_b;
5665   } ;
5666 
5667   union {
5668     __IOM uint32_t LAYER0SCALEY;                /*!< (@ 0x0000004C) Scale Y factor of layer 0.                                 */
5669 
5670     struct {
5671       __IOM uint32_t LAYER0YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
5672                                                      number)                                                                   */
5673     } LAYER0SCALEY_b;
5674   } ;
5675 
5676   union {
5677     __IOM uint32_t LAYER1MODE;                  /*!< (@ 0x00000050) Activate and set-up layer 1.                               */
5678 
5679     struct {
5680       __IOM uint32_t LAYER1COLORMODE : 5;       /*!< [4..0] Color mode                                                         */
5681       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5682       __IOM uint32_t LAYER1SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5683       __IOM uint32_t LAYER1DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5684       __IOM uint32_t LAYER1ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5685       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5686       __IOM uint32_t LAYER1GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5687       __IOM uint32_t LAYER1HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5688       __IOM uint32_t LAYER1PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5689       __IOM uint32_t LAYER1BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5690       __IOM uint32_t LAYER1FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5691       __IOM uint32_t LAYER1EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5692     } LAYER1MODE_b;
5693   } ;
5694 
5695   union {
5696     __IOM uint32_t LAYER1STARTXY;               /*!< (@ 0x00000054) X and Y start dimensions of layer 1.                       */
5697 
5698     struct {
5699       __IOM uint32_t LAYER1YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5700                                                      of layer 1                                                                */
5701       __IOM uint32_t LAYER1XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5702                                                      of layer 1                                                                */
5703     } LAYER1STARTXY_b;
5704   } ;
5705 
5706   union {
5707     __IOM uint32_t LAYER1SIZEXY;                /*!< (@ 0x00000058) X and Y size of layer 1.                                   */
5708 
5709     struct {
5710       __IOM uint32_t LAYER1PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 1 in the Y dimension          */
5711       __IOM uint32_t LAYER1PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 1 in the X dimension         */
5712     } LAYER1SIZEXY_b;
5713   } ;
5714 
5715   union {
5716     __IOM uint32_t LAYER1ADDR;                  /*!< (@ 0x0000005C) The start address of the framebuffer to be accessed
5717                                                                     by layer 1.                                                */
5718 
5719     struct {
5720       __IOM uint32_t LAYER1STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
5721                                                      1.                                                                        */
5722     } LAYER1ADDR_b;
5723   } ;
5724 
5725   union {
5726     __IOM uint32_t LAYER1STRIDE;                /*!< (@ 0x00000060) Specify the stride and the AXI bus burst of layer
5727                                                                     1.                                                         */
5728 
5729     struct {
5730       __IOM uint32_t LAYER1STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
5731                                                      to line in bytes for each layer 1 memory                                  */
5732       __IOM uint32_t LAYER1AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 1                        */
5733       __IOM uint32_t LAYER1AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
5734                                                      1                                                                         */
5735       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
5736     } LAYER1STRIDE_b;
5737   } ;
5738 
5739   union {
5740     __IOM uint32_t LAYER1RESXY;                 /*!< (@ 0x00000064) X and Y dimensions for the resolution of layer
5741                                                                     1.                                                         */
5742 
5743     struct {
5744       __IOM uint32_t LAYER1PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
5745       __IOM uint32_t LAYER1PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
5746     } LAYER1RESXY_b;
5747   } ;
5748 
5749   union {
5750     __IOM uint32_t LAYER1SCALEX;                /*!< (@ 0x00000068) Scale X factor of layer 1.                                 */
5751 
5752     struct {
5753       __IOM uint32_t LAYER1XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
5754                                                      number)                                                                   */
5755     } LAYER1SCALEX_b;
5756   } ;
5757 
5758   union {
5759     __IOM uint32_t LAYER1SCALEY;                /*!< (@ 0x0000006C) Scale Y factor of layer 1.                                 */
5760 
5761     struct {
5762       __IOM uint32_t LAYER1YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
5763                                                      number)                                                                   */
5764     } LAYER1SCALEY_b;
5765   } ;
5766 
5767   union {
5768     __IOM uint32_t LAYER2MODE;                  /*!< (@ 0x00000070) Activate and set-up layer 2.                               */
5769 
5770     struct {
5771       __IOM uint32_t LAYER2COLORMODE : 5;       /*!< [4..0] Color mode                                                         */
5772       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5773       __IOM uint32_t LAYER2SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5774       __IOM uint32_t LAYER2DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5775       __IOM uint32_t LAYER2ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5776       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5777       __IOM uint32_t LAYER2GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5778       __IOM uint32_t LAYER2HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5779       __IOM uint32_t LAYER2PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5780       __IOM uint32_t LAYER2BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5781       __IOM uint32_t LAYER2FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5782       __IOM uint32_t LAYER2EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5783     } LAYER2MODE_b;
5784   } ;
5785 
5786   union {
5787     __IOM uint32_t LAYER2STARTXY;               /*!< (@ 0x00000074) X and Y start dimensions of layer 2.                       */
5788 
5789     struct {
5790       __IOM uint32_t LAYER2YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5791                                                      of layer 2                                                                */
5792       __IOM uint32_t LAYER2XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5793                                                      of layer 2                                                                */
5794     } LAYER2STARTXY_b;
5795   } ;
5796 
5797   union {
5798     __IOM uint32_t LAYER2SIZEXY;                /*!< (@ 0x00000078) X and Y size of layer 2.                                   */
5799 
5800     struct {
5801       __IOM uint32_t LAYER2PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 2 in the Y dimension          */
5802       __IOM uint32_t LAYER2PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 2 in the X dimension         */
5803     } LAYER2SIZEXY_b;
5804   } ;
5805 
5806   union {
5807     __IOM uint32_t LAYER2ADDR;                  /*!< (@ 0x0000007C) The start address of the framebuffer to be accessed
5808                                                                     by layer 2.                                                */
5809 
5810     struct {
5811       __IOM uint32_t LAYER2STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
5812                                                      2.                                                                        */
5813     } LAYER2ADDR_b;
5814   } ;
5815 
5816   union {
5817     __IOM uint32_t LAYER2STRIDE;                /*!< (@ 0x00000080) Specify the stride and the AXI bus burst of layer
5818                                                                     2.                                                         */
5819 
5820     struct {
5821       __IOM uint32_t LAYER2STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
5822                                                      to line in bytes for each layer 2 memory                                  */
5823       __IOM uint32_t LAYER2AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 2                        */
5824       __IOM uint32_t LAYER2AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
5825                                                      2                                                                         */
5826       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
5827     } LAYER2STRIDE_b;
5828   } ;
5829 
5830   union {
5831     __IOM uint32_t LAYER2RESXY;                 /*!< (@ 0x00000084) X and Y dimensions for the resolution of layer
5832                                                                     2.                                                         */
5833 
5834     struct {
5835       __IOM uint32_t LAYER2PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
5836       __IOM uint32_t LAYER2PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
5837     } LAYER2RESXY_b;
5838   } ;
5839 
5840   union {
5841     __IOM uint32_t LAYER2SCALEX;                /*!< (@ 0x00000088) Scale X factor of layer 2.                                 */
5842 
5843     struct {
5844       __IOM uint32_t LAYER2XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
5845                                                      number)                                                                   */
5846     } LAYER2SCALEX_b;
5847   } ;
5848 
5849   union {
5850     __IOM uint32_t LAYER2SCALEY;                /*!< (@ 0x0000008C) Scale Y factor of layer 2.                                 */
5851 
5852     struct {
5853       __IOM uint32_t LAYER2YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
5854                                                      number)                                                                   */
5855     } LAYER2SCALEY_b;
5856   } ;
5857 
5858   union {
5859     __IOM uint32_t LAYER3MODE;                  /*!< (@ 0x00000090) Activate and set-up layer 3.                               */
5860 
5861     struct {
5862       __IOM uint32_t LAYER3COLORMODE : 5;       /*!< [4..0] Color mode                                                         */
5863       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5864       __IOM uint32_t LAYER3SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5865       __IOM uint32_t LAYER3DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5866       __IOM uint32_t LAYER3ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5867       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5868       __IOM uint32_t LAYER3GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5869       __IOM uint32_t LAYER3HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5870       __IOM uint32_t LAYER3PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5871       __IOM uint32_t LAYER3BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5872       __IOM uint32_t LAYER3FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5873       __IOM uint32_t LAYER3EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5874     } LAYER3MODE_b;
5875   } ;
5876 
5877   union {
5878     __IOM uint32_t LAYER3STARTXY;               /*!< (@ 0x00000094) X and Y start dimensions of layer 3.                       */
5879 
5880     struct {
5881       __IOM uint32_t LAYER3YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5882                                                      of layer 3                                                                */
5883       __IOM uint32_t LAYER3XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5884                                                      of layer 3                                                                */
5885     } LAYER3STARTXY_b;
5886   } ;
5887 
5888   union {
5889     __IOM uint32_t LAYER3SIZEXY;                /*!< (@ 0x00000098) X and Y size of layer 3.                                   */
5890 
5891     struct {
5892       __IOM uint32_t LAYER3PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 3 in the Y dimension          */
5893       __IOM uint32_t LAYER3PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 3 in the X dimension         */
5894     } LAYER3SIZEXY_b;
5895   } ;
5896 
5897   union {
5898     __IOM uint32_t LAYER3ADDR;                  /*!< (@ 0x0000009C) The start address of the framebuffer to be accessed
5899                                                                     by layer 3.                                                */
5900 
5901     struct {
5902       __IOM uint32_t LAYER3STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
5903                                                      3.                                                                        */
5904     } LAYER3ADDR_b;
5905   } ;
5906 
5907   union {
5908     __IOM uint32_t LAYER3STRIDE;                /*!< (@ 0x000000A0) Specify the stride and the AXI bus burst of layer
5909                                                                     3.                                                         */
5910 
5911     struct {
5912       __IOM uint32_t LAYER3STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
5913                                                      to line in bytes for each layer 3 memory                                  */
5914       __IOM uint32_t LAYER3AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 3                        */
5915       __IOM uint32_t LAYER3AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
5916                                                      3                                                                         */
5917       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
5918     } LAYER3STRIDE_b;
5919   } ;
5920 
5921   union {
5922     __IOM uint32_t LAYER3RESXY;                 /*!< (@ 0x000000A4) X and Y dimensions for the resolution of layer
5923                                                                     3.                                                         */
5924 
5925     struct {
5926       __IOM uint32_t LAYER3PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
5927       __IOM uint32_t LAYER3PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
5928     } LAYER3RESXY_b;
5929   } ;
5930 
5931   union {
5932     __IOM uint32_t LAYER3SCALEX;                /*!< (@ 0x000000A8) Scale X factor of layer 3.                                 */
5933 
5934     struct {
5935       __IOM uint32_t LAYER3XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
5936                                                      number)                                                                   */
5937     } LAYER3SCALEX_b;
5938   } ;
5939 
5940   union {
5941     __IOM uint32_t LAYER3SCALEY;                /*!< (@ 0x000000AC) Scale Y factor of layer 3.                                 */
5942 
5943     struct {
5944       __IOM uint32_t LAYER3YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
5945                                                      number)                                                                   */
5946     } LAYER3SCALEY_b;
5947   } ;
5948   __IM  uint32_t  RESERVED2[14];
5949 
5950   union {
5951     __IOM uint32_t DBICMD;                      /*!< (@ 0x000000E8) Register to read/write commands from/to DBI Type-B
5952                                                                     interface.                                                 */
5953 
5954     struct {
5955       __IOM uint32_t DATA2DBI   : 16;           /*!< [15..0] Data to send to the DBI interface                                 */
5956       __IOM uint32_t RSVD0      : 11;           /*!< [26..16] This field is reserved.                                          */
5957       __IOM uint32_t LOCALSTORE : 1;            /*!< [27..27] When set to 1, bits [15:0] are locally stored as base
5958                                                      address of the horizontal line; it is used along with the
5959                                                      DBI_CFG[17:16] register bits for the SPI interface                        */
5960       __IOM uint32_t READDBI    : 1;            /*!< [28..28] Read from DBI interface                                          */
5961       __IOM uint32_t RSVD1      : 1;            /*!< [29..29] This field is reserved.                                          */
5962       __IOM uint32_t DIRECTDATA : 1;            /*!< [30..30] Send direct data of type 'command' to the DBI interface          */
5963       __IOM uint32_t RSVD2      : 1;            /*!< [31..31] This field is reserved.                                          */
5964     } DBICMD_b;
5965   } ;
5966 
5967   union {
5968     __IOM uint32_t DBIRDAT;                     /*!< (@ 0x000000EC) Data read by DBI Type-B interface are stored
5969                                                                     in the DBI_RDAT register.                                  */
5970 
5971     struct {
5972       __IOM uint32_t READTYPEB  : 32;           /*!< [31..0] Read data from DBI Type-B interface                               */
5973     } DBIRDAT_b;
5974   } ;
5975 
5976   union {
5977     __IOM uint32_t CONFG;                       /*!< (@ 0x000000F0) Information of the layers n activation and setup.          */
5978 
5979     struct {
5980       __IOM uint32_t CFGGLBGAMMAEN : 1;         /*!< [0..0] Indicates that Global Gamma/Palette is enabled                     */
5981       __IOM uint32_t CFGFCURSOREN : 1;          /*!< [1..1] Indicates that fixed cursor is enabled                             */
5982       __IOM uint32_t CFGPCURSOREN : 1;          /*!< [2..2] Indicates that programmable cursor is enabled                      */
5983       __IOM uint32_t CFGDITHEREN : 1;           /*!< [3..3] Indicates that dithering is enabled                                */
5984       __IOM uint32_t CFGFORMATTEN : 1;          /*!< [4..4] Indicates that formatting is enabled                               */
5985       __IOM uint32_t CFGYUVCNVTEN : 1;          /*!< [5..5] Indicates that high quality YUV converter is enabled               */
5986       __IOM uint32_t CFGDBITYPEBEN : 1;         /*!< [6..6] Indicates that DBI Type-B interface is enabled                     */
5987       __IOM uint32_t CFGRGB2YUVEN : 1;          /*!< [7..7] Indicates that RGB to YUV converter is enabled                     */
5988       __IOM uint32_t CFGLAYER0EN : 1;           /*!< [8..8] Indicates that layer 0 is enabled                                  */
5989       __IOM uint32_t CFGLAYER0BLENDER : 1;      /*!< [9..9] Indicates that layer 0 has blender                                 */
5990       __IOM uint32_t CFGLAYER0SCALAR : 1;       /*!< [10..10] Indicates that layer 0 has scaler                                */
5991       __IOM uint32_t CFGLAYER0GAMMALUT : 1;     /*!< [11..11] Indicates that layer 0 has gamma LUT                             */
5992       __IOM uint32_t CFGLAYER1EN : 1;           /*!< [12..12] Indicates that layer 1 is enabled                                */
5993       __IOM uint32_t CFGLAYER1BLENDER : 1;      /*!< [13..13] Indicates that layer 1 has blender                               */
5994       __IOM uint32_t CFGLAYER1SCALAR : 1;       /*!< [14..14] Indicates that layer 1 has scaler                                */
5995       __IOM uint32_t CFGLAYER1GAMMALUT : 1;     /*!< [15..15] Indicates that layer 1 has gamma LUT                             */
5996       __IOM uint32_t CFGLAYER2EN : 1;           /*!< [16..16] Indicates that layer 2 is enabled                                */
5997       __IOM uint32_t CFGLAYER2BLENDER : 1;      /*!< [17..17] Indicates that layer 2 has blender                               */
5998       __IOM uint32_t CFGLAYER2SCALAR : 1;       /*!< [18..18] Indicates that layer 2 has scaler                                */
5999       __IOM uint32_t CFGLAYER2GAMMALUT : 1;     /*!< [19..19] Indicates that layer 2 has gamma LUT                             */
6000       __IOM uint32_t CFGLAYER3EN : 1;           /*!< [20..20] Indicates that layer 3 is enabled                                */
6001       __IOM uint32_t CFGLAYER3BLENDER : 1;      /*!< [21..21] Indicates that layer 3 has blender                               */
6002       __IOM uint32_t CFGLAYER3SCALAR : 1;       /*!< [22..22] Indicates that layer 3 has scaler                                */
6003       __IOM uint32_t CFGLAYER3GAMMALUT : 1;     /*!< [23..23] Indicates that layer 3 has gamma LUT                             */
6004       __IOM uint32_t RSVD       : 8;            /*!< [31..24] This field is reserved.                                          */
6005     } CONFG_b;
6006   } ;
6007 
6008   union {
6009     __IOM uint32_t IDREG;                       /*!< (@ 0x000000F4) Identification Register.                                   */
6010 
6011     struct {
6012       __IOM uint32_t DCID       : 32;           /*!< [31..0] Fixed value for DC ID                                             */
6013     } IDREG_b;
6014   } ;
6015 
6016   union {
6017     __IOM uint32_t INTERRUPT;                   /*!< (@ 0x000000F8) Register interrupts enabled, level or edge enabled.        */
6018 
6019     struct {
6020       __IOM uint32_t INTVSYNCEN : 1;            /*!< [0..0] When set to 1, VSYNC interrupt enabled                             */
6021       __IOM uint32_t INTHSYNCEN : 1;            /*!< [1..1] When set to 1, HSYNC interrupt enabled                             */
6022       __IOM uint32_t INTMMUERR  : 1;            /*!< [2..2] When set to 1, MMU error interrupt enabled                         */
6023       __IOM uint32_t INTTEEN    : 1;            /*!< [3..3] When set to 1, TE interrupt enabled                                */
6024             uint32_t            : 27;
6025       __IOM uint32_t INTTRIGGER : 1;            /*!< [31..31] Interrupt request trigger control                                */
6026     } INTERRUPT_b;
6027   } ;
6028 
6029   union {
6030     __IOM uint32_t STATUS;                      /*!< (@ 0x000000FC) DSI Status register (interrupt and pending activity)       */
6031 
6032     struct {
6033       __IOM uint32_t STATNOTBLANK : 1;          /*!< [0..0] Indicates that the controller is not in active vertical
6034                                                      blanking                                                                  */
6035       __IOM uint32_t STATDE     : 1;            /*!< [1..1] Indicates the DE signal status (0 or 1) at the current
6036                                                      time of reading                                                           */
6037       __IOM uint32_t STATHSYNC  : 1;            /*!< [2..2] Indicates the HSYNC signal status (0 or 1) at the current
6038                                                      time of reading                                                           */
6039       __IOM uint32_t STATVSYNC  : 1;            /*!< [3..3] Indicates the VSYNC signal status and the tearing e?ect
6040                                                      signal status (0 or 1) at the current time of reading                     */
6041       __IOM uint32_t STATCSYNC  : 1;            /*!< [4..4] Indicates the CSYNC signal status (0 or 1) at the current
6042                                                      time of reading                                                           */
6043       __IOM uint32_t STATLAST   : 1;            /*!< [5..5] Indicates that the last row is currently displayed                 */
6044       __IOM uint32_t STATUF     : 1;            /*!< [6..6] Indicates current underflow                                        */
6045       __IOM uint32_t STATSTICKY : 1;            /*!< [7..7] Indicates sticky underflow. This bit clears when interrupt
6046                                                      register is written                                                       */
6047       __IOM uint32_t STATTEAR   : 1;            /*!< [8..8] Indicates DBI Type-B tearing effect                                */
6048             uint32_t            : 1;
6049       __IOM uint32_t STATDBIRGB : 1;            /*!< [10..10] Indicates pending RGB data in DBI interface                      */
6050       __IOM uint32_t STATDBIPENDCOM : 1;        /*!< [11..11] Indicates pending commands in DBI interface                      */
6051       __IOM uint32_t STATDBIPENDTRANS : 1;      /*!< [12..12] Indicates pending output transaction in DBI interface            */
6052             uint32_t            : 19;
6053     } STATUS_b;
6054   } ;
6055 
6056   union {
6057     __IOM uint32_t COLMOD;                      /*!< (@ 0x00000100) Color mode status register indicating formats/back
6058                                                                     pressure are enabled.                                      */
6059 
6060     struct {
6061       __IOM uint32_t CLMDTSC4TSC6 : 1;          /*!< [0..0] Indicates that the TSc4/TSc6 propietary color format
6062                                                      is enabled                                                                */
6063       __IOM uint32_t CLMDTLYUV420 : 1;          /*!< [1..1] Indicates that the TLYUV420 color format is enabled                */
6064       __IOM uint32_t CLMDVYUV420 : 1;           /*!< [2..2] Indicates that the V_YUV420 color format is enabled                */
6065       __IOM uint32_t CLMDBGRA8888 : 1;          /*!< [3..3] Indicates that the BGRA8888 32-bit color format is enabled         */
6066       __IOM uint32_t CLMDABGR8888 : 1;          /*!< [4..4] Indicates that the ABGR8888 32-bit color format is enabled         */
6067       __IOM uint32_t CLMDYUY2   : 1;            /*!< [5..5] Indicates that the YUY2 color format is enabled                    */
6068       __IOM uint32_t CLMDRGB888 : 1;            /*!< [6..6] Indicates that the RGB888 24-bit color format is enabled           */
6069       __IOM uint32_t CLMDYUYV   : 1;            /*!< [7..7] Indicates that the YUYV color format is enabled                    */
6070       __IOM uint32_t CLMDL4     : 1;            /*!< [8..8] Indicates that the L4 color format is enabled                      */
6071       __IOM uint32_t CLMDL1     : 1;            /*!< [9..9] Indicates that the L1 color format is enabled                      */
6072       __IOM uint32_t CLMDL8     : 1;            /*!< [10..10] Indicates that the L8 color format is enabled                    */
6073       __IOM uint32_t CLMDARGB8888 : 1;          /*!< [11..11] Indicates that the ARGB8888 32-bit color format is
6074                                                      enabled                                                                   */
6075       __IOM uint32_t CLMDRGB565 : 1;            /*!< [12..12] Indicates that the RGB565 16-bit color format is enabled         */
6076       __IOM uint32_t CLMDRGB332 : 1;            /*!< [13..13] Indicates that the RGB332 8-bit color format is enabled          */
6077       __IOM uint32_t CLMDRGBA8888 : 1;          /*!< [14..14] Indicates that the RGBA8888 32-bit color format is
6078                                                      enabled                                                                   */
6079       __IOM uint32_t CLMDRGBA5551 : 1;          /*!< [15..15] Indicates that the RGBA5551 16-bit color format is
6080                                                      enabled                                                                   */
6081       __IOM uint32_t CLMDLUT8   : 1;            /*!< [16..16] Indicates that the LUT8 color format is enabled                  */
6082             uint32_t            : 14;
6083       __IOM uint32_t CLMDBKPRESSURE : 1;        /*!< [31..31] Indicates that back pressure support for the DBI Type
6084                                                      B interface is enabled                                                    */
6085     } COLMOD_b;
6086   } ;
6087   __IM  uint32_t  RESERVED3[32];
6088 
6089   union {
6090     __IOM uint32_t CRC;                         /*!< (@ 0x00000184) if cyclic redundancy errors occur, they are written
6091                                                                     in the CRC register.                                       */
6092 
6093     struct {
6094       __IOM uint32_t CRCREG     : 32;           /*!< [31..0] CRC value if CRC error exists                                     */
6095     } CRC_b;
6096   } ;
6097   __IM  uint32_t  RESERVED4[158];
6098 
6099   union {
6100     __IOM uint32_t GLLUT;                       /*!< (@ 0x00000400) R[0]G[0]B[0] thru R[255]G[255]B[255] Global palette,
6101                                                                     gamma correction memory region where x starts
6102                                                                     at 0 thru 255.Access to all 256 registers
6103                                                                     is best accomplished by passing an index
6104                                                                     via a macro. e.g. pseudocode #define DC_L0LUT(n)
6105                                                                     (*((volatile uint32_t*)(&L0LUT + (4*n))))                  */
6106 
6107     struct {
6108       __IOM uint32_t GLLUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6109       __IOM uint32_t GLLUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6110       __IOM uint32_t GLLUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6111             uint32_t            : 8;
6112     } GLLUT_b;
6113   } ;
6114   __IM  uint32_t  RESERVED5[255];
6115 
6116   union {
6117     __IOM uint32_t CURSORDATA;                  /*!< (@ 0x00000800) Color values for the pixel cursor that are used
6118                                                                     with the Cursor LUT where x starts at 0
6119                                                                     thru 127.Access to all 16 registers is best
6120                                                                     accomplished by passing an index via a macro.
6121                                                                     e.g. pseudocode #define DC_CURSORDATA(n)
6122                                                                     (*((volatile uint32_t*)(&CURSORDATA + (4*n))))             */
6123 
6124     struct {
6125       __IOM uint32_t CURDATA70  : 8;            /*!< [7..0] Pixel 'xy' color look up bits                                      */
6126             uint32_t            : 4;
6127       __IOM uint32_t CURDATA3112 : 20;          /*!< [31..12] Pixel 'xy' color look up bits                                    */
6128     } CURSORDATA_b;
6129   } ;
6130   __IM  uint32_t  RESERVED6[127];
6131 
6132   union {
6133     __IOM uint32_t CURSORLUT;                   /*!< (@ 0x00000A00) R[0]G[0]B[0] thru R[15]G[15]B[15] Cursor Look-up
6134                                                                     Table where x starts at 0 thru 15.Access
6135                                                                     to all 16 registers is best accomplished
6136                                                                     by passing an index via a macro. e.g. pseudocode
6137                                                                     #define DC_CURSORLUT(n) (*((volatile uint32_t*)(&CURSORLUT
6138                                                                     + (4*n))))                                                 */
6139 
6140     struct {
6141       __IOM uint32_t CURLUT0B   : 8;            /*!< [7..0] Cursor LUT blue bits                                               */
6142       __IOM uint32_t CURLUT0G   : 8;            /*!< [15..8] Cursor LUT green bits                                             */
6143       __IOM uint32_t CURLUT0R   : 8;            /*!< [23..16] Cursor LUT red bits                                              */
6144             uint32_t            : 8;
6145     } CURSORLUT_b;
6146   } ;
6147   __IM  uint32_t  RESERVED7[383];
6148 
6149   union {
6150     __IOM uint32_t L0LUT;                       /*!< (@ 0x00001000) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255].
6151                                                                     Layer 0 palette,gamma correction memory
6152                                                                     region where x starts at 0 thru 255.                       */
6153 
6154     struct {
6155       __IOM uint32_t L0LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6156       __IOM uint32_t L0LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6157       __IOM uint32_t L0LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6158       __IOM uint32_t L0LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6159     } L0LUT_b;
6160   } ;
6161   __IM  uint32_t  RESERVED8[255];
6162 
6163   union {
6164     __IOM uint32_t L1LUT;                       /*!< (@ 0x00001400) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255]
6165                                                                     Layer 1 palette,gamma correction memory
6166                                                                     region where x starts at 0 thru 255.Access
6167                                                                     to all 256 registers is best accomplished
6168                                                                     by passing an index via a macro. e.g. pseudocode
6169                                                                     #define DC_L1LUT(n) (*((volatile uint32_t*)(&L1LUT
6170                                                                     + (4*n))))                                                 */
6171 
6172     struct {
6173       __IOM uint32_t L1LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6174       __IOM uint32_t L1LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6175       __IOM uint32_t L1LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6176       __IOM uint32_t L1LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6177     } L1LUT_b;
6178   } ;
6179   __IM  uint32_t  RESERVED9[255];
6180 
6181   union {
6182     __IOM uint32_t L2LUT0;                      /*!< (@ 0x00001800) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255]
6183                                                                     Layer 2 palette,gamma correction memory
6184                                                                     region where x starts at 0 thru 255.Access
6185                                                                     to all 256 registers is best accomplished
6186                                                                     by passing an index via a macro. e.g. pseudocode
6187                                                                     #define DC_L2LUT(n) (*((volatile uint32_t*)(&L2LUT
6188                                                                     + (4*n))))                                                 */
6189 
6190     struct {
6191       __IOM uint32_t L2LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6192       __IOM uint32_t L2LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6193       __IOM uint32_t L2LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6194       __IOM uint32_t L2LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6195     } L2LUT0_b;
6196   } ;
6197   __IM  uint32_t  RESERVED10[255];
6198 
6199   union {
6200     __IOM uint32_t L3LUT;                       /*!< (@ 0x00001C00) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255]
6201                                                                     Layer 3 palette,gamma correction memory
6202                                                                     region where x starts at 0 thru 255.Access
6203                                                                     to all 256 registers is best accomplished
6204                                                                     by passing an index via a macro. e.g. pseudocode
6205                                                                     #define DC_L3LUT(n) (*((volatile uint32_t*)(&L3LUT
6206                                                                     + (4*n))))                                                 */
6207 
6208     struct {
6209       __IOM uint32_t L3LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6210       __IOM uint32_t L3LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6211       __IOM uint32_t L3LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6212       __IOM uint32_t L3LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6213     } L3LUT_b;
6214   } ;
6215 } DC_Type;                                      /*!< Size = 7172 (0x1c04)                                                      */
6216 
6217 
6218 
6219 /* =========================================================================================================================== */
6220 /* ================                                            DSI                                            ================ */
6221 /* =========================================================================================================================== */
6222 
6223 
6224 /**
6225   * @brief Digital Serial Interface Unit (DSI)
6226   */
6227 
6228 typedef struct {                                /*!< (@ 0x400A8000) DSI Structure                                              */
6229 
6230   union {
6231     __IOM uint32_t DEVICEREADY;                 /*!< (@ 0x00000000) Devide Ready register                                      */
6232 
6233     struct {
6234       __IOM uint32_t READY      : 1;            /*!< [0..0] Ready for programming after all count registers and timeout.       */
6235       __IOM uint32_t ULPS       : 2;            /*!< [2..1] ULPS field of the DEVICEREADY register.                            */
6236       __IOM uint32_t DISPLAYBUSPOSSESSEN : 1;   /*!< [3..3] Inform DSI receiver has to be given the bus possession
6237                                                      for receiving the tearing effect trigger message; Reset
6238                                                      by the processor to stop the bus possession of the DSI
6239                                                      receiver; Note: Tearing effect is supported only in Type1;
6240                                                      Display Architecture (command mode only) as suggested by
6241                                                      Display Command Set Specification; Note1: Even if the processor
6242                                                      does not clear the display_bus_possession bit after receiving
6243                                                      the interrupt for tearing effect, DSI-tx controller starts
6244                                                      the activities on the DSI link once the TE t                              */
6245             uint32_t            : 28;
6246     } DEVICEREADY_b;
6247   } ;
6248 
6249   union {
6250     __IOM uint32_t INTRSTAT;                    /*!< (@ 0x00000004) The interrupt status register.                             */
6251 
6252     struct {
6253       __IOM uint32_t RXSOTERROR : 1;            /*!< [0..0] (RW1C) Set to 1 if a start of transmission sequence error
6254                                                      is reported in the Acknowledge packet by the display device               */
6255       __IOM uint32_t RXSOTSYNCERROR : 1;        /*!< [1..1] (RW1C) Set to 1 if synchronisation error occurrence in
6256                                                      the start of transmission sequence is reported in the acknowledge
6257                                                      packet by the display device                                              */
6258       __IOM uint32_t RXEOTSYNCERROR : 1;        /*!< [2..2] (RW1C) Set to 1 if End of transmission synchronisation
6259                                                      Error is reported in the acknowledgment packet by the display
6260                                                      device                                                                    */
6261       __IOM uint32_t RXESCAPEMODE : 1;          /*!< [3..3] (RW1C) Entry Error; Set to 1 if Escape Mode Entry command
6262                                                      is not understandable by the display device and is reported
6263                                                      in the Acknowledge packet by the display device.                          */
6264       __IOM uint32_t RXLPTXSYNCERR : 1;         /*!< [4..4] (RW1C) Rx LP tx sync error; Set to 1 if Low power transmission
6265                                                      sync error occurs in the display device and is reported
6266                                                      in the Acknowledge packet by the display device                           */
6267       __IOM uint32_t RXPERIPHERAL : 1;          /*!< [5..5] (RW1C) Rx Peripheral timeout Error; Set to 1 if the high
6268                                                      speed receive timer value or LP Tx timer value are expired,
6269                                                      display device is reported in the Acknowledge packet                      */
6270       __IOM uint32_t RXFALSECNTRL : 1;          /*!< [6..6] (RW1C) RxFalse Control Error; Set to 1 if a control error
6271                                                      is reported in the acknowledge packet by the display device               */
6272       __IOM uint32_t RxECCS     : 1;            /*!< [7..7] (RW1C) RRxECC single bit error; Set to 1 if ECC syndrome
6273                                                      was computed and corrected for one bit error is reported
6274                                                      in the Acknowledge packet by the display device                           */
6275       __IOM uint32_t RxECCM     : 1;            /*!< [8..8] (RW1C) RxECC multibit error; Set to 1 if there is no
6276                                                      ECC correction for the packet or there are more than 2
6277                                                      bit errors in the packet isreported in the Acknowledge
6278                                                      packet by the display device                                              */
6279       __IOM uint32_t RXCHECKSUM : 1;            /*!< [9..9] (RW1C) Set to 1 if the computed CRC differs from the
6280                                                      received CRC value and is reported in the acknowledge packet
6281                                                      by the display device                                                     */
6282       __IOM uint32_t RxDSINR    : 1;            /*!< [10..10] (RW1C) RxDSI data type not recognised; Set to 1 if
6283                                                      the data type is not recognised by the display device is
6284                                                      reported in the Acknowledge packet by the display device                  */
6285       __IOM uint32_t RxDSIDI    : 1;            /*!< [11..11] (RW1C) RxDSI VC ID invalid; Set to 1 if the virtual
6286                                                      channel ID is invalid by the display device is reported
6287                                                      in the Acknowledge packet by the display device                           */
6288       __IOM uint32_t TXFALSECNTRL : 1;          /*!< [12..12] (RW1C) TxFalse Control Error; Set to 1 if a control
6289                                                      error is observed on the lanes by the Arasan_DSI_host                     */
6290       __IOM uint32_t TXECCS     : 1;            /*!< [13..13] (RW1C) Set to 1 if ECC syndrome was computed and is
6291                                                      corrected for one bit error during the reception of packets
6292                                                      by the Arasan_DSI_host.                                                   */
6293       __IOM uint32_t TXECCM     : 1;            /*!< [14..14] (RW1C) Set to 1 if there is no ECC correction for the
6294                                                      packet or there are more than 2 bit errors in the packet
6295                                                      received by Arasan_DSI_host.                                              */
6296       __IOM uint32_t TXCHECKSUM : 1;            /*!< [15..15] (RW1C) Txchecksum error; Set to 1 if the computed CRC
6297                                                      differs from the received CRC value during the reception
6298                                                      of packets by Arasan_DSI host                                             */
6299       __IOM uint32_t TxDSIN     : 1;            /*!< [16..16] (RW1C) TxDSI data type not recognised; Set to 1 if
6300                                                      the received data type is not recognised                                  */
6301       __IOM uint32_t TxDSII     : 1;            /*!< [17..17] (RW1C) TxDSI VC ID invalid; Set to 1 if the received
6302                                                      virtual channel ID is invalid                                             */
6303       __IOM uint32_t HIGHC      : 1;            /*!< [18..18] (RW1C) High contention;Set to 1 if a LP high fault
6304                                                      is registered by at the D-PHY contention detector. If this
6305                                                      interrupt is set device should be re-enumerated                           */
6306       __IOM uint32_t LOWC       : 1;            /*!< [19..19] (RW1C) Low contention; Set to 1 if a LP low fault is
6307                                                      registered by at the D-PHY contention detector. If this
6308                                                      interrupt is set device should be re-enumerated                           */
6309       __IOM uint32_t FIFOEMPTY  : 1;            /*!< [20..20] (RW1C) Set to 1 if all FIFOs are empty                           */
6310       __IOM uint32_t HSTXTIMEOUT : 1;           /*!< [21..21] (RW1C) Set if a high speed transmission prevails for
6311                                                      more than the expected count value this interrupt is raised               */
6312       __IOM uint32_t LPRXTIMEOUT : 1;           /*!< [22..22] (RW1C) Set if a low power reception count expires this
6313                                                      interrupt is generated                                                    */
6314       __IOM uint32_t TURNARNDACK : 1;           /*!< [23..23] (RW1C) Turn around acknowledge. Set if a turn around
6315                                                      acknowledgement sequence is timeout not received from the
6316                                                      display device                                                            */
6317       __IOM uint32_t ACKWNOERR  : 1;            /*!< [24..24] (RW1C) T ACK_with No_error; Set if acknowledge trigger
6318                                                      message is received with out any error.                                   */
6319       __IOM uint32_t RXINVALID  : 1;            /*!< [25..25] (RW1C) Rx Invalid; Set if acknowledge short packet
6320                                                      shows an invalid transmission count                                       */
6321       __IOM uint32_t RXDSIPROT  : 1;            /*!< [26..26] (RW1C) Rx DSI protocol violation; Set if acknowledge
6322                                                      short packet shows DSI protocol violation error                           */
6323       __IOM uint32_t SPECIALPACK : 1;           /*!< [27..27] (RW1C) Special packet command sent; Set to confirm
6324                                                      the transmission of the DPI event specific commands set
6325                                                      in the dpi control and dpi data                                           */
6326       __IOM uint32_t INITDONE   : 1;            /*!< [28..28] (RW1C) Set 1 indicates that the DSI initialization
6327                                                      is done. DSI Tx is ready to accept the DPI or DBI or Generic
6328                                                      transfer                                                                  */
6329       __IOM uint32_t RXCNT      : 1;            /*!< [29..29] (RW1C) Rx Contention; Set to 1 if contention detected
6330                                                      in the display                                                            */
6331       __IOM uint32_t DPILINETO  : 1;            /*!< [30..30] (RW1C) DPI line time out. Set to 1 indicates that the
6332                                                      line time out during the DPI transfer                                     */
6333       __IOM uint32_t DPIPRGERR  : 1;            /*!< [31..31] (RW1C) Set to 1 indicates that the error in DPI parameters
6334                                                      programming                                                               */
6335     } INTRSTAT_b;
6336   } ;
6337 
6338   union {
6339     __IOM uint32_t INTREN;                      /*!< (@ 0x00000008) Interrupt enable register.                                 */
6340 
6341     struct {
6342       __IOM uint32_t RXSOTERROR : 1;            /*!< [0..0] RX start of transmission; set to enable the interrupt
6343                                                      for start of transmission                                                 */
6344       __IOM uint32_t RXSOTSYNCERROR : 1;        /*!< [1..1] RX start of transmission; Set to enable the interrupt
6345                                                      for start of transmission synchronization error in the
6346                                                      acknowledgement packet reports                                            */
6347       __IOM uint32_t RXEOTSYNCRR : 1;           /*!< [2..2] RxEot Sync Error l set to enable the interrupt for the
6348                                                      end of transmission synchronisation Error in the acknowledgment
6349                                                      packet reports                                                            */
6350       __IOM uint32_t RXESCPMDETRYERR : 1;       /*!< [3..3] RxEscape Mode Entry Error; Set to enable the interrupt
6351                                                      for Escape Mode Entry command error in the acknowledgment
6352                                                      packet reports                                                            */
6353       __IOM uint32_t RXLPTXSYNCERR : 1;         /*!< [4..4] Rx LP tx sync error; Set to enable the interrupt for
6354                                                      Low power transmission sync error in the acknowledgment
6355                                                      packet reports                                                            */
6356       __IOM uint32_t RXPERIPHRCVTOE : 1;        /*!< [5..5] Peripheral receive timeout Error; Set to enable the interrupt
6357                                                      for the high speed timeout Error or Lp tx timeout error
6358                                                      in the acknowledgment packet reports                                      */
6359       __IOM uint32_t RXFALSE    : 1;            /*!< [6..6] RxFalse Control error; set to enable the interrupt for
6360                                                      control error in the acknowledgment packet reports.                       */
6361       __IOM uint32_t RXECCS     : 1;            /*!< [7..7] RxECC single bit error; Set to enable the interrupt for
6362                                                      ECC syndrome computation and one bit error correction for
6363                                                      the acknowledgment packet                                                 */
6364       __IOM uint32_t RXECCM     : 1;            /*!< [8..8] RxECC multibit error; Set to enable the interrupt for
6365                                                      no ECC correction for the packet or there are more than
6366                                                      2 bit errors reported in the acknowledgment packet                        */
6367       __IOM uint32_t RXCHECKSUM : 1;            /*!< [9..9] Rxchecksum error; Set to enable the interrupt for the
6368                                                      computed CRC differs from the received CRC value in the
6369                                                      acknowledgment packet reports                                             */
6370       __IOM uint32_t RxDSIData  : 1;            /*!< [10..10] RxDSI data type not recognised; Set to enable the interrupt
6371                                                      for the un recognised data type in the acknowledgment packet
6372                                                      reports                                                                   */
6373       __IOM uint32_t RxDSIV     : 1;            /*!< [11..11] RxDSI VC ID invalid virtual channel; Set to enable
6374                                                      the interrupt for invalid ID in the acknowledgment packet
6375                                                      reports                                                                   */
6376       __IOM uint32_t TxFalseCntrl : 1;          /*!< [12..12] TxFalse Control; Set to enable the interrupt for the
6377                                                      control error observed on the lanes by the Arasan_DSI_host                */
6378       __IOM uint32_t TxECCS     : 1;            /*!< [13..13] TxECC single bit; Set to enable the interrupt if ECC
6379                                                      syndrome was computed and is corrected for one bit error
6380                                                      during the reception of packets by the Arasan DSI Host                    */
6381       __IOM uint32_t TxECCM     : 1;            /*!< [14..14] TxECC multibit; Set to enable the interrupt if there
6382                                                      is no ECC correction for the packet or there are more than
6383                                                      2 bit errors in the packet received by Arasan DSI host                    */
6384       __IOM uint32_t TXCHCKSUM  : 1;            /*!< [15..15] Txchecksum error; Set to enable the interrupt if the
6385                                                      computed CRC differs from the received CRC value for the
6386                                                      received packets                                                          */
6387       __IOM uint32_t TxDSID     : 1;            /*!< [16..16] TxDSI data type not recognised; Set to enable the interrupt
6388                                                      if the received packets data type is not recognised                       */
6389       __IOM uint32_t TxDSIV     : 1;            /*!< [17..17] TxDSI VC ID invalid; Set to enable the interrupt if
6390                                                      the received packets virtual channel ID is invalid                        */
6391       __IOM uint32_t HIGHC      : 1;            /*!< [18..18] High contention; Set to enable a LP high fault interrupt         */
6392       __IOM uint32_t LOWC       : 1;            /*!< [19..19] Low contention; Set to enable a LP low fault interrupt           */
6393       __IOM uint32_t FIFOEMPTY  : 1;            /*!< [20..20] Set to enable a FIFO empty interrupt                             */
6394       __IOM uint32_t HSTXTIMEOUT : 1;           /*!< [21..21] Set to enable a high speed transmission timeout                  */
6395       __IOM uint32_t LPRXTIMEOUT : 1;           /*!< [22..22] Set to enable low power reception count timeouts                 */
6396       __IOM uint32_t TURNARNDACK : 1;           /*!< [23..23] Set to enable turn around acknowledgement sequence
6397                                                      timeout                                                                   */
6398       __IOM uint32_t ACKWITHNOERR : 1;          /*!< [24..24] ACK with No_error; Set to enable acknowledge trigger
6399                                                      message reception with out any error                                      */
6400       __IOM uint32_t RXINV      : 1;            /*!< [25..25] Rx Invalid transmission count error; Set to enable
6401                                                      acknowledge invalid transmission counterror                               */
6402       __IOM uint32_t RXDSI      : 1;            /*!< [26..26] Rx DSI protocol violation; Set to enable DSI protocol
6403                                                      violation error                                                           */
6404       __IOM uint32_t SPECIALPACK : 1;           /*!< [27..27] Special packet command sent; Set to enable the confirmation
6405                                                      interrupt for transmitting DPI events set in the dpi data
6406                                                      and dpi control registers                                                 */
6407       __IOM uint32_t INITDONE   : 1;            /*!< [28..28] Set 1 indicates that the DSI initialisation is done
6408                                                      DSI Tx is ready to accept the DPI or DBI or Generic transfer              */
6409       __IOM uint32_t RXCONTENT  : 1;            /*!< [29..29] Detected Rx Contention Detected; Set to enable the
6410                                                      interrupt for contention detected error in the acknowledgment
6411                                                      packet reports                                                            */
6412       __IOM uint32_t DPILINETO  : 1;            /*!< [30..30] Dpi line timeout; Set to 1 indicates that the line
6413                                                      time out during the DPI transfer                                          */
6414       __IOM uint32_t DPI        : 1;            /*!< [31..31] PGRMERR DPI program error; Set to 1 indicates that
6415                                                      the error in DPI parameters programming                                   */
6416     } INTREN_b;
6417   } ;
6418 
6419   union {
6420     __IOM uint32_t DSIFUNCPRG;                  /*!< (@ 0x0000000C) DSI function programming register                          */
6421 
6422     struct {
6423       __IOM uint32_t DATALANES  : 3;            /*!< [2..0] The number Data lanes to be supported is programmed by
6424                                                      the processor                                                             */
6425       __IOM uint32_t CHNUMVM    : 2;            /*!< [4..3] Channel number for video mode                                      */
6426       __IOM uint32_t CHNUMCMODE : 2;            /*!< [6..5] Channel Number for command mode is programmed by the
6427                                                      processor                                                                 */
6428       __IOM uint32_t SUPCOLVIDMODE : 3;         /*!< [9..7] Supported colour format for video mode.                            */
6429             uint32_t            : 3;
6430       __IOM uint32_t REGNAME    : 3;            /*!< [15..13] Field description needed here.                                   */
6431             uint32_t            : 16;
6432     } DSIFUNCPRG_b;
6433   } ;
6434 
6435   union {
6436     __IOM uint32_t HSTXTIMEOUT;                 /*!< (@ 0x00000010) Maximum duration allow for the DSi host to remain
6437                                                                     in High speed mode for transmission.                       */
6438 
6439     struct {
6440       __IOM uint32_t MAXDURTOCNT : 24;          /*!< [23..0] The maximum duration allowed for the DSI host to remain
6441                                                      in high speed mode for a transmission. If the counter expires,
6442                                                      processor is interrupted with HS_Tx_timeout interrupt                     */
6443             uint32_t            : 8;
6444     } HSTXTIMEOUT_b;
6445   } ;
6446 
6447   union {
6448     __IOM uint32_t LPRXTO;                      /*!< (@ 0x00000014) Timeout value to be checked for reverse communicationl     */
6449 
6450     struct {
6451       __IOM uint32_t TOCHKRVS   : 24;           /*!< [23..0] Timeout value to be checked for reverse communication.
6452                                                      If the counter expires, processor is interrupted with LP_Rx_timeout
6453                                                      interrupt.The timeout value is protocol specific. Time
6454                                                      out value is calculated from txclkesc(50ns).                              */
6455             uint32_t            : 8;
6456     } LPRXTO_b;
6457   } ;
6458 
6459   union {
6460     __IOM uint32_t TURNARNDTO;                  /*!< (@ 0x00000018) Timeout value to be checked after the DSI host
6461                                                                     makes a trun around in the direction of
6462                                                                     transfers.                                                 */
6463 
6464     struct {
6465       __IOM uint32_t TIMOUT     : 6;            /*!< [5..0] If the counter expires, processor is interrupted with
6466                                                      Turn_around_ack timeout interrupt; this specified period
6467                                                      shall be longer then the maximum possible turnaround delay
6468                                                      for the unit to which the turnaround request was sent,
6469                                                      which is 23 clock cycles of txclkesc; any number greater
6470                                                      than or equal to 23 is an acceptable number.                              */
6471             uint32_t            : 26;
6472     } TURNARNDTO_b;
6473   } ;
6474 
6475   union {
6476     __IOM uint32_t DEVICERESETTIMER;            /*!< (@ 0x0000001C) Timeout value to be checked for device to be
6477                                                                     reset after issuing reset entry command                    */
6478 
6479     struct {
6480       __IOM uint32_t TIMOUT     : 16;           /*!< [15..0] If the timer expires the DSI Host enters normal operation;
6481                                                      This time out value is used while contention recovery procedure;
6482                                                      the time out value is equal to a value longer than the
6483                                                      specified time required to complete the reset sequence                    */
6484             uint32_t            : 16;
6485     } DEVICERESETTIMER_b;
6486   } ;
6487 
6488   union {
6489     __IOM uint32_t DPIRESOLUTION;               /*!< (@ 0x00000020) Shows the horizontal address count in pixels               */
6490 
6491     struct {
6492       __IOM uint32_t DPIRESOLUTION : 32;        /*!< [31..0] DPIRESOLUTION register description needed here.                   */
6493     } DPIRESOLUTION_b;
6494   } ;
6495   __IM  uint32_t  RESERVED;
6496 
6497   union {
6498     __IOM uint32_t HSYNCCNT;                    /*!< (@ 0x00000028) Shows the horizontal sync value in terms of byte
6499                                                                     clock.                                                     */
6500 
6501     struct {
6502       __IOM uint32_t HORZCNT    : 16;           /*!< [15..0] Shows the horizontal sync value in terms of byte clock
6503                                                      (txbyteclkhs); Minimum HSA period should be sufficient
6504                                                      to transmit a Hsync start short packet(4 bytes) i) For
6505                                                      Non-burst Mode with sync pulse, Min value - 4 in decimal
6506                                                      (plus an optional 6 bytes for a zero payload blanking packet);
6507                                                      But if the value is less than 10 but more than 4, then
6508                                                      this count will be added to the HBP's count for one lane;
6509                                                      ii) For Non-Burst Sync Event and Burst Mode, there is no
6510                                                      HSA, so you can program this to zero. If you program thi                  */
6511             uint32_t            : 16;
6512     } HSYNCCNT_b;
6513   } ;
6514 
6515   union {
6516     __IOM uint32_t HORIZBKPORCHCNT;             /*!< (@ 0x0000002C) Shows the horizontal back porch value in terms
6517                                                                     of txbyteclkhs.                                            */
6518 
6519     struct {
6520       __IOM uint32_t HORZBKPCNT : 16;           /*!< [15..0] For Non Burst Sync pulse mode, for one lane. Minimum
6521                                                      HBP count = Hsync End short packet + HBP Blanking packet
6522                                                      overhead (header(4) + crc (2)) + RGB packet header For
6523                                                      other lane counts minimum value = Minimum HBPcount / lane_count.
6524                                                      For Non Burst Sync event / Burst Mode there is no HSA.
6525                                                      Minimum HBP count = (Hsync Start short packet + HBP Blanking
6526                                                      packet overhead + RGB packet header) / lane_count Min value
6527                                                      - 14 in decimal (accounted with zero payloads for blanking
6528                                                      packet] for one lane. Max value - any 12 bit v                            */
6529             uint32_t            : 16;
6530     } HORIZBKPORCHCNT_b;
6531   } ;
6532 
6533   union {
6534     __IOM uint32_t HORIZFPORCHCNT;              /*!< (@ 0x00000030) Shows the horizontal front porch value in terms
6535                                                                     of txbyteclkhs.                                            */
6536 
6537     struct {
6538       __IOM uint32_t HORZFTPCNT : 16;           /*!< [15..0] Minimum HFP period should be sufficient to transmit
6539                                                      RGB Data packet footer (2 bytes) + Blanking packet overhead
6540                                                      (6 bytes) +adjustable count (16 bytes) for non burst mode;
6541                                                      For other lane counts Minimum value = (RGB Data packet
6542                                                      footer(2 bytes) + Blanking packet overhead(6 bytes)) /
6543                                                      (lane_count) + adjustable count(16 bytes) For burst mode,
6544                                                      Minimum HFP period should be sufficient to transmit Blanking
6545                                                      packet overhead(6 bytes) +adjustable count (16 bytes) for
6546                                                      one lane for other lane counts Minimum value = ( Blan                     */
6547             uint32_t            : 16;
6548     } HORIZFPORCHCNT_b;
6549   } ;
6550 
6551   union {
6552     __IOM uint32_t HORZACTIVEAREACNT;           /*!< (@ 0x00000034) Horizontal active area count / time for active
6553                                                                     image data / Horizontal Address                            */
6554 
6555     struct {
6556       __IOM uint32_t HORACTCNT  : 16;           /*!< [15..0] Shows the horizontal active area value in terms of txbyteclkhs.
6557                                                      In Non Burst Mode, Count equal to RGB word count value
6558                                                      In Burst Mode, RGB pixel packets are time compressed, leaving
6559                                                      more time during a scan line for LP mode (saving power)
6560                                                      or for multiplexing other transmissions onto the DSI link.
6561                                                      Hence, the count equals the time in txbyteclkhs for sending
6562                                                      time compressed RGB pixels plus the time needed for moving
6563                                                      to power save mode or the time needed for secondary channel
6564                                                      to use the DSI link. But if the lef                                       */
6565             uint32_t            : 16;
6566     } HORZACTIVEAREACNT_b;
6567   } ;
6568 
6569   union {
6570     __IOM uint32_t VSYNCCNT;                    /*!< (@ 0x00000038) Shows the vertical sync value                              */
6571 
6572     struct {
6573       __IOM uint32_t VSC        : 16;           /*!< [15..0] Shows the vertical sync value in terms of lines. Min
6574                                                      value - 2 Max value - any 12 bit value greater than 2 based
6575                                                      on DPI resolution                                                         */
6576             uint32_t            : 16;
6577     } VSYNCCNT_b;
6578   } ;
6579 
6580   union {
6581     __IOM uint32_t VERTBKPORCHCNT;              /*!< (@ 0x0000003C) Shows the vertical back porch value                        */
6582 
6583     struct {
6584       __IOM uint32_t VBPSC      : 16;           /*!< [15..0] Shows the vertical back porch value in terms of lines.
6585                                                      Min value - 1; Max value - any 12 bit value greater than
6586                                                      1 based on DPI resolution                                                 */
6587             uint32_t            : 16;
6588     } VERTBKPORCHCNT_b;
6589   } ;
6590 
6591   union {
6592     __IOM uint32_t VERTFPORCHCNT;               /*!< (@ 0x00000040) Shows the vertical front porch value                       */
6593 
6594     struct {
6595       __IOM uint32_t VFPSC      : 16;           /*!< [15..0] Shows the vertical front porch value in terms of lines.
6596                                                      Min value - 1; Max value - any 12 bit value greater than
6597                                                      1 based on DPI resolution                                                 */
6598             uint32_t            : 16;
6599     } VERTFPORCHCNT_b;
6600   } ;
6601 
6602   union {
6603     __IOM uint32_t DATALANEHILOSWCNT;           /*!< (@ 0x00000044) High speed to low power or Low power to high
6604                                                                     speed switching time                                       */
6605 
6606     struct {
6607       __IOM uint32_t DATALHLSWCNT : 16;         /*!< [15..0] High speed to low power or Low power to high speed power
6608                                                      or Low switching time in terms byte clock (txbyteclkhs).
6609                                                      This power to high speed switch count value is based on
6610                                                      the byte clock (txbyteclkhs) and low power clock frequency
6611                                                      (txclkesc); Data lane Switch count = 4 * Tlpx + programmed
6612                                                      THS_prep + programmed THS_zero + 4 byteclk Tlpx = Low power
6613                                                      clock equivalence in of terms byte clock programmed in
6614                                                      AHB reg 68h; THS_prep = programmed value of dln_cnt_hs_prep
6615                                                      in AHB Reg 6ch bit (7:0) THS_zero = programmed v                          */
6616             uint32_t            : 16;
6617     } DATALANEHILOSWCNT_b;
6618   } ;
6619 
6620   union {
6621     __IOM uint32_t DPI;                         /*!< (@ 0x00000048) DPI control register.                                      */
6622 
6623     struct {
6624       __IOM uint32_t SHUTDOWN   : 1;            /*!< [0..0] Set to 1 to indicate a shut down short packet has to
6625                                                      be packetised for the DPIs virtual channel                                */
6626       __IOM uint32_t TURNON1    : 1;            /*!< [1..1] Set to 1 to indicate a Turn ON short packet has to be
6627                                                      packetised for the DPIs virtual channel                                   */
6628       __IOM uint32_t COLOR      : 1;            /*!< [2..2] MODEON Set to 1 to indicate a color Mode ON short packet
6629                                                      has to be packetised for the DPIs virtual channel.                        */
6630       __IOM uint32_t COLORMODEOFF : 1;          /*!< [3..3] Set to 1 to indicate a Color Mode OFF short packet has
6631                                                      to be packetised for the DPIs virtual channel                             */
6632             uint32_t            : 28;
6633     } DPI_b;
6634   } ;
6635 
6636   union {
6637     __IOM uint32_t PLLLOCKCNT;                  /*!< (@ 0x0000004C) The PLL counter value                                      */
6638 
6639     struct {
6640       __IOM uint32_t PLLCNTVAL  : 16;           /*!< [15..0] Pll counter value in terms of low power clock.                    */
6641             uint32_t            : 16;
6642     } PLLLOCKCNT_b;
6643   } ;
6644 
6645   union {
6646     __IOM uint32_t INITCNT;                     /*!< (@ 0x00000050) Count register to initialize the DSI HOST IP               */
6647 
6648     struct {
6649       __IOM uint32_t MSTR       : 16;           /*!< [15..0] Counter value in terms of low power clock to initialise
6650                                                      the DSI Host IP (TINIT) that drives a stop state on the
6651                                                      mipis D-PHY bus; DPHY Initialization period min 100 x B5s;
6652                                                      Time out value is calculated by txclkesc and the count
6653                                                      value is 7d0h(2000 in decimal)                                            */
6654             uint32_t            : 16;
6655     } INITCNT_b;
6656   } ;
6657 
6658   union {
6659     __IOM uint32_t MAXRETPACSZE;                /*!< (@ 0x00000054) MAXRETPACSZE register description needed here.             */
6660 
6661     struct {
6662       __IOM uint32_t COUNTVAL   : 11;           /*!< [10..0] Set the count value in bytes to collect the return data
6663                                                      packet for reverse direction data flow in data lane0 in
6664                                                      response to a DBI read operation; Count value equals the
6665                                                      maximum size of the payload in a Long packet transmitted
6666                                                      from peripheral back to; for DBI and DPI interleaving Min
6667                                                      value - 1; Max value - Maximum payload for a long packet
6668                                                      size is 1K bytes Note: DCS short Read Response or Long
6669                                                      read response with 1 or 2 parameters is applicable in this
6670                                                      mode; For DBI only, Min value - 1 Max value - Maximum pa                  */
6671             uint32_t            : 4;
6672       __IOM uint32_t HSLP       : 1;            /*!< [15..15] Indicates the data transfer type                                 */
6673             uint32_t            : 16;
6674     } MAXRETPACSZE_b;
6675   } ;
6676 
6677   union {
6678     __IOM uint32_t VIDEOMODEFMT;                /*!< (@ 0x00000058) Sets the Video mode format (packet sequence)
6679                                                                     to be supported in DSI.                                    */
6680 
6681     struct {
6682       __IOM uint32_t VIDEMDFMT  : 2;            /*!< [1..0] Sets the Video mode format (packet sequence) to be supported
6683                                                      in DSI; in Non Burst Mode, in addition to programming this
6684                                                      register the horizontal active area count register value
6685                                                      should also be programmed equal to RGB word count value;
6686                                                      in Burst Mode, in addition to programming this register
6687                                                      the horizontal active area count register value should
6688                                                      also be programmed greater than the RGB word count value,
6689                                                      leaving more time during a scan line for LP mode (saving
6690                                                      power) or for multiplexing other transmissions onto                       */
6691             uint32_t            : 30;
6692     } VIDEOMODEFMT_b;
6693   } ;
6694 
6695   union {
6696     __IOM uint32_t CLKEOT;                      /*!< (@ 0x0000005C) The EOT clock register disables the video.                 */
6697 
6698     struct {
6699       __IOM uint32_t EOT        : 1;            /*!< [0..0] Set by the processor to enable or disable EOT short disable_register
6700                                                      packet transmission; vy default this register value is
6701                                                      0; for backward compatibility of earlier DSI systems, EOT
6702                                                      short packet transmission can be disabled; 0 EOT short
6703                                                      packet transmission enabled, 1 EOT short packet transmission
6704                                                      disabled                                                                  */
6705       __IOM uint32_t CLOCK      : 1;            /*!< [1..1] Set by the processor to enable or disable clock; Stopping
6706                                                      feature during BLLP timing in a DPI transfer in dual channel
6707                                                      mode or during DPI only mode and also when there is no
6708                                                      traffic in the DBI interface in DBI only enabled mode.
6709                                                      By default this register value is 0.                                      */
6710       __IOM uint32_t BTA        : 1;            /*!< [2..2] Disable video; Set by the processor to inform the DSI
6711                                                      controller to disable the BTA sent at the last blanking
6712                                                      line of VFP. By default, this bit is set to 0; 0 BTA sending
6713                                                      at the last blanking line of VFP is enabled; 1 BTA sending
6714                                                      at the last blanking line of VFP is disabled                              */
6715             uint32_t            : 29;
6716     } CLKEOT_b;
6717   } ;
6718 
6719   union {
6720     __IOM uint32_t POLARITY;                    /*!< (@ 0x00000060) Polarity Register                                          */
6721 
6722     struct {
6723       __IOM uint32_t PBITS      : 4;            /*!< [3..0] Polarity bits                                                      */
6724             uint32_t            : 28;
6725     } POLARITY_b;
6726   } ;
6727 
6728   union {
6729     __IOM uint32_t CLKLANESWT;                  /*!< (@ 0x00000064) High speed to low power switching time in terms
6730                                                                     ofbyte clock (txbyteclkhs)                                 */
6731 
6732     struct {
6733       __IOM uint32_t HISPLPSW   : 16;           /*!< [15..0] High speed to low power switching time in terms byte
6734                                                      clock (txbyteclkhs). This value is based on the byte clock
6735                                                      (txbyteclkhs) and low power clock frequency; HS to LP switch
6736                                                      count = Tclk_trail + THS_Exit + 3 byteclk Tclk_trail =
6737                                                      programmed value of cln_cnt_hs_trail in AHB Reg 70h bit
6738                                                      (23:16) THS_Exit = programmed value of cln_cnt_hs_exit
6739                                                      in AHB Reg 70h bit (31:24) Typical value - Number of byte
6740                                                      clocks request to switch from high speed mode to low power
6741                                                      mode after txrequesths_clk is de-asserted.                                */
6742       __IOM uint32_t LOWPWR2HI  : 16;           /*!< [31..16] This value is based on the byte clock (txbyteclkhs)
6743                                                      and low power clock frequency (txclkesc)LP to HS switch
6744                                                      count = 4 * Tlpx + (programmed Tclk_prep + extracount (1
6745                                                      byteclk) ) + (programmed Tclk_zero + extracount (1 byteclk)
6746                                                      ) + Tclk_pre + 2 byteclk Tlpx = Low power clock equivalence
6747                                                      in terms of byte clock programmed in AHB reg 68h Tclk_prep
6748                                                      = programmed value of cln_cnt_prep in AHB Reg 70h bit (7:0)
6749                                                      Tclk_zero = programmed value of cln_cnt_zero in AHB Reg
6750                                                      70h bit (15:8) Tclk_pre = 8 UI Typical value x96 Nu                       */
6751     } CLKLANESWT_b;
6752   } ;
6753 
6754   union {
6755     __IOM uint32_t LPBYTECLK;                   /*!< (@ 0x00000068) Low power clock equivalence in terms of byte
6756                                                                     clock.                                                     */
6757 
6758     struct {
6759       __IOM uint32_t VALBYTECLK : 16;           /*!< [15..0] The value programmed in this register is equal to the
6760                                                      number of byte clocks occupied in one low power clock;
6761                                                      this value is based on the byte clock (txbyteclkhs) and
6762                                                      low power clock frequency (txclkesc)                                      */
6763             uint32_t            : 16;
6764     } LPBYTECLK_b;
6765   } ;
6766 
6767   union {
6768     __IOM uint32_t DPHYPARAM;                   /*!< (@ 0x0000006C) This field provides the timing requirement in
6769                                                                     byte clocks for the high speed preparation
6770                                                                     time.                                                      */
6771 
6772     struct {
6773       __IOM uint32_t HSPREP     : 8;            /*!< [7..0] This field provides the timing requirement in byte clocks
6774                                                      for the high speed preparation time. This corresponds to
6775                                                      the THS-PREP parameter specified in the DPHY specificaton                 */
6776       __IOM uint32_t HSZERO     : 8;            /*!< [15..8] This field provides the timing requirement in byte clocks
6777                                                      for the high speed drive zero time. This corresponds to
6778                                                      the THS-ZERO parameter specified in the DPHY specification                */
6779       __IOM uint32_t HSTRAIL    : 8;            /*!< [23..16] This field provides the timing requirement in byte
6780                                                      clocks for the high speed trail time; this corresponds
6781                                                      to the THS-TRAIL parameter specified in the DPHY specification            */
6782       __IOM uint32_t HSEXIT     : 8;            /*!< [31..24] This field provides the timing requirement in byte
6783                                                      clocks for the high speed exit time; this corresponds to
6784                                                      the THS-EXIT parameter specified in the DPHY specification                */
6785     } DPHYPARAM_b;
6786   } ;
6787 
6788   union {
6789     __IOM uint32_t CLKLANETIMPARM;              /*!< (@ 0x00000070) This field provides the timing requirement in
6790                                                                     byte clocks                                                */
6791 
6792     struct {
6793       __IOM uint32_t HSPREP     : 8;            /*!< [7..0] This field provides the timing requirement in byte corresponds
6794                                                      to the TCLK-PREP parameter specified in the DPHY specificatio             */
6795       __IOM uint32_t HSZERO     : 8;            /*!< [15..8] This field provides the timing requirement in byte clocks
6796                                                      for the high speed drive zero time; this corresponds to
6797                                                      the TCLK-ZERO parameter specified in the DPHY specification               */
6798       __IOM uint32_t HSTRAIL    : 8;            /*!< [23..16] This field provides the timing requirement in byte
6799                                                      clocks for the high speed trail time; This corresponds
6800                                                      to the TCLK-TRAIL parameter specified in the DPHY specification           */
6801       __IOM uint32_t HSEXIT     : 8;            /*!< [31..24] This field provides the timing requirement in byte
6802                                                      clocks for the high speed exit time; This corresponds to
6803                                                      the THS-EXIT parameter specified in the DPHY specification.               */
6804     } CLKLANETIMPARM_b;
6805   } ;
6806 
6807   union {
6808     __IOM uint32_t RSTENBDFE;                   /*!< (@ 0x00000074) This field provides the reset (enable) to the
6809                                                                     DFE                                                        */
6810 
6811     struct {
6812       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] This field provides the reset (enable) to the DFE.                 */
6813             uint32_t            : 31;
6814     } RSTENBDFE_b;
6815   } ;
6816 
6817   union {
6818     __IOM uint32_t AFETRIM0;                    /*!< (@ 0x00000078) Afe Trim reg0                                              */
6819 
6820     struct {
6821       __IOM uint32_t AFETRIM0   : 32;           /*!< [31..0] Afe Trim reg0.                                                    */
6822     } AFETRIM0_b;
6823   } ;
6824 
6825   union {
6826     __IOM uint32_t AFETRIM1;                    /*!< (@ 0x0000007C) Afe Trim reg1                                              */
6827 
6828     struct {
6829       __IOM uint32_t AFETRIM1   : 32;           /*!< [31..0] Afe Trim reg1.                                                    */
6830     } AFETRIM1_b;
6831   } ;
6832 
6833   union {
6834     __IOM uint32_t AFETRIM2;                    /*!< (@ 0x00000080) Afe Trim reg2                                              */
6835 
6836     struct {
6837       __IOM uint32_t AFETRIM2   : 32;           /*!< [31..0] Afe Trim reg2.                                                    */
6838     } AFETRIM2_b;
6839   } ;
6840 
6841   union {
6842     __IOM uint32_t AFETRIM3;                    /*!< (@ 0x00000084) Afe Trim reg3                                              */
6843 
6844     struct {
6845       __IOM uint32_t AFETRIM3   : 32;           /*!< [31..0] Afe Trim reg3.                                                    */
6846     } AFETRIM3_b;
6847   } ;
6848   __IM  uint32_t  RESERVED1[4];
6849 
6850   union {
6851     __IOM uint32_t ERRORAUTORCOV;               /*!< (@ 0x00000098) Errir ayti recivert register                               */
6852 
6853     struct {
6854       __IOM uint32_t ECCMULERRCLR : 1;          /*!< [0..0] if this bit is set to 1, Ecc_mul_err_clr error recovery
6855                                                      action is taken immediately by DSI TX                                     */
6856       __IOM uint32_t INVLDDTCLR : 1;            /*!< [1..1] If this bit is set to 1, Invld_dt_clr error recovery
6857                                                      action is taken immediately by DSI TX                                     */
6858       __IOM uint32_t HICONTCLR  : 1;            /*!< [2..2] If this bit is set to 1, Hi_cont_clr error recover action
6859                                                      is taken immediately by DSI TX                                            */
6860       __IOM uint32_t LOCONTCLR  : 1;            /*!< [3..3] If this bit is set to 1, lo_cont_clr error recovery action
6861                                                      is taken immediately by DSI TX                                            */
6862       __IOM uint32_t HSRXTIMEOUTCLR : 1;        /*!< [4..4] If this bit is set to 1, Hs_rx_timeout_clr error recovery
6863                                                      action is taken immediately by DSI TX                                     */
6864       __IOM uint32_t LPRXTIMEOUTCLR : 1;        /*!< [5..5] If this bit is set to 1, lp_rx_timeout_clr error recovery
6865                                                      action is taken immediately by DSI TX                                     */
6866             uint32_t            : 26;
6867     } ERRORAUTORCOV_b;
6868   } ;
6869 
6870   union {
6871     __IOM uint32_t MIPIDIRDPIDIFF;              /*!< (@ 0x0000009C) Mipi direction DPI difference                              */
6872 
6873     struct {
6874       __IOM uint32_t MIPIDIR    : 1;            /*!< [0..0] This field provides the direction of MIPI bus;                     */
6875             uint32_t            : 14;
6876       __IOM uint32_t DPIHIGH    : 1;            /*!< [15..15] This field provides information to check DPI line time
6877                                                      is greater or DSI line time is greater                                    */
6878       __IOM uint32_t DPIDIFF    : 16;           /*!< [31..16] This field provides the difference in one line time
6879                                                      between DPI and DSI                                                       */
6880     } MIPIDIRDPIDIFF_b;
6881   } ;
6882 
6883   union {
6884     __IOM uint32_t DATALANEPOLSWAP;             /*!< (@ 0x000000A0) Data lane polarity swap register                           */
6885 
6886     struct {
6887       __IOM uint32_t DATALNPOLSWAP : 4;         /*!< [3..0] Data lane Polarity sw                                              */
6888             uint32_t            : 28;
6889     } DATALANEPOLSWAP_b;
6890   } ;
6891 } DSI_Type;                                     /*!< Size = 164 (0xa4)                                                         */
6892 
6893 
6894 
6895 /* =========================================================================================================================== */
6896 /* ================                                            DSP                                            ================ */
6897 /* =========================================================================================================================== */
6898 
6899 
6900 /**
6901   * @brief DSP Control Interface (DSP)
6902   */
6903 
6904 typedef struct {                                /*!< (@ 0x40100000) DSP Structure                                              */
6905   __IM  uint32_t  RESERVED[16];
6906 
6907   union {
6908     __IOM uint32_t MUTEX0;                      /*!< (@ 0x00000040) MUTEX 0                                                    */
6909 
6910     struct {
6911       __IOM uint32_t MUTEX0     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6912                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6913             uint32_t            : 29;
6914     } MUTEX0_b;
6915   } ;
6916 
6917   union {
6918     __IOM uint32_t MUTEX1;                      /*!< (@ 0x00000044) MUTEX 1                                                    */
6919 
6920     struct {
6921       __IOM uint32_t MUTEX1     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6922                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6923             uint32_t            : 29;
6924     } MUTEX1_b;
6925   } ;
6926 
6927   union {
6928     __IOM uint32_t MUTEX2;                      /*!< (@ 0x00000048) MUTEX 2                                                    */
6929 
6930     struct {
6931       __IOM uint32_t MUTEX2     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6932                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6933             uint32_t            : 29;
6934     } MUTEX2_b;
6935   } ;
6936 
6937   union {
6938     __IOM uint32_t MUTEX3;                      /*!< (@ 0x0000004C) MUTEX 3                                                    */
6939 
6940     struct {
6941       __IOM uint32_t MUTEX3     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6942                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6943             uint32_t            : 29;
6944     } MUTEX3_b;
6945   } ;
6946 
6947   union {
6948     __IOM uint32_t MUTEX4;                      /*!< (@ 0x00000050) MUTEX 4                                                    */
6949 
6950     struct {
6951       __IOM uint32_t MUTEX4     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6952                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6953             uint32_t            : 29;
6954     } MUTEX4_b;
6955   } ;
6956 
6957   union {
6958     __IOM uint32_t MUTEX5;                      /*!< (@ 0x00000054) MUTEX 5                                                    */
6959 
6960     struct {
6961       __IOM uint32_t MUTEX5     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6962                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6963             uint32_t            : 29;
6964     } MUTEX5_b;
6965   } ;
6966 
6967   union {
6968     __IOM uint32_t MUTEX6;                      /*!< (@ 0x00000058) MUTEX 6                                                    */
6969 
6970     struct {
6971       __IOM uint32_t MUTEX6     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6972                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6973             uint32_t            : 29;
6974     } MUTEX6_b;
6975   } ;
6976 
6977   union {
6978     __IOM uint32_t MUTEX7;                      /*!< (@ 0x0000005C) MUTEX 7                                                    */
6979 
6980     struct {
6981       __IOM uint32_t MUTEX7     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
6982                                                      owns mutex, 100=DSP1 owns mutex)                                          */
6983             uint32_t            : 29;
6984     } MUTEX7_b;
6985   } ;
6986   __IM  uint32_t  RESERVED1[8];
6987 
6988   union {
6989     __IOM uint32_t CPUMBINTSET;                 /*!< (@ 0x00000080) CPU Mailbox Interrupt Set                                  */
6990 
6991     struct {
6992       __IOM uint32_t CPUMBINTSET : 32;          /*!< [31..0] CPU Mailbox interrupt Set. The corresponding data bit
6993                                                      will set the interrupt.                                                   */
6994     } CPUMBINTSET_b;
6995   } ;
6996 
6997   union {
6998     __IOM uint32_t CPUMBINTCLR;                 /*!< (@ 0x00000084) CPU Mailbox Interrupt Clear                                */
6999 
7000     struct {
7001       __IOM uint32_t CPUMBINTCLR : 32;          /*!< [31..0] CPU Mailbox interrupt Clear. The corresponding data
7002                                                      bit will clear the interrupt.                                             */
7003     } CPUMBINTCLR_b;
7004   } ;
7005 
7006   union {
7007     __IOM uint32_t CPUMBINTSTAT;                /*!< (@ 0x00000088) CPU Mailbox Interrupt Status                               */
7008 
7009     struct {
7010       __IOM uint32_t CPUMBINTSTAT : 32;         /*!< [31..0] CPU CPU Mailbox interrupt status                                  */
7011     } CPUMBINTSTAT_b;
7012   } ;
7013 
7014   union {
7015     __IOM uint32_t CPUCPUMBDATA;                /*!< (@ 0x0000008C) CPU CPU Mailbox Data                                       */
7016 
7017     struct {
7018       __IOM uint32_t CPUCPUMBDATA : 32;         /*!< [31..0] CPU CPU Mailbox data                                              */
7019     } CPUCPUMBDATA_b;
7020   } ;
7021 
7022   union {
7023     __IOM uint32_t DSP0CPUMBDATA;               /*!< (@ 0x00000090) DSP0 to CPU Mailbox Data                                   */
7024 
7025     struct {
7026       __IOM uint32_t DSP0CPUMBDATA : 32;        /*!< [31..0] DSP0 to CPU Mailbox data                                          */
7027     } DSP0CPUMBDATA_b;
7028   } ;
7029 
7030   union {
7031     __IOM uint32_t DSP1CPUMBDATA;               /*!< (@ 0x00000094) DSP1 to CPU Mailbox Data                                   */
7032 
7033     struct {
7034       __IOM uint32_t DSP1CPUMBDATA : 32;        /*!< [31..0] DSP1 to CPU Mailbox data                                          */
7035     } DSP1CPUMBDATA_b;
7036   } ;
7037   __IM  uint32_t  RESERVED2[2];
7038 
7039   union {
7040     __IOM uint32_t DSP0MBINTSET;                /*!< (@ 0x000000A0) DSP0 Mailbox Interrupt Set                                 */
7041 
7042     struct {
7043       __IOM uint32_t DSP0MBINTSET : 32;         /*!< [31..0] DSP0 Mailbox interrupt Set. The corresponding data bit
7044                                                      will set the interrupt.                                                   */
7045     } DSP0MBINTSET_b;
7046   } ;
7047 
7048   union {
7049     __IOM uint32_t DSP0MBINTCLR;                /*!< (@ 0x000000A4) DSP0 Mailbox Interrupt Clear                               */
7050 
7051     struct {
7052       __IOM uint32_t DSP0MBINTCLR : 32;         /*!< [31..0] DSP0 Mailbox interrupt Clear. The corresponding data
7053                                                      bit will clear the interrupt.                                             */
7054     } DSP0MBINTCLR_b;
7055   } ;
7056 
7057   union {
7058     __IOM uint32_t DSP0MBINTSTAT;               /*!< (@ 0x000000A8) DSP 0 Mailbox Interrupt Status                             */
7059 
7060     struct {
7061       __IOM uint32_t DSP0MBINTSTAT : 32;        /*!< [31..0] DSP 0 CPU Mailbox interrupt                                       */
7062     } DSP0MBINTSTAT_b;
7063   } ;
7064 
7065   union {
7066     __IOM uint32_t CPUDSP0MBDATA;               /*!< (@ 0x000000AC) CPU to DSP 0 Mailbox Data                                  */
7067 
7068     struct {
7069       __IOM uint32_t CPUDSP0MBDATA : 32;        /*!< [31..0] DSP 0 CPU Mailbox data                                            */
7070     } CPUDSP0MBDATA_b;
7071   } ;
7072 
7073   union {
7074     __IOM uint32_t DSP0DSP0MBDATA;              /*!< (@ 0x000000B0) DSP0 to DSP 0 Mailbox Data                                 */
7075 
7076     struct {
7077       __IOM uint32_t DSP0DSP0MBDATA : 32;       /*!< [31..0] DSP0 to DSP 0 Mailbox data                                        */
7078     } DSP0DSP0MBDATA_b;
7079   } ;
7080 
7081   union {
7082     __IOM uint32_t DSP1DSP0MBDATA;              /*!< (@ 0x000000B4) DSP1 to DSP 0 Mailbox Data                                 */
7083 
7084     struct {
7085       __IOM uint32_t DSP1DSP0MBDATA : 32;       /*!< [31..0] DSP1 to DSP 0 Mailbox data                                        */
7086     } DSP1DSP0MBDATA_b;
7087   } ;
7088   __IM  uint32_t  RESERVED3[2];
7089 
7090   union {
7091     __IOM uint32_t DSP1MBINTSET;                /*!< (@ 0x000000C0) DSP1 Mailbox Interrupt Set                                 */
7092 
7093     struct {
7094       __IOM uint32_t DSP1MBINTSET : 32;         /*!< [31..0] DSP1 Mailbox interrupt Set. The corresponding data bit
7095                                                      will set the interrupt.                                                   */
7096     } DSP1MBINTSET_b;
7097   } ;
7098 
7099   union {
7100     __IOM uint32_t DSP1MBINTCLR;                /*!< (@ 0x000000C4) DSP1 Mailbox Interrupt Clear                               */
7101 
7102     struct {
7103       __IOM uint32_t DSP1MBINTCLR : 32;         /*!< [31..0] DSP1 Mailbox interrupt Clear. The corresponding data
7104                                                      bit will clear the interrupt.                                             */
7105     } DSP1MBINTCLR_b;
7106   } ;
7107 
7108   union {
7109     __IOM uint32_t DSP1MBINTSTAT;               /*!< (@ 0x000000C8) DSP 1 Mailbox Interrupt Status                             */
7110 
7111     struct {
7112       __IOM uint32_t DSP1MBINTSTAT : 32;        /*!< [31..0] DSP 1 CPU Mailbox interrupt                                       */
7113     } DSP1MBINTSTAT_b;
7114   } ;
7115 
7116   union {
7117     __IOM uint32_t CPUDSP1MBDATA;               /*!< (@ 0x000000CC) CPU to DSP 1 Mailbox Data                                  */
7118 
7119     struct {
7120       __IOM uint32_t CPUDSP1MBDATA : 32;        /*!< [31..0] DSP 1 CPU Mailbox data                                            */
7121     } CPUDSP1MBDATA_b;
7122   } ;
7123 
7124   union {
7125     __IOM uint32_t DSP0DSP1MBDATA;              /*!< (@ 0x000000D0) DSP0 to DSP 1 Mailbox Data                                 */
7126 
7127     struct {
7128       __IOM uint32_t DSP0DSP1MBDATA : 32;       /*!< [31..0] DSP0 to DSP 1 Mailbox data                                        */
7129     } DSP0DSP1MBDATA_b;
7130   } ;
7131 
7132   union {
7133     __IOM uint32_t DSP1DSP1MBDATA;              /*!< (@ 0x000000D4) DSP1 to DSP 1 Mailbox Data                                 */
7134 
7135     struct {
7136       __IOM uint32_t DSP1DSP1MBDATA : 32;       /*!< [31..0] DSP1 to DSP 1 Mailbox data                                        */
7137     } DSP1DSP1MBDATA_b;
7138   } ;
7139   __IM  uint32_t  RESERVED4[10];
7140 
7141   union {
7142     __IOM uint32_t DSP0CONTROL;                 /*!< (@ 0x00000100) DSP 0 control settings                                     */
7143 
7144     struct {
7145       __IOM uint32_t DSP0STATVECSEL : 1;        /*!< [0..0] DSP 0 StatVectorSel                                                */
7146       __IOM uint32_t DSP0BRESET : 1;            /*!< [1..1] DSP0 BReset. This is the reset used for Xtensa core.
7147                                                      S/w must clear this reset to use Dsp.                                     */
7148       __IOM uint32_t DSP0DRESET : 1;            /*!< [2..2] DSP0 DReset. This is the reset used for debug functionality
7149                                                      like OCD/TRAX etc.                                                        */
7150       __IOM uint32_t DSP0RUNSTALL : 1;          /*!< [3..3] DSP 0 RunStall. When asserted, DSP 0 will stall until
7151                                                      bit is cleared.                                                           */
7152       __IOM uint32_t DSP0IDMATRIG : 2;          /*!< [5..4] DSP 0 IDMA Trigger Control                                         */
7153             uint32_t            : 2;
7154       __IOM uint32_t DSP0IDMAXTRIGSRC : 23;     /*!< [30..8] DSP 0 IDMA Cross Trigger Source. All enabled sources
7155                                                      are ANDed to generate a trigger enable.
7156                                                      Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE, Bit10: DSP Timer1,
7157                                                      Bit9: DSP Timer0, Bit8: alternate DSP iDMA trigger out                    */
7158             uint32_t            : 1;
7159     } DSP0CONTROL_b;
7160   } ;
7161 
7162   union {
7163     __IOM uint32_t DSP0RESETVEC;                /*!< (@ 0x00000104) DSP 0 Reset Vector                                         */
7164 
7165     struct {
7166       __IOM uint32_t DSP0RESETVEC : 32;         /*!< [31..0] DSP 0 Reset Vector Address.                                       */
7167     } DSP0RESETVEC_b;
7168   } ;
7169 
7170   union {
7171     __IOM uint32_t DSP0IRQMASK;                 /*!< (@ 0x00000108) DSP 0 IRQ Mask                                             */
7172 
7173     struct {
7174       __IOM uint32_t DSP0IRQMASK : 23;          /*!< [22..0] DSP 0 IRQ Mask                                                    */
7175             uint32_t            : 9;
7176     } DSP0IRQMASK_b;
7177   } ;
7178 
7179   union {
7180     __IOM uint32_t DSP0WAKEMASK;                /*!< (@ 0x0000010C) DSP 0 IRQ Wake Mask                                        */
7181 
7182     struct {
7183       __IOM uint32_t DSP0WAKEMASK : 23;         /*!< [22..0] DSP 0 IRQ Wake Mask                                               */
7184             uint32_t            : 9;
7185     } DSP0WAKEMASK_b;
7186   } ;
7187 
7188   union {
7189     __IOM uint32_t DSP0RAWIRQSTAT31to0;         /*!< (@ 0x00000110) DSP 0 Raw IRQ31-0 Status                                   */
7190 
7191     struct {
7192       __IOM uint32_t DSP0RAWIRQSTAT31to0 : 32;  /*!< [31..0] DSP 0 Raw IRQ31-0 Status                                          */
7193     } DSP0RAWIRQSTAT31to0_b;
7194   } ;
7195 
7196   union {
7197     __IOM uint32_t DSP0RAWIRQSTAT63to32;        /*!< (@ 0x00000114) DSP 0 Raw IRQ63-32 Status                                  */
7198 
7199     struct {
7200       __IOM uint32_t DSP0RAWIRQSTAT63to32 : 32; /*!< [31..0] DSP 0 Raw IRQ63-32 Status                                         */
7201     } DSP0RAWIRQSTAT63to32_b;
7202   } ;
7203 
7204   union {
7205     __IOM uint32_t DSP0RAWIRQSTAT95to64;        /*!< (@ 0x00000118) DSP 0 Raw IRQ95-64 Status                                  */
7206 
7207     struct {
7208       __IOM uint32_t DSP0RAWIRQSTAT95to64 : 32; /*!< [31..0] DSP 0 Raw IRQ95-64 Status                                         */
7209     } DSP0RAWIRQSTAT95to64_b;
7210   } ;
7211   __IM  uint32_t  RESERVED5;
7212 
7213   union {
7214     __IOM uint32_t DSP0L2LVLINT;                /*!< (@ 0x00000120) DSP 0 L2 Level Interrupt Mux                               */
7215 
7216     struct {
7217       __IOM uint32_t DSP0L2LVLINT : 19;         /*!< [18..0] DSP 0 L2 Level Interrupt Mux                                      */
7218             uint32_t            : 13;
7219     } DSP0L2LVLINT_b;
7220   } ;
7221 
7222   union {
7223     __IOM uint32_t DSP0L3LVLINT;                /*!< (@ 0x00000124) DSP 0 L3 Level Interrupt Mux                               */
7224 
7225     struct {
7226       __IOM uint32_t DSP0L3LVLINT : 19;         /*!< [18..0] DSP 0 L3 Level Interrupt Mux                                      */
7227             uint32_t            : 13;
7228     } DSP0L3LVLINT_b;
7229   } ;
7230 
7231   union {
7232     __IOM uint32_t DSP0L4LVLINT;                /*!< (@ 0x00000128) DSP 0 L4 Level Interrupt Mux                               */
7233 
7234     struct {
7235       __IOM uint32_t DSP0L4LVLINT : 19;         /*!< [18..0] DSP 0 L4 Level Interrupt Mux                                      */
7236             uint32_t            : 13;
7237     } DSP0L4LVLINT_b;
7238   } ;
7239 
7240   union {
7241     __IOM uint32_t DSP0L5LVLINT;                /*!< (@ 0x0000012C) DSP 0 L5 Level Interrupt Mux                               */
7242 
7243     struct {
7244       __IOM uint32_t DSP0L5LVLINT : 19;         /*!< [18..0] DSP 0 L5 Level Interrupt Mux                                      */
7245             uint32_t            : 13;
7246     } DSP0L5LVLINT_b;
7247   } ;
7248 
7249   union {
7250     __IOM uint32_t DSP0IDMATRIGCTL;             /*!< (@ 0x00000130) DSP 0 IDMA Trigger Control and Status                      */
7251 
7252     struct {
7253       __IOM uint32_t DSP0IDMATRIGSTAT : 1;      /*!< [0..0] DSP 0 iDMA Trigger Status                                          */
7254             uint32_t            : 3;
7255       __IOM uint32_t DSP0IDMATRIGPULSE : 1;     /*!< [4..4] DSP 0 iDMA Trigger Pulse - When written a '1', this will
7256                                                      cause a single step enable (valid only when IDMATRIG is
7257                                                      set to SSTEP)                                                             */
7258             uint32_t            : 27;
7259     } DSP0IDMATRIGCTL_b;
7260   } ;
7261   __IM  uint32_t  RESERVED6[3];
7262 
7263   union {
7264     __IOM uint32_t DSP0INTORMASK31TO0A;         /*!< (@ 0x00000140) DSP0 Interrupt OR Mask A for IRQ31-0                       */
7265 
7266     struct {
7267       __IOM uint32_t DSP0INTMCUIOORMASKA : 32;  /*!< [31..0] DSP0 MCU IO Interrupt OR Mask A                                   */
7268     } DSP0INTORMASK31TO0A_b;
7269   } ;
7270 
7271   union {
7272     __IOM uint32_t DSP0INTORMASK63TO32A;        /*!< (@ 0x00000144) DSP0 Interrupt OR Mask A for IRQ63-32                      */
7273 
7274     struct {
7275       __IOM uint32_t DSP0TMRORMASKA : 10;       /*!< [9..0] DSP0 Timer Interrupt OR Mask A                                     */
7276             uint32_t            : 2;
7277       __IOM uint32_t DSP0I2SORMASKA : 4;        /*!< [15..12] DSP0 I2S Interrupt OR Mask A                                     */
7278       __IOM uint32_t DSP0PDMORMASKA : 4;        /*!< [19..16] DSP0 PDM Interrupt OR Mask A                                     */
7279             uint32_t            : 4;
7280       __IOM uint32_t DSP0GPIOORMASKA : 6;       /*!< [29..24] DSP0 GPIO Interrupt OR Mask A                                    */
7281             uint32_t            : 2;
7282     } DSP0INTORMASK63TO32A_b;
7283   } ;
7284 
7285   union {
7286     __IOM uint32_t DSP0INTORMASK95TO64A;        /*!< (@ 0x00000148) DSP0 Interrupt OR Mask A for IRQ95-64                      */
7287 
7288     struct {
7289       __IOM uint32_t DSP0MBINTORMASKA : 32;     /*!< [31..0] DSP0 Mailbox Interrupt OR Mask A                                  */
7290     } DSP0INTORMASK95TO64A_b;
7291   } ;
7292   __IM  uint32_t  RESERVED7;
7293 
7294   union {
7295     __IOM uint32_t DSP0INTORMASK31to0B;         /*!< (@ 0x00000150) DSP0 Interrupt OR Mask B for IRQ31-0                       */
7296 
7297     struct {
7298       __IOM uint32_t DSP0INTMCUIOORMASKB : 32;  /*!< [31..0] DSP0 MCU IO Interrupt OR Mask B                                   */
7299     } DSP0INTORMASK31to0B_b;
7300   } ;
7301 
7302   union {
7303     __IOM uint32_t DSP0INTORMASK63TO32B;        /*!< (@ 0x00000154) DSP0 Interrupt OR Mask A for IRQ63-32                      */
7304 
7305     struct {
7306       __IOM uint32_t DSP0TMRORMASKB : 10;       /*!< [9..0] DSP0 Timer Interrupt OR Mask B                                     */
7307             uint32_t            : 2;
7308       __IOM uint32_t DSP0I2SORMASKB : 4;        /*!< [15..12] DSP0 I2S Interrupt OR Mask B                                     */
7309       __IOM uint32_t DSP0PDMORMASKB : 4;        /*!< [19..16] DSP0 PDM Interrupt OR Mask B                                     */
7310             uint32_t            : 4;
7311       __IOM uint32_t DSP0GPIOORMASKB : 6;       /*!< [29..24] DSP0 GPIO Interrupt OR Mask B                                    */
7312             uint32_t            : 2;
7313     } DSP0INTORMASK63TO32B_b;
7314   } ;
7315 
7316   union {
7317     __IOM uint32_t DSP0INTORMASK95TO64B;        /*!< (@ 0x00000158) DSP0 Interrupt OR Mask B for IRQ95-64                      */
7318 
7319     struct {
7320       __IOM uint32_t DSP0MBINTORMASKB : 32;     /*!< [31..0] DSP0 Mailbox Interrupt OR Mask B                                  */
7321     } DSP0INTORMASK95TO64B_b;
7322   } ;
7323   __IM  uint32_t  RESERVED8;
7324 
7325   union {
7326     __IOM uint32_t DSP0INTENIRQ31TO0;           /*!< (@ 0x00000160) DSP0 INT Enable for IRQ31-0                                */
7327 
7328     struct {
7329       __IOM uint32_t DSP0INTENIRQ31TO0 : 32;    /*!< [31..0] DSP0 INT Enable for IRQ31-0                                       */
7330     } DSP0INTENIRQ31TO0_b;
7331   } ;
7332 
7333   union {
7334     __IOM uint32_t DSP0INTENIRQ63TO32;          /*!< (@ 0x00000164) DSP0 INT Enable for IRQ63-32                               */
7335 
7336     struct {
7337       __IOM uint32_t DSP0INTENIRQ63TO32 : 32;   /*!< [31..0] DSP0 INT Enable for IRQ63-32                                      */
7338     } DSP0INTENIRQ63TO32_b;
7339   } ;
7340 
7341   union {
7342     __IOM uint32_t DSP0INTENIRQ95TO64;          /*!< (@ 0x00000168) DSP0 INT Enable for IRQ95-64                               */
7343 
7344     struct {
7345       __IOM uint32_t DSP0INTENIRQ95TO64 : 32;   /*!< [31..0] DSP0 INT Enable for IRQ95-64                                      */
7346     } DSP0INTENIRQ95TO64_b;
7347   } ;
7348   __IM  uint32_t  RESERVED9[37];
7349 
7350   union {
7351     __IOM uint32_t DSP1CONTROL;                 /*!< (@ 0x00000200) DSP 1 control settings                                     */
7352 
7353     struct {
7354       __IOM uint32_t DSP1STATVECSEL : 1;        /*!< [0..0] DSP 1 StatVectorSel                                                */
7355       __IOM uint32_t DSP1BRESET : 1;            /*!< [1..1] DSP1 BReset. This is the reset used for Xtensa core.
7356                                                      S/w must clear this reset to use Dsp.                                     */
7357       __IOM uint32_t DSP1DRESET : 1;            /*!< [2..2] DSP1 DReset. This is the reset used for debug functionality
7358                                                      like OCD/TRAX etc.                                                        */
7359       __IOM uint32_t DSP1RUNSTALL : 1;          /*!< [3..3] DSP 1 RunStall. When asserted, DSP 1 will stall until
7360                                                      bit is cleared.                                                           */
7361       __IOM uint32_t DSP1IDMATRIG : 2;          /*!< [5..4] DSP 1 IDMA Trigger Control                                         */
7362             uint32_t            : 2;
7363       __IOM uint32_t DSP1IDMAXTRIGSRC : 23;     /*!< [30..8] DSP 1 IDMA Cross Trigger Source. All enabled sources
7364                                                      are ANDed to generate a trigger enable.
7365                                                      Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE, Bit10: DSP Timer1,
7366                                                      Bit9: DSP Timer0, Bit8: alternate DSP iDMA trigger out                    */
7367             uint32_t            : 1;
7368     } DSP1CONTROL_b;
7369   } ;
7370 
7371   union {
7372     __IOM uint32_t DSP1RESETVEC;                /*!< (@ 0x00000204) DSP 1 Reset Vector                                         */
7373 
7374     struct {
7375       __IOM uint32_t DSP1RESETVEC : 32;         /*!< [31..0] DSP 1 Reset Vector Address.                                       */
7376     } DSP1RESETVEC_b;
7377   } ;
7378 
7379   union {
7380     __IOM uint32_t DSP1IRQMASK;                 /*!< (@ 0x00000208) DSP 1 IRQ Mask                                             */
7381 
7382     struct {
7383       __IOM uint32_t DSP1IRQMASK : 23;          /*!< [22..0] DSP 1 IRQ Mask                                                    */
7384             uint32_t            : 9;
7385     } DSP1IRQMASK_b;
7386   } ;
7387 
7388   union {
7389     __IOM uint32_t DSP1WAKEMASK;                /*!< (@ 0x0000020C) DSP 1 IRQ Wake Mask                                        */
7390 
7391     struct {
7392       __IOM uint32_t DSP1WAKEMASK : 23;         /*!< [22..0] DSP 1 IRQ Wake Mask                                               */
7393             uint32_t            : 9;
7394     } DSP1WAKEMASK_b;
7395   } ;
7396 
7397   union {
7398     __IOM uint32_t DSP1RAWIRQSTAT31to0;         /*!< (@ 0x00000210) DSP 1 Raw IRQ31-0 Status                                   */
7399 
7400     struct {
7401       __IOM uint32_t DSP1RAWIRQSTAT31to0 : 32;  /*!< [31..0] DSP 1 Raw IRQ31-0 Status                                          */
7402     } DSP1RAWIRQSTAT31to0_b;
7403   } ;
7404 
7405   union {
7406     __IOM uint32_t DSP1RAWIRQSTAT63to32;        /*!< (@ 0x00000214) DSP 1 Raw IRQ63-32 Status                                  */
7407 
7408     struct {
7409       __IOM uint32_t DSP1RAWIRQSTAT63to32 : 32; /*!< [31..0] DSP 1 Raw IRQ63-32 Status                                         */
7410     } DSP1RAWIRQSTAT63to32_b;
7411   } ;
7412 
7413   union {
7414     __IOM uint32_t DSP1RAWIRQSTAT95to64;        /*!< (@ 0x00000218) DSP 1 Raw IRQ95-64 Status                                  */
7415 
7416     struct {
7417       __IOM uint32_t DSP1RAWIRQSTAT95to64 : 32; /*!< [31..0] DSP 1 Raw IRQ95-64 Status                                         */
7418     } DSP1RAWIRQSTAT95to64_b;
7419   } ;
7420   __IM  uint32_t  RESERVED10;
7421 
7422   union {
7423     __IOM uint32_t DSP1L2LVLINT;                /*!< (@ 0x00000220) DSP 1 L2 Level Interrupt Mux                               */
7424 
7425     struct {
7426       __IOM uint32_t DSP1L2LVLINT : 19;         /*!< [18..0] DSP 1 L2 Level Interrupt Mux                                      */
7427             uint32_t            : 13;
7428     } DSP1L2LVLINT_b;
7429   } ;
7430 
7431   union {
7432     __IOM uint32_t DSP1L3LVLINT;                /*!< (@ 0x00000224) DSP 1 L3 Level Interrupt Mux                               */
7433 
7434     struct {
7435       __IOM uint32_t DSP1L3LVLINT : 19;         /*!< [18..0] DSP 1 L3 Level Interrupt Mux                                      */
7436             uint32_t            : 13;
7437     } DSP1L3LVLINT_b;
7438   } ;
7439 
7440   union {
7441     __IOM uint32_t DSP1L4LVLINT;                /*!< (@ 0x00000228) DSP 1 L4 Level Interrupt Mux                               */
7442 
7443     struct {
7444       __IOM uint32_t DSP1L4LVLINT : 19;         /*!< [18..0] DSP 1 L4 Level Interrupt Mux                                      */
7445             uint32_t            : 13;
7446     } DSP1L4LVLINT_b;
7447   } ;
7448 
7449   union {
7450     __IOM uint32_t DSP1L5LVLINT;                /*!< (@ 0x0000022C) DSP 1 L5 Level Interrupt Mux                               */
7451 
7452     struct {
7453       __IOM uint32_t DSP1L5LVLINT : 19;         /*!< [18..0] DSP 1 L5 Level Interrupt Mux                                      */
7454             uint32_t            : 13;
7455     } DSP1L5LVLINT_b;
7456   } ;
7457 
7458   union {
7459     __IOM uint32_t DSP1IDMATRIGCTL;             /*!< (@ 0x00000230) DSP 1 IDMA Trigger Control and Status                      */
7460 
7461     struct {
7462       __IOM uint32_t DSP1IDMATRIGSTAT : 1;      /*!< [0..0] DSP 1 iDMA Trigger Status                                          */
7463             uint32_t            : 3;
7464       __IOM uint32_t DSP1IDMATRIGPULSE : 1;     /*!< [4..4] DSP 1 iDMA Trigger Pulse - When written a '1', this will
7465                                                      cause a single step enable (valid only when IDMATRIG is
7466                                                      set to SSTEP)                                                             */
7467             uint32_t            : 27;
7468     } DSP1IDMATRIGCTL_b;
7469   } ;
7470   __IM  uint32_t  RESERVED11[3];
7471 
7472   union {
7473     __IOM uint32_t DSP1INTORMASK31TO0A;         /*!< (@ 0x00000240) DSP1 Interrupt OR Mask A for IRQ31-0                       */
7474 
7475     struct {
7476       __IOM uint32_t DSP1INTMCUIOORMASKA : 32;  /*!< [31..0] DSP1 MCU IO Interrupt OR Mask A                                   */
7477     } DSP1INTORMASK31TO0A_b;
7478   } ;
7479 
7480   union {
7481     __IOM uint32_t DSP1INTORMASK63TO32A;        /*!< (@ 0x00000244) DSP1 Interrupt OR Mask A for IRQ63-32                      */
7482 
7483     struct {
7484       __IOM uint32_t DSP1TMRORMASKA : 10;       /*!< [9..0] DSP1 Timer Interrupt OR Mask A                                     */
7485             uint32_t            : 2;
7486       __IOM uint32_t DSP1I2SORMASKA : 4;        /*!< [15..12] DSP1 I2S Interrupt OR Mask A                                     */
7487       __IOM uint32_t DSP1PDMORMASKA : 4;        /*!< [19..16] DSP1 PDM Interrupt OR Mask A                                     */
7488             uint32_t            : 4;
7489       __IOM uint32_t DSP1GPIOORMASKA : 6;       /*!< [29..24] DSP1 GPIO Interrupt OR Mask A                                    */
7490             uint32_t            : 2;
7491     } DSP1INTORMASK63TO32A_b;
7492   } ;
7493 
7494   union {
7495     __IOM uint32_t DSP1INTORMASK95TO64A;        /*!< (@ 0x00000248) DSP1 Interrupt OR Mask A for IRQ95-64                      */
7496 
7497     struct {
7498       __IOM uint32_t DSP1MBINTORMASKA : 32;     /*!< [31..0] DSP1 Mailbox Interrupt OR Mask A                                  */
7499     } DSP1INTORMASK95TO64A_b;
7500   } ;
7501   __IM  uint32_t  RESERVED12;
7502 
7503   union {
7504     __IOM uint32_t DSP1INTORMASK31to0B;         /*!< (@ 0x00000250) DSP1 Interrupt OR Mask B for IRQ31-0                       */
7505 
7506     struct {
7507       __IOM uint32_t DSP1INTMCUIOORMASKB : 32;  /*!< [31..0] DSP1 MCU IO Interrupt OR Mask B                                   */
7508     } DSP1INTORMASK31to0B_b;
7509   } ;
7510 
7511   union {
7512     __IOM uint32_t DSP1INTORMASK63TO32B;        /*!< (@ 0x00000254) DSP1 Interrupt OR Mask A for IRQ63-32                      */
7513 
7514     struct {
7515       __IOM uint32_t DSP1TMRORMASKB : 10;       /*!< [9..0] DSP1 Timer Interrupt OR Mask B                                     */
7516             uint32_t            : 2;
7517       __IOM uint32_t DSP1I2SORMASKB : 4;        /*!< [15..12] DSP1 I2S Interrupt OR Mask B                                     */
7518       __IOM uint32_t DSP1PDMORMASKB : 4;        /*!< [19..16] DSP1 PDM Interrupt OR Mask B                                     */
7519             uint32_t            : 4;
7520       __IOM uint32_t DSP1GPIOORMASKB : 6;       /*!< [29..24] DSP1 GPIO Interrupt OR Mask B                                    */
7521             uint32_t            : 2;
7522     } DSP1INTORMASK63TO32B_b;
7523   } ;
7524 
7525   union {
7526     __IOM uint32_t DSP1INTORMASK95TO64B;        /*!< (@ 0x00000258) DSP1 Interrupt OR Mask B for IRQ95-64                      */
7527 
7528     struct {
7529       __IOM uint32_t DSP1MBINTORMASKB : 32;     /*!< [31..0] DSP1 Mailbox Interrupt OR Mask B                                  */
7530     } DSP1INTORMASK95TO64B_b;
7531   } ;
7532   __IM  uint32_t  RESERVED13;
7533 
7534   union {
7535     __IOM uint32_t DSP1INTENIRQ31TO0;           /*!< (@ 0x00000260) DSP1 INT Enable for IRQ31-0                                */
7536 
7537     struct {
7538       __IOM uint32_t DSP1INTENIRQ31TO0 : 32;    /*!< [31..0] DSP1 INT Enable for IRQ31-0                                       */
7539     } DSP1INTENIRQ31TO0_b;
7540   } ;
7541 
7542   union {
7543     __IOM uint32_t DSP1INTENIRQ63TO32;          /*!< (@ 0x00000264) DSP1 INT Enable for IRQ63-32                               */
7544 
7545     struct {
7546       __IOM uint32_t DSP1INTENIRQ63TO32 : 32;   /*!< [31..0] DSP1 INT Enable for IRQ63-32                                      */
7547     } DSP1INTENIRQ63TO32_b;
7548   } ;
7549 
7550   union {
7551     __IOM uint32_t DSP1INTENIRQ95TO64;          /*!< (@ 0x00000268) DSP1 INT Enable for IRQ95-64                               */
7552 
7553     struct {
7554       __IOM uint32_t DSP1INTENIRQ95TO64 : 32;   /*!< [31..0] DSP1 INT Enable for IRQ95-64                                      */
7555     } DSP1INTENIRQ95TO64_b;
7556   } ;
7557 } DSP_Type;                                     /*!< Size = 620 (0x26c)                                                        */
7558 
7559 
7560 
7561 /* =========================================================================================================================== */
7562 /* ================                                           FPIO                                            ================ */
7563 /* =========================================================================================================================== */
7564 
7565 
7566 /**
7567   * @brief Fast PIO access (FPIO)
7568   */
7569 
7570 typedef struct {                                /*!< (@ 0x48001000) FPIO Structure                                             */
7571 
7572   union {
7573     __IOM uint32_t RD0;                         /*!< (@ 0x00000000) GPIO Input 0 (31-0)                                        */
7574 
7575     struct {
7576       __IOM uint32_t RD0        : 32;           /*!< [31..0] GPIO31-0 Reads pin state - read only. Returns the pad
7577                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
7578                                                      is active and RDZERO is inactive.                                         */
7579     } RD0_b;
7580   } ;
7581 
7582   union {
7583     __IOM uint32_t RD1;                         /*!< (@ 0x00000004) GPIO Input 1 (63-32)                                       */
7584 
7585     struct {
7586       __IOM uint32_t RD1        : 32;           /*!< [31..0] GPIO63-32 Reads pin state - read only. Returns the pad
7587                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
7588                                                      is active and RDZERO is inactive.                                         */
7589     } RD1_b;
7590   } ;
7591 
7592   union {
7593     __IOM uint32_t RD2;                         /*!< (@ 0x00000008) GPIO Input 2 (95-64)                                       */
7594 
7595     struct {
7596       __IOM uint32_t RD2        : 32;           /*!< [31..0] GPIO95-64 Reads pin state - read only. Returns the pad
7597                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
7598                                                      is active and RDZERO is inactive.                                         */
7599     } RD2_b;
7600   } ;
7601 
7602   union {
7603     __IOM uint32_t RD3;                         /*!< (@ 0x0000000C) GPIO Input 3 (127-96)                                      */
7604 
7605     struct {
7606       __IOM uint32_t RD3        : 32;           /*!< [31..0] GPIO127-96 Reads pin state - read only. Returns the
7607                                                      pad pin state for pins 0-31 if the PINCFG's input enable
7608                                                      (INPEN) is active and RDZERO is inactive.                                 */
7609     } RD3_b;
7610   } ;
7611 
7612   union {
7613     __IOM uint32_t WT0;                         /*!< (@ 0x00000010) GPIO Output 0 (31-0)                                       */
7614 
7615     struct {
7616       __IOM uint32_t WT0        : 32;           /*!< [31..0] GPIO31-0 Reads or writes pin state. Writes of 1 bits
7617                                                      set output pad signal if the GPIO is enabled for output.
7618                                                      Reads return status, including sets/clears through the
7619                                                      WTS and WTC registers.                                                    */
7620     } WT0_b;
7621   } ;
7622 
7623   union {
7624     __IOM uint32_t WT1;                         /*!< (@ 0x00000014) GPIO Output 1 (63-32)                                      */
7625 
7626     struct {
7627       __IOM uint32_t WT1        : 32;           /*!< [31..0] GPIO63-32 Reads or writes pin state. Writes of 1 bits
7628                                                      set output pad signal if the GPIO is enabled for output.
7629                                                      Reads return status, including sets/clears through the
7630                                                      WTS and WTC registers.                                                    */
7631     } WT1_b;
7632   } ;
7633 
7634   union {
7635     __IOM uint32_t WT2;                         /*!< (@ 0x00000018) GPIO Output 2 (95-64)                                      */
7636 
7637     struct {
7638       __IOM uint32_t WT2        : 32;           /*!< [31..0] GPIO95-64 Reads or writes pin state. Writes of 1 bits
7639                                                      set output pad signal if the GPIO is enabled for output.
7640                                                      Reads return status, including sets/clears through the
7641                                                      WTS and WTC registers.                                                    */
7642     } WT2_b;
7643   } ;
7644 
7645   union {
7646     __IOM uint32_t WT3;                         /*!< (@ 0x0000001C) GPIO Output 3 (127-96)                                     */
7647 
7648     struct {
7649       __IOM uint32_t WT3        : 32;           /*!< [31..0] GPIO127-96 Reads or writes pin state. Writes of 1 bits
7650                                                      set output pad signal if the GPIO is enabled for output.
7651                                                      Reads return status, including sets/clears through the
7652                                                      WTS and WTC registers.                                                    */
7653     } WT3_b;
7654   } ;
7655 
7656   union {
7657     __IOM uint32_t WTS0;                        /*!< (@ 0x00000020) GPIO Output Set 0 (31-0)                                   */
7658 
7659     struct {
7660       __IOM uint32_t WTS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin state. Writing a 1 to any bit sets
7661                                                      the corresponding bit in the WT register if the GPIO is
7662                                                      enabled for output. Writing a value of 0 has no effect
7663                                                      on the corresponding bit in the WT register. Status reads
7664                                                      should be made via the WT Register.                                       */
7665     } WTS0_b;
7666   } ;
7667 
7668   union {
7669     __IOM uint32_t WTS1;                        /*!< (@ 0x00000024) GPIO Output Set 1 (63-32)                                  */
7670 
7671     struct {
7672       __IOM uint32_t WTS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin state. Writing a 1 to any bit sets
7673                                                      the corresponding bit in the WT register if the GPIO is
7674                                                      enabled for output. Writing a value of 0 has no effect
7675                                                      on the corresponding bit in the WT register. Status reads
7676                                                      should be made via the WT Register.                                       */
7677     } WTS1_b;
7678   } ;
7679 
7680   union {
7681     __IOM uint32_t WTS2;                        /*!< (@ 0x00000028) GPIO Output Set 2 (95-64)                                  */
7682 
7683     struct {
7684       __IOM uint32_t WTS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin state. Writing a 1 to any bit sets
7685                                                      the corresponding bit in the WT register if the GPIO is
7686                                                      enabled for output. Writing a value of 0 has no effect
7687                                                      on the corresponding bit in the WT register. Status reads
7688                                                      should be made via the WT Register.                                       */
7689     } WTS2_b;
7690   } ;
7691 
7692   union {
7693     __IOM uint32_t WTS3;                        /*!< (@ 0x0000002C) GPIO Output Set 3 (127-96)                                 */
7694 
7695     struct {
7696       __IOM uint32_t WTS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin state. Writing a 1 to any bit sets
7697                                                      the corresponding bit in the WT register if the GPIO is
7698                                                      enabled for output. Writing a value of 0 has no effect
7699                                                      on the corresponding bit in the WT register. Status reads
7700                                                      should be made via the WT Register.                                       */
7701     } WTS3_b;
7702   } ;
7703 
7704   union {
7705     __IOM uint32_t WTC0;                        /*!< (@ 0x00000030) GPIO Output Clear 0 (31-0)                                 */
7706 
7707     struct {
7708       __IOM uint32_t WTC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin state. Writing a 1 to any bit clears
7709                                                      the corresponding bit in the WT register if the GPIO is
7710                                                      enabled for output. Writing a value of 0 has no effect
7711                                                      on the corresponding bit in the WT register. Status reads
7712                                                      should be made via the WT register.                                       */
7713     } WTC0_b;
7714   } ;
7715 
7716   union {
7717     __IOM uint32_t WTC1;                        /*!< (@ 0x00000034) GPIO Output Clear 1 (63-32)                                */
7718 
7719     struct {
7720       __IOM uint32_t WTC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin state. Writing a 1 to any bit clears
7721                                                      the corresponding bit in the WT register if the GPIO is
7722                                                      enabled for output. Writing a value of 0 has no effect
7723                                                      on the corresponding bit in the WT register. Status reads
7724                                                      should be made via the WT register.                                       */
7725     } WTC1_b;
7726   } ;
7727 
7728   union {
7729     __IOM uint32_t WTC2;                        /*!< (@ 0x00000038) GPIO Output Clear 2 (95-64)                                */
7730 
7731     struct {
7732       __IOM uint32_t WTC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin state. Writing a 1 to any bit clears
7733                                                      the corresponding bit in the WT register if the GPIO is
7734                                                      enabled for output. Writing a value of 0 has no effect
7735                                                      on the corresponding bit in the WT register. Status reads
7736                                                      should be made via the WT register.                                       */
7737     } WTC2_b;
7738   } ;
7739 
7740   union {
7741     __IOM uint32_t WTC3;                        /*!< (@ 0x0000003C) GPIO Output Clear 3 (127-96)                               */
7742 
7743     struct {
7744       __IOM uint32_t WTC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin state. Writing a 1 to any bit
7745                                                      clears the corresponding bit in the WT register if the
7746                                                      GPIO is enabled for output. Writing a value of 0 has no
7747                                                      effect on the corresponding bit in the WT register. Status
7748                                                      reads should be made via the WT register.                                 */
7749     } WTC3_b;
7750   } ;
7751 
7752   union {
7753     __IOM uint32_t EN0;                         /*!< (@ 0x00000040) GPIO Enable 0 (31-0)                                       */
7754 
7755     struct {
7756       __IOM uint32_t EN0        : 32;           /*!< [31..0] GPIO31-0 Enables tri-state pin output. Writing a 1 to
7757                                                      any bit enables, and writing a 0 to any bit disables, the
7758                                                      output for the corresponding GPIO. Reads return output
7759                                                      enable/disable status of GPIO.                                            */
7760     } EN0_b;
7761   } ;
7762 
7763   union {
7764     __IOM uint32_t EN1;                         /*!< (@ 0x00000044) GPIO Enable 1 (63-32)                                      */
7765 
7766     struct {
7767       __IOM uint32_t EN1        : 32;           /*!< [31..0] GPIO63-32 Enables tri-state pin output. Writing a 1
7768                                                      to any bit enables, and writing a 0 to any bit disables,
7769                                                      the output for the corresponding GPIO. Reads return output
7770                                                      enable/disable status of GPIO.                                            */
7771     } EN1_b;
7772   } ;
7773 
7774   union {
7775     __IOM uint32_t EN2;                         /*!< (@ 0x00000048) GPIO Enable 2 (95-64)                                      */
7776 
7777     struct {
7778       __IOM uint32_t EN2        : 32;           /*!< [31..0] GPIO95-64 Enables tri-state pin output. Writing a 1
7779                                                      to any bit enables, and writing a 0 to any bit disables,
7780                                                      the output for the corresponding GPIO. Reads return output
7781                                                      enable/disable status of GPIO.                                            */
7782     } EN2_b;
7783   } ;
7784 
7785   union {
7786     __IOM uint32_t EN3;                         /*!< (@ 0x0000004C) GPIO Enable 3 (127-96)                                     */
7787 
7788     struct {
7789       __IOM uint32_t EN3        : 32;           /*!< [31..0] GPIO127-96 Enables tri-state pin output. Writing a 1
7790                                                      to any bit enables, and writing a 0 to any bit disables,
7791                                                      the output for the corresponding GPIO. Reads return output
7792                                                      enable/disable status of GPIO.                                            */
7793     } EN3_b;
7794   } ;
7795 
7796   union {
7797     __IOM uint32_t ENS0;                        /*!< (@ 0x00000050) GPIO Enable Set 0 (31-0)                                   */
7798 
7799     struct {
7800       __IOM uint32_t ENS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin tri-state output enables. Writing
7801                                                      a 1 to any bit sets the corresponding bit in the EN register.
7802                                                      Writing a value of 0 has no effect on the corresponding
7803                                                      bit in the EN register. Status reads should be made to
7804                                                      the EN Register.                                                          */
7805     } ENS0_b;
7806   } ;
7807 
7808   union {
7809     __IOM uint32_t ENS1;                        /*!< (@ 0x00000054) GPIO Enable Set 1 (63-32)                                  */
7810 
7811     struct {
7812       __IOM uint32_t ENS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin tri-state output enables. Writing
7813                                                      a 1 to any bit sets the corresponding bit in the EN register.
7814                                                      Writing a value of 0 has no effect on the corresponding
7815                                                      bit in the EN register. Status reads should be made to
7816                                                      the EN Register.                                                          */
7817     } ENS1_b;
7818   } ;
7819 
7820   union {
7821     __IOM uint32_t ENS2;                        /*!< (@ 0x00000058) GPIO Enable Set 2 (95-64)                                  */
7822 
7823     struct {
7824       __IOM uint32_t ENS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin tri-state output enables. Writing
7825                                                      a 1 to any bit sets the corresponding bit in the EN register.
7826                                                      Writing a value of 0 has no effect on the corresponding
7827                                                      bit in the EN register. Status reads should be made to
7828                                                      the EN Register.                                                          */
7829     } ENS2_b;
7830   } ;
7831 
7832   union {
7833     __IOM uint32_t ENS3;                        /*!< (@ 0x0000005C) GPIO Enable Set 3 (127-96)                                 */
7834 
7835     struct {
7836       __IOM uint32_t ENS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin tri-state output enables. Writing
7837                                                      a 1 to any bit sets the corresponding bit in the EN register.
7838                                                      Writing a value of 0 has no effect on the corresponding
7839                                                      bit in the EN register. Status reads should be made to
7840                                                      the EN Register.                                                          */
7841     } ENS3_b;
7842   } ;
7843 
7844   union {
7845     __IOM uint32_t ENC0;                        /*!< (@ 0x00000060) GPIO Enable Clear 0 (31-0)                                 */
7846 
7847     struct {
7848       __IOM uint32_t ENC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin tri-state output enables. Writing
7849                                                      a 1 to any bit clears the corresponding bit in the EN register.
7850                                                      Writing a value of 0 has no effect on the corresponding
7851                                                      bit in the EN register. Status reads should be made to
7852                                                      the EN Register.                                                          */
7853     } ENC0_b;
7854   } ;
7855 
7856   union {
7857     __IOM uint32_t ENC1;                        /*!< (@ 0x00000064) GPIO Enable Clear 1 (63-32)                                */
7858 
7859     struct {
7860       __IOM uint32_t ENC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin tri-state output enables. Writing
7861                                                      a 1 to any bit clears the corresponding bit in the EN register.
7862                                                      Writing a value of 0 has no effect on the corresponding
7863                                                      bit in the EN register. Status reads should be made to
7864                                                      the EN Register.                                                          */
7865     } ENC1_b;
7866   } ;
7867 
7868   union {
7869     __IOM uint32_t ENC2;                        /*!< (@ 0x00000068) GPIO Enable Clear 2 (95-64)                                */
7870 
7871     struct {
7872       __IOM uint32_t ENC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin tri-state output enables. Writing
7873                                                      a 1 to any bit clears the corresponding bit in the EN register.
7874                                                      Writing a value of 0 has no effect on the corresponding
7875                                                      bit in the EN register. Status reads should be made to
7876                                                      the EN Register.                                                          */
7877     } ENC2_b;
7878   } ;
7879 
7880   union {
7881     __IOM uint32_t ENC3;                        /*!< (@ 0x0000006C) GPIO Enable Clear 3 (127-96)                               */
7882 
7883     struct {
7884       __IOM uint32_t ENC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin tri-state output enables. Writing
7885                                                      a 1 to any bit clears the corresponding bit in the EN register.
7886                                                      Writing a value of 0 has no effect on the corresponding
7887                                                      bit in the EN register. Status reads should be made to
7888                                                      the EN Register.                                                          */
7889     } ENC3_b;
7890   } ;
7891 } FPIO_Type;                                    /*!< Size = 112 (0x70)                                                         */
7892 
7893 
7894 
7895 /* =========================================================================================================================== */
7896 /* ================                                           GPIO                                            ================ */
7897 /* =========================================================================================================================== */
7898 
7899 
7900 /**
7901   * @brief General Purpose IO (GPIO)
7902   */
7903 
7904 typedef struct {                                /*!< (@ 0x40010000) GPIO Structure                                             */
7905 
7906   union {
7907     __IOM uint32_t PINCFG0;                     /*!< (@ 0x00000000) Controls the operation of GPIO pin 0.                      */
7908 
7909     struct {
7910       __IOM uint32_t FNCSEL0    : 4;            /*!< [3..0] Function select for GPIO pin 0                                     */
7911       __IOM uint32_t INPEN0     : 1;            /*!< [4..4] Input enable for GPIO 0                                            */
7912       __IOM uint32_t RDZERO0    : 1;            /*!< [5..5] Return 0 for read data on GPIO 0                                   */
7913       __IOM uint32_t IRPTEN0    : 2;            /*!< [7..6] Interrupt enable for GPIO 0                                        */
7914       __IOM uint32_t OUTCFG0    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 0                               */
7915       __IOM uint32_t DS0        : 2;            /*!< [11..10] Drive strength selection for GPIO 0                              */
7916       __IOM uint32_t SR0        : 1;            /*!< [12..12] Configure the slew rate                                          */
7917       __IOM uint32_t PULLCFG0   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 0                         */
7918       __IOM uint32_t NCESRC0    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 0, DISP control signals DE,
7919                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
7920       __IOM uint32_t NCEPOL0    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 0                               */
7921             uint32_t            : 3;
7922       __IOM uint32_t FIEN0      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
7923                                                      Otherwise the selected function will enable the input only
7924                                                      when needed                                                               */
7925       __IOM uint32_t FOEN0      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
7926                                                      Otherwise the selected function will enable the output
7927                                                      only when needed                                                          */
7928             uint32_t            : 4;
7929     } PINCFG0_b;
7930   } ;
7931 
7932   union {
7933     __IOM uint32_t PINCFG1;                     /*!< (@ 0x00000004) Controls the operation of GPIO pin 1.                      */
7934 
7935     struct {
7936       __IOM uint32_t FNCSEL1    : 4;            /*!< [3..0] Function select for GPIO pin 1                                     */
7937       __IOM uint32_t INPEN1     : 1;            /*!< [4..4] Input enable for GPIO 1                                            */
7938       __IOM uint32_t RDZERO1    : 1;            /*!< [5..5] Return 0 for read data on GPIO 1                                   */
7939       __IOM uint32_t IRPTEN1    : 2;            /*!< [7..6] Interrupt enable for GPIO 1                                        */
7940       __IOM uint32_t OUTCFG1    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 1                               */
7941       __IOM uint32_t DS1        : 2;            /*!< [11..10] Drive strength selection for GPIO 1                              */
7942       __IOM uint32_t SR1        : 1;            /*!< [12..12] Configure the slew rate                                          */
7943       __IOM uint32_t PULLCFG1   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 1                         */
7944       __IOM uint32_t NCESRC1    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 1, DISP control signals DE,
7945                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
7946       __IOM uint32_t NCEPOL1    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 1                               */
7947             uint32_t            : 3;
7948       __IOM uint32_t FIEN1      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
7949                                                      Otherwise the selected function will enable the input only
7950                                                      when needed                                                               */
7951       __IOM uint32_t FOEN1      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
7952                                                      Otherwise the selected function will enable the output
7953                                                      only when needed                                                          */
7954             uint32_t            : 4;
7955     } PINCFG1_b;
7956   } ;
7957 
7958   union {
7959     __IOM uint32_t PINCFG2;                     /*!< (@ 0x00000008) Controls the operation of GPIO pin 2.                      */
7960 
7961     struct {
7962       __IOM uint32_t FNCSEL2    : 4;            /*!< [3..0] Function select for GPIO pin 2                                     */
7963       __IOM uint32_t INPEN2     : 1;            /*!< [4..4] Input enable for GPIO 2                                            */
7964       __IOM uint32_t RDZERO2    : 1;            /*!< [5..5] Return 0 for read data on GPIO 2                                   */
7965       __IOM uint32_t IRPTEN2    : 2;            /*!< [7..6] Interrupt enable for GPIO 2                                        */
7966       __IOM uint32_t OUTCFG2    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 2                               */
7967       __IOM uint32_t DS2        : 2;            /*!< [11..10] Drive strength selection for GPIO 2                              */
7968       __IOM uint32_t SR2        : 1;            /*!< [12..12] Configure the slew rate                                          */
7969       __IOM uint32_t PULLCFG2   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 2                         */
7970       __IOM uint32_t NCESRC2    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 2, DISP control signals DE,
7971                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
7972       __IOM uint32_t NCEPOL2    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 2                               */
7973             uint32_t            : 3;
7974       __IOM uint32_t FIEN2      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
7975                                                      Otherwise the selected function will enable the input only
7976                                                      when needed                                                               */
7977       __IOM uint32_t FOEN2      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
7978                                                      Otherwise the selected function will enable the output
7979                                                      only when needed                                                          */
7980             uint32_t            : 4;
7981     } PINCFG2_b;
7982   } ;
7983 
7984   union {
7985     __IOM uint32_t PINCFG3;                     /*!< (@ 0x0000000C) Controls the operation of GPIO pin 3.                      */
7986 
7987     struct {
7988       __IOM uint32_t FNCSEL3    : 4;            /*!< [3..0] Function select for GPIO pin 3                                     */
7989       __IOM uint32_t INPEN3     : 1;            /*!< [4..4] Input enable for GPIO 3                                            */
7990       __IOM uint32_t RDZERO3    : 1;            /*!< [5..5] Return 0 for read data on GPIO 3                                   */
7991       __IOM uint32_t IRPTEN3    : 2;            /*!< [7..6] Interrupt enable for GPIO 3                                        */
7992       __IOM uint32_t OUTCFG3    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 3                               */
7993       __IOM uint32_t DS3        : 2;            /*!< [11..10] Drive strength selection for GPIO 3                              */
7994       __IOM uint32_t SR3        : 1;            /*!< [12..12] Configure the slew rate                                          */
7995       __IOM uint32_t PULLCFG3   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 3                         */
7996       __IOM uint32_t NCESRC3    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 3, DISP control signals DE,
7997                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
7998       __IOM uint32_t NCEPOL3    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 3                               */
7999             uint32_t            : 3;
8000       __IOM uint32_t FIEN3      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8001                                                      Otherwise the selected function will enable the input only
8002                                                      when needed                                                               */
8003       __IOM uint32_t FOEN3      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8004                                                      Otherwise the selected function will enable the output
8005                                                      only when needed                                                          */
8006             uint32_t            : 4;
8007     } PINCFG3_b;
8008   } ;
8009 
8010   union {
8011     __IOM uint32_t PINCFG4;                     /*!< (@ 0x00000010) Controls the operation of GPIO pin 4.                      */
8012 
8013     struct {
8014       __IOM uint32_t FNCSEL4    : 4;            /*!< [3..0] Function select for GPIO pin 4                                     */
8015       __IOM uint32_t INPEN4     : 1;            /*!< [4..4] Input enable for GPIO 4                                            */
8016       __IOM uint32_t RDZERO4    : 1;            /*!< [5..5] Return 0 for read data on GPIO 4                                   */
8017       __IOM uint32_t IRPTEN4    : 2;            /*!< [7..6] Interrupt enable for GPIO 4                                        */
8018       __IOM uint32_t OUTCFG4    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 4                               */
8019       __IOM uint32_t DS4        : 2;            /*!< [11..10] Drive strength selection for GPIO 4                              */
8020       __IOM uint32_t SR4        : 1;            /*!< [12..12] Configure the slew rate                                          */
8021       __IOM uint32_t PULLCFG4   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 4                         */
8022       __IOM uint32_t NCESRC4    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 4, DISP control signals DE,
8023                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8024       __IOM uint32_t NCEPOL4    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 4                               */
8025             uint32_t            : 3;
8026       __IOM uint32_t FIEN4      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8027                                                      Otherwise the selected function will enable the input only
8028                                                      when needed                                                               */
8029       __IOM uint32_t FOEN4      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8030                                                      Otherwise the selected function will enable the output
8031                                                      only when needed                                                          */
8032             uint32_t            : 4;
8033     } PINCFG4_b;
8034   } ;
8035 
8036   union {
8037     __IOM uint32_t PINCFG5;                     /*!< (@ 0x00000014) Controls the operation of GPIO pin 5.                      */
8038 
8039     struct {
8040       __IOM uint32_t FNCSEL5    : 4;            /*!< [3..0] Function select for GPIO pin 5                                     */
8041       __IOM uint32_t INPEN5     : 1;            /*!< [4..4] Input enable for GPIO 5                                            */
8042       __IOM uint32_t RDZERO5    : 1;            /*!< [5..5] Return 0 for read data on GPIO 5                                   */
8043       __IOM uint32_t IRPTEN5    : 2;            /*!< [7..6] Interrupt enable for GPIO 5                                        */
8044       __IOM uint32_t OUTCFG5    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 5                               */
8045       __IOM uint32_t DS5        : 2;            /*!< [11..10] Drive strength selection for GPIO 5                              */
8046       __IOM uint32_t SR5        : 1;            /*!< [12..12] Configure the slew rate                                          */
8047       __IOM uint32_t PULLCFG5   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 5                         */
8048       __IOM uint32_t NCESRC5    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 5, DISP control signals DE,
8049                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8050       __IOM uint32_t NCEPOL5    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 5                               */
8051             uint32_t            : 3;
8052       __IOM uint32_t FIEN5      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8053                                                      Otherwise the selected function will enable the input only
8054                                                      when needed                                                               */
8055       __IOM uint32_t FOEN5      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8056                                                      Otherwise the selected function will enable the output
8057                                                      only when needed                                                          */
8058             uint32_t            : 4;
8059     } PINCFG5_b;
8060   } ;
8061 
8062   union {
8063     __IOM uint32_t PINCFG6;                     /*!< (@ 0x00000018) Controls the operation of GPIO pin 6.                      */
8064 
8065     struct {
8066       __IOM uint32_t FNCSEL6    : 4;            /*!< [3..0] Function select for GPIO pin 6                                     */
8067       __IOM uint32_t INPEN6     : 1;            /*!< [4..4] Input enable for GPIO 6                                            */
8068       __IOM uint32_t RDZERO6    : 1;            /*!< [5..5] Return 0 for read data on GPIO 6                                   */
8069       __IOM uint32_t IRPTEN6    : 2;            /*!< [7..6] Interrupt enable for GPIO 6                                        */
8070       __IOM uint32_t OUTCFG6    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 6                               */
8071       __IOM uint32_t DS6        : 2;            /*!< [11..10] Drive strength selection for GPIO 6                              */
8072       __IOM uint32_t SR6        : 1;            /*!< [12..12] Configure the slew rate                                          */
8073       __IOM uint32_t PULLCFG6   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 6                         */
8074       __IOM uint32_t NCESRC6    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 6, DISP control signals DE,
8075                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8076       __IOM uint32_t NCEPOL6    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 6                               */
8077             uint32_t            : 3;
8078       __IOM uint32_t FIEN6      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8079                                                      Otherwise the selected function will enable the input only
8080                                                      when needed                                                               */
8081       __IOM uint32_t FOEN6      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8082                                                      Otherwise the selected function will enable the output
8083                                                      only when needed                                                          */
8084             uint32_t            : 4;
8085     } PINCFG6_b;
8086   } ;
8087 
8088   union {
8089     __IOM uint32_t PINCFG7;                     /*!< (@ 0x0000001C) Controls the operation of GPIO pin 7.                      */
8090 
8091     struct {
8092       __IOM uint32_t FNCSEL7    : 4;            /*!< [3..0] Function select for GPIO pin 7                                     */
8093       __IOM uint32_t INPEN7     : 1;            /*!< [4..4] Input enable for GPIO 7                                            */
8094       __IOM uint32_t RDZERO7    : 1;            /*!< [5..5] Return 0 for read data on GPIO 7                                   */
8095       __IOM uint32_t IRPTEN7    : 2;            /*!< [7..6] Interrupt enable for GPIO 7                                        */
8096       __IOM uint32_t OUTCFG7    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 7                               */
8097       __IOM uint32_t DS7        : 2;            /*!< [11..10] Drive strength selection for GPIO 7                              */
8098       __IOM uint32_t SR7        : 1;            /*!< [12..12] Configure the slew rate                                          */
8099       __IOM uint32_t PULLCFG7   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 7                         */
8100       __IOM uint32_t NCESRC7    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 7, DISP control signals DE,
8101                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8102       __IOM uint32_t NCEPOL7    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 7                               */
8103             uint32_t            : 3;
8104       __IOM uint32_t FIEN7      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8105                                                      Otherwise the selected function will enable the input only
8106                                                      when needed                                                               */
8107       __IOM uint32_t FOEN7      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8108                                                      Otherwise the selected function will enable the output
8109                                                      only when needed                                                          */
8110             uint32_t            : 4;
8111     } PINCFG7_b;
8112   } ;
8113 
8114   union {
8115     __IOM uint32_t PINCFG8;                     /*!< (@ 0x00000020) Controls the operation of GPIO pin 8.                      */
8116 
8117     struct {
8118       __IOM uint32_t FNCSEL8    : 4;            /*!< [3..0] Function select for GPIO pin 8                                     */
8119       __IOM uint32_t INPEN8     : 1;            /*!< [4..4] Input enable for GPIO 8                                            */
8120       __IOM uint32_t RDZERO8    : 1;            /*!< [5..5] Return 0 for read data on GPIO 8                                   */
8121       __IOM uint32_t IRPTEN8    : 2;            /*!< [7..6] Interrupt enable for GPIO 8                                        */
8122       __IOM uint32_t OUTCFG8    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 8                               */
8123       __IOM uint32_t DS8        : 2;            /*!< [11..10] Drive strength selection for GPIO 8                              */
8124       __IOM uint32_t SR8        : 1;            /*!< [12..12] Configure the slew rate                                          */
8125       __IOM uint32_t PULLCFG8   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 8                         */
8126       __IOM uint32_t NCESRC8    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 8, DISP control signals DE,
8127                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8128       __IOM uint32_t NCEPOL8    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 8                               */
8129             uint32_t            : 3;
8130       __IOM uint32_t FIEN8      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8131                                                      Otherwise the selected function will enable the input only
8132                                                      when needed                                                               */
8133       __IOM uint32_t FOEN8      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8134                                                      Otherwise the selected function will enable the output
8135                                                      only when needed                                                          */
8136             uint32_t            : 4;
8137     } PINCFG8_b;
8138   } ;
8139 
8140   union {
8141     __IOM uint32_t PINCFG9;                     /*!< (@ 0x00000024) Controls the operation of GPIO pin 9.                      */
8142 
8143     struct {
8144       __IOM uint32_t FNCSEL9    : 4;            /*!< [3..0] Function select for GPIO pin 9                                     */
8145       __IOM uint32_t INPEN9     : 1;            /*!< [4..4] Input enable for GPIO 9                                            */
8146       __IOM uint32_t RDZERO9    : 1;            /*!< [5..5] Return 0 for read data on GPIO 9                                   */
8147       __IOM uint32_t IRPTEN9    : 2;            /*!< [7..6] Interrupt enable for GPIO 9                                        */
8148       __IOM uint32_t OUTCFG9    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 9                               */
8149       __IOM uint32_t DS9        : 2;            /*!< [11..10] Drive strength selection for GPIO 9                              */
8150       __IOM uint32_t SR9        : 1;            /*!< [12..12] Configure the slew rate                                          */
8151       __IOM uint32_t PULLCFG9   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 9                         */
8152       __IOM uint32_t NCESRC9    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 9, DISP control signals DE,
8153                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8154       __IOM uint32_t NCEPOL9    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 9                               */
8155             uint32_t            : 3;
8156       __IOM uint32_t FIEN9      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8157                                                      Otherwise the selected function will enable the input only
8158                                                      when needed                                                               */
8159       __IOM uint32_t FOEN9      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8160                                                      Otherwise the selected function will enable the output
8161                                                      only when needed                                                          */
8162             uint32_t            : 4;
8163     } PINCFG9_b;
8164   } ;
8165 
8166   union {
8167     __IOM uint32_t PINCFG10;                    /*!< (@ 0x00000028) Controls the operation of GPIO pin 10.                     */
8168 
8169     struct {
8170       __IOM uint32_t FNCSEL10   : 4;            /*!< [3..0] Function select for GPIO pin 10                                    */
8171       __IOM uint32_t INPEN10    : 1;            /*!< [4..4] Input enable for GPIO 10                                           */
8172       __IOM uint32_t RDZERO10   : 1;            /*!< [5..5] Return 0 for read data on GPIO 10                                  */
8173       __IOM uint32_t IRPTEN10   : 2;            /*!< [7..6] Interrupt enable for GPIO 10                                       */
8174       __IOM uint32_t OUTCFG10   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 10                              */
8175       __IOM uint32_t DS10       : 2;            /*!< [11..10] Drive strength selection for GPIO 10                             */
8176       __IOM uint32_t SR10       : 1;            /*!< [12..12] Configure the slew rate                                          */
8177       __IOM uint32_t PULLCFG10  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 10                        */
8178       __IOM uint32_t NCESRC10   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 10, DISP control signals
8179                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8180                                                      field                                                                     */
8181       __IOM uint32_t NCEPOL10   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 10                              */
8182             uint32_t            : 3;
8183       __IOM uint32_t FIEN10     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8184                                                      Otherwise the selected function will enable the input only
8185                                                      when needed                                                               */
8186       __IOM uint32_t FOEN10     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8187                                                      Otherwise the selected function will enable the output
8188                                                      only when needed                                                          */
8189             uint32_t            : 4;
8190     } PINCFG10_b;
8191   } ;
8192 
8193   union {
8194     __IOM uint32_t PINCFG11;                    /*!< (@ 0x0000002C) Controls the operation of GPIO pin 11.                     */
8195 
8196     struct {
8197       __IOM uint32_t FNCSEL11   : 4;            /*!< [3..0] Function select for GPIO pin 11                                    */
8198       __IOM uint32_t INPEN11    : 1;            /*!< [4..4] Input enable for GPIO 11                                           */
8199       __IOM uint32_t RDZERO11   : 1;            /*!< [5..5] Return 0 for read data on GPIO 11                                  */
8200       __IOM uint32_t IRPTEN11   : 2;            /*!< [7..6] Interrupt enable for GPIO 11                                       */
8201       __IOM uint32_t OUTCFG11   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 11                              */
8202       __IOM uint32_t DS11       : 2;            /*!< [11..10] Drive strength selection for GPIO 11                             */
8203       __IOM uint32_t SR11       : 1;            /*!< [12..12] Configure the slew rate                                          */
8204       __IOM uint32_t PULLCFG11  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 11                        */
8205       __IOM uint32_t NCESRC11   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 11, DISP control signals
8206                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8207                                                      field                                                                     */
8208       __IOM uint32_t NCEPOL11   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 11                              */
8209             uint32_t            : 3;
8210       __IOM uint32_t FIEN11     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8211                                                      Otherwise the selected function will enable the input only
8212                                                      when needed                                                               */
8213       __IOM uint32_t FOEN11     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8214                                                      Otherwise the selected function will enable the output
8215                                                      only when needed                                                          */
8216             uint32_t            : 4;
8217     } PINCFG11_b;
8218   } ;
8219 
8220   union {
8221     __IOM uint32_t PINCFG12;                    /*!< (@ 0x00000030) Controls the operation of GPIO pin 12.                     */
8222 
8223     struct {
8224       __IOM uint32_t FNCSEL12   : 4;            /*!< [3..0] Function select for GPIO pin 12                                    */
8225       __IOM uint32_t INPEN12    : 1;            /*!< [4..4] Input enable for GPIO 12                                           */
8226       __IOM uint32_t RDZERO12   : 1;            /*!< [5..5] Return 0 for read data on GPIO 12                                  */
8227       __IOM uint32_t IRPTEN12   : 2;            /*!< [7..6] Interrupt enable for GPIO 12                                       */
8228       __IOM uint32_t OUTCFG12   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 12                              */
8229       __IOM uint32_t DS12       : 2;            /*!< [11..10] Drive strength selection for GPIO 12                             */
8230       __IOM uint32_t SR12       : 1;            /*!< [12..12] Configure the slew rate                                          */
8231       __IOM uint32_t PULLCFG12  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 12                        */
8232       __IOM uint32_t NCESRC12   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 12, DISP control signals
8233                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8234                                                      field                                                                     */
8235       __IOM uint32_t NCEPOL12   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 12                              */
8236             uint32_t            : 3;
8237       __IOM uint32_t FIEN12     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8238                                                      Otherwise the selected function will enable the input only
8239                                                      when needed                                                               */
8240       __IOM uint32_t FOEN12     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8241                                                      Otherwise the selected function will enable the output
8242                                                      only when needed                                                          */
8243             uint32_t            : 4;
8244     } PINCFG12_b;
8245   } ;
8246 
8247   union {
8248     __IOM uint32_t PINCFG13;                    /*!< (@ 0x00000034) Controls the operation of GPIO pin 13.                     */
8249 
8250     struct {
8251       __IOM uint32_t FNCSEL13   : 4;            /*!< [3..0] Function select for GPIO pin 13                                    */
8252       __IOM uint32_t INPEN13    : 1;            /*!< [4..4] Input enable for GPIO 13                                           */
8253       __IOM uint32_t RDZERO13   : 1;            /*!< [5..5] Return 0 for read data on GPIO 13                                  */
8254       __IOM uint32_t IRPTEN13   : 2;            /*!< [7..6] Interrupt enable for GPIO 13                                       */
8255       __IOM uint32_t OUTCFG13   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 13                              */
8256       __IOM uint32_t DS13       : 2;            /*!< [11..10] Drive strength selection for GPIO 13                             */
8257       __IOM uint32_t SR13       : 1;            /*!< [12..12] Configure the slew rate                                          */
8258       __IOM uint32_t PULLCFG13  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 13                        */
8259       __IOM uint32_t NCESRC13   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 13, DISP control signals
8260                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8261                                                      field                                                                     */
8262       __IOM uint32_t NCEPOL13   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 13                              */
8263             uint32_t            : 3;
8264       __IOM uint32_t FIEN13     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8265                                                      Otherwise the selected function will enable the input only
8266                                                      when needed                                                               */
8267       __IOM uint32_t FOEN13     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8268                                                      Otherwise the selected function will enable the output
8269                                                      only when needed                                                          */
8270             uint32_t            : 4;
8271     } PINCFG13_b;
8272   } ;
8273 
8274   union {
8275     __IOM uint32_t PINCFG14;                    /*!< (@ 0x00000038) Controls the operation of GPIO pin 14.                     */
8276 
8277     struct {
8278       __IOM uint32_t FNCSEL14   : 4;            /*!< [3..0] Function select for GPIO pin 14                                    */
8279       __IOM uint32_t INPEN14    : 1;            /*!< [4..4] Input enable for GPIO 14                                           */
8280       __IOM uint32_t RDZERO14   : 1;            /*!< [5..5] Return 0 for read data on GPIO 14                                  */
8281       __IOM uint32_t IRPTEN14   : 2;            /*!< [7..6] Interrupt enable for GPIO 14                                       */
8282       __IOM uint32_t OUTCFG14   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 14                              */
8283       __IOM uint32_t DS14       : 2;            /*!< [11..10] Drive strength selection for GPIO 14                             */
8284       __IOM uint32_t SR14       : 1;            /*!< [12..12] Configure the slew rate                                          */
8285       __IOM uint32_t PULLCFG14  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 14                        */
8286       __IOM uint32_t NCESRC14   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 14, DISP control signals
8287                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8288                                                      field                                                                     */
8289       __IOM uint32_t NCEPOL14   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 14                              */
8290             uint32_t            : 3;
8291       __IOM uint32_t FIEN14     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8292                                                      Otherwise the selected function will enable the input only
8293                                                      when needed                                                               */
8294       __IOM uint32_t FOEN14     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8295                                                      Otherwise the selected function will enable the output
8296                                                      only when needed                                                          */
8297             uint32_t            : 4;
8298     } PINCFG14_b;
8299   } ;
8300 
8301   union {
8302     __IOM uint32_t PINCFG15;                    /*!< (@ 0x0000003C) Controls the operation of GPIO pin 15.                     */
8303 
8304     struct {
8305       __IOM uint32_t FNCSEL15   : 4;            /*!< [3..0] Function select for GPIO pin 15                                    */
8306       __IOM uint32_t INPEN15    : 1;            /*!< [4..4] Input enable for GPIO 15                                           */
8307       __IOM uint32_t RDZERO15   : 1;            /*!< [5..5] Return 0 for read data on GPIO 15                                  */
8308       __IOM uint32_t IRPTEN15   : 2;            /*!< [7..6] Interrupt enable for GPIO 15                                       */
8309       __IOM uint32_t OUTCFG15   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 15                              */
8310       __IOM uint32_t DS15       : 2;            /*!< [11..10] Drive strength selection for GPIO 15                             */
8311       __IOM uint32_t SR15       : 1;            /*!< [12..12] Configure the slew rate                                          */
8312       __IOM uint32_t PULLCFG15  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 15                        */
8313       __IOM uint32_t NCESRC15   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 15, DISP control signals
8314                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8315                                                      field                                                                     */
8316       __IOM uint32_t NCEPOL15   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 15                              */
8317             uint32_t            : 3;
8318       __IOM uint32_t FIEN15     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8319                                                      Otherwise the selected function will enable the input only
8320                                                      when needed                                                               */
8321       __IOM uint32_t FOEN15     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8322                                                      Otherwise the selected function will enable the output
8323                                                      only when needed                                                          */
8324             uint32_t            : 4;
8325     } PINCFG15_b;
8326   } ;
8327 
8328   union {
8329     __IOM uint32_t PINCFG16;                    /*!< (@ 0x00000040) Controls the operation of GPIO pin 16.                     */
8330 
8331     struct {
8332       __IOM uint32_t FNCSEL16   : 4;            /*!< [3..0] Function select for GPIO pin 16                                    */
8333       __IOM uint32_t INPEN16    : 1;            /*!< [4..4] Input enable for GPIO 16                                           */
8334       __IOM uint32_t RDZERO16   : 1;            /*!< [5..5] Return 0 for read data on GPIO 16                                  */
8335       __IOM uint32_t IRPTEN16   : 2;            /*!< [7..6] Interrupt enable for GPIO 16                                       */
8336       __IOM uint32_t OUTCFG16   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 16                              */
8337       __IOM uint32_t DS16       : 2;            /*!< [11..10] Drive strength selection for GPIO 16                             */
8338       __IOM uint32_t SR16       : 1;            /*!< [12..12] Configure the slew rate                                          */
8339       __IOM uint32_t PULLCFG16  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 16                        */
8340       __IOM uint32_t NCESRC16   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 16, DISP control signals
8341                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8342                                                      field                                                                     */
8343       __IOM uint32_t NCEPOL16   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 16                              */
8344             uint32_t            : 3;
8345       __IOM uint32_t FIEN16     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8346                                                      Otherwise the selected function will enable the input only
8347                                                      when needed                                                               */
8348       __IOM uint32_t FOEN16     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8349                                                      Otherwise the selected function will enable the output
8350                                                      only when needed                                                          */
8351             uint32_t            : 4;
8352     } PINCFG16_b;
8353   } ;
8354 
8355   union {
8356     __IOM uint32_t PINCFG17;                    /*!< (@ 0x00000044) Controls the operation of GPIO pin 17.                     */
8357 
8358     struct {
8359       __IOM uint32_t FNCSEL17   : 4;            /*!< [3..0] Function select for GPIO pin 17                                    */
8360       __IOM uint32_t INPEN17    : 1;            /*!< [4..4] Input enable for GPIO 17                                           */
8361       __IOM uint32_t RDZERO17   : 1;            /*!< [5..5] Return 0 for read data on GPIO 17                                  */
8362       __IOM uint32_t IRPTEN17   : 2;            /*!< [7..6] Interrupt enable for GPIO 17                                       */
8363       __IOM uint32_t OUTCFG17   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 17                              */
8364       __IOM uint32_t DS17       : 2;            /*!< [11..10] Drive strength selection for GPIO 17                             */
8365       __IOM uint32_t SR17       : 1;            /*!< [12..12] Configure the slew rate                                          */
8366       __IOM uint32_t PULLCFG17  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 17                        */
8367       __IOM uint32_t NCESRC17   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 17, DISP control signals
8368                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8369                                                      field                                                                     */
8370       __IOM uint32_t NCEPOL17   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 17                              */
8371             uint32_t            : 3;
8372       __IOM uint32_t FIEN17     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8373                                                      Otherwise the selected function will enable the input only
8374                                                      when needed                                                               */
8375       __IOM uint32_t FOEN17     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8376                                                      Otherwise the selected function will enable the output
8377                                                      only when needed                                                          */
8378             uint32_t            : 4;
8379     } PINCFG17_b;
8380   } ;
8381 
8382   union {
8383     __IOM uint32_t PINCFG18;                    /*!< (@ 0x00000048) Controls the operation of GPIO pin 18.                     */
8384 
8385     struct {
8386       __IOM uint32_t FNCSEL18   : 4;            /*!< [3..0] Function select for GPIO pin 18                                    */
8387       __IOM uint32_t INPEN18    : 1;            /*!< [4..4] Input enable for GPIO 18                                           */
8388       __IOM uint32_t RDZERO18   : 1;            /*!< [5..5] Return 0 for read data on GPIO 18                                  */
8389       __IOM uint32_t IRPTEN18   : 2;            /*!< [7..6] Interrupt enable for GPIO 18                                       */
8390       __IOM uint32_t OUTCFG18   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 18                              */
8391       __IOM uint32_t DS18       : 2;            /*!< [11..10] Drive strength selection for GPIO 18                             */
8392       __IOM uint32_t SR18       : 1;            /*!< [12..12] Configure the slew rate                                          */
8393       __IOM uint32_t PULLCFG18  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 18                        */
8394       __IOM uint32_t NCESRC18   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 18, DISP control signals
8395                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8396                                                      field                                                                     */
8397       __IOM uint32_t NCEPOL18   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 18                              */
8398             uint32_t            : 3;
8399       __IOM uint32_t FIEN18     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8400                                                      Otherwise the selected function will enable the input only
8401                                                      when needed                                                               */
8402       __IOM uint32_t FOEN18     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8403                                                      Otherwise the selected function will enable the output
8404                                                      only when needed                                                          */
8405             uint32_t            : 4;
8406     } PINCFG18_b;
8407   } ;
8408 
8409   union {
8410     __IOM uint32_t PINCFG19;                    /*!< (@ 0x0000004C) Controls the operation of GPIO pin 19.                     */
8411 
8412     struct {
8413       __IOM uint32_t FNCSEL19   : 4;            /*!< [3..0] Function select for GPIO pin 19                                    */
8414       __IOM uint32_t INPEN19    : 1;            /*!< [4..4] Input enable for GPIO 19                                           */
8415       __IOM uint32_t RDZERO19   : 1;            /*!< [5..5] Return 0 for read data on GPIO 19                                  */
8416       __IOM uint32_t IRPTEN19   : 2;            /*!< [7..6] Interrupt enable for GPIO 19                                       */
8417       __IOM uint32_t OUTCFG19   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 19                              */
8418       __IOM uint32_t DS19       : 2;            /*!< [11..10] Drive strength selection for GPIO 19                             */
8419       __IOM uint32_t SR19       : 1;            /*!< [12..12] Configure the slew rate                                          */
8420       __IOM uint32_t PULLCFG19  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 19                        */
8421       __IOM uint32_t NCESRC19   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 19, DISP control signals
8422                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8423                                                      field                                                                     */
8424       __IOM uint32_t NCEPOL19   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 19                              */
8425             uint32_t            : 3;
8426       __IOM uint32_t FIEN19     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8427                                                      Otherwise the selected function will enable the input only
8428                                                      when needed                                                               */
8429       __IOM uint32_t FOEN19     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8430                                                      Otherwise the selected function will enable the output
8431                                                      only when needed                                                          */
8432             uint32_t            : 4;
8433     } PINCFG19_b;
8434   } ;
8435 
8436   union {
8437     __IOM uint32_t PINCFG20;                    /*!< (@ 0x00000050) Controls the operation of GPIO pin 20.                     */
8438 
8439     struct {
8440       __IOM uint32_t FNCSEL20   : 4;            /*!< [3..0] Function select for GPIO pin 20                                    */
8441       __IOM uint32_t INPEN20    : 1;            /*!< [4..4] Input enable for GPIO 20                                           */
8442       __IOM uint32_t RDZERO20   : 1;            /*!< [5..5] Return 0 for read data on GPIO 20                                  */
8443       __IOM uint32_t IRPTEN20   : 2;            /*!< [7..6] Interrupt enable for GPIO 20                                       */
8444       __IOM uint32_t OUTCFG20   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 20                              */
8445       __IOM uint32_t DS20       : 2;            /*!< [11..10] Drive strength selection for GPIO 20                             */
8446       __IOM uint32_t SR20       : 1;            /*!< [12..12] Configure the slew rate                                          */
8447       __IOM uint32_t PULLCFG20  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 20                        */
8448       __IOM uint32_t NCESRC20   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 20, DISP control signals
8449                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8450                                                      field                                                                     */
8451       __IOM uint32_t NCEPOL20   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 20                              */
8452             uint32_t            : 3;
8453       __IOM uint32_t FIEN20     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8454                                                      Otherwise the selected function will enable the input only
8455                                                      when needed                                                               */
8456       __IOM uint32_t FOEN20     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8457                                                      Otherwise the selected function will enable the output
8458                                                      only when needed                                                          */
8459             uint32_t            : 4;
8460     } PINCFG20_b;
8461   } ;
8462 
8463   union {
8464     __IOM uint32_t PINCFG21;                    /*!< (@ 0x00000054) Controls the operation of GPIO pin 21.                     */
8465 
8466     struct {
8467       __IOM uint32_t FNCSEL21   : 4;            /*!< [3..0] Function select for GPIO pin 21                                    */
8468       __IOM uint32_t INPEN21    : 1;            /*!< [4..4] Input enable for GPIO 21                                           */
8469       __IOM uint32_t RDZERO21   : 1;            /*!< [5..5] Return 0 for read data on GPIO 21                                  */
8470       __IOM uint32_t IRPTEN21   : 2;            /*!< [7..6] Interrupt enable for GPIO 21                                       */
8471       __IOM uint32_t OUTCFG21   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 21                              */
8472       __IOM uint32_t DS21       : 2;            /*!< [11..10] Drive strength selection for GPIO 21                             */
8473       __IOM uint32_t SR21       : 1;            /*!< [12..12] Configure the slew rate                                          */
8474       __IOM uint32_t PULLCFG21  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 21                        */
8475       __IOM uint32_t NCESRC21   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 21, DISP control signals
8476                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8477                                                      field                                                                     */
8478       __IOM uint32_t NCEPOL21   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 21                              */
8479             uint32_t            : 3;
8480       __IOM uint32_t FIEN21     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8481                                                      Otherwise the selected function will enable the input only
8482                                                      when needed                                                               */
8483       __IOM uint32_t FOEN21     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8484                                                      Otherwise the selected function will enable the output
8485                                                      only when needed                                                          */
8486             uint32_t            : 4;
8487     } PINCFG21_b;
8488   } ;
8489 
8490   union {
8491     __IOM uint32_t PINCFG22;                    /*!< (@ 0x00000058) Controls the operation of GPIO pin 22.                     */
8492 
8493     struct {
8494       __IOM uint32_t FNCSEL22   : 4;            /*!< [3..0] Function select for GPIO pin 22                                    */
8495       __IOM uint32_t INPEN22    : 1;            /*!< [4..4] Input enable for GPIO 22                                           */
8496       __IOM uint32_t RDZERO22   : 1;            /*!< [5..5] Return 0 for read data on GPIO 22                                  */
8497       __IOM uint32_t IRPTEN22   : 2;            /*!< [7..6] Interrupt enable for GPIO 22                                       */
8498       __IOM uint32_t OUTCFG22   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 22                              */
8499       __IOM uint32_t DS22       : 2;            /*!< [11..10] Drive strength selection for GPIO 22                             */
8500       __IOM uint32_t SR22       : 1;            /*!< [12..12] Configure the slew rate                                          */
8501       __IOM uint32_t PULLCFG22  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 22                        */
8502       __IOM uint32_t NCESRC22   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 22, DISP control signals
8503                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8504                                                      field                                                                     */
8505       __IOM uint32_t NCEPOL22   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 22                              */
8506             uint32_t            : 3;
8507       __IOM uint32_t FIEN22     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8508                                                      Otherwise the selected function will enable the input only
8509                                                      when needed                                                               */
8510       __IOM uint32_t FOEN22     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8511                                                      Otherwise the selected function will enable the output
8512                                                      only when needed                                                          */
8513             uint32_t            : 4;
8514     } PINCFG22_b;
8515   } ;
8516 
8517   union {
8518     __IOM uint32_t PINCFG23;                    /*!< (@ 0x0000005C) Controls the operation of GPIO pin 23.                     */
8519 
8520     struct {
8521       __IOM uint32_t FNCSEL23   : 4;            /*!< [3..0] Function select for GPIO pin 23                                    */
8522       __IOM uint32_t INPEN23    : 1;            /*!< [4..4] Input enable for GPIO 23                                           */
8523       __IOM uint32_t RDZERO23   : 1;            /*!< [5..5] Return 0 for read data on GPIO 23                                  */
8524       __IOM uint32_t IRPTEN23   : 2;            /*!< [7..6] Interrupt enable for GPIO 23                                       */
8525       __IOM uint32_t OUTCFG23   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 23                              */
8526       __IOM uint32_t DS23       : 2;            /*!< [11..10] Drive strength selection for GPIO 23                             */
8527       __IOM uint32_t SR23       : 1;            /*!< [12..12] Configure the slew rate                                          */
8528       __IOM uint32_t PULLCFG23  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 23                        */
8529       __IOM uint32_t NCESRC23   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 23, DISP control signals
8530                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8531                                                      field                                                                     */
8532       __IOM uint32_t NCEPOL23   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 23                              */
8533             uint32_t            : 3;
8534       __IOM uint32_t FIEN23     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8535                                                      Otherwise the selected function will enable the input only
8536                                                      when needed                                                               */
8537       __IOM uint32_t FOEN23     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8538                                                      Otherwise the selected function will enable the output
8539                                                      only when needed                                                          */
8540             uint32_t            : 4;
8541     } PINCFG23_b;
8542   } ;
8543 
8544   union {
8545     __IOM uint32_t PINCFG24;                    /*!< (@ 0x00000060) Controls the operation of GPIO pin 24.                     */
8546 
8547     struct {
8548       __IOM uint32_t FNCSEL24   : 4;            /*!< [3..0] Function select for GPIO pin 24                                    */
8549       __IOM uint32_t INPEN24    : 1;            /*!< [4..4] Input enable for GPIO 24                                           */
8550       __IOM uint32_t RDZERO24   : 1;            /*!< [5..5] Return 0 for read data on GPIO 24                                  */
8551       __IOM uint32_t IRPTEN24   : 2;            /*!< [7..6] Interrupt enable for GPIO 24                                       */
8552       __IOM uint32_t OUTCFG24   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 24                              */
8553       __IOM uint32_t DS24       : 2;            /*!< [11..10] Drive strength selection for GPIO 24                             */
8554       __IOM uint32_t SR24       : 1;            /*!< [12..12] Configure the slew rate                                          */
8555       __IOM uint32_t PULLCFG24  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 24                        */
8556       __IOM uint32_t NCESRC24   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 24, DISP control signals
8557                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8558                                                      field                                                                     */
8559       __IOM uint32_t NCEPOL24   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 24                              */
8560             uint32_t            : 3;
8561       __IOM uint32_t FIEN24     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8562                                                      Otherwise the selected function will enable the input only
8563                                                      when needed                                                               */
8564       __IOM uint32_t FOEN24     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8565                                                      Otherwise the selected function will enable the output
8566                                                      only when needed                                                          */
8567             uint32_t            : 4;
8568     } PINCFG24_b;
8569   } ;
8570 
8571   union {
8572     __IOM uint32_t PINCFG25;                    /*!< (@ 0x00000064) Controls the operation of GPIO pin 25.                     */
8573 
8574     struct {
8575       __IOM uint32_t FNCSEL25   : 4;            /*!< [3..0] Function select for GPIO pin 25                                    */
8576       __IOM uint32_t INPEN25    : 1;            /*!< [4..4] Input enable for GPIO 25                                           */
8577       __IOM uint32_t RDZERO25   : 1;            /*!< [5..5] Return 0 for read data on GPIO 25                                  */
8578       __IOM uint32_t IRPTEN25   : 2;            /*!< [7..6] Interrupt enable for GPIO 25                                       */
8579       __IOM uint32_t OUTCFG25   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 25                              */
8580       __IOM uint32_t DS25       : 2;            /*!< [11..10] Drive strength selection for GPIO 25                             */
8581       __IOM uint32_t SR25       : 1;            /*!< [12..12] Configure the slew rate                                          */
8582       __IOM uint32_t PULLCFG25  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 25                        */
8583       __IOM uint32_t NCESRC25   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 25, DISP control signals
8584                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8585                                                      field                                                                     */
8586       __IOM uint32_t NCEPOL25   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 25                              */
8587             uint32_t            : 3;
8588       __IOM uint32_t FIEN25     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8589                                                      Otherwise the selected function will enable the input only
8590                                                      when needed                                                               */
8591       __IOM uint32_t FOEN25     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8592                                                      Otherwise the selected function will enable the output
8593                                                      only when needed                                                          */
8594             uint32_t            : 4;
8595     } PINCFG25_b;
8596   } ;
8597 
8598   union {
8599     __IOM uint32_t PINCFG26;                    /*!< (@ 0x00000068) Controls the operation of GPIO pin 26.                     */
8600 
8601     struct {
8602       __IOM uint32_t FNCSEL26   : 4;            /*!< [3..0] Function select for GPIO pin 26                                    */
8603       __IOM uint32_t INPEN26    : 1;            /*!< [4..4] Input enable for GPIO 26                                           */
8604       __IOM uint32_t RDZERO26   : 1;            /*!< [5..5] Return 0 for read data on GPIO 26                                  */
8605       __IOM uint32_t IRPTEN26   : 2;            /*!< [7..6] Interrupt enable for GPIO 26                                       */
8606       __IOM uint32_t OUTCFG26   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 26                              */
8607       __IOM uint32_t DS26       : 2;            /*!< [11..10] Drive strength selection for GPIO 26                             */
8608       __IOM uint32_t SR26       : 1;            /*!< [12..12] Configure the slew rate                                          */
8609       __IOM uint32_t PULLCFG26  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 26                        */
8610       __IOM uint32_t NCESRC26   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 26, DISP control signals
8611                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8612                                                      field                                                                     */
8613       __IOM uint32_t NCEPOL26   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 26                              */
8614             uint32_t            : 3;
8615       __IOM uint32_t FIEN26     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8616                                                      Otherwise the selected function will enable the input only
8617                                                      when needed                                                               */
8618       __IOM uint32_t FOEN26     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8619                                                      Otherwise the selected function will enable the output
8620                                                      only when needed                                                          */
8621             uint32_t            : 4;
8622     } PINCFG26_b;
8623   } ;
8624 
8625   union {
8626     __IOM uint32_t PINCFG27;                    /*!< (@ 0x0000006C) Controls the operation of GPIO pin 27.                     */
8627 
8628     struct {
8629       __IOM uint32_t FNCSEL27   : 4;            /*!< [3..0] Function select for GPIO pin 27                                    */
8630       __IOM uint32_t INPEN27    : 1;            /*!< [4..4] Input enable for GPIO 27                                           */
8631       __IOM uint32_t RDZERO27   : 1;            /*!< [5..5] Return 0 for read data on GPIO 27                                  */
8632       __IOM uint32_t IRPTEN27   : 2;            /*!< [7..6] Interrupt enable for GPIO 27                                       */
8633       __IOM uint32_t OUTCFG27   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 27                              */
8634       __IOM uint32_t DS27       : 2;            /*!< [11..10] Drive strength selection for GPIO 27                             */
8635       __IOM uint32_t SR27       : 1;            /*!< [12..12] Configure the slew rate                                          */
8636       __IOM uint32_t PULLCFG27  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 27                        */
8637       __IOM uint32_t NCESRC27   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 27, DISP control signals
8638                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8639                                                      field                                                                     */
8640       __IOM uint32_t NCEPOL27   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 27                              */
8641             uint32_t            : 3;
8642       __IOM uint32_t FIEN27     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8643                                                      Otherwise the selected function will enable the input only
8644                                                      when needed                                                               */
8645       __IOM uint32_t FOEN27     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8646                                                      Otherwise the selected function will enable the output
8647                                                      only when needed                                                          */
8648             uint32_t            : 4;
8649     } PINCFG27_b;
8650   } ;
8651 
8652   union {
8653     __IOM uint32_t PINCFG28;                    /*!< (@ 0x00000070) Controls the operation of GPIO pin 28.                     */
8654 
8655     struct {
8656       __IOM uint32_t FNCSEL28   : 4;            /*!< [3..0] Function select for GPIO pin 28                                    */
8657       __IOM uint32_t INPEN28    : 1;            /*!< [4..4] Input enable for GPIO 28                                           */
8658       __IOM uint32_t RDZERO28   : 1;            /*!< [5..5] Return 0 for read data on GPIO 28                                  */
8659       __IOM uint32_t IRPTEN28   : 2;            /*!< [7..6] Interrupt enable for GPIO 28                                       */
8660       __IOM uint32_t OUTCFG28   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 28                              */
8661       __IOM uint32_t DS28       : 2;            /*!< [11..10] Drive strength selection for GPIO 28                             */
8662       __IOM uint32_t SR28       : 1;            /*!< [12..12] Configure the slew rate                                          */
8663       __IOM uint32_t PULLCFG28  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 28                        */
8664       __IOM uint32_t NCESRC28   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 28, DISP control signals
8665                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8666                                                      field                                                                     */
8667       __IOM uint32_t NCEPOL28   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 28                              */
8668             uint32_t            : 3;
8669       __IOM uint32_t FIEN28     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8670                                                      Otherwise the selected function will enable the input only
8671                                                      when needed                                                               */
8672       __IOM uint32_t FOEN28     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8673                                                      Otherwise the selected function will enable the output
8674                                                      only when needed                                                          */
8675             uint32_t            : 4;
8676     } PINCFG28_b;
8677   } ;
8678 
8679   union {
8680     __IOM uint32_t PINCFG29;                    /*!< (@ 0x00000074) Controls the operation of GPIO pin 29.                     */
8681 
8682     struct {
8683       __IOM uint32_t FNCSEL29   : 4;            /*!< [3..0] Function select for GPIO pin 29                                    */
8684       __IOM uint32_t INPEN29    : 1;            /*!< [4..4] Input enable for GPIO 29                                           */
8685       __IOM uint32_t RDZERO29   : 1;            /*!< [5..5] Return 0 for read data on GPIO 29                                  */
8686       __IOM uint32_t IRPTEN29   : 2;            /*!< [7..6] Interrupt enable for GPIO 29                                       */
8687       __IOM uint32_t OUTCFG29   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 29                              */
8688       __IOM uint32_t DS29       : 2;            /*!< [11..10] Drive strength selection for GPIO 29                             */
8689       __IOM uint32_t SR29       : 1;            /*!< [12..12] Configure the slew rate                                          */
8690       __IOM uint32_t PULLCFG29  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 29                        */
8691       __IOM uint32_t NCESRC29   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 29, DISP control signals
8692                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8693                                                      field                                                                     */
8694       __IOM uint32_t NCEPOL29   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 29                              */
8695             uint32_t            : 2;
8696       __IOM uint32_t VSSPWRSWEN29 : 1;          /*!< [25..25] VSS power switch enable. Enable VSS power switch when
8697                                                      driving pad signal to 0 for GPIO 29                                       */
8698       __IOM uint32_t FIEN29     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8699                                                      Otherwise the selected function will enable the input only
8700                                                      when needed                                                               */
8701       __IOM uint32_t FOEN29     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8702                                                      Otherwise the selected function will enable the output
8703                                                      only when needed                                                          */
8704             uint32_t            : 4;
8705     } PINCFG29_b;
8706   } ;
8707 
8708   union {
8709     __IOM uint32_t PINCFG30;                    /*!< (@ 0x00000078) Controls the operation of GPIO pin 30.                     */
8710 
8711     struct {
8712       __IOM uint32_t FNCSEL30   : 4;            /*!< [3..0] Function select for GPIO pin 30                                    */
8713       __IOM uint32_t INPEN30    : 1;            /*!< [4..4] Input enable for GPIO 30                                           */
8714       __IOM uint32_t RDZERO30   : 1;            /*!< [5..5] Return 0 for read data on GPIO 30                                  */
8715       __IOM uint32_t IRPTEN30   : 2;            /*!< [7..6] Interrupt enable for GPIO 30                                       */
8716       __IOM uint32_t OUTCFG30   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 30                              */
8717       __IOM uint32_t DS30       : 2;            /*!< [11..10] Drive strength selection for GPIO 30                             */
8718       __IOM uint32_t SR30       : 1;            /*!< [12..12] Configure the slew rate                                          */
8719       __IOM uint32_t PULLCFG30  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 30                        */
8720       __IOM uint32_t NCESRC30   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 30, DISP control signals
8721                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8722                                                      field                                                                     */
8723       __IOM uint32_t NCEPOL30   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 30                              */
8724             uint32_t            : 2;
8725       __IOM uint32_t VDDPWRSWEN30 : 1;          /*!< [25..25] VDD power switch enable. Enable VDD power switch when
8726                                                      driving pad signal to 1 for GPIO 30                                       */
8727       __IOM uint32_t FIEN30     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8728                                                      Otherwise the selected function will enable the input only
8729                                                      when needed                                                               */
8730       __IOM uint32_t FOEN30     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8731                                                      Otherwise the selected function will enable the output
8732                                                      only when needed                                                          */
8733             uint32_t            : 4;
8734     } PINCFG30_b;
8735   } ;
8736 
8737   union {
8738     __IOM uint32_t PINCFG31;                    /*!< (@ 0x0000007C) Controls the operation of GPIO pin 31.                     */
8739 
8740     struct {
8741       __IOM uint32_t FNCSEL31   : 4;            /*!< [3..0] Function select for GPIO pin 31                                    */
8742       __IOM uint32_t INPEN31    : 1;            /*!< [4..4] Input enable for GPIO 31                                           */
8743       __IOM uint32_t RDZERO31   : 1;            /*!< [5..5] Return 0 for read data on GPIO 31                                  */
8744       __IOM uint32_t IRPTEN31   : 2;            /*!< [7..6] Interrupt enable for GPIO 31                                       */
8745       __IOM uint32_t OUTCFG31   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 31                              */
8746       __IOM uint32_t DS31       : 2;            /*!< [11..10] Drive strength selection for GPIO 31                             */
8747       __IOM uint32_t SR31       : 1;            /*!< [12..12] Configure the slew rate                                          */
8748       __IOM uint32_t PULLCFG31  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 31                        */
8749       __IOM uint32_t NCESRC31   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 31, DISP control signals
8750                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8751                                                      field                                                                     */
8752       __IOM uint32_t NCEPOL31   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 31                              */
8753             uint32_t            : 3;
8754       __IOM uint32_t FIEN31     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8755                                                      Otherwise the selected function will enable the input only
8756                                                      when needed                                                               */
8757       __IOM uint32_t FOEN31     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8758                                                      Otherwise the selected function will enable the output
8759                                                      only when needed                                                          */
8760             uint32_t            : 4;
8761     } PINCFG31_b;
8762   } ;
8763 
8764   union {
8765     __IOM uint32_t PINCFG32;                    /*!< (@ 0x00000080) Controls the operation of GPIO pin 32.                     */
8766 
8767     struct {
8768       __IOM uint32_t FNCSEL32   : 4;            /*!< [3..0] Function select for GPIO pin 32                                    */
8769       __IOM uint32_t INPEN32    : 1;            /*!< [4..4] Input enable for GPIO 32                                           */
8770       __IOM uint32_t RDZERO32   : 1;            /*!< [5..5] Return 0 for read data on GPIO 32                                  */
8771       __IOM uint32_t IRPTEN32   : 2;            /*!< [7..6] Interrupt enable for GPIO 32                                       */
8772       __IOM uint32_t OUTCFG32   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 32                              */
8773       __IOM uint32_t DS32       : 2;            /*!< [11..10] Drive strength selection for GPIO 32                             */
8774       __IOM uint32_t SR32       : 1;            /*!< [12..12] Configure the slew rate                                          */
8775       __IOM uint32_t PULLCFG32  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 32                        */
8776       __IOM uint32_t NCESRC32   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 32, DISP control signals
8777                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8778                                                      field                                                                     */
8779       __IOM uint32_t NCEPOL32   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 32                              */
8780             uint32_t            : 3;
8781       __IOM uint32_t FIEN32     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8782                                                      Otherwise the selected function will enable the input only
8783                                                      when needed                                                               */
8784       __IOM uint32_t FOEN32     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8785                                                      Otherwise the selected function will enable the output
8786                                                      only when needed                                                          */
8787             uint32_t            : 4;
8788     } PINCFG32_b;
8789   } ;
8790 
8791   union {
8792     __IOM uint32_t PINCFG33;                    /*!< (@ 0x00000084) Controls the operation of GPIO pin 33.                     */
8793 
8794     struct {
8795       __IOM uint32_t FNCSEL33   : 4;            /*!< [3..0] Function select for GPIO pin 33                                    */
8796       __IOM uint32_t INPEN33    : 1;            /*!< [4..4] Input enable for GPIO 33                                           */
8797       __IOM uint32_t RDZERO33   : 1;            /*!< [5..5] Return 0 for read data on GPIO 33                                  */
8798       __IOM uint32_t IRPTEN33   : 2;            /*!< [7..6] Interrupt enable for GPIO 33                                       */
8799       __IOM uint32_t OUTCFG33   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 33                              */
8800       __IOM uint32_t DS33       : 2;            /*!< [11..10] Drive strength selection for GPIO 33                             */
8801       __IOM uint32_t SR33       : 1;            /*!< [12..12] Configure the slew rate                                          */
8802       __IOM uint32_t PULLCFG33  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 33                        */
8803       __IOM uint32_t NCESRC33   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 33, DISP control signals
8804                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8805                                                      field                                                                     */
8806       __IOM uint32_t NCEPOL33   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 33                              */
8807             uint32_t            : 3;
8808       __IOM uint32_t FIEN33     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8809                                                      Otherwise the selected function will enable the input only
8810                                                      when needed                                                               */
8811       __IOM uint32_t FOEN33     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8812                                                      Otherwise the selected function will enable the output
8813                                                      only when needed                                                          */
8814             uint32_t            : 4;
8815     } PINCFG33_b;
8816   } ;
8817 
8818   union {
8819     __IOM uint32_t PINCFG34;                    /*!< (@ 0x00000088) Controls the operation of GPIO pin 34.                     */
8820 
8821     struct {
8822       __IOM uint32_t FNCSEL34   : 4;            /*!< [3..0] Function select for GPIO pin 34                                    */
8823       __IOM uint32_t INPEN34    : 1;            /*!< [4..4] Input enable for GPIO 34                                           */
8824       __IOM uint32_t RDZERO34   : 1;            /*!< [5..5] Return 0 for read data on GPIO 34                                  */
8825       __IOM uint32_t IRPTEN34   : 2;            /*!< [7..6] Interrupt enable for GPIO 34                                       */
8826       __IOM uint32_t OUTCFG34   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 34                              */
8827       __IOM uint32_t DS34       : 2;            /*!< [11..10] Drive strength selection for GPIO 34                             */
8828       __IOM uint32_t SR34       : 1;            /*!< [12..12] Configure the slew rate                                          */
8829       __IOM uint32_t PULLCFG34  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 34                        */
8830       __IOM uint32_t NCESRC34   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 34, DISP control signals
8831                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8832                                                      field                                                                     */
8833       __IOM uint32_t NCEPOL34   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 34                              */
8834             uint32_t            : 3;
8835       __IOM uint32_t FIEN34     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8836                                                      Otherwise the selected function will enable the input only
8837                                                      when needed                                                               */
8838       __IOM uint32_t FOEN34     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8839                                                      Otherwise the selected function will enable the output
8840                                                      only when needed                                                          */
8841             uint32_t            : 4;
8842     } PINCFG34_b;
8843   } ;
8844 
8845   union {
8846     __IOM uint32_t PINCFG35;                    /*!< (@ 0x0000008C) Controls the operation of GPIO pin 35.                     */
8847 
8848     struct {
8849       __IOM uint32_t FNCSEL35   : 4;            /*!< [3..0] Function select for GPIO pin 35                                    */
8850       __IOM uint32_t INPEN35    : 1;            /*!< [4..4] Input enable for GPIO 35                                           */
8851       __IOM uint32_t RDZERO35   : 1;            /*!< [5..5] Return 0 for read data on GPIO 35                                  */
8852       __IOM uint32_t IRPTEN35   : 2;            /*!< [7..6] Interrupt enable for GPIO 35                                       */
8853       __IOM uint32_t OUTCFG35   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 35                              */
8854       __IOM uint32_t DS35       : 2;            /*!< [11..10] Drive strength selection for GPIO 35                             */
8855       __IOM uint32_t SR35       : 1;            /*!< [12..12] Configure the slew rate                                          */
8856       __IOM uint32_t PULLCFG35  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 35                        */
8857       __IOM uint32_t NCESRC35   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 35, DISP control signals
8858                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8859                                                      field                                                                     */
8860       __IOM uint32_t NCEPOL35   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 35                              */
8861             uint32_t            : 3;
8862       __IOM uint32_t FIEN35     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8863                                                      Otherwise the selected function will enable the input only
8864                                                      when needed                                                               */
8865       __IOM uint32_t FOEN35     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8866                                                      Otherwise the selected function will enable the output
8867                                                      only when needed                                                          */
8868             uint32_t            : 4;
8869     } PINCFG35_b;
8870   } ;
8871 
8872   union {
8873     __IOM uint32_t PINCFG36;                    /*!< (@ 0x00000090) Controls the operation of GPIO pin 36.                     */
8874 
8875     struct {
8876       __IOM uint32_t FNCSEL36   : 4;            /*!< [3..0] Function select for GPIO pin 36                                    */
8877       __IOM uint32_t INPEN36    : 1;            /*!< [4..4] Input enable for GPIO 36                                           */
8878       __IOM uint32_t RDZERO36   : 1;            /*!< [5..5] Return 0 for read data on GPIO 36                                  */
8879       __IOM uint32_t IRPTEN36   : 2;            /*!< [7..6] Interrupt enable for GPIO 36                                       */
8880       __IOM uint32_t OUTCFG36   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 36                              */
8881       __IOM uint32_t DS36       : 2;            /*!< [11..10] Drive strength selection for GPIO 36                             */
8882       __IOM uint32_t SR36       : 1;            /*!< [12..12] Configure the slew rate                                          */
8883       __IOM uint32_t PULLCFG36  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 36                        */
8884       __IOM uint32_t NCESRC36   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 36, DISP control signals
8885                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8886                                                      field                                                                     */
8887       __IOM uint32_t NCEPOL36   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 36                              */
8888             uint32_t            : 3;
8889       __IOM uint32_t FIEN36     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8890                                                      Otherwise the selected function will enable the input only
8891                                                      when needed                                                               */
8892       __IOM uint32_t FOEN36     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8893                                                      Otherwise the selected function will enable the output
8894                                                      only when needed                                                          */
8895             uint32_t            : 4;
8896     } PINCFG36_b;
8897   } ;
8898 
8899   union {
8900     __IOM uint32_t PINCFG37;                    /*!< (@ 0x00000094) Controls the operation of GPIO pin 37.                     */
8901 
8902     struct {
8903       __IOM uint32_t FNCSEL37   : 4;            /*!< [3..0] Function select for GPIO pin 37                                    */
8904       __IOM uint32_t INPEN37    : 1;            /*!< [4..4] Input enable for GPIO 37                                           */
8905       __IOM uint32_t RDZERO37   : 1;            /*!< [5..5] Return 0 for read data on GPIO 37                                  */
8906       __IOM uint32_t IRPTEN37   : 2;            /*!< [7..6] Interrupt enable for GPIO 37                                       */
8907       __IOM uint32_t OUTCFG37   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 37                              */
8908       __IOM uint32_t DS37       : 2;            /*!< [11..10] Drive strength selection for GPIO 37                             */
8909       __IOM uint32_t SR37       : 1;            /*!< [12..12] Configure the slew rate                                          */
8910       __IOM uint32_t PULLCFG37  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 37                        */
8911       __IOM uint32_t NCESRC37   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 37, DISP control signals
8912                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8913                                                      field                                                                     */
8914       __IOM uint32_t NCEPOL37   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 37                              */
8915             uint32_t            : 3;
8916       __IOM uint32_t FIEN37     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8917                                                      Otherwise the selected function will enable the input only
8918                                                      when needed                                                               */
8919       __IOM uint32_t FOEN37     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8920                                                      Otherwise the selected function will enable the output
8921                                                      only when needed                                                          */
8922             uint32_t            : 4;
8923     } PINCFG37_b;
8924   } ;
8925 
8926   union {
8927     __IOM uint32_t PINCFG38;                    /*!< (@ 0x00000098) Controls the operation of GPIO pin 38.                     */
8928 
8929     struct {
8930       __IOM uint32_t FNCSEL38   : 4;            /*!< [3..0] Function select for GPIO pin 38                                    */
8931       __IOM uint32_t INPEN38    : 1;            /*!< [4..4] Input enable for GPIO 38                                           */
8932       __IOM uint32_t RDZERO38   : 1;            /*!< [5..5] Return 0 for read data on GPIO 38                                  */
8933       __IOM uint32_t IRPTEN38   : 2;            /*!< [7..6] Interrupt enable for GPIO 38                                       */
8934       __IOM uint32_t OUTCFG38   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 38                              */
8935       __IOM uint32_t DS38       : 2;            /*!< [11..10] Drive strength selection for GPIO 38                             */
8936       __IOM uint32_t SR38       : 1;            /*!< [12..12] Configure the slew rate                                          */
8937       __IOM uint32_t PULLCFG38  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 38                        */
8938       __IOM uint32_t NCESRC38   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 38, DISP control signals
8939                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8940                                                      field                                                                     */
8941       __IOM uint32_t NCEPOL38   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 38                              */
8942             uint32_t            : 3;
8943       __IOM uint32_t FIEN38     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8944                                                      Otherwise the selected function will enable the input only
8945                                                      when needed                                                               */
8946       __IOM uint32_t FOEN38     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8947                                                      Otherwise the selected function will enable the output
8948                                                      only when needed                                                          */
8949             uint32_t            : 4;
8950     } PINCFG38_b;
8951   } ;
8952 
8953   union {
8954     __IOM uint32_t PINCFG39;                    /*!< (@ 0x0000009C) Controls the operation of GPIO pin 39.                     */
8955 
8956     struct {
8957       __IOM uint32_t FNCSEL39   : 4;            /*!< [3..0] Function select for GPIO pin 39                                    */
8958       __IOM uint32_t INPEN39    : 1;            /*!< [4..4] Input enable for GPIO 39                                           */
8959       __IOM uint32_t RDZERO39   : 1;            /*!< [5..5] Return 0 for read data on GPIO 39                                  */
8960       __IOM uint32_t IRPTEN39   : 2;            /*!< [7..6] Interrupt enable for GPIO 39                                       */
8961       __IOM uint32_t OUTCFG39   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 39                              */
8962       __IOM uint32_t DS39       : 2;            /*!< [11..10] Drive strength selection for GPIO 39                             */
8963       __IOM uint32_t SR39       : 1;            /*!< [12..12] Configure the slew rate                                          */
8964       __IOM uint32_t PULLCFG39  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 39                        */
8965       __IOM uint32_t NCESRC39   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 39, DISP control signals
8966                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8967                                                      field                                                                     */
8968       __IOM uint32_t NCEPOL39   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 39                              */
8969             uint32_t            : 3;
8970       __IOM uint32_t FIEN39     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8971                                                      Otherwise the selected function will enable the input only
8972                                                      when needed                                                               */
8973       __IOM uint32_t FOEN39     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8974                                                      Otherwise the selected function will enable the output
8975                                                      only when needed                                                          */
8976             uint32_t            : 4;
8977     } PINCFG39_b;
8978   } ;
8979 
8980   union {
8981     __IOM uint32_t PINCFG40;                    /*!< (@ 0x000000A0) Controls the operation of GPIO pin 40.                     */
8982 
8983     struct {
8984       __IOM uint32_t FNCSEL40   : 4;            /*!< [3..0] Function select for GPIO pin 40                                    */
8985       __IOM uint32_t INPEN40    : 1;            /*!< [4..4] Input enable for GPIO 40                                           */
8986       __IOM uint32_t RDZERO40   : 1;            /*!< [5..5] Return 0 for read data on GPIO 40                                  */
8987       __IOM uint32_t IRPTEN40   : 2;            /*!< [7..6] Interrupt enable for GPIO 40                                       */
8988       __IOM uint32_t OUTCFG40   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 40                              */
8989       __IOM uint32_t DS40       : 2;            /*!< [11..10] Drive strength selection for GPIO 40                             */
8990       __IOM uint32_t SR40       : 1;            /*!< [12..12] Configure the slew rate                                          */
8991       __IOM uint32_t PULLCFG40  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 40                        */
8992       __IOM uint32_t NCESRC40   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 40, DISP control signals
8993                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8994                                                      field                                                                     */
8995       __IOM uint32_t NCEPOL40   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 40                              */
8996             uint32_t            : 3;
8997       __IOM uint32_t FIEN40     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8998                                                      Otherwise the selected function will enable the input only
8999                                                      when needed                                                               */
9000       __IOM uint32_t FOEN40     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9001                                                      Otherwise the selected function will enable the output
9002                                                      only when needed                                                          */
9003             uint32_t            : 4;
9004     } PINCFG40_b;
9005   } ;
9006 
9007   union {
9008     __IOM uint32_t PINCFG41;                    /*!< (@ 0x000000A4) Controls the operation of GPIO pin 41.                     */
9009 
9010     struct {
9011       __IOM uint32_t FNCSEL41   : 4;            /*!< [3..0] Function select for GPIO pin 41                                    */
9012       __IOM uint32_t INPEN41    : 1;            /*!< [4..4] Input enable for GPIO 41                                           */
9013       __IOM uint32_t RDZERO41   : 1;            /*!< [5..5] Return 0 for read data on GPIO 41                                  */
9014       __IOM uint32_t IRPTEN41   : 2;            /*!< [7..6] Interrupt enable for GPIO 41                                       */
9015       __IOM uint32_t OUTCFG41   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 41                              */
9016       __IOM uint32_t DS41       : 2;            /*!< [11..10] Drive strength selection for GPIO 41                             */
9017       __IOM uint32_t SR41       : 1;            /*!< [12..12] Configure the slew rate                                          */
9018       __IOM uint32_t PULLCFG41  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 41                        */
9019       __IOM uint32_t NCESRC41   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 41, DISP control signals
9020                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9021                                                      field                                                                     */
9022       __IOM uint32_t NCEPOL41   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 41                              */
9023             uint32_t            : 3;
9024       __IOM uint32_t FIEN41     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9025                                                      Otherwise the selected function will enable the input only
9026                                                      when needed                                                               */
9027       __IOM uint32_t FOEN41     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9028                                                      Otherwise the selected function will enable the output
9029                                                      only when needed                                                          */
9030             uint32_t            : 4;
9031     } PINCFG41_b;
9032   } ;
9033 
9034   union {
9035     __IOM uint32_t PINCFG42;                    /*!< (@ 0x000000A8) Controls the operation of GPIO pin 42.                     */
9036 
9037     struct {
9038       __IOM uint32_t FNCSEL42   : 4;            /*!< [3..0] Function select for GPIO pin 42                                    */
9039       __IOM uint32_t INPEN42    : 1;            /*!< [4..4] Input enable for GPIO 42                                           */
9040       __IOM uint32_t RDZERO42   : 1;            /*!< [5..5] Return 0 for read data on GPIO 42                                  */
9041       __IOM uint32_t IRPTEN42   : 2;            /*!< [7..6] Interrupt enable for GPIO 42                                       */
9042       __IOM uint32_t OUTCFG42   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 42                              */
9043       __IOM uint32_t DS42       : 2;            /*!< [11..10] Drive strength selection for GPIO 42                             */
9044       __IOM uint32_t SR42       : 1;            /*!< [12..12] Configure the slew rate                                          */
9045       __IOM uint32_t PULLCFG42  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 42                        */
9046       __IOM uint32_t NCESRC42   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 42, DISP control signals
9047                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9048                                                      field                                                                     */
9049       __IOM uint32_t NCEPOL42   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 42                              */
9050             uint32_t            : 3;
9051       __IOM uint32_t FIEN42     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9052                                                      Otherwise the selected function will enable the input only
9053                                                      when needed                                                               */
9054       __IOM uint32_t FOEN42     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9055                                                      Otherwise the selected function will enable the output
9056                                                      only when needed                                                          */
9057             uint32_t            : 4;
9058     } PINCFG42_b;
9059   } ;
9060 
9061   union {
9062     __IOM uint32_t PINCFG43;                    /*!< (@ 0x000000AC) Controls the operation of GPIO pin 43.                     */
9063 
9064     struct {
9065       __IOM uint32_t FNCSEL43   : 4;            /*!< [3..0] Function select for GPIO pin 43                                    */
9066       __IOM uint32_t INPEN43    : 1;            /*!< [4..4] Input enable for GPIO 43                                           */
9067       __IOM uint32_t RDZERO43   : 1;            /*!< [5..5] Return 0 for read data on GPIO 43                                  */
9068       __IOM uint32_t IRPTEN43   : 2;            /*!< [7..6] Interrupt enable for GPIO 43                                       */
9069       __IOM uint32_t OUTCFG43   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 43                              */
9070       __IOM uint32_t DS43       : 2;            /*!< [11..10] Drive strength selection for GPIO 43                             */
9071       __IOM uint32_t SR43       : 1;            /*!< [12..12] Configure the slew rate                                          */
9072       __IOM uint32_t PULLCFG43  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 43                        */
9073       __IOM uint32_t NCESRC43   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 43, DISP control signals
9074                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9075                                                      field                                                                     */
9076       __IOM uint32_t NCEPOL43   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 43                              */
9077             uint32_t            : 3;
9078       __IOM uint32_t FIEN43     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9079                                                      Otherwise the selected function will enable the input only
9080                                                      when needed                                                               */
9081       __IOM uint32_t FOEN43     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9082                                                      Otherwise the selected function will enable the output
9083                                                      only when needed                                                          */
9084             uint32_t            : 4;
9085     } PINCFG43_b;
9086   } ;
9087 
9088   union {
9089     __IOM uint32_t PINCFG44;                    /*!< (@ 0x000000B0) Controls the operation of GPIO pin 44.                     */
9090 
9091     struct {
9092       __IOM uint32_t FNCSEL44   : 4;            /*!< [3..0] Function select for GPIO pin 44                                    */
9093       __IOM uint32_t INPEN44    : 1;            /*!< [4..4] Input enable for GPIO 44                                           */
9094       __IOM uint32_t RDZERO44   : 1;            /*!< [5..5] Return 0 for read data on GPIO 44                                  */
9095       __IOM uint32_t IRPTEN44   : 2;            /*!< [7..6] Interrupt enable for GPIO 44                                       */
9096       __IOM uint32_t OUTCFG44   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 44                              */
9097       __IOM uint32_t DS44       : 2;            /*!< [11..10] Drive strength selection for GPIO 44                             */
9098       __IOM uint32_t SR44       : 1;            /*!< [12..12] Configure the slew rate                                          */
9099       __IOM uint32_t PULLCFG44  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 44                        */
9100       __IOM uint32_t NCESRC44   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 44, DISP control signals
9101                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9102                                                      field                                                                     */
9103       __IOM uint32_t NCEPOL44   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 44                              */
9104             uint32_t            : 3;
9105       __IOM uint32_t FIEN44     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9106                                                      Otherwise the selected function will enable the input only
9107                                                      when needed                                                               */
9108       __IOM uint32_t FOEN44     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9109                                                      Otherwise the selected function will enable the output
9110                                                      only when needed                                                          */
9111             uint32_t            : 4;
9112     } PINCFG44_b;
9113   } ;
9114 
9115   union {
9116     __IOM uint32_t PINCFG45;                    /*!< (@ 0x000000B4) Controls the operation of GPIO pin 45.                     */
9117 
9118     struct {
9119       __IOM uint32_t FNCSEL45   : 4;            /*!< [3..0] Function select for GPIO pin 45                                    */
9120       __IOM uint32_t INPEN45    : 1;            /*!< [4..4] Input enable for GPIO 45                                           */
9121       __IOM uint32_t RDZERO45   : 1;            /*!< [5..5] Return 0 for read data on GPIO 45                                  */
9122       __IOM uint32_t IRPTEN45   : 2;            /*!< [7..6] Interrupt enable for GPIO 45                                       */
9123       __IOM uint32_t OUTCFG45   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 45                              */
9124       __IOM uint32_t DS45       : 2;            /*!< [11..10] Drive strength selection for GPIO 45                             */
9125       __IOM uint32_t SR45       : 1;            /*!< [12..12] Configure the slew rate                                          */
9126       __IOM uint32_t PULLCFG45  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 45                        */
9127       __IOM uint32_t NCESRC45   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 45, DISP control signals
9128                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9129                                                      field                                                                     */
9130       __IOM uint32_t NCEPOL45   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 45                              */
9131             uint32_t            : 3;
9132       __IOM uint32_t FIEN45     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9133                                                      Otherwise the selected function will enable the input only
9134                                                      when needed                                                               */
9135       __IOM uint32_t FOEN45     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9136                                                      Otherwise the selected function will enable the output
9137                                                      only when needed                                                          */
9138             uint32_t            : 4;
9139     } PINCFG45_b;
9140   } ;
9141 
9142   union {
9143     __IOM uint32_t PINCFG46;                    /*!< (@ 0x000000B8) Controls the operation of GPIO pin 46.                     */
9144 
9145     struct {
9146       __IOM uint32_t FNCSEL46   : 4;            /*!< [3..0] Function select for GPIO pin 46                                    */
9147       __IOM uint32_t INPEN46    : 1;            /*!< [4..4] Input enable for GPIO 46                                           */
9148       __IOM uint32_t RDZERO46   : 1;            /*!< [5..5] Return 0 for read data on GPIO 46                                  */
9149       __IOM uint32_t IRPTEN46   : 2;            /*!< [7..6] Interrupt enable for GPIO 46                                       */
9150       __IOM uint32_t OUTCFG46   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 46                              */
9151       __IOM uint32_t DS46       : 2;            /*!< [11..10] Drive strength selection for GPIO 46                             */
9152       __IOM uint32_t SR46       : 1;            /*!< [12..12] Configure the slew rate                                          */
9153       __IOM uint32_t PULLCFG46  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 46                        */
9154       __IOM uint32_t NCESRC46   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 46, DISP control signals
9155                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9156                                                      field                                                                     */
9157       __IOM uint32_t NCEPOL46   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 46                              */
9158             uint32_t            : 3;
9159       __IOM uint32_t FIEN46     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9160                                                      Otherwise the selected function will enable the input only
9161                                                      when needed                                                               */
9162       __IOM uint32_t FOEN46     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9163                                                      Otherwise the selected function will enable the output
9164                                                      only when needed                                                          */
9165             uint32_t            : 4;
9166     } PINCFG46_b;
9167   } ;
9168 
9169   union {
9170     __IOM uint32_t PINCFG47;                    /*!< (@ 0x000000BC) Controls the operation of GPIO pin 47.                     */
9171 
9172     struct {
9173       __IOM uint32_t FNCSEL47   : 4;            /*!< [3..0] Function select for GPIO pin 47                                    */
9174       __IOM uint32_t INPEN47    : 1;            /*!< [4..4] Input enable for GPIO 47                                           */
9175       __IOM uint32_t RDZERO47   : 1;            /*!< [5..5] Return 0 for read data on GPIO 47                                  */
9176       __IOM uint32_t IRPTEN47   : 2;            /*!< [7..6] Interrupt enable for GPIO 47                                       */
9177       __IOM uint32_t OUTCFG47   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 47                              */
9178       __IOM uint32_t DS47       : 2;            /*!< [11..10] Drive strength selection for GPIO 47                             */
9179       __IOM uint32_t SR47       : 1;            /*!< [12..12] Configure the slew rate                                          */
9180       __IOM uint32_t PULLCFG47  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 47                        */
9181       __IOM uint32_t NCESRC47   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 47, DISP control signals
9182                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9183                                                      field                                                                     */
9184       __IOM uint32_t NCEPOL47   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 47                              */
9185             uint32_t            : 3;
9186       __IOM uint32_t FIEN47     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9187                                                      Otherwise the selected function will enable the input only
9188                                                      when needed                                                               */
9189       __IOM uint32_t FOEN47     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9190                                                      Otherwise the selected function will enable the output
9191                                                      only when needed                                                          */
9192             uint32_t            : 4;
9193     } PINCFG47_b;
9194   } ;
9195 
9196   union {
9197     __IOM uint32_t PINCFG48;                    /*!< (@ 0x000000C0) Controls the operation of GPIO pin 48.                     */
9198 
9199     struct {
9200       __IOM uint32_t FNCSEL48   : 4;            /*!< [3..0] Function select for GPIO pin 48                                    */
9201       __IOM uint32_t INPEN48    : 1;            /*!< [4..4] Input enable for GPIO 48                                           */
9202       __IOM uint32_t RDZERO48   : 1;            /*!< [5..5] Return 0 for read data on GPIO 48                                  */
9203       __IOM uint32_t IRPTEN48   : 2;            /*!< [7..6] Interrupt enable for GPIO 48                                       */
9204       __IOM uint32_t OUTCFG48   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 48                              */
9205       __IOM uint32_t DS48       : 2;            /*!< [11..10] Drive strength selection for GPIO 48                             */
9206       __IOM uint32_t SR48       : 1;            /*!< [12..12] Configure the slew rate                                          */
9207       __IOM uint32_t PULLCFG48  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 48                        */
9208       __IOM uint32_t NCESRC48   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 48, DISP control signals
9209                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9210                                                      field                                                                     */
9211       __IOM uint32_t NCEPOL48   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 48                              */
9212             uint32_t            : 3;
9213       __IOM uint32_t FIEN48     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9214                                                      Otherwise the selected function will enable the input only
9215                                                      when needed                                                               */
9216       __IOM uint32_t FOEN48     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9217                                                      Otherwise the selected function will enable the output
9218                                                      only when needed                                                          */
9219             uint32_t            : 4;
9220     } PINCFG48_b;
9221   } ;
9222 
9223   union {
9224     __IOM uint32_t PINCFG49;                    /*!< (@ 0x000000C4) Controls the operation of GPIO pin 49.                     */
9225 
9226     struct {
9227       __IOM uint32_t FNCSEL49   : 4;            /*!< [3..0] Function select for GPIO pin 49                                    */
9228       __IOM uint32_t INPEN49    : 1;            /*!< [4..4] Input enable for GPIO 49                                           */
9229       __IOM uint32_t RDZERO49   : 1;            /*!< [5..5] Return 0 for read data on GPIO 49                                  */
9230       __IOM uint32_t IRPTEN49   : 2;            /*!< [7..6] Interrupt enable for GPIO 49                                       */
9231       __IOM uint32_t OUTCFG49   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 49                              */
9232       __IOM uint32_t DS49       : 2;            /*!< [11..10] Drive strength selection for GPIO 49                             */
9233       __IOM uint32_t SR49       : 1;            /*!< [12..12] Configure the slew rate                                          */
9234       __IOM uint32_t PULLCFG49  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 49                        */
9235       __IOM uint32_t NCESRC49   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 49, DISP control signals
9236                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9237                                                      field                                                                     */
9238       __IOM uint32_t NCEPOL49   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 49                              */
9239             uint32_t            : 3;
9240       __IOM uint32_t FIEN49     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9241                                                      Otherwise the selected function will enable the input only
9242                                                      when needed                                                               */
9243       __IOM uint32_t FOEN49     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9244                                                      Otherwise the selected function will enable the output
9245                                                      only when needed                                                          */
9246             uint32_t            : 4;
9247     } PINCFG49_b;
9248   } ;
9249 
9250   union {
9251     __IOM uint32_t PINCFG50;                    /*!< (@ 0x000000C8) Controls the operation of GPIO pin 50.                     */
9252 
9253     struct {
9254       __IOM uint32_t FNCSEL50   : 4;            /*!< [3..0] Function select for GPIO pin 50                                    */
9255       __IOM uint32_t INPEN50    : 1;            /*!< [4..4] Input enable for GPIO 50                                           */
9256       __IOM uint32_t RDZERO50   : 1;            /*!< [5..5] Return 0 for read data on GPIO 50                                  */
9257       __IOM uint32_t IRPTEN50   : 2;            /*!< [7..6] Interrupt enable for GPIO 50                                       */
9258       __IOM uint32_t OUTCFG50   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 50                              */
9259       __IOM uint32_t DS50       : 2;            /*!< [11..10] Drive strength selection for GPIO 50                             */
9260       __IOM uint32_t SR50       : 1;            /*!< [12..12] Configure the slew rate                                          */
9261       __IOM uint32_t PULLCFG50  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 50                        */
9262       __IOM uint32_t NCESRC50   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 50, DISP control signals
9263                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9264                                                      field                                                                     */
9265       __IOM uint32_t NCEPOL50   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 50                              */
9266             uint32_t            : 3;
9267       __IOM uint32_t FIEN50     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9268                                                      Otherwise the selected function will enable the input only
9269                                                      when needed                                                               */
9270       __IOM uint32_t FOEN50     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9271                                                      Otherwise the selected function will enable the output
9272                                                      only when needed                                                          */
9273             uint32_t            : 4;
9274     } PINCFG50_b;
9275   } ;
9276 
9277   union {
9278     __IOM uint32_t PINCFG51;                    /*!< (@ 0x000000CC) Controls the operation of GPIO pin 51.                     */
9279 
9280     struct {
9281       __IOM uint32_t FNCSEL51   : 4;            /*!< [3..0] Function select for GPIO pin 51                                    */
9282       __IOM uint32_t INPEN51    : 1;            /*!< [4..4] Input enable for GPIO 51                                           */
9283       __IOM uint32_t RDZERO51   : 1;            /*!< [5..5] Return 0 for read data on GPIO 51                                  */
9284       __IOM uint32_t IRPTEN51   : 2;            /*!< [7..6] Interrupt enable for GPIO 51                                       */
9285       __IOM uint32_t OUTCFG51   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 51                              */
9286       __IOM uint32_t DS51       : 2;            /*!< [11..10] Drive strength selection for GPIO 51                             */
9287       __IOM uint32_t SR51       : 1;            /*!< [12..12] Configure the slew rate                                          */
9288       __IOM uint32_t PULLCFG51  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 51                        */
9289       __IOM uint32_t NCESRC51   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 51, DISP control signals
9290                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9291                                                      field                                                                     */
9292       __IOM uint32_t NCEPOL51   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 51                              */
9293             uint32_t            : 3;
9294       __IOM uint32_t FIEN51     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9295                                                      Otherwise the selected function will enable the input only
9296                                                      when needed                                                               */
9297       __IOM uint32_t FOEN51     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9298                                                      Otherwise the selected function will enable the output
9299                                                      only when needed                                                          */
9300             uint32_t            : 4;
9301     } PINCFG51_b;
9302   } ;
9303 
9304   union {
9305     __IOM uint32_t PINCFG52;                    /*!< (@ 0x000000D0) Controls the operation of GPIO pin 52.                     */
9306 
9307     struct {
9308       __IOM uint32_t FNCSEL52   : 4;            /*!< [3..0] Function select for GPIO pin 52                                    */
9309       __IOM uint32_t INPEN52    : 1;            /*!< [4..4] Input enable for GPIO 52                                           */
9310       __IOM uint32_t RDZERO52   : 1;            /*!< [5..5] Return 0 for read data on GPIO 52                                  */
9311       __IOM uint32_t IRPTEN52   : 2;            /*!< [7..6] Interrupt enable for GPIO 52                                       */
9312       __IOM uint32_t OUTCFG52   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 52                              */
9313       __IOM uint32_t DS52       : 2;            /*!< [11..10] Drive strength selection for GPIO 52                             */
9314       __IOM uint32_t SR52       : 1;            /*!< [12..12] Configure the slew rate                                          */
9315       __IOM uint32_t PULLCFG52  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 52                        */
9316       __IOM uint32_t NCESRC52   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 52, DISP control signals
9317                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9318                                                      field                                                                     */
9319       __IOM uint32_t NCEPOL52   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 52                              */
9320             uint32_t            : 3;
9321       __IOM uint32_t FIEN52     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9322                                                      Otherwise the selected function will enable the input only
9323                                                      when needed                                                               */
9324       __IOM uint32_t FOEN52     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9325                                                      Otherwise the selected function will enable the output
9326                                                      only when needed                                                          */
9327             uint32_t            : 4;
9328     } PINCFG52_b;
9329   } ;
9330 
9331   union {
9332     __IOM uint32_t PINCFG53;                    /*!< (@ 0x000000D4) Controls the operation of GPIO pin 53.                     */
9333 
9334     struct {
9335       __IOM uint32_t FNCSEL53   : 4;            /*!< [3..0] Function select for GPIO pin 53                                    */
9336       __IOM uint32_t INPEN53    : 1;            /*!< [4..4] Input enable for GPIO 53                                           */
9337       __IOM uint32_t RDZERO53   : 1;            /*!< [5..5] Return 0 for read data on GPIO 53                                  */
9338       __IOM uint32_t IRPTEN53   : 2;            /*!< [7..6] Interrupt enable for GPIO 53                                       */
9339       __IOM uint32_t OUTCFG53   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 53                              */
9340       __IOM uint32_t DS53       : 2;            /*!< [11..10] Drive strength selection for GPIO 53                             */
9341       __IOM uint32_t SR53       : 1;            /*!< [12..12] Configure the slew rate                                          */
9342       __IOM uint32_t PULLCFG53  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 53                        */
9343       __IOM uint32_t NCESRC53   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 53, DISP control signals
9344                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9345                                                      field                                                                     */
9346       __IOM uint32_t NCEPOL53   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 53                              */
9347             uint32_t            : 3;
9348       __IOM uint32_t FIEN53     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9349                                                      Otherwise the selected function will enable the input only
9350                                                      when needed                                                               */
9351       __IOM uint32_t FOEN53     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9352                                                      Otherwise the selected function will enable the output
9353                                                      only when needed                                                          */
9354             uint32_t            : 4;
9355     } PINCFG53_b;
9356   } ;
9357 
9358   union {
9359     __IOM uint32_t PINCFG54;                    /*!< (@ 0x000000D8) Controls the operation of GPIO pin 54.                     */
9360 
9361     struct {
9362       __IOM uint32_t FNCSEL54   : 4;            /*!< [3..0] Function select for GPIO pin 54                                    */
9363       __IOM uint32_t INPEN54    : 1;            /*!< [4..4] Input enable for GPIO 54                                           */
9364       __IOM uint32_t RDZERO54   : 1;            /*!< [5..5] Return 0 for read data on GPIO 54                                  */
9365       __IOM uint32_t IRPTEN54   : 2;            /*!< [7..6] Interrupt enable for GPIO 54                                       */
9366       __IOM uint32_t OUTCFG54   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 54                              */
9367       __IOM uint32_t DS54       : 2;            /*!< [11..10] Drive strength selection for GPIO 54                             */
9368       __IOM uint32_t SR54       : 1;            /*!< [12..12] Configure the slew rate                                          */
9369       __IOM uint32_t PULLCFG54  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 54                        */
9370       __IOM uint32_t NCESRC54   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 54, DISP control signals
9371                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9372                                                      field                                                                     */
9373       __IOM uint32_t NCEPOL54   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 54                              */
9374             uint32_t            : 3;
9375       __IOM uint32_t FIEN54     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9376                                                      Otherwise the selected function will enable the input only
9377                                                      when needed                                                               */
9378       __IOM uint32_t FOEN54     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9379                                                      Otherwise the selected function will enable the output
9380                                                      only when needed                                                          */
9381             uint32_t            : 4;
9382     } PINCFG54_b;
9383   } ;
9384 
9385   union {
9386     __IOM uint32_t PINCFG55;                    /*!< (@ 0x000000DC) Controls the operation of GPIO pin 55.                     */
9387 
9388     struct {
9389       __IOM uint32_t FNCSEL55   : 4;            /*!< [3..0] Function select for GPIO pin 55                                    */
9390       __IOM uint32_t INPEN55    : 1;            /*!< [4..4] Input enable for GPIO 55                                           */
9391       __IOM uint32_t RDZERO55   : 1;            /*!< [5..5] Return 0 for read data on GPIO 55                                  */
9392       __IOM uint32_t IRPTEN55   : 2;            /*!< [7..6] Interrupt enable for GPIO 55                                       */
9393       __IOM uint32_t OUTCFG55   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 55                              */
9394       __IOM uint32_t DS55       : 2;            /*!< [11..10] Drive strength selection for GPIO 55                             */
9395       __IOM uint32_t SR55       : 1;            /*!< [12..12] Configure the slew rate                                          */
9396       __IOM uint32_t PULLCFG55  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 55                        */
9397       __IOM uint32_t NCESRC55   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 55, DISP control signals
9398                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9399                                                      field                                                                     */
9400       __IOM uint32_t NCEPOL55   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 55                              */
9401             uint32_t            : 3;
9402       __IOM uint32_t FIEN55     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9403                                                      Otherwise the selected function will enable the input only
9404                                                      when needed                                                               */
9405       __IOM uint32_t FOEN55     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9406                                                      Otherwise the selected function will enable the output
9407                                                      only when needed                                                          */
9408             uint32_t            : 4;
9409     } PINCFG55_b;
9410   } ;
9411 
9412   union {
9413     __IOM uint32_t PINCFG56;                    /*!< (@ 0x000000E0) Controls the operation of GPIO pin 56.                     */
9414 
9415     struct {
9416       __IOM uint32_t FNCSEL56   : 4;            /*!< [3..0] Function select for GPIO pin 56                                    */
9417       __IOM uint32_t INPEN56    : 1;            /*!< [4..4] Input enable for GPIO 56                                           */
9418       __IOM uint32_t RDZERO56   : 1;            /*!< [5..5] Return 0 for read data on GPIO 56                                  */
9419       __IOM uint32_t IRPTEN56   : 2;            /*!< [7..6] Interrupt enable for GPIO 56                                       */
9420       __IOM uint32_t OUTCFG56   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 56                              */
9421       __IOM uint32_t DS56       : 2;            /*!< [11..10] Drive strength selection for GPIO 56                             */
9422       __IOM uint32_t SR56       : 1;            /*!< [12..12] Configure the slew rate                                          */
9423       __IOM uint32_t PULLCFG56  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 56                        */
9424       __IOM uint32_t NCESRC56   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 56, DISP control signals
9425                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9426                                                      field                                                                     */
9427       __IOM uint32_t NCEPOL56   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 56                              */
9428             uint32_t            : 3;
9429       __IOM uint32_t FIEN56     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9430                                                      Otherwise the selected function will enable the input only
9431                                                      when needed                                                               */
9432       __IOM uint32_t FOEN56     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9433                                                      Otherwise the selected function will enable the output
9434                                                      only when needed                                                          */
9435             uint32_t            : 4;
9436     } PINCFG56_b;
9437   } ;
9438 
9439   union {
9440     __IOM uint32_t PINCFG57;                    /*!< (@ 0x000000E4) Controls the operation of GPIO pin 57.                     */
9441 
9442     struct {
9443       __IOM uint32_t FNCSEL57   : 4;            /*!< [3..0] Function select for GPIO pin 57                                    */
9444       __IOM uint32_t INPEN57    : 1;            /*!< [4..4] Input enable for GPIO 57                                           */
9445       __IOM uint32_t RDZERO57   : 1;            /*!< [5..5] Return 0 for read data on GPIO 57                                  */
9446       __IOM uint32_t IRPTEN57   : 2;            /*!< [7..6] Interrupt enable for GPIO 57                                       */
9447       __IOM uint32_t OUTCFG57   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 57                              */
9448       __IOM uint32_t DS57       : 2;            /*!< [11..10] Drive strength selection for GPIO 57                             */
9449       __IOM uint32_t SR57       : 1;            /*!< [12..12] Configure the slew rate                                          */
9450       __IOM uint32_t PULLCFG57  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 57                        */
9451       __IOM uint32_t NCESRC57   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 57, DISP control signals
9452                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9453                                                      field                                                                     */
9454       __IOM uint32_t NCEPOL57   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 57                              */
9455             uint32_t            : 3;
9456       __IOM uint32_t FIEN57     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9457                                                      Otherwise the selected function will enable the input only
9458                                                      when needed                                                               */
9459       __IOM uint32_t FOEN57     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9460                                                      Otherwise the selected function will enable the output
9461                                                      only when needed                                                          */
9462             uint32_t            : 4;
9463     } PINCFG57_b;
9464   } ;
9465 
9466   union {
9467     __IOM uint32_t PINCFG58;                    /*!< (@ 0x000000E8) Controls the operation of GPIO pin 58.                     */
9468 
9469     struct {
9470       __IOM uint32_t FNCSEL58   : 4;            /*!< [3..0] Function select for GPIO pin 58                                    */
9471       __IOM uint32_t INPEN58    : 1;            /*!< [4..4] Input enable for GPIO 58                                           */
9472       __IOM uint32_t RDZERO58   : 1;            /*!< [5..5] Return 0 for read data on GPIO 58                                  */
9473       __IOM uint32_t IRPTEN58   : 2;            /*!< [7..6] Interrupt enable for GPIO 58                                       */
9474       __IOM uint32_t OUTCFG58   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 58                              */
9475       __IOM uint32_t DS58       : 2;            /*!< [11..10] Drive strength selection for GPIO 58                             */
9476       __IOM uint32_t SR58       : 1;            /*!< [12..12] Configure the slew rate                                          */
9477       __IOM uint32_t PULLCFG58  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 58                        */
9478       __IOM uint32_t NCESRC58   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 58, DISP control signals
9479                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9480                                                      field                                                                     */
9481       __IOM uint32_t NCEPOL58   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 58                              */
9482             uint32_t            : 3;
9483       __IOM uint32_t FIEN58     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9484                                                      Otherwise the selected function will enable the input only
9485                                                      when needed                                                               */
9486       __IOM uint32_t FOEN58     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9487                                                      Otherwise the selected function will enable the output
9488                                                      only when needed                                                          */
9489             uint32_t            : 4;
9490     } PINCFG58_b;
9491   } ;
9492 
9493   union {
9494     __IOM uint32_t PINCFG59;                    /*!< (@ 0x000000EC) Controls the operation of GPIO pin 59.                     */
9495 
9496     struct {
9497       __IOM uint32_t FNCSEL59   : 4;            /*!< [3..0] Function select for GPIO pin 59                                    */
9498       __IOM uint32_t INPEN59    : 1;            /*!< [4..4] Input enable for GPIO 59                                           */
9499       __IOM uint32_t RDZERO59   : 1;            /*!< [5..5] Return 0 for read data on GPIO 59                                  */
9500       __IOM uint32_t IRPTEN59   : 2;            /*!< [7..6] Interrupt enable for GPIO 59                                       */
9501       __IOM uint32_t OUTCFG59   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 59                              */
9502       __IOM uint32_t DS59       : 2;            /*!< [11..10] Drive strength selection for GPIO 59                             */
9503       __IOM uint32_t SR59       : 1;            /*!< [12..12] Configure the slew rate                                          */
9504       __IOM uint32_t PULLCFG59  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 59                        */
9505       __IOM uint32_t NCESRC59   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 59, DISP control signals
9506                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9507                                                      field                                                                     */
9508       __IOM uint32_t NCEPOL59   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 59                              */
9509             uint32_t            : 3;
9510       __IOM uint32_t FIEN59     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9511                                                      Otherwise the selected function will enable the input only
9512                                                      when needed                                                               */
9513       __IOM uint32_t FOEN59     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9514                                                      Otherwise the selected function will enable the output
9515                                                      only when needed                                                          */
9516             uint32_t            : 4;
9517     } PINCFG59_b;
9518   } ;
9519 
9520   union {
9521     __IOM uint32_t PINCFG60;                    /*!< (@ 0x000000F0) Controls the operation of GPIO pin 60.                     */
9522 
9523     struct {
9524       __IOM uint32_t FNCSEL60   : 4;            /*!< [3..0] Function select for GPIO pin 60                                    */
9525       __IOM uint32_t INPEN60    : 1;            /*!< [4..4] Input enable for GPIO 60                                           */
9526       __IOM uint32_t RDZERO60   : 1;            /*!< [5..5] Return 0 for read data on GPIO 60                                  */
9527       __IOM uint32_t IRPTEN60   : 2;            /*!< [7..6] Interrupt enable for GPIO 60                                       */
9528       __IOM uint32_t OUTCFG60   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 60                              */
9529       __IOM uint32_t DS60       : 2;            /*!< [11..10] Drive strength selection for GPIO 60                             */
9530       __IOM uint32_t SR60       : 1;            /*!< [12..12] Configure the slew rate                                          */
9531       __IOM uint32_t PULLCFG60  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 60                        */
9532       __IOM uint32_t NCESRC60   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 60, DISP control signals
9533                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9534                                                      field                                                                     */
9535       __IOM uint32_t NCEPOL60   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 60                              */
9536             uint32_t            : 3;
9537       __IOM uint32_t FIEN60     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9538                                                      Otherwise the selected function will enable the input only
9539                                                      when needed                                                               */
9540       __IOM uint32_t FOEN60     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9541                                                      Otherwise the selected function will enable the output
9542                                                      only when needed                                                          */
9543             uint32_t            : 4;
9544     } PINCFG60_b;
9545   } ;
9546 
9547   union {
9548     __IOM uint32_t PINCFG61;                    /*!< (@ 0x000000F4) Controls the operation of GPIO pin 61.                     */
9549 
9550     struct {
9551       __IOM uint32_t FNCSEL61   : 4;            /*!< [3..0] Function select for GPIO pin 61                                    */
9552       __IOM uint32_t INPEN61    : 1;            /*!< [4..4] Input enable for GPIO 61                                           */
9553       __IOM uint32_t RDZERO61   : 1;            /*!< [5..5] Return 0 for read data on GPIO 61                                  */
9554       __IOM uint32_t IRPTEN61   : 2;            /*!< [7..6] Interrupt enable for GPIO 61                                       */
9555       __IOM uint32_t OUTCFG61   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 61                              */
9556       __IOM uint32_t DS61       : 2;            /*!< [11..10] Drive strength selection for GPIO 61                             */
9557       __IOM uint32_t SR61       : 1;            /*!< [12..12] Configure the slew rate                                          */
9558       __IOM uint32_t PULLCFG61  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 61                        */
9559       __IOM uint32_t NCESRC61   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 61, DISP control signals
9560                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9561                                                      field                                                                     */
9562       __IOM uint32_t NCEPOL61   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 61                              */
9563             uint32_t            : 3;
9564       __IOM uint32_t FIEN61     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9565                                                      Otherwise the selected function will enable the input only
9566                                                      when needed                                                               */
9567       __IOM uint32_t FOEN61     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9568                                                      Otherwise the selected function will enable the output
9569                                                      only when needed                                                          */
9570             uint32_t            : 4;
9571     } PINCFG61_b;
9572   } ;
9573 
9574   union {
9575     __IOM uint32_t PINCFG62;                    /*!< (@ 0x000000F8) Controls the operation of GPIO pin 62.                     */
9576 
9577     struct {
9578       __IOM uint32_t FNCSEL62   : 4;            /*!< [3..0] Function select for GPIO pin 62                                    */
9579       __IOM uint32_t INPEN62    : 1;            /*!< [4..4] Input enable for GPIO 62                                           */
9580       __IOM uint32_t RDZERO62   : 1;            /*!< [5..5] Return 0 for read data on GPIO 62                                  */
9581       __IOM uint32_t IRPTEN62   : 2;            /*!< [7..6] Interrupt enable for GPIO 62                                       */
9582       __IOM uint32_t OUTCFG62   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 62                              */
9583       __IOM uint32_t DS62       : 2;            /*!< [11..10] Drive strength selection for GPIO 62                             */
9584       __IOM uint32_t SR62       : 1;            /*!< [12..12] Configure the slew rate                                          */
9585       __IOM uint32_t PULLCFG62  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 62                        */
9586       __IOM uint32_t NCESRC62   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 62, DISP control signals
9587                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9588                                                      field                                                                     */
9589       __IOM uint32_t NCEPOL62   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 62                              */
9590             uint32_t            : 3;
9591       __IOM uint32_t FIEN62     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9592                                                      Otherwise the selected function will enable the input only
9593                                                      when needed                                                               */
9594       __IOM uint32_t FOEN62     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9595                                                      Otherwise the selected function will enable the output
9596                                                      only when needed                                                          */
9597             uint32_t            : 4;
9598     } PINCFG62_b;
9599   } ;
9600 
9601   union {
9602     __IOM uint32_t PINCFG63;                    /*!< (@ 0x000000FC) Controls the operation of GPIO pin 63.                     */
9603 
9604     struct {
9605       __IOM uint32_t FNCSEL63   : 4;            /*!< [3..0] Function select for GPIO pin 63                                    */
9606       __IOM uint32_t INPEN63    : 1;            /*!< [4..4] Input enable for GPIO 63                                           */
9607       __IOM uint32_t RDZERO63   : 1;            /*!< [5..5] Return 0 for read data on GPIO 63                                  */
9608       __IOM uint32_t IRPTEN63   : 2;            /*!< [7..6] Interrupt enable for GPIO 63                                       */
9609       __IOM uint32_t OUTCFG63   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 63                              */
9610       __IOM uint32_t DS63       : 2;            /*!< [11..10] Drive strength selection for GPIO 63                             */
9611       __IOM uint32_t SR63       : 1;            /*!< [12..12] Configure the slew rate                                          */
9612       __IOM uint32_t PULLCFG63  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 63                        */
9613       __IOM uint32_t NCESRC63   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 63, DISP control signals
9614                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9615                                                      field                                                                     */
9616       __IOM uint32_t NCEPOL63   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 63                              */
9617             uint32_t            : 3;
9618       __IOM uint32_t FIEN63     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9619                                                      Otherwise the selected function will enable the input only
9620                                                      when needed                                                               */
9621       __IOM uint32_t FOEN63     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9622                                                      Otherwise the selected function will enable the output
9623                                                      only when needed                                                          */
9624             uint32_t            : 4;
9625     } PINCFG63_b;
9626   } ;
9627 
9628   union {
9629     __IOM uint32_t PINCFG64;                    /*!< (@ 0x00000100) Controls the operation of GPIO pin 64.                     */
9630 
9631     struct {
9632       __IOM uint32_t FNCSEL64   : 4;            /*!< [3..0] Function select for GPIO pin 64                                    */
9633       __IOM uint32_t INPEN64    : 1;            /*!< [4..4] Input enable for GPIO 64                                           */
9634       __IOM uint32_t RDZERO64   : 1;            /*!< [5..5] Return 0 for read data on GPIO 64                                  */
9635       __IOM uint32_t IRPTEN64   : 2;            /*!< [7..6] Interrupt enable for GPIO 64                                       */
9636       __IOM uint32_t OUTCFG64   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 64                              */
9637       __IOM uint32_t DS64       : 2;            /*!< [11..10] Drive strength selection for GPIO 64                             */
9638       __IOM uint32_t SR64       : 1;            /*!< [12..12] Configure the slew rate                                          */
9639       __IOM uint32_t PULLCFG64  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 64                        */
9640       __IOM uint32_t NCESRC64   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 64, DISP control signals
9641                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9642                                                      field                                                                     */
9643       __IOM uint32_t NCEPOL64   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 64                              */
9644             uint32_t            : 3;
9645       __IOM uint32_t FIEN64     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9646                                                      Otherwise the selected function will enable the input only
9647                                                      when needed                                                               */
9648       __IOM uint32_t FOEN64     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9649                                                      Otherwise the selected function will enable the output
9650                                                      only when needed                                                          */
9651             uint32_t            : 4;
9652     } PINCFG64_b;
9653   } ;
9654 
9655   union {
9656     __IOM uint32_t PINCFG65;                    /*!< (@ 0x00000104) Controls the operation of GPIO pin 65.                     */
9657 
9658     struct {
9659       __IOM uint32_t FNCSEL65   : 4;            /*!< [3..0] Function select for GPIO pin 65                                    */
9660       __IOM uint32_t INPEN65    : 1;            /*!< [4..4] Input enable for GPIO 65                                           */
9661       __IOM uint32_t RDZERO65   : 1;            /*!< [5..5] Return 0 for read data on GPIO 65                                  */
9662       __IOM uint32_t IRPTEN65   : 2;            /*!< [7..6] Interrupt enable for GPIO 65                                       */
9663       __IOM uint32_t OUTCFG65   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 65                              */
9664       __IOM uint32_t DS65       : 2;            /*!< [11..10] Drive strength selection for GPIO 65                             */
9665       __IOM uint32_t SR65       : 1;            /*!< [12..12] Configure the slew rate                                          */
9666       __IOM uint32_t PULLCFG65  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 65                        */
9667       __IOM uint32_t NCESRC65   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 65, DISP control signals
9668                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9669                                                      field                                                                     */
9670       __IOM uint32_t NCEPOL65   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 65                              */
9671             uint32_t            : 3;
9672       __IOM uint32_t FIEN65     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9673                                                      Otherwise the selected function will enable the input only
9674                                                      when needed                                                               */
9675       __IOM uint32_t FOEN65     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9676                                                      Otherwise the selected function will enable the output
9677                                                      only when needed                                                          */
9678             uint32_t            : 4;
9679     } PINCFG65_b;
9680   } ;
9681 
9682   union {
9683     __IOM uint32_t PINCFG66;                    /*!< (@ 0x00000108) Controls the operation of GPIO pin 66.                     */
9684 
9685     struct {
9686       __IOM uint32_t FNCSEL66   : 4;            /*!< [3..0] Function select for GPIO pin 66                                    */
9687       __IOM uint32_t INPEN66    : 1;            /*!< [4..4] Input enable for GPIO 66                                           */
9688       __IOM uint32_t RDZERO66   : 1;            /*!< [5..5] Return 0 for read data on GPIO 66                                  */
9689       __IOM uint32_t IRPTEN66   : 2;            /*!< [7..6] Interrupt enable for GPIO 66                                       */
9690       __IOM uint32_t OUTCFG66   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 66                              */
9691       __IOM uint32_t DS66       : 2;            /*!< [11..10] Drive strength selection for GPIO 66                             */
9692       __IOM uint32_t SR66       : 1;            /*!< [12..12] Configure the slew rate                                          */
9693       __IOM uint32_t PULLCFG66  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 66                        */
9694       __IOM uint32_t NCESRC66   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 66, DISP control signals
9695                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9696                                                      field                                                                     */
9697       __IOM uint32_t NCEPOL66   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 66                              */
9698             uint32_t            : 3;
9699       __IOM uint32_t FIEN66     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9700                                                      Otherwise the selected function will enable the input only
9701                                                      when needed                                                               */
9702       __IOM uint32_t FOEN66     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9703                                                      Otherwise the selected function will enable the output
9704                                                      only when needed                                                          */
9705             uint32_t            : 4;
9706     } PINCFG66_b;
9707   } ;
9708 
9709   union {
9710     __IOM uint32_t PINCFG67;                    /*!< (@ 0x0000010C) Controls the operation of GPIO pin 67.                     */
9711 
9712     struct {
9713       __IOM uint32_t FNCSEL67   : 4;            /*!< [3..0] Function select for GPIO pin 67                                    */
9714       __IOM uint32_t INPEN67    : 1;            /*!< [4..4] Input enable for GPIO 67                                           */
9715       __IOM uint32_t RDZERO67   : 1;            /*!< [5..5] Return 0 for read data on GPIO 67                                  */
9716       __IOM uint32_t IRPTEN67   : 2;            /*!< [7..6] Interrupt enable for GPIO 67                                       */
9717       __IOM uint32_t OUTCFG67   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 67                              */
9718       __IOM uint32_t DS67       : 2;            /*!< [11..10] Drive strength selection for GPIO 67                             */
9719       __IOM uint32_t SR67       : 1;            /*!< [12..12] Configure the slew rate                                          */
9720       __IOM uint32_t PULLCFG67  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 67                        */
9721       __IOM uint32_t NCESRC67   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 67, DISP control signals
9722                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9723                                                      field                                                                     */
9724       __IOM uint32_t NCEPOL67   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 67                              */
9725             uint32_t            : 3;
9726       __IOM uint32_t FIEN67     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9727                                                      Otherwise the selected function will enable the input only
9728                                                      when needed                                                               */
9729       __IOM uint32_t FOEN67     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9730                                                      Otherwise the selected function will enable the output
9731                                                      only when needed                                                          */
9732             uint32_t            : 4;
9733     } PINCFG67_b;
9734   } ;
9735 
9736   union {
9737     __IOM uint32_t PINCFG68;                    /*!< (@ 0x00000110) Controls the operation of GPIO pin 68.                     */
9738 
9739     struct {
9740       __IOM uint32_t FNCSEL68   : 4;            /*!< [3..0] Function select for GPIO pin 68                                    */
9741       __IOM uint32_t INPEN68    : 1;            /*!< [4..4] Input enable for GPIO 68                                           */
9742       __IOM uint32_t RDZERO68   : 1;            /*!< [5..5] Return 0 for read data on GPIO 68                                  */
9743       __IOM uint32_t IRPTEN68   : 2;            /*!< [7..6] Interrupt enable for GPIO 68                                       */
9744       __IOM uint32_t OUTCFG68   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 68                              */
9745       __IOM uint32_t DS68       : 2;            /*!< [11..10] Drive strength selection for GPIO 68                             */
9746       __IOM uint32_t SR68       : 1;            /*!< [12..12] Configure the slew rate                                          */
9747       __IOM uint32_t PULLCFG68  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 68                        */
9748       __IOM uint32_t NCESRC68   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 68, DISP control signals
9749                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9750                                                      field                                                                     */
9751       __IOM uint32_t NCEPOL68   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 68                              */
9752             uint32_t            : 3;
9753       __IOM uint32_t FIEN68     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9754                                                      Otherwise the selected function will enable the input only
9755                                                      when needed                                                               */
9756       __IOM uint32_t FOEN68     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9757                                                      Otherwise the selected function will enable the output
9758                                                      only when needed                                                          */
9759             uint32_t            : 4;
9760     } PINCFG68_b;
9761   } ;
9762 
9763   union {
9764     __IOM uint32_t PINCFG69;                    /*!< (@ 0x00000114) Controls the operation of GPIO pin 69.                     */
9765 
9766     struct {
9767       __IOM uint32_t FNCSEL69   : 4;            /*!< [3..0] Function select for GPIO pin 69                                    */
9768       __IOM uint32_t INPEN69    : 1;            /*!< [4..4] Input enable for GPIO 69                                           */
9769       __IOM uint32_t RDZERO69   : 1;            /*!< [5..5] Return 0 for read data on GPIO 69                                  */
9770       __IOM uint32_t IRPTEN69   : 2;            /*!< [7..6] Interrupt enable for GPIO 69                                       */
9771       __IOM uint32_t OUTCFG69   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 69                              */
9772       __IOM uint32_t DS69       : 2;            /*!< [11..10] Drive strength selection for GPIO 69                             */
9773       __IOM uint32_t SR69       : 1;            /*!< [12..12] Configure the slew rate                                          */
9774       __IOM uint32_t PULLCFG69  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 69                        */
9775       __IOM uint32_t NCESRC69   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 69, DISP control signals
9776                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9777                                                      field                                                                     */
9778       __IOM uint32_t NCEPOL69   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 69                              */
9779             uint32_t            : 3;
9780       __IOM uint32_t FIEN69     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9781                                                      Otherwise the selected function will enable the input only
9782                                                      when needed                                                               */
9783       __IOM uint32_t FOEN69     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9784                                                      Otherwise the selected function will enable the output
9785                                                      only when needed                                                          */
9786             uint32_t            : 4;
9787     } PINCFG69_b;
9788   } ;
9789 
9790   union {
9791     __IOM uint32_t PINCFG70;                    /*!< (@ 0x00000118) Controls the operation of GPIO pin 70.                     */
9792 
9793     struct {
9794       __IOM uint32_t FNCSEL70   : 4;            /*!< [3..0] Function select for GPIO pin 70                                    */
9795       __IOM uint32_t INPEN70    : 1;            /*!< [4..4] Input enable for GPIO 70                                           */
9796       __IOM uint32_t RDZERO70   : 1;            /*!< [5..5] Return 0 for read data on GPIO 70                                  */
9797       __IOM uint32_t IRPTEN70   : 2;            /*!< [7..6] Interrupt enable for GPIO 70                                       */
9798       __IOM uint32_t OUTCFG70   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 70                              */
9799       __IOM uint32_t DS70       : 2;            /*!< [11..10] Drive strength selection for GPIO 70                             */
9800       __IOM uint32_t SR70       : 1;            /*!< [12..12] Configure the slew rate                                          */
9801       __IOM uint32_t PULLCFG70  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 70                        */
9802       __IOM uint32_t NCESRC70   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 70, DISP control signals
9803                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9804                                                      field                                                                     */
9805       __IOM uint32_t NCEPOL70   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 70                              */
9806             uint32_t            : 3;
9807       __IOM uint32_t FIEN70     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9808                                                      Otherwise the selected function will enable the input only
9809                                                      when needed                                                               */
9810       __IOM uint32_t FOEN70     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9811                                                      Otherwise the selected function will enable the output
9812                                                      only when needed                                                          */
9813             uint32_t            : 4;
9814     } PINCFG70_b;
9815   } ;
9816 
9817   union {
9818     __IOM uint32_t PINCFG71;                    /*!< (@ 0x0000011C) Controls the operation of GPIO pin 71.                     */
9819 
9820     struct {
9821       __IOM uint32_t FNCSEL71   : 4;            /*!< [3..0] Function select for GPIO pin 71                                    */
9822       __IOM uint32_t INPEN71    : 1;            /*!< [4..4] Input enable for GPIO 71                                           */
9823       __IOM uint32_t RDZERO71   : 1;            /*!< [5..5] Return 0 for read data on GPIO 71                                  */
9824       __IOM uint32_t IRPTEN71   : 2;            /*!< [7..6] Interrupt enable for GPIO 71                                       */
9825       __IOM uint32_t OUTCFG71   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 71                              */
9826       __IOM uint32_t DS71       : 2;            /*!< [11..10] Drive strength selection for GPIO 71                             */
9827       __IOM uint32_t SR71       : 1;            /*!< [12..12] Configure the slew rate                                          */
9828       __IOM uint32_t PULLCFG71  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 71                        */
9829       __IOM uint32_t NCESRC71   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 71, DISP control signals
9830                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9831                                                      field                                                                     */
9832       __IOM uint32_t NCEPOL71   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 71                              */
9833             uint32_t            : 3;
9834       __IOM uint32_t FIEN71     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9835                                                      Otherwise the selected function will enable the input only
9836                                                      when needed                                                               */
9837       __IOM uint32_t FOEN71     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9838                                                      Otherwise the selected function will enable the output
9839                                                      only when needed                                                          */
9840             uint32_t            : 4;
9841     } PINCFG71_b;
9842   } ;
9843 
9844   union {
9845     __IOM uint32_t PINCFG72;                    /*!< (@ 0x00000120) Controls the operation of GPIO pin 72.                     */
9846 
9847     struct {
9848       __IOM uint32_t FNCSEL72   : 4;            /*!< [3..0] Function select for GPIO pin 72                                    */
9849       __IOM uint32_t INPEN72    : 1;            /*!< [4..4] Input enable for GPIO 72                                           */
9850       __IOM uint32_t RDZERO72   : 1;            /*!< [5..5] Return 0 for read data on GPIO 72                                  */
9851       __IOM uint32_t IRPTEN72   : 2;            /*!< [7..6] Interrupt enable for GPIO 72                                       */
9852       __IOM uint32_t OUTCFG72   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 72                              */
9853       __IOM uint32_t DS72       : 2;            /*!< [11..10] Drive strength selection for GPIO 72                             */
9854       __IOM uint32_t SR72       : 1;            /*!< [12..12] Configure the slew rate                                          */
9855       __IOM uint32_t PULLCFG72  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 72                        */
9856       __IOM uint32_t NCESRC72   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 72, DISP control signals
9857                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9858                                                      field                                                                     */
9859       __IOM uint32_t NCEPOL72   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 72                              */
9860             uint32_t            : 3;
9861       __IOM uint32_t FIEN72     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9862                                                      Otherwise the selected function will enable the input only
9863                                                      when needed                                                               */
9864       __IOM uint32_t FOEN72     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9865                                                      Otherwise the selected function will enable the output
9866                                                      only when needed                                                          */
9867             uint32_t            : 4;
9868     } PINCFG72_b;
9869   } ;
9870 
9871   union {
9872     __IOM uint32_t PINCFG73;                    /*!< (@ 0x00000124) Controls the operation of GPIO pin 73.                     */
9873 
9874     struct {
9875       __IOM uint32_t FNCSEL73   : 4;            /*!< [3..0] Function select for GPIO pin 73                                    */
9876       __IOM uint32_t INPEN73    : 1;            /*!< [4..4] Input enable for GPIO 73                                           */
9877       __IOM uint32_t RDZERO73   : 1;            /*!< [5..5] Return 0 for read data on GPIO 73                                  */
9878       __IOM uint32_t IRPTEN73   : 2;            /*!< [7..6] Interrupt enable for GPIO 73                                       */
9879       __IOM uint32_t OUTCFG73   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 73                              */
9880       __IOM uint32_t DS73       : 2;            /*!< [11..10] Drive strength selection for GPIO 73                             */
9881       __IOM uint32_t SR73       : 1;            /*!< [12..12] Configure the slew rate                                          */
9882       __IOM uint32_t PULLCFG73  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 73                        */
9883       __IOM uint32_t NCESRC73   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 73, DISP control signals
9884                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9885                                                      field                                                                     */
9886       __IOM uint32_t NCEPOL73   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 73                              */
9887             uint32_t            : 3;
9888       __IOM uint32_t FIEN73     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9889                                                      Otherwise the selected function will enable the input only
9890                                                      when needed                                                               */
9891       __IOM uint32_t FOEN73     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9892                                                      Otherwise the selected function will enable the output
9893                                                      only when needed                                                          */
9894             uint32_t            : 4;
9895     } PINCFG73_b;
9896   } ;
9897 
9898   union {
9899     __IOM uint32_t PINCFG74;                    /*!< (@ 0x00000128) Controls the operation of GPIO pin 74.                     */
9900 
9901     struct {
9902       __IOM uint32_t FNCSEL74   : 4;            /*!< [3..0] Function select for GPIO pin 74                                    */
9903       __IOM uint32_t INPEN74    : 1;            /*!< [4..4] Input enable for GPIO 74                                           */
9904       __IOM uint32_t RDZERO74   : 1;            /*!< [5..5] Return 0 for read data on GPIO 74                                  */
9905       __IOM uint32_t IRPTEN74   : 2;            /*!< [7..6] Interrupt enable for GPIO 74                                       */
9906       __IOM uint32_t OUTCFG74   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 74                              */
9907       __IOM uint32_t DS74       : 2;            /*!< [11..10] Drive strength selection for GPIO 74                             */
9908       __IOM uint32_t SR74       : 1;            /*!< [12..12] Configure the slew rate                                          */
9909       __IOM uint32_t PULLCFG74  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 74                        */
9910       __IOM uint32_t NCESRC74   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 74, DISP control signals
9911                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9912                                                      field                                                                     */
9913       __IOM uint32_t NCEPOL74   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 74                              */
9914             uint32_t            : 3;
9915       __IOM uint32_t FIEN74     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9916                                                      Otherwise the selected function will enable the input only
9917                                                      when needed                                                               */
9918       __IOM uint32_t FOEN74     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9919                                                      Otherwise the selected function will enable the output
9920                                                      only when needed                                                          */
9921             uint32_t            : 4;
9922     } PINCFG74_b;
9923   } ;
9924 
9925   union {
9926     __IOM uint32_t PINCFG75;                    /*!< (@ 0x0000012C) Controls the operation of GPIO pin 75.                     */
9927 
9928     struct {
9929       __IOM uint32_t FNCSEL75   : 4;            /*!< [3..0] Function select for GPIO pin 75                                    */
9930       __IOM uint32_t INPEN75    : 1;            /*!< [4..4] Input enable for GPIO 75                                           */
9931       __IOM uint32_t RDZERO75   : 1;            /*!< [5..5] Return 0 for read data on GPIO 75                                  */
9932       __IOM uint32_t IRPTEN75   : 2;            /*!< [7..6] Interrupt enable for GPIO 75                                       */
9933       __IOM uint32_t OUTCFG75   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 75                              */
9934       __IOM uint32_t DS75       : 2;            /*!< [11..10] Drive strength selection for GPIO 75                             */
9935       __IOM uint32_t SR75       : 1;            /*!< [12..12] Configure the slew rate                                          */
9936       __IOM uint32_t PULLCFG75  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 75                        */
9937       __IOM uint32_t NCESRC75   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 75, DISP control signals
9938                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9939                                                      field                                                                     */
9940       __IOM uint32_t NCEPOL75   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 75                              */
9941             uint32_t            : 3;
9942       __IOM uint32_t FIEN75     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9943                                                      Otherwise the selected function will enable the input only
9944                                                      when needed                                                               */
9945       __IOM uint32_t FOEN75     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9946                                                      Otherwise the selected function will enable the output
9947                                                      only when needed                                                          */
9948             uint32_t            : 4;
9949     } PINCFG75_b;
9950   } ;
9951 
9952   union {
9953     __IOM uint32_t PINCFG76;                    /*!< (@ 0x00000130) Controls the operation of GPIO pin 76.                     */
9954 
9955     struct {
9956       __IOM uint32_t FNCSEL76   : 4;            /*!< [3..0] Function select for GPIO pin 76                                    */
9957       __IOM uint32_t INPEN76    : 1;            /*!< [4..4] Input enable for GPIO 76                                           */
9958       __IOM uint32_t RDZERO76   : 1;            /*!< [5..5] Return 0 for read data on GPIO 76                                  */
9959       __IOM uint32_t IRPTEN76   : 2;            /*!< [7..6] Interrupt enable for GPIO 76                                       */
9960       __IOM uint32_t OUTCFG76   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 76                              */
9961       __IOM uint32_t DS76       : 2;            /*!< [11..10] Drive strength selection for GPIO 76                             */
9962       __IOM uint32_t SR76       : 1;            /*!< [12..12] Configure the slew rate                                          */
9963       __IOM uint32_t PULLCFG76  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 76                        */
9964       __IOM uint32_t NCESRC76   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 76, DISP control signals
9965                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9966                                                      field                                                                     */
9967       __IOM uint32_t NCEPOL76   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 76                              */
9968             uint32_t            : 3;
9969       __IOM uint32_t FIEN76     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9970                                                      Otherwise the selected function will enable the input only
9971                                                      when needed                                                               */
9972       __IOM uint32_t FOEN76     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9973                                                      Otherwise the selected function will enable the output
9974                                                      only when needed                                                          */
9975             uint32_t            : 4;
9976     } PINCFG76_b;
9977   } ;
9978 
9979   union {
9980     __IOM uint32_t PINCFG77;                    /*!< (@ 0x00000134) Controls the operation of GPIO pin 77.                     */
9981 
9982     struct {
9983       __IOM uint32_t FNCSEL77   : 4;            /*!< [3..0] Function select for GPIO pin 77                                    */
9984       __IOM uint32_t INPEN77    : 1;            /*!< [4..4] Input enable for GPIO 77                                           */
9985       __IOM uint32_t RDZERO77   : 1;            /*!< [5..5] Return 0 for read data on GPIO 77                                  */
9986       __IOM uint32_t IRPTEN77   : 2;            /*!< [7..6] Interrupt enable for GPIO 77                                       */
9987       __IOM uint32_t OUTCFG77   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 77                              */
9988       __IOM uint32_t DS77       : 2;            /*!< [11..10] Drive strength selection for GPIO 77                             */
9989       __IOM uint32_t SR77       : 1;            /*!< [12..12] Configure the slew rate                                          */
9990       __IOM uint32_t PULLCFG77  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 77                        */
9991       __IOM uint32_t NCESRC77   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 77, DISP control signals
9992                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9993                                                      field                                                                     */
9994       __IOM uint32_t NCEPOL77   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 77                              */
9995             uint32_t            : 3;
9996       __IOM uint32_t FIEN77     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9997                                                      Otherwise the selected function will enable the input only
9998                                                      when needed                                                               */
9999       __IOM uint32_t FOEN77     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10000                                                      Otherwise the selected function will enable the output
10001                                                      only when needed                                                          */
10002             uint32_t            : 4;
10003     } PINCFG77_b;
10004   } ;
10005 
10006   union {
10007     __IOM uint32_t PINCFG78;                    /*!< (@ 0x00000138) Controls the operation of GPIO pin 78.                     */
10008 
10009     struct {
10010       __IOM uint32_t FNCSEL78   : 4;            /*!< [3..0] Function select for GPIO pin 78                                    */
10011       __IOM uint32_t INPEN78    : 1;            /*!< [4..4] Input enable for GPIO 78                                           */
10012       __IOM uint32_t RDZERO78   : 1;            /*!< [5..5] Return 0 for read data on GPIO 78                                  */
10013       __IOM uint32_t IRPTEN78   : 2;            /*!< [7..6] Interrupt enable for GPIO 78                                       */
10014       __IOM uint32_t OUTCFG78   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 78                              */
10015       __IOM uint32_t DS78       : 2;            /*!< [11..10] Drive strength selection for GPIO 78                             */
10016       __IOM uint32_t SR78       : 1;            /*!< [12..12] Configure the slew rate                                          */
10017       __IOM uint32_t PULLCFG78  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 78                        */
10018       __IOM uint32_t NCESRC78   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 78, DISP control signals
10019                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10020                                                      field                                                                     */
10021       __IOM uint32_t NCEPOL78   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 78                              */
10022             uint32_t            : 3;
10023       __IOM uint32_t FIEN78     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10024                                                      Otherwise the selected function will enable the input only
10025                                                      when needed                                                               */
10026       __IOM uint32_t FOEN78     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10027                                                      Otherwise the selected function will enable the output
10028                                                      only when needed                                                          */
10029             uint32_t            : 4;
10030     } PINCFG78_b;
10031   } ;
10032 
10033   union {
10034     __IOM uint32_t PINCFG79;                    /*!< (@ 0x0000013C) Controls the operation of GPIO pin 79.                     */
10035 
10036     struct {
10037       __IOM uint32_t FNCSEL79   : 4;            /*!< [3..0] Function select for GPIO pin 79                                    */
10038       __IOM uint32_t INPEN79    : 1;            /*!< [4..4] Input enable for GPIO 79                                           */
10039       __IOM uint32_t RDZERO79   : 1;            /*!< [5..5] Return 0 for read data on GPIO 79                                  */
10040       __IOM uint32_t IRPTEN79   : 2;            /*!< [7..6] Interrupt enable for GPIO 79                                       */
10041       __IOM uint32_t OUTCFG79   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 79                              */
10042       __IOM uint32_t DS79       : 2;            /*!< [11..10] Drive strength selection for GPIO 79                             */
10043       __IOM uint32_t SR79       : 1;            /*!< [12..12] Configure the slew rate                                          */
10044       __IOM uint32_t PULLCFG79  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 79                        */
10045       __IOM uint32_t NCESRC79   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 79, DISP control signals
10046                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10047                                                      field                                                                     */
10048       __IOM uint32_t NCEPOL79   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 79                              */
10049             uint32_t            : 3;
10050       __IOM uint32_t FIEN79     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10051                                                      Otherwise the selected function will enable the input only
10052                                                      when needed                                                               */
10053       __IOM uint32_t FOEN79     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10054                                                      Otherwise the selected function will enable the output
10055                                                      only when needed                                                          */
10056             uint32_t            : 4;
10057     } PINCFG79_b;
10058   } ;
10059 
10060   union {
10061     __IOM uint32_t PINCFG80;                    /*!< (@ 0x00000140) Controls the operation of GPIO pin 80.                     */
10062 
10063     struct {
10064       __IOM uint32_t FNCSEL80   : 4;            /*!< [3..0] Function select for GPIO pin 80                                    */
10065       __IOM uint32_t INPEN80    : 1;            /*!< [4..4] Input enable for GPIO 80                                           */
10066       __IOM uint32_t RDZERO80   : 1;            /*!< [5..5] Return 0 for read data on GPIO 80                                  */
10067       __IOM uint32_t IRPTEN80   : 2;            /*!< [7..6] Interrupt enable for GPIO 80                                       */
10068       __IOM uint32_t OUTCFG80   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 80                              */
10069       __IOM uint32_t DS80       : 2;            /*!< [11..10] Drive strength selection for GPIO 80                             */
10070       __IOM uint32_t SR80       : 1;            /*!< [12..12] Configure the slew rate                                          */
10071       __IOM uint32_t PULLCFG80  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 80                        */
10072       __IOM uint32_t NCESRC80   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 80, DISP control signals
10073                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10074                                                      field                                                                     */
10075       __IOM uint32_t NCEPOL80   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 80                              */
10076             uint32_t            : 3;
10077       __IOM uint32_t FIEN80     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10078                                                      Otherwise the selected function will enable the input only
10079                                                      when needed                                                               */
10080       __IOM uint32_t FOEN80     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10081                                                      Otherwise the selected function will enable the output
10082                                                      only when needed                                                          */
10083             uint32_t            : 4;
10084     } PINCFG80_b;
10085   } ;
10086 
10087   union {
10088     __IOM uint32_t PINCFG81;                    /*!< (@ 0x00000144) Controls the operation of GPIO pin 81.                     */
10089 
10090     struct {
10091       __IOM uint32_t FNCSEL81   : 4;            /*!< [3..0] Function select for GPIO pin 81                                    */
10092       __IOM uint32_t INPEN81    : 1;            /*!< [4..4] Input enable for GPIO 81                                           */
10093       __IOM uint32_t RDZERO81   : 1;            /*!< [5..5] Return 0 for read data on GPIO 81                                  */
10094       __IOM uint32_t IRPTEN81   : 2;            /*!< [7..6] Interrupt enable for GPIO 81                                       */
10095       __IOM uint32_t OUTCFG81   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 81                              */
10096       __IOM uint32_t DS81       : 2;            /*!< [11..10] Drive strength selection for GPIO 81                             */
10097       __IOM uint32_t SR81       : 1;            /*!< [12..12] Configure the slew rate                                          */
10098       __IOM uint32_t PULLCFG81  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 81                        */
10099       __IOM uint32_t NCESRC81   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 81, DISP control signals
10100                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10101                                                      field                                                                     */
10102       __IOM uint32_t NCEPOL81   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 81                              */
10103             uint32_t            : 3;
10104       __IOM uint32_t FIEN81     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10105                                                      Otherwise the selected function will enable the input only
10106                                                      when needed                                                               */
10107       __IOM uint32_t FOEN81     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10108                                                      Otherwise the selected function will enable the output
10109                                                      only when needed                                                          */
10110             uint32_t            : 4;
10111     } PINCFG81_b;
10112   } ;
10113 
10114   union {
10115     __IOM uint32_t PINCFG82;                    /*!< (@ 0x00000148) Controls the operation of GPIO pin 82.                     */
10116 
10117     struct {
10118       __IOM uint32_t FNCSEL82   : 4;            /*!< [3..0] Function select for GPIO pin 82                                    */
10119       __IOM uint32_t INPEN82    : 1;            /*!< [4..4] Input enable for GPIO 82                                           */
10120       __IOM uint32_t RDZERO82   : 1;            /*!< [5..5] Return 0 for read data on GPIO 82                                  */
10121       __IOM uint32_t IRPTEN82   : 2;            /*!< [7..6] Interrupt enable for GPIO 82                                       */
10122       __IOM uint32_t OUTCFG82   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 82                              */
10123       __IOM uint32_t DS82       : 2;            /*!< [11..10] Drive strength selection for GPIO 82                             */
10124       __IOM uint32_t SR82       : 1;            /*!< [12..12] Configure the slew rate                                          */
10125       __IOM uint32_t PULLCFG82  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 82                        */
10126       __IOM uint32_t NCESRC82   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 82, DISP control signals
10127                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10128                                                      field                                                                     */
10129       __IOM uint32_t NCEPOL82   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 82                              */
10130             uint32_t            : 3;
10131       __IOM uint32_t FIEN82     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10132                                                      Otherwise the selected function will enable the input only
10133                                                      when needed                                                               */
10134       __IOM uint32_t FOEN82     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10135                                                      Otherwise the selected function will enable the output
10136                                                      only when needed                                                          */
10137             uint32_t            : 4;
10138     } PINCFG82_b;
10139   } ;
10140 
10141   union {
10142     __IOM uint32_t PINCFG83;                    /*!< (@ 0x0000014C) Controls the operation of GPIO pin 83.                     */
10143 
10144     struct {
10145       __IOM uint32_t FNCSEL83   : 4;            /*!< [3..0] Function select for GPIO pin 83                                    */
10146       __IOM uint32_t INPEN83    : 1;            /*!< [4..4] Input enable for GPIO 83                                           */
10147       __IOM uint32_t RDZERO83   : 1;            /*!< [5..5] Return 0 for read data on GPIO 83                                  */
10148       __IOM uint32_t IRPTEN83   : 2;            /*!< [7..6] Interrupt enable for GPIO 83                                       */
10149       __IOM uint32_t OUTCFG83   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 83                              */
10150       __IOM uint32_t DS83       : 2;            /*!< [11..10] Drive strength selection for GPIO 83                             */
10151       __IOM uint32_t SR83       : 1;            /*!< [12..12] Configure the slew rate                                          */
10152       __IOM uint32_t PULLCFG83  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 83                        */
10153       __IOM uint32_t NCESRC83   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 83, DISP control signals
10154                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10155                                                      field                                                                     */
10156       __IOM uint32_t NCEPOL83   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 83                              */
10157             uint32_t            : 3;
10158       __IOM uint32_t FIEN83     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10159                                                      Otherwise the selected function will enable the input only
10160                                                      when needed                                                               */
10161       __IOM uint32_t FOEN83     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10162                                                      Otherwise the selected function will enable the output
10163                                                      only when needed                                                          */
10164             uint32_t            : 4;
10165     } PINCFG83_b;
10166   } ;
10167 
10168   union {
10169     __IOM uint32_t PINCFG84;                    /*!< (@ 0x00000150) Controls the operation of GPIO pin 84.                     */
10170 
10171     struct {
10172       __IOM uint32_t FNCSEL84   : 4;            /*!< [3..0] Function select for GPIO pin 84                                    */
10173       __IOM uint32_t INPEN84    : 1;            /*!< [4..4] Input enable for GPIO 84                                           */
10174       __IOM uint32_t RDZERO84   : 1;            /*!< [5..5] Return 0 for read data on GPIO 84                                  */
10175       __IOM uint32_t IRPTEN84   : 2;            /*!< [7..6] Interrupt enable for GPIO 84                                       */
10176       __IOM uint32_t OUTCFG84   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 84                              */
10177       __IOM uint32_t DS84       : 2;            /*!< [11..10] Drive strength selection for GPIO 84                             */
10178       __IOM uint32_t SR84       : 1;            /*!< [12..12] Configure the slew rate                                          */
10179       __IOM uint32_t PULLCFG84  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 84                        */
10180       __IOM uint32_t NCESRC84   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 84, DISP control signals
10181                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10182                                                      field                                                                     */
10183       __IOM uint32_t NCEPOL84   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 84                              */
10184             uint32_t            : 3;
10185       __IOM uint32_t FIEN84     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10186                                                      Otherwise the selected function will enable the input only
10187                                                      when needed                                                               */
10188       __IOM uint32_t FOEN84     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10189                                                      Otherwise the selected function will enable the output
10190                                                      only when needed                                                          */
10191             uint32_t            : 4;
10192     } PINCFG84_b;
10193   } ;
10194 
10195   union {
10196     __IOM uint32_t PINCFG85;                    /*!< (@ 0x00000154) Controls the operation of GPIO pin 85.                     */
10197 
10198     struct {
10199       __IOM uint32_t FNCSEL85   : 4;            /*!< [3..0] Function select for GPIO pin 85                                    */
10200       __IOM uint32_t INPEN85    : 1;            /*!< [4..4] Input enable for GPIO 85                                           */
10201       __IOM uint32_t RDZERO85   : 1;            /*!< [5..5] Return 0 for read data on GPIO 85                                  */
10202       __IOM uint32_t IRPTEN85   : 2;            /*!< [7..6] Interrupt enable for GPIO 85                                       */
10203       __IOM uint32_t OUTCFG85   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 85                              */
10204       __IOM uint32_t DS85       : 2;            /*!< [11..10] Drive strength selection for GPIO 85                             */
10205       __IOM uint32_t SR85       : 1;            /*!< [12..12] Configure the slew rate                                          */
10206       __IOM uint32_t PULLCFG85  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 85                        */
10207       __IOM uint32_t NCESRC85   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 85, DISP control signals
10208                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10209                                                      field                                                                     */
10210       __IOM uint32_t NCEPOL85   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 85                              */
10211             uint32_t            : 3;
10212       __IOM uint32_t FIEN85     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10213                                                      Otherwise the selected function will enable the input only
10214                                                      when needed                                                               */
10215       __IOM uint32_t FOEN85     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10216                                                      Otherwise the selected function will enable the output
10217                                                      only when needed                                                          */
10218             uint32_t            : 4;
10219     } PINCFG85_b;
10220   } ;
10221 
10222   union {
10223     __IOM uint32_t PINCFG86;                    /*!< (@ 0x00000158) Controls the operation of GPIO pin 86.                     */
10224 
10225     struct {
10226       __IOM uint32_t FNCSEL86   : 4;            /*!< [3..0] Function select for GPIO pin 86                                    */
10227       __IOM uint32_t INPEN86    : 1;            /*!< [4..4] Input enable for GPIO 86                                           */
10228       __IOM uint32_t RDZERO86   : 1;            /*!< [5..5] Return 0 for read data on GPIO 86                                  */
10229       __IOM uint32_t IRPTEN86   : 2;            /*!< [7..6] Interrupt enable for GPIO 86                                       */
10230       __IOM uint32_t OUTCFG86   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 86                              */
10231       __IOM uint32_t DS86       : 2;            /*!< [11..10] Drive strength selection for GPIO 86                             */
10232       __IOM uint32_t SR86       : 1;            /*!< [12..12] Configure the slew rate                                          */
10233       __IOM uint32_t PULLCFG86  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 86                        */
10234       __IOM uint32_t NCESRC86   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 86, DISP control signals
10235                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10236                                                      field                                                                     */
10237       __IOM uint32_t NCEPOL86   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 86                              */
10238             uint32_t            : 3;
10239       __IOM uint32_t FIEN86     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10240                                                      Otherwise the selected function will enable the input only
10241                                                      when needed                                                               */
10242       __IOM uint32_t FOEN86     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10243                                                      Otherwise the selected function will enable the output
10244                                                      only when needed                                                          */
10245             uint32_t            : 4;
10246     } PINCFG86_b;
10247   } ;
10248 
10249   union {
10250     __IOM uint32_t PINCFG87;                    /*!< (@ 0x0000015C) Controls the operation of GPIO pin 87.                     */
10251 
10252     struct {
10253       __IOM uint32_t FNCSEL87   : 4;            /*!< [3..0] Function select for GPIO pin 87                                    */
10254       __IOM uint32_t INPEN87    : 1;            /*!< [4..4] Input enable for GPIO 87                                           */
10255       __IOM uint32_t RDZERO87   : 1;            /*!< [5..5] Return 0 for read data on GPIO 87                                  */
10256       __IOM uint32_t IRPTEN87   : 2;            /*!< [7..6] Interrupt enable for GPIO 87                                       */
10257       __IOM uint32_t OUTCFG87   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 87                              */
10258       __IOM uint32_t DS87       : 2;            /*!< [11..10] Drive strength selection for GPIO 87                             */
10259       __IOM uint32_t SR87       : 1;            /*!< [12..12] Configure the slew rate                                          */
10260       __IOM uint32_t PULLCFG87  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 87                        */
10261       __IOM uint32_t NCESRC87   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 87, DISP control signals
10262                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10263                                                      field                                                                     */
10264       __IOM uint32_t NCEPOL87   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 87                              */
10265             uint32_t            : 3;
10266       __IOM uint32_t FIEN87     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10267                                                      Otherwise the selected function will enable the input only
10268                                                      when needed                                                               */
10269       __IOM uint32_t FOEN87     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10270                                                      Otherwise the selected function will enable the output
10271                                                      only when needed                                                          */
10272             uint32_t            : 4;
10273     } PINCFG87_b;
10274   } ;
10275 
10276   union {
10277     __IOM uint32_t PINCFG88;                    /*!< (@ 0x00000160) Controls the operation of GPIO pin 88.                     */
10278 
10279     struct {
10280       __IOM uint32_t FNCSEL88   : 4;            /*!< [3..0] Function select for GPIO pin 88                                    */
10281       __IOM uint32_t INPEN88    : 1;            /*!< [4..4] Input enable for GPIO 88                                           */
10282       __IOM uint32_t RDZERO88   : 1;            /*!< [5..5] Return 0 for read data on GPIO 88                                  */
10283       __IOM uint32_t IRPTEN88   : 2;            /*!< [7..6] Interrupt enable for GPIO 88                                       */
10284       __IOM uint32_t OUTCFG88   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 88                              */
10285       __IOM uint32_t DS88       : 2;            /*!< [11..10] Drive strength selection for GPIO 88                             */
10286       __IOM uint32_t SR88       : 1;            /*!< [12..12] Configure the slew rate                                          */
10287       __IOM uint32_t PULLCFG88  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 88                        */
10288       __IOM uint32_t NCESRC88   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 88, DISP control signals
10289                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10290                                                      field                                                                     */
10291       __IOM uint32_t NCEPOL88   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 88                              */
10292             uint32_t            : 3;
10293       __IOM uint32_t FIEN88     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10294                                                      Otherwise the selected function will enable the input only
10295                                                      when needed                                                               */
10296       __IOM uint32_t FOEN88     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10297                                                      Otherwise the selected function will enable the output
10298                                                      only when needed                                                          */
10299             uint32_t            : 4;
10300     } PINCFG88_b;
10301   } ;
10302 
10303   union {
10304     __IOM uint32_t PINCFG89;                    /*!< (@ 0x00000164) Controls the operation of GPIO pin 89.                     */
10305 
10306     struct {
10307       __IOM uint32_t FNCSEL89   : 4;            /*!< [3..0] Function select for GPIO pin 89                                    */
10308       __IOM uint32_t INPEN89    : 1;            /*!< [4..4] Input enable for GPIO 89                                           */
10309       __IOM uint32_t RDZERO89   : 1;            /*!< [5..5] Return 0 for read data on GPIO 89                                  */
10310       __IOM uint32_t IRPTEN89   : 2;            /*!< [7..6] Interrupt enable for GPIO 89                                       */
10311       __IOM uint32_t OUTCFG89   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 89                              */
10312       __IOM uint32_t DS89       : 2;            /*!< [11..10] Drive strength selection for GPIO 89                             */
10313       __IOM uint32_t SR89       : 1;            /*!< [12..12] Configure the slew rate                                          */
10314       __IOM uint32_t PULLCFG89  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 89                        */
10315       __IOM uint32_t NCESRC89   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 89, DISP control signals
10316                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10317                                                      field                                                                     */
10318       __IOM uint32_t NCEPOL89   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 89                              */
10319             uint32_t            : 3;
10320       __IOM uint32_t FIEN89     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10321                                                      Otherwise the selected function will enable the input only
10322                                                      when needed                                                               */
10323       __IOM uint32_t FOEN89     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10324                                                      Otherwise the selected function will enable the output
10325                                                      only when needed                                                          */
10326             uint32_t            : 4;
10327     } PINCFG89_b;
10328   } ;
10329 
10330   union {
10331     __IOM uint32_t PINCFG90;                    /*!< (@ 0x00000168) Controls the operation of GPIO pin 90.                     */
10332 
10333     struct {
10334       __IOM uint32_t FNCSEL90   : 4;            /*!< [3..0] Function select for GPIO pin 90                                    */
10335       __IOM uint32_t INPEN90    : 1;            /*!< [4..4] Input enable for GPIO 90                                           */
10336       __IOM uint32_t RDZERO90   : 1;            /*!< [5..5] Return 0 for read data on GPIO 90                                  */
10337       __IOM uint32_t IRPTEN90   : 2;            /*!< [7..6] Interrupt enable for GPIO 90                                       */
10338       __IOM uint32_t OUTCFG90   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 90                              */
10339       __IOM uint32_t DS90       : 2;            /*!< [11..10] Drive strength selection for GPIO 90                             */
10340       __IOM uint32_t SR90       : 1;            /*!< [12..12] Configure the slew rate                                          */
10341       __IOM uint32_t PULLCFG90  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 90                        */
10342       __IOM uint32_t NCESRC90   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 90, DISP control signals
10343                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10344                                                      field                                                                     */
10345       __IOM uint32_t NCEPOL90   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 90                              */
10346             uint32_t            : 3;
10347       __IOM uint32_t FIEN90     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10348                                                      Otherwise the selected function will enable the input only
10349                                                      when needed                                                               */
10350       __IOM uint32_t FOEN90     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10351                                                      Otherwise the selected function will enable the output
10352                                                      only when needed                                                          */
10353             uint32_t            : 4;
10354     } PINCFG90_b;
10355   } ;
10356 
10357   union {
10358     __IOM uint32_t PINCFG91;                    /*!< (@ 0x0000016C) Controls the operation of GPIO pin 91.                     */
10359 
10360     struct {
10361       __IOM uint32_t FNCSEL91   : 4;            /*!< [3..0] Function select for GPIO pin 91                                    */
10362       __IOM uint32_t INPEN91    : 1;            /*!< [4..4] Input enable for GPIO 91                                           */
10363       __IOM uint32_t RDZERO91   : 1;            /*!< [5..5] Return 0 for read data on GPIO 91                                  */
10364       __IOM uint32_t IRPTEN91   : 2;            /*!< [7..6] Interrupt enable for GPIO 91                                       */
10365       __IOM uint32_t OUTCFG91   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 91                              */
10366       __IOM uint32_t DS91       : 2;            /*!< [11..10] Drive strength selection for GPIO 91                             */
10367       __IOM uint32_t SR91       : 1;            /*!< [12..12] Configure the slew rate                                          */
10368       __IOM uint32_t PULLCFG91  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 91                        */
10369       __IOM uint32_t NCESRC91   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 91, DISP control signals
10370                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10371                                                      field                                                                     */
10372       __IOM uint32_t NCEPOL91   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 91                              */
10373             uint32_t            : 3;
10374       __IOM uint32_t FIEN91     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10375                                                      Otherwise the selected function will enable the input only
10376                                                      when needed                                                               */
10377       __IOM uint32_t FOEN91     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10378                                                      Otherwise the selected function will enable the output
10379                                                      only when needed                                                          */
10380             uint32_t            : 4;
10381     } PINCFG91_b;
10382   } ;
10383 
10384   union {
10385     __IOM uint32_t PINCFG92;                    /*!< (@ 0x00000170) Controls the operation of GPIO pin 92.                     */
10386 
10387     struct {
10388       __IOM uint32_t FNCSEL92   : 4;            /*!< [3..0] Function select for GPIO pin 92                                    */
10389       __IOM uint32_t INPEN92    : 1;            /*!< [4..4] Input enable for GPIO 92                                           */
10390       __IOM uint32_t RDZERO92   : 1;            /*!< [5..5] Return 0 for read data on GPIO 92                                  */
10391       __IOM uint32_t IRPTEN92   : 2;            /*!< [7..6] Interrupt enable for GPIO 92                                       */
10392       __IOM uint32_t OUTCFG92   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 92                              */
10393       __IOM uint32_t DS92       : 2;            /*!< [11..10] Drive strength selection for GPIO 92                             */
10394       __IOM uint32_t SR92       : 1;            /*!< [12..12] Configure the slew rate                                          */
10395       __IOM uint32_t PULLCFG92  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 92                        */
10396       __IOM uint32_t NCESRC92   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 92, DISP control signals
10397                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10398                                                      field                                                                     */
10399       __IOM uint32_t NCEPOL92   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 92                              */
10400             uint32_t            : 3;
10401       __IOM uint32_t FIEN92     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10402                                                      Otherwise the selected function will enable the input only
10403                                                      when needed                                                               */
10404       __IOM uint32_t FOEN92     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10405                                                      Otherwise the selected function will enable the output
10406                                                      only when needed                                                          */
10407             uint32_t            : 4;
10408     } PINCFG92_b;
10409   } ;
10410 
10411   union {
10412     __IOM uint32_t PINCFG93;                    /*!< (@ 0x00000174) Controls the operation of GPIO pin 93.                     */
10413 
10414     struct {
10415       __IOM uint32_t FNCSEL93   : 4;            /*!< [3..0] Function select for GPIO pin 93                                    */
10416       __IOM uint32_t INPEN93    : 1;            /*!< [4..4] Input enable for GPIO 93                                           */
10417       __IOM uint32_t RDZERO93   : 1;            /*!< [5..5] Return 0 for read data on GPIO 93                                  */
10418       __IOM uint32_t IRPTEN93   : 2;            /*!< [7..6] Interrupt enable for GPIO 93                                       */
10419       __IOM uint32_t OUTCFG93   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 93                              */
10420       __IOM uint32_t DS93       : 2;            /*!< [11..10] Drive strength selection for GPIO 93                             */
10421       __IOM uint32_t SR93       : 1;            /*!< [12..12] Configure the slew rate                                          */
10422       __IOM uint32_t PULLCFG93  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 93                        */
10423       __IOM uint32_t NCESRC93   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 93, DISP control signals
10424                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10425                                                      field                                                                     */
10426       __IOM uint32_t NCEPOL93   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 93                              */
10427             uint32_t            : 3;
10428       __IOM uint32_t FIEN93     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10429                                                      Otherwise the selected function will enable the input only
10430                                                      when needed                                                               */
10431       __IOM uint32_t FOEN93     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10432                                                      Otherwise the selected function will enable the output
10433                                                      only when needed                                                          */
10434             uint32_t            : 4;
10435     } PINCFG93_b;
10436   } ;
10437 
10438   union {
10439     __IOM uint32_t PINCFG94;                    /*!< (@ 0x00000178) Controls the operation of GPIO pin 94.                     */
10440 
10441     struct {
10442       __IOM uint32_t FNCSEL94   : 4;            /*!< [3..0] Function select for GPIO pin 94                                    */
10443       __IOM uint32_t INPEN94    : 1;            /*!< [4..4] Input enable for GPIO 94                                           */
10444       __IOM uint32_t RDZERO94   : 1;            /*!< [5..5] Return 0 for read data on GPIO 94                                  */
10445       __IOM uint32_t IRPTEN94   : 2;            /*!< [7..6] Interrupt enable for GPIO 94                                       */
10446       __IOM uint32_t OUTCFG94   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 94                              */
10447       __IOM uint32_t DS94       : 2;            /*!< [11..10] Drive strength selection for GPIO 94                             */
10448       __IOM uint32_t SR94       : 1;            /*!< [12..12] Configure the slew rate                                          */
10449       __IOM uint32_t PULLCFG94  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 94                        */
10450       __IOM uint32_t NCESRC94   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 94, DISP control signals
10451                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10452                                                      field                                                                     */
10453       __IOM uint32_t NCEPOL94   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 94                              */
10454             uint32_t            : 3;
10455       __IOM uint32_t FIEN94     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10456                                                      Otherwise the selected function will enable the input only
10457                                                      when needed                                                               */
10458       __IOM uint32_t FOEN94     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10459                                                      Otherwise the selected function will enable the output
10460                                                      only when needed                                                          */
10461             uint32_t            : 4;
10462     } PINCFG94_b;
10463   } ;
10464 
10465   union {
10466     __IOM uint32_t PINCFG95;                    /*!< (@ 0x0000017C) Controls the operation of GPIO pin 95.                     */
10467 
10468     struct {
10469       __IOM uint32_t FNCSEL95   : 4;            /*!< [3..0] Function select for GPIO pin 95                                    */
10470       __IOM uint32_t INPEN95    : 1;            /*!< [4..4] Input enable for GPIO 95                                           */
10471       __IOM uint32_t RDZERO95   : 1;            /*!< [5..5] Return 0 for read data on GPIO 95                                  */
10472       __IOM uint32_t IRPTEN95   : 2;            /*!< [7..6] Interrupt enable for GPIO 95                                       */
10473       __IOM uint32_t OUTCFG95   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 95                              */
10474       __IOM uint32_t DS95       : 2;            /*!< [11..10] Drive strength selection for GPIO 95                             */
10475       __IOM uint32_t SR95       : 1;            /*!< [12..12] Configure the slew rate                                          */
10476       __IOM uint32_t PULLCFG95  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 95                        */
10477       __IOM uint32_t NCESRC95   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 95, DISP control signals
10478                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10479                                                      field                                                                     */
10480       __IOM uint32_t NCEPOL95   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 95                              */
10481             uint32_t            : 3;
10482       __IOM uint32_t FIEN95     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10483                                                      Otherwise the selected function will enable the input only
10484                                                      when needed                                                               */
10485       __IOM uint32_t FOEN95     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10486                                                      Otherwise the selected function will enable the output
10487                                                      only when needed                                                          */
10488             uint32_t            : 4;
10489     } PINCFG95_b;
10490   } ;
10491 
10492   union {
10493     __IOM uint32_t PINCFG96;                    /*!< (@ 0x00000180) Controls the operation of GPIO pin 96.                     */
10494 
10495     struct {
10496       __IOM uint32_t FNCSEL96   : 4;            /*!< [3..0] Function select for GPIO pin 96                                    */
10497       __IOM uint32_t INPEN96    : 1;            /*!< [4..4] Input enable for GPIO 96                                           */
10498       __IOM uint32_t RDZERO96   : 1;            /*!< [5..5] Return 0 for read data on GPIO 96                                  */
10499       __IOM uint32_t IRPTEN96   : 2;            /*!< [7..6] Interrupt enable for GPIO 96                                       */
10500       __IOM uint32_t OUTCFG96   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 96                              */
10501       __IOM uint32_t DS96       : 2;            /*!< [11..10] Drive strength selection for GPIO 96                             */
10502       __IOM uint32_t SR96       : 1;            /*!< [12..12] Configure the slew rate                                          */
10503       __IOM uint32_t PULLCFG96  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 96                        */
10504       __IOM uint32_t NCESRC96   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 96, DISP control signals
10505                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10506                                                      field                                                                     */
10507       __IOM uint32_t NCEPOL96   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 96                              */
10508             uint32_t            : 3;
10509       __IOM uint32_t FIEN96     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10510                                                      Otherwise the selected function will enable the input only
10511                                                      when needed                                                               */
10512       __IOM uint32_t FOEN96     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10513                                                      Otherwise the selected function will enable the output
10514                                                      only when needed                                                          */
10515             uint32_t            : 4;
10516     } PINCFG96_b;
10517   } ;
10518 
10519   union {
10520     __IOM uint32_t PINCFG97;                    /*!< (@ 0x00000184) Controls the operation of GPIO pin 97.                     */
10521 
10522     struct {
10523       __IOM uint32_t FNCSEL97   : 4;            /*!< [3..0] Function select for GPIO pin 97                                    */
10524       __IOM uint32_t INPEN97    : 1;            /*!< [4..4] Input enable for GPIO 97                                           */
10525       __IOM uint32_t RDZERO97   : 1;            /*!< [5..5] Return 0 for read data on GPIO 97                                  */
10526       __IOM uint32_t IRPTEN97   : 2;            /*!< [7..6] Interrupt enable for GPIO 97                                       */
10527       __IOM uint32_t OUTCFG97   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 97                              */
10528       __IOM uint32_t DS97       : 2;            /*!< [11..10] Drive strength selection for GPIO 97                             */
10529       __IOM uint32_t SR97       : 1;            /*!< [12..12] Configure the slew rate                                          */
10530       __IOM uint32_t PULLCFG97  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 97                        */
10531       __IOM uint32_t NCESRC97   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 97, DISP control signals
10532                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10533                                                      field                                                                     */
10534       __IOM uint32_t NCEPOL97   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 97                              */
10535             uint32_t            : 3;
10536       __IOM uint32_t FIEN97     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10537                                                      Otherwise the selected function will enable the input only
10538                                                      when needed                                                               */
10539       __IOM uint32_t FOEN97     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10540                                                      Otherwise the selected function will enable the output
10541                                                      only when needed                                                          */
10542             uint32_t            : 4;
10543     } PINCFG97_b;
10544   } ;
10545 
10546   union {
10547     __IOM uint32_t PINCFG98;                    /*!< (@ 0x00000188) Controls the operation of GPIO pin 98.                     */
10548 
10549     struct {
10550       __IOM uint32_t FNCSEL98   : 4;            /*!< [3..0] Function select for GPIO pin 98                                    */
10551       __IOM uint32_t INPEN98    : 1;            /*!< [4..4] Input enable for GPIO 98                                           */
10552       __IOM uint32_t RDZERO98   : 1;            /*!< [5..5] Return 0 for read data on GPIO 98                                  */
10553       __IOM uint32_t IRPTEN98   : 2;            /*!< [7..6] Interrupt enable for GPIO 98                                       */
10554       __IOM uint32_t OUTCFG98   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 98                              */
10555       __IOM uint32_t DS98       : 2;            /*!< [11..10] Drive strength selection for GPIO 98                             */
10556       __IOM uint32_t SR98       : 1;            /*!< [12..12] Configure the slew rate                                          */
10557       __IOM uint32_t PULLCFG98  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 98                        */
10558       __IOM uint32_t NCESRC98   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 98, DISP control signals
10559                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10560                                                      field                                                                     */
10561       __IOM uint32_t NCEPOL98   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 98                              */
10562             uint32_t            : 3;
10563       __IOM uint32_t FIEN98     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10564                                                      Otherwise the selected function will enable the input only
10565                                                      when needed                                                               */
10566       __IOM uint32_t FOEN98     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10567                                                      Otherwise the selected function will enable the output
10568                                                      only when needed                                                          */
10569             uint32_t            : 4;
10570     } PINCFG98_b;
10571   } ;
10572 
10573   union {
10574     __IOM uint32_t PINCFG99;                    /*!< (@ 0x0000018C) Controls the operation of GPIO pin 99.                     */
10575 
10576     struct {
10577       __IOM uint32_t FNCSEL99   : 4;            /*!< [3..0] Function select for GPIO pin 99                                    */
10578       __IOM uint32_t INPEN99    : 1;            /*!< [4..4] Input enable for GPIO 99                                           */
10579       __IOM uint32_t RDZERO99   : 1;            /*!< [5..5] Return 0 for read data on GPIO 99                                  */
10580       __IOM uint32_t IRPTEN99   : 2;            /*!< [7..6] Interrupt enable for GPIO 99                                       */
10581       __IOM uint32_t OUTCFG99   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 99                              */
10582       __IOM uint32_t DS99       : 2;            /*!< [11..10] Drive strength selection for GPIO 99                             */
10583       __IOM uint32_t SR99       : 1;            /*!< [12..12] Configure the slew rate                                          */
10584       __IOM uint32_t PULLCFG99  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 99                        */
10585       __IOM uint32_t NCESRC99   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 99, DISP control signals
10586                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10587                                                      field                                                                     */
10588       __IOM uint32_t NCEPOL99   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 99                              */
10589             uint32_t            : 3;
10590       __IOM uint32_t FIEN99     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10591                                                      Otherwise the selected function will enable the input only
10592                                                      when needed                                                               */
10593       __IOM uint32_t FOEN99     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10594                                                      Otherwise the selected function will enable the output
10595                                                      only when needed                                                          */
10596             uint32_t            : 4;
10597     } PINCFG99_b;
10598   } ;
10599 
10600   union {
10601     __IOM uint32_t PINCFG100;                   /*!< (@ 0x00000190) Controls the operation of GPIO pin 100.                    */
10602 
10603     struct {
10604       __IOM uint32_t FNCSEL100  : 4;            /*!< [3..0] Function select for GPIO pin 100                                   */
10605       __IOM uint32_t INPEN100   : 1;            /*!< [4..4] Input enable for GPIO 100                                          */
10606       __IOM uint32_t RDZERO100  : 1;            /*!< [5..5] Return 0 for read data on GPIO 100                                 */
10607       __IOM uint32_t IRPTEN100  : 2;            /*!< [7..6] Interrupt enable for GPIO 100                                      */
10608       __IOM uint32_t OUTCFG100  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 100                             */
10609       __IOM uint32_t DS100      : 2;            /*!< [11..10] Drive strength selection for GPIO 100                            */
10610       __IOM uint32_t SR100      : 1;            /*!< [12..12] Configure the slew rate                                          */
10611       __IOM uint32_t PULLCFG100 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 100                       */
10612       __IOM uint32_t NCESRC100  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 100, DISP control signals
10613                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10614                                                      field                                                                     */
10615       __IOM uint32_t NCEPOL100  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 100                             */
10616             uint32_t            : 3;
10617       __IOM uint32_t FIEN100    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10618                                                      Otherwise the selected function will enable the input only
10619                                                      when needed                                                               */
10620       __IOM uint32_t FOEN100    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10621                                                      Otherwise the selected function will enable the output
10622                                                      only when needed                                                          */
10623             uint32_t            : 4;
10624     } PINCFG100_b;
10625   } ;
10626 
10627   union {
10628     __IOM uint32_t PINCFG101;                   /*!< (@ 0x00000194) Controls the operation of GPIO pin 101.                    */
10629 
10630     struct {
10631       __IOM uint32_t FNCSEL101  : 4;            /*!< [3..0] Function select for GPIO pin 101                                   */
10632       __IOM uint32_t INPEN101   : 1;            /*!< [4..4] Input enable for GPIO 101                                          */
10633       __IOM uint32_t RDZERO101  : 1;            /*!< [5..5] Return 0 for read data on GPIO 101                                 */
10634       __IOM uint32_t IRPTEN101  : 2;            /*!< [7..6] Interrupt enable for GPIO 101                                      */
10635       __IOM uint32_t OUTCFG101  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 101                             */
10636       __IOM uint32_t DS101      : 2;            /*!< [11..10] Drive strength selection for GPIO 101                            */
10637       __IOM uint32_t SR101      : 1;            /*!< [12..12] Configure the slew rate                                          */
10638       __IOM uint32_t PULLCFG101 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 101                       */
10639       __IOM uint32_t NCESRC101  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 101, DISP control signals
10640                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10641                                                      field                                                                     */
10642       __IOM uint32_t NCEPOL101  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 101                             */
10643             uint32_t            : 3;
10644       __IOM uint32_t FIEN101    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10645                                                      Otherwise the selected function will enable the input only
10646                                                      when needed                                                               */
10647       __IOM uint32_t FOEN101    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10648                                                      Otherwise the selected function will enable the output
10649                                                      only when needed                                                          */
10650             uint32_t            : 4;
10651     } PINCFG101_b;
10652   } ;
10653 
10654   union {
10655     __IOM uint32_t PINCFG102;                   /*!< (@ 0x00000198) Controls the operation of GPIO pin 102.                    */
10656 
10657     struct {
10658       __IOM uint32_t FNCSEL102  : 4;            /*!< [3..0] Function select for GPIO pin 102                                   */
10659       __IOM uint32_t INPEN102   : 1;            /*!< [4..4] Input enable for GPIO 102                                          */
10660       __IOM uint32_t RDZERO102  : 1;            /*!< [5..5] Return 0 for read data on GPIO 102                                 */
10661       __IOM uint32_t IRPTEN102  : 2;            /*!< [7..6] Interrupt enable for GPIO 102                                      */
10662       __IOM uint32_t OUTCFG102  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 102                             */
10663       __IOM uint32_t DS102      : 2;            /*!< [11..10] Drive strength selection for GPIO 102                            */
10664       __IOM uint32_t SR102      : 1;            /*!< [12..12] Configure the slew rate                                          */
10665       __IOM uint32_t PULLCFG102 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 102                       */
10666       __IOM uint32_t NCESRC102  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 102, DISP control signals
10667                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10668                                                      field                                                                     */
10669       __IOM uint32_t NCEPOL102  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 102                             */
10670             uint32_t            : 3;
10671       __IOM uint32_t FIEN102    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10672                                                      Otherwise the selected function will enable the input only
10673                                                      when needed                                                               */
10674       __IOM uint32_t FOEN102    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10675                                                      Otherwise the selected function will enable the output
10676                                                      only when needed                                                          */
10677             uint32_t            : 4;
10678     } PINCFG102_b;
10679   } ;
10680 
10681   union {
10682     __IOM uint32_t PINCFG103;                   /*!< (@ 0x0000019C) Controls the operation of GPIO pin 103.                    */
10683 
10684     struct {
10685       __IOM uint32_t FNCSEL103  : 4;            /*!< [3..0] Function select for GPIO pin 103                                   */
10686       __IOM uint32_t INPEN103   : 1;            /*!< [4..4] Input enable for GPIO 103                                          */
10687       __IOM uint32_t RDZERO103  : 1;            /*!< [5..5] Return 0 for read data on GPIO 103                                 */
10688       __IOM uint32_t IRPTEN103  : 2;            /*!< [7..6] Interrupt enable for GPIO 103                                      */
10689       __IOM uint32_t OUTCFG103  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 103                             */
10690       __IOM uint32_t DS103      : 2;            /*!< [11..10] Drive strength selection for GPIO 103                            */
10691       __IOM uint32_t SR103      : 1;            /*!< [12..12] Configure the slew rate                                          */
10692       __IOM uint32_t PULLCFG103 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 103                       */
10693       __IOM uint32_t NCESRC103  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 103, DISP control signals
10694                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10695                                                      field                                                                     */
10696       __IOM uint32_t NCEPOL103  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 103                             */
10697             uint32_t            : 3;
10698       __IOM uint32_t FIEN103    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10699                                                      Otherwise the selected function will enable the input only
10700                                                      when needed                                                               */
10701       __IOM uint32_t FOEN103    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10702                                                      Otherwise the selected function will enable the output
10703                                                      only when needed                                                          */
10704             uint32_t            : 4;
10705     } PINCFG103_b;
10706   } ;
10707 
10708   union {
10709     __IOM uint32_t PINCFG104;                   /*!< (@ 0x000001A0) Controls the operation of GPIO pin 104.                    */
10710 
10711     struct {
10712       __IOM uint32_t FNCSEL104  : 4;            /*!< [3..0] Function select for GPIO pin 104                                   */
10713       __IOM uint32_t INPEN104   : 1;            /*!< [4..4] Input enable for GPIO 104                                          */
10714       __IOM uint32_t RDZERO104  : 1;            /*!< [5..5] Return 0 for read data on GPIO 104                                 */
10715       __IOM uint32_t IRPTEN104  : 2;            /*!< [7..6] Interrupt enable for GPIO 104                                      */
10716       __IOM uint32_t OUTCFG104  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 104                             */
10717       __IOM uint32_t DS104      : 2;            /*!< [11..10] Drive strength selection for GPIO 104                            */
10718       __IOM uint32_t SR104      : 1;            /*!< [12..12] Configure the slew rate                                          */
10719       __IOM uint32_t PULLCFG104 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 104                       */
10720       __IOM uint32_t NCESRC104  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 104, DISP control signals
10721                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10722                                                      field                                                                     */
10723       __IOM uint32_t NCEPOL104  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 104                             */
10724             uint32_t            : 3;
10725       __IOM uint32_t FIEN104    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10726                                                      Otherwise the selected function will enable the input only
10727                                                      when needed                                                               */
10728       __IOM uint32_t FOEN104    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10729                                                      Otherwise the selected function will enable the output
10730                                                      only when needed                                                          */
10731             uint32_t            : 4;
10732     } PINCFG104_b;
10733   } ;
10734 
10735   union {
10736     __IOM uint32_t PINCFG105;                   /*!< (@ 0x000001A4) Controls the operation of virtual GPIO pin 105.            */
10737 
10738     struct {
10739       __IOM uint32_t FNCSEL105  : 4;            /*!< [3..0] Function select for GPIO pin 105                                   */
10740       __IOM uint32_t INPEN105   : 1;            /*!< [4..4] Input enable for GPIO 105                                          */
10741       __IOM uint32_t RDZERO105  : 1;            /*!< [5..5] Return 0 for read data on GPIO 105                                 */
10742       __IOM uint32_t IRPTEN105  : 2;            /*!< [7..6] Interrupt enable for GPIO 105                                      */
10743       __IOM uint32_t OUTCFG105  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 105                             */
10744             uint32_t            : 22;
10745     } PINCFG105_b;
10746   } ;
10747 
10748   union {
10749     __IOM uint32_t PINCFG106;                   /*!< (@ 0x000001A8) Controls the operation of virtual GPIO pin 106.            */
10750 
10751     struct {
10752       __IOM uint32_t FNCSEL106  : 4;            /*!< [3..0] Function select for GPIO pin 106                                   */
10753       __IOM uint32_t INPEN106   : 1;            /*!< [4..4] Input enable for GPIO 106                                          */
10754       __IOM uint32_t RDZERO106  : 1;            /*!< [5..5] Return 0 for read data on GPIO 106                                 */
10755       __IOM uint32_t IRPTEN106  : 2;            /*!< [7..6] Interrupt enable for GPIO 106                                      */
10756       __IOM uint32_t OUTCFG106  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 106                             */
10757             uint32_t            : 22;
10758     } PINCFG106_b;
10759   } ;
10760 
10761   union {
10762     __IOM uint32_t PINCFG107;                   /*!< (@ 0x000001AC) Controls the operation of virtual GPIO pin 107.            */
10763 
10764     struct {
10765       __IOM uint32_t FNCSEL107  : 4;            /*!< [3..0] Function select for GPIO pin 107                                   */
10766       __IOM uint32_t INPEN107   : 1;            /*!< [4..4] Input enable for GPIO 107                                          */
10767       __IOM uint32_t RDZERO107  : 1;            /*!< [5..5] Return 0 for read data on GPIO 107                                 */
10768       __IOM uint32_t IRPTEN107  : 2;            /*!< [7..6] Interrupt enable for GPIO 107                                      */
10769       __IOM uint32_t OUTCFG107  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 107                             */
10770             uint32_t            : 22;
10771     } PINCFG107_b;
10772   } ;
10773 
10774   union {
10775     __IOM uint32_t PINCFG108;                   /*!< (@ 0x000001B0) Controls the operation of virtual GPIO pin 108.            */
10776 
10777     struct {
10778       __IOM uint32_t FNCSEL108  : 4;            /*!< [3..0] Function select for GPIO pin 108                                   */
10779       __IOM uint32_t INPEN108   : 1;            /*!< [4..4] Input enable for GPIO 108                                          */
10780       __IOM uint32_t RDZERO108  : 1;            /*!< [5..5] Return 0 for read data on GPIO 108                                 */
10781       __IOM uint32_t IRPTEN108  : 2;            /*!< [7..6] Interrupt enable for GPIO 108                                      */
10782       __IOM uint32_t OUTCFG108  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 108                             */
10783             uint32_t            : 22;
10784     } PINCFG108_b;
10785   } ;
10786 
10787   union {
10788     __IOM uint32_t PINCFG109;                   /*!< (@ 0x000001B4) Controls the operation of virtual GPIO pin 109.            */
10789 
10790     struct {
10791       __IOM uint32_t FNCSEL109  : 4;            /*!< [3..0] Function select for GPIO pin 109                                   */
10792       __IOM uint32_t INPEN109   : 1;            /*!< [4..4] Input enable for GPIO 109                                          */
10793       __IOM uint32_t RDZERO109  : 1;            /*!< [5..5] Return 0 for read data on GPIO 109                                 */
10794       __IOM uint32_t IRPTEN109  : 2;            /*!< [7..6] Interrupt enable for GPIO 109                                      */
10795       __IOM uint32_t OUTCFG109  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 109                             */
10796             uint32_t            : 22;
10797     } PINCFG109_b;
10798   } ;
10799 
10800   union {
10801     __IOM uint32_t PINCFG110;                   /*!< (@ 0x000001B8) Controls the operation of virtual GPIO pin 110.            */
10802 
10803     struct {
10804       __IOM uint32_t FNCSEL110  : 4;            /*!< [3..0] Function select for GPIO pin 110                                   */
10805       __IOM uint32_t INPEN110   : 1;            /*!< [4..4] Input enable for GPIO 110                                          */
10806       __IOM uint32_t RDZERO110  : 1;            /*!< [5..5] Return 0 for read data on GPIO 110                                 */
10807       __IOM uint32_t IRPTEN110  : 2;            /*!< [7..6] Interrupt enable for GPIO 110                                      */
10808       __IOM uint32_t OUTCFG110  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 110                             */
10809             uint32_t            : 22;
10810     } PINCFG110_b;
10811   } ;
10812 
10813   union {
10814     __IOM uint32_t PINCFG111;                   /*!< (@ 0x000001BC) Controls the operation of virtual GPIO pin 111.            */
10815 
10816     struct {
10817       __IOM uint32_t FNCSEL111  : 4;            /*!< [3..0] Function select for GPIO pin 111                                   */
10818       __IOM uint32_t INPEN111   : 1;            /*!< [4..4] Input enable for GPIO 111                                          */
10819       __IOM uint32_t RDZERO111  : 1;            /*!< [5..5] Return 0 for read data on GPIO 111                                 */
10820       __IOM uint32_t IRPTEN111  : 2;            /*!< [7..6] Interrupt enable for GPIO 111                                      */
10821       __IOM uint32_t OUTCFG111  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 111                             */
10822             uint32_t            : 22;
10823     } PINCFG111_b;
10824   } ;
10825 
10826   union {
10827     __IOM uint32_t PINCFG112;                   /*!< (@ 0x000001C0) Controls the operation of virtual GPIO pin 112.            */
10828 
10829     struct {
10830       __IOM uint32_t FNCSEL112  : 4;            /*!< [3..0] Function select for GPIO pin 112                                   */
10831       __IOM uint32_t INPEN112   : 1;            /*!< [4..4] Input enable for GPIO 112                                          */
10832       __IOM uint32_t RDZERO112  : 1;            /*!< [5..5] Return 0 for read data on GPIO 112                                 */
10833       __IOM uint32_t IRPTEN112  : 2;            /*!< [7..6] Interrupt enable for GPIO 112                                      */
10834       __IOM uint32_t OUTCFG112  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 112                             */
10835             uint32_t            : 22;
10836     } PINCFG112_b;
10837   } ;
10838 
10839   union {
10840     __IOM uint32_t PINCFG113;                   /*!< (@ 0x000001C4) Controls the operation of virtual GPIO pin 113.            */
10841 
10842     struct {
10843       __IOM uint32_t FNCSEL113  : 4;            /*!< [3..0] Function select for GPIO pin 113                                   */
10844       __IOM uint32_t INPEN113   : 1;            /*!< [4..4] Input enable for GPIO 113                                          */
10845       __IOM uint32_t RDZERO113  : 1;            /*!< [5..5] Return 0 for read data on GPIO 113                                 */
10846       __IOM uint32_t IRPTEN113  : 2;            /*!< [7..6] Interrupt enable for GPIO 113                                      */
10847       __IOM uint32_t OUTCFG113  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 113                             */
10848             uint32_t            : 22;
10849     } PINCFG113_b;
10850   } ;
10851 
10852   union {
10853     __IOM uint32_t PINCFG114;                   /*!< (@ 0x000001C8) Controls the operation of virtual GPIO pin 114.            */
10854 
10855     struct {
10856       __IOM uint32_t FNCSEL114  : 4;            /*!< [3..0] Function select for GPIO pin 114                                   */
10857       __IOM uint32_t INPEN114   : 1;            /*!< [4..4] Input enable for GPIO 114                                          */
10858       __IOM uint32_t RDZERO114  : 1;            /*!< [5..5] Return 0 for read data on GPIO 114                                 */
10859       __IOM uint32_t IRPTEN114  : 2;            /*!< [7..6] Interrupt enable for GPIO 114                                      */
10860       __IOM uint32_t OUTCFG114  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 114                             */
10861             uint32_t            : 22;
10862     } PINCFG114_b;
10863   } ;
10864 
10865   union {
10866     __IOM uint32_t PINCFG115;                   /*!< (@ 0x000001CC) Controls the operation of virtual GPIO pin 115.            */
10867 
10868     struct {
10869       __IOM uint32_t FNCSEL115  : 4;            /*!< [3..0] Function select for GPIO pin 115                                   */
10870       __IOM uint32_t INPEN115   : 1;            /*!< [4..4] Input enable for GPIO 115                                          */
10871       __IOM uint32_t RDZERO115  : 1;            /*!< [5..5] Return 0 for read data on GPIO 115                                 */
10872       __IOM uint32_t IRPTEN115  : 2;            /*!< [7..6] Interrupt enable for GPIO 115                                      */
10873       __IOM uint32_t OUTCFG115  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 115                             */
10874             uint32_t            : 22;
10875     } PINCFG115_b;
10876   } ;
10877 
10878   union {
10879     __IOM uint32_t PINCFG116;                   /*!< (@ 0x000001D0) Controls the operation of virtual GPIO pin 116.            */
10880 
10881     struct {
10882       __IOM uint32_t FNCSEL116  : 4;            /*!< [3..0] Function select for GPIO pin 116                                   */
10883       __IOM uint32_t INPEN116   : 1;            /*!< [4..4] Input enable for GPIO 116                                          */
10884       __IOM uint32_t RDZERO116  : 1;            /*!< [5..5] Return 0 for read data on GPIO 116                                 */
10885       __IOM uint32_t IRPTEN116  : 2;            /*!< [7..6] Interrupt enable for GPIO 116                                      */
10886       __IOM uint32_t OUTCFG116  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 116                             */
10887             uint32_t            : 22;
10888     } PINCFG116_b;
10889   } ;
10890 
10891   union {
10892     __IOM uint32_t PINCFG117;                   /*!< (@ 0x000001D4) Controls the operation of virtual GPIO pin 117.            */
10893 
10894     struct {
10895       __IOM uint32_t FNCSEL117  : 4;            /*!< [3..0] Function select for GPIO pin 117                                   */
10896       __IOM uint32_t INPEN117   : 1;            /*!< [4..4] Input enable for GPIO 117                                          */
10897       __IOM uint32_t RDZERO117  : 1;            /*!< [5..5] Return 0 for read data on GPIO 117                                 */
10898       __IOM uint32_t IRPTEN117  : 2;            /*!< [7..6] Interrupt enable for GPIO 117                                      */
10899       __IOM uint32_t OUTCFG117  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 117                             */
10900             uint32_t            : 22;
10901     } PINCFG117_b;
10902   } ;
10903 
10904   union {
10905     __IOM uint32_t PINCFG118;                   /*!< (@ 0x000001D8) Controls the operation of virtual GPIO pin 118.            */
10906 
10907     struct {
10908       __IOM uint32_t FNCSEL118  : 4;            /*!< [3..0] Function select for GPIO pin 118                                   */
10909       __IOM uint32_t INPEN118   : 1;            /*!< [4..4] Input enable for GPIO 118                                          */
10910       __IOM uint32_t RDZERO118  : 1;            /*!< [5..5] Return 0 for read data on GPIO 118                                 */
10911       __IOM uint32_t IRPTEN118  : 2;            /*!< [7..6] Interrupt enable for GPIO 118                                      */
10912       __IOM uint32_t OUTCFG118  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 118                             */
10913             uint32_t            : 22;
10914     } PINCFG118_b;
10915   } ;
10916 
10917   union {
10918     __IOM uint32_t PINCFG119;                   /*!< (@ 0x000001DC) Controls the operation of virtual GPIO pin 119.            */
10919 
10920     struct {
10921       __IOM uint32_t FNCSEL119  : 4;            /*!< [3..0] Function select for GPIO pin 119                                   */
10922       __IOM uint32_t INPEN119   : 1;            /*!< [4..4] Input enable for GPIO 119                                          */
10923       __IOM uint32_t RDZERO119  : 1;            /*!< [5..5] Return 0 for read data on GPIO 119                                 */
10924       __IOM uint32_t IRPTEN119  : 2;            /*!< [7..6] Interrupt enable for GPIO 119                                      */
10925       __IOM uint32_t OUTCFG119  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 119                             */
10926             uint32_t            : 22;
10927     } PINCFG119_b;
10928   } ;
10929 
10930   union {
10931     __IOM uint32_t PINCFG120;                   /*!< (@ 0x000001E0) Controls the operation of virtual GPIO pin 120.            */
10932 
10933     struct {
10934       __IOM uint32_t FNCSEL120  : 4;            /*!< [3..0] Function select for GPIO pin 120                                   */
10935       __IOM uint32_t INPEN120   : 1;            /*!< [4..4] Input enable for GPIO 120                                          */
10936       __IOM uint32_t RDZERO120  : 1;            /*!< [5..5] Return 0 for read data on GPIO 120                                 */
10937       __IOM uint32_t IRPTEN120  : 2;            /*!< [7..6] Interrupt enable for GPIO 120                                      */
10938       __IOM uint32_t OUTCFG120  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 120                             */
10939             uint32_t            : 22;
10940     } PINCFG120_b;
10941   } ;
10942 
10943   union {
10944     __IOM uint32_t PINCFG121;                   /*!< (@ 0x000001E4) Controls the operation of virtual GPIO pin 121.            */
10945 
10946     struct {
10947       __IOM uint32_t FNCSEL121  : 4;            /*!< [3..0] Function select for GPIO pin 121                                   */
10948       __IOM uint32_t INPEN121   : 1;            /*!< [4..4] Input enable for GPIO 121                                          */
10949       __IOM uint32_t RDZERO121  : 1;            /*!< [5..5] Return 0 for read data on GPIO 121                                 */
10950       __IOM uint32_t IRPTEN121  : 2;            /*!< [7..6] Interrupt enable for GPIO 121                                      */
10951       __IOM uint32_t OUTCFG121  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 121                             */
10952             uint32_t            : 22;
10953     } PINCFG121_b;
10954   } ;
10955 
10956   union {
10957     __IOM uint32_t PINCFG122;                   /*!< (@ 0x000001E8) Controls the operation of virtual GPIO pin 122.            */
10958 
10959     struct {
10960       __IOM uint32_t FNCSEL122  : 4;            /*!< [3..0] Function select for GPIO pin 122                                   */
10961       __IOM uint32_t INPEN122   : 1;            /*!< [4..4] Input enable for GPIO 122                                          */
10962       __IOM uint32_t RDZERO122  : 1;            /*!< [5..5] Return 0 for read data on GPIO 122                                 */
10963       __IOM uint32_t IRPTEN122  : 2;            /*!< [7..6] Interrupt enable for GPIO 122                                      */
10964       __IOM uint32_t OUTCFG122  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 122                             */
10965             uint32_t            : 22;
10966     } PINCFG122_b;
10967   } ;
10968 
10969   union {
10970     __IOM uint32_t PINCFG123;                   /*!< (@ 0x000001EC) Controls the operation of virtual GPIO pin 123.            */
10971 
10972     struct {
10973       __IOM uint32_t FNCSEL123  : 4;            /*!< [3..0] Function select for GPIO pin 123                                   */
10974       __IOM uint32_t INPEN123   : 1;            /*!< [4..4] Input enable for GPIO 123                                          */
10975       __IOM uint32_t RDZERO123  : 1;            /*!< [5..5] Return 0 for read data on GPIO 123                                 */
10976       __IOM uint32_t IRPTEN123  : 2;            /*!< [7..6] Interrupt enable for GPIO 123                                      */
10977       __IOM uint32_t OUTCFG123  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 123                             */
10978             uint32_t            : 22;
10979     } PINCFG123_b;
10980   } ;
10981 
10982   union {
10983     __IOM uint32_t PINCFG124;                   /*!< (@ 0x000001F0) Controls the operation of virtual GPIO pin 124.            */
10984 
10985     struct {
10986       __IOM uint32_t FNCSEL124  : 4;            /*!< [3..0] Function select for GPIO pin 124                                   */
10987       __IOM uint32_t INPEN124   : 1;            /*!< [4..4] Input enable for GPIO 124                                          */
10988       __IOM uint32_t RDZERO124  : 1;            /*!< [5..5] Return 0 for read data on GPIO 124                                 */
10989       __IOM uint32_t IRPTEN124  : 2;            /*!< [7..6] Interrupt enable for GPIO 124                                      */
10990       __IOM uint32_t OUTCFG124  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 124                             */
10991             uint32_t            : 22;
10992     } PINCFG124_b;
10993   } ;
10994 
10995   union {
10996     __IOM uint32_t PINCFG125;                   /*!< (@ 0x000001F4) Controls the operation of virtual GPIO pin 125.            */
10997 
10998     struct {
10999       __IOM uint32_t FNCSEL125  : 4;            /*!< [3..0] Function select for GPIO pin 125                                   */
11000       __IOM uint32_t INPEN125   : 1;            /*!< [4..4] Input enable for GPIO 125                                          */
11001       __IOM uint32_t RDZERO125  : 1;            /*!< [5..5] Return 0 for read data on GPIO 125                                 */
11002       __IOM uint32_t IRPTEN125  : 2;            /*!< [7..6] Interrupt enable for GPIO 125                                      */
11003       __IOM uint32_t OUTCFG125  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 125                             */
11004             uint32_t            : 22;
11005     } PINCFG125_b;
11006   } ;
11007 
11008   union {
11009     __IOM uint32_t PINCFG126;                   /*!< (@ 0x000001F8) Controls the operation of virtual GPIO pin 126.            */
11010 
11011     struct {
11012       __IOM uint32_t FNCSEL126  : 4;            /*!< [3..0] Function select for GPIO pin 126                                   */
11013       __IOM uint32_t INPEN126   : 1;            /*!< [4..4] Input enable for GPIO 126                                          */
11014       __IOM uint32_t RDZERO126  : 1;            /*!< [5..5] Return 0 for read data on GPIO 126                                 */
11015       __IOM uint32_t IRPTEN126  : 2;            /*!< [7..6] Interrupt enable for GPIO 126                                      */
11016       __IOM uint32_t OUTCFG126  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 126                             */
11017             uint32_t            : 22;
11018     } PINCFG126_b;
11019   } ;
11020 
11021   union {
11022     __IOM uint32_t PINCFG127;                   /*!< (@ 0x000001FC) Controls the operation of virtual GPIO pin 127.            */
11023 
11024     struct {
11025       __IOM uint32_t FNCSEL127  : 4;            /*!< [3..0] Function select for GPIO pin 127                                   */
11026       __IOM uint32_t INPEN127   : 1;            /*!< [4..4] Input enable for GPIO 127                                          */
11027       __IOM uint32_t RDZERO127  : 1;            /*!< [5..5] Return 0 for read data on GPIO 127                                 */
11028       __IOM uint32_t IRPTEN127  : 2;            /*!< [7..6] Interrupt enable for GPIO 127                                      */
11029       __IOM uint32_t OUTCFG127  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 127                             */
11030             uint32_t            : 22;
11031     } PINCFG127_b;
11032   } ;
11033 
11034   union {
11035     __IOM uint32_t PADKEY;                      /*!< (@ 0x00000200) Lock state of the PINCFG and GPIO configuration
11036                                                                     registers. Write a value of 0x73 to unlock
11037                                                                     write access to the PAD and GPIO.                          */
11038 
11039     struct {
11040       __IOM uint32_t PADKEY     : 32;           /*!< [31..0] Key register value.                                               */
11041     } PADKEY_b;
11042   } ;
11043 
11044   union {
11045     __IOM uint32_t RD0;                         /*!< (@ 0x00000204) GPIO Input 0 (31-0)                                        */
11046 
11047     struct {
11048       __IOM uint32_t RD0        : 32;           /*!< [31..0] GPIO31-0 Reads pin state - read only. Returns the pad
11049                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
11050                                                      is active and RDZERO is inactive.                                         */
11051     } RD0_b;
11052   } ;
11053 
11054   union {
11055     __IOM uint32_t RD1;                         /*!< (@ 0x00000208) GPIO Input 1 (63-32)                                       */
11056 
11057     struct {
11058       __IOM uint32_t RD1        : 32;           /*!< [31..0] GPIO63-32 Reads pin state - read only. Returns the pad
11059                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
11060                                                      is active and RDZERO is inactive.                                         */
11061     } RD1_b;
11062   } ;
11063 
11064   union {
11065     __IOM uint32_t RD2;                         /*!< (@ 0x0000020C) GPIO Input 2 (95-64)                                       */
11066 
11067     struct {
11068       __IOM uint32_t RD2        : 32;           /*!< [31..0] GPIO95-64 Reads pin state - read only. Returns the pad
11069                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
11070                                                      is active and RDZERO is inactive.                                         */
11071     } RD2_b;
11072   } ;
11073 
11074   union {
11075     __IOM uint32_t RD3;                         /*!< (@ 0x00000210) GPIO Input 3 (127-96)                                      */
11076 
11077     struct {
11078       __IOM uint32_t RD3        : 32;           /*!< [31..0] GPIO127-96 Reads pin state - read only. Returns the
11079                                                      pad pin state for pins 0-31 if the PINCFG's input enable
11080                                                      (INPEN) is active and RDZERO is inactive.                                 */
11081     } RD3_b;
11082   } ;
11083 
11084   union {
11085     __IOM uint32_t WT0;                         /*!< (@ 0x00000214) GPIO Output 0 (31-0)                                       */
11086 
11087     struct {
11088       __IOM uint32_t WT0        : 32;           /*!< [31..0] GPIO31-0 Reads or writes pin state. Writes of 1 bits
11089                                                      set output pad signal if the GPIO is enabled for output.
11090                                                      Reads return status, including sets/clears through the
11091                                                      WTS and WTC registers.                                                    */
11092     } WT0_b;
11093   } ;
11094 
11095   union {
11096     __IOM uint32_t WT1;                         /*!< (@ 0x00000218) GPIO Output 1 (63-32)                                      */
11097 
11098     struct {
11099       __IOM uint32_t WT1        : 32;           /*!< [31..0] GPIO63-32 Reads or writes pin state. Writes of 1 bits
11100                                                      set output pad signal if the GPIO is enabled for output.
11101                                                      Reads return status, including sets/clears through the
11102                                                      WTS and WTC registers.                                                    */
11103     } WT1_b;
11104   } ;
11105 
11106   union {
11107     __IOM uint32_t WT2;                         /*!< (@ 0x0000021C) GPIO Output 2 (95-64)                                      */
11108 
11109     struct {
11110       __IOM uint32_t WT2        : 32;           /*!< [31..0] GPIO95-64 Reads or writes pin state. Writes of 1 bits
11111                                                      set output pad signal if the GPIO is enabled for output.
11112                                                      Reads return status, including sets/clears through the
11113                                                      WTS and WTC registers.                                                    */
11114     } WT2_b;
11115   } ;
11116 
11117   union {
11118     __IOM uint32_t WT3;                         /*!< (@ 0x00000220) GPIO Output 3 (127-96)                                     */
11119 
11120     struct {
11121       __IOM uint32_t WT3        : 32;           /*!< [31..0] GPIO127-96 Reads or writes pin state. Writes of 1 bits
11122                                                      set output pad signal if the GPIO is enabled for output.
11123                                                      Reads return status, including sets/clears through the
11124                                                      WTS and WTC registers.                                                    */
11125     } WT3_b;
11126   } ;
11127 
11128   union {
11129     __IOM uint32_t WTS0;                        /*!< (@ 0x00000224) GPIO Output Set 0 (31-0)                                   */
11130 
11131     struct {
11132       __IOM uint32_t WTS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin state. Writing a 1 to any bit sets
11133                                                      the corresponding bit in the WT register if the GPIO is
11134                                                      enabled for output. Writing a value of 0 has no effect
11135                                                      on the corresponding bit in the WT register. Status reads
11136                                                      should be made via the WT Register.                                       */
11137     } WTS0_b;
11138   } ;
11139 
11140   union {
11141     __IOM uint32_t WTS1;                        /*!< (@ 0x00000228) GPIO Output Set 1 (63-32)                                  */
11142 
11143     struct {
11144       __IOM uint32_t WTS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin state. Writing a 1 to any bit sets
11145                                                      the corresponding bit in the WT register if the GPIO is
11146                                                      enabled for output. Writing a value of 0 has no effect
11147                                                      on the corresponding bit in the WT register. Status reads
11148                                                      should be made via the WT Register.                                       */
11149     } WTS1_b;
11150   } ;
11151 
11152   union {
11153     __IOM uint32_t WTS2;                        /*!< (@ 0x0000022C) GPIO Output Set 2 (95-64)                                  */
11154 
11155     struct {
11156       __IOM uint32_t WTS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin state. Writing a 1 to any bit sets
11157                                                      the corresponding bit in the WT register if the GPIO is
11158                                                      enabled for output. Writing a value of 0 has no effect
11159                                                      on the corresponding bit in the WT register. Status reads
11160                                                      should be made via the WT Register.                                       */
11161     } WTS2_b;
11162   } ;
11163 
11164   union {
11165     __IOM uint32_t WTS3;                        /*!< (@ 0x00000230) GPIO Output Set 3 (127-96)                                 */
11166 
11167     struct {
11168       __IOM uint32_t WTS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin state. Writing a 1 to any bit sets
11169                                                      the corresponding bit in the WT register if the GPIO is
11170                                                      enabled for output. Writing a value of 0 has no effect
11171                                                      on the corresponding bit in the WT register. Status reads
11172                                                      should be made via the WT Register.                                       */
11173     } WTS3_b;
11174   } ;
11175 
11176   union {
11177     __IOM uint32_t WTC0;                        /*!< (@ 0x00000234) GPIO Output Clear 0 (31-0)                                 */
11178 
11179     struct {
11180       __IOM uint32_t WTC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin state. Writing a 1 to any bit clears
11181                                                      the corresponding bit in the WT register if the GPIO is
11182                                                      enabled for output. Writing a value of 0 has no effect
11183                                                      on the corresponding bit in the WT register. Status reads
11184                                                      should be made via the WT register.                                       */
11185     } WTC0_b;
11186   } ;
11187 
11188   union {
11189     __IOM uint32_t WTC1;                        /*!< (@ 0x00000238) GPIO Output Clear 1 (63-32)                                */
11190 
11191     struct {
11192       __IOM uint32_t WTC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin state. Writing a 1 to any bit clears
11193                                                      the corresponding bit in the WT register if the GPIO is
11194                                                      enabled for output. Writing a value of 0 has no effect
11195                                                      on the corresponding bit in the WT register. Status reads
11196                                                      should be made via the WT register.                                       */
11197     } WTC1_b;
11198   } ;
11199 
11200   union {
11201     __IOM uint32_t WTC2;                        /*!< (@ 0x0000023C) GPIO Output Clear 2 (95-64)                                */
11202 
11203     struct {
11204       __IOM uint32_t WTC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin state. Writing a 1 to any bit clears
11205                                                      the corresponding bit in the WT register if the GPIO is
11206                                                      enabled for output. Writing a value of 0 has no effect
11207                                                      on the corresponding bit in the WT register. Status reads
11208                                                      should be made via the WT register.                                       */
11209     } WTC2_b;
11210   } ;
11211 
11212   union {
11213     __IOM uint32_t WTC3;                        /*!< (@ 0x00000240) GPIO Output Clear 3 (127-96)                               */
11214 
11215     struct {
11216       __IOM uint32_t WTC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin state. Writing a 1 to any bit
11217                                                      clears the corresponding bit in the WT register if the
11218                                                      GPIO is enabled for output. Writing a value of 0 has no
11219                                                      effect on the corresponding bit in the WT register. Status
11220                                                      reads should be made via the WT register.                                 */
11221     } WTC3_b;
11222   } ;
11223 
11224   union {
11225     __IOM uint32_t EN0;                         /*!< (@ 0x00000244) GPIO Enable 0 (31-0)                                       */
11226 
11227     struct {
11228       __IOM uint32_t EN0        : 32;           /*!< [31..0] GPIO31-0 Enables tri-state pin output. Writing a 1 to
11229                                                      any bit enables, and writing a 0 to any bit disables, the
11230                                                      output for the corresponding GPIO. Reads return output
11231                                                      enable/disable status of GPIO.                                            */
11232     } EN0_b;
11233   } ;
11234 
11235   union {
11236     __IOM uint32_t EN1;                         /*!< (@ 0x00000248) GPIO Enable 1 (63-32)                                      */
11237 
11238     struct {
11239       __IOM uint32_t EN1        : 32;           /*!< [31..0] GPIO63-32 Enables tri-state pin output. Writing a 1
11240                                                      to any bit enables, and writing a 0 to any bit disables,
11241                                                      the output for the corresponding GPIO. Reads return output
11242                                                      enable/disable status of GPIO.                                            */
11243     } EN1_b;
11244   } ;
11245 
11246   union {
11247     __IOM uint32_t EN2;                         /*!< (@ 0x0000024C) GPIO Enable 2 (95-64)                                      */
11248 
11249     struct {
11250       __IOM uint32_t EN2        : 32;           /*!< [31..0] GPIO95-64 Enables tri-state pin output. Writing a 1
11251                                                      to any bit enables, and writing a 0 to any bit disables,
11252                                                      the output for the corresponding GPIO. Reads return output
11253                                                      enable/disable status of GPIO.                                            */
11254     } EN2_b;
11255   } ;
11256 
11257   union {
11258     __IOM uint32_t EN3;                         /*!< (@ 0x00000250) GPIO Enable 3 (127-96)                                     */
11259 
11260     struct {
11261       __IOM uint32_t EN3        : 32;           /*!< [31..0] GPIO127-96 Enables tri-state pin output. Writing a 1
11262                                                      to any bit enables, and writing a 0 to any bit disables,
11263                                                      the output for the corresponding GPIO. Reads return output
11264                                                      enable/disable status of GPIO.                                            */
11265     } EN3_b;
11266   } ;
11267 
11268   union {
11269     __IOM uint32_t ENS0;                        /*!< (@ 0x00000254) GPIO Enable Set 0 (31-0)                                   */
11270 
11271     struct {
11272       __IOM uint32_t ENS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin tri-state output enables. Writing
11273                                                      a 1 to any bit sets the corresponding bit in the EN register.
11274                                                      Writing a value of 0 has no effect on the corresponding
11275                                                      bit in the EN register. Status reads should be made to
11276                                                      the EN Register.                                                          */
11277     } ENS0_b;
11278   } ;
11279 
11280   union {
11281     __IOM uint32_t ENS1;                        /*!< (@ 0x00000258) GPIO Enable Set 1 (63-32)                                  */
11282 
11283     struct {
11284       __IOM uint32_t ENS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin tri-state output enables. Writing
11285                                                      a 1 to any bit sets the corresponding bit in the EN register.
11286                                                      Writing a value of 0 has no effect on the corresponding
11287                                                      bit in the EN register. Status reads should be made to
11288                                                      the EN Register.                                                          */
11289     } ENS1_b;
11290   } ;
11291 
11292   union {
11293     __IOM uint32_t ENS2;                        /*!< (@ 0x0000025C) GPIO Enable Set 2 (95-64)                                  */
11294 
11295     struct {
11296       __IOM uint32_t ENS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin tri-state output enables. Writing
11297                                                      a 1 to any bit sets the corresponding bit in the EN register.
11298                                                      Writing a value of 0 has no effect on the corresponding
11299                                                      bit in the EN register. Status reads should be made to
11300                                                      the EN Register.                                                          */
11301     } ENS2_b;
11302   } ;
11303 
11304   union {
11305     __IOM uint32_t ENS3;                        /*!< (@ 0x00000260) GPIO Enable Set 3 (127-96)                                 */
11306 
11307     struct {
11308       __IOM uint32_t ENS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin tri-state output enables. Writing
11309                                                      a 1 to any bit sets the corresponding bit in the EN register.
11310                                                      Writing a value of 0 has no effect on the corresponding
11311                                                      bit in the EN register. Status reads should be made to
11312                                                      the EN Register.                                                          */
11313     } ENS3_b;
11314   } ;
11315 
11316   union {
11317     __IOM uint32_t ENC0;                        /*!< (@ 0x00000264) GPIO Enable Clear 0 (31-0)                                 */
11318 
11319     struct {
11320       __IOM uint32_t ENC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin tri-state output enables. Writing
11321                                                      a 1 to any bit clears the corresponding bit in the EN register.
11322                                                      Writing a value of 0 has no effect on the corresponding
11323                                                      bit in the EN register. Status reads should be made to
11324                                                      the EN Register.                                                          */
11325     } ENC0_b;
11326   } ;
11327 
11328   union {
11329     __IOM uint32_t ENC1;                        /*!< (@ 0x00000268) GPIO Enable Clear 1 (63-32)                                */
11330 
11331     struct {
11332       __IOM uint32_t ENC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin tri-state output enables. Writing
11333                                                      a 1 to any bit clears the corresponding bit in the EN register.
11334                                                      Writing a value of 0 has no effect on the corresponding
11335                                                      bit in the EN register. Status reads should be made to
11336                                                      the EN Register.                                                          */
11337     } ENC1_b;
11338   } ;
11339 
11340   union {
11341     __IOM uint32_t ENC2;                        /*!< (@ 0x0000026C) GPIO Enable Clear 2 (95-64)                                */
11342 
11343     struct {
11344       __IOM uint32_t ENC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin tri-state output enables. Writing
11345                                                      a 1 to any bit clears the corresponding bit in the EN register.
11346                                                      Writing a value of 0 has no effect on the corresponding
11347                                                      bit in the EN register. Status reads should be made to
11348                                                      the EN Register.                                                          */
11349     } ENC2_b;
11350   } ;
11351 
11352   union {
11353     __IOM uint32_t ENC3;                        /*!< (@ 0x00000270) GPIO Enable Clear 3 (127-96)                               */
11354 
11355     struct {
11356       __IOM uint32_t ENC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin tri-state output enables. Writing
11357                                                      a 1 to any bit clears the corresponding bit in the EN register.
11358                                                      Writing a value of 0 has no effect on the corresponding
11359                                                      bit in the EN register. Status reads should be made to
11360                                                      the EN Register.                                                          */
11361     } ENC3_b;
11362   } ;
11363 
11364   union {
11365     __IOM uint32_t IOM0IRQ;                     /*!< (@ 0x00000274) IOM0 IRQ select for flow control.                          */
11366 
11367     struct {
11368       __IOM uint32_t IOM0IRQ    : 7;            /*!< [6..0] IOM0 IRQ pad select.                                               */
11369             uint32_t            : 25;
11370     } IOM0IRQ_b;
11371   } ;
11372 
11373   union {
11374     __IOM uint32_t IOM1IRQ;                     /*!< (@ 0x00000278) IOM1 IRQ select for flow control.                          */
11375 
11376     struct {
11377       __IOM uint32_t IOM1IRQ    : 7;            /*!< [6..0] IOM1 IRQ pad select.                                               */
11378             uint32_t            : 25;
11379     } IOM1IRQ_b;
11380   } ;
11381 
11382   union {
11383     __IOM uint32_t IOM2IRQ;                     /*!< (@ 0x0000027C) IOM2 IRQ select for flow control.                          */
11384 
11385     struct {
11386       __IOM uint32_t IOM2IRQ    : 7;            /*!< [6..0] IOM2 IRQ pad select.                                               */
11387             uint32_t            : 25;
11388     } IOM2IRQ_b;
11389   } ;
11390 
11391   union {
11392     __IOM uint32_t IOM3IRQ;                     /*!< (@ 0x00000280) IOM3 IRQ select for flow control.                          */
11393 
11394     struct {
11395       __IOM uint32_t IOM3IRQ    : 7;            /*!< [6..0] IOM3 IRQ pad select.                                               */
11396             uint32_t            : 25;
11397     } IOM3IRQ_b;
11398   } ;
11399 
11400   union {
11401     __IOM uint32_t IOM4IRQ;                     /*!< (@ 0x00000284) IOM4 IRQ select for flow control.                          */
11402 
11403     struct {
11404       __IOM uint32_t IOM4IRQ    : 7;            /*!< [6..0] IOM4 IRQ pad select.                                               */
11405             uint32_t            : 25;
11406     } IOM4IRQ_b;
11407   } ;
11408 
11409   union {
11410     __IOM uint32_t IOM5IRQ;                     /*!< (@ 0x00000288) IOM5 IRQ select for flow control.                          */
11411 
11412     struct {
11413       __IOM uint32_t IOM5IRQ    : 7;            /*!< [6..0] IOM5 IRQ pad select.                                               */
11414             uint32_t            : 25;
11415     } IOM5IRQ_b;
11416   } ;
11417 
11418   union {
11419     __IOM uint32_t IOM6IRQ;                     /*!< (@ 0x0000028C) IOM6 IRQ select for flow control.                          */
11420 
11421     struct {
11422       __IOM uint32_t IOM6IRQ    : 7;            /*!< [6..0] IOM6 IRQ pad select.                                               */
11423             uint32_t            : 25;
11424     } IOM6IRQ_b;
11425   } ;
11426 
11427   union {
11428     __IOM uint32_t IOM7IRQ;                     /*!< (@ 0x00000290) IOM7 IRQ select for flow control.                          */
11429 
11430     struct {
11431       __IOM uint32_t IOM7IRQ    : 7;            /*!< [6..0] IOM7 IRQ pad select.                                               */
11432             uint32_t            : 25;
11433     } IOM7IRQ_b;
11434   } ;
11435 
11436   union {
11437     __IOM uint32_t SDIFCDWP;                    /*!< (@ 0x00000294) SDIF CD and WP Select.                                     */
11438 
11439     struct {
11440       __IOM uint32_t SDIFCD     : 7;            /*!< [6..0] SDIF CD pad select.                                                */
11441             uint32_t            : 1;
11442       __IOM uint32_t SDIFWP     : 7;            /*!< [14..8] SDIF WP pad select.                                               */
11443             uint32_t            : 17;
11444     } SDIFCDWP_b;
11445   } ;
11446 
11447   union {
11448     __IOM uint32_t OBSDATA;                     /*!< (@ 0x00000298) GPIO Observation mode sample                               */
11449 
11450     struct {
11451       __IOM uint32_t OBSDATA    : 16;           /*!< [15..0] Sample of the data output on the GPIO observation port.
11452                                                      May have async sampling issues, as the data is not synronized
11453                                                      to the read operation. Intended for debug purposes only.                  */
11454             uint32_t            : 16;
11455     } OBSDATA_b;
11456   } ;
11457 
11458   union {
11459     __IOM uint32_t IEOBS0;                      /*!< (@ 0x0000029C) Read only. Reflects the value of the input enable
11460                                                                     signals for pads 31-0 sent to the pad.                     */
11461 
11462     struct {
11463       __IOM uint32_t IEDATA0    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11464                                                      the pad will be trasmitted to the internal logic within
11465                                                      the device.                                                               */
11466     } IEOBS0_b;
11467   } ;
11468 
11469   union {
11470     __IOM uint32_t IEOBS1;                      /*!< (@ 0x000002A0) Read only. Reflects the value of the input enable
11471                                                                     signals for pads 63-32 sent to the pad.                    */
11472 
11473     struct {
11474       __IOM uint32_t IEDATA1    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11475                                                      the pad will be trasmitted to the internal logic within
11476                                                      the device.                                                               */
11477     } IEOBS1_b;
11478   } ;
11479 
11480   union {
11481     __IOM uint32_t IEOBS2;                      /*!< (@ 0x000002A4) Read only. Reflects the value of the input enable
11482                                                                     signals for pads 95-64 sent to the pad.                    */
11483 
11484     struct {
11485       __IOM uint32_t IEDATA2    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11486                                                      the pad will be trasmitted to the internal logic within
11487                                                      the device.                                                               */
11488     } IEOBS2_b;
11489   } ;
11490 
11491   union {
11492     __IOM uint32_t IEOBS3;                      /*!< (@ 0x000002A8) Read only. Reflects the value of the input enable
11493                                                                     signals for pads 127-96 sent to the pad.                   */
11494 
11495     struct {
11496       __IOM uint32_t IEDATA3    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11497                                                      the pad will be trasmitted to the internal logic within
11498                                                      the device.                                                               */
11499     } IEOBS3_b;
11500   } ;
11501 
11502   union {
11503     __IOM uint32_t OEOBS0;                      /*!< (@ 0x000002AC) Read only. Reflects the value of the output enable
11504                                                                     signals for pads 31-0 sent to the pad.                     */
11505 
11506     struct {
11507       __IOM uint32_t OEDATA0    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11508                                                      the output_en_ is active and the MCU will be driving the
11509                                                      pad.                                                                      */
11510     } OEOBS0_b;
11511   } ;
11512 
11513   union {
11514     __IOM uint32_t OEOBS1;                      /*!< (@ 0x000002B0) Read only. Reflects the value of the output enable
11515                                                                     signals for pads 63-32 sent to the pad.                    */
11516 
11517     struct {
11518       __IOM uint32_t OEDATA1    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11519                                                      the output_en_ is active and the MCU will be driving the
11520                                                      pad.                                                                      */
11521     } OEOBS1_b;
11522   } ;
11523 
11524   union {
11525     __IOM uint32_t OEOBS2;                      /*!< (@ 0x000002B4) Read only. Reflects the value of the output enable
11526                                                                     signals for pads 95-64 sent to the pad.                    */
11527 
11528     struct {
11529       __IOM uint32_t OEDATA2    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11530                                                      the output_en_ is active and the MCU will be driving the
11531                                                      pad.                                                                      */
11532     } OEOBS2_b;
11533   } ;
11534 
11535   union {
11536     __IOM uint32_t OEOBS3;                      /*!< (@ 0x000002B8) Read only. Reflects the value of the output enable
11537                                                                     signals for pads 127-96 sent to the pad.                   */
11538 
11539     struct {
11540       __IOM uint32_t OEDATA3    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11541                                                      the output_en_ is active and the MCU will be driving the
11542                                                      pad.                                                                      */
11543     } OEOBS3_b;
11544   } ;
11545   __IM  uint32_t  RESERVED;
11546 
11547   union {
11548     __IOM uint32_t MCUN0INT0EN;                 /*!< (@ 0x000002C0) Set bits in this register to allow this module
11549                                                                     to generate the corresponding interrupt.                   */
11550 
11551     struct {
11552       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11553       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11554       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11555       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11556       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11557       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11558       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11559       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11560       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11561       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11562       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11563       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11564       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11565       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11566       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11567       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11568       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11569       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11570       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11571       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11572       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11573       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11574       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11575       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11576       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11577       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11578       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11579       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11580       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11581       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11582       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11583       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11584     } MCUN0INT0EN_b;
11585   } ;
11586 
11587   union {
11588     __IOM uint32_t MCUN0INT0STAT;               /*!< (@ 0x000002C4) Read bits from this register to discover the
11589                                                                     cause of a recent interrupt.                               */
11590 
11591     struct {
11592       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11593       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11594       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11595       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11596       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11597       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11598       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11599       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11600       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11601       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11602       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11603       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11604       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11605       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11606       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11607       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11608       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11609       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11610       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11611       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11612       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11613       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11614       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11615       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11616       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11617       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11618       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11619       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11620       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11621       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11622       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11623       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11624     } MCUN0INT0STAT_b;
11625   } ;
11626 
11627   union {
11628     __IOM uint32_t MCUN0INT0CLR;                /*!< (@ 0x000002C8) Write a 1 to a bit in this register to clear
11629                                                                     the interrupt status associated with that
11630                                                                     bit.                                                       */
11631 
11632     struct {
11633       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11634       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11635       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11636       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11637       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11638       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11639       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11640       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11641       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11642       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11643       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11644       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11645       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11646       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11647       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11648       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11649       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11650       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11651       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11652       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11653       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11654       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11655       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11656       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11657       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11658       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11659       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11660       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11661       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11662       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11663       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11664       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11665     } MCUN0INT0CLR_b;
11666   } ;
11667 
11668   union {
11669     __IOM uint32_t MCUN0INT0SET;                /*!< (@ 0x000002CC) Write a 1 to a bit in this register to instantly
11670                                                                     generate an interrupt from this module.
11671                                                                     (Generally used for testing purposes).                     */
11672 
11673     struct {
11674       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11675       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11676       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11677       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11678       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11679       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11680       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11681       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11682       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11683       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11684       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11685       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11686       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11687       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11688       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11689       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11690       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11691       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11692       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11693       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11694       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11695       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11696       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11697       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11698       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11699       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11700       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11701       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11702       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11703       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11704       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11705       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11706     } MCUN0INT0SET_b;
11707   } ;
11708 
11709   union {
11710     __IOM uint32_t MCUN0INT1EN;                 /*!< (@ 0x000002D0) Set bits in this register to allow this module
11711                                                                     to generate the corresponding interrupt.                   */
11712 
11713     struct {
11714       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11715       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11716       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11717       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11718       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11719       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11720       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11721       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11722       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11723       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11724       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11725       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11726       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11727       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11728       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11729       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11730       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11731       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11732       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11733       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11734       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11735       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11736       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11737       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11738       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11739       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11740       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11741       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11742       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11743       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11744       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11745       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11746     } MCUN0INT1EN_b;
11747   } ;
11748 
11749   union {
11750     __IOM uint32_t MCUN0INT1STAT;               /*!< (@ 0x000002D4) Read bits from this register to discover the
11751                                                                     cause of a recent interrupt.                               */
11752 
11753     struct {
11754       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11755       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11756       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11757       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11758       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11759       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11760       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11761       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11762       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11763       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11764       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11765       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11766       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11767       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11768       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11769       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11770       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11771       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11772       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11773       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11774       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11775       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11776       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11777       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11778       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11779       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11780       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11781       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11782       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11783       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11784       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11785       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11786     } MCUN0INT1STAT_b;
11787   } ;
11788 
11789   union {
11790     __IOM uint32_t MCUN0INT1CLR;                /*!< (@ 0x000002D8) Write a 1 to a bit in this register to clear
11791                                                                     the interrupt status associated with that
11792                                                                     bit.                                                       */
11793 
11794     struct {
11795       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11796       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11797       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11798       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11799       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11800       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11801       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11802       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11803       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11804       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11805       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11806       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11807       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11808       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11809       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11810       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11811       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11812       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11813       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11814       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11815       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11816       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11817       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11818       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11819       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11820       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11821       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11822       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11823       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11824       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11825       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11826       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11827     } MCUN0INT1CLR_b;
11828   } ;
11829 
11830   union {
11831     __IOM uint32_t MCUN0INT1SET;                /*!< (@ 0x000002DC) Write a 1 to a bit in this register to instantly
11832                                                                     generate an interrupt from this module.
11833                                                                     (Generally used for testing purposes).                     */
11834 
11835     struct {
11836       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11837       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11838       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11839       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11840       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11841       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11842       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11843       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11844       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11845       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11846       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11847       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11848       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11849       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11850       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11851       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11852       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11853       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11854       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11855       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11856       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11857       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11858       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11859       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11860       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11861       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11862       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11863       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11864       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11865       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11866       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11867       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11868     } MCUN0INT1SET_b;
11869   } ;
11870 
11871   union {
11872     __IOM uint32_t MCUN0INT2EN;                 /*!< (@ 0x000002E0) Set bits in this register to allow this module
11873                                                                     to generate the corresponding interrupt.                   */
11874 
11875     struct {
11876       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
11877       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
11878       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
11879       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
11880       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
11881       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
11882       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
11883       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
11884       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
11885       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
11886       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
11887       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
11888       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
11889       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
11890       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
11891       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
11892       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
11893       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
11894       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
11895       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
11896       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
11897       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
11898       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
11899       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
11900       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
11901       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
11902       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
11903       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
11904       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
11905       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
11906       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
11907       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
11908     } MCUN0INT2EN_b;
11909   } ;
11910 
11911   union {
11912     __IOM uint32_t MCUN0INT2STAT;               /*!< (@ 0x000002E4) Read bits from this register to discover the
11913                                                                     cause of a recent interrupt.                               */
11914 
11915     struct {
11916       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
11917       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
11918       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
11919       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
11920       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
11921       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
11922       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
11923       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
11924       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
11925       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
11926       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
11927       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
11928       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
11929       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
11930       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
11931       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
11932       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
11933       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
11934       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
11935       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
11936       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
11937       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
11938       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
11939       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
11940       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
11941       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
11942       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
11943       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
11944       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
11945       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
11946       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
11947       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
11948     } MCUN0INT2STAT_b;
11949   } ;
11950 
11951   union {
11952     __IOM uint32_t MCUN0INT2CLR;                /*!< (@ 0x000002E8) Write a 1 to a bit in this register to clear
11953                                                                     the interrupt status associated with that
11954                                                                     bit.                                                       */
11955 
11956     struct {
11957       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
11958       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
11959       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
11960       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
11961       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
11962       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
11963       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
11964       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
11965       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
11966       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
11967       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
11968       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
11969       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
11970       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
11971       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
11972       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
11973       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
11974       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
11975       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
11976       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
11977       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
11978       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
11979       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
11980       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
11981       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
11982       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
11983       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
11984       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
11985       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
11986       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
11987       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
11988       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
11989     } MCUN0INT2CLR_b;
11990   } ;
11991 
11992   union {
11993     __IOM uint32_t MCUN0INT2SET;                /*!< (@ 0x000002EC) Write a 1 to a bit in this register to instantly
11994                                                                     generate an interrupt from this module.
11995                                                                     (Generally used for testing purposes).                     */
11996 
11997     struct {
11998       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
11999       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
12000       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
12001       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
12002       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
12003       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
12004       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
12005       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
12006       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
12007       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
12008       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
12009       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
12010       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
12011       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
12012       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
12013       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
12014       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
12015       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
12016       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
12017       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
12018       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
12019       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
12020       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
12021       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
12022       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
12023       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
12024       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
12025       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
12026       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
12027       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
12028       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
12029       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
12030     } MCUN0INT2SET_b;
12031   } ;
12032 
12033   union {
12034     __IOM uint32_t MCUN0INT3EN;                 /*!< (@ 0x000002F0) Set bits in this register to allow this module
12035                                                                     to generate the corresponding interrupt.                   */
12036 
12037     struct {
12038       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12039       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12040       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12041       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12042       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12043       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12044       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12045       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12046       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12047       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12048       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12049       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12050       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12051       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12052       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12053       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12054       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12055       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12056       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12057       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12058       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12059       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12060       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12061       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12062       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12063       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12064       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12065       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12066       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12067       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12068       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12069       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12070     } MCUN0INT3EN_b;
12071   } ;
12072 
12073   union {
12074     __IOM uint32_t MCUN0INT3STAT;               /*!< (@ 0x000002F4) Read bits from this register to discover the
12075                                                                     cause of a recent interrupt.                               */
12076 
12077     struct {
12078       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12079       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12080       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12081       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12082       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12083       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12084       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12085       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12086       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12087       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12088       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12089       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12090       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12091       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12092       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12093       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12094       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12095       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12096       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12097       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12098       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12099       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12100       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12101       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12102       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12103       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12104       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12105       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12106       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12107       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12108       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12109       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12110     } MCUN0INT3STAT_b;
12111   } ;
12112 
12113   union {
12114     __IOM uint32_t MCUN0INT3CLR;                /*!< (@ 0x000002F8) Write a 1 to a bit in this register to clear
12115                                                                     the interrupt status associated with that
12116                                                                     bit.                                                       */
12117 
12118     struct {
12119       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12120       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12121       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12122       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12123       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12124       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12125       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12126       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12127       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12128       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12129       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12130       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12131       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12132       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12133       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12134       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12135       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12136       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12137       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12138       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12139       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12140       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12141       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12142       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12143       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12144       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12145       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12146       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12147       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12148       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12149       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12150       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12151     } MCUN0INT3CLR_b;
12152   } ;
12153 
12154   union {
12155     __IOM uint32_t MCUN0INT3SET;                /*!< (@ 0x000002FC) Write a 1 to a bit in this register to instantly
12156                                                                     generate an interrupt from this module.
12157                                                                     (Generally used for testing purposes).                     */
12158 
12159     struct {
12160       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12161       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12162       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12163       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12164       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12165       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12166       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12167       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12168       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12169       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12170       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12171       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12172       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12173       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12174       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12175       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12176       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12177       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12178       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12179       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12180       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12181       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12182       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12183       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12184       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12185       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12186       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12187       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12188       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12189       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12190       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12191       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12192     } MCUN0INT3SET_b;
12193   } ;
12194 
12195   union {
12196     __IOM uint32_t MCUN1INT0EN;                 /*!< (@ 0x00000300) Set bits in this register to allow this module
12197                                                                     to generate the corresponding interrupt.                   */
12198 
12199     struct {
12200       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12201       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12202       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12203       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12204       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12205       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12206       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12207       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12208       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12209       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12210       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12211       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12212       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12213       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12214       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12215       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12216       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12217       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12218       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12219       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12220       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12221       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12222       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12223       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12224       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12225       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12226       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12227       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12228       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12229       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12230       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12231       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12232     } MCUN1INT0EN_b;
12233   } ;
12234 
12235   union {
12236     __IOM uint32_t MCUN1INT0STAT;               /*!< (@ 0x00000304) Read bits from this register to discover the
12237                                                                     cause of a recent interrupt.                               */
12238 
12239     struct {
12240       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12241       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12242       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12243       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12244       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12245       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12246       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12247       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12248       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12249       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12250       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12251       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12252       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12253       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12254       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12255       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12256       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12257       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12258       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12259       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12260       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12261       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12262       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12263       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12264       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12265       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12266       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12267       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12268       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12269       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12270       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12271       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12272     } MCUN1INT0STAT_b;
12273   } ;
12274 
12275   union {
12276     __IOM uint32_t MCUN1INT0CLR;                /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
12277                                                                     the interrupt status associated with that
12278                                                                     bit.                                                       */
12279 
12280     struct {
12281       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12282       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12283       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12284       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12285       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12286       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12287       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12288       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12289       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12290       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12291       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12292       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12293       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12294       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12295       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12296       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12297       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12298       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12299       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12300       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12301       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12302       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12303       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12304       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12305       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12306       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12307       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12308       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12309       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12310       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12311       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12312       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12313     } MCUN1INT0CLR_b;
12314   } ;
12315 
12316   union {
12317     __IOM uint32_t MCUN1INT0SET;                /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
12318                                                                     generate an interrupt from this module.
12319                                                                     (Generally used for testing purposes).                     */
12320 
12321     struct {
12322       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12323       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12324       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12325       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12326       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12327       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12328       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12329       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12330       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12331       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12332       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12333       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12334       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12335       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12336       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12337       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12338       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12339       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12340       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12341       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12342       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12343       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12344       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12345       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12346       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12347       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12348       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12349       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12350       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12351       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12352       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12353       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12354     } MCUN1INT0SET_b;
12355   } ;
12356 
12357   union {
12358     __IOM uint32_t MCUN1INT1EN;                 /*!< (@ 0x00000310) Set bits in this register to allow this module
12359                                                                     to generate the corresponding interrupt.                   */
12360 
12361     struct {
12362       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12363       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12364       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12365       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12366       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12367       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12368       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12369       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12370       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12371       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12372       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12373       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12374       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12375       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12376       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12377       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12378       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12379       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12380       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12381       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12382       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12383       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12384       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12385       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12386       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12387       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12388       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12389       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12390       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12391       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12392       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12393       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12394     } MCUN1INT1EN_b;
12395   } ;
12396 
12397   union {
12398     __IOM uint32_t MCUN1INT1STAT;               /*!< (@ 0x00000314) Read bits from this register to discover the
12399                                                                     cause of a recent interrupt.                               */
12400 
12401     struct {
12402       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12403       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12404       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12405       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12406       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12407       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12408       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12409       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12410       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12411       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12412       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12413       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12414       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12415       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12416       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12417       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12418       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12419       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12420       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12421       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12422       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12423       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12424       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12425       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12426       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12427       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12428       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12429       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12430       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12431       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12432       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12433       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12434     } MCUN1INT1STAT_b;
12435   } ;
12436 
12437   union {
12438     __IOM uint32_t MCUN1INT1CLR;                /*!< (@ 0x00000318) Write a 1 to a bit in this register to clear
12439                                                                     the interrupt status associated with that
12440                                                                     bit.                                                       */
12441 
12442     struct {
12443       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12444       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12445       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12446       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12447       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12448       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12449       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12450       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12451       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12452       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12453       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12454       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12455       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12456       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12457       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12458       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12459       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12460       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12461       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12462       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12463       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12464       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12465       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12466       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12467       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12468       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12469       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12470       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12471       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12472       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12473       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12474       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12475     } MCUN1INT1CLR_b;
12476   } ;
12477 
12478   union {
12479     __IOM uint32_t MCUN1INT1SET;                /*!< (@ 0x0000031C) Write a 1 to a bit in this register to instantly
12480                                                                     generate an interrupt from this module.
12481                                                                     (Generally used for testing purposes).                     */
12482 
12483     struct {
12484       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12485       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12486       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12487       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12488       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12489       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12490       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12491       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12492       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12493       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12494       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12495       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12496       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12497       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12498       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12499       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12500       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12501       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12502       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12503       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12504       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12505       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12506       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12507       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12508       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12509       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12510       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12511       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12512       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12513       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12514       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12515       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12516     } MCUN1INT1SET_b;
12517   } ;
12518 
12519   union {
12520     __IOM uint32_t MCUN1INT2EN;                 /*!< (@ 0x00000320) Set bits in this register to allow this module
12521                                                                     to generate the corresponding interrupt.                   */
12522 
12523     struct {
12524       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12525       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12526       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12527       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12528       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12529       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12530       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12531       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12532       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12533       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12534       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12535       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12536       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12537       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12538       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12539       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12540       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12541       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12542       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12543       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12544       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12545       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12546       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12547       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12548       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12549       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12550       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12551       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12552       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12553       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12554       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12555       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12556     } MCUN1INT2EN_b;
12557   } ;
12558 
12559   union {
12560     __IOM uint32_t MCUN1INT2STAT;               /*!< (@ 0x00000324) Read bits from this register to discover the
12561                                                                     cause of a recent interrupt.                               */
12562 
12563     struct {
12564       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12565       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12566       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12567       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12568       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12569       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12570       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12571       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12572       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12573       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12574       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12575       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12576       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12577       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12578       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12579       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12580       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12581       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12582       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12583       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12584       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12585       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12586       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12587       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12588       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12589       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12590       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12591       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12592       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12593       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12594       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12595       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12596     } MCUN1INT2STAT_b;
12597   } ;
12598 
12599   union {
12600     __IOM uint32_t MCUN1INT2CLR;                /*!< (@ 0x00000328) Write a 1 to a bit in this register to clear
12601                                                                     the interrupt status associated with that
12602                                                                     bit.                                                       */
12603 
12604     struct {
12605       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12606       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12607       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12608       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12609       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12610       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12611       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12612       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12613       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12614       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12615       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12616       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12617       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12618       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12619       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12620       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12621       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12622       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12623       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12624       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12625       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12626       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12627       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12628       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12629       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12630       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12631       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12632       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12633       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12634       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12635       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12636       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12637     } MCUN1INT2CLR_b;
12638   } ;
12639 
12640   union {
12641     __IOM uint32_t MCUN1INT2SET;                /*!< (@ 0x0000032C) Write a 1 to a bit in this register to instantly
12642                                                                     generate an interrupt from this module.
12643                                                                     (Generally used for testing purposes).                     */
12644 
12645     struct {
12646       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12647       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12648       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12649       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12650       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12651       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12652       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12653       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12654       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12655       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12656       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12657       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12658       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12659       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12660       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12661       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12662       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12663       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12664       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12665       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12666       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12667       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12668       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12669       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12670       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12671       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12672       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12673       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12674       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12675       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12676       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12677       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12678     } MCUN1INT2SET_b;
12679   } ;
12680 
12681   union {
12682     __IOM uint32_t MCUN1INT3EN;                 /*!< (@ 0x00000330) Set bits in this register to allow this module
12683                                                                     to generate the corresponding interrupt.                   */
12684 
12685     struct {
12686       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12687       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12688       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12689       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12690       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12691       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12692       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12693       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12694       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12695       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12696       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12697       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12698       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12699       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12700       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12701       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12702       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12703       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12704       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12705       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12706       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12707       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12708       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12709       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12710       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12711       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12712       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12713       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12714       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12715       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12716       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12717       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12718     } MCUN1INT3EN_b;
12719   } ;
12720 
12721   union {
12722     __IOM uint32_t MCUN1INT3STAT;               /*!< (@ 0x00000334) Read bits from this register to discover the
12723                                                                     cause of a recent interrupt.                               */
12724 
12725     struct {
12726       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12727       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12728       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12729       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12730       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12731       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12732       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12733       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12734       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12735       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12736       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12737       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12738       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12739       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12740       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12741       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12742       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12743       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12744       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12745       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12746       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12747       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12748       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12749       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12750       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12751       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12752       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12753       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12754       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12755       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12756       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12757       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12758     } MCUN1INT3STAT_b;
12759   } ;
12760 
12761   union {
12762     __IOM uint32_t MCUN1INT3CLR;                /*!< (@ 0x00000338) Write a 1 to a bit in this register to clear
12763                                                                     the interrupt status associated with that
12764                                                                     bit.                                                       */
12765 
12766     struct {
12767       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12768       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12769       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12770       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12771       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12772       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12773       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12774       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12775       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12776       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12777       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12778       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12779       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12780       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12781       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12782       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12783       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12784       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12785       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12786       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12787       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12788       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12789       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12790       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12791       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12792       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12793       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12794       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12795       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12796       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12797       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12798       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12799     } MCUN1INT3CLR_b;
12800   } ;
12801 
12802   union {
12803     __IOM uint32_t MCUN1INT3SET;                /*!< (@ 0x0000033C) Write a 1 to a bit in this register to instantly
12804                                                                     generate an interrupt from this module.
12805                                                                     (Generally used for testing purposes).                     */
12806 
12807     struct {
12808       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12809       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12810       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12811       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12812       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12813       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12814       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12815       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12816       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12817       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12818       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12819       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12820       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12821       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12822       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12823       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12824       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12825       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12826       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12827       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12828       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12829       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12830       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12831       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12832       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12833       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12834       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12835       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12836       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12837       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12838       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12839       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12840     } MCUN1INT3SET_b;
12841   } ;
12842 
12843   union {
12844     __IOM uint32_t DSP0N0INT0EN;                /*!< (@ 0x00000340) Set bits in this register to allow this module
12845                                                                     to generate the corresponding interrupt.                   */
12846 
12847     struct {
12848       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
12849       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
12850       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
12851       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
12852       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
12853       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
12854       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
12855       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
12856       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
12857       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
12858       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
12859       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
12860       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
12861       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
12862       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
12863       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
12864       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
12865       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
12866       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
12867       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
12868       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
12869       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
12870       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
12871       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
12872       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
12873       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
12874       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
12875       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
12876       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
12877       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
12878       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
12879       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
12880     } DSP0N0INT0EN_b;
12881   } ;
12882 
12883   union {
12884     __IOM uint32_t DSP0N0INT0STAT;              /*!< (@ 0x00000344) Read bits from this register to discover the
12885                                                                     cause of a recent interrupt.                               */
12886 
12887     struct {
12888       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
12889       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
12890       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
12891       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
12892       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
12893       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
12894       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
12895       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
12896       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
12897       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
12898       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
12899       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
12900       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
12901       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
12902       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
12903       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
12904       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
12905       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
12906       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
12907       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
12908       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
12909       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
12910       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
12911       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
12912       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
12913       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
12914       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
12915       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
12916       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
12917       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
12918       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
12919       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
12920     } DSP0N0INT0STAT_b;
12921   } ;
12922 
12923   union {
12924     __IOM uint32_t DSP0N0INT0CLR;               /*!< (@ 0x00000348) Write a 1 to a bit in this register to clear
12925                                                                     the interrupt status associated with that
12926                                                                     bit.                                                       */
12927 
12928     struct {
12929       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
12930       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
12931       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
12932       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
12933       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
12934       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
12935       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
12936       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
12937       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
12938       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
12939       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
12940       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
12941       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
12942       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
12943       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
12944       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
12945       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
12946       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
12947       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
12948       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
12949       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
12950       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
12951       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
12952       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
12953       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
12954       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
12955       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
12956       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
12957       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
12958       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
12959       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
12960       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
12961     } DSP0N0INT0CLR_b;
12962   } ;
12963 
12964   union {
12965     __IOM uint32_t DSP0N0INT0SET;               /*!< (@ 0x0000034C) Write a 1 to a bit in this register to instantly
12966                                                                     generate an interrupt from this module.
12967                                                                     (Generally used for testing purposes).                     */
12968 
12969     struct {
12970       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
12971       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
12972       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
12973       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
12974       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
12975       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
12976       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
12977       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
12978       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
12979       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
12980       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
12981       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
12982       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
12983       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
12984       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
12985       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
12986       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
12987       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
12988       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
12989       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
12990       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
12991       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
12992       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
12993       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
12994       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
12995       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
12996       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
12997       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
12998       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
12999       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
13000       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
13001       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
13002     } DSP0N0INT0SET_b;
13003   } ;
13004 
13005   union {
13006     __IOM uint32_t DSP0N0INT1EN;                /*!< (@ 0x00000350) Set bits in this register to allow this module
13007                                                                     to generate the corresponding interrupt.                   */
13008 
13009     struct {
13010       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13011       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13012       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13013       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13014       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13015       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13016       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13017       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13018       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13019       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13020       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13021       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13022       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13023       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13024       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13025       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13026       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13027       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13028       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13029       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13030       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13031       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13032       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13033       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13034       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13035       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13036       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13037       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13038       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13039       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13040       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13041       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13042     } DSP0N0INT1EN_b;
13043   } ;
13044 
13045   union {
13046     __IOM uint32_t DSP0N0INT1STAT;              /*!< (@ 0x00000354) Read bits from this register to discover the
13047                                                                     cause of a recent interrupt.                               */
13048 
13049     struct {
13050       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13051       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13052       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13053       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13054       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13055       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13056       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13057       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13058       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13059       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13060       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13061       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13062       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13063       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13064       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13065       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13066       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13067       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13068       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13069       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13070       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13071       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13072       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13073       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13074       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13075       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13076       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13077       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13078       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13079       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13080       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13081       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13082     } DSP0N0INT1STAT_b;
13083   } ;
13084 
13085   union {
13086     __IOM uint32_t DSP0N0INT1CLR;               /*!< (@ 0x00000358) Write a 1 to a bit in this register to clear
13087                                                                     the interrupt status associated with that
13088                                                                     bit.                                                       */
13089 
13090     struct {
13091       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13092       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13093       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13094       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13095       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13096       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13097       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13098       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13099       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13100       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13101       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13102       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13103       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13104       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13105       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13106       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13107       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13108       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13109       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13110       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13111       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13112       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13113       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13114       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13115       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13116       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13117       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13118       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13119       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13120       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13121       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13122       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13123     } DSP0N0INT1CLR_b;
13124   } ;
13125 
13126   union {
13127     __IOM uint32_t DSP0N0INT1SET;               /*!< (@ 0x0000035C) Write a 1 to a bit in this register to instantly
13128                                                                     generate an interrupt from this module.
13129                                                                     (Generally used for testing purposes).                     */
13130 
13131     struct {
13132       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13133       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13134       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13135       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13136       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13137       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13138       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13139       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13140       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13141       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13142       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13143       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13144       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13145       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13146       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13147       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13148       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13149       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13150       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13151       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13152       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13153       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13154       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13155       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13156       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13157       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13158       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13159       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13160       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13161       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13162       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13163       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13164     } DSP0N0INT1SET_b;
13165   } ;
13166 
13167   union {
13168     __IOM uint32_t DSP0N0INT2EN;                /*!< (@ 0x00000360) Set bits in this register to allow this module
13169                                                                     to generate the corresponding interrupt.                   */
13170 
13171     struct {
13172       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13173       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13174       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13175       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13176       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13177       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13178       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13179       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13180       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13181       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13182       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13183       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13184       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13185       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13186       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13187       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13188       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13189       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13190       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13191       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13192       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13193       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13194       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13195       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13196       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13197       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13198       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13199       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13200       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13201       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13202       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13203       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13204     } DSP0N0INT2EN_b;
13205   } ;
13206 
13207   union {
13208     __IOM uint32_t DSP0N0INT2STAT;              /*!< (@ 0x00000364) Read bits from this register to discover the
13209                                                                     cause of a recent interrupt.                               */
13210 
13211     struct {
13212       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13213       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13214       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13215       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13216       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13217       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13218       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13219       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13220       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13221       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13222       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13223       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13224       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13225       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13226       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13227       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13228       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13229       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13230       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13231       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13232       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13233       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13234       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13235       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13236       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13237       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13238       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13239       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13240       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13241       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13242       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13243       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13244     } DSP0N0INT2STAT_b;
13245   } ;
13246 
13247   union {
13248     __IOM uint32_t DSP0N0INT2CLR;               /*!< (@ 0x00000368) Write a 1 to a bit in this register to clear
13249                                                                     the interrupt status associated with that
13250                                                                     bit.                                                       */
13251 
13252     struct {
13253       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13254       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13255       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13256       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13257       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13258       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13259       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13260       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13261       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13262       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13263       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13264       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13265       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13266       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13267       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13268       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13269       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13270       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13271       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13272       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13273       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13274       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13275       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13276       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13277       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13278       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13279       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13280       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13281       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13282       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13283       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13284       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13285     } DSP0N0INT2CLR_b;
13286   } ;
13287 
13288   union {
13289     __IOM uint32_t DSP0N0INT2SET;               /*!< (@ 0x0000036C) Write a 1 to a bit in this register to instantly
13290                                                                     generate an interrupt from this module.
13291                                                                     (Generally used for testing purposes).                     */
13292 
13293     struct {
13294       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13295       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13296       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13297       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13298       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13299       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13300       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13301       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13302       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13303       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13304       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13305       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13306       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13307       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13308       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13309       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13310       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13311       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13312       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13313       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13314       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13315       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13316       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13317       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13318       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13319       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13320       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13321       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13322       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13323       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13324       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13325       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13326     } DSP0N0INT2SET_b;
13327   } ;
13328 
13329   union {
13330     __IOM uint32_t DSP0N0INT3EN;                /*!< (@ 0x00000370) Set bits in this register to allow this module
13331                                                                     to generate the corresponding interrupt.                   */
13332 
13333     struct {
13334       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13335       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13336       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13337       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13338       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13339       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13340       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13341       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13342       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13343       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13344       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13345       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13346       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13347       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13348       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13349       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13350       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13351       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13352       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13353       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13354       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13355       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13356       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13357       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13358       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13359       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13360       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13361       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13362       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13363       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13364       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13365       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13366     } DSP0N0INT3EN_b;
13367   } ;
13368 
13369   union {
13370     __IOM uint32_t DSP0N0INT3STAT;              /*!< (@ 0x00000374) Read bits from this register to discover the
13371                                                                     cause of a recent interrupt.                               */
13372 
13373     struct {
13374       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13375       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13376       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13377       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13378       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13379       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13380       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13381       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13382       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13383       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13384       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13385       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13386       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13387       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13388       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13389       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13390       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13391       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13392       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13393       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13394       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13395       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13396       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13397       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13398       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13399       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13400       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13401       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13402       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13403       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13404       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13405       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13406     } DSP0N0INT3STAT_b;
13407   } ;
13408 
13409   union {
13410     __IOM uint32_t DSP0N0INT3CLR;               /*!< (@ 0x00000378) Write a 1 to a bit in this register to clear
13411                                                                     the interrupt status associated with that
13412                                                                     bit.                                                       */
13413 
13414     struct {
13415       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13416       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13417       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13418       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13419       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13420       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13421       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13422       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13423       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13424       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13425       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13426       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13427       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13428       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13429       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13430       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13431       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13432       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13433       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13434       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13435       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13436       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13437       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13438       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13439       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13440       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13441       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13442       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13443       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13444       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13445       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13446       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13447     } DSP0N0INT3CLR_b;
13448   } ;
13449 
13450   union {
13451     __IOM uint32_t DSP0N0INT3SET;               /*!< (@ 0x0000037C) Write a 1 to a bit in this register to instantly
13452                                                                     generate an interrupt from this module.
13453                                                                     (Generally used for testing purposes).                     */
13454 
13455     struct {
13456       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13457       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13458       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13459       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13460       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13461       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13462       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13463       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13464       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13465       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13466       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13467       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13468       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13469       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13470       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13471       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13472       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13473       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13474       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13475       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13476       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13477       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13478       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13479       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13480       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13481       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13482       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13483       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13484       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13485       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13486       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13487       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13488     } DSP0N0INT3SET_b;
13489   } ;
13490 
13491   union {
13492     __IOM uint32_t DSP0N1INT0EN;                /*!< (@ 0x00000380) Set bits in this register to allow this module
13493                                                                     to generate the corresponding interrupt.                   */
13494 
13495     struct {
13496       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13497       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13498       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13499       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13500       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13501       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13502       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13503       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13504       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13505       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13506       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13507       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13508       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13509       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13510       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13511       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13512       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13513       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13514       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13515       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13516       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13517       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13518       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13519       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13520       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13521       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13522       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13523       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13524       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13525       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13526       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13527       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13528     } DSP0N1INT0EN_b;
13529   } ;
13530 
13531   union {
13532     __IOM uint32_t DSP0N1INT0STAT;              /*!< (@ 0x00000384) Read bits from this register to discover the
13533                                                                     cause of a recent interrupt.                               */
13534 
13535     struct {
13536       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13537       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13538       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13539       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13540       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13541       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13542       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13543       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13544       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13545       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13546       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13547       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13548       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13549       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13550       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13551       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13552       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13553       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13554       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13555       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13556       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13557       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13558       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13559       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13560       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13561       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13562       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13563       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13564       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13565       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13566       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13567       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13568     } DSP0N1INT0STAT_b;
13569   } ;
13570 
13571   union {
13572     __IOM uint32_t DSP0N1INT0CLR;               /*!< (@ 0x00000388) Write a 1 to a bit in this register to clear
13573                                                                     the interrupt status associated with that
13574                                                                     bit.                                                       */
13575 
13576     struct {
13577       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13578       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13579       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13580       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13581       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13582       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13583       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13584       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13585       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13586       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13587       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13588       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13589       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13590       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13591       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13592       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13593       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13594       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13595       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13596       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13597       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13598       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13599       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13600       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13601       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13602       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13603       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13604       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13605       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13606       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13607       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13608       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13609     } DSP0N1INT0CLR_b;
13610   } ;
13611 
13612   union {
13613     __IOM uint32_t DSP0N1INT0SET;               /*!< (@ 0x0000038C) Write a 1 to a bit in this register to instantly
13614                                                                     generate an interrupt from this module.
13615                                                                     (Generally used for testing purposes).                     */
13616 
13617     struct {
13618       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13619       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13620       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13621       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13622       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13623       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13624       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13625       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13626       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13627       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13628       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13629       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13630       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13631       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13632       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13633       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13634       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13635       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13636       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13637       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13638       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13639       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13640       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13641       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13642       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13643       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13644       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13645       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13646       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13647       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13648       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13649       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13650     } DSP0N1INT0SET_b;
13651   } ;
13652 
13653   union {
13654     __IOM uint32_t DSP0N1INT1EN;                /*!< (@ 0x00000390) Set bits in this register to allow this module
13655                                                                     to generate the corresponding interrupt.                   */
13656 
13657     struct {
13658       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13659       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13660       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13661       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13662       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13663       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13664       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13665       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13666       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13667       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13668       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13669       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13670       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13671       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13672       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13673       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13674       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13675       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13676       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13677       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13678       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13679       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13680       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13681       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13682       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13683       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13684       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13685       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13686       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13687       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13688       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13689       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13690     } DSP0N1INT1EN_b;
13691   } ;
13692 
13693   union {
13694     __IOM uint32_t DSP0N1INT1STAT;              /*!< (@ 0x00000394) Read bits from this register to discover the
13695                                                                     cause of a recent interrupt.                               */
13696 
13697     struct {
13698       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13699       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13700       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13701       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13702       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13703       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13704       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13705       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13706       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13707       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13708       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13709       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13710       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13711       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13712       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13713       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13714       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13715       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13716       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13717       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13718       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13719       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13720       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13721       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13722       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13723       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13724       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13725       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13726       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13727       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13728       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13729       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13730     } DSP0N1INT1STAT_b;
13731   } ;
13732 
13733   union {
13734     __IOM uint32_t DSP0N1INT1CLR;               /*!< (@ 0x00000398) Write a 1 to a bit in this register to clear
13735                                                                     the interrupt status associated with that
13736                                                                     bit.                                                       */
13737 
13738     struct {
13739       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13740       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13741       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13742       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13743       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13744       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13745       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13746       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13747       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13748       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13749       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13750       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13751       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13752       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13753       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13754       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13755       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13756       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13757       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13758       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13759       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13760       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13761       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13762       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13763       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13764       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13765       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13766       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13767       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13768       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13769       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13770       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13771     } DSP0N1INT1CLR_b;
13772   } ;
13773 
13774   union {
13775     __IOM uint32_t DSP0N1INT1SET;               /*!< (@ 0x0000039C) Write a 1 to a bit in this register to instantly
13776                                                                     generate an interrupt from this module.
13777                                                                     (Generally used for testing purposes).                     */
13778 
13779     struct {
13780       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13781       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13782       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13783       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13784       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13785       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13786       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13787       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13788       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13789       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13790       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13791       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13792       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13793       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13794       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13795       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13796       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13797       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13798       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13799       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13800       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13801       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13802       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13803       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13804       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13805       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13806       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13807       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13808       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13809       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13810       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13811       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13812     } DSP0N1INT1SET_b;
13813   } ;
13814 
13815   union {
13816     __IOM uint32_t DSP0N1INT2EN;                /*!< (@ 0x000003A0) Set bits in this register to allow this module
13817                                                                     to generate the corresponding interrupt.                   */
13818 
13819     struct {
13820       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
13821       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
13822       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
13823       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
13824       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
13825       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
13826       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
13827       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
13828       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
13829       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
13830       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
13831       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
13832       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
13833       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
13834       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
13835       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
13836       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
13837       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
13838       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
13839       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
13840       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
13841       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
13842       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
13843       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
13844       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
13845       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
13846       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
13847       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
13848       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
13849       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
13850       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
13851       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
13852     } DSP0N1INT2EN_b;
13853   } ;
13854 
13855   union {
13856     __IOM uint32_t DSP0N1INT2STAT;              /*!< (@ 0x000003A4) Read bits from this register to discover the
13857                                                                     cause of a recent interrupt.                               */
13858 
13859     struct {
13860       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
13861       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
13862       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
13863       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
13864       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
13865       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
13866       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
13867       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
13868       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
13869       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
13870       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
13871       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
13872       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
13873       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
13874       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
13875       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
13876       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
13877       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
13878       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
13879       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
13880       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
13881       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
13882       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
13883       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
13884       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
13885       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
13886       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
13887       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
13888       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
13889       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
13890       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
13891       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
13892     } DSP0N1INT2STAT_b;
13893   } ;
13894 
13895   union {
13896     __IOM uint32_t DSP0N1INT2CLR;               /*!< (@ 0x000003A8) Write a 1 to a bit in this register to clear
13897                                                                     the interrupt status associated with that
13898                                                                     bit.                                                       */
13899 
13900     struct {
13901       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
13902       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
13903       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
13904       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
13905       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
13906       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
13907       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
13908       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
13909       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
13910       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
13911       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
13912       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
13913       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
13914       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
13915       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
13916       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
13917       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
13918       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
13919       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
13920       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
13921       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
13922       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
13923       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
13924       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
13925       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
13926       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
13927       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
13928       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
13929       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
13930       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
13931       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
13932       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
13933     } DSP0N1INT2CLR_b;
13934   } ;
13935 
13936   union {
13937     __IOM uint32_t DSP0N1INT2SET;               /*!< (@ 0x000003AC) Write a 1 to a bit in this register to instantly
13938                                                                     generate an interrupt from this module.
13939                                                                     (Generally used for testing purposes).                     */
13940 
13941     struct {
13942       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
13943       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
13944       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
13945       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
13946       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
13947       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
13948       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
13949       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
13950       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
13951       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
13952       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
13953       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
13954       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
13955       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
13956       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
13957       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
13958       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
13959       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
13960       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
13961       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
13962       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
13963       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
13964       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
13965       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
13966       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
13967       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
13968       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
13969       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
13970       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
13971       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
13972       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
13973       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
13974     } DSP0N1INT2SET_b;
13975   } ;
13976 
13977   union {
13978     __IOM uint32_t DSP0N1INT3EN;                /*!< (@ 0x000003B0) Set bits in this register to allow this module
13979                                                                     to generate the corresponding interrupt.                   */
13980 
13981     struct {
13982       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
13983       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
13984       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
13985       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
13986       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
13987       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
13988       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
13989       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
13990       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
13991       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
13992       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
13993       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
13994       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
13995       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
13996       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
13997       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
13998       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
13999       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14000       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14001       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14002       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14003       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14004       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14005       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14006       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14007       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14008       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14009       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14010       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14011       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14012       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14013       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14014     } DSP0N1INT3EN_b;
14015   } ;
14016 
14017   union {
14018     __IOM uint32_t DSP0N1INT3STAT;              /*!< (@ 0x000003B4) Read bits from this register to discover the
14019                                                                     cause of a recent interrupt.                               */
14020 
14021     struct {
14022       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
14023       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
14024       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
14025       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
14026       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
14027       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
14028       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
14029       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
14030       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
14031       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
14032       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
14033       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
14034       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
14035       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
14036       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
14037       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
14038       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
14039       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14040       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14041       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14042       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14043       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14044       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14045       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14046       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14047       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14048       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14049       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14050       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14051       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14052       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14053       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14054     } DSP0N1INT3STAT_b;
14055   } ;
14056 
14057   union {
14058     __IOM uint32_t DSP0N1INT3CLR;               /*!< (@ 0x000003B8) Write a 1 to a bit in this register to clear
14059                                                                     the interrupt status associated with that
14060                                                                     bit.                                                       */
14061 
14062     struct {
14063       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
14064       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
14065       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
14066       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
14067       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
14068       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
14069       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
14070       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
14071       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
14072       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
14073       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
14074       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
14075       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
14076       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
14077       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
14078       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
14079       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
14080       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14081       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14082       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14083       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14084       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14085       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14086       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14087       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14088       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14089       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14090       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14091       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14092       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14093       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14094       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14095     } DSP0N1INT3CLR_b;
14096   } ;
14097 
14098   union {
14099     __IOM uint32_t DSP0N1INT3SET;               /*!< (@ 0x000003BC) Write a 1 to a bit in this register to instantly
14100                                                                     generate an interrupt from this module.
14101                                                                     (Generally used for testing purposes).                     */
14102 
14103     struct {
14104       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
14105       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
14106       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
14107       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
14108       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
14109       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
14110       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
14111       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
14112       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
14113       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
14114       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
14115       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
14116       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
14117       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
14118       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
14119       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
14120       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
14121       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14122       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14123       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14124       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14125       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14126       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14127       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14128       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14129       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14130       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14131       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14132       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14133       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14134       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14135       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14136     } DSP0N1INT3SET_b;
14137   } ;
14138 
14139   union {
14140     __IOM uint32_t DSP1N0INT0EN;                /*!< (@ 0x000003C0) Set bits in this register to allow this module
14141                                                                     to generate the corresponding interrupt.                   */
14142 
14143     struct {
14144       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14145       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14146       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14147       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14148       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14149       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14150       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14151       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14152       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14153       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14154       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14155       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14156       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14157       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14158       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14159       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14160       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14161       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14162       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14163       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14164       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14165       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14166       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14167       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14168       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14169       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14170       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14171       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14172       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14173       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14174       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14175       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14176     } DSP1N0INT0EN_b;
14177   } ;
14178 
14179   union {
14180     __IOM uint32_t DSP1N0INT0STAT;              /*!< (@ 0x000003C4) Read bits from this register to discover the
14181                                                                     cause of a recent interrupt.                               */
14182 
14183     struct {
14184       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14185       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14186       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14187       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14188       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14189       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14190       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14191       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14192       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14193       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14194       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14195       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14196       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14197       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14198       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14199       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14200       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14201       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14202       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14203       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14204       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14205       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14206       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14207       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14208       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14209       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14210       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14211       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14212       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14213       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14214       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14215       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14216     } DSP1N0INT0STAT_b;
14217   } ;
14218 
14219   union {
14220     __IOM uint32_t DSP1N0INT0CLR;               /*!< (@ 0x000003C8) Write a 1 to a bit in this register to clear
14221                                                                     the interrupt status associated with that
14222                                                                     bit.                                                       */
14223 
14224     struct {
14225       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14226       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14227       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14228       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14229       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14230       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14231       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14232       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14233       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14234       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14235       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14236       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14237       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14238       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14239       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14240       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14241       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14242       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14243       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14244       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14245       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14246       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14247       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14248       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14249       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14250       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14251       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14252       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14253       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14254       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14255       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14256       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14257     } DSP1N0INT0CLR_b;
14258   } ;
14259 
14260   union {
14261     __IOM uint32_t DSP1N0INT0SET;               /*!< (@ 0x000003CC) Write a 1 to a bit in this register to instantly
14262                                                                     generate an interrupt from this module.
14263                                                                     (Generally used for testing purposes).                     */
14264 
14265     struct {
14266       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14267       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14268       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14269       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14270       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14271       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14272       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14273       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14274       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14275       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14276       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14277       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14278       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14279       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14280       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14281       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14282       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14283       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14284       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14285       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14286       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14287       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14288       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14289       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14290       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14291       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14292       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14293       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14294       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14295       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14296       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14297       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14298     } DSP1N0INT0SET_b;
14299   } ;
14300 
14301   union {
14302     __IOM uint32_t DSP1N0INT1EN;                /*!< (@ 0x000003D0) Set bits in this register to allow this module
14303                                                                     to generate the corresponding interrupt.                   */
14304 
14305     struct {
14306       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14307       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14308       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14309       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14310       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14311       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14312       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14313       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14314       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14315       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14316       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14317       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14318       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14319       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14320       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14321       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14322       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14323       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14324       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14325       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14326       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14327       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14328       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14329       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14330       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14331       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14332       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14333       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14334       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14335       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14336       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14337       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14338     } DSP1N0INT1EN_b;
14339   } ;
14340 
14341   union {
14342     __IOM uint32_t DSP1N0INT1STAT;              /*!< (@ 0x000003D4) Read bits from this register to discover the
14343                                                                     cause of a recent interrupt.                               */
14344 
14345     struct {
14346       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14347       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14348       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14349       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14350       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14351       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14352       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14353       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14354       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14355       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14356       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14357       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14358       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14359       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14360       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14361       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14362       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14363       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14364       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14365       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14366       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14367       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14368       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14369       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14370       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14371       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14372       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14373       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14374       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14375       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14376       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14377       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14378     } DSP1N0INT1STAT_b;
14379   } ;
14380 
14381   union {
14382     __IOM uint32_t DSP1N0INT1CLR;               /*!< (@ 0x000003D8) Write a 1 to a bit in this register to clear
14383                                                                     the interrupt status associated with that
14384                                                                     bit.                                                       */
14385 
14386     struct {
14387       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14388       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14389       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14390       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14391       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14392       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14393       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14394       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14395       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14396       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14397       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14398       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14399       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14400       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14401       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14402       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14403       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14404       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14405       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14406       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14407       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14408       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14409       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14410       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14411       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14412       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14413       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14414       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14415       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14416       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14417       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14418       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14419     } DSP1N0INT1CLR_b;
14420   } ;
14421 
14422   union {
14423     __IOM uint32_t DSP1N0INT1SET;               /*!< (@ 0x000003DC) Write a 1 to a bit in this register to instantly
14424                                                                     generate an interrupt from this module.
14425                                                                     (Generally used for testing purposes).                     */
14426 
14427     struct {
14428       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14429       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14430       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14431       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14432       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14433       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14434       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14435       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14436       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14437       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14438       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14439       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14440       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14441       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14442       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14443       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14444       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14445       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14446       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14447       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14448       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14449       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14450       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14451       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14452       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14453       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14454       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14455       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14456       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14457       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14458       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14459       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14460     } DSP1N0INT1SET_b;
14461   } ;
14462 
14463   union {
14464     __IOM uint32_t DSP1N0INT2EN;                /*!< (@ 0x000003E0) Set bits in this register to allow this module
14465                                                                     to generate the corresponding interrupt.                   */
14466 
14467     struct {
14468       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14469       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14470       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14471       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14472       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14473       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14474       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14475       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14476       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14477       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14478       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14479       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14480       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14481       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14482       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14483       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14484       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14485       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14486       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14487       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14488       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14489       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14490       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14491       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14492       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14493       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14494       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14495       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14496       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14497       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14498       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14499       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14500     } DSP1N0INT2EN_b;
14501   } ;
14502 
14503   union {
14504     __IOM uint32_t DSP1N0INT2STAT;              /*!< (@ 0x000003E4) Read bits from this register to discover the
14505                                                                     cause of a recent interrupt.                               */
14506 
14507     struct {
14508       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14509       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14510       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14511       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14512       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14513       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14514       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14515       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14516       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14517       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14518       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14519       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14520       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14521       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14522       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14523       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14524       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14525       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14526       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14527       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14528       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14529       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14530       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14531       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14532       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14533       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14534       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14535       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14536       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14537       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14538       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14539       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14540     } DSP1N0INT2STAT_b;
14541   } ;
14542 
14543   union {
14544     __IOM uint32_t DSP1N0INT2CLR;               /*!< (@ 0x000003E8) Write a 1 to a bit in this register to clear
14545                                                                     the interrupt status associated with that
14546                                                                     bit.                                                       */
14547 
14548     struct {
14549       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14550       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14551       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14552       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14553       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14554       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14555       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14556       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14557       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14558       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14559       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14560       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14561       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14562       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14563       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14564       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14565       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14566       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14567       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14568       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14569       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14570       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14571       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14572       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14573       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14574       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14575       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14576       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14577       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14578       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14579       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14580       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14581     } DSP1N0INT2CLR_b;
14582   } ;
14583 
14584   union {
14585     __IOM uint32_t DSP1N0INT2SET;               /*!< (@ 0x000003EC) Write a 1 to a bit in this register to instantly
14586                                                                     generate an interrupt from this module.
14587                                                                     (Generally used for testing purposes).                     */
14588 
14589     struct {
14590       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14591       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14592       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14593       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14594       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14595       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14596       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14597       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14598       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14599       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14600       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14601       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14602       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14603       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14604       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14605       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14606       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14607       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14608       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14609       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14610       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14611       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14612       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14613       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14614       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14615       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14616       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14617       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14618       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14619       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14620       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14621       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14622     } DSP1N0INT2SET_b;
14623   } ;
14624 
14625   union {
14626     __IOM uint32_t DSP1N0INT3EN;                /*!< (@ 0x000003F0) Set bits in this register to allow this module
14627                                                                     to generate the corresponding interrupt.                   */
14628 
14629     struct {
14630       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14631       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14632       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14633       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14634       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14635       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14636       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14637       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14638       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14639       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14640       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14641       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14642       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14643       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14644       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14645       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14646       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14647       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14648       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14649       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14650       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14651       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14652       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14653       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14654       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14655       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14656       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14657       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14658       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14659       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14660       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14661       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14662     } DSP1N0INT3EN_b;
14663   } ;
14664 
14665   union {
14666     __IOM uint32_t DSP1N0INT3STAT;              /*!< (@ 0x000003F4) Read bits from this register to discover the
14667                                                                     cause of a recent interrupt.                               */
14668 
14669     struct {
14670       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14671       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14672       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14673       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14674       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14675       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14676       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14677       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14678       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14679       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14680       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14681       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14682       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14683       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14684       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14685       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14686       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14687       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14688       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14689       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14690       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14691       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14692       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14693       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14694       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14695       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14696       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14697       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14698       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14699       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14700       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14701       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14702     } DSP1N0INT3STAT_b;
14703   } ;
14704 
14705   union {
14706     __IOM uint32_t DSP1N0INT3CLR;               /*!< (@ 0x000003F8) Write a 1 to a bit in this register to clear
14707                                                                     the interrupt status associated with that
14708                                                                     bit.                                                       */
14709 
14710     struct {
14711       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14712       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14713       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14714       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14715       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14716       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14717       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14718       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14719       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14720       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14721       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14722       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14723       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14724       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14725       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14726       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14727       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14728       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14729       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14730       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14731       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14732       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14733       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14734       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14735       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14736       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14737       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14738       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14739       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14740       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14741       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14742       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14743     } DSP1N0INT3CLR_b;
14744   } ;
14745 
14746   union {
14747     __IOM uint32_t DSP1N0INT3SET;               /*!< (@ 0x000003FC) Write a 1 to a bit in this register to instantly
14748                                                                     generate an interrupt from this module.
14749                                                                     (Generally used for testing purposes).                     */
14750 
14751     struct {
14752       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14753       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14754       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14755       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14756       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14757       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14758       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14759       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14760       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14761       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14762       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14763       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14764       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14765       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14766       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14767       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14768       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14769       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14770       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14771       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14772       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14773       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14774       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14775       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14776       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14777       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14778       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14779       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14780       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14781       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14782       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14783       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14784     } DSP1N0INT3SET_b;
14785   } ;
14786 
14787   union {
14788     __IOM uint32_t DSP1N1INT0EN;                /*!< (@ 0x00000400) Set bits in this register to allow this module
14789                                                                     to generate the corresponding interrupt.                   */
14790 
14791     struct {
14792       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
14793       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
14794       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
14795       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
14796       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
14797       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
14798       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
14799       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
14800       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
14801       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
14802       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
14803       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
14804       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
14805       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
14806       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
14807       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
14808       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
14809       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
14810       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
14811       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
14812       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
14813       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
14814       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
14815       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
14816       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
14817       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
14818       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
14819       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
14820       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
14821       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
14822       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
14823       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
14824     } DSP1N1INT0EN_b;
14825   } ;
14826 
14827   union {
14828     __IOM uint32_t DSP1N1INT0STAT;              /*!< (@ 0x00000404) Read bits from this register to discover the
14829                                                                     cause of a recent interrupt.                               */
14830 
14831     struct {
14832       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
14833       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
14834       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
14835       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
14836       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
14837       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
14838       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
14839       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
14840       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
14841       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
14842       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
14843       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
14844       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
14845       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
14846       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
14847       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
14848       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
14849       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
14850       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
14851       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
14852       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
14853       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
14854       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
14855       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
14856       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
14857       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
14858       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
14859       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
14860       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
14861       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
14862       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
14863       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
14864     } DSP1N1INT0STAT_b;
14865   } ;
14866 
14867   union {
14868     __IOM uint32_t DSP1N1INT0CLR;               /*!< (@ 0x00000408) Write a 1 to a bit in this register to clear
14869                                                                     the interrupt status associated with that
14870                                                                     bit.                                                       */
14871 
14872     struct {
14873       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
14874       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
14875       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
14876       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
14877       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
14878       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
14879       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
14880       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
14881       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
14882       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
14883       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
14884       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
14885       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
14886       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
14887       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
14888       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
14889       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
14890       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
14891       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
14892       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
14893       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
14894       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
14895       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
14896       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
14897       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
14898       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
14899       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
14900       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
14901       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
14902       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
14903       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
14904       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
14905     } DSP1N1INT0CLR_b;
14906   } ;
14907 
14908   union {
14909     __IOM uint32_t DSP1N1INT0SET;               /*!< (@ 0x0000040C) Write a 1 to a bit in this register to instantly
14910                                                                     generate an interrupt from this module.
14911                                                                     (Generally used for testing purposes).                     */
14912 
14913     struct {
14914       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
14915       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
14916       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
14917       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
14918       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
14919       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
14920       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
14921       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
14922       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
14923       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
14924       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
14925       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
14926       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
14927       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
14928       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
14929       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
14930       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
14931       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
14932       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
14933       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
14934       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
14935       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
14936       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
14937       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
14938       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
14939       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
14940       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
14941       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
14942       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
14943       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
14944       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
14945       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
14946     } DSP1N1INT0SET_b;
14947   } ;
14948 
14949   union {
14950     __IOM uint32_t DSP1N1INT1EN;                /*!< (@ 0x00000410) Set bits in this register to allow this module
14951                                                                     to generate the corresponding interrupt.                   */
14952 
14953     struct {
14954       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
14955       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
14956       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
14957       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
14958       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
14959       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
14960       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
14961       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
14962       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
14963       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
14964       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
14965       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
14966       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
14967       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
14968       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
14969       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
14970       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
14971       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
14972       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
14973       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
14974       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
14975       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
14976       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
14977       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
14978       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
14979       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
14980       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
14981       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
14982       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
14983       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
14984       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
14985       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
14986     } DSP1N1INT1EN_b;
14987   } ;
14988 
14989   union {
14990     __IOM uint32_t DSP1N1INT1STAT;              /*!< (@ 0x00000414) Read bits from this register to discover the
14991                                                                     cause of a recent interrupt.                               */
14992 
14993     struct {
14994       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
14995       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
14996       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
14997       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
14998       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
14999       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
15000       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
15001       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
15002       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
15003       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
15004       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
15005       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
15006       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
15007       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
15008       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
15009       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
15010       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
15011       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
15012       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
15013       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
15014       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
15015       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
15016       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
15017       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
15018       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
15019       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
15020       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
15021       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
15022       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
15023       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
15024       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
15025       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
15026     } DSP1N1INT1STAT_b;
15027   } ;
15028 
15029   union {
15030     __IOM uint32_t DSP1N1INT1CLR;               /*!< (@ 0x00000418) Write a 1 to a bit in this register to clear
15031                                                                     the interrupt status associated with that
15032                                                                     bit.                                                       */
15033 
15034     struct {
15035       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
15036       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
15037       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
15038       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
15039       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
15040       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
15041       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
15042       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
15043       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
15044       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
15045       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
15046       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
15047       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
15048       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
15049       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
15050       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
15051       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
15052       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
15053       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
15054       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
15055       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
15056       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
15057       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
15058       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
15059       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
15060       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
15061       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
15062       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
15063       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
15064       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
15065       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
15066       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
15067     } DSP1N1INT1CLR_b;
15068   } ;
15069 
15070   union {
15071     __IOM uint32_t DSP1N1INT1SET;               /*!< (@ 0x0000041C) Write a 1 to a bit in this register to instantly
15072                                                                     generate an interrupt from this module.
15073                                                                     (Generally used for testing purposes).                     */
15074 
15075     struct {
15076       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
15077       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
15078       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
15079       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
15080       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
15081       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
15082       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
15083       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
15084       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
15085       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
15086       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
15087       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
15088       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
15089       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
15090       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
15091       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
15092       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
15093       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
15094       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
15095       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
15096       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
15097       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
15098       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
15099       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
15100       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
15101       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
15102       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
15103       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
15104       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
15105       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
15106       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
15107       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
15108     } DSP1N1INT1SET_b;
15109   } ;
15110 
15111   union {
15112     __IOM uint32_t DSP1N1INT2EN;                /*!< (@ 0x00000420) Set bits in this register to allow this module
15113                                                                     to generate the corresponding interrupt.                   */
15114 
15115     struct {
15116       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15117       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15118       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15119       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15120       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15121       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15122       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15123       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15124       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15125       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15126       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15127       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15128       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15129       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15130       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15131       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15132       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15133       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15134       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15135       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15136       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15137       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15138       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15139       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15140       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15141       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15142       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15143       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15144       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15145       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15146       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15147       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15148     } DSP1N1INT2EN_b;
15149   } ;
15150 
15151   union {
15152     __IOM uint32_t DSP1N1INT2STAT;              /*!< (@ 0x00000424) Read bits from this register to discover the
15153                                                                     cause of a recent interrupt.                               */
15154 
15155     struct {
15156       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15157       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15158       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15159       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15160       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15161       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15162       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15163       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15164       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15165       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15166       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15167       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15168       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15169       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15170       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15171       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15172       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15173       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15174       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15175       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15176       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15177       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15178       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15179       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15180       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15181       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15182       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15183       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15184       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15185       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15186       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15187       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15188     } DSP1N1INT2STAT_b;
15189   } ;
15190 
15191   union {
15192     __IOM uint32_t DSP1N1INT2CLR;               /*!< (@ 0x00000428) Write a 1 to a bit in this register to clear
15193                                                                     the interrupt status associated with that
15194                                                                     bit.                                                       */
15195 
15196     struct {
15197       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15198       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15199       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15200       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15201       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15202       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15203       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15204       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15205       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15206       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15207       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15208       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15209       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15210       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15211       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15212       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15213       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15214       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15215       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15216       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15217       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15218       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15219       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15220       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15221       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15222       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15223       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15224       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15225       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15226       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15227       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15228       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15229     } DSP1N1INT2CLR_b;
15230   } ;
15231 
15232   union {
15233     __IOM uint32_t DSP1N1INT2SET;               /*!< (@ 0x0000042C) Write a 1 to a bit in this register to instantly
15234                                                                     generate an interrupt from this module.
15235                                                                     (Generally used for testing purposes).                     */
15236 
15237     struct {
15238       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15239       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15240       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15241       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15242       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15243       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15244       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15245       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15246       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15247       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15248       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15249       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15250       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15251       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15252       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15253       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15254       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15255       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15256       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15257       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15258       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15259       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15260       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15261       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15262       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15263       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15264       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15265       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15266       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15267       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15268       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15269       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15270     } DSP1N1INT2SET_b;
15271   } ;
15272 
15273   union {
15274     __IOM uint32_t DSP1N1INT3EN;                /*!< (@ 0x00000430) Set bits in this register to allow this module
15275                                                                     to generate the corresponding interrupt.                   */
15276 
15277     struct {
15278       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15279       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15280       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15281       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15282       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15283       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15284       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15285       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15286       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15287       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15288       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15289       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15290       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15291       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15292       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15293       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15294       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15295       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15296       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15297       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15298       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15299       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15300       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15301       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15302       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15303       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15304       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15305       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15306       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15307       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15308       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15309       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15310     } DSP1N1INT3EN_b;
15311   } ;
15312 
15313   union {
15314     __IOM uint32_t DSP1N1INT3STAT;              /*!< (@ 0x00000434) Read bits from this register to discover the
15315                                                                     cause of a recent interrupt.                               */
15316 
15317     struct {
15318       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15319       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15320       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15321       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15322       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15323       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15324       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15325       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15326       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15327       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15328       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15329       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15330       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15331       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15332       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15333       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15334       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15335       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15336       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15337       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15338       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15339       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15340       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15341       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15342       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15343       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15344       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15345       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15346       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15347       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15348       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15349       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15350     } DSP1N1INT3STAT_b;
15351   } ;
15352 
15353   union {
15354     __IOM uint32_t DSP1N1INT3CLR;               /*!< (@ 0x00000438) Write a 1 to a bit in this register to clear
15355                                                                     the interrupt status associated with that
15356                                                                     bit.                                                       */
15357 
15358     struct {
15359       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15360       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15361       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15362       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15363       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15364       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15365       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15366       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15367       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15368       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15369       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15370       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15371       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15372       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15373       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15374       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15375       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15376       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15377       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15378       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15379       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15380       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15381       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15382       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15383       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15384       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15385       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15386       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15387       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15388       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15389       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15390       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15391     } DSP1N1INT3CLR_b;
15392   } ;
15393 
15394   union {
15395     __IOM uint32_t DSP1N1INT3SET;               /*!< (@ 0x0000043C) Write a 1 to a bit in this register to instantly
15396                                                                     generate an interrupt from this module.
15397                                                                     (Generally used for testing purposes).                     */
15398 
15399     struct {
15400       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15401       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15402       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15403       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15404       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15405       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15406       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15407       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15408       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15409       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15410       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15411       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15412       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15413       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15414       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15415       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15416       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15417       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15418       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15419       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15420       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15421       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15422       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15423       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15424       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15425       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15426       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15427       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15428       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15429       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15430       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15431       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15432     } DSP1N1INT3SET_b;
15433   } ;
15434 } GPIO_Type;                                    /*!< Size = 1088 (0x440)                                                       */
15435 
15436 
15437 
15438 /* =========================================================================================================================== */
15439 /* ================                                            GPU                                            ================ */
15440 /* =========================================================================================================================== */
15441 
15442 
15443 /**
15444   * @brief Graphics Processing Unit (GPU)
15445   */
15446 
15447 typedef struct {                                /*!< (@ 0x40090000) GPU Structure                                              */
15448 
15449   union {
15450     __IOM uint32_t TEX0BASE;                    /*!< (@ 0x00000000) Base address of the drawing surface 0 (must be
15451                                                                     word aligned).                                             */
15452 
15453     struct {
15454       __IOM uint32_t Base       : 32;           /*!< [31..0] Address 0: base address of the drawing surface 0 (must
15455                                                      be word aligned).                                                         */
15456     } TEX0BASE_b;
15457   } ;
15458 
15459   union {
15460     __IOM uint32_t TEX0STRIDE;                  /*!< (@ 0x00000004) Image 0 mode and stride.                                   */
15461 
15462     struct {
15463       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15464                                                      to another                                                                */
15465       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] Image Mode                                                       */
15466       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] Image Format                                                     */
15467     } TEX0STRIDE_b;
15468   } ;
15469 
15470   union {
15471     __IOM uint32_t TEX0RES;                     /*!< (@ 0x00000008) Image 0 resolution.                                        */
15472 
15473     struct {
15474       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15475       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15476     } TEX0RES_b;
15477   } ;
15478   __IM  uint32_t  RESERVED;
15479 
15480   union {
15481     __IOM uint32_t TEX1BASE;                    /*!< (@ 0x00000010) Base address of the drawing surface 1 (must be
15482                                                                     word aligned).                                             */
15483 
15484     struct {
15485       __IOM uint32_t Base       : 32;           /*!< [31..0] address 1: base address of the drawing surface 1 (must
15486                                                      be word aligned).                                                         */
15487     } TEX1BASE_b;
15488   } ;
15489 
15490   union {
15491     __IOM uint32_t TEX1STRIDE;                  /*!< (@ 0x00000014) Image 1 mode and stride.                                   */
15492 
15493     struct {
15494       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15495                                                      to another                                                                */
15496       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] Image Mode                                                       */
15497       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] Image Format                                                     */
15498     } TEX1STRIDE_b;
15499   } ;
15500 
15501   union {
15502     __IOM uint32_t TEX1RES;                     /*!< (@ 0x00000018) Image 1 resolution.                                        */
15503 
15504     struct {
15505       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15506       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15507     } TEX1RES_b;
15508   } ;
15509 
15510   union {
15511     __IOM uint32_t TEX1COLOR;                   /*!< (@ 0x0000001C) Texture maps default color.Used with luminance
15512                                                                     and alpha-only color formats.                              */
15513 
15514     struct {
15515       __IOM uint32_t RED        : 8;            /*!< [7..0] red value                                                          */
15516       __IOM uint32_t GREEN      : 8;            /*!< [15..8] green value                                                       */
15517       __IOM uint32_t BLUE       : 8;            /*!< [23..16] blue value                                                       */
15518       __IOM uint32_t ALPHA      : 8;            /*!< [31..24] alpha value                                                      */
15519     } TEX1COLOR_b;
15520   } ;
15521 
15522   union {
15523     __IOM uint32_t TEX2BASE;                    /*!< (@ 0x00000020) Base address of the drawing surface 2 (must be
15524                                                                     word aligned).                                             */
15525 
15526     struct {
15527       __IOM uint32_t Drawing    : 32;           /*!< [31..0] surface 2 Base address of the drawing surface 2                   */
15528     } TEX2BASE_b;
15529   } ;
15530 
15531   union {
15532     __IOM uint32_t TEX2STRIDE;                  /*!< (@ 0x00000024) Image 2 mode and stride.                                   */
15533 
15534     struct {
15535       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15536                                                      to another                                                                */
15537       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] image mode                                                       */
15538       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] image format                                                     */
15539     } TEX2STRIDE_b;
15540   } ;
15541 
15542   union {
15543     __IOM uint32_t TEX2RES;                     /*!< (@ 0x00000028) Image 2 resolution.                                        */
15544 
15545     struct {
15546       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15547       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15548     } TEX2RES_b;
15549   } ;
15550   __IM  uint32_t  RESERVED1;
15551 
15552   union {
15553     __IOM uint32_t TEX3BASE;                    /*!< (@ 0x00000030) Base address of the drawing surface 3 (must be
15554                                                                     word aligned).                                             */
15555 
15556     struct {
15557       __IOM uint32_t Image      : 32;           /*!< [31..0] 3 Base address of the drawing surface                             */
15558     } TEX3BASE_b;
15559   } ;
15560 
15561   union {
15562     __IOM uint32_t TEX3STRIDE;                  /*!< (@ 0x00000034) mode and stride.                                           */
15563 
15564     struct {
15565       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15566                                                      to another                                                                */
15567       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] image mode                                                       */
15568       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] image format                                                     */
15569     } TEX3STRIDE_b;
15570   } ;
15571 
15572   union {
15573     __IOM uint32_t TEX3RES;                     /*!< (@ 0x00000038) Image 3 resolution.                                        */
15574 
15575     struct {
15576       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15577       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15578     } TEX3RES_b;
15579   } ;
15580   __IM  uint32_t  RESERVED2[21];
15581 
15582   union {
15583     __IOM uint32_t CGCMD;                       /*!< (@ 0x00000090) Clock gating enable                                        */
15584 
15585     struct {
15586       __IOM uint32_t STOP       : 1;            /*!< [0..0] stop clock                                                         */
15587       __IOM uint32_t START      : 1;            /*!< [1..1] start clock                                                        */
15588             uint32_t            : 30;
15589     } CGCMD_b;
15590   } ;
15591 
15592   union {
15593     __IOM uint32_t CGCTRL;                      /*!< (@ 0x00000094) CGCTRL register description needed here.                   */
15594 
15595     struct {
15596       __IOM uint32_t DISCLKPROC : 1;            /*!< [0..0] disable clock gating for command list processor                    */
15597       __IOM uint32_t DISCLKCFG  : 1;            /*!< [1..1] disable clock gating for configuration file                        */
15598       __IOM uint32_t DISCLKFRAME : 2;           /*!< [3..2] disable clock gating for framebuffer 0 (MISTAKE ?)                 */
15599       __IOM uint32_t RSVD0      : 19;           /*!< [22..4] This bitfield is reserved.                                        */
15600       __IOM uint32_t DISCLKCORE : 1;            /*!< [23..23] disable clock gating for core 0                                  */
15601       __IOM uint32_t RSVD1      : 6;            /*!< [29..24] This bitfield is reserved.                                       */
15602       __IOM uint32_t DISCLKMOD  : 2;            /*!< [31..30] disable clock gating for all modules (MISTAKE ?)                 */
15603     } CGCTRL_b;
15604   } ;
15605 
15606   union {
15607     __IOM uint32_t DIRTYTRIGMIN;                /*!< (@ 0x00000098) Resets dirty region to resolution size when written.       */
15608 
15609     struct {
15610       __IOM uint32_t DRTYREG    : 32;           /*!< [31..0] Resets dirty region to resolution size when written.              */
15611     } DIRTYTRIGMIN_b;
15612   } ;
15613 
15614   union {
15615     __IOM uint32_t DIRTYTRIGMAX;                /*!< (@ 0x0000009C) Resets dirty region to resolution size when written.       */
15616 
15617     struct {
15618       __IOM uint32_t DRTYREG    : 32;           /*!< [31..0] Resets dirty region to resolution size when written.              */
15619     } DIRTYTRIGMAX_b;
15620   } ;
15621   __IM  uint32_t  RESERVED3[4];
15622 
15623   union {
15624     __IOM uint32_t STATUS;                      /*!< (@ 0x000000B0) On read, returns GPU status (CHECK address!!).             */
15625 
15626     struct {
15627       __IOM uint32_t COREBSY    : 4;            /*!< [3..0] processing core busy (Cores 3-0)                                   */
15628       __IOM uint32_t PIPEBSY    : 4;            /*!< [7..4] pipeline busy (Cores 3-0)                                          */
15629       __IOM uint32_t TEXTMAPBSY : 4;            /*!< [11..8] texture map busy (Cores 3-0)                                      */
15630       __IOM uint32_t RENDERBSY  : 4;            /*!< [15..12] render output unit busy (Cores 3-0)                              */
15631       __IOM uint32_t DEPTHFIFOBSY : 4;          /*!< [19..16] depth buffer busy (Cores 3-0)                                    */
15632             uint32_t            : 4;
15633       __IOM uint32_t RASTBSY    : 4;            /*!< [27..24] rasterizer busy                                                  */
15634       __IOM uint32_t CLPBSY     : 1;            /*!< [28..28] command list processor busy                                      */
15635       __IOM uint32_t CLBSY      : 1;            /*!< [29..29] command list bus busy                                            */
15636       __IOM uint32_t MEMBSY     : 1;            /*!< [30..30] memory system busy                                               */
15637       __IOM uint32_t SYSBSY     : 1;            /*!< [31..31] system busy                                                      */
15638     } STATUS_b;
15639   } ;
15640   __IM  uint32_t  RESERVED4[3];
15641 
15642   union {
15643     __IOM uint32_t BUSCTRL;                     /*!< (@ 0x000000C0) Bus Control                                                */
15644 
15645     struct {
15646       __IOM uint32_t BUSCTRL    : 32;           /*!< [31..0] Bus Control                                                       */
15647     } BUSCTRL_b;
15648   } ;
15649 
15650   union {
15651     __IOM uint32_t IMEMLDIADDR;                 /*!< (@ 0x000000C4) Load shader instruction memory address.                    */
15652 
15653     struct {
15654       __IOM uint32_t IMEM       : 32;           /*!< [31..0] ADDR Load shader. Load shader instruction memory address.         */
15655     } IMEMLDIADDR_b;
15656   } ;
15657 
15658   union {
15659     __IOM uint32_t IMEMLDIDATAHL;               /*!< (@ 0x000000C8) Load shader instruction Memory data (31:0).                */
15660 
15661     struct {
15662       __IOM uint32_t IMEM       : 32;           /*!< [31..0] DATA Load shader. Load shader instruction Memory data
15663                                                      (31:0).                                                                   */
15664     } IMEMLDIDATAHL_b;
15665   } ;
15666 
15667   union {
15668     __IOM uint32_t IMEMLDIDATAHH;               /*!< (@ 0x000000CC) Load shader instruction Memory data (63:32).               */
15669 
15670     struct {
15671       __IOM uint32_t IMEM       : 32;           /*!< [31..0] DATA Load shader. Load shader instruction Memory data
15672                                                      (63:32).                                                                  */
15673     } IMEMLDIDATAHH_b;
15674   } ;
15675   __IM  uint32_t  RESERVED5[6];
15676 
15677   union {
15678     __IOM uint32_t CMDLISTSTATUS;               /*!< (@ 0x000000E8) On read, returns command list processor status;
15679                                                                     On write, resets command list processor.                   */
15680 
15681     struct {
15682       __IOM uint32_t LIST       : 1;            /*!< [0..0] processor status                                                   */
15683             uint32_t            : 31;
15684     } CMDLISTSTATUS_b;
15685   } ;
15686 
15687   union {
15688     __IOM uint32_t CMDLISTRINGSTOP;             /*!< (@ 0x000000EC) Updates GPU command list pointer to stop executing.        */
15689 
15690     struct {
15691       __IOM uint32_t UPDATEPRT  : 32;           /*!< [31..0] Updates GPU command list pointer to stop executing.               */
15692     } CMDLISTRINGSTOP_b;
15693   } ;
15694 
15695   union {
15696     __IOM uint32_t CMDLISTADDR;                 /*!< (@ 0x000000F0) Command list base pointer.                                 */
15697 
15698     struct {
15699       __IOM uint32_t BASEPTR    : 32;           /*!< [31..0] Command list base pointer.                                        */
15700     } CMDLISTADDR_b;
15701   } ;
15702 
15703   union {
15704     __IOM uint32_t CMDLISTSIZE;                 /*!< (@ 0x000000F4) Command list length in words.                              */
15705 
15706     struct {
15707       __IOM uint32_t LISTWORDS  : 32;           /*!< [31..0] Command list length in words.                                     */
15708     } CMDLISTSIZE_b;
15709   } ;
15710 
15711   union {
15712     __IOM uint32_t INTERRUPTCTRL;               /*!< (@ 0x000000F8) On write, clears the IRQ (CHECK address!).                 */
15713 
15714     struct {
15715       __IOM uint32_t IRQACTIVE  : 1;            /*!< [0..0] if set to zero IRQ is active high, if set to one IRQ
15716                                                      is active low                                                             */
15717       __IOM uint32_t INTCMDEND  : 1;            /*!< [1..1] if set, signals interrupt at the end of command list               */
15718       __IOM uint32_t INTDRAWEND : 1;            /*!< [2..2] if set, signals interrupt at the end of drawing command            */
15719       __IOM uint32_t AUTOCLR    : 1;            /*!< [3..3] if set, auto clears interrupt                                      */
15720       __IOM uint32_t RSVD       : 26;           /*!< [29..4] This bitfield is reserved.                                        */
15721       __IOM uint32_t CHANGEFREQ : 2;            /*!< [31..30] change frequency of asynchronous clock                           */
15722     } INTERRUPTCTRL_b;
15723   } ;
15724 
15725   union {
15726     __IOM uint32_t SYSCLEAR;                    /*!< (@ 0x000000FC) On write, resets the GPU (CHECK address!).                 */
15727 
15728     struct {
15729       __IOM uint32_t RESETGPU   : 32;           /*!< [31..0] On write, resets the GPU (CHECK address!).                        */
15730     } SYSCLEAR_b;
15731   } ;
15732 
15733   union {
15734     __IOM uint32_t DRAWCMD;                     /*!< (@ 0x00000100) Rasterizer drawing command.                                */
15735 
15736     struct {
15737       __IOM uint32_t START      : 3;            /*!< [2..0] Start the draw command                                             */
15738       __IOM uint32_t RSVD       : 29;           /*!< [31..3] This bitfield is reserved.                                        */
15739     } DRAWCMD_b;
15740   } ;
15741 
15742   union {
15743     __IOM uint32_t DRAWPT0;                     /*!< (@ 0x00000104) Stores only integer values. For greater accurancy
15744                                                                     DRAWPT0X and DRAWPT0Y registers are used
15745                                                                     which are 16, 16 fixed point.                              */
15746 
15747     struct {
15748       __IOM uint32_t COORDX     : 16;           /*!< [15..0] vertex 0 X coordinate (integer value)                             */
15749       __IOM uint32_t COORDY     : 16;           /*!< [31..16] vertex 0 Y coordinate (integer value)                            */
15750     } DRAWPT0_b;
15751   } ;
15752 
15753   union {
15754     __IOM uint32_t DRAWPT1;                     /*!< (@ 0x00000108) Stores only integer values. Vertex 1 drawing
15755                                                                     primitive. Stores only integer values. For
15756                                                                     greater accurancy DRAWPT1X and DRAWPT1Y
15757                                                                     registers are used which are 16, 16 fixed
15758                                                                     point.                                                     */
15759 
15760     struct {
15761       __IOM uint32_t COORDX     : 16;           /*!< [15..0] vertex 0 X coordinate (integer value)                             */
15762       __IOM uint32_t COORDY     : 16;           /*!< [31..16] vertex 0 Y coordinate (integer value)                            */
15763     } DRAWPT1_b;
15764   } ;
15765   __IM  uint32_t  RESERVED6;
15766 
15767   union {
15768     __IOM uint32_t CLIPMIN;                     /*!< (@ 0x00000110) Clipping rectangle upper left vertex.                      */
15769 
15770     struct {
15771       __IOM uint32_t COORDX     : 16;           /*!< [15..0] upper left X coordinate                                           */
15772       __IOM uint32_t COORDY     : 16;           /*!< [31..16] upper left Y coordinate                                          */
15773     } CLIPMIN_b;
15774   } ;
15775 
15776   union {
15777     __IOM uint32_t CLIPMAX;                     /*!< (@ 0x00000114) Clipping rectangle bottom right vertex.                    */
15778 
15779     struct {
15780       __IOM uint32_t COORDX     : 16;           /*!< [15..0] bottom right X coordinate                                         */
15781       __IOM uint32_t COORDY     : 16;           /*!< [31..16] bottom right Y coordinate                                        */
15782     } CLIPMAX_b;
15783   } ;
15784 
15785   union {
15786     __IOM uint32_t RASTCTRL;                    /*!< (@ 0x00000118) Rasterizer matrix multiplication control                   */
15787 
15788     struct {
15789       __IOM uint32_t RSVD       : 28;           /*!< [27..0] This bitfield is reserved.                                        */
15790       __IOM uint32_t BYPASS     : 1;            /*!< [28..28] tells module to bypass calculations                              */
15791       __IOM uint32_t ADD        : 1;            /*!< [29..29] adds 0.5 to X and Y                                              */
15792       __IOM uint32_t PERSP      : 2;            /*!< [31..30] when set to 0 is in perspective mode (MISTAKE IN DOC?)           */
15793     } RASTCTRL_b;
15794   } ;
15795 
15796   union {
15797     __IOM uint32_t DRAWCODEPTR;                 /*!< (@ 0x0000011C) DRAWCODEPTR register description needed here.              */
15798 
15799     struct {
15800       __IOM uint32_t FRGND      : 16;           /*!< [15..0] the pointer for the instruction that will be executed
15801                                                      for foreground pixel                                                      */
15802       __IOM uint32_t BKGND      : 16;           /*!< [31..16] the pointer for the instruction that will be executed
15803                                                      for background pixel                                                      */
15804     } DRAWCODEPTR_b;
15805   } ;
15806 
15807   union {
15808     __IOM uint32_t DRAWPT0X;                    /*!< (@ 0x00000120) X coordinate of Vertex 0 drawing primitive 16,
15809                                                                     16 fixed point.                                            */
15810 
15811     struct {
15812       __IOM uint32_t DRAW0X     : 32;           /*!< [31..0] X coordinate                                                      */
15813     } DRAWPT0X_b;
15814   } ;
15815 
15816   union {
15817     __IOM uint32_t DRAWPT0Y;                    /*!< (@ 0x00000124) Y coordinate of Vertex 0 drawing primitive 16,
15818                                                                     16 fixed point.                                            */
15819 
15820     struct {
15821       __IOM uint32_t DRAW0Y     : 32;           /*!< [31..0] Y coordinate                                                      */
15822     } DRAWPT0Y_b;
15823   } ;
15824 
15825   union {
15826     __IOM uint32_t DRAWPT0Z;                    /*!< (@ 0x00000128) DRAWPTOX register description needed here.                 */
15827 
15828     struct {
15829       __IOM uint32_t DRAW0Z     : 32;           /*!< [31..0] This bitfield is reserved.                                        */
15830     } DRAWPT0Z_b;
15831   } ;
15832 
15833   union {
15834     __IOM uint32_t DRAWCOLOR;                   /*!< (@ 0x0000012C) DRAWCOLOR register description needed here.                */
15835 
15836     struct {
15837       __IOM uint32_t RASTPRIM   : 32;           /*!< [31..0] Rasterizer drawing                                                */
15838     } DRAWCOLOR_b;
15839   } ;
15840 
15841   union {
15842     __IOM uint32_t DRAWPT1X;                    /*!< (@ 0x00000130) X coordinate of Vertex 1 drawing primitive 16,
15843                                                                     16 fixed point.                                            */
15844 
15845     struct {
15846       __IOM uint32_t DRAW1X     : 32;           /*!< [31..0] X coordinate                                                      */
15847     } DRAWPT1X_b;
15848   } ;
15849 
15850   union {
15851     __IOM uint32_t DRAWPT1Y;                    /*!< (@ 0x00000134) Y coordinate of Vertex 1 drawing primitive 16,
15852                                                                     16 fixed point.                                            */
15853 
15854     struct {
15855       __IOM uint32_t DRAW1Y     : 32;           /*!< [31..0] Y coordinate                                                      */
15856     } DRAWPT1Y_b;
15857   } ;
15858 
15859   union {
15860     __IOM uint32_t DRAWPT1Z;                    /*!< (@ 0x00000138) DRAWPT1Z register description needed here.                 */
15861 
15862     struct {
15863       __IOM uint32_t DRAW1Z     : 32;           /*!< [31..0] This bitfield is reserved.                                        */
15864     } DRAWPT1Z_b;
15865   } ;
15866   __IM  uint32_t  RESERVED7;
15867 
15868   union {
15869     __IOM uint32_t DRAWPT2X;                    /*!< (@ 0x00000140) X coordinate of Vertex 2 drawing primitive 16,
15870                                                                     16 fixed point.                                            */
15871 
15872     struct {
15873       __IOM uint32_t DRAW2X     : 32;           /*!< [31..0] X coordinate                                                      */
15874     } DRAWPT2X_b;
15875   } ;
15876 
15877   union {
15878     __IOM uint32_t DRAWPT2Y;                    /*!< (@ 0x00000144) Y coordinate of Vertex 2 drawing primitive 16,
15879                                                                     16 fixed point.                                            */
15880 
15881     struct {
15882       __IOM uint32_t DRAW2Y     : 32;           /*!< [31..0] Y coordinate                                                      */
15883     } DRAWPT2Y_b;
15884   } ;
15885 
15886   union {
15887     __IOM uint32_t DRAWPT2Z;                    /*!< (@ 0x00000148) DRAWPT2Z register description needed here.                 */
15888 
15889     struct {
15890       __IOM uint32_t RSVD       : 32;           /*!< [31..0] This bitfield is reserved.                                        */
15891     } DRAWPT2Z_b;
15892   } ;
15893   __IM  uint32_t  RESERVED8;
15894 
15895   union {
15896     __IOM uint32_t DRAWPT3X;                    /*!< (@ 0x00000150) X coordinate of Vertex 3 drawing primitive 16,
15897                                                                     16 fixed point.                                            */
15898 
15899     struct {
15900       __IOM uint32_t DRAW3X     : 32;           /*!< [31..0] X coordinate                                                      */
15901     } DRAWPT3X_b;
15902   } ;
15903 
15904   union {
15905     __IOM uint32_t DRAWPT3Y;                    /*!< (@ 0x00000154) Y coordinate of Vertex 3 drawing primitive 16,
15906                                                                     16 fixed point.                                            */
15907 
15908     struct {
15909       __IOM uint32_t DRAW3Y     : 32;           /*!< [31..0] Y coordinate.                                                     */
15910     } DRAWPT3Y_b;
15911   } ;
15912 
15913   union {
15914     __IOM uint32_t DRAWPT3Z;                    /*!< (@ 0x00000158) Fixed value (not accessible). Registers 0x160-0x180
15915                                                                     are the elements of the 3x3 transformation
15916                                                                     matrix used for homogeneous conversion from
15917                                                                     screen coordinates to texture coordinates;
15918                                                                     the elements are floating points                           */
15919 
15920     struct {
15921       __IOM uint32_t DRAW3Z     : 32;           /*!< [31..0] Fixed value (not accessible)                                      */
15922     } DRAWPT3Z_b;
15923   } ;
15924   __IM  uint32_t  RESERVED9;
15925 
15926   union {
15927     __IOM uint32_t MM00;                        /*!< (@ 0x00000160) matrix floating point element.                             */
15928 
15929     struct {
15930       __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,0). matrix floating point element.                             */
15931     } MM00_b;
15932   } ;
15933 
15934   union {
15935     __IOM uint32_t MM01;                        /*!< (@ 0x00000164) matrix floating point element.                             */
15936 
15937     struct {
15938       __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,1). matrix floating point element.                             */
15939     } MM01_b;
15940   } ;
15941 
15942   union {
15943     __IOM uint32_t MM02;                        /*!< (@ 0x00000168) matrix floating point element; sets to unit matrix
15944                                                                     if previously written element is MM12.                     */
15945 
15946     struct {
15947       __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,2). matrix floating point element.                             */
15948     } MM02_b;
15949   } ;
15950 
15951   union {
15952     __IOM uint32_t MM10;                        /*!< (@ 0x0000016C) matrix floating point element.                             */
15953 
15954     struct {
15955       __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,0). matrix floating point element.                             */
15956     } MM10_b;
15957   } ;
15958 
15959   union {
15960     __IOM uint32_t MM11;                        /*!< (@ 0x00000170) matrix floating point element.                             */
15961 
15962     struct {
15963       __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,1). matrix floating point element                              */
15964     } MM11_b;
15965   } ;
15966 
15967   union {
15968     __IOM uint32_t MM12;                        /*!< (@ 0x00000174) matrix floating point element.                             */
15969 
15970     struct {
15971       __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,2). matrix floating point element.                             */
15972     } MM12_b;
15973   } ;
15974 
15975   union {
15976     __IOM uint32_t MM20;                        /*!< (@ 0x00000178) matrix floating point element.                             */
15977 
15978     struct {
15979       __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,0). matrix floating point element.                             */
15980     } MM20_b;
15981   } ;
15982 
15983   union {
15984     __IOM uint32_t MM21;                        /*!< (@ 0x0000017C) matrix floating point element.                             */
15985 
15986     struct {
15987       __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,1). matrix floating point element.                             */
15988     } MM21_b;
15989   } ;
15990 
15991   union {
15992     __IOM uint32_t MM22;                        /*!< (@ 0x00000180) matrix floating point element.                             */
15993 
15994     struct {
15995       __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,2). matrix floating point element                              */
15996     } MM22_b;
15997   } ;
15998 
15999   union {
16000     __IOM uint32_t DEPTHSTARTL;                 /*!< (@ 0x00000184) Depth value of START pixel, (32 low bits fractional.)      */
16001 
16002     struct {
16003       __IOM uint32_t DEPTH32LO  : 32;           /*!< [31..0] Depth value of START pixel                                        */
16004     } DEPTHSTARTL_b;
16005   } ;
16006 
16007   union {
16008     __IOM uint32_t DEPTHSTARTH;                 /*!< (@ 0x00000188) Depth value of START pixel, (32 high bits integral.)       */
16009 
16010     struct {
16011       __IOM uint32_t DEPTH32HI  : 32;           /*!< [31..0] Depth value of START pixel                                        */
16012     } DEPTHSTARTH_b;
16013   } ;
16014 
16015   union {
16016     __IOM uint32_t DEPTHDXL;                    /*!< (@ 0x0000018C) Added depth value for each step at x-axis (32
16017                                                                     low bits fractional.)                                      */
16018 
16019     struct {
16020       __IOM uint32_t XAXISLO    : 32;           /*!< [31..0] Added depth value for each step at x-axis                         */
16021     } DEPTHDXL_b;
16022   } ;
16023 
16024   union {
16025     __IOM uint32_t DEPTHDXH;                    /*!< (@ 0x00000190) Added depth value for each step at x-axis (32
16026                                                                     high bits integral.)                                       */
16027 
16028     struct {
16029       __IOM uint32_t XAXISHI    : 32;           /*!< [31..0] Added depth value for each step at x-axis                         */
16030     } DEPTHDXH_b;
16031   } ;
16032 
16033   union {
16034     __IOM uint32_t DEPTHDYL;                    /*!< (@ 0x00000194) Added depth value for each step at y-axis (32
16035                                                                     low bits fractional.)                                      */
16036 
16037     struct {
16038       __IOM uint32_t YAXISLO    : 32;           /*!< [31..0] Added depth value for each step at y-axis                         */
16039     } DEPTHDYL_b;
16040   } ;
16041 
16042   union {
16043     __IOM uint32_t DEPTHDYH;                    /*!< (@ 0x00000198) Added depth value for each step at y-axis (32
16044                                                                     high bits integral.)                                       */
16045 
16046     struct {
16047       __IOM uint32_t YAXISHI    : 32;           /*!< [31..0] Added depth value for each step at y-axis                         */
16048     } DEPTHDYH_b;
16049   } ;
16050   __IM  uint32_t  RESERVED10;
16051 
16052   union {
16053     __IOM uint32_t REDX;                        /*!< (@ 0x000001A0) Added red value for each step at x-axis, (16,
16054                                                                     16 fixed point)                                            */
16055 
16056     struct {
16057       __IOM uint32_t REDX       : 32;           /*!< [31..0] Added red value for each step at x-axis                           */
16058     } REDX_b;
16059   } ;
16060 
16061   union {
16062     __IOM uint32_t REDY;                        /*!< (@ 0x000001A4) Added red value for each step at y-axis, (16,
16063                                                                     16 fixed point)                                            */
16064 
16065     struct {
16066       __IOM uint32_t REDY       : 32;           /*!< [31..0] red value for each step at y-axis                                 */
16067     } REDY_b;
16068   } ;
16069 
16070   union {
16071     __IOM uint32_t GREENX;                      /*!< (@ 0x000001A8) Added green value for each step at x-axis, (16,
16072                                                                     16 fixed point)                                            */
16073 
16074     struct {
16075       __IOM uint32_t GREENX     : 32;           /*!< [31..0] Added green value for each step at x-axis                         */
16076     } GREENX_b;
16077   } ;
16078 
16079   union {
16080     __IOM uint32_t GREENY;                      /*!< (@ 0x000001AC) Added green value for each step at y-axis, (16,
16081                                                                     16 fixed point)                                            */
16082 
16083     struct {
16084       __IOM uint32_t GREENY     : 32;           /*!< [31..0] Added green value for each step at y-axis                         */
16085     } GREENY_b;
16086   } ;
16087 
16088   union {
16089     __IOM uint32_t BLUEX;                       /*!< (@ 0x000001B0) Added blue value for each step at x-axis, (16,
16090                                                                     16 fixed point)                                            */
16091 
16092     struct {
16093       __IOM uint32_t BLUEX      : 32;           /*!< [31..0] Added blue value for each step at x-axis                          */
16094     } BLUEX_b;
16095   } ;
16096 
16097   union {
16098     __IOM uint32_t BLUEY;                       /*!< (@ 0x000001B4) Added blue value for each step at y-axis, (16,
16099                                                                     16 fixed point)                                            */
16100 
16101     struct {
16102       __IOM uint32_t BLUEY      : 32;           /*!< [31..0] Added blue value for each step at y-axis                          */
16103     } BLUEY_b;
16104   } ;
16105 
16106   union {
16107     __IOM uint32_t ALFX;                        /*!< (@ 0x000001B8) Added alfa value for each step at x-axis, (16,
16108                                                                     16 fixed point)                                            */
16109 
16110     struct {
16111       __IOM uint32_t ALFX       : 32;           /*!< [31..0] Added alfa value for each step at x-axis                          */
16112     } ALFX_b;
16113   } ;
16114 
16115   union {
16116     __IOM uint32_t ALFY;                        /*!< (@ 0x000001BC) Added alfa value for each step at y-axis, (16,
16117                                                                     16 fixed point)                                            */
16118 
16119     struct {
16120       __IOM uint32_t ALFY       : 32;           /*!< [31..0] Added alfa value for each step at y-axis                          */
16121     } ALFY_b;
16122   } ;
16123 
16124   union {
16125     __IOM uint32_t REDINIT;                     /*!< (@ 0x000001C0) Red value of STARTXY pixel, (16, 16 fixed point)           */
16126 
16127     struct {
16128       __IOM uint32_t REDXY      : 32;           /*!< [31..0] Red value of STARTXY pixel                                        */
16129     } REDINIT_b;
16130   } ;
16131 
16132   union {
16133     __IOM uint32_t GREINIT;                     /*!< (@ 0x000001C4) Green value of STARTXY pixel, (16, 16 fixed point)         */
16134 
16135     struct {
16136       __IOM uint32_t GREENXY    : 32;           /*!< [31..0] Green value of STARTXY pixel                                      */
16137     } GREINIT_b;
16138   } ;
16139 
16140   union {
16141     __IOM uint32_t BLUINIT;                     /*!< (@ 0x000001C8) Blue value of STARTXY pixel, (16, 16 fixed point)          */
16142 
16143     struct {
16144       __IOM uint32_t BLUEXY     : 32;           /*!< [31..0] Blue value of STARTXY pixel                                       */
16145     } BLUINIT_b;
16146   } ;
16147 
16148   union {
16149     __IOM uint32_t ALFINIT;                     /*!< (@ 0x000001CC) Alfa value of STARTXY pixel, (16, 16 fixed point)
16150                                                                     Shader Registers                                           */
16151 
16152     struct {
16153       __IOM uint32_t ALFXY      : 32;           /*!< [31..0] Alfa value of STARTXY pixel                                       */
16154     } ALFINIT_b;
16155   } ;
16156   __IM  uint32_t  RESERVED11[7];
16157 
16158   union {
16159     __IOM uint32_t IDREG;                       /*!< (@ 0x000001EC) Fixed value                                                */
16160 
16161     struct {
16162       __IOM uint32_t GPUID      : 32;           /*!< [31..0] Fixed value for GPU ID                                            */
16163     } IDREG_b;
16164   } ;
16165 
16166   union {
16167     __IOM uint32_t LOADCTRL;                    /*!< (@ 0x000001F0) Load Control                                               */
16168 
16169     struct {
16170       __IOM uint32_t LOADCTRL   : 32;           /*!< [31..0] Load Control                                                      */
16171     } LOADCTRL_b;
16172   } ;
16173   __IM  uint32_t  RESERVED12[3];
16174 
16175   union {
16176     __IOM uint32_t C0REG;                       /*!< (@ 0x00000200) Shader constant register 0.                                */
16177 
16178     struct {
16179       __IOM uint32_t C0SHADER   : 32;           /*!< [31..0] Shader constant register 0.                                       */
16180     } C0REG_b;
16181   } ;
16182 
16183   union {
16184     __IOM uint32_t C1REG;                       /*!< (@ 0x00000204) Shader constant register 1.                                */
16185 
16186     struct {
16187       __IOM uint32_t C1SHADER   : 32;           /*!< [31..0] Shader constant register 1.                                       */
16188     } C1REG_b;
16189   } ;
16190 
16191   union {
16192     __IOM uint32_t C2REG;                       /*!< (@ 0x00000208) Shader constant register 2.                                */
16193 
16194     struct {
16195       __IOM uint32_t C2SHADER   : 32;           /*!< [31..0] Shader constant register 2                                        */
16196     } C2REG_b;
16197   } ;
16198 
16199   union {
16200     __IOM uint32_t C3REG;                       /*!< (@ 0x0000020C) Shader constant register 3, the dirty Region
16201                                                                     Register                                                   */
16202 
16203     struct {
16204       __IOM uint32_t C3SHADER   : 32;           /*!< [31..0] Shader constant register 3                                        */
16205     } C3REG_b;
16206   } ;
16207   __IM  uint32_t  RESERVED13[888];
16208 
16209   union {
16210     __IOM uint32_t IRQID;                       /*!< (@ 0x00000FF0) Signals interrupt when set (CHECK address!).               */
16211 
16212     struct {
16213       __IOM uint32_t IRQID      : 32;           /*!< [31..0] Signals interrupt when set (CHECK address!                        */
16214     } IRQID_b;
16215   } ;
16216 } GPU_Type;                                     /*!< Size = 4084 (0xff4)                                                       */
16217 
16218 
16219 
16220 /* =========================================================================================================================== */
16221 /* ================                                           I2S0                                            ================ */
16222 /* =========================================================================================================================== */
16223 
16224 
16225 /**
16226   * @brief I2S ASRC Master/Slave Module (I2S0)
16227   */
16228 
16229 typedef struct {                                /*!< (@ 0x40208000) I2S0 Structure                                             */
16230 
16231   union {
16232     __IOM uint32_t RXDATA;                      /*!< (@ 0x00000000) Read only access to the i2S receive data                   */
16233 
16234     struct {
16235       __IOM uint32_t RXSAMPLE   : 32;           /*!< [31..0] 32b audio sample from the internal receive FIFO. MSB
16236                                                      is always in bit 31                                                       */
16237     } RXDATA_b;
16238   } ;
16239 
16240   union {
16241     __IOM uint32_t RXCHANID;                    /*!< (@ 0x00000004) Read only received channel identification register         */
16242 
16243     struct {
16244       __IOM uint32_t RXCHANID   : 8;            /*!< [7..0] Channel ID value 0-255.                                            */
16245             uint32_t            : 24;
16246     } RXCHANID_b;
16247   } ;
16248 
16249   union {
16250     __IOM uint32_t RXFIFOSTATUS;                /*!< (@ 0x00000008) Holds the number of samples currently in the
16251                                                                     receive FIFO, and the empty condition flag                 */
16252 
16253     struct {
16254       __IOM uint32_t RXSAMPLECNT : 28;          /*!< [27..0] The count of the number of samples currently in the
16255                                                      receive FIFO.                                                             */
16256       __IOM uint32_t RXEMPTY    : 1;            /*!< [28..28] Receive FIFO empty bit. a 1 indicates the receive FIFO
16257                                                      is empty.                                                                 */
16258             uint32_t            : 3;
16259     } RXFIFOSTATUS_b;
16260   } ;
16261 
16262   union {
16263     __IOM uint32_t RXFIFOSIZE;                  /*!< (@ 0x0000000C) Holds the size of the receive FIFO in samples              */
16264 
16265     struct {
16266       __IOM uint32_t SIZE       : 32;           /*!< [31..0] Size of the receive FIFO in units of i2S samples. Read
16267                                                      only value.                                                               */
16268     } RXFIFOSIZE_b;
16269   } ;
16270 
16271   union {
16272     __IOM uint32_t RXUPPERLIMIT;                /*!< (@ 0x00000010) The number of samples required to be in the RX
16273                                                                     FIFO before asserting the RX_FFi interrupt
16274                                                                     bit                                                        */
16275 
16276     struct {
16277       __IOM uint32_t SIZE       : 32;           /*!< [31..0] When the I2S sample count stored within the receive
16278                                                      FIFO reaches this value or is larger, the interrupt RX_FFi
16279                                                      bit is asserted.                                                          */
16280     } RXUPPERLIMIT_b;
16281   } ;
16282   __IM  uint32_t  RESERVED[3];
16283 
16284   union {
16285     __IOM uint32_t TXDATA;                      /*!< (@ 0x00000020) Write only register to hold the i2S sample to
16286                                                                     transmit via the write FIFO                                */
16287 
16288     struct {
16289       __IOM uint32_t TXSAMPLE   : 32;           /*!< [31..0] 32b I2S sample to send out of the I2S module via the
16290                                                      external pins. All sample have the MSB in bit 31 regardless
16291                                                      of number of bits per sample and data justification                       */
16292     } TXDATA_b;
16293   } ;
16294 
16295   union {
16296     __IOM uint32_t TXCHANID;                    /*!< (@ 0x00000024) Channel ID used for the next audio sample to
16297                                                                     be written to the data transmission register               */
16298 
16299     struct {
16300       __IOM uint32_t TXCHANID   : 8;            /*!< [7..0] Channel ID value 0-255.                                            */
16301             uint32_t            : 24;
16302     } TXCHANID_b;
16303   } ;
16304 
16305   union {
16306     __IOM uint32_t TXFIFOSTATUS;                /*!< (@ 0x00000028) Holds the number of samples currently in the
16307                                                                     transmit FIFO, and the full condition flag                 */
16308 
16309     struct {
16310       __IOM uint32_t TXFIFOCNT  : 28;           /*!< [27..0] The count of the number of samples currently in the
16311                                                      transmit FIFO.                                                            */
16312       __IOM uint32_t TXFIFOFULL : 1;            /*!< [28..28] Transmit FIFO full bit. a 1 indicates the transmit
16313                                                      FIFO is full.                                                             */
16314             uint32_t            : 3;
16315     } TXFIFOSTATUS_b;
16316   } ;
16317 
16318   union {
16319     __IOM uint32_t TXFIFOSIZE;                  /*!< (@ 0x0000002C) Holds the size of the transmit FIFO in samples             */
16320 
16321     struct {
16322       __IOM uint32_t SIZE       : 32;           /*!< [31..0] Size of the transmit FIFO in units of I2S samples. Read
16323                                                      only value.                                                               */
16324     } TXFIFOSIZE_b;
16325   } ;
16326 
16327   union {
16328     __IOM uint32_t TXLOWERLIMIT;                /*!< (@ 0x00000030) Minimum number of samples have been reached in
16329                                                                     the transmit FIFO.                                         */
16330 
16331     struct {
16332       __IOM uint32_t SIZE       : 32;           /*!< [31..0] When the number of sample in the TX FIFO goes below
16333                                                      this value, the interrupt TX_FFi bit is asserted.                         */
16334     } TXLOWERLIMIT_b;
16335   } ;
16336   __IM  uint32_t  RESERVED1[3];
16337 
16338   union {
16339     __IOM uint32_t I2SDATACFG;                  /*!< (@ 0x00000040) Specifies the data format of I2S sub frames                */
16340 
16341     struct {
16342       __IOM uint32_t SSZ1       : 3;            /*!< [2..0] Receive audio sample length for phase 1. 0: 8b, 2: 16b,
16343                                                      4: 24b, 5: 32b, 1,3,6,7: Reserved                                         */
16344       __IOM uint32_t JUST       : 1;            /*!< [3..3] Audio sample justification. 0: Left-justified, 1: Right-justified  */
16345             uint32_t            : 1;
16346       __IOM uint32_t WDLEN1     : 3;            /*!< [7..5] Receive channel length in bits for phase 1. 0: 8b, 2:
16347                                                      16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                    */
16348       __IOM uint32_t FRLEN1     : 7;            /*!< [14..8] Number of channels in phase 1; 0: 1 Channel in phase
16349                                                      2, .. 0x7: 8 channels in phase 1                                          */
16350             uint32_t            : 1;
16351       __IOM uint32_t SSZ2       : 3;            /*!< [18..16] Receive audio sample length for phase 2. 0: 8b, 2:
16352                                                      16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                    */
16353       __IOM uint32_t DATADLY    : 2;            /*!< [20..19] Receive data delay bit count. Valid values are 0-2,
16354                                                      3 is reserved.                                                            */
16355       __IOM uint32_t WDLEN2     : 3;            /*!< [23..21] Receive channel length in bits for phase 2. 0: 8b,
16356                                                      2: 16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                 */
16357       __IOM uint32_t FRLEN2     : 7;            /*!< [30..24] Number of channels in phase 2; 0: 1 Channel in phase
16358                                                      2, .. 0x7: 8 channels in phase 2                                          */
16359       __IOM uint32_t PH         : 1;            /*!< [31..31] Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase
16360                                                      frame.                                                                    */
16361     } I2SDATACFG_b;
16362   } ;
16363 
16364   union {
16365     __IOM uint32_t I2SIOCFG;                    /*!< (@ 0x00000044) Specified polarity and clock configuration of
16366                                                                     the I2S IPB clocks and IO signals                          */
16367 
16368     struct {
16369       __IOM uint32_t OEN        : 1;            /*!< [0..0] Output enable for SDATA output                                     */
16370             uint32_t            : 3;
16371       __IOM uint32_t FPER       : 12;           /*!< [15..4] Frame period in units of sclk. Period is FPER + 1 sclks
16372                                                      in length. 0: 1 sclk, 0x3F: 64 sclks                                      */
16373       __IOM uint32_t FSP        : 1;            /*!< [16..16] Polarity of fsync/lr_clk signal. 0: Active high. 1:
16374                                                      Active low                                                                */
16375       __IOM uint32_t PRTX       : 1;            /*!< [17..17] Transmit clock edge polarity bit. 0: sdata is transmitted
16376                                                      starting from the falling edge of sclk. 1: sdata is transmitted
16377                                                      starting from the rising edge of sclk.                                    */
16378       __IOM uint32_t MSL        : 1;            /*!< [18..18] Master/Slave clock configuration. 0: External clock(sclk
16379                                                      and lr_clk provided externally). 1: Internal clock (sclk
16380                                                      and lr_clk sourced internally).                                           */
16381       __IOM uint32_t PRx        : 1;            /*!< [19..19] Receive clock edge polarity bit. 0: sdata is sampled
16382                                                      on the rising edge of sclk. 1: sdata is sampled on the
16383                                                      falling edge of sclk.                                                     */
16384       __IOM uint32_t FWID       : 8;            /*!< [27..20] period of fsync/lr_clk in units of sclks                         */
16385             uint32_t            : 4;
16386     } I2SIOCFG_b;
16387   } ;
16388 
16389   union {
16390     __IOM uint32_t I2SCTL;                      /*!< (@ 0x00000048) Specified polarity and clock configuration of
16391                                                                     the I2S IPB clocks and IO signals                          */
16392 
16393     struct {
16394       __IOM uint32_t TXEN       : 1;            /*!< [0..0] Transmit enable signal. 1 will enable the transmission
16395                                                      of serial audio. For Full duplex operation, RXEN and TXEN
16396                                                      MUST be set in a single register write access, or the Slave
16397                                                      FSM may ignore one of the bit-field read-modify-write accesses.
16398                                                      TXRST and RXRST must be cleared in advance.                               */
16399       __IOM uint32_t TXRST      : 1;            /*!< [1..1] Transmit reset signal. 1 will reset the TX side registers
16400                                                      and flush the TX FIFO.                                                    */
16401             uint32_t            : 2;
16402       __IOM uint32_t RXEN       : 1;            /*!< [4..4] Receive enable control. 1: Enables capture of serial
16403                                                      audio, starting with first channel. 0: No receive data
16404                                                      captured. For Full duplex operation, RXEN and TXEN MUST
16405                                                      be set in a single register write access, or the Slave
16406                                                      FSM may ignore one of the bit-field read-modify-write accesses.
16407                                                      TXRST and RXRST must be cleared in advance.                               */
16408       __IOM uint32_t RXRST      : 1;            /*!< [5..5] Active high receiver reset signal. 1: Flush the RX FIFO            */
16409             uint32_t            : 25;
16410       __IOM uint32_t I2SVAL     : 1;            /*!< [31..31] I2S validity bit mode. 1: RX data stored only when
16411                                                      validity mask condition is asserted. 0: No validity mask
16412                                                      conditions checking is done.                                              */
16413     } I2SCTL_b;
16414   } ;
16415 
16416   union {
16417     __IOM uint32_t IPBIRPT;                     /*!< (@ 0x0000004C) Additional mask and status registers for the
16418                                                                     IPB core.                                                  */
16419 
16420     struct {
16421       __IOM uint32_t RXFFM      : 1;            /*!< [0..0] Receive FIFO interrupt mask. Will assert interrupt when
16422                                                      = 1 and RXFFI is asserted                                                 */
16423       __IOM uint32_t TXFFM      : 1;            /*!< [1..1] Transmit FIFO interrupt mask. Will assert interrupt when
16424                                                      = 1 and TXFFI is asserted                                                 */
16425       __IOM uint32_t RXFM       : 1;            /*!< [2..2] Receive FIFO interrupt mask. Will assert interrupt when
16426                                                      = 1 and RXFI is asserted                                                  */
16427       __IOM uint32_t TXEM       : 1;            /*!< [3..3] Transmit FIFO interrupt mask. Will assert interrupt when
16428                                                      = 1 and TXEI is asserted                                                  */
16429       __IOM uint32_t RXDMAM     : 1;            /*!< [4..4] Receive FIFO interrupt mask. Will assert interrupt when
16430                                                      = 1 and cimdmareq_rx is asserted                                          */
16431       __IOM uint32_t TXDMAM     : 1;            /*!< [5..5] Transmit FIFO interrupt mask. Will assert interrupt when
16432                                                      = 1 and cimdmareq_tx is asserted                                          */
16433             uint32_t            : 10;
16434       __IOM uint32_t RXFFI      : 1;            /*!< [16..16] Receive fifo high limit interrupt                                */
16435       __IOM uint32_t TXFFI      : 1;            /*!< [17..17] Transmit fifo low limit interrupt                                */
16436       __IOM uint32_t RXFI       : 1;            /*!< [18..18] RX Full interrupt. RX unit attempted to write to a
16437                                                      full FIFO                                                                 */
16438       __IOM uint32_t TXEI       : 1;            /*!< [19..19] TX Empty interrupt. TX unit attempted to read an empty
16439                                                      FIFO                                                                      */
16440       __IOM uint32_t RXDMAI     : 1;            /*!< [20..20] RX dma interrupt                                                 */
16441       __IOM uint32_t TXDMAI     : 1;            /*!< [21..21] TX dma interrupt                                                 */
16442             uint32_t            : 10;
16443     } IPBIRPT_b;
16444   } ;
16445 
16446   union {
16447     __IOM uint32_t IPCOREID;                    /*!< (@ 0x00000050) Returns the core ID of the IPB core, and used
16448                                                                     to write the I2S validity mask.                            */
16449 
16450     struct {
16451             uint32_t            : 16;
16452       __IOM uint32_t COREID     : 8;            /*!< [23..16] Core ID of the IPB core                                          */
16453       __IOM uint32_t COREFAM    : 8;            /*!< [31..24] Core Family. Also bit 31 is used to set the I2S validity
16454                                                      bit when a write is done.                                                 */
16455     } IPCOREID_b;
16456   } ;
16457 
16458   union {
16459     __IOM uint32_t AMQCFG;                      /*!< (@ 0x00000054) Control the enablement of the ASRC module and
16460                                                                     the source of the MCLK used in the IPB core.               */
16461 
16462     struct {
16463       __IOM uint32_t MCLKSRC    : 1;            /*!< [0..0] MCLK source. 1: Output of nco_clk divider. 0: MCLK from
16464                                                      ambiq clock configuration directly                                        */
16465       __IOM uint32_t ASRCEN     : 1;            /*!< [1..1] ASRC sub module enable. 0: Enabled. 1: Disabled/Bypassed           */
16466             uint32_t            : 30;
16467     } AMQCFG_b;
16468   } ;
16469   __IM  uint32_t  RESERVED2[2];
16470 
16471   union {
16472     __IOM uint32_t INTDIV;                      /*!< (@ 0x00000060) Integer divide value for the nco_clk divider               */
16473 
16474     struct {
16475       __IOM uint32_t INTDIV     : 32;           /*!< [31..0] Integer divide value for internal clock divider                   */
16476     } INTDIV_b;
16477   } ;
16478 
16479   union {
16480     __IOM uint32_t FRACDIV;                     /*!< (@ 0x00000064) Fractional divide value for the nco_clk divider            */
16481 
16482     struct {
16483       __IOM uint32_t FRACDIV    : 32;           /*!< [31..0] Fractional divide value for internal clock divider                */
16484     } FRACDIV_b;
16485   } ;
16486   __IM  uint32_t  RESERVED3[38];
16487 
16488   union {
16489     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000100) Provides clock selection and control for I2S
16490                                                                     clocks                                                     */
16491 
16492     struct {
16493       __IOM uint32_t MCLKEN     : 1;            /*!< [0..0] Enable for the master audio clock.                                 */
16494             uint32_t            : 3;
16495       __IOM uint32_t FSEL       : 5;            /*!< [8..4] Select the input clock frequency for the MCLK.Whenever
16496                                                      changing the clock source here, the MISC_HFRC2FRC bit in
16497                                                      the CLKGEN module must first be set. The sequence for changing
16498                                                      the clock source regardless of clock selection is to first
16499                                                      force HFRC2 on by setting the CLKGEN_MISC_HFRC2FRC bit,
16500                                                      select the clock source in this field, clear the CLKGEN_MISC_HFRC2FRC
16501                                                      bit only if HFRC2 is NOT selected, and then engage the
16502                                                      peripheral.If HFRC2 is the clock source, then shutting
16503                                                      the module down cleanly requires switchin                                 */
16504             uint32_t            : 3;
16505       __IOM uint32_t REFCLKEN   : 1;            /*!< [12..12] FUTURE USE Enable for the reference clock                        */
16506             uint32_t            : 3;
16507       __IOM uint32_t REFFSEL    : 2;            /*!< [17..16] FUTURE USE Select the input clock frequency for the
16508                                                      ref_clk. 0: HFRC_48MHz 1: HFRC_48MHz_GATED 2: XT_24MHz
16509                                                      3: HFRC2_48MHz                                                            */
16510             uint32_t            : 2;
16511       __IOM uint32_t DIV3       : 1;            /*!< [20..20] 0: no change to the clock selected by FSEL 1: frequency
16512                                                      divide-by-3 of the clock selected by FSEL                                 */
16513             uint32_t            : 11;
16514     } CLKCFG_b;
16515   } ;
16516   __IM  uint32_t  RESERVED4[63];
16517 
16518   union {
16519     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000200) Configuration control of the DMA process, including
16520                                                                     the direction of DMA, and enablement of
16521                                                                     DMA                                                        */
16522 
16523     struct {
16524       __IOM uint32_t RXDMAEN    : 1;            /*!< [0..0] DMA Enable for RX channel. Setting this bit to EN will
16525                                                      start the DMA operation. This should be the last DMA related
16526                                                      register set prior to issuing the command                                 */
16527       __IOM uint32_t RXDMAPRI   : 1;            /*!< [1..1] Sets the Priority of the RXDMA request                             */
16528             uint32_t            : 2;
16529       __IOM uint32_t TXDMAEN    : 1;            /*!< [4..4] DMA Enable for TX channel. Setting this bit to EN will
16530                                                      start the DMA operation. This should be the last DMA related
16531                                                      register set prior to issuing the command                                 */
16532       __IOM uint32_t TXDMAPRI   : 1;            /*!< [5..5] Sets the Priority of the TXDMA request                             */
16533             uint32_t            : 2;
16534       __IOM uint32_t TXREQCNT   : 8;            /*!< [15..8] Number of blocks of samples transferred before asserting
16535                                                      the TXREQCNT interrupt signal. A block is 8 samples. The
16536                                                      interrupt will assert if enabled and after TXREQCNT blocks
16537                                                      of data has been transferred to the I2S module from the
16538                                                      device. A value of 0 will cause the assertion of the interrupt
16539                                                      for every block of transfer done.                                         */
16540       __IOM uint32_t RXREQCNT   : 8;            /*!< [23..16] Number of blocks of samples transferred before asserting
16541                                                      the RXREQCNT interrupt signal. A block is 8 samples. The
16542                                                      interrupt will assert if enabled and after RXREQCNT blocks
16543                                                      of data has been transferred from the I2S into the device.
16544                                                      A value of 0 will cause the assertion of the interrupt
16545                                                      for every block of transfer done.                                         */
16546             uint32_t            : 8;
16547     } DMACFG_b;
16548   } ;
16549 
16550   union {
16551     __IOM uint32_t RXDMATOTCNT;                 /*!< (@ 0x00000204) Contains the total count of samples to be stored
16552                                                                     for the current RX DMA operation. This register
16553                                                                     is updated as DMA beats complete.                          */
16554 
16555     struct {
16556       __IOM uint32_t RXTOTCNT   : 12;           /*!< [11..0] Number of 32b audio samples to transfer for RX DMA.               */
16557             uint32_t            : 20;
16558     } RXDMATOTCNT_b;
16559   } ;
16560 
16561   union {
16562     __IOM uint32_t RXDMAADDR;                   /*!< (@ 0x00000208) The address which the DMA operation will store
16563                                                                     the incoming audio samples. This address
16564                                                                     is updated as the samples are stored.                      */
16565 
16566     struct {
16567       __IOM uint32_t RXTARGADDR : 32;           /*!< [31..0] Address bits of the target byte address for source of
16568                                                      RX write DMA.                                                             */
16569     } RXDMAADDR_b;
16570   } ;
16571 
16572   union {
16573     __IOM uint32_t RXDMASTAT;                   /*!< (@ 0x0000020C) Status of the RX DMA operation currently in progress.      */
16574 
16575     struct {
16576       __IOM uint32_t RXDMATIP   : 1;            /*!< [0..0] RX DMA Transfer In Progress indicator. 1 will indicate
16577                                                      that a DMA transfer is active. The DMA transfer may be
16578                                                      waiting on data, transferring data, or waiting for priority.All
16579                                                      of these will be indicated with a 1. A 0 will indicate
16580                                                      that the DMA is fully complete and no further transactions
16581                                                      will be done. This bit is read only.                                      */
16582       __IOM uint32_t RXDMACPL   : 1;            /*!< [1..1] RX DMA Transfer Complete. This signals the end of the
16583                                                      DMA operation. This bit can be cleared by writing to 0,
16584                                                      and will also be cleared when a new DMA is started.                       */
16585       __IOM uint32_t RXDMAERR   : 1;            /*!< [2..2] RX DMA Error. This active high bit signals an error was
16586                                                      encountered during the DMA operation. The bit can be cleared
16587                                                      by writing to 0. Once set, this bit will remain set until
16588                                                      cleared by software.                                                      */
16589             uint32_t            : 29;
16590     } RXDMASTAT_b;
16591   } ;
16592 
16593   union {
16594     __IOM uint32_t TXDMATOTCNT;                 /*!< (@ 0x00000210) Contains the total count of samples to be read
16595                                                                     and transmitted for the current TX DMA operation.
16596                                                                     This register is updated as DMA beats complete.            */
16597 
16598     struct {
16599       __IOM uint32_t TXTOTCNT   : 12;           /*!< [11..0] Number of 32b audio samples to transmit                           */
16600             uint32_t            : 20;
16601     } TXDMATOTCNT_b;
16602   } ;
16603 
16604   union {
16605     __IOM uint32_t TXDMAADDR;                   /*!< (@ 0x00000214) The address which the DMA operation will fetch
16606                                                                     the audio samples. This address is updated
16607                                                                     as the samples are stored.                                 */
16608 
16609     struct {
16610       __IOM uint32_t TXTARGADDR : 32;           /*!< [31..0] Address bits of the target byte address for source of
16611                                                      TX write DMA.                                                             */
16612     } TXDMAADDR_b;
16613   } ;
16614 
16615   union {
16616     __IOM uint32_t TXDMASTAT;                   /*!< (@ 0x00000218) Status of the TX DMA operation currently in progress.      */
16617 
16618     struct {
16619       __IOM uint32_t TXDMATIP   : 1;            /*!< [0..0] TX DMA Transfer In Progress indicator. 1 will indicate
16620                                                      that a DMA transfer is active. The DMA transfer may be
16621                                                      waiting on data, transferring data, or waiting for priority.All
16622                                                      of these will be indicated with a 1. A 0 will indicate
16623                                                      that the DMA is fully complete and no further transactions
16624                                                      will be done. This bit is read only.                                      */
16625       __IOM uint32_t TXDMACPL   : 1;            /*!< [1..1] TX DMA Transfer Complete. This signals the end of the
16626                                                      DMA operation. This bit can be cleared by writing to 0,
16627                                                      and will also be cleared when a new DMA is started.                       */
16628       __IOM uint32_t TXDMAERR   : 1;            /*!< [2..2] TX DMA Error. This active high bit signals an error was
16629                                                      encountered during the DMA operation. The bit can be cleared
16630                                                      by writing to 0. Once set, this bit will remain set until
16631                                                      cleared by software.                                                      */
16632             uint32_t            : 29;
16633     } TXDMASTAT_b;
16634   } ;
16635   __IM  uint32_t  RESERVED5[5];
16636 
16637   union {
16638     __IOM uint32_t STATUS;                      /*!< (@ 0x00000230) I2S Module Status                                          */
16639 
16640     struct {
16641       __IOM uint32_t TBD        : 1;            /*!< [0..0] To Be determined.                                                  */
16642             uint32_t            : 31;
16643     } STATUS_b;
16644   } ;
16645   __IM  uint32_t  RESERVED6[51];
16646 
16647   union {
16648     __IOM uint32_t INTEN;                       /*!< (@ 0x00000300) Set bits in this register to allow this module
16649                                                                     to generate the corresponding interrupt.                   */
16650 
16651     struct {
16652       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16653       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16654                                                      of size 8 samples. This interrupt allows servicing of buffers
16655                                                      at a programmable location within the overall DMA transfer.               */
16656       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16657                                                      on TX fifo level.                                                         */
16658       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16659       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16660             uint32_t            : 27;
16661     } INTEN_b;
16662   } ;
16663 
16664   union {
16665     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000304) Read bits from this register to discover the
16666                                                                     cause of a recent interrupt.                               */
16667 
16668     struct {
16669       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16670       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16671                                                      of size 8 samples. This interrupt allows servicing of buffers
16672                                                      at a programmable location within the overall DMA transfer.               */
16673       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16674                                                      on TX fifo level.                                                         */
16675       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16676       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16677             uint32_t            : 27;
16678     } INTSTAT_b;
16679   } ;
16680 
16681   union {
16682     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
16683                                                                     the interrupt status associated with that
16684                                                                     bit.                                                       */
16685 
16686     struct {
16687       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16688       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16689                                                      of size 8 samples. This interrupt allows servicing of buffers
16690                                                      at a programmable location within the overall DMA transfer.               */
16691       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16692                                                      on TX fifo level.                                                         */
16693       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16694       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16695             uint32_t            : 27;
16696     } INTCLR_b;
16697   } ;
16698 
16699   union {
16700     __IOM uint32_t INTSET;                      /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
16701                                                                     generate an interrupt from this module.
16702                                                                     (Generally used for testing purposes).                     */
16703 
16704     struct {
16705       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16706       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16707                                                      of size 8 samples. This interrupt allows servicing of buffers
16708                                                      at a programmable location within the overall DMA transfer.               */
16709       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16710                                                      on TX fifo level.                                                         */
16711       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16712       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16713             uint32_t            : 27;
16714     } INTSET_b;
16715   } ;
16716   __IM  uint32_t  RESERVED7[60];
16717 
16718   union {
16719     __IOM uint32_t I2SDBG;                      /*!< (@ 0x00000400) Debug control                                              */
16720 
16721     struct {
16722       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
16723                                                      within this register, otherwise it is clock gated for power
16724                                                      savings                                                                   */
16725       __IOM uint32_t MCLKON     : 1;            /*!< [1..1] MCLK debug clock control. Enable MCLK to be active when
16726                                                      this bit is '1'. Otherwise, the clock is controlled with
16727                                                      gating from the logic as needed.                                          */
16728       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
16729                                                      when this bit is '1'. Otherwise, the clock is controlled
16730                                                      with gating from the logic as needed.                                     */
16731       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
16732                                                      to select between different debug data available in the
16733                                                      DBG0 and DBG1 registers.                                                  */
16734     } I2SDBG_b;
16735   } ;
16736 } I2S0_Type;                                    /*!< Size = 1028 (0x404)                                                       */
16737 
16738 
16739 
16740 /* =========================================================================================================================== */
16741 /* ================                                           IOM0                                            ================ */
16742 /* =========================================================================================================================== */
16743 
16744 
16745 /**
16746   * @brief IO Peripheral Master (IOM0)
16747   */
16748 
16749 typedef struct {                                /*!< (@ 0x40050000) IOM0 Structure                                             */
16750 
16751   union {
16752     __IOM uint32_t FIFO;                        /*!< (@ 0x00000000) Provides direct random access to both input and
16753                                                                     output fifos. The state of the FIFO is not
16754                                                                     distured by reading these locations (ie
16755                                                                     no POP will be done). FIFO0 is accessible
16756                                                                     from addresses 0x0 - 0x1C, and is used for
16757                                                                     data outuput from the IOM to external devices.
16758                                                                     These FIFO locations can be read and written
16759                                                                     directly.FIFO locations 0x20 - 0x3C provide
16760                                                                     read only access to the input fifo. These
16761                                                                     FIFO locations cannot be directly written
16762                                                                     by the MCU, and are updated only by the
16763                                                                     internal hardware.                                         */
16764 
16765     struct {
16766       __IOM uint32_t FIFO       : 32;           /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
16767                                                      valid information.                                                        */
16768     } FIFO_b;
16769   } ;
16770   __IM  uint32_t  RESERVED[63];
16771 
16772   union {
16773     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Provides the current valid byte count of data
16774                                                                     within the FIFO as seen from the internal
16775                                                                     state machines. FIFO0 is dedicated to outgoing
16776                                                                     transactions and FIFO1 is dedicated to incoming
16777                                                                     transactions. All counts are specified in
16778                                                                     units of bytes.                                            */
16779 
16780     struct {
16781       __IOM uint32_t FIFO0SIZ   : 8;            /*!< [7..0] The number of valid data bytes currently in the FIFO
16782                                                      0 (written by MCU, read by interface)                                     */
16783       __IOM uint32_t FIFO0REM   : 8;            /*!< [15..8] The number of remaining data bytes slots currently in
16784                                                      FIFO 0 (written by MCU, read by interface)                                */
16785       __IOM uint32_t FIFO1SIZ   : 8;            /*!< [23..16] The number of valid data bytes currently in FIFO 1
16786                                                      (written by interface, read by MCU)                                       */
16787       __IOM uint32_t FIFO1REM   : 8;            /*!< [31..24] The number of remaining data bytes slots currently
16788                                                      in FIFO 1 (written by interface, read by MCU)                             */
16789     } FIFOPTR_b;
16790   } ;
16791 
16792   union {
16793     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
16794                                                                     transactions. The threshold values are used
16795                                                                     to assert the interrupt if enabled, and
16796                                                                     also used during DMA to set the transfer
16797                                                                     size as a result of DMATHR trigger.The WTHR
16798                                                                     is used to indicate when there are more
16799                                                                     than WTHR bytes of open fifo locations available
16800                                                                     in the outgoing FIFO (FIFO0). The intended
16801                                                                     use to invoke an interrupt or DMA transfer
16802                                                                     that will refill the FIFO with a byte count
16803                                                                     up to this value.The RTHR is used to indicate
16804                                                                     when t                                                     */
16805 
16806     struct {
16807       __IOM uint32_t FIFORTHR   : 6;            /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
16808                                                      the read FIFO level from activating the threshold interrupt.
16809                                                      If this field is non-zero, it will trigger a threshold
16810                                                      interrupt when the read fifo contains FIFORTHR valid bytes
16811                                                      of data, as indicated by the FIFO1SIZ field. This is intended
16812                                                      to signal when a data transfer of FIFORTHR bytes can be
16813                                                      done from the IOM module to the host via the read fifo
16814                                                      to support large IOM read operations.                                     */
16815             uint32_t            : 2;
16816       __IOM uint32_t FIFOWTHR   : 6;            /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
16817                                                      the write FIFO level from activating the threshold interrupt.
16818                                                      If this field is non-zero, it will trigger a threshold
16819                                                      interrupt when the write fifo contains FIFOWTHR free bytes,
16820                                                      as indicated by the FIFO0REM field. This is intended to
16821                                                      signal when a transfer of FIFOWTHR bytes can be done from
16822                                                      the host to the IOM write fifo to support large IOM write
16823                                                      operations.                                                               */
16824             uint32_t            : 18;
16825     } FIFOTHR_b;
16826   } ;
16827 
16828   union {
16829     __IOM uint32_t FIFOPOP;                     /*!< (@ 0x00000108) Will advance the internal read pointer of the
16830                                                                     incoming FIFO (FIFO1) when read, if POPWR
16831                                                                     is not active. If POPWR is active, a write
16832                                                                     to this register is needed to advance the
16833                                                                     internal FIFO pointer.                                     */
16834 
16835     struct {
16836       __IOM uint32_t FIFODOUT   : 32;           /*!< [31..0] This register will return the read data indicated by
16837                                                      the current read pointer on reads. If the POPWR control
16838                                                      bit in the FIFOCTRL register is reset (0), the fifo read
16839                                                      pointer will be advanced by one word as a result of the
16840                                                      read.If the POPWR bit is set (1), the fifo read pointer
16841                                                      will only be advanced after a write operation to this register.
16842                                                      The write data is ignored for this register.If less than
16843                                                      a even word multiple is available, and the command is completed,
16844                                                      the module will return the word containing                                */
16845     } FIFOPOP_b;
16846   } ;
16847 
16848   union {
16849     __IOM uint32_t FIFOPUSH;                    /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
16850                                                                     advance the internal write pointer.                        */
16851 
16852     struct {
16853       __IOM uint32_t FIFODIN    : 32;           /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
16854                                                      and will cause a push event to occur to the next open slot
16855                                                      within the FIFORAM. Writing to this register will cause
16856                                                      the write point to increment by 1 word(4 bytes).                          */
16857     } FIFOPUSH_b;
16858   } ;
16859 
16860   union {
16861     __IOM uint32_t FIFOCTRL;                    /*!< (@ 0x00000110) Provides controls for the operation of the internal
16862                                                                     FIFOs. Contains fields used to control the
16863                                                                     operation of the POP register, and also
16864                                                                     controls to reset the internal pointers
16865                                                                     of the FIFOs.                                              */
16866 
16867     struct {
16868       __IOM uint32_t POPWR      : 1;            /*!< [0..0] Selects the mode in which 'pop' events are done for the
16869                                                      fifo read operations. A value of '1' will prevent a pop
16870                                                      event on a read operation, and will require a write to
16871                                                      the FIFOPOP register to create a pop event.A value of '0'
16872                                                      in this register will allow a pop event to occur on the
16873                                                      read of the FIFOPOP register, and may cause inadvertant
16874                                                      fifo pops when used in a debugging mode.                                  */
16875       __IOM uint32_t FIFORSTN   : 1;            /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset
16876                                                      fifo, and then write to 1 to remove the reset.                            */
16877             uint32_t            : 30;
16878     } FIFOCTRL_b;
16879   } ;
16880 
16881   union {
16882     __IOM uint32_t FIFOLOC;                     /*!< (@ 0x00000114) Provides a read only value of the current read
16883                                                                     and write pointers. This register is read
16884                                                                     only and can be used alogn with the FIFO
16885                                                                     direct access method to determine the next
16886                                                                     data to be used for input and output functions.            */
16887 
16888     struct {
16889       __IOM uint32_t FIFOWPTR   : 4;            /*!< [3..0] Current FIFO write pointer. Value is the index into the
16890                                                      outgoing FIFO (FIFO0), which is used during write operations
16891                                                      to external devices.                                                      */
16892             uint32_t            : 4;
16893       __IOM uint32_t FIFORPTR   : 4;            /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
16894                                                      FIFO (FIFO1), which is used to store read data returned
16895                                                      from external devices during a read operation.                            */
16896             uint32_t            : 20;
16897     } FIFOLOC_b;
16898   } ;
16899 
16900   union {
16901     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000118) Provides clock related controls used internal
16902                                                                     to the BLEIF module, and enablement of 32KHz
16903                                                                     clock to the BLE Core module. The internal
16904                                                                     clock sourced is selected via the FSEL and
16905                                                                     can be further divided by 3 using the DIV3
16906                                                                     control.This register is also used to enable
16907                                                                     the clock, which must be done prior to performing
16908                                                                     any IO transactions.                                       */
16909 
16910     struct {
16911       __IOM uint32_t IOCLKEN    : 1;            /*!< [0..0] Enable for the interface clock. Must be enabled prior
16912                                                      to executing any IO operations.                                           */
16913             uint32_t            : 7;
16914       __IOM uint32_t FSEL       : 3;            /*!< [10..8] Select the input clock frequency.                                 */
16915       __IOM uint32_t DIV3       : 1;            /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by
16916                                                      3 is done before the DIVEN programmable divider, and if
16917                                                      enabledwill provide the divided by 3 clock as the source
16918                                                      to the programmable divider.                                              */
16919       __IOM uint32_t DIVEN      : 1;            /*!< [12..12] Enable clock division by TOTPER and LOWPER                       */
16920             uint32_t            : 3;
16921       __IOM uint32_t LOWPER     : 8;            /*!< [23..16] Clock low clock count minus 1. This provides the number
16922                                                      of clocks the divided clock will be low when the DIVEN
16923                                                      = 1.Only applicable when DIVEN = 1.                                       */
16924       __IOM uint32_t TOTPER     : 8;            /*!< [31..24] Clock total clock count minus 1. This provides the
16925                                                      total period of the divided clock -1 when the DIVEN is
16926                                                      active. Thesource clock is selected by FSEL. Only applicable
16927                                                      when DIVEN = 1.                                                           */
16928     } CLKCFG_b;
16929   } ;
16930 
16931   union {
16932     __IOM uint32_t SUBMODCTRL;                  /*!< (@ 0x0000011C) Provides enable for each submodule. Only a sigle
16933                                                                     submodule can be enabled at one time.                      */
16934 
16935     struct {
16936       __IOM uint32_t SMOD0EN    : 1;            /*!< [0..0] Submodule 0 enable (1) or disable (0)                              */
16937       __IOM uint32_t SMOD0TYPE  : 3;            /*!< [3..1] Submodule 0 module type. This is the SPI Master interface.         */
16938       __IOM uint32_t SMOD1EN    : 1;            /*!< [4..4] Submodule 1 enable (1) or disable (0)                              */
16939       __IOM uint32_t SMOD1TYPE  : 3;            /*!< [7..5] Submodule 1 module type. This is the I2C Master interface          */
16940       __IOM uint32_t SMOD2EN    : 1;            /*!< [8..8] Submodule 2 enable (1) or disable (0)                              */
16941       __IOM uint32_t SMOD2TYPE  : 3;            /*!< [11..9] Submodule 2 module type. This is the I2S Master/Slave
16942                                                      interface                                                                 */
16943             uint32_t            : 20;
16944     } SUBMODCTRL_b;
16945   } ;
16946 
16947   union {
16948     __IOM uint32_t CMD;                         /*!< (@ 0x00000120) Writes to this register will start an IO transaction,
16949                                                                     as well as set various parameters for the
16950                                                                     command itself. Reads will return the command
16951                                                                     value written to the CMD register.To read
16952                                                                     the number of bytes that have yet to be
16953                                                                     transferred, refer to the CTSIZE field within
16954                                                                     the CMDSTAT register.                                      */
16955 
16956     struct {
16957       __IOM uint32_t CMD        : 4;            /*!< [3..0] Command for submodule.                                             */
16958       __IOM uint32_t OFFSETCNT  : 3;            /*!< [6..4] Number of offset bytes to use for the command - 0, 1,
16959                                                      2, 3, 4, 5 are valid selections. The second (byte 1),third
16960                                                      (byte 2), and forth (byte 3) are read from the OFFSETHI
16961                                                      register, and the low order byte is pulled from this register
16962                                                      in the OFFSETLO field.Offset bytes are transmitted highest
16963                                                      byte first. EG if offsetcnt == 4, OFFSETHI[23:16] will
16964                                                      be transmitted first, then OFFSETHI[15:8], then OFFSETHI[7:0]
16965                                                      then OFFSETLO.If offsetcnt == 5, OFFSETHI[31:24] will be
16966                                                      transmitted, then OFFSETHI[23:0], then O                                  */
16967       __IOM uint32_t CONT       : 1;            /*!< [7..7] Contine to hold the bus after the current transaction
16968                                                      if set to a 1 with a new command issued.                                  */
16969       __IOM uint32_t TSIZE      : 12;           /*!< [19..8] Defines the transaction size in bytes. The offset transfer
16970                                                      is not included in this size.                                             */
16971       __IOM uint32_t CMDSEL     : 2;            /*!< [21..20] Command Specific selection information. Not used in
16972                                                      Master I2C. Used as CEn select for Master SPI transactions                */
16973             uint32_t            : 2;
16974       __IOM uint32_t OFFSETLO   : 8;            /*!< [31..24] This register holds the low order byte of offset to
16975                                                      be used in the transaction. The number of offset bytes
16976                                                      to use is set with bits 1:0 of the command.                               */
16977     } CMD_b;
16978   } ;
16979 
16980   union {
16981     __IOM uint32_t DCXCTRL;                     /*!< (@ 0x00000124) Enables transmission of DCX signal with SPI transactions
16982                                                                     and selects which CE signals will be used
16983                                                                     to transmit the DCX signal.                                */
16984 
16985     struct {
16986       __IOM uint32_t DCXSEL     : 4;            /*!< [3..0] Selects the CE channel used to convey the DCX function.
16987                                                      The select is bitwise encoded, with bit 0 = 1 enabling
16988                                                      CE0 for DCX transmission, bit 1 = 1 enableing CE1 for DCX
16989                                                      transmission, etc. If the CE used for the SPI transaction
16990                                                      is set, it will be ignored and used as the transaction
16991                                                      CE instead. Multiple CE channels can be selected at once.
16992                                                      To enable the DCX signal to be transmitted out of the chip,
16993                                                      the corresponding pin mux function must be enabled in the
16994                                                      GPIO logic as well.                                                       */
16995       __IOM uint32_t DCXEN      : 1;            /*!< [4..4] Global enable of the DCX function. Setting to 1 will
16996                                                      enable the generation of the DCX signal, which will assert
16997                                                      when sending the offset bytes of the SPI transaction.                     */
16998             uint32_t            : 27;
16999     } DCXCTRL_b;
17000   } ;
17001 
17002   union {
17003     __IOM uint32_t OFFSETHI;                    /*!< (@ 0x00000128) High order bytes of offset for IO transaction              */
17004 
17005     struct {
17006       __IOM uint32_t OFFSETHI   : 32;           /*!< [31..0] Holds the high order bytes of the byte addressing/offset
17007                                                      field to use with IO commands. The number of offset bytes
17008                                                      to use is specified in the command register                               */
17009     } OFFSETHI_b;
17010   } ;
17011 
17012   union {
17013     __IOM uint32_t CMDSTAT;                     /*!< (@ 0x0000012C) Provides staus on the execution of the command
17014                                                                     currently in progress. The fields in this
17015                                                                     register will reflect the real time status
17016                                                                     of the internal state machines and data
17017                                                                     transfers within the IOM.These are read
17018                                                                     only fields and writes to the registers
17019                                                                     are ignored.                                               */
17020 
17021     struct {
17022       __IOM uint32_t CCMD       : 5;            /*!< [4..0] Current command that is being executed; This will update
17023                                                      based on the phase of the I2C, and will indicate a write
17024                                                      operation during transmission of the offset,and then the
17025                                                      programmed command. After the command is completed, it
17026                                                      will be cleared to zero. (Note this field is defined as
17027                                                      5b, but top bit is unsed, and matches the size of the CMD
17028                                                      field in the IOM_CMD register )                                           */
17029       __IOM uint32_t CMDSTAT    : 3;            /*!< [7..5] The current status of the command execution.                       */
17030       __IOM uint32_t CTSIZE     : 12;           /*!< [19..8] The current number of bytes still to be transferred
17031                                                      with this command. This field will count down to zero.                    */
17032             uint32_t            : 12;
17033     } CMDSTAT_b;
17034   } ;
17035   __IM  uint32_t  RESERVED1[52];
17036 
17037   union {
17038     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
17039                                                                     to generate the corresponding interrupt.                   */
17040 
17041     struct {
17042       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17043                                                      operation has completed. For repeated commands, this will
17044                                                      only be asserted when the final repeated command is completed.            */
17045       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17046                                                      when the number of free bytes in the write FIFO equals
17047                                                      or exceeds the WTHR field.For read operations, asserted
17048                                                      when the number of valid bytes in the read FIFO equals
17049                                                      of exceeds the value set in the RTHR field.                               */
17050       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17051                                                      tries to pop from an empty fifo.                                          */
17052       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17053                                                      tries to write to a full fifo. The current operation does
17054                                                      not stop.                                                                 */
17055       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17056                                                      been received on the I2C bus.                                             */
17057       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17058                                                      a overflow or underflow event                                             */
17059       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17060                                                      written when an active command is in progress.                            */
17061       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17062                                                      on the bus has signaled a START command.                                  */
17063       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17064                                                      on the bus has signaled a STOP command.                                   */
17065       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17066                                                      is enabled and has been lost to another master on the bus.
17067                                                      Also asserted during I2C write operations when value of
17068                                                      1 expected on bus, but 0 is observed. When asserted, the
17069                                                      I2C state machine will immediately go to idle. This interrupt
17070                                                      condition is cleared by the next command.                                 */
17071       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17072                                                      and the DMA submodule is returned into the idle state                     */
17073       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17074                                                      DMA command. The DMA error could occur when the memory
17075                                                      access specified in the DMA operation is not available
17076                                                      or incorrectly specified.                                                 */
17077       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17078                                                      in the PAUSEEN register. The interrupt is posted when the
17079                                                      event is enabled within the PAUSEEN register, the mask
17080                                                      is active in the CQIRQMASK field and the event occurs.                    */
17081       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17082                                                      the register address bit 0 set to 1. The low address bits
17083                                                      in the CQ address fields are unused and bit 0 can be used
17084                                                      to trigger an interrupt to indicate when this register
17085                                                      write is performed by the CQ operation.                                   */
17086       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17087             uint32_t            : 17;
17088     } INTEN_b;
17089   } ;
17090 
17091   union {
17092     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
17093                                                                     cause of a recent interrupt.                               */
17094 
17095     struct {
17096       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17097                                                      operation has completed. For repeated commands, this will
17098                                                      only be asserted when the final repeated command is completed.            */
17099       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17100                                                      when the number of free bytes in the write FIFO equals
17101                                                      or exceeds the WTHR field.For read operations, asserted
17102                                                      when the number of valid bytes in the read FIFO equals
17103                                                      of exceeds the value set in the RTHR field.                               */
17104       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17105                                                      tries to pop from an empty fifo.                                          */
17106       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17107                                                      tries to write to a full fifo. The current operation does
17108                                                      not stop.                                                                 */
17109       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17110                                                      been received on the I2C bus.                                             */
17111       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17112                                                      a overflow or underflow event                                             */
17113       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17114                                                      written when an active command is in progress.                            */
17115       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17116                                                      on the bus has signaled a START command.                                  */
17117       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17118                                                      on the bus has signaled a STOP command.                                   */
17119       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17120                                                      is enabled and has been lost to another master on the bus.
17121                                                      Also asserted during I2C write operations when value of
17122                                                      1 expected on bus, but 0 is observed. When asserted, the
17123                                                      I2C state machine will immediately go to idle. This interrupt
17124                                                      condition is cleared by the next command.                                 */
17125       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17126                                                      and the DMA submodule is returned into the idle state                     */
17127       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17128                                                      DMA command. The DMA error could occur when the memory
17129                                                      access specified in the DMA operation is not available
17130                                                      or incorrectly specified.                                                 */
17131       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17132                                                      in the PAUSEEN register. The interrupt is posted when the
17133                                                      event is enabled within the PAUSEEN register, the mask
17134                                                      is active in the CQIRQMASK field and the event occurs.                    */
17135       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17136                                                      the register address bit 0 set to 1. The low address bits
17137                                                      in the CQ address fields are unused and bit 0 can be used
17138                                                      to trigger an interrupt to indicate when this register
17139                                                      write is performed by the CQ operation.                                   */
17140       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17141             uint32_t            : 17;
17142     } INTSTAT_b;
17143   } ;
17144 
17145   union {
17146     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
17147                                                                     the interrupt status associated with that
17148                                                                     bit.                                                       */
17149 
17150     struct {
17151       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17152                                                      operation has completed. For repeated commands, this will
17153                                                      only be asserted when the final repeated command is completed.            */
17154       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17155                                                      when the number of free bytes in the write FIFO equals
17156                                                      or exceeds the WTHR field.For read operations, asserted
17157                                                      when the number of valid bytes in the read FIFO equals
17158                                                      of exceeds the value set in the RTHR field.                               */
17159       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17160                                                      tries to pop from an empty fifo.                                          */
17161       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17162                                                      tries to write to a full fifo. The current operation does
17163                                                      not stop.                                                                 */
17164       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17165                                                      been received on the I2C bus.                                             */
17166       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17167                                                      a overflow or underflow event                                             */
17168       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17169                                                      written when an active command is in progress.                            */
17170       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17171                                                      on the bus has signaled a START command.                                  */
17172       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17173                                                      on the bus has signaled a STOP command.                                   */
17174       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17175                                                      is enabled and has been lost to another master on the bus.
17176                                                      Also asserted during I2C write operations when value of
17177                                                      1 expected on bus, but 0 is observed. When asserted, the
17178                                                      I2C state machine will immediately go to idle. This interrupt
17179                                                      condition is cleared by the next command.                                 */
17180       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17181                                                      and the DMA submodule is returned into the idle state                     */
17182       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17183                                                      DMA command. The DMA error could occur when the memory
17184                                                      access specified in the DMA operation is not available
17185                                                      or incorrectly specified.                                                 */
17186       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17187                                                      in the PAUSEEN register. The interrupt is posted when the
17188                                                      event is enabled within the PAUSEEN register, the mask
17189                                                      is active in the CQIRQMASK field and the event occurs.                    */
17190       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17191                                                      the register address bit 0 set to 1. The low address bits
17192                                                      in the CQ address fields are unused and bit 0 can be used
17193                                                      to trigger an interrupt to indicate when this register
17194                                                      write is performed by the CQ operation.                                   */
17195       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17196             uint32_t            : 17;
17197     } INTCLR_b;
17198   } ;
17199 
17200   union {
17201     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
17202                                                                     generate an interrupt from this module.
17203                                                                     (Generally used for testing purposes).                     */
17204 
17205     struct {
17206       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17207                                                      operation has completed. For repeated commands, this will
17208                                                      only be asserted when the final repeated command is completed.            */
17209       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17210                                                      when the number of free bytes in the write FIFO equals
17211                                                      or exceeds the WTHR field.For read operations, asserted
17212                                                      when the number of valid bytes in the read FIFO equals
17213                                                      of exceeds the value set in the RTHR field.                               */
17214       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17215                                                      tries to pop from an empty fifo.                                          */
17216       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17217                                                      tries to write to a full fifo. The current operation does
17218                                                      not stop.                                                                 */
17219       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17220                                                      been received on the I2C bus.                                             */
17221       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17222                                                      a overflow or underflow event                                             */
17223       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17224                                                      written when an active command is in progress.                            */
17225       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17226                                                      on the bus has signaled a START command.                                  */
17227       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17228                                                      on the bus has signaled a STOP command.                                   */
17229       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17230                                                      is enabled and has been lost to another master on the bus.
17231                                                      Also asserted during I2C write operations when value of
17232                                                      1 expected on bus, but 0 is observed. When asserted, the
17233                                                      I2C state machine will immediately go to idle. This interrupt
17234                                                      condition is cleared by the next command.                                 */
17235       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17236                                                      and the DMA submodule is returned into the idle state                     */
17237       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17238                                                      DMA command. The DMA error could occur when the memory
17239                                                      access specified in the DMA operation is not available
17240                                                      or incorrectly specified.                                                 */
17241       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17242                                                      in the PAUSEEN register. The interrupt is posted when the
17243                                                      event is enabled within the PAUSEEN register, the mask
17244                                                      is active in the CQIRQMASK field and the event occurs.                    */
17245       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17246                                                      the register address bit 0 set to 1. The low address bits
17247                                                      in the CQ address fields are unused and bit 0 can be used
17248                                                      to trigger an interrupt to indicate when this register
17249                                                      write is performed by the CQ operation.                                   */
17250       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17251             uint32_t            : 17;
17252     } INTSET_b;
17253   } ;
17254 
17255   union {
17256     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000210) Provides control on which event will trigger
17257                                                                     the DMA transfer after the DMA operation
17258                                                                     is setup and enabled. The trigger event
17259                                                                     will cause a number of bytes (depending
17260                                                                     on trigger event) to betransferred via the
17261                                                                     DMA operation, and can be used to adjust
17262                                                                     the latency of data to/from the IOM module
17263                                                                     to/from the dma target. DMA transfers are
17264                                                                     broken into smaller transfers internally
17265                                                                     of up to16 bytes each, and multiple trigger
17266                                                                     events can be used to complete the entire
17267                                                                     programmed DMA transfer.                                   */
17268 
17269     struct {
17270       __IOM uint32_t DCMDCMPEN  : 1;            /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
17271                                                      of the DMA when a command is completed. When this event
17272                                                      is triggered, the number of words transferred will be the
17273                                                      lesser of the remaining TOTCOUNT bytes, or                                */
17274       __IOM uint32_t DTHREN     : 1;            /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
17275                                                      (IOM writes), the trigger will assert when the write FIFO
17276                                                      has (WTHR/4) number of words free in the write FIFO, and
17277                                                      will transfer (WTHR/4) number of wordsor, if the number
17278                                                      of words left to transfer is less than the WTHR value,
17279                                                      will transfer the remaining byte count.For P2M DMA operations,
17280                                                      the trigger will assert when the read FIFO has (RTHR/4)
17281                                                      words available in the read FIFO, and will transfer (RTHR/4)
17282                                                      words to SRAM. This trigger will NOT asser                                */
17283             uint32_t            : 30;
17284     } DMATRIGEN_b;
17285   } ;
17286 
17287   union {
17288     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000214) Provides the status of trigger events that have
17289                                                                     occurred for the transaction. Some of the
17290                                                                     bits are read only and some can be reset
17291                                                                     via a write of 0.                                          */
17292 
17293     struct {
17294       __IOM uint32_t DCMDCMP    : 1;            /*!< [0..0] Triggered DMA from Command complete event. Bit is read
17295                                                      only and can be cleared by disabling the DCMDCMP trigger
17296                                                      enable or by disabling DMA.                                               */
17297       __IOM uint32_t DTHR       : 1;            /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
17298                                                      be cleared by disabling the DTHR trigger enable or by disabling
17299                                                      DMA.                                                                      */
17300       __IOM uint32_t DTOTCMP    : 1;            /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
17301                                                      in the FIFO was enough to complete the DMA operation (greater
17302                                                      than or equal to current TOTCOUNT) when the command completed.
17303                                                      This trigger is default active when the DCMDCMP trigger
17304                                                      isdisabled and there is enough data in the FIFO to complete
17305                                                      the DMA operation.                                                        */
17306             uint32_t            : 29;
17307     } DMATRIGSTAT_b;
17308   } ;
17309 
17310   union {
17311     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000218) Configuration control of the DMA process, including
17312                                                                     the direction of DMA, and enablement of
17313                                                                     DMA                                                        */
17314 
17315     struct {
17316       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
17317                                                      operation. This should be the last DMA related register
17318                                                      set prior to issuing the command                                          */
17319       __IOM uint32_t DMADIR     : 1;            /*!< [1..1] Direction                                                          */
17320             uint32_t            : 6;
17321       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
17322       __IOM uint32_t DPWROFF    : 1;            /*!< [9..9] Power off module after DMA is complete. If this bit is
17323                                                      active, the module will request to power off the supply
17324                                                      it is attached to. If there are other units still requiring
17325                                                      power from the same domain, power down will not be performed.             */
17326             uint32_t            : 22;
17327     } DMACFG_b;
17328   } ;
17329 
17330   union {
17331     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x0000021C) Contains the number of bytes to be transferred
17332                                                                     for this DMA transaction. This register
17333                                                                     is decremented as the data is transferred,
17334                                                                     and will be 0 at the completion of the DMA
17335                                                                     operation.                                                 */
17336 
17337     struct {
17338       __IOM uint32_t TOTCOUNT   : 12;           /*!< [11..0] Triggered DMA from Command complete event occured. Bit
17339                                                      is read only and can be cleared by disabling the DTHR trigger
17340                                                      enable or by disabling DMA.                                               */
17341             uint32_t            : 20;
17342     } DMATOTCOUNT_b;
17343   } ;
17344 
17345   union {
17346     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000220) The source or destination address internal the
17347                                                                     SRAM for the DMA data. For write operations,
17348                                                                     this can only be SRAM data (ADDR bit 28
17349                                                                     = 1); For read operations, this can ve either
17350                                                                     SRAM or FLASH (ADDR bit 28 = 0)                            */
17351 
17352     struct {
17353       __IOM uint32_t TARGADDR   : 29;           /*!< [28..0] Bits [28:0] of the target byte address for source of
17354                                                      DMA (either read or write). The address can be any byte
17355                                                      alignment, and does not have to be word aligned. In cases
17356                                                      of non-word aligned addresses, the DMA logic will take
17357                                                      care for ensuring only the target bytes are read/written.                 */
17358             uint32_t            : 3;
17359     } DMATARGADDR_b;
17360   } ;
17361 
17362   union {
17363     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000224) Status of the DMA operation currently in progress.         */
17364 
17365     struct {
17366       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
17367                                                      a DMA transfer is active. The DMA transfer may be waiting
17368                                                      on data, transferring data, or waiting for priority.All
17369                                                      of these will be indicated with a 1. A 0 will indicate
17370                                                      that the DMA is fully complete and no further transactions
17371                                                      will be done. This bit is read only.                                      */
17372       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
17373                                                      operation. This bit can be cleared by writing to 0, and
17374                                                      will also be cleared when a new DMA is started.                           */
17375       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals an error was
17376                                                      encountered during the DMA operation. The bit can be cleared
17377                                                      by writing to 0. Once set, this bit will remain set until
17378                                                      cleared by software.                                                      */
17379             uint32_t            : 29;
17380     } DMASTAT_b;
17381   } ;
17382 
17383   union {
17384     __IOM uint32_t CQCFG;                       /*!< (@ 0x00000228) Controls parameters and options for execution
17385                                                                     of the command queue operation. To enable
17386                                                                     command queue, create this in memory, set
17387                                                                     the address, and enable it with a write
17388                                                                     to CQEN                                                    */
17389 
17390     struct {
17391       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
17392                                                      of the command queue and fetches of address/data pairs
17393                                                      will proceed from the word address within the CQADDR register.
17394                                                      Can be disabledusing a CQ executed write to this bit as
17395                                                      well.                                                                     */
17396       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue dma request                 */
17397       __IOM uint32_t MSPIFLGSEL : 2;            /*!< [3..2] Selects the MPSI modules used for sourcing the CQFLAG
17398                                                      [11:8].                                                                   */
17399             uint32_t            : 28;
17400     } CQCFG_b;
17401   } ;
17402 
17403   union {
17404     __IOM uint32_t CQADDR;                      /*!< (@ 0x0000022C) The SRAM address which will be fetched next execution
17405                                                                     of the CQ operation. This register is updated
17406                                                                     as the CQ operation progresses, and is the
17407                                                                     live version of the register. The register
17408                                                                     can also bewritten by the Command Queue
17409                                                                     operation itself, allowing the relocation
17410                                                                     of successive CQ fetches. In this case,
17411                                                                     the new CQ address will be used for the
17412                                                                     next CQ address/data fetch                                 */
17413 
17414     struct {
17415             uint32_t            : 2;
17416       __IOM uint32_t CQADDR     : 27;           /*!< [28..2] Bits 28:2 of target byte address for source of CQ .
17417                                                      The buffer must be aligned on a word boundary                             */
17418             uint32_t            : 3;
17419     } CQADDR_b;
17420   } ;
17421 
17422   union {
17423     __IOM uint32_t CQSTAT;                      /*!< (@ 0x00000230) Provides the status of the command queue operation.
17424                                                                     If the command queue is disabled, these
17425                                                                     bits will be cleared. The bits are read
17426                                                                     only                                                       */
17427 
17428     struct {
17429       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
17430                                                      indicate that a CQ transfer is active and this will remain
17431                                                      active even when paused waiting for external event.                       */
17432       __IOM uint32_t CQPAUSED   : 1;            /*!< [1..1] Command queue operation is currently paused.                       */
17433       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
17434                                                      signals that an error was encountered during the CQ operation.            */
17435             uint32_t            : 29;
17436     } CQSTAT_b;
17437   } ;
17438 
17439   union {
17440     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x00000234) Command Queue Flag                                         */
17441 
17442     struct {
17443       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
17444                                                      controllable and bits [15:8] are hardware status.                         */
17445       __IOM uint32_t CQIRQMASK  : 16;           /*!< [31..16] Mask the bits used to generate the command queue interrupt.
17446                                                      A '1' in the bit position will enable the pause event to
17447                                                      trigger the interrupt, if the CQWT_int interrupt is enabled.
17448                                                      Bits definitions are the same as CQPAUSE                                  */
17449     } CQFLAGS_b;
17450   } ;
17451 
17452   union {
17453     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x00000238) Set/Clear the command queue software pause flags
17454                                                                     on a per-bit basis. Contains 3 fields, allowing
17455                                                                     for setting, clearing or toggling the value
17456                                                                     in the software flags. Priority when the
17457                                                                     same bitis enabled in each field is toggle,
17458                                                                     then set, then clear.                                      */
17459 
17460     struct {
17461       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
17462                                                      SWFLAG with a '1' in the corresponding bit position of
17463                                                      this field                                                                */
17464       __IOM uint32_t CQFTGL     : 8;            /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
17465                                                      SWFLAG with a '1' in the corresponding bit position of
17466                                                      this field                                                                */
17467       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
17468                                                      with a '1' in the corresponding bit position of this field                */
17469             uint32_t            : 8;
17470     } CQSETCLEAR_b;
17471   } ;
17472 
17473   union {
17474     __IOM uint32_t CQPAUSEEN;                   /*!< (@ 0x0000023C) Enables a flag to pause an active command queue
17475                                                                     operation. If a bit is '1' and the corresponding
17476                                                                     bit in the CQFLAG register is '1', CQ processing
17477                                                                     will halt until either value is changed
17478                                                                     to '0'.                                                    */
17479 
17480     struct {
17481       __IOM uint32_t CQPEN      : 16;           /*!< [15..0] Enables the specified event to pause command processing
17482                                                      when active                                                               */
17483             uint32_t            : 16;
17484     } CQPAUSEEN_b;
17485   } ;
17486 
17487   union {
17488     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x00000240) Current index value, targeted to be written by
17489                                                                     register write operations within the command
17490                                                                     queue. This is compared to the CQENDIDX
17491                                                                     and will stop the CQ operation if bit 15
17492                                                                     of the CQPAUSEEN is '1' andthis current
17493                                                                     index equals the CQENDIDX register value.
17494                                                                     This will only pause when the values are
17495                                                                     equal.                                                     */
17496 
17497     struct {
17498       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
17499                                                      register field. If the values match, the IDXEQ pause event
17500                                                      will be activated, which will cause the pausing of command
17501                                                      quue operation if the IDXEQ bit is enabled in CQPAUSEEN.                  */
17502             uint32_t            : 24;
17503     } CQCURIDX_b;
17504   } ;
17505 
17506   union {
17507     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x00000244) End index value, targeted to be written by software
17508                                                                     to indicate the last valid register pair
17509                                                                     contained within the command queue. rgister
17510                                                                     write operations within the command queue.This
17511                                                                     is compared to the CQCURIDX and will stop
17512                                                                     the CQ operation if bit 15 of the CQPAUSEEN
17513                                                                     is '1' andthis current index equals the
17514                                                                     CQCURIDX register value. This will only
17515                                                                     pause when the values are equal.                           */
17516 
17517     struct {
17518       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
17519                                                      register field. If the values match, the IDXEQ pause event
17520                                                      will be activated, which will cause the pausing of command
17521                                                      quue operation if the IDXEQ bit is enabled in CQPAUSEEN.                  */
17522             uint32_t            : 24;
17523     } CQENDIDX_b;
17524   } ;
17525 
17526   union {
17527     __IOM uint32_t STATUS;                      /*!< (@ 0x00000248) IOM Module Status                                          */
17528 
17529     struct {
17530       __IOM uint32_t ERR        : 1;            /*!< [0..0] Bit has been deprecated. Please refer to the other error
17531                                                      indicators. This will always return 0.                                    */
17532       __IOM uint32_t CMDACT     : 1;            /*!< [1..1] Indicates if the active I/O Command is currently processing
17533                                                      a transaction, or command is complete, but the FIFO pointers
17534                                                      are still syncronizing internally. This bit will go high
17535                                                      atthe start of the transaction, and will go low when the
17536                                                      command is complete, and the data and pointers within the
17537                                                      FIFO have been syncronized.                                               */
17538       __IOM uint32_t IDLEST     : 1;            /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
17539                                                      - The state machine could be in idle state due to holdoffs
17540                                                      from data availability, or as the command gets propagated
17541                                                      into the logic from the registers.                                        */
17542             uint32_t            : 29;
17543     } STATUS_b;
17544   } ;
17545   __IM  uint32_t  RESERVED2[13];
17546 
17547   union {
17548     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000280) Controls the configuration of the SPI master
17549                                                                     module, including POL/PHA, LSB, flow control,
17550                                                                     and delays for MISO and MOSI                               */
17551 
17552     struct {
17553       __IOM uint32_t SPOL       : 1;            /*!< [0..0] Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility
17554                                                      of creating a clock glitch which could cause register corruption,
17555                                                      changing SPHA and SPOL bits should be done in separate
17556                                                      writes to this register.                                                  */
17557       __IOM uint32_t SPHA       : 1;            /*!< [1..1] Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility
17558                                                      of creating a clock glitch which could cause register corruption,
17559                                                      changing SPHA and SPOL bits should be done in separate
17560                                                      writes to this register.                                                  */
17561       __IOM uint32_t FULLDUP    : 1;            /*!< [2..2] Enables full duplex mode for Master SPI write operations.
17562                                                      Data will be captured simultaneously into the read fifo                   */
17563             uint32_t            : 13;
17564       __IOM uint32_t WTFC       : 1;            /*!< [16..16] enables write mode flow control.                                 */
17565       __IOM uint32_t RDFC       : 1;            /*!< [17..17] Enables read mode flow control.                                  */
17566       __IOM uint32_t MOSIINV    : 1;            /*!< [18..18] Inverts MOSI when flow control is enabled.                       */
17567             uint32_t            : 1;
17568       __IOM uint32_t WTFCIRQ    : 1;            /*!< [20..20] Selects the write mode flow control signal.                      */
17569       __IOM uint32_t WTFCPOL    : 1;            /*!< [21..21] selects the write flow control signal polarity. The
17570                                                      transfers are halted when the selected flow control signal
17571                                                      is OPPOSITE polarity of bit. (For example: WTFCPOL = 0
17572                                                      will allow a IRQ=1 to pause transfers).                                   */
17573       __IOM uint32_t RDFCPOL    : 1;            /*!< [22..22] Selects the read flow control signal polarity.                   */
17574       __IOM uint32_t SPILSB     : 1;            /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
17575                                                      (1) for the data portion of the SPI transaction. The offset
17576                                                      bytes are always transmitted MSB first.                                   */
17577       __IOM uint32_t DINDLY     : 3;            /*!< [26..24] Delay tap to use for the input signal (MISO). This
17578                                                      gives more hold time on the input data.                                   */
17579       __IOM uint32_t DOUTDLY    : 3;            /*!< [29..27] Delay tap to use for the output signal (MOSI). This
17580                                                      give more hold time on the output data                                    */
17581       __IOM uint32_t MSPIRST    : 1;            /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for
17582                                                      the module                                                                */
17583             uint32_t            : 1;
17584     } MSPICFG_b;
17585   } ;
17586   __IM  uint32_t  RESERVED3[15];
17587 
17588   union {
17589     __IOM uint32_t MI2CCFG;                     /*!< (@ 0x000002C0) Controls the configuration of the I2C bus master.          */
17590 
17591     struct {
17592       __IOM uint32_t ADDRSZ     : 1;            /*!< [0..0] Sets the I2C master device address size to either 7b
17593                                                      (0) or 10b (1).                                                           */
17594       __IOM uint32_t I2CLSB     : 1;            /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1)
17595                                                      first. Default per I2C specification is MSB first. This
17596                                                      applies to both read and write data, and read data will
17597                                                      be bit                                                                    */
17598       __IOM uint32_t ARBEN      : 1;            /*!< [2..2] Enables multi-master arbitration for the I2C master.
17599                                                      If the bus is known to have only a single master, this
17600                                                      function can be disabled to save clock cycles on I2C transactions         */
17601             uint32_t            : 1;
17602       __IOM uint32_t SDADLY     : 2;            /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3.             */
17603       __IOM uint32_t MI2CRST    : 1;            /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for
17604                                                      the module                                                                */
17605             uint32_t            : 1;
17606       __IOM uint32_t SCLENDLY   : 4;            /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the
17607                                                      SCL output en (clock will go low on this edge). Used to
17608                                                      allow clock shaping.                                                      */
17609       __IOM uint32_t SDAENDLY   : 4;            /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all
17610                                                      transitions affected). Used to delay data relative to clock               */
17611       __IOM uint32_t SMPCNT     : 8;            /*!< [23..16] Number of Base clk cycles to wait before sampling the
17612                                                      SCL clock to determine if a clock stretch event has occured               */
17613       __IOM uint32_t STRDIS     : 1;            /*!< [24..24] Disable detection of clock stretch events smaller than
17614                                                      1 cycle                                                                   */
17615             uint32_t            : 7;
17616     } MI2CCFG_b;
17617   } ;
17618 
17619   union {
17620     __IOM uint32_t DEVCFG;                      /*!< (@ 0x000002C4) Contains the I2C device address.                           */
17621 
17622     struct {
17623       __IOM uint32_t DEVADDR    : 10;           /*!< [9..0] I2C address of the device that the Master will use to
17624                                                      target for read/write operations. This can be either a
17625                                                      7b or 10b address.                                                        */
17626             uint32_t            : 22;
17627     } DEVCFG_b;
17628   } ;
17629   __IM  uint32_t  RESERVED4[48];
17630 
17631   union {
17632     __IOM uint32_t IOMDBG;                      /*!< (@ 0x00000388) Debug control                                              */
17633 
17634     struct {
17635       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
17636                                                      within this register, otherwise it is clock gated for power
17637                                                      savings                                                                   */
17638       __IOM uint32_t IOCLKON    : 1;            /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
17639                                                      when this bit is '1'. Otherwise, the clock is controlled
17640                                                      with gating from the logic as needed.                                     */
17641       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
17642                                                      when this bit is '1'. Otherwise, the clock is controlled
17643                                                      with gating from the logic as needed.                                     */
17644       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
17645                                                      to select between different debug data available in the
17646                                                      DBG0 and DBG1 registers.                                                  */
17647     } IOMDBG_b;
17648   } ;
17649 } IOM0_Type;                                    /*!< Size = 908 (0x38c)                                                        */
17650 
17651 
17652 
17653 /* =========================================================================================================================== */
17654 /* ================                                          IOSLAVE                                          ================ */
17655 /* =========================================================================================================================== */
17656 
17657 
17658 /**
17659   * @brief I2C/SPI Slave (IOSLAVE)
17660   */
17661 
17662 typedef struct {                                /*!< (@ 0x40034000) IOSLAVE Structure                                          */
17663   __IM  uint32_t  RESERVED[64];
17664 
17665   union {
17666     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Current FIFO Pointer                                       */
17667 
17668     struct {
17669       __IOM uint32_t FIFOPTR    : 8;            /*!< [7..0] Current FIFO pointer.                                              */
17670       __IOM uint32_t FIFOSIZ    : 8;            /*!< [15..8] The number of bytes currently in the hardware FIFO.               */
17671             uint32_t            : 16;
17672     } FIFOPTR_b;
17673   } ;
17674 
17675   union {
17676     __IOM uint32_t FIFOCFG;                     /*!< (@ 0x00000104) FIFO Configuration                                         */
17677 
17678     struct {
17679       __IOM uint32_t FIFOBASE   : 5;            /*!< [4..0] These bits hold the base address of the I/O FIFO in 8
17680                                                      byte segments. The IO Slave FIFO is situated in LRAM at
17681                                                      (FIFOBASE*8) to (FIFOMAX*8-1).                                            */
17682             uint32_t            : 3;
17683       __IOM uint32_t FIFOMAX    : 6;            /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments.
17684                                                      It is also the beginning of the RAM area of the LRAM. Note
17685                                                      that no RAM area is configured if FIFOMAX is set to 0x1F.                 */
17686             uint32_t            : 10;
17687       __IOM uint32_t ROBASE     : 6;            /*!< [29..24] Defines the read-only area. The IO Slave read-only
17688                                                      area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)                  */
17689             uint32_t            : 2;
17690     } FIFOCFG_b;
17691   } ;
17692 
17693   union {
17694     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000108) FIFO Threshold Configuration                               */
17695 
17696     struct {
17697       __IOM uint32_t FIFOTHR    : 8;            /*!< [7..0] FIFO size interrupt threshold.                                     */
17698             uint32_t            : 24;
17699     } FIFOTHR_b;
17700   } ;
17701 
17702   union {
17703     __IOM uint32_t FUPD;                        /*!< (@ 0x0000010C) FIFO Update Status                                         */
17704 
17705     struct {
17706       __IOM uint32_t FIFOUPD    : 1;            /*!< [0..0] This bit indicates that a FIFO update is underway.                 */
17707       __IOM uint32_t IOREAD     : 1;            /*!< [1..1] This bitfield indicates an IO read is active.                      */
17708             uint32_t            : 30;
17709     } FUPD_b;
17710   } ;
17711 
17712   union {
17713     __IOM uint32_t FIFOCTR;                     /*!< (@ 0x00000110) Overall FIFO Counter                                       */
17714 
17715     struct {
17716       __IOM uint32_t FIFOCTR    : 10;           /*!< [9..0] Virtual FIFO byte count                                            */
17717             uint32_t            : 22;
17718     } FIFOCTR_b;
17719   } ;
17720 
17721   union {
17722     __IOM uint32_t FIFOINC;                     /*!< (@ 0x00000114) Overall FIFO Counter Increment                             */
17723 
17724     struct {
17725       __IOM uint32_t FIFOINC    : 10;           /*!< [9..0] Increment the Overall FIFO Counter by this value on a
17726                                                      write                                                                     */
17727             uint32_t            : 22;
17728     } FIFOINC_b;
17729   } ;
17730 
17731   union {
17732     __IOM uint32_t CFG;                         /*!< (@ 0x00000118) I/O Slave Configuration                                    */
17733 
17734     struct {
17735       __IOM uint32_t IFCSEL     : 1;            /*!< [0..0] This bit selects the I/O interface.                                */
17736       __IOM uint32_t SPOL       : 1;            /*!< [1..1] This bit selects SPI polarity.                                     */
17737       __IOM uint32_t LSB        : 1;            /*!< [2..2] This bit selects the transfer bit ordering.                        */
17738             uint32_t            : 1;
17739       __IOM uint32_t STARTRD    : 1;            /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read.              */
17740             uint32_t            : 3;
17741       __IOM uint32_t I2CADDR    : 12;           /*!< [19..8] 7-bit or 10-bit I2C device address.                               */
17742       __IOM uint32_t WRAPPTR    : 1;            /*!< [20..20] Address pointer wrap mode enable.                                */
17743             uint32_t            : 10;
17744       __IOM uint32_t IFCEN      : 1;            /*!< [31..31] IOSLAVE interface enable.                                        */
17745     } CFG_b;
17746   } ;
17747 
17748   union {
17749     __IOM uint32_t PRENC;                       /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode                        */
17750 
17751     struct {
17752       __IOM uint32_t PRENC      : 5;            /*!< [4..0] These bits hold the priority encode of the REGACC interrupts.      */
17753             uint32_t            : 27;
17754     } PRENC_b;
17755   } ;
17756 
17757   union {
17758     __IOM uint32_t IOINTCTL;                    /*!< (@ 0x00000120) I/O Interrupt Control                                      */
17759 
17760     struct {
17761       __IOM uint32_t IOINTEN    : 8;            /*!< [7..0] These read-only bits indicate whether the IOINT interrupts
17762                                                      are enabled.                                                              */
17763       __IOM uint32_t IOINT      : 8;            /*!< [15..8] These bits read the IOINT interrupts.                             */
17764       __IOM uint32_t IOINTCLR   : 1;            /*!< [16..16] This bit clears all of the IOINT interrupts when written
17765                                                      with a 1.                                                                 */
17766             uint32_t            : 7;
17767       __IOM uint32_t IOINTSET   : 8;            /*!< [31..24] These bits set the IOINT interrupts when written with
17768                                                      a 1.                                                                      */
17769     } IOINTCTL_b;
17770   } ;
17771 
17772   union {
17773     __IOM uint32_t GENADD;                      /*!< (@ 0x00000124) General Address Data                                       */
17774 
17775     struct {
17776       __IOM uint32_t GADATA     : 8;            /*!< [7..0] The data supplied on the last General Address reference.           */
17777             uint32_t            : 24;
17778     } GENADD_b;
17779   } ;
17780 
17781   union {
17782     __IOM uint32_t ADDPTR;                      /*!< (@ 0x00000128) Address pointer                                            */
17783 
17784     struct {
17785       __IOM uint32_t ADDPTR     : 8;            /*!< [7..0] The current value in the Address pointer.                          */
17786             uint32_t            : 24;
17787     } ADDPTR_b;
17788   } ;
17789   __IM  uint32_t  RESERVED1[53];
17790 
17791   union {
17792     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
17793                                                                     to generate the corresponding interrupt.                   */
17794 
17795     struct {
17796       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17797       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17798       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17799       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17800       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17801       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17802       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17803       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17804       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17805       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17806             uint32_t            : 22;
17807     } INTEN_b;
17808   } ;
17809 
17810   union {
17811     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
17812                                                                     cause of a recent interrupt.                               */
17813 
17814     struct {
17815       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17816       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17817       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17818       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17819       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17820       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17821       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17822       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17823       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17824       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17825             uint32_t            : 22;
17826     } INTSTAT_b;
17827   } ;
17828 
17829   union {
17830     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
17831                                                                     the interrupt status associated with that
17832                                                                     bit.                                                       */
17833 
17834     struct {
17835       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17836       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17837       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17838       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17839       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17840       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17841       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17842       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17843       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17844       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17845             uint32_t            : 22;
17846     } INTCLR_b;
17847   } ;
17848 
17849   union {
17850     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
17851                                                                     generate an interrupt from this module.
17852                                                                     (Generally used for testing purposes).                     */
17853 
17854     struct {
17855       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17856       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17857       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17858       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17859       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17860       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17861       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17862       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17863       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17864       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17865             uint32_t            : 22;
17866     } INTSET_b;
17867   } ;
17868 
17869   union {
17870     __IOM uint32_t REGACCINTEN;                 /*!< (@ 0x00000210) Set bits in this register to allow this module
17871                                                                     to generate the corresponding interrupt.                   */
17872 
17873     struct {
17874       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17875     } REGACCINTEN_b;
17876   } ;
17877 
17878   union {
17879     __IOM uint32_t REGACCINTSTAT;               /*!< (@ 0x00000214) Read bits from this register to discover the
17880                                                                     cause of a recent interrupt.                               */
17881 
17882     struct {
17883       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17884     } REGACCINTSTAT_b;
17885   } ;
17886 
17887   union {
17888     __IOM uint32_t REGACCINTCLR;                /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
17889                                                                     the interrupt status associated with that
17890                                                                     bit.                                                       */
17891 
17892     struct {
17893       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17894     } REGACCINTCLR_b;
17895   } ;
17896 
17897   union {
17898     __IOM uint32_t REGACCINTSET;                /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
17899                                                                     generate an interrupt from this module.
17900                                                                     (Generally used for testing purposes).                     */
17901 
17902     struct {
17903       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17904     } REGACCINTSET_b;
17905   } ;
17906 } IOSLAVE_Type;                                 /*!< Size = 544 (0x220)                                                        */
17907 
17908 
17909 
17910 /* =========================================================================================================================== */
17911 /* ================                                          MCUCTRL                                          ================ */
17912 /* =========================================================================================================================== */
17913 
17914 
17915 /**
17916   * @brief MCU Miscellaneous Control Logic (MCUCTRL)
17917   */
17918 
17919 typedef struct {                                /*!< (@ 0x40020000) MCUCTRL Structure                                          */
17920 
17921   union {
17922     __IOM uint32_t CHIPPN;                      /*!< (@ 0x00000000) Chip Information                                           */
17923 
17924     struct {
17925       __IOM uint32_t PARTNUM    : 32;           /*!< [31..0] BCD part number.                                                  */
17926     } CHIPPN_b;
17927   } ;
17928 
17929   union {
17930     __IOM uint32_t CHIPID0;                     /*!< (@ 0x00000004) Unique Chip ID 0                                           */
17931 
17932     struct {
17933       __IOM uint32_t CHIPID0    : 32;           /*!< [31..0] Unique chip ID 0.                                                 */
17934     } CHIPID0_b;
17935   } ;
17936 
17937   union {
17938     __IOM uint32_t CHIPID1;                     /*!< (@ 0x00000008) Unique Chip ID 1                                           */
17939 
17940     struct {
17941       __IOM uint32_t CHIPID1    : 32;           /*!< [31..0] Unique chip ID 1.                                                 */
17942     } CHIPID1_b;
17943   } ;
17944 
17945   union {
17946     __IOM uint32_t CHIPREV;                     /*!< (@ 0x0000000C) Chip Revision                                              */
17947 
17948     struct {
17949       __IOM uint32_t REVMIN     : 4;            /*!< [3..0] Minor Revision ID.                                                 */
17950       __IOM uint32_t REVMAJ     : 4;            /*!< [7..4] Major Revision ID.                                                 */
17951       __IOM uint32_t SIPART     : 12;           /*!< [19..8] Silicon Part ID                                                   */
17952             uint32_t            : 12;
17953     } CHIPREV_b;
17954   } ;
17955 
17956   union {
17957     __IOM uint32_t VENDORID;                    /*!< (@ 0x00000010) Unique Vendor ID                                           */
17958 
17959     struct {
17960       __IOM uint32_t VENDORID   : 32;           /*!< [31..0] Unique Vendor ID                                                  */
17961     } VENDORID_b;
17962   } ;
17963 
17964   union {
17965     __IOM uint32_t SKU;                         /*!< (@ 0x00000014) Unique Chip SKU                                            */
17966 
17967     struct {
17968       __IOM uint32_t SKUSRAMSIZE : 2;           /*!< [1..0] SRAM SKU dictates the available memory for MCU. All of
17969                                                      the MCU TCM is always available in addition to these. 0:
17970                                                      512K SSRAM, 1: 1MB SSRAM, 2: 1MB SSRAM + DSP Memories                     */
17971       __IOM uint32_t SKUMRAMSIZE : 2;           /*!< [3..2] MRAM size SKU. 0:0.5MB, 1=1MB, 2=1.5MB, 3:2MB                      */
17972       __IOM uint32_t SKUDSP     : 2;            /*!< [5..4] DSP availability SKU setting. 0:No DSPs available, 1:
17973                                                      DSP0 only available, 2 (or 3): Both DSP0 and DSP1 are available           */
17974       __IOM uint32_t SKUTURBOSPOT : 1;          /*!< [6..6] High performance mode for MCU and DSPs.                            */
17975       __IOM uint32_t SKUMIPIDSI : 1;            /*!< [7..7] MIPI DSI available                                                 */
17976       __IOM uint32_t SKUGFX     : 1;            /*!< [8..8] GFX available                                                      */
17977       __IOM uint32_t SKUUSB     : 1;            /*!< [9..9] USB available                                                      */
17978       __IOM uint32_t SKUSECURESPOT : 1;         /*!< [10..10] Secure boot feature                                              */
17979             uint32_t            : 21;
17980     } SKU_b;
17981   } ;
17982   __IM  uint32_t  RESERVED[2];
17983 
17984   union {
17985     __IOM uint32_t DEBUGGER;                    /*!< (@ 0x00000020) Debugger Control                                           */
17986 
17987     struct {
17988       __IOM uint32_t LOCKOUT    : 32;           /*!< [31..0] Lockout of debugger (SWD).                                        */
17989     } DEBUGGER_b;
17990   } ;
17991   __IM  uint32_t  RESERVED1;
17992 
17993   union {
17994     __IOM uint32_t ACRG;                        /*!< (@ 0x00000028) Active Current Reference Generator Control                 */
17995 
17996     struct {
17997       __IOM uint32_t ACRGSWE    : 1;            /*!< [0..0] Software enablement for ACRG register. A value of 1 will
17998                                                      allow writes to the register                                              */
17999       __IOM uint32_t ACRGPWD    : 1;            /*!< [1..1] Power down the ACRG.                                               */
18000       __IOM uint32_t ACRGIBIASSEL : 1;          /*!< [2..2] Set the ACRG ibias. Note: the SWE mux select in PWRSEQ2SWE
18001                                                      must be set for this to take effect. The inversion of this
18002                                                      register is driven to analog.                                             */
18003       __IOM uint32_t ACRGTRIM   : 5;            /*!< [7..3] ACRG Trim value                                                    */
18004             uint32_t            : 24;
18005     } ACRG_b;
18006   } ;
18007   __IM  uint32_t  RESERVED2[6];
18008 
18009   union {
18010     __IOM uint32_t VREFGEN2;                    /*!< (@ 0x00000044) Voltage Reference Generator 2 Control                      */
18011 
18012     struct {
18013       __IOM uint32_t TVRGTEMPCOTRIM : 5;        /*!< [4..0] Calibrated Voltage Reference Generator tc trim (bottom
18014                                                      transistor)                                                               */
18015       __IOM uint32_t TVRGPWD    : 1;            /*!< [5..5] Power Down, Calibrated Voltage Reference Generator.                */
18016       __IOM uint32_t TVRGCURRENTTRIM : 1;       /*!< [6..6] Calibrated voltage reference current trim.                         */
18017       __IOM uint32_t TVRGVREFTRIM : 7;          /*!< [13..7] Calibrated voltage reference 580m trim                            */
18018       __IOM uint32_t TVRG2TEMPCOTRIM : 5;       /*!< [18..14] Calibrated Voltage Reference Generator tc trim (bottom
18019                                                      transistor)                                                               */
18020       __IOM uint32_t TVRG2PWD   : 1;            /*!< [19..19] Power Down, Calibrated Voltage Reference Generator.              */
18021       __IOM uint32_t TVRG2CURRENTTRIM : 1;      /*!< [20..20] Calibrated voltage reference current trim.                       */
18022       __IOM uint32_t TVRG2VREFTRIM : 7;         /*!< [27..21] Calibrated voltage reference 580m trim                           */
18023       __IOM uint32_t TVRGSELVREF : 1;           /*!< [28..28] TVRG SEL VREF                                                    */
18024       __IOM uint32_t TVRG2SELVREF : 1;          /*!< [29..29] TVRG2 SEL VREF                                                   */
18025             uint32_t            : 2;
18026     } VREFGEN2_b;
18027   } ;
18028   __IM  uint32_t  RESERVED3[6];
18029 
18030   union {
18031     __IOM uint32_t VRCTRL;                      /*!< (@ 0x00000060) Overrides for Voltage Regulators Controls                  */
18032 
18033     struct {
18034       __IOM uint32_t CORELDOOVER : 1;           /*!< [0..0] Override control for CORE LDO signals                              */
18035       __IOM uint32_t CORELDOPDNB : 1;           /*!< [1..1] CORE LDO PDNB control. Override for PWRCTRL going to
18036                                                      analog when CORELDOOVER = 1                                               */
18037       __IOM uint32_t CORELDOACTIVEEARLY : 1;    /*!< [2..2] CORE LDO EARLY ACTIVE control. Override for PWRCTRL going
18038                                                      to analog when CORELDOOVER = 1                                            */
18039       __IOM uint32_t CORELDOACTIVE : 1;         /*!< [3..3] CORE LDO ACTIVE control. Override for PWRCTRL going to
18040                                                      analog when CORELDOOVER = 1                                               */
18041       __IOM uint32_t CORELDOCOLDSTARTEN : 1;    /*!< [4..4] CORE LDO COLDSTART EN control. This is a shadow backed
18042                                                      register and no need to set CORELDOOVER.                                  */
18043       __IOM uint32_t MEMLDOOVER : 1;            /*!< [5..5] Override control for MEM LDO signals                               */
18044       __IOM uint32_t MEMLDOPDNB : 1;            /*!< [6..6] MEM LDO PDNB control. Override signal for PWRCTRL going
18045                                                      to analog when MEMLDOOVER = 1                                             */
18046       __IOM uint32_t MEMLDOACTIVEEARLY : 1;     /*!< [7..7] MEM LDO EARLY ACTIVE control. Override for PWRCTRL going
18047                                                      to analog when MEMLDOOVER = 1                                             */
18048       __IOM uint32_t MEMLDOACTIVE : 1;          /*!< [8..8] MEM LDO ACTIVE control. Override for PWRCTRL going to
18049                                                      analog when MEMLDOOVER = 1                                                */
18050       __IOM uint32_t MEMLDOCOLDSTARTEN : 1;     /*!< [9..9] MEM LDO COLDSTART EN control. This is a shadow backed
18051                                                      register and no need to set MEMLDOOVER.                                   */
18052       __IOM uint32_t MEMLPLDOOVER : 1;          /*!< [10..10] Override control for MEM LP LDO signals                          */
18053       __IOM uint32_t MEMLPLDOPDNB : 1;          /*!< [11..11] MEM LP LDO PDNB control. Override for PWRCTRL going
18054                                                      to analog when MEMLPLDOOVER = 1                                           */
18055       __IOM uint32_t MEMLPLDOACTIVE : 1;        /*!< [12..12] MEM LP LDO ACTVIVE control. Override for PWRCTRL going
18056                                                      to analog when MEMLPLDOOVER = 1                                           */
18057       __IOM uint32_t ANALDOOVER : 1;            /*!< [13..13] Override control for ANALDO signals                              */
18058       __IOM uint32_t ANALDOPDNB : 1;            /*!< [14..14] ANALDO PDNB control. Override for PWRCTRL going to
18059                                                      analog when ANALDOOVER = 1                                                */
18060       __IOM uint32_t ANALDOACTIVE : 1;          /*!< [15..15] ANALDO LDO ACTIVE control. Override for PWRCTRL going
18061                                                      to analog when ANALDOOVER = 1                                             */
18062       __IOM uint32_t SIMOBUCKOVER : 1;          /*!< [16..16] Override control for SIMO BUCK signals                           */
18063       __IOM uint32_t SIMOBUCKPDNB : 1;          /*!< [17..17] SIMO BUCK PDNB control. Override for PWRCTRL going
18064                                                      to analog when SIMOBUCKOVER = 1                                           */
18065       __IOM uint32_t SIMOBUCKRSTB : 1;          /*!< [18..18] SIMO BUCK RSTB control. Override for PWRCTRL going
18066                                                      to analog when SIMOBUCKOVER = 1                                           */
18067       __IOM uint32_t SIMOBUCKACTIVE : 1;        /*!< [19..19] SIMO BUCK ACTIVE control. Override for PWRCTRL going
18068                                                      to analog when SIMOBUCKOVER = 1                                           */
18069             uint32_t            : 12;
18070     } VRCTRL_b;
18071   } ;
18072   __IM  uint32_t  RESERVED4[7];
18073 
18074   union {
18075     __IOM uint32_t LDOREG1;                     /*!< (@ 0x00000080) CORELDO trims Reg                                          */
18076 
18077     struct {
18078       __IOM uint32_t CORELDOACTIVETRIM : 10;    /*!< [9..0] CORE LDO active trim                                               */
18079       __IOM uint32_t CORELDOTEMPCOTRIM : 4;     /*!< [13..10] CORE LDO TEMPCO trim                                             */
18080       __IOM uint32_t CORELDOLPTRIM : 6;         /*!< [19..14] CORE LDO Low Power Trim                                          */
18081       __IOM uint32_t CORELDOIBIASTRIM : 1;      /*!< [20..20] CORE LDO IBIAS Trim                                              */
18082       __IOM uint32_t CORELDOIBIASSEL : 1;       /*!< [21..21] Core LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE
18083                                                      must be set for this to take effect.                                      */
18084             uint32_t            : 10;
18085     } LDOREG1_b;
18086   } ;
18087   __IM  uint32_t  RESERVED5;
18088 
18089   union {
18090     __IOM uint32_t LDOREG2;                     /*!< (@ 0x00000088) MEMLDO and MEMLPLDO Trims                                  */
18091 
18092     struct {
18093       __IOM uint32_t MEMLDOACTIVETRIM : 6;      /*!< [5..0] MEM LDO active trim                                                */
18094             uint32_t            : 12;
18095       __IOM uint32_t MEMLPLDOTRIM : 6;          /*!< [23..18] MEM LPLDO TRIM                                                   */
18096             uint32_t            : 8;
18097     } LDOREG2_b;
18098   } ;
18099   __IM  uint32_t  RESERVED6[21];
18100 
18101   union {
18102     __IOM uint32_t LFRC;                        /*!< (@ 0x000000E0) LFRC Control                                               */
18103 
18104     struct {
18105       __IOM uint32_t LFRCSWE    : 1;            /*!< [0..0] LFRC Software Override Enable.                                     */
18106       __IOM uint32_t TRIMTUNELFRC : 5;          /*!< [5..1] LFRC Frequency Tune trim bits                                      */
18107       __IOM uint32_t PWDLFRC    : 1;            /*!< [6..6] Power Down LFRC.                                                   */
18108       __IOM uint32_t RESETLFRC  : 1;            /*!< [7..7] LFRC Reset.                                                        */
18109       __IOM uint32_t LFRCITAILTRIM : 2;         /*!< [9..8] LFRC ITAIL trim                                                    */
18110       __IOM uint32_t LFRCSIMOCLKDIV : 3;        /*!< [12..10] SIMOBUCK LP mode clock divider                                   */
18111             uint32_t            : 19;
18112     } LFRC_b;
18113   } ;
18114   __IM  uint32_t  RESERVED7[7];
18115 
18116   union {
18117     __IOM uint32_t BODCTRL;                     /*!< (@ 0x00000100) BOD control                                                */
18118 
18119     struct {
18120       __IOM uint32_t BODLPWD    : 1;            /*!< [0..0] BODL Power Down.                                                   */
18121       __IOM uint32_t BODHPWD    : 1;            /*!< [1..1] BODH Power Down.                                                   */
18122       __IOM uint32_t BODCPWD    : 1;            /*!< [2..2] BODC Power Down.                                                   */
18123       __IOM uint32_t BODFPWD    : 1;            /*!< [3..3] BODF Power Down.                                                   */
18124       __IOM uint32_t BODSPWD    : 1;            /*!< [4..4] BODS Power Down.                                                   */
18125       __IOM uint32_t BODCLVPWD  : 1;            /*!< [5..5] BODC_LV Power Down.                                                */
18126       __IOM uint32_t BODLVREFSEL : 1;           /*!< [6..6] BODL External Reference Select. Note: the SWE mux select
18127                                                      in PWRSEQ2SWE must be set for this to take effect.                        */
18128       __IOM uint32_t BODHVREFSEL : 1;           /*!< [7..7] BODH External Reference Select. Note: the SWE mux select
18129                                                      in PWRSEQ2SWE must be set for this to take effect.                        */
18130             uint32_t            : 24;
18131     } BODCTRL_b;
18132   } ;
18133 
18134   union {
18135     __IOM uint32_t ADCPWRDLY;                   /*!< (@ 0x00000104) ADC Power Up Delay Control                                 */
18136 
18137     struct {
18138       __IOM uint32_t ADCPWR0    : 8;            /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
18139                                                      increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
18140                                                      for ADC_CLKSEL = 0x2.                                                     */
18141       __IOM uint32_t ADCPWR1    : 8;            /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
18142                                                      for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
18143                                                      = 0x2.                                                                    */
18144             uint32_t            : 16;
18145     } ADCPWRDLY_b;
18146   } ;
18147 
18148   union {
18149     __IOM uint32_t ADCPWRCTRL;                  /*!< (@ 0x00000108) ADC Power Control                                          */
18150 
18151     struct {
18152       __IOM uint32_t ADCPWRCTRLSWE : 1;         /*!< [0..0] ADC Power Control Software Override Enable                         */
18153       __IOM uint32_t ADCAPSEN   : 1;            /*!< [1..1] Enable the Global ADC Power Switch on when set to 1 if
18154                                                      the ADCPWRCTRLSWE bit is set.                                             */
18155       __IOM uint32_t ADCBPSEN   : 1;            /*!< [2..2] Enable the Analog, IO and SAR Digital logic Power Switch
18156                                                      on when set to 1 if the ADCPWRCTRLSWE bit is set.                         */
18157       __IOM uint32_t BGTPEN     : 1;            /*!< [3..3] Bandgap and Temperature Sensor Power Switch Enable                 */
18158       __IOM uint32_t BGTLPPEN   : 1;            /*!< [4..4] Bandgap and Temperature Sensor Power Switch Enable                 */
18159       __IOM uint32_t REFBUFPEN  : 1;            /*!< [5..5] Reference Buffer Power Switch Enable                               */
18160       __IOM uint32_t REFKEEPPEN : 1;            /*!< [6..6] Reference Buffer Keeper Power Switch Enable                        */
18161       __IOM uint32_t VDDADCSARISOLATE : 1;      /*!< [7..7] ISOLATE signal for Power Switched SAR ( when ADCBPSEN
18162                                                      is switched off )                                                         */
18163       __IOM uint32_t VDDADCDIGISOLATE : 1;      /*!< [8..8] ISOLATE signal for ADC Digital Contoller ( when ADCAPSEN
18164                                                      is switched off and if the ADCPWRCTRLSWE bit is set)                      */
18165       __IOM uint32_t VDDADCRESETN : 1;          /*!< [9..9] RESETN signal for Power Switched SAR and Digital Controller
18166                                                      (when global power switch is off and if the ADCPWRCTRLSWE
18167                                                      bit is set)                                                               */
18168             uint32_t            : 1;
18169       __IOM uint32_t ADCVBATDIVEN : 1;          /*!< [11..11] ADC VBAT DIV Power Enable ( if the ADCPWRCTRLSWE bit
18170                                                      is set )                                                                  */
18171       __IOM uint32_t ADCINBUFSEL : 2;           /*!< [13..12] ADC input buffer mux select                                      */
18172       __IOM uint32_t ADCINBUFEN : 1;            /*!< [14..14] ADC Input Buffer Power Enable ( if the ADCPWRCTRLSWE
18173                                                      bit is set )                                                              */
18174       __IOM uint32_t ADCRFBUFSLWEN : 1;         /*!< [15..15] ADC reference buffer slew enable                                 */
18175       __IOM uint32_t ADCKEEPOUTEN : 1;          /*!< [16..16] ADC reference keeper out en                                      */
18176             uint32_t            : 15;
18177     } ADCPWRCTRL_b;
18178   } ;
18179 
18180   union {
18181     __IOM uint32_t ADCCAL;                      /*!< (@ 0x0000010C) ADC Calibration Control                                    */
18182 
18183     struct {
18184       __IOM uint32_t CALONPWRUP : 1;            /*!< [0..0] Run ADC Calibration on initial power up sequence                   */
18185       __IOM uint32_t ADCCALIBRATED : 1;         /*!< [1..1] Status for ADC Calibration                                         */
18186             uint32_t            : 30;
18187     } ADCCAL_b;
18188   } ;
18189 
18190   union {
18191     __IOM uint32_t ADCBATTLOAD;                 /*!< (@ 0x00000110) ADC Battery Load Enable                                    */
18192 
18193     struct {
18194       __IOM uint32_t BATTLOAD   : 1;            /*!< [0..0] Enable the ADC battery load resistor                               */
18195             uint32_t            : 31;
18196     } ADCBATTLOAD_b;
18197   } ;
18198   __IM  uint32_t  RESERVED8[3];
18199 
18200   union {
18201     __IOM uint32_t XTALCTRL;                    /*!< (@ 0x00000120) XTAL Oscillator Control                                    */
18202 
18203     struct {
18204       __IOM uint32_t XTALSWE    : 1;            /*!< [0..0] XTAL Software Override Enable.                                     */
18205       __IOM uint32_t XTALCOREDISFB : 1;         /*!< [1..1] XTAL Oscillator Disable Feedback.                                  */
18206       __IOM uint32_t XTALCOMPBYPASS : 1;        /*!< [2..2] XTAL Oscillator Bypass Comparator.                                 */
18207       __IOM uint32_t XTALPDNB   : 1;            /*!< [3..3] XTAL Oscillator Power Down Core.                                   */
18208       __IOM uint32_t XTALCOMPPDNB : 1;          /*!< [4..4] XTAL Oscillator Power Down Comparator.                             */
18209       __IOM uint32_t XTALIBUFTRIM : 2;          /*!< [6..5] XTAL IBUFF trim                                                    */
18210       __IOM uint32_t XTALICOMPTRIM : 2;         /*!< [8..7] XTAL ICOMP trim                                                    */
18211             uint32_t            : 23;
18212     } XTALCTRL_b;
18213   } ;
18214 
18215   union {
18216     __IOM uint32_t XTALGENCTRL;                 /*!< (@ 0x00000124) XTAL Oscillator General Control                            */
18217 
18218     struct {
18219       __IOM uint32_t ACWARMUP   : 2;            /*!< [1..0] Auto-calibration delay control                                     */
18220       __IOM uint32_t XTALBIASTRIM : 6;          /*!< [7..2] XTAL BIAS trim                                                     */
18221       __IOM uint32_t XTALKSBIASTRIM : 6;        /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used
18222                                                      during the startup process to enable a faster lock.                       */
18223             uint32_t            : 18;
18224     } XTALGENCTRL_b;
18225   } ;
18226 
18227   union {
18228     __IOM uint32_t XTALHSTRIMS;                 /*!< (@ 0x00000128) XTALHS Trims                                               */
18229 
18230     struct {
18231       __IOM uint32_t XTALHSCAP2TRIM : 6;        /*!< [5..0] xtalhs_cap2_trim                                                   */
18232       __IOM uint32_t XTALHSCAPTRIM : 4;         /*!< [9..6] xtalhs_cap_trim                                                    */
18233       __IOM uint32_t XTALHSDRIVETRIM : 2;       /*!< [11..10] xtalhs_drive_trim                                                */
18234       __IOM uint32_t XTALHSDRIVERSTRENGTH : 3;  /*!< [14..12] xtalhs_driver_strength                                           */
18235       __IOM uint32_t XTALHSIBIASCOMP2TRIM : 2;  /*!< [16..15] xtalhs_ibias_comp2_trim                                          */
18236       __IOM uint32_t XTALHSIBIASCOMPTRIM : 4;   /*!< [20..17] xtalhs_ibias_comp_trim                                           */
18237       __IOM uint32_t XTALHSIBIASTRIM : 7;       /*!< [27..21] xtalhs_ibias_trim                                                */
18238       __IOM uint32_t XTALHSRSTRIM : 1;          /*!< [28..28] xtalhs_rs_trim                                                   */
18239       __IOM uint32_t XTALHSSPARE : 1;           /*!< [29..29] xtalhs_spare                                                     */
18240             uint32_t            : 2;
18241     } XTALHSTRIMS_b;
18242   } ;
18243 
18244   union {
18245     __IOM uint32_t XTALHSCTRL;                  /*!< (@ 0x0000012C) XTALHS Control                                             */
18246 
18247     struct {
18248       __IOM uint32_t XTALHSPDNB : 1;            /*!< [0..0] xtalhs_pdnb                                                        */
18249       __IOM uint32_t XTALHSCOMPPDNB : 1;        /*!< [1..1] xtalhs_comp_pdnb                                                   */
18250       __IOM uint32_t XTALHSCOMPSEL : 1;         /*!< [2..2] xtalhs_comp_sel                                                    */
18251       __IOM uint32_t XTALHSIBSTENABLE : 1;      /*!< [3..3] xtalhs_ibst_enable                                                 */
18252       __IOM uint32_t XTALHSINJECTIONENABLE : 1; /*!< [4..4] xtalhs_injection_enable                                            */
18253       __IOM uint32_t XTALHSPDNPNIMPROVE : 1;    /*!< [5..5] xtalhs_pdn_pn_improve                                              */
18254       __IOM uint32_t XTALHSSELRCOM : 1;         /*!< [6..6] xtalhs_sel_rcom                                                    */
18255       __IOM uint32_t XTALHSPADOUTEN : 1;        /*!< [7..7] xtalhs_padout_en                                                   */
18256       __IOM uint32_t XTALHSEXTERNALCLOCK : 1;   /*!< [8..8] xtalhs_external_clock                                              */
18257             uint32_t            : 23;
18258     } XTALHSCTRL_b;
18259   } ;
18260   __IM  uint32_t  RESERVED9[20];
18261 
18262   union {
18263     __IOM uint32_t MRAMPWRCTRL;                 /*!< (@ 0x00000180) MRAM Power Control                                         */
18264 
18265     struct {
18266       __IOM uint32_t MRAMLPREN  : 1;            /*!< [0..0] MRAM low power mode enable                                         */
18267       __IOM uint32_t MRAMSLPEN  : 1;            /*!< [1..1] MRAM sleep mode enable                                             */
18268       __IOM uint32_t MRAMPWRCTRL : 1;           /*!< [2..2] MRAM low power mode control. '0' tmc_lpr and tmc_slp
18269                                                      are driven into mcu_ctrl, '1' tmc_lpr and tmc_slp are driven
18270                                                      into MRAM wrapper.                                                        */
18271             uint32_t            : 29;
18272     } MRAMPWRCTRL_b;
18273   } ;
18274   __IM  uint32_t  RESERVED10[10];
18275 
18276   union {
18277     __IOM uint32_t BODISABLE;                   /*!< (@ 0x000001AC) Brownout Disable                                           */
18278 
18279     struct {
18280       __IOM uint32_t BODLRDE    : 1;            /*!< [0..0] Disable Unregulated 1.8V Brown-out reset.                          */
18281       __IOM uint32_t BODCREN    : 1;            /*!< [1..1] Disable VDDC Brown Out reset.                                      */
18282       __IOM uint32_t BODFREN    : 1;            /*!< [2..2] Disable VDDF Brown Out reset.                                      */
18283       __IOM uint32_t BODSREN    : 1;            /*!< [3..3] Disable VDDS Brown Out reset.                                      */
18284       __IOM uint32_t BODCLVREN  : 1;            /*!< [4..4] Disable VDDC_LV Brown Out reset.                                   */
18285             uint32_t            : 27;
18286     } BODISABLE_b;
18287   } ;
18288   __IM  uint32_t  RESERVED11[2];
18289 
18290   union {
18291     __IOM uint32_t BOOTLOADER;                  /*!< (@ 0x000001B8) Bootloader and secure boot functions                       */
18292 
18293     struct {
18294       __IOM uint32_t BOOTLOADERLOW : 1;         /*!< [0..0] Determines whether the bootloader code is visible at
18295                                                      address 0x00000000 or not. Resets to 1, write 1 to clear.                 */
18296       __IOM uint32_t SBRLOCK    : 1;            /*!< [1..1] Secure boot ROM lock. Always resets to 1, write 1 to
18297                                                      clear. Enables system visibility to bootloader until set.                 */
18298       __IOM uint32_t PROTLOCK   : 1;            /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to
18299                                                      clear. Enables writes to flash protection register set.                   */
18300       __IOM uint32_t SBLLOCK    : 1;            /*!< [3..3] Secure boot loader lock. Always resets to 1, write 1
18301                                                      to clear. Enables system visibility to bootloader until
18302                                                      set.                                                                      */
18303             uint32_t            : 22;
18304       __IOM uint32_t SECBOOTFEATURE : 2;        /*!< [27..26] Indicates whether the secure boot feature is enabled.            */
18305       __IOM uint32_t SECBOOT    : 2;            /*!< [29..28] Indicates whether the secure boot on cold reset is
18306                                                      enabled                                                                   */
18307       __IOM uint32_t SECBOOTONRST : 2;          /*!< [31..30] Indicates whether the secure boot on warm reset is
18308                                                      enabled                                                                   */
18309     } BOOTLOADER_b;
18310   } ;
18311 
18312   union {
18313     __IOM uint32_t SHADOWVALID;                 /*!< (@ 0x000001BC) Register to indicate whether the shadow registers
18314                                                                     have been successfully loaded from the Flash
18315                                                                     Information Space.                                         */
18316 
18317     struct {
18318       __IOM uint32_t VALID      : 1;            /*!< [0..0] Indicates whether the shadow registers contain valid
18319                                                      data from the Flash Information Space.                                    */
18320       __IOM uint32_t BLDSLEEP   : 1;            /*!< [1..1] Indicates whether the bootloader should sleep or deep
18321                                                      sleep if no image loaded.                                                 */
18322       __IOM uint32_t INFO0VALID : 1;            /*!< [2..2] Indicates whether info0 contains valid data                        */
18323             uint32_t            : 29;
18324     } SHADOWVALID_b;
18325   } ;
18326 
18327   union {
18328     __IOM uint32_t SCRATCH0;                    /*!< (@ 0x000001C0) Scratch register that is not reset by any reset            */
18329 
18330     struct {
18331       __IOM uint32_t HALTREQ    : 1;            /*!< [0..0] Reset-Halt requested from debugger.                                */
18332             uint32_t            : 31;
18333     } SCRATCH0_b;
18334   } ;
18335   __IM  uint32_t  RESERVED12[15];
18336 
18337   union {
18338     __IOM uint32_t DBGR1;                       /*!< (@ 0x00000200) Read-only debug 1                                          */
18339 
18340     struct {
18341       __IOM uint32_t ONETO8     : 32;           /*!< [31..0] Read-only register for communication validation                   */
18342     } DBGR1_b;
18343   } ;
18344 
18345   union {
18346     __IOM uint32_t DBGR2;                       /*!< (@ 0x00000204) Read-only debug 2                                          */
18347 
18348     struct {
18349       __IOM uint32_t COOLCODE   : 32;           /*!< [31..0] Read-only register for communication validation                   */
18350     } DBGR2_b;
18351   } ;
18352   __IM  uint32_t  RESERVED13[6];
18353 
18354   union {
18355     __IOM uint32_t PMUENABLE;                   /*!< (@ 0x00000220) Control bit to enable/disable the PMU                      */
18356 
18357     struct {
18358       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will
18359                                                      place the MCU into the lowest power consuming Deep Sleep
18360                                                      mode upon execution of a WFI instruction (dependent on
18361                                                      the setting of the SLEEPDEEP bit in the ARM SCR register).
18362                                                      When cleared, regardless of the requested sleep mode, the
18363                                                      PMU will not enter the lowest power Deep Sleep mode, instead
18364                                                      entering the Sleep mode.                                                  */
18365             uint32_t            : 31;
18366     } PMUENABLE_b;
18367   } ;
18368   __IM  uint32_t  RESERVED14[11];
18369 
18370   union {
18371     __IOM uint32_t DBGCTRL;                     /*!< (@ 0x00000250) Debug subsystem Control. Determines the debug
18372                                                                     components enable and clk frequency.                       */
18373 
18374     struct {
18375       __IOM uint32_t CM4TPIUENABLE : 1;         /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled
18376                                                      and data can be streamed out of the MCU's SWO port using
18377                                                      the ARM ITM and TPIU modules.                                             */
18378       __IOM uint32_t CM4CLKSEL  : 3;            /*!< [3..1] This field selects the frequency of the ARM M4 TPIU port.          */
18379       __IOM uint32_t DBGTPIUENABLE : 1;         /*!< [4..4] TPIU Enable field. When set, the Debug Trace TPIU is
18380                                                      enabled and data can be streamed out of the MCU ETM or
18381                                                      DSP TRAXs.                                                                */
18382       __IOM uint32_t DBGCLKSEL  : 3;            /*!< [7..5] This field selects the frequency of the Debug Trace TPIU
18383                                                      port.                                                                     */
18384       __IOM uint32_t DBGETBENABLE : 1;          /*!< [8..8] Debug subsystem ETB enable to store the trace data.                */
18385       __IOM uint32_t DBGETMTRACEEN : 1;         /*!< [9..9] Debug subsystem ETM trace enable                                   */
18386       __IOM uint32_t DBGDSP0TRACEEN : 1;        /*!< [10..10] Debug subsystem DSP0 trace enable                                */
18387       __IOM uint32_t DBGDSP1TRACEEN : 1;        /*!< [11..11] Debug subsystem DSP1 trace enable                                */
18388       __IOM uint32_t DBGTSCLKSEL : 3;           /*!< [14..12] This field selects the frequency of the ARM M4 dbg
18389                                                      ts port.                                                                  */
18390             uint32_t            : 1;
18391       __IOM uint32_t DBGDSP0OCDHALTONRST : 1;   /*!< [16..16] Debug subsystem DSP0 OCD Halt on Reset                           */
18392       __IOM uint32_t DBGDSP1OCDHALTONRST : 1;   /*!< [17..17] Debug subsystem DSP1 OCD Halt on Reset                           */
18393             uint32_t            : 14;
18394     } DBGCTRL_b;
18395   } ;
18396   __IM  uint32_t  RESERVED15[4];
18397 
18398   union {
18399     __IOM uint32_t OTAPOINTER;                  /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset
18400                                                                     only by POA                                                */
18401 
18402     struct {
18403       __IOM uint32_t OTAVALID   : 1;            /*!< [0..0] Indicates that an OTA update is valid                              */
18404       __IOM uint32_t OTASBLUPDATE : 1;          /*!< [1..1] Indicates that the sbl_init has been updated                       */
18405       __IOM uint32_t OTAPOINTER : 30;           /*!< [31..2] Flash page pointer with updated OTA image                         */
18406     } OTAPOINTER_b;
18407   } ;
18408   __IM  uint32_t  RESERVED16[6];
18409 
18410   union {
18411     __IOM uint32_t APBDMACTRL;                  /*!< (@ 0x00000280) DMA Control Register. Determines misc settings
18412                                                                     for DMA operation                                          */
18413 
18414     struct {
18415       __IOM uint32_t DMAENABLE  : 1;            /*!< [0..0] Enable the DMA controller. When disabled, DMA requests
18416                                                      will be ignored by the controller                                         */
18417       __IOM uint32_t DECODEABORT : 1;           /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue
18418                                                      a data abort (bus fault) on transactions to peripherals
18419                                                      that are powered down. When set to 0, writes are quietly
18420                                                      discarded and reads return 0.                                             */
18421             uint32_t            : 6;
18422       __IOM uint32_t HYSTERESIS : 8;            /*!< [15..8] This field determines how long the DMA engine of apb/disp/gfx
18423                                                      will remain active during deep sleep before shutting down
18424                                                      and returning the system to full deep sleep. Values are
18425                                                      based on a 94KHz clock and are roughly 10us increments
18426                                                      for a range of ~10us to 2.55ms                                            */
18427             uint32_t            : 16;
18428     } APBDMACTRL_b;
18429   } ;
18430   __IM  uint32_t  RESERVED17[45];
18431 
18432   union {
18433     __IOM uint32_t KEXTCLKSEL;                  /*!< (@ 0x00000338) Locks the state of the EXTCLKSEL register from
18434                                                                     writes. This is done to prevent errant writes
18435                                                                     to the register, as this could cause the
18436                                                                     chip to halt. Write a value of 0x53 to unlock
18437                                                                     write access to the EXTCLKSEL register.
18438                                                                     Once unlocked, the register will read back
18439                                                                     a 1 to undicate this is unlocked. Writing
18440                                                                     the register with any other value other
18441                                                                     than 0x53 will enable the lock.                            */
18442 
18443     struct {
18444       __IOM uint32_t KEXTCLKSEL : 32;           /*!< [31..0] Key register value.                                               */
18445     } KEXTCLKSEL_b;
18446   } ;
18447 
18448   union {
18449     __IOM uint32_t SIMOBUCK0;                   /*!< (@ 0x0000033C) This WRITE_ONLY register controls various buck
18450                                                                     parameters. It will read back as 0x00000000.               */
18451 
18452     struct {
18453       __IOM uint32_t VDDCRXCOMPEN : 1;          /*!< [0..0] Enable the VDDC rail.                                              */
18454       __IOM uint32_t VDDFRXCOMPEN : 1;          /*!< [1..1] Enable the VDDS rail.                                              */
18455       __IOM uint32_t VDDSRXCOMPEN : 1;          /*!< [2..2] Enable the VDDS rail.                                              */
18456       __IOM uint32_t VDDCLVRXCOMPEN : 1;        /*!< [3..3] Enable the VDDC LV rail.                                           */
18457       __IOM uint32_t TONTOFFNODEGLITCH : 1;     /*!< [4..4] Enable the ton and toff signals no deglitch output.                */
18458             uint32_t            : 27;
18459     } SIMOBUCK0_b;
18460   } ;
18461 
18462   union {
18463     __IOM uint32_t SIMOBUCK1;                   /*!< (@ 0x00000340) 1. Control the even division of 3 clocks: refresh,
18464                                                                     low power and TONCLK. 2. Control gap bewteen
18465                                                                     secondary switches. 3. Debug features: control
18466                                                                     the amount of time TONCLK is on, and the
18467                                                                     time before snubber asserts for each buck
18468                                                                     sequence. 4. Enable or disable the observation
18469                                                                     bus. 5. Select the buck sequence operation
18470                                                                     mode. 6. Control delay between primary Pmos
18471                                                                     and Nmos transitions.                                      */
18472 
18473     struct {
18474             uint32_t            : 6;
18475       __IOM uint32_t SIMOBUCKRXCLKACTTRIM : 5;  /*!< [10..6] This divides the 5 MHz refresh clock. Even divides are
18476                                                      supported only. This value represents the division amount
18477                                                      minus 1.                                                                  */
18478             uint32_t            : 11;
18479       __IOM uint32_t SIMOBUCKTONCLKTRIM : 4;    /*!< [25..22] This divides the 100 MHz ton clock. Even divides are
18480                                                      supported only. This value represents the division amount
18481                                                      minus 1.                                                                  */
18482             uint32_t            : 6;
18483     } SIMOBUCK1_b;
18484   } ;
18485 
18486   union {
18487     __IOM uint32_t SIMOBUCK2;                   /*!< (@ 0x00000344) SIMO Buck Muxed VDDC Active Sequence Trim Control          */
18488 
18489     struct {
18490             uint32_t            : 11;
18491       __IOM uint32_t SIMOBUCKVDDCACTHIGHTONTRIM : 4;/*!< [14..11] VDDC active high ton trim control for Buck sequence.         */
18492             uint32_t            : 9;
18493       __IOM uint32_t SIMOBUCKVDDCACTLOWTONTRIM : 4;/*!< [27..24] VDDC active high ton trim control for Buck sequence.          */
18494             uint32_t            : 4;
18495     } SIMOBUCK2_b;
18496   } ;
18497 
18498   union {
18499     __IOM uint32_t SIMOBUCK3;                   /*!< (@ 0x00000348) SIMO Buck Muxed VDDC low power Sequence Trim
18500                                                                     Control                                                    */
18501 
18502     struct {
18503             uint32_t            : 2;
18504       __IOM uint32_t SIMOBUCKVDDCLPDRVSTRTRIM : 2;/*!< [3..2] VDDC LP trim control for drive strength.                         */
18505             uint32_t            : 4;
18506       __IOM uint32_t SIMOBUCKVDDCLPHIGHTOFFTRIM : 5;/*!< [12..8] VDDC LP high toff trim control for Buck sequence.             */
18507       __IOM uint32_t SIMOBUCKVDDCLPHIGHTONTRIM : 4;/*!< [16..13] VDDC LP high ton trim control for Buck sequence.              */
18508             uint32_t            : 4;
18509       __IOM uint32_t SIMOBUCKVDDCLPLOWTOFFTRIM : 5;/*!< [25..21] VDDC LP low toff trim control for Buck sequence.              */
18510       __IOM uint32_t SIMOBUCKVDDCLPLOWTONTRIM : 4;/*!< [29..26] VDDC LP low ton trim control for Buck sequence.                */
18511             uint32_t            : 2;
18512     } SIMOBUCK3_b;
18513   } ;
18514 
18515   union {
18516     __IOM uint32_t SIMOBUCK4;                   /*!< (@ 0x0000034C) SIMO Buck Muxed VDDC LV Active Sequence Trim
18517                                                                     Control                                                    */
18518 
18519     struct {
18520       __IOM uint32_t VDDCLVACTDRVSTRTRIM : 2;   /*!< [1..0] VDDC LV active trim control for drive strength.                    */
18521             uint32_t            : 4;
18522       __IOM uint32_t VDDCLVACTHIGHTOFFTRIM : 5; /*!< [10..6] VDDC LV active high toff trim control for Buck sequence.          */
18523       __IOM uint32_t VDDCLVACTHIGHTONTRIM : 4;  /*!< [14..11] VDDC LV active high ton trim control for Buck sequence.          */
18524             uint32_t            : 4;
18525       __IOM uint32_t VDDCLVACTLOWTOFFTRIM : 5;  /*!< [23..19] VDDC LV active low trim control for a 500 MHz clock
18526                                                      inside the simobuck analog design.                                        */
18527       __IOM uint32_t VDDCLVACTLOWTONTRIM : 4;   /*!< [27..24] VDDC LV active low ton trim control for Buck sequence.           */
18528             uint32_t            : 4;
18529     } SIMOBUCK4_b;
18530   } ;
18531   __IM  uint32_t  RESERVED18;
18532 
18533   union {
18534     __IOM uint32_t SIMOBUCK6;                   /*!< (@ 0x00000354) SIMO Buck Muxed VDDF Active Sequence Trim Control          */
18535 
18536     struct {
18537             uint32_t            : 17;
18538       __IOM uint32_t SIMOBUCKVDDFACTHIGHTONTRIM : 4;/*!< [20..17] VDDF active high ton trim control for Buck sequence.         */
18539             uint32_t            : 11;
18540     } SIMOBUCK6_b;
18541   } ;
18542 
18543   union {
18544     __IOM uint32_t SIMOBUCK7;                   /*!< (@ 0x00000358) SIMO Buck Muxed VDDF active Sequence Trim Control          */
18545 
18546     struct {
18547             uint32_t            : 4;
18548       __IOM uint32_t VDDFACTLOWTOFFTRIM : 5;    /*!< [8..4] VDDF active low toff trim control for Buck sequence.               */
18549       __IOM uint32_t VDDFACTLOWTONTRIM : 4;     /*!< [12..9] VDDF active low ton trim control for Buck sequence.               */
18550       __IOM uint32_t VDDFLPDRVSTRTRIM : 2;      /*!< [14..13] VDDF active trim control for drive strength.                     */
18551             uint32_t            : 3;
18552       __IOM uint32_t ZXCOMPZXTRIM : 5;          /*!< [22..18] Zxcomp trim. Feedthrough to analog.                              */
18553             uint32_t            : 9;
18554     } SIMOBUCK7_b;
18555   } ;
18556 
18557   union {
18558     __IOM uint32_t SIMOBUCK8;                   /*!< (@ 0x0000035C) SIMO Buck Muxed VDDF Low Power Sequence Trim
18559                                                                     Control                                                    */
18560 
18561     struct {
18562             uint32_t            : 4;
18563       __IOM uint32_t SIMOBUCKVDDFLPHIGHTOFFTRIM : 5;/*!< [8..4] VDDF low power high toff trim control for Buck sequence.       */
18564       __IOM uint32_t SIMOBUCKVDDFLPHIGHTONTRIM : 4;/*!< [12..9] VDDF low power high ton trim control for Buck sequence.        */
18565             uint32_t            : 4;
18566       __IOM uint32_t SIMOBUCKVDDFLPLOWTOFFTRIM : 5;/*!< [21..17] VDDF low power low toff trim control for Buck sequence.       */
18567       __IOM uint32_t SIMOBUCKVDDFLPLOWTONTRIM : 4;/*!< [25..22] VDDF low power low ton trim control for Buck sequence.         */
18568             uint32_t            : 6;
18569     } SIMOBUCK8_b;
18570   } ;
18571 
18572   union {
18573     __IOM uint32_t SIMOBUCK9;                   /*!< (@ 0x00000360) SIMO Buck Muxed VDDS Active Sequence Trim Control          */
18574 
18575     struct {
18576             uint32_t            : 17;
18577       __IOM uint32_t SIMOBUCKVDDSACTHIGHTONTRIM : 4;/*!< [20..17] VDDS active high ton trim control for Buck sequence.         */
18578             uint32_t            : 1;
18579       __IOM uint32_t SIMOBUCKVDDSACTLOWTONTRIM : 4;/*!< [25..22] VDDS active low ton trim control for Buck sequence.           */
18580             uint32_t            : 6;
18581     } SIMOBUCK9_b;
18582   } ;
18583   __IM  uint32_t  RESERVED19[2];
18584 
18585   union {
18586     __IOM uint32_t SIMOBUCK12;                  /*!< (@ 0x0000036C) SIMO Buck Compare, Brown out, Active, Low power
18587                                                                     Trim Control                                               */
18588 
18589     struct {
18590       __IOM uint32_t VDDCLVCOMPTRIMMINUS : 5;   /*!< [4..0] Static trim to allow separation between low power and
18591                                                      active rail.                                                              */
18592       __IOM uint32_t VDDCLVCOMPTRIMPLUS : 5;    /*!< [9..5] Static trim to allow separation when low power GT active
18593                                                      rail.                                                                     */
18594       __IOM uint32_t VDDCLVBRNOUTTRIM : 10;     /*!< [19..10] Digital brown out max counter value for VDDC LV rail.            */
18595       __IOM uint32_t ACTTRIMVDDF : 6;           /*!< [25..20] Active VDDF trim.                                                */
18596       __IOM uint32_t LPTRIMVDDF : 6;            /*!< [31..26] Low power VDDF trim.                                             */
18597     } SIMOBUCK12_b;
18598   } ;
18599 
18600   union {
18601     __IOM uint32_t SIMOBUCK13;                  /*!< (@ 0x00000370) SIMO Buck Compare, Brown out, Active, Low power
18602                                                                     Trim Control                                               */
18603 
18604     struct {
18605             uint32_t            : 20;
18606       __IOM uint32_t SIMOBUCKACTTRIMVDDS : 6;   /*!< [25..20] Active VDDS trim.                                                */
18607       __IOM uint32_t SIMOBUCKLPTRIMVDDS : 6;    /*!< [31..26] Low power VDDS trim.                                             */
18608     } SIMOBUCK13_b;
18609   } ;
18610   __IM  uint32_t  RESERVED20;
18611 
18612   union {
18613     __IOM uint32_t SIMOBUCK15;                  /*!< (@ 0x00000378) SIMO Buck Compare, Brown out, Active and Low
18614                                                                     power Trim Control                                         */
18615 
18616     struct {
18617       __IOM uint32_t VDDCCOMPTRIMMINUS : 5;     /*!< [4..0] Static trim to allow separation between low power and
18618                                                      active rail.                                                              */
18619       __IOM uint32_t VDDCCOMPTRIMPLUS : 5;      /*!< [9..5] Static trim to allow separation when low power GT active
18620                                                      rail.                                                                     */
18621       __IOM uint32_t VDDCBRNOUTTRIM : 10;       /*!< [19..10] Digital brown out max counter value for VDDC rail.               */
18622       __IOM uint32_t VDDCLVRXCOMPTRIMEN : 1;    /*!< [20..20] Enable the VDDC LV rail. If not enabled, the rail will
18623                                                      not be regulated. This must be done before simobuck comes
18624                                                      up.                                                                       */
18625       __IOM uint32_t VDDSRXCOMPTRIMEN : 1;      /*!< [21..21] Enable the VDDS rail. If not enabled, the rail will
18626                                                      not be regulated. This must be done before simobuck comes
18627                                                      up.                                                                       */
18628       __IOM uint32_t VDDFRXCOMPTRIMEN : 1;      /*!< [22..22] Enable the VDDF rail. If not enabled, the rail will
18629                                                      not be regulated. This must be done before simobuck comes
18630                                                      up.                                                                       */
18631       __IOM uint32_t VDDCRXCOMPTRIMEN : 1;      /*!< [23..23] Enable the VDDC rail. If not enabled, the rail will
18632                                                      not be regulated. This must be done before simobuck comes
18633                                                      up.                                                                       */
18634       __IOM uint32_t ZXCOMPOFFSETTRIM : 5;      /*!< [28..24] Zxcomp offset trim. Feedthrough to analog.                       */
18635             uint32_t            : 2;
18636       __IOM uint32_t TRIMLATCHOVER : 1;         /*!< [31..31] Override / Bypass the simobuck trim latch to enable
18637                                                      on-the-fly trimming for VDDF and VDDS active and LP trims                 */
18638     } SIMOBUCK15_b;
18639   } ;
18640 
18641   union {
18642     __IOM uint32_t PWRSW0;                      /*!< (@ 0x0000037C) PWRSW Control 0                                            */
18643 
18644     struct {
18645       __IOM uint32_t PWRSWVDDCPUDYNSEL : 2;     /*!< [1..0] override value for pwrsw_vddcpu_dynsel                             */
18646             uint32_t            : 1;
18647       __IOM uint32_t PWRSWVDDCPUOVERRIDE : 1;   /*!< [3..3] override enable for pwrsw_vddcpu_dynsel and pgn                    */
18648       __IOM uint32_t PWRSWVDDCAORDYNSEL : 2;    /*!< [5..4] override value for pwrsw_vddcaor_dynsel                            */
18649       __IOM uint32_t PWRSWVDDCAOROVERRIDE : 1;  /*!< [6..6] override enable for pwrsw_vddcaor_dynsel                           */
18650             uint32_t            : 8;
18651       __IOM uint32_t PWRSWVDDMCPUDYNSEL : 1;    /*!< [15..15] override value for pwrsw_vddmcpu_dynsel                          */
18652       __IOM uint32_t PWRSWVDDMCPUSTATSEL : 1;   /*!< [16..16] VDDMCPU power switch static select                               */
18653       __IOM uint32_t PWRSWVDDMCPUOVERRIDE : 1;  /*!< [17..17] override enable for pwrsw_vddmcpu_dynsel                         */
18654       __IOM uint32_t PWRSWVDDMDSP0DYNSEL : 1;   /*!< [18..18] override value for pwrsw_vddmdsp0_dynsel                         */
18655       __IOM uint32_t PWRSWVDDMDSP0STATSEL : 1;  /*!< [19..19] VDDMDSP0 power switch static select                              */
18656       __IOM uint32_t PWRSWVDDMDSP0OVERRIDE : 1; /*!< [20..20] override enable for pwrsw_vddmdsp0_dynsel                        */
18657       __IOM uint32_t PWRSWVDDMDSP1DYNSEL : 1;   /*!< [21..21] override value for pwrsw_vddmdsp1_dynsel                         */
18658       __IOM uint32_t PWRSWVDDMDSP1STATSEL : 1;  /*!< [22..22] VDDMDSP1 power switch static select                              */
18659       __IOM uint32_t PWRSWVDDMDSP1OVERRIDE : 1; /*!< [23..23] override enable for pwrsw_vddmdsp1_dynsel                        */
18660       __IOM uint32_t PWRSWVDDMLDYNSEL : 1;      /*!< [24..24] override value for pwrsw_vddml_dynsel                            */
18661             uint32_t            : 1;
18662       __IOM uint32_t PWRSWVDDMLOVERRIDE : 1;    /*!< [26..26] override enable for pwrsw_vddml_dynsel                           */
18663       __IOM uint32_t PWRSWVDDRCPUDYNSEL : 2;    /*!< [28..27] override value for pwrsw_vddrcpu_dynsel                          */
18664             uint32_t            : 1;
18665       __IOM uint32_t PWRSWVDDRCPUSTATSEL : 1;   /*!< [30..30] VDDRCPU power switch static select                               */
18666       __IOM uint32_t PWRSWVDDRCPUOVERRIDE : 1;  /*!< [31..31] override enable for pwrsw_vddrcpu_dynsel and pgn                 */
18667     } PWRSW0_b;
18668   } ;
18669 
18670   union {
18671     __IOM uint32_t PWRSW1;                      /*!< (@ 0x00000380) PWRSW Control 1                                            */
18672 
18673     struct {
18674             uint32_t            : 25;
18675       __IOM uint32_t USEVDDF4VDDRCPUINHP : 1;   /*!< [25..25] Setting this bit selects VDDF for VDDRCPU in when MCU
18676                                                      is in HP mode. This is valid for only normal operational
18677                                                      mode (i.e without overrides).                                             */
18678             uint32_t            : 2;
18679       __IOM uint32_t SHORTVDDCVDDCLVOREN : 1;   /*!< [28..28] pwrsw short override select for vddc/vddclv                      */
18680       __IOM uint32_t SHORTVDDCVDDCLVORVAL : 1;  /*!< [29..29] pwrsw short override value for vddc/vddclv                       */
18681       __IOM uint32_t SHORTVDDFVDDSOREN : 1;     /*!< [30..30] pwrsw short override select for vddf/vdds                        */
18682       __IOM uint32_t SHORTVDDFVDDSORVAL : 1;    /*!< [31..31] pwrsw short override value for vddf/vdds                         */
18683     } PWRSW1_b;
18684   } ;
18685   __IM  uint32_t  RESERVED21[9];
18686 
18687   union {
18688     __IOM uint32_t FLASHWPROT0;                 /*!< (@ 0x000003A8) These bits write-protect flash in 16KB chunks.             */
18689 
18690     struct {
18691       __IOM uint32_t FW0BITS    : 32;           /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit
18692                                                      provides write protection for 16KB chunks of flash data
18693                                                      space. Bits are cleared by writing a 1 to the bit. When
18694                                                      read, 0 indicates the region is protected. Bits are sticky
18695                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18696     } FLASHWPROT0_b;
18697   } ;
18698 
18699   union {
18700     __IOM uint32_t FLASHWPROT1;                 /*!< (@ 0x000003AC) These bits write-protect flash in 16KB chunks.             */
18701 
18702     struct {
18703       __IOM uint32_t FW1BITS    : 32;           /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit
18704                                                      provides write protection for 16KB chunks of flash data
18705                                                      space. Bits are cleared by writing a 1 to the bit. When
18706                                                      read, 0 indicates the region is protected. Bits are sticky
18707                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18708     } FLASHWPROT1_b;
18709   } ;
18710 
18711   union {
18712     __IOM uint32_t FLASHWPROT2;                 /*!< (@ 0x000003B0) These bits write-protect flash in 16KB chunks.             */
18713 
18714     struct {
18715       __IOM uint32_t FW2BITS    : 32;           /*!< [31..0] Write protect flash 0x00100000 - 0x0017FFFF. Each bit
18716                                                      provides write protection for 16KB chunks of flash data
18717                                                      space. Bits are cleared by writing a 1 to the bit. When
18718                                                      read, 0 indicates the region is protected. Bits are sticky
18719                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18720     } FLASHWPROT2_b;
18721   } ;
18722 
18723   union {
18724     __IOM uint32_t FLASHWPROT3;                 /*!< (@ 0x000003B4) These bits write-protect flash in 16KB chunks.             */
18725 
18726     struct {
18727       __IOM uint32_t FW3BITS    : 32;           /*!< [31..0] Write protect flash 0x00180000 - 0x001FFFFF. Each bit
18728                                                      provides write protection for 16KB chunks of flash data
18729                                                      space. Bits are cleared by writing a 1 to the bit. When
18730                                                      read, 0 indicates the region is protected. Bits are sticky
18731                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18732     } FLASHWPROT3_b;
18733   } ;
18734 
18735   union {
18736     __IOM uint32_t FLASHRPROT0;                 /*!< (@ 0x000003B8) These bits read-protect flash in 16KB chunks.              */
18737 
18738     struct {
18739       __IOM uint32_t FR0BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each
18740                                                      bit provides read protection for 16KB chunks of flash.
18741                                                      Bits are cleared by writing a 1 to the bit. When read,
18742                                                      0 indicates the region is protected. Bits are sticky (can
18743                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18744     } FLASHRPROT0_b;
18745   } ;
18746 
18747   union {
18748     __IOM uint32_t FLASHRPROT1;                 /*!< (@ 0x000003BC) These bits read-protect flash in 16KB chunks.              */
18749 
18750     struct {
18751       __IOM uint32_t FR1BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each
18752                                                      bit provides read protection for 16KB chunks of flash.
18753                                                      Bits are cleared by writing a 1 to the bit. When read,
18754                                                      0 indicates the region is protected. Bits are sticky (can
18755                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18756     } FLASHRPROT1_b;
18757   } ;
18758 
18759   union {
18760     __IOM uint32_t FLASHRPROT2;                 /*!< (@ 0x000003C0) These bits read-protect flash in 16KB chunks.              */
18761 
18762     struct {
18763       __IOM uint32_t FR2BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each
18764                                                      bit provides read protection for 16KB chunks of flash.
18765                                                      Bits are cleared by writing a 1 to the bit. When read,
18766                                                      0 indicates the region is protected. Bits are sticky (can
18767                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18768     } FLASHRPROT2_b;
18769   } ;
18770 
18771   union {
18772     __IOM uint32_t FLASHRPROT3;                 /*!< (@ 0x000003C4) These bits read-protect flash in 16KB chunks.              */
18773 
18774     struct {
18775       __IOM uint32_t FR3BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each
18776                                                      bit provides read protection for 16KB chunks of flash.
18777                                                      Bits are cleared by writing a 1 to the bit. When read,
18778                                                      0 indicates the region is protected. Bits are sticky (can
18779                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18780     } FLASHRPROT3_b;
18781   } ;
18782 
18783   union {
18784     __IOM uint32_t DMASRAMWPROT0;               /*!< (@ 0x000003C8) These bits write-protect system SRAM from DMA
18785                                                                     operations in 8KB chunks.                                  */
18786 
18787     struct {
18788       __IOM uint32_t DMAWPROT0  : 32;           /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
18789                                                      protection for an 8KB region of memory. When set to 1,
18790                                                      the region will be protected from DMA writes, when set
18791                                                      to 0, DMA may write the region.                                           */
18792     } DMASRAMWPROT0_b;
18793   } ;
18794 
18795   union {
18796     __IOM uint32_t DMASRAMWPROT1;               /*!< (@ 0x000003CC) These bits write-protect system SRAM from DMA
18797                                                                     operations in 8KB chunks.                                  */
18798 
18799     struct {
18800       __IOM uint32_t DMAWPROT1  : 16;           /*!< [15..0] Write protect SRAM from DMA. Each bit provides write
18801                                                      protection for an 8KB region of memory. When set to 1,
18802                                                      the region will be protected from DMA writes, when set
18803                                                      to 0, DMA may write the region.                                           */
18804             uint32_t            : 16;
18805     } DMASRAMWPROT1_b;
18806   } ;
18807 
18808   union {
18809     __IOM uint32_t DMASRAMRPROT0;               /*!< (@ 0x000003D0) These bits read-protect system SRAM from DMA
18810                                                                     operations in 8KB chunks.                                  */
18811 
18812     struct {
18813       __IOM uint32_t DMARPROT0  : 32;           /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
18814                                                      protection for an 8KB region of memory. When set to 1,
18815                                                      the region will be protected from DMA reads, when set to
18816                                                      0, DMA may read the region.                                               */
18817     } DMASRAMRPROT0_b;
18818   } ;
18819 
18820   union {
18821     __IOM uint32_t DMASRAMRPROT1;               /*!< (@ 0x000003D4) These bits read-protect system SRAM from DMA
18822                                                                     operations in 8KB chunks.                                  */
18823 
18824     struct {
18825       __IOM uint32_t DMARPROT1  : 16;           /*!< [15..0] Read protect SRAM from DMA. Each bit provides write
18826                                                      protection for an 8KB region of memory. When set to 1,
18827                                                      the region will be protected from DMA reads, when set to
18828                                                      0, DMA may read the region.                                               */
18829             uint32_t            : 16;
18830     } DMASRAMRPROT1_b;
18831   } ;
18832   __IM  uint32_t  RESERVED22[16];
18833 
18834   union {
18835     __IOM uint32_t USBPHYRESET;                 /*!< (@ 0x00000418) DSP0 CACHE RAM TRIM                                        */
18836 
18837     struct {
18838       __IOM uint32_t USBPHYPORRSTDIS : 1;       /*!< [0..0] De-assert USB PHY POR reset override                               */
18839       __IOM uint32_t USBPHYUTMIRSTDIS : 1;      /*!< [1..1] De-assert USB PHY UTMI reset override                              */
18840             uint32_t            : 30;
18841     } USBPHYRESET_b;
18842   } ;
18843   __IM  uint32_t  RESERVED23[4];
18844 
18845   union {
18846     __IOM uint32_t AUDADCPWRCTRL;               /*!< (@ 0x0000042C) Audio ADC Power Control                                    */
18847 
18848     struct {
18849       __IOM uint32_t AUDADCPWRCTRLSWE : 1;      /*!< [0..0] Audio ADC Power Control Software Override Enable                   */
18850       __IOM uint32_t AUDADCAPSEN : 1;           /*!< [1..1] Enable the Global audio ADC Power Switch on when set
18851                                                      to 1 if the AUDADCPWRCTRLSWE bit is set.                                  */
18852       __IOM uint32_t AUDADCBPSEN : 1;           /*!< [2..2] Enable the Analog, IO and SAR Digital logic Power Switch
18853                                                      on when set to 1 if the AUDADCPWRCTRLSWE bit is set.                      */
18854       __IOM uint32_t AUDBGTPEN  : 1;            /*!< [3..3] Bandgap and Temperature Sensor Power Switch Enable                 */
18855       __IOM uint32_t AUDREFBUFPEN : 1;          /*!< [4..4] Reference Buffer Power Switch Enable                               */
18856       __IOM uint32_t AUDREFKEEPPEN : 1;         /*!< [5..5] Reference Buffer Keeper Power Switch Enable                        */
18857             uint32_t            : 2;
18858       __IOM uint32_t VDDAUDADCSARISOLATE : 1;   /*!< [8..8] ISOLATE signal for Power Switched SAR ( when AUDADCBPSEN
18859                                                      is switched off )                                                         */
18860       __IOM uint32_t VDDAUDADCDIGISOLATE : 1;   /*!< [9..9] ISOLATE signal for audio ADC Digital Contoller ( when
18861                                                      AUDADCAPSEN is switched off and if the AUDADCPWRCTRLSWE
18862                                                      bit is set)                                                               */
18863       __IOM uint32_t VDDAUDADCRESETN : 1;       /*!< [10..10] RESETN signal for Power Switched SAR and Digital Controller
18864                                                      (when global power switch is off and if the AUDADCPWRCTRLSWE
18865                                                      bit is set)                                                               */
18866             uint32_t            : 1;
18867       __IOM uint32_t AUDADCVBATDIVEN : 1;       /*!< [12..12] Audio ADC VBAT DIV Power Enable ( if the AUDADCPWRCTRLSWE
18868                                                      bit is set )                                                              */
18869             uint32_t            : 1;
18870       __IOM uint32_t AUDADCINBUFSEL : 2;        /*!< [15..14] Audio ADC input buffer mux select                                */
18871       __IOM uint32_t AUDADCINBUFEN : 1;         /*!< [16..16] Audio ADC Input Buffer Power Enable ( if the AUDADCPWRCTRLSWE
18872                                                      bit is set )                                                              */
18873       __IOM uint32_t AUDADCRFBUFSLWEN : 1;      /*!< [17..17] Audio ADC reference buffer slew enable                           */
18874       __IOM uint32_t AUDADCKEEPOUTEN : 1;       /*!< [18..18] Audio ADC reference keeper out en                                */
18875             uint32_t            : 13;
18876     } AUDADCPWRCTRL_b;
18877   } ;
18878 
18879   union {
18880     __IOM uint32_t AUDIO1;                      /*!< (@ 0x00000430) Audio trims 1                                              */
18881 
18882     struct {
18883             uint32_t            : 6;
18884       __IOM uint32_t MICBIASVOLTAGETRIM : 6;    /*!< [11..6] Output voltage trim                                               */
18885       __IOM uint32_t MICBIASPDNB : 1;           /*!< [12..12] Power down control for the block                                 */
18886             uint32_t            : 19;
18887     } AUDIO1_b;
18888   } ;
18889   __IM  uint32_t  RESERVED24;
18890 
18891   union {
18892     __IOM uint32_t PGAADCIFCTRL;                /*!< (@ 0x00000438) PGA ADCIF control                                          */
18893 
18894     struct {
18895       __IOM uint32_t PGAADCIFCHAACTIVE : 2;     /*!< [1..0] PGAADCIF active signal for channels A0 and A1. Starts
18896                                                      and stops 2 clocks after demultiplexed SOC signal.                        */
18897       __IOM uint32_t PGAADCIFCHAPDNB : 2;       /*!< [3..2] Power down for channels A0 and A1 (0 = powered down;
18898                                                      1 = standby)                                                              */
18899       __IOM uint32_t PGAADCIFCHBACTIVE : 2;     /*!< [5..4] PGAADCIF active signal for channels B0 and B1. Starts
18900                                                      and stops 2 clocks after demultiplexed SOC signal.                        */
18901       __IOM uint32_t PGAADCIFCHBPDNB : 2;       /*!< [7..6] Power down for channels B0 and B1 (0 = powered down;
18902                                                      1 = standby)                                                              */
18903             uint32_t            : 4;
18904       __IOM uint32_t PGAADCIFVCOMPEN : 1;       /*!< [12..12] Enable for VCOMP output                                          */
18905       __IOM uint32_t PGAADCIFVCOMPSEL : 2;      /*!< [14..13] Select for VCOMP output (0: A0, 1: A1, 2: B0, 3: B1)             */
18906             uint32_t            : 17;
18907     } PGAADCIFCTRL_b;
18908   } ;
18909 
18910   union {
18911     __IOM uint32_t PGACTRL1;                    /*!< (@ 0x0000043C) PGA control 1                                              */
18912 
18913     struct {
18914       __IOM uint32_t PGACHA0GAIN1SEL : 3;       /*!< [2..0] Channel A0 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
18915                                                      steps)                                                                    */
18916       __IOM uint32_t PGACHA0GAIN2DIV2SEL : 1;   /*!< [3..3] Channel A0 PGA divide by two select (0: 0 dB, 1: -6dB),
18917                                                      needed for fully differential inputs                                      */
18918       __IOM uint32_t PGACHA0GAIN2SEL : 5;       /*!< [8..4] Channel A0 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5 dB
18919                                                      steps)                                                                    */
18920       __IOM uint32_t PGACHA1GAIN1SEL : 3;       /*!< [11..9] Channel A1 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
18921                                                      steps)                                                                    */
18922       __IOM uint32_t PGACHA1GAIN2DIV2SEL : 1;   /*!< [12..12] Channel A1 PGA divide by two select (0: 0 dB, 1: -6dB),
18923                                                      needed for fully differential inputs                                      */
18924       __IOM uint32_t PGACHA1GAIN2SEL : 5;       /*!< [17..13] Channel A1 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5
18925                                                      dB steps)                                                                 */
18926       __IOM uint32_t PGACHABYPASSEN : 2;        /*!< [19..18] Bypass enable for Channels A0 and A1 (1: bypass, when
18927                                                      gain LT 12 dB; 0: otherwise)                                              */
18928       __IOM uint32_t PGACHAOPAMPINPDNB : 2;     /*!< [21..20] Channels A0 and A1 input stage opamp power down (0:
18929                                                      powered down, 1: powered up). Must be 1 when respective
18930                                                      PGACHABYPASSEN = 0.                                                       */
18931       __IOM uint32_t PGACHAOPAMPOUTPDNB : 2;    /*!< [23..22] Channels A0 and A1 output stage opamp power down (0:
18932                                                      powered down, 1: powered up)                                              */
18933       __IOM uint32_t PGACHAVCMGENPDNB : 1;      /*!< [24..24] Channel A VCMGEN power down (0: powered down, 1: powered
18934                                                      up)                                                                       */
18935       __IOM uint32_t PGACHAVCMGENQCHARGEEN : 1; /*!< [25..25] Channel A VCMGEN quick charge enable (pulsed during
18936                                                      channel powerup)                                                          */
18937       __IOM uint32_t PGAIREFGENPDNB : 1;        /*!< [26..26] IREFGEN power down (0: powered down, 1: powered up)              */
18938       __IOM uint32_t PGAVREFGENPDNB : 1;        /*!< [27..27] VREFGEN power down (0: powered down, 1: powered up)              */
18939       __IOM uint32_t PGAVREFGENQUICKSTARTEN : 1;/*!< [28..28] VREFGEN quick start enable (pulsed during startup)               */
18940       __IOM uint32_t VCOMPSELPGA : 1;           /*!< [29..29] Select for VCOMP output (0: A0, 1: A1, 2: B0, 3: B1)             */
18941             uint32_t            : 1;
18942       __IOM uint32_t PGAGAINAOVRD : 1;          /*!< [31..31] Apply BYPASS and GAIN bits from this register (for
18943                                                      channel A) instead of automatically via audio ADC. Note
18944                                                      that audio ADC FIFO meta data will not reflect dB gain
18945                                                      as used when configuring audio ADC.                                       */
18946     } PGACTRL1_b;
18947   } ;
18948 
18949   union {
18950     __IOM uint32_t PGACTRL2;                    /*!< (@ 0x00000440) PGA control 2                                              */
18951 
18952     struct {
18953       __IOM uint32_t PGACHB0GAIN1SEL : 3;       /*!< [2..0] Channel B0 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
18954                                                      steps)                                                                    */
18955       __IOM uint32_t PGACHB0GAIN2DIV2SEL : 1;   /*!< [3..3] Channel B0 PGA divide by two select (0: 0 dB, 1: -6dB),
18956                                                      needed for fully differential inputs                                      */
18957       __IOM uint32_t PGACHB0GAIN2SEL : 5;       /*!< [8..4] Channel B0 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5 dB
18958                                                      steps)                                                                    */
18959       __IOM uint32_t PGACHB1GAIN1SEL : 3;       /*!< [11..9] Channel B1 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
18960                                                      steps)                                                                    */
18961       __IOM uint32_t PGACHB1GAIN2DIV2SEL : 1;   /*!< [12..12] Channel B1 PGA divide by two select (0: 0 dB, 1: -6dB),
18962                                                      needed for fully differential inputs                                      */
18963       __IOM uint32_t PGACHB1GAIN2SEL : 5;       /*!< [17..13] Channel B1 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5
18964                                                      dB steps)                                                                 */
18965       __IOM uint32_t PGACHBBYPASSEN : 2;        /*!< [19..18] Bypass enable for Channels B0 and B1 (1: bypass, when
18966                                                      gain LT 12 dB; 0: otherwise)                                              */
18967       __IOM uint32_t PGACHBOPAMPINPDNB : 2;     /*!< [21..20] Channels B0 and B1 input stage opamp power down (0:
18968                                                      powered down, 1: powered up). Must be 1 when respective
18969                                                      PGACHBBYPASSEN = 0.                                                       */
18970       __IOM uint32_t PGACHBOPAMPOUTPDNB : 2;    /*!< [23..22] Channels B0 and B1 output stage opamp power down (0:
18971                                                      powered down, 1: powered up)                                              */
18972       __IOM uint32_t PGACHBVCMGENPDNB : 1;      /*!< [24..24] Channel B VCMGEN power down (0: powered down, 1: powered
18973                                                      up)                                                                       */
18974       __IOM uint32_t PGACHBVCMGENQCHARGEEN : 1; /*!< [25..25] Channel B VCMGEN quick charge enable (pulsed during
18975                                                      channel powerup)                                                          */
18976             uint32_t            : 5;
18977       __IOM uint32_t PGAGAINBOVRD : 1;          /*!< [31..31] Apply BYPASS and GAIN bits from this register (for
18978                                                      channel B) instead of automatically via audio ADC. Note
18979                                                      that audio ADC FIFO meta data will not reflect dB gain
18980                                                      as used when configuring audio ADC.                                       */
18981     } PGACTRL2_b;
18982   } ;
18983 
18984   union {
18985     __IOM uint32_t AUDADCPWRDLY;                /*!< (@ 0x00000444) Audio ADC Power Up Delay Control                           */
18986 
18987     struct {
18988       __IOM uint32_t AUDADCPWR0 : 8;            /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
18989                                                      increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
18990                                                      for ADC_CLKSEL = 0x2.                                                     */
18991       __IOM uint32_t AUDADCPWR1 : 8;            /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
18992                                                      for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
18993                                                      = 0x2.                                                                    */
18994             uint32_t            : 16;
18995     } AUDADCPWRDLY_b;
18996   } ;
18997   __IM  uint32_t  RESERVED25[2];
18998 
18999   union {
19000     __IOM uint32_t SDIOCTRL;                    /*!< (@ 0x00000450) SDIO/eMMC Control                                          */
19001 
19002     struct {
19003       __IOM uint32_t SDIOSYSCLKEN : 1;          /*!< [0..0] SDIO system clock enable.                                          */
19004       __IOM uint32_t SDIOXINCLKEN : 1;          /*!< [1..1] SDIO serial clock source enable.                                   */
19005       __IOM uint32_t SDIOITAPCHGWIN : 1;        /*!< [2..2] This is used to gate the output of the Tap Delay lines
19006                                                      so as to avoid glithches being propagated into the Core.
19007                                                      This signal should be asserted few clocks before the itapdlysel
19008                                                      changes and should be asserted for few clocks after.                      */
19009       __IOM uint32_t SDIOITAPDLYENA : 1;        /*!< [3..3] Used to enable selective Tap delay line on the Looped
19010                                                      back SD Clock (rxclk_in). This signal along with the itapdlysel[4:0]
19011                                                      selects the the amount of delay to be inserted on the line.
19012                                                      When Tuning is enabled (for SDR104 and optionally for SDR50),
19013                                                      this signal is ignored and internalcontrols are used instead.
19014                                                      This should not be asserted when operating in DS mode.                    */
19015       __IOM uint32_t SDIOITAPDLYSEL : 5;        /*!< [8..4] Selects one of the 32 Taps on the rxclk_in line. This
19016                                                      is effective only when itapdlyena is asserted and Tuning
19017                                                      is not enabled.                                                           */
19018       __IOM uint32_t SDIOOTAPDLYENA : 1;        /*!< [9..9] Used to enable the selective Tap delay on the sdcard_clk
19019                                                      so as to generate the delayed sdcard_clk. This is used
19020                                                      to latch the CMD/DAT outputs to generate delay on them
19021                                                      w.r.t CLK going out. This signal along with otapdlysel[3:0]
19022                                                      selects the amount of delay to be inserted on the Clock
19023                                                      line. This signal should not be asserted when operating
19024                                                      in DS mode.                                                               */
19025       __IOM uint32_t SDIOOTAPDLYSEL : 4;        /*!< [13..10] Selects one of the 16 Taps on the sdcard_clk. This
19026                                                      is effective only when otapdlyena is asserted.                            */
19027       __IOM uint32_t SDIOASYNCWKUPENA : 1;      /*!< [14..14] SDIO asynchronous wakeup mode. 0: Synchronous wakeup
19028                                                      mode, 1: Asynchronous wakeup mode                                         */
19029       __IOM uint32_t SDIOXINCLKSEL : 2;         /*!< [16..15] Select clock source for SDIO xin_clk.                            */
19030       __IOM uint32_t SDIOCMDOPENDRAINEN : 1;    /*!< [17..17] SDIO CMD line configured as open-drian. 0: Push-pull
19031                                                      mode, 1: Open-drain mode                                                  */
19032       __IOM uint32_t SDIODATOPENDRAINEN : 1;    /*!< [18..18] SDIO DAT line configured as open-drian. 0: Push-pull
19033                                                      mode, 1: Open-drain mode                                                  */
19034             uint32_t            : 13;
19035     } SDIOCTRL_b;
19036   } ;
19037 
19038   union {
19039     __IOM uint32_t PDMCTRL;                     /*!< (@ 0x00000454) PDM Control                                                */
19040 
19041     struct {
19042       __IOM uint32_t PDMGLOBALEN : 1;           /*!< [0..0] PDM global enable to allow all PDMs to have synchronized
19043                                                      interface clocks and FIFO sampling.                                       */
19044             uint32_t            : 31;
19045     } PDMCTRL_b;
19046   } ;
19047 } MCUCTRL_Type;                                 /*!< Size = 1112 (0x458)                                                       */
19048 
19049 
19050 
19051 /* =========================================================================================================================== */
19052 /* ================                                           MSPI0                                           ================ */
19053 /* =========================================================================================================================== */
19054 
19055 
19056 /**
19057   * @brief Multi-bit SPI Master (MSPI0)
19058   */
19059 
19060 typedef struct {                                /*!< (@ 0x40060000) MSPI0 Structure                                            */
19061 
19062   union {
19063     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) This register is used to enable individual PIO
19064                                                                     based transactions to a device on the bus.
19065                                                                     The CFG register must be programmed properly
19066                                                                     for the transfer, and the ADDR and INSTR
19067                                                                     registers should be programmed if the SENDI
19068                                                                     and SENDA fields are enabled.                              */
19069 
19070     struct {
19071       __IOM uint32_t START      : 1;            /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically
19072                                                      the entire register should be written at once with this
19073                                                      bit set).                                                                 */
19074       __IOM uint32_t STATUS     : 1;            /*!< [1..1] Command status: 1 indicates command has completed. Cleared
19075                                                      by writing 1 to this bit or starting a new transfer.                      */
19076       __IOM uint32_t BUSY       : 1;            /*!< [2..2] Command status: 1 indicates controller is busy (command
19077                                                      in progress)                                                              */
19078             uint32_t            : 1;
19079       __IOM uint32_t PIODEV     : 1;            /*!< [4..4] Selects the Device configutation to use for PIO requests           */
19080       __IOM uint32_t SENDA      : 1;            /*!< [5..5] Indicates whether an address phase should be sent (see
19081                                                      ADDR register and ASIZE field in CFG register)                            */
19082       __IOM uint32_t SENDI      : 1;            /*!< [6..6] Indicates whether an instruction phase should be sent
19083                                                      (see INSTR field and ISIZE field in CFG register)                         */
19084       __IOM uint32_t TXRX       : 1;            /*!< [7..7] 1 Indicates a TX operation, 0 indicates an RX operation
19085                                                      of XFERBYTES                                                              */
19086       __IOM uint32_t BIGENDIAN  : 1;            /*!< [8..8] 1 indicates data in FIFO is in big endian format (MSB
19087                                                      first); 0 indicates little endian data (default, LSB first).              */
19088       __IOM uint32_t PIOSCRAMBLE : 1;           /*!< [9..9] Enables data scrambling for PIO opertions. This should
19089                                                      only be used for data operations and never for commands
19090                                                      to a device.                                                              */
19091       __IOM uint32_t ENTURN     : 1;            /*!< [10..10] Indicates whether TX->RX turnaround cycles should be
19092                                                      enabled for this operation (see TURNAROUND field in CFG
19093                                                      register).                                                                */
19094       __IOM uint32_t ENDCX      : 1;            /*!< [11..11] Enable DCX signal on data [1]                                    */
19095       __IOM uint32_t ENWLAT     : 1;            /*!< [12..12] Enable Write Latency Counter (time between address
19096                                                      and first data byte). Counter value is WRITELATENCY.                      */
19097       __IOM uint32_t PIOMIXED   : 3;            /*!< [15..13] Provides override controls for data operations where
19098                                                      instruction, address, and data may transfer in different
19099                                                      rates.                                                                    */
19100       __IOM uint32_t XFERBYTES  : 16;           /*!< [31..16] Number of bytes to transmit or receive (based on TXRX
19101                                                      bit)                                                                      */
19102     } CTRL_b;
19103   } ;
19104   __IM  uint32_t  RESERVED;
19105 
19106   union {
19107     __IOM uint32_t ADDR;                        /*!< (@ 0x00000008) Optional Address field to send for PIO transfers           */
19108 
19109     struct {
19110       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Optional Address field to send (after optional instruction
19111                                                      field) - qualified by ASIZE in CMD register. NOTE: This
19112                                                      register is aliased to DMADEVADDR.                                        */
19113     } ADDR_b;
19114   } ;
19115 
19116   union {
19117     __IOM uint32_t INSTR;                       /*!< (@ 0x0000000C) Optional Instruction field to send for PIO transfers       */
19118 
19119     struct {
19120       __IOM uint32_t INSTR      : 16;           /*!< [15..0] Optional Instruction field to send (1st byte) - qualified
19121                                                      by ISEND/ISIZE                                                            */
19122             uint32_t            : 16;
19123     } INSTR_b;
19124   } ;
19125 
19126   union {
19127     __IOM uint32_t TXFIFO;                      /*!< (@ 0x00000010) TX Data FIFO                                               */
19128 
19129     struct {
19130       __IOM uint32_t TXFIFO     : 32;           /*!< [31..0] Data to be transmitted. Data should normally be aligned
19131                                                      to the LSB (pad the upper bits with zeros) unless BIGENDIAN
19132                                                      is set.                                                                   */
19133     } TXFIFO_b;
19134   } ;
19135 
19136   union {
19137     __IOM uint32_t RXFIFO;                      /*!< (@ 0x00000014) RX Data FIFO                                               */
19138 
19139     struct {
19140       __IOM uint32_t RXFIFO     : 32;           /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros
19141                                                      on upper bits) unless BIGENDIAN is set.                                   */
19142     } RXFIFO_b;
19143   } ;
19144 
19145   union {
19146     __IOM uint32_t TXENTRIES;                   /*!< (@ 0x00000018) Number of words in TX FIFO                                 */
19147 
19148     struct {
19149       __IOM uint32_t TXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in TX FIFO                          */
19150             uint32_t            : 26;
19151     } TXENTRIES_b;
19152   } ;
19153 
19154   union {
19155     __IOM uint32_t RXENTRIES;                   /*!< (@ 0x0000001C) Number of words in RX FIFO                                 */
19156 
19157     struct {
19158       __IOM uint32_t RXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in RX FIFO                          */
19159             uint32_t            : 26;
19160     } RXENTRIES_b;
19161   } ;
19162 
19163   union {
19164     __IOM uint32_t THRESHOLD;                   /*!< (@ 0x00000020) Threshold levels that trigger RXFull and TXEmpty
19165                                                                     interrupts                                                 */
19166 
19167     struct {
19168       __IOM uint32_t TXTHRESH   : 6;            /*!< [5..0] Number of entries in TX FIFO that cause TXF interrupt              */
19169             uint32_t            : 2;
19170       __IOM uint32_t RXTHRESH   : 6;            /*!< [13..8] Number of entries in TX FIFO that cause RXE interrupt             */
19171             uint32_t            : 18;
19172     } THRESHOLD_b;
19173   } ;
19174   __IM  uint32_t  RESERVED1[3];
19175 
19176   union {
19177     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000030) Timing configuration bits for the MSPI module.
19178                                                                     PRSTN, IPRSTN, and FIFORESET can be used
19179                                                                     to reset portions of the MSPI interface
19180                                                                     in order to clear error conditions. The
19181                                                                     remaining bits control clock frequency and
19182                                                                     TX/RX capture timings.                                     */
19183 
19184     struct {
19185       __IOM uint32_t APBCLK     : 1;            /*!< [0..0] Enable continuous APB clock. For power-efficient operation,
19186                                                      APBCLK should be set to 0.                                                */
19187             uint32_t            : 3;
19188       __IOM uint32_t IOMSEL     : 4;            /*!< [7..4] Selects which IOM is selected for CQ handshake status.             */
19189             uint32_t            : 21;
19190       __IOM uint32_t FIFORESET  : 1;            /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal
19191                                                      operation. May be used to manually flush the FIFO in error
19192                                                      handling.                                                                 */
19193       __IOM uint32_t IPRSTN     : 1;            /*!< [30..30] IP block reset. Write to 0 to put the transfer module
19194                                                      in reset or 1 for normal operation. This may be required
19195                                                      after error conditions to clear the transfer on the bus.                  */
19196       __IOM uint32_t PRSTN      : 1;            /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module
19197                                                      (DMA, XIP, and transfer state machines). 1=normal operation,
19198                                                      0=in reset.                                                               */
19199     } MSPICFG_b;
19200   } ;
19201   __IM  uint32_t  RESERVED2[4];
19202 
19203   union {
19204     __IOM uint32_t PADOUTEN;                    /*!< (@ 0x00000044) Enable bits for the MSPI output pads. Each active
19205                                                                     MSPI line should be set to 1 in the OUTEN
19206                                                                     field below.                                               */
19207 
19208     struct {
19209       __IOM uint32_t OUTEN      : 10;           /*!< [9..0] Output pad enable configuration. Indicates which pads
19210                                                      should be driven. Bits [3:0] are Quad0 data, [7:4] are
19211                                                      Quad1 data, and [8] is clock.                                             */
19212             uint32_t            : 2;
19213       __IOM uint32_t CLKOND4    : 1;            /*!< [12..12] Output clock on MSPI data[4]                                     */
19214             uint32_t            : 19;
19215     } PADOUTEN_b;
19216   } ;
19217 
19218   union {
19219     __IOM uint32_t PADOVEREN;                   /*!< (@ 0x00000048) Enables PIO-like pad override control                      */
19220 
19221     struct {
19222       __IOM uint32_t OVERRIDEEN : 10;           /*!< [9..0] Output pad override enable. Bit mask for pad outputs.
19223                                                      When set to 1, the values in the OVERRIDE field are driven
19224                                                      on the pad (output enable is implicitly set in this mode).
19225                                                      [7:0]=data [8]=clock [9]=DM                                               */
19226             uint32_t            : 22;
19227     } PADOVEREN_b;
19228   } ;
19229 
19230   union {
19231     __IOM uint32_t PADOVER;                     /*!< (@ 0x0000004C) Override data value                                        */
19232 
19233     struct {
19234       __IOM uint32_t OVERRIDE   : 10;           /*!< [9..0] Output pad override value. [7:0]=data [8]=clock [9]=DM             */
19235             uint32_t            : 22;
19236     } PADOVER_b;
19237   } ;
19238   __IM  uint32_t  RESERVED3[12];
19239 
19240   union {
19241     __IOM uint32_t DEV0AXI;                     /*!< (@ 0x00000080) Specifies the base address and aperture range
19242                                                                     of the device as mapped onto the AXI bus                   */
19243 
19244     struct {
19245       __IOM uint32_t SIZE0      : 4;            /*!< [3..0] Indicates the AXI aperture size                                    */
19246       __IOM uint32_t READONLY0  : 1;            /*!< [4..4] Indicates the AXI aperture is read-only                            */
19247             uint32_t            : 11;
19248       __IOM uint32_t BASE0      : 10;           /*!< [25..16] XIPEN has to be enabled to enable aperture                       */
19249             uint32_t            : 6;
19250     } DEV0AXI_b;
19251   } ;
19252 
19253   union {
19254     __IOM uint32_t DEV0CFG;                     /*!< (@ 0x00000084) Command formatting for PIO based transactions
19255                                                                     (initiated by writes to CTRL register)                     */
19256 
19257     struct {
19258       __IOM uint32_t DEVCFG0    : 4;            /*!< [3..0] Flash configuration for XIP and AUTO DMA operations.
19259                                                      Controls value for SER (Slave Enable) for XIP operations
19260                                                      and address generation for DMA/XIP modes. Also used to
19261                                                      configure SPIFRF (frame format).                                          */
19262       __IOM uint32_t ASIZE0     : 2;            /*!< [5..4] Address Size. Address bytes to send from ADDR register             */
19263       __IOM uint32_t ISIZE0     : 1;            /*!< [6..6] Instruction Size                                                   */
19264       __IOM uint32_t SEPIO0     : 1;            /*!< [7..7] Separate IO configuration. This bit should be set when
19265                                                      the target device has separate MOSI and MISO pins. Respective
19266                                                      IN/OUT bits below should be set to map pins.                              */
19267       __IOM uint32_t TURNAROUND0 : 6;           /*!< [13..8] Number of turnaound cycles (for TX->RX transitions).
19268                                                      Qualified by ENTURN bit field.                                            */
19269       __IOM uint32_t CPHA0      : 1;            /*!< [14..14] Serial clock phase.                                              */
19270       __IOM uint32_t CPOL0      : 1;            /*!< [15..15] Serial clock polarity.                                           */
19271       __IOM uint32_t CLKDIV0    : 6;            /*!< [21..16] Clock Divider. Allows dividing 96 MHz base clock by
19272                                                      integer multiples. Enumerations are provided for common
19273                                                      frequency, but any integer divide from 96 MHz is allowed.
19274                                                      Odd divide ratios will result in a 33/66 percent duty cycle
19275                                                      with a long low clock pulse (to allow longer round-trip
19276                                                      for read data).                                                           */
19277       __IOM uint32_t RXCAP0     : 1;            /*!< [22..22] Controls RX data capture phase. A setting of 0 (NORMAL)
19278                                                      captures read data at the normal capture point relative
19279                                                      to the internal clock launch point. However, to accomodate
19280                                                      chip/pad/board delays, a setting of RXCAP of 1 is expected
19281                                                      to be used to align the capture point with the return data
19282                                                      window. This bit is used in conjunction with RXNEG to provide
19283                                                      4 unique capture points, all about 10ns apart.                            */
19284       __IOM uint32_t RXNEG0     : 1;            /*!< [23..23] Adjusts the RX capture phase to the negedge of the
19285                                                      48MHz internal clock (~10ns early). For normal operation,
19286                                                      it is expected that RXNEG will be set to 0.                               */
19287       __IOM uint32_t TXNEG0     : 1;            /*!< [24..24] Launches TX data a half clock cycle (~10ns) early.
19288                                                      This should normally be programmed to zero (NORMAL).                      */
19289             uint32_t            : 1;
19290       __IOM uint32_t WRITELATENCY0 : 6;         /*!< [31..26] Number of write Latency cycles. Qualified by ENTURN
19291                                                      bit field.                                                                */
19292     } DEV0CFG_b;
19293   } ;
19294 
19295   union {
19296     __IOM uint32_t DEV0DDR;                     /*!< (@ 0x00000088) Timing configuration bits for DDR operation of
19297                                                                     the MSPI module.                                           */
19298 
19299     struct {
19300       __IOM uint32_t EMULATEDDR0 : 1;           /*!< [0..0] Drive external clock at 1/2 rate to emulate DDR mode               */
19301       __IOM uint32_t QUADDDR0   : 1;            /*!< [1..1] Enables use of delay line to provide fine control over
19302                                                      traditional RX capture clock.                                             */
19303       __IOM uint32_t ENABLEDQS0 : 1;            /*!< [2..2] In EMULATEDDR mode, enable DQS for read capture                    */
19304       __IOM uint32_t DQSSYNCNEG0 : 1;           /*!< [3..3] Use negative edge of clock for DDR data sync                       */
19305       __IOM uint32_t OVERRIDERXDQSDELAY0 : 1;   /*!< [4..4] Override DQS delay line with the value in DQSDELAY (for
19306                                                      RX capture in QUADDDR mode)                                               */
19307       __IOM uint32_t OVERRIDEDDRCLKOUTDELAY0 : 1;/*!< [5..5] Override TX delay line with the value in DQSDELAY (for
19308                                                      TX clock offset when in QUADDDR mode)                                     */
19309       __IOM uint32_t ENABLEFINEDELAY0 : 1;      /*!< [6..6] Enables use of delay line to provide fine control over
19310                                                      traditional RX capture clock.                                             */
19311             uint32_t            : 1;
19312       __IOM uint32_t RXDQSDELAY0 : 5;           /*!< [12..8] When OVERRIDEDQSDELAY is set this sets the DQS delay
19313                                                      line value. In ENABLEDQS mode, this acts as an offset to
19314                                                      the computed value (should be set to 0 by default)                        */
19315             uint32_t            : 3;
19316       __IOM uint32_t TXDQSDELAY0 : 5;           /*!< [20..16] When OVERRIDEDQSDELAY is set this sets the DQS delay
19317                                                      line value. In ENABLEDQS mode, this acts as an offset to
19318                                                      the computed value (should be set to 0 by default)                        */
19319             uint32_t            : 11;
19320     } DEV0DDR_b;
19321   } ;
19322   __IM  uint32_t  RESERVED4;
19323 
19324   union {
19325     __IOM uint32_t DEV0XIP;                     /*!< (@ 0x00000090) When any SPI flash is configured, this register
19326                                                                     must be properly programmed before XIP or
19327                                                                     AUTO DMA operations commence.                              */
19328 
19329     struct {
19330       __IOM uint32_t XIPEN0     : 1;            /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively
19331                                                      enables the address decoding of the MSPI device in the
19332                                                      flash/cache address space at address 0x04000000-0x07FFFFFF.               */
19333             uint32_t            : 1;
19334       __IOM uint32_t XIPACK0    : 2;            /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles
19335                                                      (Micron Flash devices only)                                               */
19336       __IOM uint32_t XIPBIGENDIAN0 : 1;         /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in
19337                                                      big or little endian format                                               */
19338       __IOM uint32_t XIPENTURN0 : 1;            /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable
19339                                                      TX->RX turnaround cycles                                                  */
19340       __IOM uint32_t XIPSENDA0  : 1;            /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send
19341                                                      an an address phase (see DMADEVADDR register and ASIZE
19342                                                      field in CFG)                                                             */
19343       __IOM uint32_t XIPSENDI0  : 1;            /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send
19344                                                      an instruction (see READINSTR field and ISIZE field in
19345                                                      CFG)                                                                      */
19346       __IOM uint32_t XIPMIXED0  : 3;            /*!< [10..8] Provides override controls for data operations where
19347                                                      instruction, address, and data may transfer in different
19348                                                      rates.                                                                    */
19349       __IOM uint32_t XIPENDCX0  : 1;            /*!< [11..11] Enable DCX signal on data [1] for XIP/DMA operations             */
19350       __IOM uint32_t XIPENWLAT0 : 1;            /*!< [12..12] Enable Write Latency counter for XIP write transactions          */
19351       __IOM uint32_t XIPTURNAROUND0 : 6;        /*!< [18..13] Number of turnaound cycles (for TX->RX transitions).
19352                                                      Qualified by XIPENTURN bit field.                                         */
19353       __IOM uint32_t XIPWRITELATENCY0 : 6;      /*!< [24..19] Number of write Latency cycles. Qualified by XIPENWLAT
19354                                                      bit field.                                                                */
19355             uint32_t            : 7;
19356     } DEV0XIP_b;
19357   } ;
19358 
19359   union {
19360     __IOM uint32_t DEV0INSTR;                   /*!< (@ 0x00000094) When any SPI flash is configured, this register
19361                                                                     must be properly programmed before XIP or
19362                                                                     AUTO DMA operations commence.                              */
19363 
19364     struct {
19365       __IOM uint32_t WRITEINSTR0 : 16;          /*!< [15..0] Write command sent for DMA operations                             */
19366       __IOM uint32_t READINSTR0 : 16;           /*!< [31..16] Read command sent to flash for DMA/XIP operations                */
19367     } DEV0INSTR_b;
19368   } ;
19369 
19370   union {
19371     __IOM uint32_t DEV0BOUNDARY;                /*!< (@ 0x00000098) Allows large transfers to be broken up into smaller
19372                                                                     ones in hardware to accommodate needs of
19373                                                                     external devices and allow XIP/XIPMM. Only
19374                                                                     applicable for memory-mapped devices (PSRAM,
19375                                                                     Flash, etc) where address can be retransmitted
19376                                                                     without side effects.                                      */
19377 
19378     struct {
19379       __IOM uint32_t DMATIMELIMIT0 : 12;        /*!< [11..0] DMA time limit. Can be used to limit the transaction
19380                                                      time on the MSPI bus. The count is in 50 ns increments
19381                                                      for the 96 MHz clock input on rev B silicon (100 ns increments
19382                                                      for the 48 MHz clock on rev A). A value of 0 disables the
19383                                                      counter.                                                                  */
19384       __IOM uint32_t DMABOUND0  : 4;            /*!< [15..12] DMA Address boundary                                             */
19385             uint32_t            : 16;
19386     } DEV0BOUNDARY_b;
19387   } ;
19388 
19389   union {
19390     __IOM uint32_t DEV0SCRAMBLING;              /*!< (@ 0x0000009C) Enables data scrambling for the specified range
19391                                                                     external flash addresses. Scrambling does
19392                                                                     not impact flash access performance.                       */
19393 
19394     struct {
19395       __IOM uint32_t SCRSTART0  : 10;           /*!< [9..0] Scrambling region start address [25:16] (64K block granularity).
19396                                                      The START block is the FIRST block included in the scrambled
19397                                                      address range.                                                            */
19398             uint32_t            : 6;
19399       __IOM uint32_t SCREND0    : 10;           /*!< [25..16] Scrambling region end address [25:16] (64K block granularity).
19400                                                      The END block is the LAST block included in the scrambled
19401                                                      address range.                                                            */
19402             uint32_t            : 5;
19403       __IOM uint32_t SCRENABLE0 : 1;            /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes
19404                                                      to the range will be scrambled. When 0, data will be read/written
19405                                                      unmodified. Address range is specified in 64K granularity
19406                                                      and the START/END ranges are included within the range.                   */
19407     } DEV0SCRAMBLING_b;
19408   } ;
19409 
19410   union {
19411     __IOM uint32_t DEV0XIPMISC;                 /*!< (@ 0x000000A0) Miscellaneous XIP control registers for AXI logic          */
19412 
19413     struct {
19414       __IOM uint32_t CEBREAK0   : 12;           /*!< [11..0] CEBREAK0 field description needed.                                */
19415       __IOM uint32_t XIPODD0    : 1;            /*!< [12..12] Convert odd starting address to even starting address
19416                                                      with bytemask                                                             */
19417       __IOM uint32_t BEPOL0     : 1;            /*!< [13..13] byte mask polarity to MSPI xfer                                  */
19418       __IOM uint32_t BEON0      : 1;            /*!< [14..14] Byte enable always on for all lanes                              */
19419       __IOM uint32_t XIPBOUNDARY0 : 1;          /*!< [15..15] Control DMAxBOUNDARY to AXI                                      */
19420       __IOM uint32_t AFIFOLVL0  : 5;            /*!< [20..16] AFIFOLVL0 register description needed.                           */
19421       __IOM uint32_t APNDODD0   : 1;            /*!< [21..21] Append dummy byte to odd number of write                         */
19422             uint32_t            : 10;
19423     } DEV0XIPMISC_b;
19424   } ;
19425   __IM  uint32_t  RESERVED5[23];
19426 
19427   union {
19428     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000100) DMA Configuration                                          */
19429 
19430     struct {
19431       __IOM uint32_t DMAEN      : 2;            /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA
19432                                                      operation                                                                 */
19433       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
19434       __IOM uint32_t DMADEV     : 1;            /*!< [3..3] DMA Device Select                                                  */
19435       __IOM uint32_t DMAPRI     : 2;            /*!< [5..4] Sets the Priority of the DMA request                               */
19436             uint32_t            : 12;
19437       __IOM uint32_t DMAPWROFF  : 1;            /*!< [18..18] Power off MSPI domain upon completion of DMA operation.          */
19438             uint32_t            : 13;
19439     } DMACFG_b;
19440   } ;
19441 
19442   union {
19443     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000104) DMA Status                                                 */
19444 
19445     struct {
19446       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
19447                                                      a DMA transfer is active. The DMA transfer may be waiting
19448                                                      on data, transferring data, or waiting for priority. All
19449                                                      of these will be indicated with a 1. A 0 will indicate
19450                                                      that the DMA is fully complete and no further transactions
19451                                                      will be done.                                                             */
19452       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
19453                                                      operation.                                                                */
19454       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals that an error
19455                                                      was encountered during the DMA operation.                                 */
19456       __IOM uint32_t SCRERR     : 1;            /*!< [3..3] Scrambling Access Alignment Error. This active high bit
19457                                                      signals that a scrambling operation was specified for a
19458                                                      non-word aligned DEVADDR.                                                 */
19459             uint32_t            : 28;
19460     } DMASTAT_b;
19461   } ;
19462 
19463   union {
19464     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000108) DMA Target Address                                         */
19465 
19466     struct {
19467       __IOM uint32_t TARGADDR   : 32;           /*!< [31..0] Target byte address for source of DMA (either read or
19468                                                      write). In cases of non-word aligned addresses, the DMA
19469                                                      logic will take care for ensuring only the target bytes
19470                                                      are read/written.                                                         */
19471     } DMATARGADDR_b;
19472   } ;
19473 
19474   union {
19475     __IOM uint32_t DMADEVADDR;                  /*!< (@ 0x0000010C) DMA Device Address                                         */
19476 
19477     struct {
19478       __IOM uint32_t DEVADDR    : 32;           /*!< [31..0] SPI Device address for automated DMA transactions (both
19479                                                      read and write).                                                          */
19480     } DMADEVADDR_b;
19481   } ;
19482 
19483   union {
19484     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000110) DMA Total Transfer Count                                   */
19485 
19486     struct {
19487       __IOM uint32_t TOTCOUNT   : 24;           /*!< [23..0] Total Transfer Count in bytes.                                    */
19488             uint32_t            : 8;
19489     } DMATOTCOUNT_b;
19490   } ;
19491 
19492   union {
19493     __IOM uint32_t DMABCOUNT;                   /*!< (@ 0x00000114) DMA BYTE Transfer Count                                    */
19494 
19495     struct {
19496       __IOM uint32_t BCOUNT     : 8;            /*!< [7..0] Burst transfer size in bytes. This is the number of bytes
19497                                                      transferred when a FIFO trigger event occurs. Recommended
19498                                                      value is 32.                                                              */
19499             uint32_t            : 24;
19500     } DMABCOUNT_b;
19501   } ;
19502 
19503   union {
19504     __IOM uint32_t DMATHRESH;                   /*!< (@ 0x00000118) Indicates FIFO level at which a DMA should be
19505                                                                     triggered. For most configurations, a setting
19506                                                                     of 8 is recommended for both read and write
19507                                                                     operations.                                                */
19508 
19509     struct {
19510       __IOM uint32_t DMATXTHRESH : 5;           /*!< [4..0] DMA transfer FIFO level trigger. For read operations,
19511                                                      DMA is triggered when the FIFO level is greater than this
19512                                                      value. For write operations, DMA is triggered when the
19513                                                      FIFO level is less than this level. Each DMA operation
19514                                                      will consist of BCOUNT bytes.                                             */
19515             uint32_t            : 3;
19516       __IOM uint32_t DMARXTHRESH : 5;           /*!< [12..8] DMA transfer FIFO level trigger. For read operations,
19517                                                      DMA is triggered when the FIFO level is greater than this
19518                                                      value. For write operations, DMA is triggered when the
19519                                                      FIFO level is less than this level. Each DMA operation
19520                                                      will consist of BCOUNT bytes.                                             */
19521             uint32_t            : 19;
19522     } DMATHRESH_b;
19523   } ;
19524   __IM  uint32_t  RESERVED6[57];
19525 
19526   union {
19527     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
19528                                                                     to generate the corresponding interrupt.                   */
19529 
19530     struct {
19531       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19532                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19533       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19534       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19535                                                      a full FIFO).                                                             */
19536       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19537                                                      an empty FIFO)                                                            */
19538       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19539                                                      MSPI bus pins will stall)                                                 */
19540       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19541       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19542       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19543       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19544       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19545                                                      performs an operation where address bit[0] is set. Useful
19546                                                      for triggering CURIDX interrupts.                                         */
19547       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19548       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19549       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19550                                                      be aligned to word (4-byte) start address.                                */
19551             uint32_t            : 19;
19552     } INTEN_b;
19553   } ;
19554 
19555   union {
19556     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
19557                                                                     cause of a recent interrupt.                               */
19558 
19559     struct {
19560       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19561                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19562       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19563       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19564                                                      a full FIFO).                                                             */
19565       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19566                                                      an empty FIFO)                                                            */
19567       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19568                                                      MSPI bus pins will stall)                                                 */
19569       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19570       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19571       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19572       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19573       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19574                                                      performs an operation where address bit[0] is set. Useful
19575                                                      for triggering CURIDX interrupts.                                         */
19576       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19577       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19578       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19579                                                      be aligned to word (4-byte) start address.                                */
19580             uint32_t            : 19;
19581     } INTSTAT_b;
19582   } ;
19583 
19584   union {
19585     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
19586                                                                     the interrupt status associated with that
19587                                                                     bit.                                                       */
19588 
19589     struct {
19590       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19591                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19592       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19593       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19594                                                      a full FIFO).                                                             */
19595       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19596                                                      an empty FIFO)                                                            */
19597       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19598                                                      MSPI bus pins will stall)                                                 */
19599       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19600       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19601       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19602       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19603       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19604                                                      performs an operation where address bit[0] is set. Useful
19605                                                      for triggering CURIDX interrupts.                                         */
19606       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19607       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19608       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19609                                                      be aligned to word (4-byte) start address.                                */
19610             uint32_t            : 19;
19611     } INTCLR_b;
19612   } ;
19613 
19614   union {
19615     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
19616                                                                     generate an interrupt from this module.
19617                                                                     (Generally used for testing purposes).                     */
19618 
19619     struct {
19620       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19621                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19622       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19623       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19624                                                      a full FIFO).                                                             */
19625       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19626                                                      an empty FIFO)                                                            */
19627       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19628                                                      MSPI bus pins will stall)                                                 */
19629       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19630       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19631       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19632       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19633       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19634                                                      performs an operation where address bit[0] is set. Useful
19635                                                      for triggering CURIDX interrupts.                                         */
19636       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19637       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19638       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19639                                                      be aligned to word (4-byte) start address.                                */
19640             uint32_t            : 19;
19641     } INTSET_b;
19642   } ;
19643   __IM  uint32_t  RESERVED7[36];
19644 
19645   union {
19646     __IOM uint32_t CQCFG;                       /*!< (@ 0x000002A0) This register controls Command Queuing (CQ) operations
19647                                                                     in a manner similar to the DMACFG register.                */
19648 
19649     struct {
19650       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
19651                                                      of the command queue                                                      */
19652       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request                 */
19653       __IOM uint32_t CQPWROFF   : 1;            /*!< [2..2] Power off MSPI domain upon completion of DMA operation.            */
19654       __IOM uint32_t CQAUTOCLEARMASK : 1;       /*!< [3..3] Enable clear of CQMASK after each pause operation. This
19655                                                      may be useful when using software flags to pause CQ.                      */
19656             uint32_t            : 28;
19657     } CQCFG_b;
19658   } ;
19659   __IM  uint32_t  RESERVED8;
19660 
19661   union {
19662     __IOM uint32_t CQADDR;                      /*!< (@ 0x000002A8) Location of the command queue in SRAM or flash
19663                                                                     memory. This register will increment as
19664                                                                     CQ operations commence. Software should
19665                                                                     only write CQADDR when CQEN is disabled,
19666                                                                     however the command queue script itself
19667                                                                     may update CQADDR in order to perform queue
19668                                                                     management functions (like resetting the
19669                                                                     pointers)                                                  */
19670 
19671     struct {
19672       __IOM uint32_t CQADDR     : 29;           /*!< [28..0] Address of command queue buffer in SRAM or flash. The
19673                                                      buffer address must be aligned to a word boundary.                        */
19674             uint32_t            : 3;
19675     } CQADDR_b;
19676   } ;
19677 
19678   union {
19679     __IOM uint32_t CQSTAT;                      /*!< (@ 0x000002AC) Command Queue Status                                       */
19680 
19681     struct {
19682       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
19683                                                      indicate that a CQ transfer is active and this will remain
19684                                                      active even when paused waiting for external event.                       */
19685       __IOM uint32_t CQCPL      : 1;            /*!< [1..1] Command queue operation Complete. This signals the end
19686                                                      of the command queue operation.                                           */
19687       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
19688                                                      signals that an error was encountered during the CQ operation.            */
19689       __IOM uint32_t CQPAUSED   : 1;            /*!< [3..3] Command queue is currently paused status.                          */
19690             uint32_t            : 28;
19691     } CQSTAT_b;
19692   } ;
19693 
19694   union {
19695     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x000002B0) Command Queue Flags                                        */
19696 
19697     struct {
19698       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
19699                                                      controllable and bits [15:8] are hardware status.                         */
19700             uint32_t            : 16;
19701     } CQFLAGS_b;
19702   } ;
19703 
19704   union {
19705     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x000002B4) Command Queue Flag Set/Clear                               */
19706 
19707     struct {
19708       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Set has priority over clear if
19709                                                      both are high.                                                            */
19710       __IOM uint32_t CQFTOGGLE  : 8;            /*!< [15..8] Toggle CQFlag status bits                                         */
19711       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits.                                        */
19712             uint32_t            : 8;
19713     } CQSETCLEAR_b;
19714   } ;
19715 
19716   union {
19717     __IOM uint32_t CQPAUSE;                     /*!< (@ 0x000002B8) Command Queue Pause Mask                                   */
19718 
19719     struct {
19720       __IOM uint32_t CQMASK     : 16;           /*!< [15..0] CQ will pause processing when ALL specified events are
19721                                                      satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.                      */
19722             uint32_t            : 16;
19723     } CQPAUSE_b;
19724   } ;
19725   __IM  uint32_t  RESERVED9;
19726 
19727   union {
19728     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x000002C0) This register can be used in conjunction with
19729                                                                     the CQENDIDX register to manage the command
19730                                                                     queue. Typically software will initialize
19731                                                                     the CQCURIDX and CQENDIDX to the same value,
19732                                                                     which will cause the CQ to be paused when
19733                                                                     enabled. Software may then add entries to
19734                                                                     the command queue (in SRAM) and update CQENDIDX.
19735                                                                     The command queue operations will then increment
19736                                                                     CQCURIDX as it processes operations. Once
19737                                                                     CQCURIDX==CQENDIDX, the command queue hardware
19738                                                                     will automatically pause since no additional
19739                                                                     ope                                                        */
19740 
19741     struct {
19742       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Can be used to indicate the current position of the command
19743                                                      queue by having CQ operations write this field. A CQ hardware
19744                                                      status flag indicates when CURIDX and ENDIDX are not equal,
19745                                                      allowing SW to pause the CQ processing until the end index
19746                                                      is updated.                                                               */
19747             uint32_t            : 24;
19748     } CQCURIDX_b;
19749   } ;
19750 
19751   union {
19752     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x000002C4) Command Queue End Index                                    */
19753 
19754     struct {
19755       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Can be used to indicate the end position of the command
19756                                                      queue. A CQ hardware status bit indices when CURIDX !=
19757                                                      ENDIDX so that the CQ can be paused when it reaches the
19758                                                      end pointer.                                                              */
19759             uint32_t            : 24;
19760     } CQENDIDX_b;
19761   } ;
19762 } MSPI0_Type;                                   /*!< Size = 712 (0x2c8)                                                        */
19763 
19764 
19765 
19766 /* =========================================================================================================================== */
19767 /* ================                                           PDM0                                            ================ */
19768 /* =========================================================================================================================== */
19769 
19770 
19771 /**
19772   * @brief PDM Audio (PDM0)
19773   */
19774 
19775 typedef struct {                                /*!< (@ 0x40201000) PDM0 Structure                                             */
19776 
19777   union {
19778     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) PDM Control                                                */
19779 
19780     struct {
19781       __IOM uint32_t CLKEN      : 1;            /*!< [0..0] PDM Clock enable.If multiple clocks are enabled, priority
19782                                                      is HFRC2, HF XTAL, HFRC.                                                  */
19783       __IOM uint32_t CLKSEL     : 2;            /*!< [2..1] PDM Master Clock select (24.576MHz).0: HFRC2_192MHz div8
19784                                                      with HFAdj21: XTAL_HS Byapss2: HFRC_96MHz div4                            */
19785             uint32_t            : 1;
19786       __IOM uint32_t RSTB       : 1;            /*!< [4..4] Reset IP core. 0 puts the core in reset; 1 takes the
19787                                                      core out of reset.                                                        */
19788       __IOM uint32_t PCMPACK    : 1;            /*!< [5..5] Enable PCM packing. Only 24-bit unpacked mode supported.           */
19789       __IOM uint32_t EN         : 1;            /*!< [6..6] PDM enable register                                                */
19790             uint32_t            : 25;
19791     } CTRL_b;
19792   } ;
19793 
19794   union {
19795     __IOM uint32_t CORECFG0;                    /*!< (@ 0x00000004) PDM to PCM Core Configuration                              */
19796 
19797     struct {
19798       __IOM uint32_t LRSWAP     : 1;            /*!< [0..0] Left/Right channel swap when = 1                                   */
19799       __IOM uint32_t SOFTMUTE   : 1;            /*!< [1..1] Soft mute enable when = 1                                          */
19800       __IOM uint32_t SCYCLES    : 3;            /*!< [4..2] Set number of PDMA_CKO cycles during gain setting changes
19801                                                      or soft mute                                                              */
19802       __IOM uint32_t HPGAIN     : 4;            /*!< [8..5] Adjust High Pass filter coefficients                               */
19803       __IOM uint32_t ADCHPD     : 1;            /*!< [9..9] Disable high pass filter when = 1                                  */
19804       __IOM uint32_t MCLKDIV    : 4;            /*!< [13..10] PDMA_CKO frequency divisor.MCLKDIV > 0. MCLKDIV = 0
19805                                                      PROHIBITED.MCLKDIV = (PDM_CLK /Fsin / (DIVMCLKQ + 1)) -1                  */
19806       __IOM uint32_t SINCRATE   : 7;            /*!< [20..14] Sinc decimation rate.SINC_RATE = OSR /2. OSR = Fsin
19807                                                      / Fsout.Must be even.16 to 64 allowed.96 allowed for special
19808                                                      configuration.                                                            */
19809       __IOM uint32_t PGAL       : 5;            /*!< [25..21] Left Channel PGA Gain: +1.5dB/step, -12dB ~ +34.5dB;enum
19810                                                      name = M12_0DB value = 0x0 desc = Left channel PGA gain
19811                                                      = -12.0 dB                                                                */
19812       __IOM uint32_t PGAR       : 5;            /*!< [30..26] Right Channel PGA Gain:+1.5dB/step, -12dB ~ +34.5dB;             */
19813             uint32_t            : 1;
19814     } CORECFG0_b;
19815   } ;
19816 
19817   union {
19818     __IOM uint32_t CORECFG1;                    /*!< (@ 0x00000008) PDM to PCM Extra Configuration                             */
19819 
19820     struct {
19821       __IOM uint32_t PCMCHSET   : 2;            /*!< [1..0] PCM output chanel 0xsetting                                        */
19822       __IOM uint32_t DIVMCLKQ   : 2;            /*!< [3..2] Divide down ratio for generating internal master MCLKQ.DIVMCLKQ
19823                                                      > 0. DIVMCLKQ = 0 PROHIBITED.Recommend value of 1.Fmclkq
19824                                                      = Fpdmclk/(DIVMCLKQ+1).                                                   */
19825       __IOM uint32_t CKODLY     : 3;            /*!< [6..4] PDMA_CKO clock phase delay in terms of PDMCLK period
19826                                                      to internal sampler                                                       */
19827       __IOM uint32_t SELSTEP    : 1;            /*!< [7..7] Fine grain step size for smooth PGA or Softmute attenuation
19828                                                      transition0: 0.13dB1: 0.26dB                                              */
19829             uint32_t            : 24;
19830     } CORECFG1_b;
19831   } ;
19832 
19833   union {
19834     __IOM uint32_t CORECTRL;                    /*!< (@ 0x0000000C) PDM to PCM Control                                         */
19835 
19836     struct {
19837       __IOM uint32_t CORECTRL   : 32;           /*!< [31..0] Overall control of PDM core. Internal use only                    */
19838     } CORECTRL_b;
19839   } ;
19840 
19841   union {
19842     __IOM uint32_t FIFOCNT;                     /*!< (@ 0x00000010) FIFO count                                                 */
19843 
19844     struct {
19845       __IOM uint32_t FIFOCNT    : 6;            /*!< [5..0] Valid 32-bit entries currently in the FIFO.                        */
19846             uint32_t            : 26;
19847     } FIFOCNT_b;
19848   } ;
19849 
19850   union {
19851     __IOM uint32_t FIFOREAD;                    /*!< (@ 0x00000014) FIFO Read                                                  */
19852 
19853     struct {
19854       __IOM uint32_t FIFOREAD   : 32;           /*!< [31..0] FIFO read data.                                                   */
19855     } FIFOREAD_b;
19856   } ;
19857 
19858   union {
19859     __IOM uint32_t FIFOFLUSH;                   /*!< (@ 0x00000018) FIFO Flush                                                 */
19860 
19861     struct {
19862       __IOM uint32_t FIFOFLUSH  : 1;            /*!< [0..0] FIFO FLUSH.                                                        */
19863             uint32_t            : 31;
19864     } FIFOFLUSH_b;
19865   } ;
19866 
19867   union {
19868     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x0000001C) FIFO Threshold                                             */
19869 
19870     struct {
19871       __IOM uint32_t FIFOTHR    : 5;            /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to,
19872                                                      or larger than this value (in words), a THR interrupt is
19873                                                      generated (if enabled). If used for DMA purposes then only
19874                                                      supported values are 0x4, 0x8, 0xc, 0x10, 0x14, 0x18 and
19875                                                      0x1C.                                                                     */
19876             uint32_t            : 27;
19877     } FIFOTHR_b;
19878   } ;
19879   __IM  uint32_t  RESERVED[56];
19880 
19881   union {
19882     __IOM uint32_t INTEN;                       /*!< (@ 0x00000100) Set bits in this register to allow this module
19883                                                                     to generate the corresponding interrupt.                   */
19884 
19885     struct {
19886       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
19887       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
19888       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
19889       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
19890       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
19891             uint32_t            : 27;
19892     } INTEN_b;
19893   } ;
19894 
19895   union {
19896     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000104) Read bits from this register to discover the
19897                                                                     cause of a recent interrupt.                               */
19898 
19899     struct {
19900       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
19901       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
19902       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
19903       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
19904       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
19905             uint32_t            : 27;
19906     } INTSTAT_b;
19907   } ;
19908 
19909   union {
19910     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
19911                                                                     the interrupt status associated with that
19912                                                                     bit.                                                       */
19913 
19914     struct {
19915       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
19916       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
19917       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
19918       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
19919       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
19920             uint32_t            : 27;
19921     } INTCLR_b;
19922   } ;
19923 
19924   union {
19925     __IOM uint32_t INTSET;                      /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
19926                                                                     generate an interrupt from this module.
19927                                                                     (Generally used for testing purposes).                     */
19928 
19929     struct {
19930       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
19931       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
19932       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
19933       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
19934       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
19935             uint32_t            : 27;
19936     } INTSET_b;
19937   } ;
19938   __IM  uint32_t  RESERVED1[12];
19939 
19940   union {
19941     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000140) DMA Trigger Enable                                         */
19942 
19943     struct {
19944       __IOM uint32_t DTHR       : 1;            /*!< [0..0] Trigger DMA upon when FIFO iss filled to level indicated
19945                                                      by the FIFO THRESHOLD,at granularity of 16 bytes only                     */
19946       __IOM uint32_t DTHR90     : 1;            /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also
19947                                                      used internally for AUTOHIP function                                      */
19948             uint32_t            : 30;
19949     } DMATRIGEN_b;
19950   } ;
19951 
19952   union {
19953     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000144) DMA Trigger Status                                         */
19954 
19955     struct {
19956       __IOM uint32_t DTHRSTAT   : 1;            /*!< [0..0] Triggered DMA from FIFO reaching threshold                         */
19957       __IOM uint32_t DTHR90STAT : 1;            /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full                   */
19958             uint32_t            : 30;
19959     } DMATRIGSTAT_b;
19960   } ;
19961 
19962   union {
19963     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000148) DMA Configuration                                          */
19964 
19965     struct {
19966       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
19967             uint32_t            : 1;
19968       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
19969             uint32_t            : 5;
19970       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
19971       __IOM uint32_t DAUTOHIP   : 1;            /*!< [9..9] Raise priority to high on fifo full, and DMAPRI set to
19972                                                      low                                                                       */
19973       __IOM uint32_t DPWROFF    : 1;            /*!< [10..10] Power Off the ADC System upon DMACPL.                            */
19974             uint32_t            : 21;
19975     } DMACFG_b;
19976   } ;
19977   __IM  uint32_t  RESERVED2[2];
19978 
19979   union {
19980     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000154) DMA Target Address                                         */
19981 
19982     struct {
19983       __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address. This register is not updated with
19984                                                      the current address of the DMA, but will remain static
19985                                                      with the original address during the DMA transfer.                        */
19986       __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
19987     } DMATARGADDR_b;
19988   } ;
19989 
19990   union {
19991     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000158) DMA Status                                                 */
19992 
19993     struct {
19994       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
19995       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
19996       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
19997             uint32_t            : 29;
19998     } DMASTAT_b;
19999   } ;
20000   __IM  uint32_t  RESERVED3[61];
20001 
20002   union {
20003     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000250) DMA Total Transfer Count                                   */
20004 
20005     struct {
20006       __IOM uint32_t TOTCOUNT   : 20;           /*!< [19..0] Total Transfer Count. The transfer count must be a multiple
20007                                                      of the THR setting to avoid DMA overruns.                                 */
20008             uint32_t            : 12;
20009     } DMATOTCOUNT_b;
20010   } ;
20011 } PDM0_Type;                                    /*!< Size = 596 (0x254)                                                        */
20012 
20013 
20014 
20015 /* =========================================================================================================================== */
20016 /* ================                                          PWRCTRL                                          ================ */
20017 /* =========================================================================================================================== */
20018 
20019 
20020 /**
20021   * @brief PWR Controller Register Bank (PWRCTRL)
20022   */
20023 
20024 typedef struct {                                /*!< (@ 0x40021000) PWRCTRL Structure                                          */
20025 
20026   union {
20027     __IOM uint32_t MCUPERFREQ;                  /*!< (@ 0x00000000) This register provides the performance mode knobs
20028                                                                     for MCU. S/w should write the *PERFREQ field
20029                                                                     to desired mode and wait for the *PERFACK
20030                                                                     and check for the *PERFSTATUS. Some times
20031                                                                     system may not allow certain modes but *PERFACK
20032                                                                     should always follow *PERFREQ change.                      */
20033 
20034     struct {
20035       __IOM uint32_t MCUPERFREQ : 2;            /*!< [1..0] MCU Performance mode request                                       */
20036       __IOM uint32_t MCUPERFACK : 1;            /*!< [2..2] Indicates the MCU performance status indicated in STATUS
20037                                                      register is valid.                                                        */
20038       __IOM uint32_t MCUPERFSTATUS : 2;         /*!< [4..3] MCU Performance mode request                                       */
20039             uint32_t            : 27;
20040     } MCUPERFREQ_b;
20041   } ;
20042 
20043   union {
20044     __IOM uint32_t DEVPWREN;                    /*!< (@ 0x00000004) This enables various peripherals power domains.            */
20045 
20046     struct {
20047       __IOM uint32_t PWRENIOS   : 1;            /*!< [0..0] Power up IO Slave                                                  */
20048       __IOM uint32_t PWRENIOM0  : 1;            /*!< [1..1] Power up IO Master 0                                               */
20049       __IOM uint32_t PWRENIOM1  : 1;            /*!< [2..2] Power up IO Master 1                                               */
20050       __IOM uint32_t PWRENIOM2  : 1;            /*!< [3..3] Power up IO Master 2                                               */
20051       __IOM uint32_t PWRENIOM3  : 1;            /*!< [4..4] Power up IO Master 3                                               */
20052       __IOM uint32_t PWRENIOM4  : 1;            /*!< [5..5] Power up IO Master 4                                               */
20053       __IOM uint32_t PWRENIOM5  : 1;            /*!< [6..6] Power up IO Master 5                                               */
20054       __IOM uint32_t PWRENIOM6  : 1;            /*!< [7..7] Power up IO Master 6                                               */
20055       __IOM uint32_t PWRENIOM7  : 1;            /*!< [8..8] Power up IO Master 7                                               */
20056       __IOM uint32_t PWRENUART0 : 1;            /*!< [9..9] Power up UART Controller 0                                         */
20057       __IOM uint32_t PWRENUART1 : 1;            /*!< [10..10] Power up UART Controller 1                                       */
20058       __IOM uint32_t PWRENUART2 : 1;            /*!< [11..11] Power up UART Controller 2                                       */
20059       __IOM uint32_t PWRENUART3 : 1;            /*!< [12..12] Power up UART Controller 3                                       */
20060       __IOM uint32_t PWRENADC   : 1;            /*!< [13..13] Power up ADC Digital Controller                                  */
20061       __IOM uint32_t PWRENMSPI0 : 1;            /*!< [14..14] Power up MSPI Controller0                                        */
20062       __IOM uint32_t PWRENMSPI1 : 1;            /*!< [15..15] Power up MSPI Controller1                                        */
20063       __IOM uint32_t PWRENMSPI2 : 1;            /*!< [16..16] Power up MSPI Controller2                                        */
20064       __IOM uint32_t PWRENGFX   : 1;            /*!< [17..17] Power up GFX controller                                          */
20065       __IOM uint32_t PWRENDISP  : 1;            /*!< [18..18] Power up DISP controller                                         */
20066       __IOM uint32_t PWRENDISPPHY : 1;          /*!< [19..19] Power up DISP PHY                                                */
20067       __IOM uint32_t PWRENCRYPTO : 1;           /*!< [20..20] Power up CRYPTO module                                           */
20068       __IOM uint32_t PWRENSDIO  : 1;            /*!< [21..21] Power up SDIO controller                                         */
20069       __IOM uint32_t PWRENUSB   : 1;            /*!< [22..22] Power up USB controller                                          */
20070       __IOM uint32_t PWRENUSBPHY : 1;           /*!< [23..23] Power up USB PHY                                                 */
20071       __IOM uint32_t PWRENDBG   : 1;            /*!< [24..24] Powerup DBG power domain                                         */
20072             uint32_t            : 7;
20073     } DEVPWREN_b;
20074   } ;
20075 
20076   union {
20077     __IOM uint32_t DEVPWRSTATUS;                /*!< (@ 0x00000008) This provides the power status for the peripheral
20078                                                                     device domains controlled through DEVPWREN
20079                                                                     register. Value of 1 means the device is
20080                                                                     powred up and ready to be used and 0 means
20081                                                                     its not powered up.                                        */
20082 
20083     struct {
20084       __IOM uint32_t PWRSTIOS   : 1;            /*!< [0..0] Power status IO Slave                                              */
20085       __IOM uint32_t PWRSTIOM0  : 1;            /*!< [1..1] Power status IO Master 0                                           */
20086       __IOM uint32_t PWRSTIOM1  : 1;            /*!< [2..2] Power status IO Master 1                                           */
20087       __IOM uint32_t PWRSTIOM2  : 1;            /*!< [3..3] Power status IO Master 2                                           */
20088       __IOM uint32_t PWRSTIOM3  : 1;            /*!< [4..4] Power status IO Master 3                                           */
20089       __IOM uint32_t PWRSTIOM4  : 1;            /*!< [5..5] Power status IO Master 4                                           */
20090       __IOM uint32_t PWRSTIOM5  : 1;            /*!< [6..6] Power Status IO Master 5                                           */
20091       __IOM uint32_t PWRSTIOM6  : 1;            /*!< [7..7] Power Status IO Master 6                                           */
20092       __IOM uint32_t PWRSTIOM7  : 1;            /*!< [8..8] Power Status IO Master 7                                           */
20093       __IOM uint32_t PWRSTUART0 : 1;            /*!< [9..9] Power Status UART Controller 0                                     */
20094       __IOM uint32_t PWRSTUART1 : 1;            /*!< [10..10] Power Status UART Controller 1                                   */
20095       __IOM uint32_t PWRSTUART2 : 1;            /*!< [11..11] Power Status UART Controller 2                                   */
20096       __IOM uint32_t PWRSTUART3 : 1;            /*!< [12..12] Power Status UART Controller 3                                   */
20097       __IOM uint32_t PWRSTADC   : 1;            /*!< [13..13] Power Status ADC Digital Controller                              */
20098       __IOM uint32_t PWRSTMSPI0 : 1;            /*!< [14..14] Power Status MSPI Controller0                                    */
20099       __IOM uint32_t PWRSTMSPI1 : 1;            /*!< [15..15] Power Status MSPI Controller1                                    */
20100       __IOM uint32_t PWRSTMSPI2 : 1;            /*!< [16..16] Power Status MSPI Controller2                                    */
20101       __IOM uint32_t PWRSTGFX   : 1;            /*!< [17..17] Power Status GFX controller                                      */
20102       __IOM uint32_t PWRSTDISP  : 1;            /*!< [18..18] Power Status DISP controller                                     */
20103       __IOM uint32_t PWRSTDISPPHY : 1;          /*!< [19..19] Power Status DISP PHY                                            */
20104       __IOM uint32_t PWRSTCRYPTO : 1;           /*!< [20..20] Power Status CRYPTO module                                       */
20105       __IOM uint32_t PWRSTSDIO  : 1;            /*!< [21..21] Power Status SDIO controller                                     */
20106       __IOM uint32_t PWRSTUSB   : 1;            /*!< [22..22] Power Status USB controller                                      */
20107       __IOM uint32_t PWRSTUSBPHY : 1;           /*!< [23..23] Power Status USB PHY                                             */
20108       __IOM uint32_t PWRSTDBG   : 1;            /*!< [24..24] Power Status DBG subsystem                                       */
20109             uint32_t            : 7;
20110     } DEVPWRSTATUS_b;
20111   } ;
20112 
20113   union {
20114     __IOM uint32_t AUDSSPWREN;                  /*!< (@ 0x0000000C) This enables various power domains in audio subsystem.     */
20115 
20116     struct {
20117       __IOM uint32_t PWRENAUDREC : 1;           /*!< [0..0] Power up Audio Record                                              */
20118       __IOM uint32_t PWRENAUDPB : 1;            /*!< [1..1] Power up Audio Playback                                            */
20119       __IOM uint32_t PWRENPDM0  : 1;            /*!< [2..2] Power up audio subsystem PDM0 domain                               */
20120       __IOM uint32_t PWRENPDM1  : 1;            /*!< [3..3] Power up audio subsystem PDM1 domain                               */
20121       __IOM uint32_t PWRENPDM2  : 1;            /*!< [4..4] Power up audio subsystem PDM2 domain                               */
20122       __IOM uint32_t PWRENPDM3  : 1;            /*!< [5..5] Power up audio subsystem PDM3 domain                               */
20123       __IOM uint32_t PWRENI2S0  : 1;            /*!< [6..6] Power up audio subsystem I2S0 domain                               */
20124       __IOM uint32_t PWRENI2S1  : 1;            /*!< [7..7] Power up audio subsystem I2S1 domain                               */
20125             uint32_t            : 2;
20126       __IOM uint32_t PWRENAUDADC : 1;           /*!< [10..10] Power up audio subsystem ADC domain                              */
20127       __IOM uint32_t PWRENDSPA  : 1;            /*!< [11..11] Enable one or more DSP subsystems                                */
20128             uint32_t            : 20;
20129     } AUDSSPWREN_b;
20130   } ;
20131 
20132   union {
20133     __IOM uint32_t AUDSSPWRSTATUS;              /*!< (@ 0x00000010) This provides the power status for the peripheral
20134                                                                     domains controlled through AUDSSPWREN register.
20135                                                                     Value of 1 means the device is powred up
20136                                                                     and ready to be used and 0 means its not
20137                                                                     powered up.                                                */
20138 
20139     struct {
20140       __IOM uint32_t PWRSTAUDREC : 1;           /*!< [0..0] Power Status Audio Record block                                    */
20141       __IOM uint32_t PWRSTAUDPB : 1;            /*!< [1..1] Power Status Audio Playback block                                  */
20142       __IOM uint32_t PWRSTPDM0  : 1;            /*!< [2..2] Power Status audio subsystem PDM0 domain                           */
20143       __IOM uint32_t PWRSTPDM1  : 1;            /*!< [3..3] Power Status audio subsystem PDM1 domain                           */
20144       __IOM uint32_t PWRSTPDM2  : 1;            /*!< [4..4] Power Status audio subsystem PDM2 domain                           */
20145       __IOM uint32_t PWRSTPDM3  : 1;            /*!< [5..5] Power Status audio subsystem PDM3 domain                           */
20146       __IOM uint32_t PWRSTI2S0  : 1;            /*!< [6..6] Power Status audio subsystem I2S0 domain                           */
20147       __IOM uint32_t PWRSTI2S1  : 1;            /*!< [7..7] Power Status audio subsystem I2S1 domain                           */
20148             uint32_t            : 2;
20149       __IOM uint32_t PWRSTAUDADC : 1;           /*!< [10..10] Power Status audio subsystem ADC domain                          */
20150       __IOM uint32_t PWRSTDSPA  : 1;            /*!< [11..11] Power Status DSPA subsystem                                      */
20151             uint32_t            : 20;
20152     } AUDSSPWRSTATUS_b;
20153   } ;
20154 
20155   union {
20156     __IOM uint32_t MEMPWREN;                    /*!< (@ 0x00000014) This register enables the individual banks for
20157                                                                     the memories. When set, power will be enabled
20158                                                                     to the banks. This register works in conjunction
20159                                                                     with the MEMRETCFG register. If this register
20160                                                                     is not set, then power will always be disabled
20161                                                                     to the memory bank.                                        */
20162 
20163     struct {
20164       __IOM uint32_t PWRENDTCM  : 3;            /*!< [2..0] Power up DTCM                                                      */
20165       __IOM uint32_t PWRENNVM0  : 1;            /*!< [3..3] Power up NVM0                                                      */
20166       __IOM uint32_t PWRENCACHEB0 : 1;          /*!< [4..4] Power up Cache Bank 0. This works in conjunction with
20167                                                      Cache enable from flash_cache module. To power up cache
20168                                                      bank0, cache has to be enabled and this bit has to be set.                */
20169       __IOM uint32_t PWRENCACHEB2 : 1;          /*!< [5..5] Power up Cache Bank 2. This works in conjunction with
20170                                                      Cache enable from flash_cache module. To power up cache
20171                                                      bank2, cache has to be enabled and this bit has to be set.                */
20172             uint32_t            : 26;
20173     } MEMPWREN_b;
20174   } ;
20175 
20176   union {
20177     __IOM uint32_t MEMPWRSTATUS;                /*!< (@ 0x00000018) It provides the power status for all the memory
20178                                                                     banks including- caches, nvm (0 and 1) and
20179                                                                     all the SRAM groups. The status here should
20180                                                                     reflect the enable provided by the MEMPWREN
20181                                                                     register. There may be a lag time between
20182                                                                     setting the bits in MEMPWREN register and
20183                                                                     MEMPWRSTATUS register, due to the need to
20184                                                                     cycle the power gate and isolation seqeunces
20185                                                                     to the memory banks.                                       */
20186 
20187     struct {
20188       __IOM uint32_t PWRSTDTCM  : 3;            /*!< [2..0] Power status for DTCM. Each bit corresponds to one of
20189                                                      the TCMs. bit0=DTCM0_0, bit1=DTCM0_1, bit2=DTCM1.                         */
20190       __IOM uint32_t PWRSTNVM0  : 1;            /*!< [3..3] This bit is 1 if power is supplied to NVM 0                        */
20191       __IOM uint32_t PWRSTCACHEB0 : 1;          /*!< [4..4] This bit is 1 if power is supplied to Cache Bank 0                 */
20192       __IOM uint32_t PWRSTCACHEB2 : 1;          /*!< [5..5] This bit is 1 if power is supplied to Cache Bank 2                 */
20193             uint32_t            : 26;
20194     } MEMPWRSTATUS_b;
20195   } ;
20196 
20197   union {
20198     __IOM uint32_t MEMRETCFG;                   /*!< (@ 0x0000001C) This controls the power down of the SRAM banks
20199                                                                     in deep sleep mode. If this is set, then
20200                                                                     the power for that SRAM bank will be gated
20201                                                                     when the core goes into deep sleep. Upon
20202                                                                     wake, the data within the SRAMs will be
20203                                                                     erased. If this is not set, retention voltage
20204                                                                     will be applied to the SRAM bank when the
20205                                                                     core goes into deep sleep. Upon wake, the
20206                                                                     data within the SRAMs are retained. Do not
20207                                                                     set this if the SRAM bank is used as the
20208                                                                     target for DMA transfer while CPU in deepsleep.            */
20209 
20210     struct {
20211       __IOM uint32_t DTCMPWDSLP : 3;            /*!< [2..0] power down DTCM in deep sleep                                      */
20212       __IOM uint32_t NVM0PWDSLP : 1;            /*!< [3..3] Powerdown NVM0 in deep sleep                                       */
20213       __IOM uint32_t CACHEPWDSLP : 1;           /*!< [4..4] power down cache in deep sleep                                     */
20214             uint32_t            : 27;
20215     } MEMRETCFG_b;
20216   } ;
20217 
20218   union {
20219     __IOM uint32_t SYSPWRSTATUS;                /*!< (@ 0x00000020) Power ON Status for domains that are not part
20220                                                                     of devpwrstatus or mempwrstatus                            */
20221 
20222     struct {
20223       __IOM uint32_t PWRSTMCUL  : 1;            /*!< [0..0] Power Domain status for MCUL                                       */
20224       __IOM uint32_t PWRSTMCUH  : 1;            /*!< [1..1] Power Domain status for MCUH                                       */
20225       __IOM uint32_t PWRSTDSP0H : 1;            /*!< [2..2] Power Domain status for DSP0H                                      */
20226       __IOM uint32_t PWRSTDSP1H : 1;            /*!< [3..3] Power Domain status for DSP1H                                      */
20227             uint32_t            : 25;
20228       __IOM uint32_t CORESLEEP  : 1;            /*!< [29..29] Indicates MCU entered SLEEP state since it was last
20229                                                      cleared. Write 1 to to clear it.                                          */
20230       __IOM uint32_t COREDEEPSLEEP : 1;         /*!< [30..30] Indicates MCU entered DEEPSLEEP state since it was
20231                                                      last cleared. Write 1 to to clear it.                                     */
20232       __IOM uint32_t SYSDEEPSLEEP : 1;          /*!< [31..31] Indicates all device domains powered down and MCU entered
20233                                                      DEEPSLEEP state since it was last cleared. Write 1 to to
20234                                                      clear it.                                                                 */
20235     } SYSPWRSTATUS_b;
20236   } ;
20237 
20238   union {
20239     __IOM uint32_t SSRAMPWREN;                  /*!< (@ 0x00000024) This register enables the individual banks for
20240                                                                     the memories. When set, power will be enabled
20241                                                                     to the banks. This register works in conjunction
20242                                                                     with the SSRAMRETCFG register. If this register
20243                                                                     is not set, then power will always be disabled
20244                                                                     to the memory bank.                                        */
20245 
20246     struct {
20247       __IOM uint32_t PWRENSSRAM : 2;            /*!< [1..0] Power up SRAM groups                                               */
20248             uint32_t            : 30;
20249     } SSRAMPWREN_b;
20250   } ;
20251 
20252   union {
20253     __IOM uint32_t SSRAMPWRST;                  /*!< (@ 0x00000028) It provides the power status for shared sram
20254                                                                     banks. The status here should reflect the
20255                                                                     enable provided by the SSRAMPWREN register.                */
20256 
20257     struct {
20258       __IOM uint32_t SSRAMPWRST : 2;            /*!< [1..0] Each bit corresponds to 512K SSRAM groups. Power Status-
20259                                                      1:ON, 0:OFF                                                               */
20260             uint32_t            : 30;
20261     } SSRAMPWRST_b;
20262   } ;
20263 
20264   union {
20265     __IOM uint32_t SSRAMRETCFG;                 /*!< (@ 0x0000002C) This controls the power down of the Shared SRAM
20266                                                                     banks in deep sleep mode. If this is set,
20267                                                                     then the power for that SRAM bank will be
20268                                                                     gated when the core goes into deep sleep.
20269                                                                     Upon wake, the data within the SRAMs will
20270                                                                     be erased. If this is not set, retention
20271                                                                     voltage will be applied to the SRAM bank
20272                                                                     when none of the CPU agents are in powered
20273                                                                     up and active mode. Do not set this if the
20274                                                                     SRAM bank is used as the target for DMA
20275                                                                     transfer while CPU in deepsleep.                           */
20276 
20277     struct {
20278       __IOM uint32_t SSRAMPWDSLP : 2;           /*!< [1..0] Selects which shared SRAM banks are powered down in deep
20279                                                      sleep mode, causing the contents of the bank to be lost.                  */
20280       __IOM uint32_t SSRAMACTMCU : 2;           /*!< [3..2] Keep the memory domain active based on MCU state. Each
20281                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Wakeup
20282                                                      on demand (i.e. when MCU is powered up)                                   */
20283       __IOM uint32_t SSRAMACTDSP : 2;           /*!< [5..4] Keep the memory domain active based on DSP state. Each
20284                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
20285                                                      on demand (i.e. when DSP is powered up)                                   */
20286       __IOM uint32_t SSRAMACTGFX : 2;           /*!< [7..6] Keep the memory domain active based on GFX state. Each
20287                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
20288                                                      on demand (i.e. when GFX is powered up)                                   */
20289       __IOM uint32_t SSRAMACTDISP : 2;          /*!< [9..8] Keep the memory domain active based on DISP state. Each
20290                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
20291                                                      on demand (i.e. when DISP is powered up)                                  */
20292             uint32_t            : 22;
20293     } SSRAMRETCFG_b;
20294   } ;
20295 
20296   union {
20297     __IOM uint32_t DEVPWREVENTEN;               /*!< (@ 0x00000030) This register controls which feature trigger
20298                                                                     will result in an event to the CPU. It includes
20299                                                                     all the power on status for the core domains.
20300                                                                     If any bits are set, then if the domain
20301                                                                     is turned on, it will result in an event
20302                                                                     to the ARM core.                                           */
20303 
20304     struct {
20305       __IOM uint32_t MCULEVEN   : 1;            /*!< [0..0] Control MCUL power-on status event                                 */
20306       __IOM uint32_t MCUHEVEN   : 1;            /*!< [1..1] Control MCUH power-on status event                                 */
20307       __IOM uint32_t HCPAEVEN   : 1;            /*!< [2..2] Control HCPA power-on status event                                 */
20308       __IOM uint32_t HCPBEVEN   : 1;            /*!< [3..3] Control HCPB power-on status event                                 */
20309       __IOM uint32_t HCPCEVEN   : 1;            /*!< [4..4] Control HCPC power-on status event                                 */
20310       __IOM uint32_t ADCEVEN    : 1;            /*!< [5..5] Control ADC power-on status event                                  */
20311       __IOM uint32_t MSPIEVEN   : 1;            /*!< [6..6] Control MSPI power-on status event                                 */
20312       __IOM uint32_t AUDEVEN    : 1;            /*!< [7..7] Control AUD power-on status event                                  */
20313             uint32_t            : 24;
20314     } DEVPWREVENTEN_b;
20315   } ;
20316 
20317   union {
20318     __IOM uint32_t MEMPWREVENTEN;               /*!< (@ 0x00000034) This register controls which power enable for
20319                                                                     the memories will result in an event to
20320                                                                     the CPU. It includes all the power on status
20321                                                                     for the memory domains. If any bits are
20322                                                                     set, then if the domain is turned on, it
20323                                                                     will result in an event to the ARM core.                   */
20324 
20325     struct {
20326       __IOM uint32_t DTCMEN     : 3;            /*!< [2..0] Enable DTCM power-on status event                                  */
20327       __IOM uint32_t NVM0EN     : 1;            /*!< [3..3] Control NVM power-on status event                                  */
20328       __IOM uint32_t CACHEB0EN  : 1;            /*!< [4..4] Control CACHE BANK 0 power-on status event                         */
20329       __IOM uint32_t CACHEB2EN  : 1;            /*!< [5..5] Control CACHEB2 power-on status event                              */
20330             uint32_t            : 26;
20331     } MEMPWREVENTEN_b;
20332   } ;
20333   __IM  uint32_t  RESERVED[2];
20334 
20335   union {
20336     __IOM uint32_t MMSOVERRIDE;                 /*!< (@ 0x00000040) Power domain behavior overrides related to MMS
20337                                                                     ( Multimedia System ).                                     */
20338 
20339     struct {
20340       __IOM uint32_t MMSOVRMCULDISP : 1;        /*!< [0..0] MMS override for MCUL on by PD_DISP setting.                       */
20341       __IOM uint32_t MMSOVRMCULGFX : 1;         /*!< [1..1] MMS override for MCUL on by PD_GFX setting.                        */
20342       __IOM uint32_t MMSOVRSSRAMDISP : 1;       /*!< [2..2] MMS override for SSRAM power state by PD_DISP power setting.       */
20343       __IOM uint32_t MMSOVRSSRAMGFX : 1;        /*!< [3..3] MMS override for SSRAM power state by PD_GFX power setting.        */
20344       __IOM uint32_t MMSOVRDSPRAMRETDISP : 2;   /*!< [5..4] If set, retention equation doesn't consider DISP. Each
20345                                                      bit corresponds to a domain.                                              */
20346       __IOM uint32_t MMSOVRDSPRAMRETGFX : 2;    /*!< [7..6] If set, retention equation doesn't consider GFX. Each
20347                                                      bit corresponds to a domain.                                              */
20348       __IOM uint32_t MMSOVRSSRAMRETDISP : 2;    /*!< [9..8] If set, retention equation doesn't consider DISP. Each
20349                                                      bit corresponds to a domain.                                              */
20350       __IOM uint32_t MMSOVRSSRAMRETGFX : 2;     /*!< [11..10] If set, retention equation doesn't consider GFX. Each
20351                                                      bit corresponds to a domain.                                              */
20352             uint32_t            : 20;
20353     } MMSOVERRIDE_b;
20354   } ;
20355   __IM  uint32_t  RESERVED1[3];
20356 
20357   union {
20358     __IOM uint32_t DSP0PWRCTRL;                 /*!< (@ 0x00000050) Power and RST controls for DSP0                            */
20359 
20360     struct {
20361       __IOM uint32_t DSP0PCMRSTDLY : 4;         /*!< [3..0] PCM Reset delay in number of 24MHz clocks.                         */
20362       __IOM uint32_t DSP0PCMRSTOR : 1;          /*!< [4..4] PCM Reset override. If this is disabled, then h/w will
20363                                                      handle the de-assertion of pcm reset.                                     */
20364             uint32_t            : 27;
20365     } DSP0PWRCTRL_b;
20366   } ;
20367 
20368   union {
20369     __IOM uint32_t DSP0PERFREQ;                 /*!< (@ 0x00000054) This register provides the performance mode knobs
20370                                                                     for DSP0. S/w should write the *PERFREQ
20371                                                                     field to desired mode and wait for the *PERFACK
20372                                                                     and check for the *PERFSTATUS. Some times
20373                                                                     system may not allow certain modes but *PERFACK
20374                                                                     should always follow *PERFREQ change.                      */
20375 
20376     struct {
20377       __IOM uint32_t DSP0PERFREQ : 2;           /*!< [1..0] DSP0 Performance mode request                                      */
20378       __IOM uint32_t DSP0PERFACK : 1;           /*!< [2..2] Indicates the DSP0 performance status indicated in STATUS
20379                                                      register is valid.                                                        */
20380       __IOM uint32_t DSP0PERFSTATUS : 2;        /*!< [4..3] DSP0 Performance mode request                                      */
20381             uint32_t            : 27;
20382     } DSP0PERFREQ_b;
20383   } ;
20384 
20385   union {
20386     __IOM uint32_t DSP0MEMPWREN;                /*!< (@ 0x00000058) This register enables the individual banks for
20387                                                                     the memories. When set, power will be enabled
20388                                                                     to the banks. This register works in conjunction
20389                                                                     with the DSP0MEMRETCFG register when DSP0
20390                                                                     is OFF.                                                    */
20391 
20392     struct {
20393       __IOM uint32_t PWRENDSP0RAM : 1;          /*!< [0..0] Power up DSP0 IRAM and DRAM                                        */
20394       __IOM uint32_t PWRENDSP0ICACHE : 1;       /*!< [1..1] Power up DSP0 ICACHE banks                                         */
20395             uint32_t            : 30;
20396     } DSP0MEMPWREN_b;
20397   } ;
20398 
20399   union {
20400     __IOM uint32_t DSP0MEMPWRST;                /*!< (@ 0x0000005C) It provides the power status for all the memories
20401                                                                     of DSP0 subsystem                                          */
20402 
20403     struct {
20404       __IOM uint32_t PWRSTDSP0RAM : 1;          /*!< [0..0] Status- 1:ON, 0:OFF                                                */
20405       __IOM uint32_t PWRSTDSP0ICACHE : 1;       /*!< [1..1] Power Status- 1:ON, 0:OFF                                          */
20406             uint32_t            : 30;
20407     } DSP0MEMPWRST_b;
20408   } ;
20409 
20410   union {
20411     __IOM uint32_t DSP0MEMRETCFG;               /*!< (@ 0x00000060) This controls the power down of the DRAM/IRAM/CACHE
20412                                                                     banks when DSP0 is powered off. If this
20413                                                                     is set, then the power for that corresponding
20414                                                                     SRAM bank will be gated when the DSP0 is
20415                                                                     powered off and data is erased. If this
20416                                                                     is not set, retention voltage will be applied
20417                                                                     when DSP0 is powered off. Do not set this
20418                                                                     if the SRAM bank is used as the target for
20419                                                                     DMA transfer while DSP0 is powered off.                    */
20420 
20421     struct {
20422       __IOM uint32_t RAMPWDDSP0OFF : 1;         /*!< [0..0] IRAM/DRAM banks are powered down when DSP0 is switched
20423                                                      off, causing the contents of the bank to be lost.                         */
20424       __IOM uint32_t DSP0RAMACTMCU : 1;         /*!< [1..1] Keep the memory domain active based on MCU state.                  */
20425       __IOM uint32_t ICACHEPWDDSP0OFF : 1;      /*!< [2..2] ICACHE is powered down when DSP0 is switched off, causing
20426                                                      the contents of the bank to be lost.                                      */
20427       __IOM uint32_t DSP0RAMACTDISP : 1;        /*!< [3..3] Keep the memory domain active based on DISP state.                 */
20428       __IOM uint32_t DSP0RAMACTGFX : 1;         /*!< [4..4] Keep the memory domain active based on GFX state.                  */
20429             uint32_t            : 27;
20430     } DSP0MEMRETCFG_b;
20431   } ;
20432   __IM  uint32_t  RESERVED2[3];
20433 
20434   union {
20435     __IOM uint32_t DSP1PWRCTRL;                 /*!< (@ 0x00000070) Power and RST controls for DSP1                            */
20436 
20437     struct {
20438       __IOM uint32_t DSP1PCMRSTDLY : 4;         /*!< [3..0] PCM Reset delay in number of 24MHz clocks.                         */
20439       __IOM uint32_t DSP1PCMRSTOR : 1;          /*!< [4..4] PCM Reset override. If this is disabled, then h/w will
20440                                                      handle the de-assertion of pcm reset.                                     */
20441             uint32_t            : 27;
20442     } DSP1PWRCTRL_b;
20443   } ;
20444 
20445   union {
20446     __IOM uint32_t DSP1PERFREQ;                 /*!< (@ 0x00000074) This register provides the performance mode knobs
20447                                                                     for DSP1. S/w should write the *PERFREQ
20448                                                                     field to desired mode and wait for the *PERFACK
20449                                                                     and check for the *PERFSTATUS. Some times
20450                                                                     system may not allow certain modes but *PERFACK
20451                                                                     should always follow *PERFREQ change.                      */
20452 
20453     struct {
20454       __IOM uint32_t DSP1PERFREQ : 2;           /*!< [1..0] DSP1 Performance mode request                                      */
20455       __IOM uint32_t DSP1PERFACK : 1;           /*!< [2..2] Indicates the DSP1 performance status indicated in STATUS
20456                                                      register is valid.                                                        */
20457       __IOM uint32_t DSP1PERFSTATUS : 2;        /*!< [4..3] DSP1 Performance mode request                                      */
20458             uint32_t            : 27;
20459     } DSP1PERFREQ_b;
20460   } ;
20461 
20462   union {
20463     __IOM uint32_t DSP1MEMPWREN;                /*!< (@ 0x00000078) This register enables the individual banks for
20464                                                                     the memories. When set, power will be enabled
20465                                                                     to the banks. This register works in conjunction
20466                                                                     with the DSP1MEMRETCFG register when DSP1
20467                                                                     is OFF.                                                    */
20468 
20469     struct {
20470       __IOM uint32_t PWRENDSP1RAM : 1;          /*!< [0..0] Power up DSP1 IRAM and DRAM                                        */
20471       __IOM uint32_t PWRENDSP1ICACHE : 1;       /*!< [1..1] Power up DSP1 ICACHE banks                                         */
20472             uint32_t            : 30;
20473     } DSP1MEMPWREN_b;
20474   } ;
20475 
20476   union {
20477     __IOM uint32_t DSP1MEMPWRST;                /*!< (@ 0x0000007C) It provides the power status for all the memories
20478                                                                     of DSP1 subsystem                                          */
20479 
20480     struct {
20481       __IOM uint32_t PWRSTDSP1RAM : 1;          /*!< [0..0] Status- 1:ON, 0:OFF                                                */
20482       __IOM uint32_t PWRSTDSP1ICACHE : 1;       /*!< [1..1] Power Status- 1:ON, 0:OFF                                          */
20483             uint32_t            : 30;
20484     } DSP1MEMPWRST_b;
20485   } ;
20486 
20487   union {
20488     __IOM uint32_t DSP1MEMRETCFG;               /*!< (@ 0x00000080) This controls the power down of the DRAM/IRAM/CACHE
20489                                                                     banks when DSP1 is powered off. If this
20490                                                                     is set, then the power for that corresponding
20491                                                                     SRAM bank will be gated when the DSP1 is
20492                                                                     powered off and data is erased. If this
20493                                                                     is not set, retention voltage will be applied
20494                                                                     when DSP1 is powered off. Do not set this
20495                                                                     if the SRAM bank is used as the target for
20496                                                                     DMA transfer while DSP1 is powered off.                    */
20497 
20498     struct {
20499       __IOM uint32_t RAMPWDDSP1OFF : 1;         /*!< [0..0] IRAM/DRAM banks are powered down when DSP1 is switched
20500                                                      off, causing the contents of the bank to be lost.                         */
20501       __IOM uint32_t DSP1RAMACTMCU : 1;         /*!< [1..1] Keep the memory domain active based on MCU state.                  */
20502       __IOM uint32_t ICACHEPWDDSP1OFF : 1;      /*!< [2..2] ICACHE is powered down when DSP1 is switched off, causing
20503                                                      the contents of the bank to be lost.                                      */
20504       __IOM uint32_t DSP1RAMACTDISP : 1;        /*!< [3..3] Keep the memory domain active based on DISP state.                 */
20505       __IOM uint32_t DSP1RAMACTGFX : 1;         /*!< [4..4] Keep the memory domain active based on GFX state.                  */
20506             uint32_t            : 27;
20507     } DSP1MEMRETCFG_b;
20508   } ;
20509   __IM  uint32_t  RESERVED3[31];
20510 
20511   union {
20512     __IOM uint32_t VRCTRL;                      /*!< (@ 0x00000100) This register includes additional debug control
20513                                                                     bits. This is an internal Ambiq-only register.
20514                                                                     Customers should not attempt to change this
20515                                                                     or else functionality cannot be guaranteed.                */
20516 
20517     struct {
20518       __IOM uint32_t SIMOBUCKEN : 1;            /*!< [0..0] Enables and Selects the SIMO Buck as the supply for the
20519                                                      low-voltage power domains. It takes the initial value from
20520                                                      the bit set in Customer INFO space.                                       */
20521             uint32_t            : 31;
20522     } VRCTRL_b;
20523   } ;
20524 
20525   union {
20526     __IOM uint32_t LEGACYVRLPOVR;               /*!< (@ 0x00000104) When an override is set for a power domain, VR
20527                                                                     logic will ignore that power domain state
20528                                                                     in making a decision to go into lp state.                  */
20529 
20530     struct {
20531       __IOM uint32_t IGNOREIOS  : 1;            /*!< [0..0] Ignore IOS                                                         */
20532       __IOM uint32_t IGNOREHCPA : 1;            /*!< [1..1] Ignore HCPA                                                        */
20533       __IOM uint32_t IGNOREHCPB : 1;            /*!< [2..2] Ignore HCPB                                                        */
20534       __IOM uint32_t IGNOREHCPC : 1;            /*!< [3..3] Ignore HCPC                                                        */
20535       __IOM uint32_t IGNOREHCPD : 1;            /*!< [4..4] Ignore HCPD                                                        */
20536       __IOM uint32_t IGNOREHCPE : 1;            /*!< [5..5] Ignore HCPE                                                        */
20537       __IOM uint32_t IGNOREMSPI : 1;            /*!< [6..6] Ignore MSPI                                                        */
20538       __IOM uint32_t IGNOREGFX  : 1;            /*!< [7..7] Ignore GFX                                                         */
20539       __IOM uint32_t IGNOREDISP : 1;            /*!< [8..8] Ignore DISP Control                                                */
20540       __IOM uint32_t IGNOREDISPPHY : 1;         /*!< [9..9] Ignore DISP PHY                                                    */
20541       __IOM uint32_t IGNORECRYPTO : 1;          /*!< [10..10] Ignore CRYPTO                                                    */
20542       __IOM uint32_t IGNORESDIO : 1;            /*!< [11..11] Ignore SDIO                                                      */
20543       __IOM uint32_t IGNOREUSB  : 1;            /*!< [12..12] Ignore USB Control                                               */
20544       __IOM uint32_t IGNOREUSBPHY : 1;          /*!< [13..13] Ignore USB PHY                                                   */
20545       __IOM uint32_t IGNOREAUD  : 1;            /*!< [14..14] Ignore AUD                                                       */
20546       __IOM uint32_t IGNOREDSPA : 1;            /*!< [15..15] Ignore DSPA                                                      */
20547       __IOM uint32_t IGNOREDSP0H : 1;           /*!< [16..16] Ignore DSP0H                                                     */
20548       __IOM uint32_t IGNOREDSP1H : 1;           /*!< [17..17] Ignore DSP1H                                                     */
20549       __IOM uint32_t IGNOREDBG  : 1;            /*!< [18..18] Ignore DBG                                                       */
20550             uint32_t            : 13;
20551     } LEGACYVRLPOVR_b;
20552   } ;
20553 
20554   union {
20555     __IOM uint32_t VRSTATUS;                    /*!< (@ 0x00000108) Provides BUCK and LDOs status.                             */
20556 
20557     struct {
20558       __IOM uint32_t CORELDOST  : 2;            /*!< [1..0] Indicates CORELDO status. bit[1] indicates ON/OFF and
20559                                                      bit[0] indicates ACT/LP.                                                  */
20560       __IOM uint32_t MEMLDOST   : 2;            /*!< [3..2] Indicates MEMLDO status. bit[1] indicates ON/OFF and
20561                                                      bit[0] indicates ACT/LP.                                                  */
20562       __IOM uint32_t SIMOBUCKST : 2;            /*!< [5..4] Indicates SIMO BUCK status. bit[1] indicates ON/OFF and
20563                                                      bit[0] indicates ACT/LP                                                   */
20564             uint32_t            : 26;
20565     } VRSTATUS_b;
20566   } ;
20567   __IM  uint32_t  RESERVED4[13];
20568 
20569   union {
20570     __IOM uint32_t PWRWEIGHTULP0;               /*!< (@ 0x00000140) Weights specified in this register are applied
20571                                                                     to each of the masters active requests.
20572                                                                     The aggregate of all the masters is compared
20573                                                                     against the allowed value to change the
20574                                                                     buck from active to inactive mode.                         */
20575 
20576     struct {
20577       __IOM uint32_t WTULPMCU   : 4;            /*!< [3..0] Weight used for ULP mode MCU                                       */
20578       __IOM uint32_t WTULPDSP0  : 4;            /*!< [7..4] Weight used for ULP mode DSP0                                      */
20579       __IOM uint32_t WTULPDSP1  : 4;            /*!< [11..8] Weight used for ULP mode DSP1                                     */
20580       __IOM uint32_t WTULPIOS   : 4;            /*!< [15..12] Weight used for ULP mode IOS                                     */
20581       __IOM uint32_t WTULPUART0 : 4;            /*!< [19..16] Weight used for ULP mode UART0                                   */
20582       __IOM uint32_t WTULPUART1 : 4;            /*!< [23..20] Weight used for ULP mode UART1                                   */
20583       __IOM uint32_t WTULPUART2 : 4;            /*!< [27..24] Weight used for ULP mode UART2                                   */
20584       __IOM uint32_t WTULPUART3 : 4;            /*!< [31..28] Weight used for ULP mode UART3                                   */
20585     } PWRWEIGHTULP0_b;
20586   } ;
20587 
20588   union {
20589     __IOM uint32_t PWRWEIGHTULP1;               /*!< (@ 0x00000144) Weights specified in this register are applied
20590                                                                     to each of the masters active requests.
20591                                                                     The aggregate of all the masters is compared
20592                                                                     against the allowed value to change the
20593                                                                     buck from active to inactive mode.                         */
20594 
20595     struct {
20596       __IOM uint32_t WTULPIOM0  : 4;            /*!< [3..0] Weight used for ULP mode IOM0                                      */
20597       __IOM uint32_t WTULPIOM1  : 4;            /*!< [7..4] Weight used for ULP mode IOM1                                      */
20598       __IOM uint32_t WTULPIOM2  : 4;            /*!< [11..8] Weight used for ULP mode IOM2                                     */
20599       __IOM uint32_t WTULPIOM3  : 4;            /*!< [15..12] Weight used for ULP mode IOM3                                    */
20600       __IOM uint32_t WTULPIOM4  : 4;            /*!< [19..16] Weight used for ULP mode IOM4                                    */
20601       __IOM uint32_t WTULPIOM5  : 4;            /*!< [23..20] Weight used for ULP mode IOM5                                    */
20602       __IOM uint32_t WTULPIOM6  : 4;            /*!< [27..24] Weight used for ULP mode IOM6                                    */
20603       __IOM uint32_t WTULPIOM7  : 4;            /*!< [31..28] Weight used for ULP mode IOM7                                    */
20604     } PWRWEIGHTULP1_b;
20605   } ;
20606 
20607   union {
20608     __IOM uint32_t PWRWEIGHTULP2;               /*!< (@ 0x00000148) Weights specified in this register are applied
20609                                                                     to each of the masters active requests.
20610                                                                     The aggregate of all the masters is compared
20611                                                                     against the allowed value to change the
20612                                                                     buck from active to inactive mode.                         */
20613 
20614     struct {
20615       __IOM uint32_t WTULPADC   : 4;            /*!< [3..0] Weight used for ULP mode ADC                                       */
20616       __IOM uint32_t WTULPMSPI0 : 4;            /*!< [7..4] Weight used for ULP mode MSPI0                                     */
20617       __IOM uint32_t WTULPMSPI1 : 4;            /*!< [11..8] Weight used for ULP mode MSPI1                                    */
20618       __IOM uint32_t WTULPGFX   : 4;            /*!< [15..12] Weight used for ULP mode GFX                                     */
20619       __IOM uint32_t WTULPDISP  : 4;            /*!< [19..16] Weight used for ULP mode DISP                                    */
20620       __IOM uint32_t WTULPCRYPTO : 4;           /*!< [23..20] Weight used for ULP mode CRYPTO                                  */
20621       __IOM uint32_t WTULPSDIO  : 4;            /*!< [27..24] Weight used for ULP mode SDIO                                    */
20622       __IOM uint32_t WTULPUSB   : 4;            /*!< [31..28] Weight used for ULP mode USB                                     */
20623     } PWRWEIGHTULP2_b;
20624   } ;
20625 
20626   union {
20627     __IOM uint32_t PWRWEIGHTULP3;               /*!< (@ 0x0000014C) Weights specified in this register are applied
20628                                                                     to each of the masters active requests.
20629                                                                     The aggregate of all the masters is compared
20630                                                                     against the allowed value to change the
20631                                                                     buck from active to inactive mode.                         */
20632 
20633     struct {
20634       __IOM uint32_t WTULPDSPA  : 4;            /*!< [3..0] Weight used for ULP mode DSPA                                      */
20635       __IOM uint32_t WTULPDBG   : 4;            /*!< [7..4] Weight used for ULP mode DBG                                       */
20636       __IOM uint32_t WTULPAUDREC : 4;           /*!< [11..8] Weight used for ULP mode AUDREC                                   */
20637       __IOM uint32_t WTULPAUDPB : 4;            /*!< [15..12] Weight used for ULP mode AUDPB                                   */
20638       __IOM uint32_t WTULPAUDADC : 4;           /*!< [19..16] Weight used for ULP mode AUDADC                                  */
20639             uint32_t            : 8;
20640       __IOM uint32_t WTULPMSPI2 : 4;            /*!< [31..28] Weight used for ULP mode MSPI2                                   */
20641     } PWRWEIGHTULP3_b;
20642   } ;
20643 
20644   union {
20645     __IOM uint32_t PWRWEIGHTULP4;               /*!< (@ 0x00000150) Weights specified in this register are applied
20646                                                                     to each of the masters active requests.
20647                                                                     The aggregate of all the masters is compared
20648                                                                     against the allowed value to change the
20649                                                                     buck from active to inactive mode.                         */
20650 
20651     struct {
20652       __IOM uint32_t WTULPI2S0  : 4;            /*!< [3..0] Weight used for ULP mode I2S0                                      */
20653       __IOM uint32_t WTULPI2S1  : 4;            /*!< [7..4] Weight used for ULP mode I2S1                                      */
20654             uint32_t            : 8;
20655       __IOM uint32_t WTULPPDM0  : 4;            /*!< [19..16] Weight used for ULP mode PDM0                                    */
20656       __IOM uint32_t WTULPPDM1  : 4;            /*!< [23..20] Weight used for ULP mode PDM1                                    */
20657       __IOM uint32_t WTULPPDM2  : 4;            /*!< [27..24] Weight used for ULP mode PDM2                                    */
20658       __IOM uint32_t WTULPPDM3  : 4;            /*!< [31..28] Weight used for ULP mode PDM3                                    */
20659     } PWRWEIGHTULP4_b;
20660   } ;
20661 
20662   union {
20663     __IOM uint32_t PWRWEIGHTULP5;               /*!< (@ 0x00000154) Weights specified in this register are applied
20664                                                                     to each of the masters active requests.
20665                                                                     The aggregate of all the masters is compared
20666                                                                     against the allowed value to change the
20667                                                                     buck from active to inactive mode.                         */
20668 
20669     struct {
20670       __IOM uint32_t WTULPDISPPHY : 4;          /*!< [3..0] Weight used for ULP mode DISP PHY                                  */
20671       __IOM uint32_t WTULPUSBPHY : 4;           /*!< [7..4] Weight used for ULP mode USB PHY                                   */
20672             uint32_t            : 24;
20673     } PWRWEIGHTULP5_b;
20674   } ;
20675 
20676   union {
20677     __IOM uint32_t PWRWEIGHTLP0;                /*!< (@ 0x00000158) Weights specified in this register are applied
20678                                                                     to each of the masters active requests.
20679                                                                     The aggregate of all the masters is compared
20680                                                                     against the allowed value to change the
20681                                                                     buck from active to inactive mode.                         */
20682 
20683     struct {
20684       __IOM uint32_t WTLPMCU    : 4;            /*!< [3..0] Weight used for LP mode MCU                                        */
20685       __IOM uint32_t WTLPDSP0   : 4;            /*!< [7..4] Weight used for LP mode DSP0                                       */
20686       __IOM uint32_t WTLPDSP1   : 4;            /*!< [11..8] Weight used for LP mode DSP1                                      */
20687       __IOM uint32_t WTLPIOS    : 4;            /*!< [15..12] Weight used for LP mode IOS                                      */
20688       __IOM uint32_t WTLPUART0  : 4;            /*!< [19..16] Weight used for LP mode UART0                                    */
20689       __IOM uint32_t WTLPUART1  : 4;            /*!< [23..20] Weight used for LP mode UART1                                    */
20690       __IOM uint32_t WTLPUART2  : 4;            /*!< [27..24] Weight used for LP mode UART2                                    */
20691       __IOM uint32_t WTLPUART3  : 4;            /*!< [31..28] Weight used for LP mode UART3                                    */
20692     } PWRWEIGHTLP0_b;
20693   } ;
20694 
20695   union {
20696     __IOM uint32_t PWRWEIGHTLP1;                /*!< (@ 0x0000015C) Weights specified in this register are applied
20697                                                                     to each of the masters active requests.
20698                                                                     The aggregate of all the masters is compared
20699                                                                     against the allowed value to change the
20700                                                                     buck from active to inactive mode.                         */
20701 
20702     struct {
20703       __IOM uint32_t WTLPIOM0   : 4;            /*!< [3..0] Weight used for LP mode IOM0                                       */
20704       __IOM uint32_t WTLPIOM1   : 4;            /*!< [7..4] Weight used for LP mode IOM1                                       */
20705       __IOM uint32_t WTLPIOM2   : 4;            /*!< [11..8] Weight used for LP mode IOM2                                      */
20706       __IOM uint32_t WTLPIOM3   : 4;            /*!< [15..12] Weight used for LP mode IOM3                                     */
20707       __IOM uint32_t WTLPIOM4   : 4;            /*!< [19..16] Weight used for LP mode IOM4                                     */
20708       __IOM uint32_t WTLPIOM5   : 4;            /*!< [23..20] Weight used for LP mode IOM5                                     */
20709       __IOM uint32_t WTLPIOM6   : 4;            /*!< [27..24] Weight used for LP mode IOM6                                     */
20710       __IOM uint32_t WTLPIOM7   : 4;            /*!< [31..28] Weight used for LP mode IOM7                                     */
20711     } PWRWEIGHTLP1_b;
20712   } ;
20713 
20714   union {
20715     __IOM uint32_t PWRWEIGHTLP2;                /*!< (@ 0x00000160) Weights specified in this register are applied
20716                                                                     to each of the masters active requests.
20717                                                                     The aggregate of all the masters is compared
20718                                                                     against the allowed value to change the
20719                                                                     buck from active to inactive mode.                         */
20720 
20721     struct {
20722       __IOM uint32_t WTLPADC    : 4;            /*!< [3..0] Weight used for LP mode ADC                                        */
20723       __IOM uint32_t WTLPMSPI0  : 4;            /*!< [7..4] Weight used for LP mode MSPI0                                      */
20724       __IOM uint32_t WTLPMSPI1  : 4;            /*!< [11..8] Weight used for LP mode MSPI1                                     */
20725       __IOM uint32_t WTLPGFX    : 4;            /*!< [15..12] Weight used for LP mode GFX                                      */
20726       __IOM uint32_t WTLPDISP   : 4;            /*!< [19..16] Weight used for LP mode DISP                                     */
20727       __IOM uint32_t WTLPCRYPTO : 4;            /*!< [23..20] Weight used for LP mode CRYPTO                                   */
20728       __IOM uint32_t WTLPSDIO   : 4;            /*!< [27..24] Weight used for LP mode SDIO                                     */
20729       __IOM uint32_t WTLPUSB    : 4;            /*!< [31..28] Weight used for LP mode USB                                      */
20730     } PWRWEIGHTLP2_b;
20731   } ;
20732 
20733   union {
20734     __IOM uint32_t PWRWEIGHTLP3;                /*!< (@ 0x00000164) Weights specified in this register are applied
20735                                                                     to each of the masters active requests.
20736                                                                     The aggregate of all the masters is compared
20737                                                                     against the allowed value to change the
20738                                                                     buck from active to inactive mode.                         */
20739 
20740     struct {
20741       __IOM uint32_t WTLPDSPA   : 4;            /*!< [3..0] Weight used for LP mode DSPA                                       */
20742       __IOM uint32_t WTLPDBG    : 4;            /*!< [7..4] Weight used for LP mode DBG                                        */
20743       __IOM uint32_t WTLPAUDREC : 4;            /*!< [11..8] Weight used for LP mode AUDREC                                    */
20744       __IOM uint32_t WTLPAUDPB  : 4;            /*!< [15..12] Weight used for LP mode AUDPB                                    */
20745       __IOM uint32_t WTLPAUDADC : 4;            /*!< [19..16] Weight used for LP mode AUDADC                                   */
20746             uint32_t            : 8;
20747       __IOM uint32_t WTLPMSPI2  : 4;            /*!< [31..28] Weight used for LP mode MSPI2                                    */
20748     } PWRWEIGHTLP3_b;
20749   } ;
20750 
20751   union {
20752     __IOM uint32_t PWRWEIGHTLP4;                /*!< (@ 0x00000168) Weights specified in this register are applied
20753                                                                     to each of the masters active requests.
20754                                                                     The aggregate of all the masters is compared
20755                                                                     against the allowed value to change the
20756                                                                     buck from active to inactive mode.                         */
20757 
20758     struct {
20759       __IOM uint32_t WTLPI2S0   : 4;            /*!< [3..0] Weight used for LP mode I2S0                                       */
20760       __IOM uint32_t WTLPI2S1   : 4;            /*!< [7..4] Weight used for LP mode I2S1                                       */
20761             uint32_t            : 8;
20762       __IOM uint32_t WTLPPDM0   : 4;            /*!< [19..16] Weight used for LP mode PDM0                                     */
20763       __IOM uint32_t WTLPPDM1   : 4;            /*!< [23..20] Weight used for LP mode PDM1                                     */
20764       __IOM uint32_t WTLPPDM2   : 4;            /*!< [27..24] Weight used for LP mode PDM2                                     */
20765       __IOM uint32_t WTLPPDM3   : 4;            /*!< [31..28] Weight used for LP mode PDM3                                     */
20766     } PWRWEIGHTLP4_b;
20767   } ;
20768 
20769   union {
20770     __IOM uint32_t PWRWEIGHTLP5;                /*!< (@ 0x0000016C) Weights specified in this register are applied
20771                                                                     to each of the masters active requests.
20772                                                                     The aggregate of all the masters is compared
20773                                                                     against the allowed value to change the
20774                                                                     buck from active to inactive mode.                         */
20775 
20776     struct {
20777       __IOM uint32_t WTLPDISPPHY : 4;           /*!< [3..0] Weight used for LP mode DISP PHY                                   */
20778       __IOM uint32_t WTLPUSBPHY : 4;            /*!< [7..4] Weight used for LP mode USB PHY                                    */
20779             uint32_t            : 24;
20780     } PWRWEIGHTLP5_b;
20781   } ;
20782 
20783   union {
20784     __IOM uint32_t PWRWEIGHTHP0;                /*!< (@ 0x00000170) Weights specified in this register are applied
20785                                                                     to each of the masters active requests.
20786                                                                     The aggregate of all the masters is compared
20787                                                                     against the allowed value to change the
20788                                                                     buck from active to inactive mode.                         */
20789 
20790     struct {
20791       __IOM uint32_t WTHPMCU    : 4;            /*!< [3..0] Weight used for HP mode MCU                                        */
20792       __IOM uint32_t WTHPDSP0   : 4;            /*!< [7..4] Weight used for HP mode DSP0                                       */
20793       __IOM uint32_t WTHPDSP1   : 4;            /*!< [11..8] Weight used for HP mode DSP1                                      */
20794       __IOM uint32_t WTHPIOS    : 4;            /*!< [15..12] Weight used for HP mode IOS                                      */
20795       __IOM uint32_t WTHPUART0  : 4;            /*!< [19..16] Weight used for HP mode UART0                                    */
20796       __IOM uint32_t WTHPUART1  : 4;            /*!< [23..20] Weight used for HP mode UART1                                    */
20797       __IOM uint32_t WTHPUART2  : 4;            /*!< [27..24] Weight used for HP mode UART2                                    */
20798       __IOM uint32_t WTHPUART3  : 4;            /*!< [31..28] Weight used for HP mode UART3                                    */
20799     } PWRWEIGHTHP0_b;
20800   } ;
20801 
20802   union {
20803     __IOM uint32_t PWRWEIGHTHP1;                /*!< (@ 0x00000174) Weights specified in this register are applied
20804                                                                     to each of the masters active requests.
20805                                                                     The aggregate of all the masters is compared
20806                                                                     against the allowed value to change the
20807                                                                     buck from active to inactive mode.                         */
20808 
20809     struct {
20810       __IOM uint32_t WTHPIOM0   : 4;            /*!< [3..0] Weight used for HP mode IOM0                                       */
20811       __IOM uint32_t WTHPIOM1   : 4;            /*!< [7..4] Weight used for HP mode IOM1                                       */
20812       __IOM uint32_t WTHPIOM2   : 4;            /*!< [11..8] Weight used for HP mode IOM2                                      */
20813       __IOM uint32_t WTHPIOM3   : 4;            /*!< [15..12] Weight used for HP mode IOM3                                     */
20814       __IOM uint32_t WTHPIOM4   : 4;            /*!< [19..16] Weight used for HP mode IOM4                                     */
20815       __IOM uint32_t WTHPIOM5   : 4;            /*!< [23..20] Weight used for HP mode IOM5                                     */
20816       __IOM uint32_t WTHPIOM6   : 4;            /*!< [27..24] Weight used for HP mode IOM6                                     */
20817       __IOM uint32_t WTHPIOM7   : 4;            /*!< [31..28] Weight used for HP mode IOM7                                     */
20818     } PWRWEIGHTHP1_b;
20819   } ;
20820 
20821   union {
20822     __IOM uint32_t PWRWEIGHTHP2;                /*!< (@ 0x00000178) Weights specified in this register are applied
20823                                                                     to each of the masters active requests.
20824                                                                     The aggregate of all the masters is compared
20825                                                                     against the allowed value to change the
20826                                                                     buck from active to inactive mode.                         */
20827 
20828     struct {
20829       __IOM uint32_t WTHPADC    : 4;            /*!< [3..0] Weight used for HP mode ADC                                        */
20830       __IOM uint32_t WTHPMSPI0  : 4;            /*!< [7..4] Weight used for HP mode MSPI0                                      */
20831       __IOM uint32_t WTHPMSPI1  : 4;            /*!< [11..8] Weight used for HP mode MSPI1                                     */
20832       __IOM uint32_t WTHPGFX    : 4;            /*!< [15..12] Weight used for HP mode GFX                                      */
20833       __IOM uint32_t WTHPDISP   : 4;            /*!< [19..16] Weight used for HP mode DISP                                     */
20834       __IOM uint32_t WTHPCRYPTO : 4;            /*!< [23..20] Weight used for HP mode CRYPTO                                   */
20835       __IOM uint32_t WTHPSDIO   : 4;            /*!< [27..24] Weight used for HP mode SDIO                                     */
20836       __IOM uint32_t WTHPUSB    : 4;            /*!< [31..28] Weight used for HP mode USB                                      */
20837     } PWRWEIGHTHP2_b;
20838   } ;
20839 
20840   union {
20841     __IOM uint32_t PWRWEIGHTHP3;                /*!< (@ 0x0000017C) Weights specified in this register are applied
20842                                                                     to each of the masters active requests.
20843                                                                     The aggregate of all the masters is compared
20844                                                                     against the allowed value to change the
20845                                                                     buck from active to inactive mode.                         */
20846 
20847     struct {
20848       __IOM uint32_t WTHPDSPA   : 4;            /*!< [3..0] Weight used for HP mode DSPA                                       */
20849       __IOM uint32_t WTHPDBG    : 4;            /*!< [7..4] Weight used for HP mode DBG                                        */
20850       __IOM uint32_t WTHPAUDREC : 4;            /*!< [11..8] Weight used for HP mode AUDREC                                    */
20851       __IOM uint32_t WTHPAUDPB  : 4;            /*!< [15..12] Weight used for HP mode AUDPB                                    */
20852       __IOM uint32_t WTHPAUDADC : 4;            /*!< [19..16] Weight used for HP mode AUDADC                                   */
20853             uint32_t            : 8;
20854       __IOM uint32_t WTHPMSPI2  : 4;            /*!< [31..28] Weight used for HP mode MSPI2                                    */
20855     } PWRWEIGHTHP3_b;
20856   } ;
20857 
20858   union {
20859     __IOM uint32_t PWRWEIGHTHP4;                /*!< (@ 0x00000180) Weights specified in this register are applied
20860                                                                     to each of the masters active requests.
20861                                                                     The aggregate of all the masters is compared
20862                                                                     against the allowed value to change the
20863                                                                     buck from active to inactive mode.                         */
20864 
20865     struct {
20866       __IOM uint32_t WTHPI2S0   : 4;            /*!< [3..0] Weight used for HP mode I2S0                                       */
20867       __IOM uint32_t WTHPI2S1   : 4;            /*!< [7..4] Weight used for HP mode I2S1                                       */
20868             uint32_t            : 8;
20869       __IOM uint32_t WTHPPDM0   : 4;            /*!< [19..16] Weight used for HP mode PDM0                                     */
20870       __IOM uint32_t WTHPPDM1   : 4;            /*!< [23..20] Weight used for HP mode PDM1                                     */
20871       __IOM uint32_t WTHPPDM2   : 4;            /*!< [27..24] Weight used for HP mode PDM2                                     */
20872       __IOM uint32_t WTHPPDM3   : 4;            /*!< [31..28] Weight used for HP mode PDM3                                     */
20873     } PWRWEIGHTHP4_b;
20874   } ;
20875 
20876   union {
20877     __IOM uint32_t PWRWEIGHTHP5;                /*!< (@ 0x00000184) Weights specified in this register are applied
20878                                                                     to each of the masters active requests.
20879                                                                     The aggregate of all the masters is compared
20880                                                                     against the allowed value to change the
20881                                                                     buck from active to inactive mode.                         */
20882 
20883     struct {
20884       __IOM uint32_t WTHPDISPPHY : 4;           /*!< [3..0] Weight used for HP mode DISP PHY                                   */
20885       __IOM uint32_t WTHPUSBPHY : 4;            /*!< [7..4] Weight used for HP mode USB PHY                                    */
20886             uint32_t            : 24;
20887     } PWRWEIGHTHP5_b;
20888   } ;
20889 
20890   union {
20891     __IOM uint32_t PWRWEIGHTSLP;                /*!< (@ 0x00000188) Weights specified in this register are applied
20892                                                                     to each of the masters active requests.
20893                                                                     The aggregate of all the masters is compared
20894                                                                     against the allowed value to change the
20895                                                                     buck from active to inactive mode.                         */
20896 
20897     struct {
20898       __IOM uint32_t WTDSMCU    : 4;            /*!< [3..0] Weight used for Deep Sleep mode MCU                                */
20899             uint32_t            : 28;
20900     } PWRWEIGHTSLP_b;
20901   } ;
20902 
20903   union {
20904     __IOM uint32_t VRDEMOTIONTHR;               /*!< (@ 0x0000018C) Weights specified in PWRWEIGHT* registers are
20905                                                                     applied to each of the masters active requests.
20906                                                                     The aggregate of all the masters is compared
20907                                                                     against the this threshold value to change
20908                                                                     the buck from active to inactive mode.                     */
20909 
20910     struct {
20911       __IOM uint32_t VRDEMOTIONTHR : 32;        /*!< [31..0] VR Demotion Threshold                                             */
20912     } VRDEMOTIONTHR_b;
20913   } ;
20914 
20915   union {
20916     __IOM uint32_t SRAMCTRL;                    /*!< (@ 0x00000190) This register provides additional fine-tune power
20917                                                                     management controls for the SRAMs and the
20918                                                                     SRAM controller. This includes enabling
20919                                                                     light sleep for the SRAM and TCM banks,
20920                                                                     and clock gating for reduced dynamic power.                */
20921 
20922     struct {
20923             uint32_t            : 1;
20924       __IOM uint32_t SRAMCLKGATE : 1;           /*!< [1..1] This bit is 1 if clock gating is allowed for individual
20925                                                      system SRAMs                                                              */
20926       __IOM uint32_t SRAMMASTERCLKGATE : 1;     /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level
20927                                                      clock gate for entire SRAM block)                                         */
20928             uint32_t            : 5;
20929       __IOM uint32_t SRAMLIGHTSLEEP : 12;       /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding
20930                                                      bank will be put into light sleep. For optimal power, banks
20931                                                      should be put into light sleep while the system is active
20932                                                      but the bank has minimal or no accesses.                                  */
20933             uint32_t            : 12;
20934     } SRAMCTRL_b;
20935   } ;
20936 
20937   union {
20938     __IOM uint32_t ADCSTATUS;                   /*!< (@ 0x00000194) This provides the power status for various blocks
20939                                                                     within the ADC. These status comes directly
20940                                                                     from the ADC module and is captured through
20941                                                                     this interface.                                            */
20942 
20943     struct {
20944       __IOM uint32_t ADCPWD     : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
20945       __IOM uint32_t BGTPWD     : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
20946       __IOM uint32_t VPTATPWD   : 1;            /*!< [2..2] This bit indicates that the ADC temperature sensor input
20947                                                      buffer is powered down                                                    */
20948       __IOM uint32_t VBATPWD    : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
20949                                                      is powered down                                                           */
20950       __IOM uint32_t REFKEEPPWD : 1;            /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
20951       __IOM uint32_t REFBUFPWD  : 1;            /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
20952             uint32_t            : 26;
20953     } ADCSTATUS_b;
20954   } ;
20955 
20956   union {
20957     __IOM uint32_t AUDADCSTATUS;                /*!< (@ 0x00000198) This provides the power status for various blocks
20958                                                                     within the audio ADC. These status comes
20959                                                                     directly from the audio ADC module and is
20960                                                                     captured through this interface.                           */
20961 
20962     struct {
20963       __IOM uint32_t AUDADCPWD  : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
20964       __IOM uint32_t AUDBGTPWD  : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
20965       __IOM uint32_t AUDVPTATPWD : 1;           /*!< [2..2] This bit indicates that the ADC temperature sensor input
20966                                                      buffer is powered down                                                    */
20967       __IOM uint32_t AUDVBATPWD : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
20968                                                      is powered down                                                           */
20969       __IOM uint32_t AUDREFKEEPPWD : 1;         /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
20970       __IOM uint32_t AUDREFBUFPWD : 1;          /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
20971             uint32_t            : 26;
20972     } AUDADCSTATUS_b;
20973   } ;
20974   __IM  uint32_t  RESERVED5[25];
20975 
20976   union {
20977     __IOM uint32_t EMONCTRL;                    /*!< (@ 0x00000200) Controls each of the energy monitor conuters               */
20978 
20979     struct {
20980       __IOM uint32_t FREEZE     : 8;            /*!< [7..0] Freeze the counter. Each bit corresponds to a counter.
20981                                                      0: Let the counter run. 1: Stop the counter.                              */
20982       __IOM uint32_t CLEAR      : 8;            /*!< [15..8] Clear the counter. Each bit corresponds to a counter.
20983                                                      0: Let the counter run run on its input clk. 1: Clear the
20984                                                      counter                                                                   */
20985             uint32_t            : 16;
20986     } EMONCTRL_b;
20987   } ;
20988 
20989   union {
20990     __IOM uint32_t EMONCFG0;                    /*!< (@ 0x00000204) The counter increments when the counter is enabled
20991                                                                     and the mode selected here matches the power
20992                                                                     mode.                                                      */
20993 
20994     struct {
20995       __IOM uint32_t EMONSEL0   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
20996             uint32_t            : 24;
20997     } EMONCFG0_b;
20998   } ;
20999 
21000   union {
21001     __IOM uint32_t EMONCFG1;                    /*!< (@ 0x00000208) The counter increments when the counter is enabled
21002                                                                     and the mode selected here matches the power
21003                                                                     mode.                                                      */
21004 
21005     struct {
21006       __IOM uint32_t EMONSEL1   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21007             uint32_t            : 24;
21008     } EMONCFG1_b;
21009   } ;
21010 
21011   union {
21012     __IOM uint32_t EMONCFG2;                    /*!< (@ 0x0000020C) The counter increments when the counter is enabled
21013                                                                     and the mode selected here matches the power
21014                                                                     mode.                                                      */
21015 
21016     struct {
21017       __IOM uint32_t EMONSEL2   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21018             uint32_t            : 24;
21019     } EMONCFG2_b;
21020   } ;
21021 
21022   union {
21023     __IOM uint32_t EMONCFG3;                    /*!< (@ 0x00000210) The counter increments when the counter is enabled
21024                                                                     and the mode selected here matches the power
21025                                                                     mode.                                                      */
21026 
21027     struct {
21028       __IOM uint32_t EMONSEL3   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21029             uint32_t            : 24;
21030     } EMONCFG3_b;
21031   } ;
21032 
21033   union {
21034     __IOM uint32_t EMONCFG4;                    /*!< (@ 0x00000214) The counter increments when the counter is enabled
21035                                                                     and the mode selected here matches the power
21036                                                                     mode.                                                      */
21037 
21038     struct {
21039       __IOM uint32_t EMONSEL4   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21040             uint32_t            : 24;
21041     } EMONCFG4_b;
21042   } ;
21043 
21044   union {
21045     __IOM uint32_t EMONCFG5;                    /*!< (@ 0x00000218) The counter increments when the counter is enabled
21046                                                                     and the mode selected here matches the power
21047                                                                     mode.                                                      */
21048 
21049     struct {
21050       __IOM uint32_t EMONSEL5   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21051             uint32_t            : 24;
21052     } EMONCFG5_b;
21053   } ;
21054 
21055   union {
21056     __IOM uint32_t EMONCFG6;                    /*!< (@ 0x0000021C) The counter increments when the counter is enabled
21057                                                                     and the mode selected here matches the power
21058                                                                     mode.                                                      */
21059 
21060     struct {
21061       __IOM uint32_t EMONSEL6   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21062             uint32_t            : 24;
21063     } EMONCFG6_b;
21064   } ;
21065 
21066   union {
21067     __IOM uint32_t EMONCFG7;                    /*!< (@ 0x00000220) The counter increments when the counter is enabled
21068                                                                     and the mode selected here matches the power
21069                                                                     mode.                                                      */
21070 
21071     struct {
21072       __IOM uint32_t EMONSEL7   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21073             uint32_t            : 24;
21074     } EMONCFG7_b;
21075   } ;
21076   __IM  uint32_t  RESERVED6;
21077 
21078   union {
21079     __IOM uint32_t EMONCOUNT0;                  /*!< (@ 0x00000228) Energy Monitor count value for counter 0                   */
21080 
21081     struct {
21082       __IOM uint32_t EMONCOUNT0 : 32;           /*!< [31..0] Energy Monitor count value counter 0                              */
21083     } EMONCOUNT0_b;
21084   } ;
21085 
21086   union {
21087     __IOM uint32_t EMONCOUNT1;                  /*!< (@ 0x0000022C) Energy Monitor count value for counter 1                   */
21088 
21089     struct {
21090       __IOM uint32_t EMONCOUNT1 : 32;           /*!< [31..0] Energy Monitor count value counter 1                              */
21091     } EMONCOUNT1_b;
21092   } ;
21093 
21094   union {
21095     __IOM uint32_t EMONCOUNT2;                  /*!< (@ 0x00000230) Energy Monitor count value for counter 2                   */
21096 
21097     struct {
21098       __IOM uint32_t EMONCOUNT2 : 32;           /*!< [31..0] Energy Monitor count value counter 2                              */
21099     } EMONCOUNT2_b;
21100   } ;
21101 
21102   union {
21103     __IOM uint32_t EMONCOUNT3;                  /*!< (@ 0x00000234) Energy Monitor count value for counter 3                   */
21104 
21105     struct {
21106       __IOM uint32_t EMONCOUNT3 : 32;           /*!< [31..0] Energy Monitor count value counter 3                              */
21107     } EMONCOUNT3_b;
21108   } ;
21109 
21110   union {
21111     __IOM uint32_t EMONCOUNT4;                  /*!< (@ 0x00000238) Energy Monitor count value for counter 4                   */
21112 
21113     struct {
21114       __IOM uint32_t EMONCOUNT4 : 32;           /*!< [31..0] Energy Monitor count value counter 4                              */
21115     } EMONCOUNT4_b;
21116   } ;
21117 
21118   union {
21119     __IOM uint32_t EMONCOUNT5;                  /*!< (@ 0x0000023C) Energy Monitor count value for counter 5                   */
21120 
21121     struct {
21122       __IOM uint32_t EMONCOUNT5 : 32;           /*!< [31..0] Energy Monitor count value counter 5                              */
21123     } EMONCOUNT5_b;
21124   } ;
21125 
21126   union {
21127     __IOM uint32_t EMONCOUNT6;                  /*!< (@ 0x00000240) Energy Monitor count value for counter 6                   */
21128 
21129     struct {
21130       __IOM uint32_t EMONCOUNT6 : 32;           /*!< [31..0] Energy Monitor count value counter 6                              */
21131     } EMONCOUNT6_b;
21132   } ;
21133 
21134   union {
21135     __IOM uint32_t EMONCOUNT7;                  /*!< (@ 0x00000244) Energy Monitor count value for counter 7                   */
21136 
21137     struct {
21138       __IOM uint32_t EMONCOUNT7 : 32;           /*!< [31..0] Energy Monitor count value counter 7                              */
21139     } EMONCOUNT7_b;
21140   } ;
21141   __IM  uint32_t  RESERVED7;
21142 
21143   union {
21144     __IOM uint32_t EMONSTATUS;                  /*!< (@ 0x0000024C) Energy Monitor status                                      */
21145 
21146     struct {
21147       __IOM uint32_t EMONOVERFLOW0 : 1;         /*!< [0..0] Energy Monitor counter0 overflow                                   */
21148       __IOM uint32_t EMONOVERFLOW1 : 1;         /*!< [1..1] Energy Monitor counter1 overflow                                   */
21149       __IOM uint32_t EMONOVERFLOW2 : 1;         /*!< [2..2] Energy Monitor counter2 overflow                                   */
21150       __IOM uint32_t EMONOVERFLOW3 : 1;         /*!< [3..3] Energy Monitor counter3 overflow                                   */
21151       __IOM uint32_t EMONOVERFLOW4 : 1;         /*!< [4..4] Energy Monitor counter4 overflow                                   */
21152       __IOM uint32_t EMONOVERFLOW5 : 1;         /*!< [5..5] Energy Monitor counter5 overflow                                   */
21153       __IOM uint32_t EMONOVERFLOW6 : 1;         /*!< [6..6] Energy Monitor counter6 overflow                                   */
21154       __IOM uint32_t EMONOVERFLOW7 : 1;         /*!< [7..7] Energy Monitor counter7 overflow                                   */
21155             uint32_t            : 24;
21156     } EMONSTATUS_b;
21157   } ;
21158 } PWRCTRL_Type;                                 /*!< Size = 592 (0x250)                                                        */
21159 
21160 
21161 
21162 /* =========================================================================================================================== */
21163 /* ================                                          RSTGEN                                           ================ */
21164 /* =========================================================================================================================== */
21165 
21166 
21167 /**
21168   * @brief MCU Reset Generator (RSTGEN)
21169   */
21170 
21171 typedef struct {                                /*!< (@ 0x40000000) RSTGEN Structure                                           */
21172 
21173   union {
21174     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) Reset configuration register. This controls the
21175                                                                     reset enables for brownout condition, choice
21176                                                                     of brownout method and for the expiration
21177                                                                     of the watch dog timer.                                    */
21178 
21179     struct {
21180       __IOM uint32_t BODHREN    : 1;            /*!< [0..0] Brown out high (2.1v) reset enable. Note - Enabling this
21181                                                      bit for Apollo4, which operates at 1.8v/1.9v, will cause
21182                                                      a continual reset loop.                                                   */
21183       __IOM uint32_t WDREN      : 1;            /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must
21184                                                      also be configured for WDT reset. This includes enabling
21185                                                      the RESEN bit in WDTCFG register in Watch dog timer block.                */
21186             uint32_t            : 30;
21187     } CFG_b;
21188   } ;
21189 
21190   union {
21191     __IOM uint32_t SWPOI;                       /*!< (@ 0x00000004) This is the software POI reset. writing the key
21192                                                                     value to this register will trigger a POI
21193                                                                     to the system. This will cause a reset to
21194                                                                     all blocks except for registers in clock
21195                                                                     gen, RTC and the stimer.                                   */
21196 
21197     struct {
21198       __IOM uint32_t SWPOIKEY   : 8;            /*!< [7..0] 0x1B generates a software POI reset. This is a write-only
21199                                                      register. Reading from this register will yield only all
21200                                                      0s.                                                                       */
21201             uint32_t            : 24;
21202     } SWPOI_b;
21203   } ;
21204 
21205   union {
21206     __IOM uint32_t SWPOR;                       /*!< (@ 0x00000008) This is the software POR reset. Writing the key
21207                                                                     value to this register will trigger a POR
21208                                                                     to the system. This will cause a reset to
21209                                                                     all blocks except for registers in clock
21210                                                                     gen, RTC, power management unit, the stimer,
21211                                                                     and the power management unit.                             */
21212 
21213     struct {
21214       __IOM uint32_t SWPORKEY   : 8;            /*!< [7..0] 0xD4 generates a software POR reset.                               */
21215             uint32_t            : 24;
21216     } SWPOR_b;
21217   } ;
21218   __IM  uint32_t  RESERVED[2];
21219 
21220   union {
21221     __IOM uint32_t SIMOBODM;                    /*!< (@ 0x00000014) This register unmasks the individual digital
21222                                                                     detection brownout bits into the interrupt
21223                                                                     block                                                      */
21224 
21225     struct {
21226       __IOM uint32_t DIGBOEC    : 1;            /*!< [0..0] Enable the gate into the interrupt block for the digital
21227                                                      brownout detection on VDDC. Note: The interrupt block must
21228                                                      also be unmasked for ISR and interrupt status to be set                   */
21229       __IOM uint32_t DIGBOEF    : 1;            /*!< [1..1] Enable the gate into the interrupt block for the digital
21230                                                      brownout detection on VDDF. Note: The interrupt block must
21231                                                      also be unmasked for ISR and interrupt status to be set                   */
21232       __IOM uint32_t DIGBOES    : 1;            /*!< [2..2] Enable the gate into the interrupt block for the digital
21233                                                      brownout detection on VDDS. Note: The interrupt block must
21234                                                      also be unmasked for ISR and interrupt status to be set                   */
21235       __IOM uint32_t DIGBOECLV  : 1;            /*!< [3..3] Enable the gate into the interrupt block for the digital
21236                                                      brownout detection on VDDC_LV. Note: The interrupt block
21237                                                      must also be unmasked for ISR and interrupt status to be
21238                                                      set                                                                       */
21239             uint32_t            : 28;
21240     } SIMOBODM_b;
21241   } ;
21242   __IM  uint32_t  RESERVED1[122];
21243 
21244   union {
21245     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
21246                                                                     to generate the corresponding interrupt.                   */
21247 
21248     struct {
21249       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21250                                                      BODH level.                                                               */
21251       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21252                                                      detects inactivity on VDDC                                                */
21253       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21254                                                      detects inactivity on VDDF                                                */
21255       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21256                                                      detects inactivity on VDDS                                                */
21257       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21258                                                      detects inactivity on VDDC_LV                                             */
21259             uint32_t            : 27;
21260     } INTEN_b;
21261   } ;
21262 
21263   union {
21264     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
21265                                                                     cause of a recent interrupt.                               */
21266 
21267     struct {
21268       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21269                                                      BODH level.                                                               */
21270       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21271                                                      detects inactivity on VDDC                                                */
21272       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21273                                                      detects inactivity on VDDF                                                */
21274       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21275                                                      detects inactivity on VDDS                                                */
21276       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21277                                                      detects inactivity on VDDC_LV                                             */
21278             uint32_t            : 27;
21279     } INTSTAT_b;
21280   } ;
21281 
21282   union {
21283     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
21284                                                                     the interrupt status associated with that
21285                                                                     bit.                                                       */
21286 
21287     struct {
21288       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21289                                                      BODH level.                                                               */
21290       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21291                                                      detects inactivity on VDDC                                                */
21292       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21293                                                      detects inactivity on VDDF                                                */
21294       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21295                                                      detects inactivity on VDDS                                                */
21296       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21297                                                      detects inactivity on VDDC_LV                                             */
21298             uint32_t            : 27;
21299     } INTCLR_b;
21300   } ;
21301 
21302   union {
21303     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
21304                                                                     generate an interrupt from this module.
21305                                                                     (Generally used for testing purposes).                     */
21306 
21307     struct {
21308       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21309                                                      BODH level.                                                               */
21310       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21311                                                      detects inactivity on VDDC                                                */
21312       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21313                                                      detects inactivity on VDDF                                                */
21314       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21315                                                      detects inactivity on VDDS                                                */
21316       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21317                                                      detects inactivity on VDDC_LV                                             */
21318             uint32_t            : 27;
21319     } INTSET_b;
21320   } ;
21321   __IM  uint32_t  RESERVED2[8595];
21322 
21323   union {
21324     __IOM uint32_t STAT;                        /*!< (@ 0x0000885C) This register contains the status for brownout
21325                                                                     events and the causes for resets.
21326                                                                     NOTE 1: All bits in this register, including
21327                                                                     reserved bits, are writable. Therefore care
21328                                                                     should be taken not to write this register.
21329                                                                     NOTE 2: This register is only reset by POI
21330                                                                     not by HRESETn. Its contents are intended
21331                                                                     to survive all reset level except POI and
21332                                                                     full power cycles.                                         */
21333 
21334     struct {
21335       __IOM uint32_t EXRSTAT    : 1;            /*!< [0..0] Reset was initiated by an External Reset.                          */
21336       __IOM uint32_t PORSTAT    : 1;            /*!< [1..1] Reset was initiated by a Power-On Reset.                           */
21337       __IOM uint32_t BORSTAT    : 1;            /*!< [2..2] Reset was initiated by a Brown-Out Reset.                          */
21338       __IOM uint32_t SWRSTAT    : 1;            /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset.                    */
21339       __IOM uint32_t POIRSTAT   : 1;            /*!< [4..4] Reset was a initiated by Software POI Reset.                       */
21340       __IOM uint32_t DBGRSTAT   : 1;            /*!< [5..5] Reset was a initiated by Debugger Reset.                           */
21341       __IOM uint32_t WDRSTAT    : 1;            /*!< [6..6] Reset was initiated by a Watchdog Timer Reset.                     */
21342       __IOM uint32_t BOUSTAT    : 1;            /*!< [7..7] An Unregulated Supply Brownout Event occured.                      */
21343       __IOM uint32_t BOCSTAT    : 1;            /*!< [8..8] VDDC Analog Brownout Event occured.                                */
21344       __IOM uint32_t BOFSTAT    : 1;            /*!< [9..9] VDDF Analog Brownout Event occured.                                */
21345       __IOM uint32_t BOSSTAT    : 1;            /*!< [10..10] VDDS Analog Brownout Event occured.                              */
21346             uint32_t            : 21;
21347     } STAT_b;
21348   } ;
21349 } RSTGEN_Type;                                  /*!< Size = 34912 (0x8860)                                                     */
21350 
21351 
21352 
21353 /* =========================================================================================================================== */
21354 /* ================                                            RTC                                            ================ */
21355 /* =========================================================================================================================== */
21356 
21357 
21358 /**
21359   * @brief Real Time Clock (RTC)
21360   */
21361 
21362 typedef struct {                                /*!< (@ 0x40004800) RTC Structure                                              */
21363 
21364   union {
21365     __IOM uint32_t RTCCTL;                      /*!< (@ 0x00000000) This is the register control for the RTC module.
21366                                                                     It enables counter writes and sets the alarm
21367                                                                     repeat interval.                                           */
21368 
21369     struct {
21370       __IOM uint32_t WRTC       : 1;            /*!< [0..0] Counter write control                                              */
21371       __IOM uint32_t RPT        : 3;            /*!< [3..1] Alarm repeat interval                                              */
21372       __IOM uint32_t RSTOP      : 1;            /*!< [4..4] RTC input clock control                                            */
21373             uint32_t            : 27;
21374     } RTCCTL_b;
21375   } ;
21376 
21377   union {
21378     __IOM uint32_t RTCSTAT;                     /*!< (@ 0x00000004) This is the register status for the RTC module.            */
21379 
21380     struct {
21381       __IOM uint32_t WRITEBUSY  : 1;            /*!< [0..0] Indicates that an RTC update (write) is still in progress.
21382                                                      Writes are initiated by writing the CTTLOW register - CTRUP
21383                                                      must be written before CTRLOW to be updated (otherwise
21384                                                      it will retain its current value)                                         */
21385             uint32_t            : 31;
21386     } RTCSTAT_b;
21387   } ;
21388   __IM  uint32_t  RESERVED[6];
21389 
21390   union {
21391     __IOM uint32_t CTRLOW;                      /*!< (@ 0x00000020) This counter contains the values for hour, minutes,
21392                                                                     seconds and 100ths of a second Counter.                    */
21393 
21394     struct {
21395       __IOM uint32_t CTR100     : 8;            /*!< [7..0] 100ths of a second Counter                                         */
21396       __IOM uint32_t CTRSEC     : 7;            /*!< [14..8] Seconds Counter                                                   */
21397             uint32_t            : 1;
21398       __IOM uint32_t CTRMIN     : 7;            /*!< [22..16] Minutes Counter                                                  */
21399             uint32_t            : 1;
21400       __IOM uint32_t CTRHR      : 6;            /*!< [29..24] Hours Counter                                                    */
21401             uint32_t            : 2;
21402     } CTRLOW_b;
21403   } ;
21404 
21405   union {
21406     __IOM uint32_t CTRUP;                       /*!< (@ 0x00000024) This register contains the day, month and year
21407                                                                     information. It contains which day in the
21408                                                                     week, and the century as well. The information
21409                                                                     of the century can also be derived from
21410                                                                     the year information. The 31st bit contains
21411                                                                     the error bit. See description in the register
21412                                                                     bit for condition when error is triggered.                 */
21413 
21414     struct {
21415       __IOM uint32_t CTRDATE    : 6;            /*!< [5..0] Date Counter                                                       */
21416             uint32_t            : 2;
21417       __IOM uint32_t CTRMO      : 5;            /*!< [12..8] Months Counter                                                    */
21418             uint32_t            : 3;
21419       __IOM uint32_t CTRYR      : 8;            /*!< [23..16] Years Counter                                                    */
21420       __IOM uint32_t CTRWKDY    : 3;            /*!< [26..24] Weekdays Counter                                                 */
21421             uint32_t            : 1;
21422       __IOM uint32_t CB         : 1;            /*!< [28..28] Century                                                          */
21423       __IOM uint32_t CEB        : 1;            /*!< [29..29] Century enable                                                   */
21424             uint32_t            : 1;
21425       __IOM uint32_t CTERR      : 1;            /*!< [31..31] Counter read error status. Error is triggered when
21426                                                      software reads the lower word of the counters, and fails
21427                                                      to read the upper counter within 1/100 second. This is
21428                                                      because when the lower counter is read, the upper counter
21429                                                      is held off from incrementing until it is read so that
21430                                                      the full time stamp can be read.                                          */
21431     } CTRUP_b;
21432   } ;
21433   __IM  uint32_t  RESERVED1[2];
21434 
21435   union {
21436     __IOM uint32_t ALMLOW;                      /*!< (@ 0x00000030) This register is the Alarm settings for hours,
21437                                                                     minutes, second and 1/100th seconds settings.              */
21438 
21439     struct {
21440       __IOM uint32_t ALM100     : 8;            /*!< [7..0] 100ths of a second Alarm                                           */
21441       __IOM uint32_t ALMSEC     : 7;            /*!< [14..8] Seconds Alarm                                                     */
21442             uint32_t            : 1;
21443       __IOM uint32_t ALMMIN     : 7;            /*!< [22..16] Minutes Alarm                                                    */
21444             uint32_t            : 1;
21445       __IOM uint32_t ALMHR      : 6;            /*!< [29..24] Hours Alarm                                                      */
21446             uint32_t            : 2;
21447     } ALMLOW_b;
21448   } ;
21449 
21450   union {
21451     __IOM uint32_t ALMUP;                       /*!< (@ 0x00000034) This register is the alarm settings for week,
21452                                                                     month and day.                                             */
21453 
21454     struct {
21455       __IOM uint32_t ALMDATE    : 6;            /*!< [5..0] Date Alarm                                                         */
21456             uint32_t            : 2;
21457       __IOM uint32_t ALMMO      : 5;            /*!< [12..8] Months Alarm                                                      */
21458             uint32_t            : 3;
21459       __IOM uint32_t ALMWKDY    : 3;            /*!< [18..16] Weekdays Alarm                                                   */
21460             uint32_t            : 13;
21461     } ALMUP_b;
21462   } ;
21463   __IM  uint32_t  RESERVED2[114];
21464 
21465   union {
21466     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
21467                                                                     to generate the corresponding interrupt.                   */
21468 
21469     struct {
21470       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21471             uint32_t            : 31;
21472     } INTEN_b;
21473   } ;
21474 
21475   union {
21476     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
21477                                                                     cause of a recent interrupt.                               */
21478 
21479     struct {
21480       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21481             uint32_t            : 31;
21482     } INTSTAT_b;
21483   } ;
21484 
21485   union {
21486     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
21487                                                                     the interrupt status associated with that
21488                                                                     bit.                                                       */
21489 
21490     struct {
21491       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21492             uint32_t            : 31;
21493     } INTCLR_b;
21494   } ;
21495 
21496   union {
21497     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
21498                                                                     generate an interrupt from this module.
21499                                                                     (Generally used for testing purposes).                     */
21500 
21501     struct {
21502       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21503             uint32_t            : 31;
21504     } INTSET_b;
21505   } ;
21506 } RTC_Type;                                     /*!< Size = 528 (0x210)                                                        */
21507 
21508 
21509 
21510 /* =========================================================================================================================== */
21511 /* ================                                           SDIO                                            ================ */
21512 /* =========================================================================================================================== */
21513 
21514 
21515 /**
21516   * @brief SDIO Control Registers (SDIO)
21517   */
21518 
21519 typedef struct {                                /*!< (@ 0x40070000) SDIO Structure                                             */
21520 
21521   union {
21522     __IOM uint32_t SDMA;                        /*!< (@ 0x00000000) SDMA system address                                        */
21523 
21524     struct {
21525       __IOM uint32_t SDMASYSTEMADDRESS : 32;    /*!< [31..0] This register contains the physical system memory address
21526                                                      used for DMA transfers or the second argument for the Auto
21527                                                      CMD23. (1) SDMA System Address This register contains the
21528                                                      system memory address for a SDMA transfer. When the Host
21529                                                      Controller stops a SDMA transfer, this register shall point
21530                                                      to the system address of the next contiguous data position.
21531                                                      It can be accessed only if no transaction is executing
21532                                                      (i.e., after a transaction has stopped). Read operations
21533                                                      during transfers may return an invalid value. T                           */
21534     } SDMA_b;
21535   } ;
21536 
21537   union {
21538     __IOM uint32_t BLOCK;                       /*!< (@ 0x00000004) Block size                                                 */
21539 
21540     struct {
21541       __IOM uint32_t TRANSFERBLOCKSIZE : 12;    /*!< [11..0] This register specifies the block size for block data
21542                                                      transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It
21543                                                      can be accessed only if no transaction is executing (i.e
21544                                                      after a transaction has stopped). Read operations during
21545                                                      transfer return an invalid value and write operations shall
21546                                                      be ignored.                                                               */
21547       __IOM uint32_t HOSTSDMABUFSZ : 3;         /*!< [14..12] To perform long DMA transfer, System Address register
21548                                                      shall be updated at every system boundary during DMA transfer.
21549                                                      These bits specify the size of contiguous buffer in the
21550                                                      system memory. The DMA transfer shall wait at the every
21551                                                      boundary specified by these fields and the HC generates
21552                                                      the DMA Interrupt to request the HD to update the System
21553                                                      Address register. These bits shall support when the DMA
21554                                                      Support in the Capabilities register is set to 1 and this
21555                                                      function is active when the DMA Enable in the Transfer
21556                                                                                                                                */
21557             uint32_t            : 1;
21558       __IOM uint32_t BLKCNT     : 16;           /*!< [31..16] This register is enabled when Block Count Enable in
21559                                                      the Transfer Mode register is set to 1 and is valid only
21560                                                      for multiple block transfers. The HC decrements the block
21561                                                      count after each block transfer and stops when the count
21562                                                      reaches zero. It can be accessed only if no transaction
21563                                                      is executing (i.e. after a transaction has stopped). Read
21564                                                      operations during transfer return an invalid value and
21565                                                      write operations shall be ignored. When saving transfer
21566                                                      context as a result of Suspend command, the number of blocks
21567                                                      y                                                                         */
21568     } BLOCK_b;
21569   } ;
21570 
21571   union {
21572     __IOM uint32_t ARGUMENT1;                   /*!< (@ 0x00000008) Argument1                                                  */
21573 
21574     struct {
21575       __IOM uint32_t CMDARG1    : 32;           /*!< [31..0] The SD Command Argument is specified as bit39-8 of Command-Format. */
21576     } ARGUMENT1_b;
21577   } ;
21578 
21579   union {
21580     __IOM uint32_t TRANSFER;                    /*!< (@ 0x0000000C) Transfer mode                                              */
21581 
21582     struct {
21583       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA can be enabled only if DMA Support bit in the Capabilities
21584                                                      register is set. If this bit is set to 1, a DMA operation
21585                                                      shall begin when the HD writes to the upper byte of Command
21586                                                      register (00Fh).                                                          */
21587       __IOM uint32_t BLKCNTEN   : 1;            /*!< [1..1] This bit is used to enable the Block count register,
21588                                                      which is only relevant for multiple block transfers. When
21589                                                      this bit is 0, the Block Count register is disabled, which
21590                                                      is useful in executing an infinite transfer.                              */
21591       __IOM uint32_t ACMDEN     : 2;            /*!< [3..2] This field determines use of auto command functions.
21592                                                      There are two methods to stop Multiple-block read and write
21593                                                      operation. (1) Auto CMD12 Enable Multiple-block read and
21594                                                      write commands for memory require CMD12 to stop the operation.
21595                                                      When this field is set to 01b, the Host Controller issues
21596                                                      CMD12 automatically when last block transfer is completed.
21597                                                      Auto CMD12 error is indicated to the Auto CMD Error Status
21598                                                      register. The Host Driver shall not set this bit if the
21599                                                      command does not require CMD12. (2) Auto CMD23                            */
21600       __IOM uint32_t DXFERDIRSEL : 1;           /*!< [4..4] Data Transfer Direction Select. This bit defines the
21601                                                      direction of data transfers.                                              */
21602       __IOM uint32_t BLKSEL     : 1;            /*!< [5..5] This bit enables multiple block data transfers.                    */
21603             uint32_t            : 10;
21604       __IOM uint32_t RESPTYPESEL : 2;           /*!< [17..16] Response Type Select                                             */
21605             uint32_t            : 1;
21606       __IOM uint32_t CMDCRCCHKEN : 1;           /*!< [19..19] If this bit is set to 1, the HC shall check the CRC
21607                                                      field in the response. If an error is detected, it is reported
21608                                                      as a Command CRC Error. If this bit is set to 0, the CRC
21609                                                      field is not checked.                                                     */
21610       __IOM uint32_t CMDIDXCHKEN : 1;           /*!< [20..20] If this bit is set to 1, the HC shall check the index
21611                                                      field in the response to see if it has the same value as
21612                                                      the command index. If it is not, it is reported as a Command
21613                                                      Index Error. If this bit is set to 0, the Index field is
21614                                                      not checked.                                                              */
21615       __IOM uint32_t DATAPRSNTSEL : 1;          /*!< [21..21] This bit is set to 1 to indicate that data is present
21616                                                      and shall be transferred using the DAT line. If is set
21617                                                      to 0 for the following: 1. Commands using only CMD line
21618                                                      (ex. CMD52) 2. Commands with no data transfer but using
21619                                                      busy signal on DAT[0] line (R1b or R5b ex. CMD38) 3. Resume
21620                                                      Command                                                                   */
21621       __IOM uint32_t CMDTYPE    : 2;            /*!< [23..22] There are three types of special commands. Suspend,
21622                                                      Resume and Abort. These bits shall bet set to 00b for all
21623                                                      other commands. Suspend Command If the Suspend command
21624                                                      succeeds, the HC shall assume the SD Bus has been released
21625                                                      and that it is possible to issue the next command which
21626                                                      uses the DAT line. The HC shall de-assert Read Wait for
21627                                                      read transactions and stop checking busy for write transactions.
21628                                                      The Interrupt cycle shall start, in 4-bit mode. If the
21629                                                      Suspend command fails, the HC shall maintain its curren                   */
21630       __IOM uint32_t CMDIDX     : 6;            /*!< [29..24] This bit shall be set to the command number (CMD0-63,
21631                                                      ACMD063).                                                                 */
21632             uint32_t            : 2;
21633     } TRANSFER_b;
21634   } ;
21635 
21636   union {
21637     __IOM uint32_t RESPONSE0;                   /*!< (@ 0x00000010) Response0                                                  */
21638 
21639     struct {
21640       __IOM uint32_t CMDRESP0   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21641                                                      transmitted on the SD Bus, REP[] refers to a bit range
21642                                                      within the Response register.                                             */
21643     } RESPONSE0_b;
21644   } ;
21645 
21646   union {
21647     __IOM uint32_t RESPONSE1;                   /*!< (@ 0x00000014) Response1                                                  */
21648 
21649     struct {
21650       __IOM uint32_t CMDRESP1   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21651                                                      transmitted on the SD Bus, REP[] refers to a bit range
21652                                                      within the Response register.                                             */
21653     } RESPONSE1_b;
21654   } ;
21655 
21656   union {
21657     __IOM uint32_t RESPONSE2;                   /*!< (@ 0x00000018) Response2                                                  */
21658 
21659     struct {
21660       __IOM uint32_t CMDRESP2   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21661                                                      transmitted on the SD Bus, REP[] refers to a bit range
21662                                                      within the Response register.                                             */
21663     } RESPONSE2_b;
21664   } ;
21665 
21666   union {
21667     __IOM uint32_t RESPONSE3;                   /*!< (@ 0x0000001C) Response3                                                  */
21668 
21669     struct {
21670       __IOM uint32_t CMDRESP3   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21671                                                      transmitted on the SD Bus, REP[] refers to a bit range
21672                                                      within the Response register.                                             */
21673     } RESPONSE3_b;
21674   } ;
21675 
21676   union {
21677     __IOM uint32_t BUFFER;                      /*!< (@ 0x00000020) Buffer data port                                           */
21678 
21679     struct {
21680       __IOM uint32_t BUFFERDATA : 32;           /*!< [31..0] The Host Controller Buffer can be accessed through this
21681                                                      32-bit Data Port Register.                                                */
21682     } BUFFER_b;
21683   } ;
21684 
21685   union {
21686     __IOM uint32_t PRESENT;                     /*!< (@ 0x00000024) Present state                                              */
21687 
21688     struct {
21689       __IOM uint32_t CMDINHCMD  : 1;            /*!< [0..0] If this bit is 0, it indicates the CMD line is not in
21690                                                      use and the HC can issue a SD command using the CMD line.
21691                                                      This bit is set immediately after the Command register
21692                                                      (00Fh) is written. This bit is cleared when the command
21693                                                      response is received. Even if the Command Inhibit (DAT)
21694                                                      is set to 1, Commands using only the CMD line can be issued
21695                                                      if this bit is 0. Changing from 1 to 0 generates a Command
21696                                                      complete interrupt in the Normal Interrupt Status register.
21697                                                      If the HC cannot issue the command because of a comma                     */
21698       __IOM uint32_t CMDINHDAT  : 1;            /*!< [1..1] This status bit is generated if either the DAT Line Active
21699                                                      or the Read transfer Active is set to 1. If this bit is
21700                                                      0, it indicates the HC can issue the next SD command. Commands
21701                                                      with busy signal belong to Command Inhibit (DAT) (ex. R1b,
21702                                                      R5b type). Changing from 1 to 0 generates a Transfer Complete
21703                                                      interrupt in the Normal interrupt status register. Note:
21704                                                      The SD Host Driver can save registers in the range of 000-00Dh
21705                                                      for a suspend transaction after this bit has changed from
21706                                                      1 to 0.                                                                   */
21707       __IOM uint32_t DLINEACT   : 1;            /*!< [2..2] This bit indicates whether one of the DAT line on SD
21708                                                      bus is in use.                                                            */
21709       __IOM uint32_t RETUNINGREQUEST : 1;       /*!< [3..3] Re-Tuning Request Host Controller may request Host Driver
21710                                                      to execute re-tuning sequence by setting this bit when
21711                                                      the data window is shifted by temperature drift and a tuned
21712                                                      sampling point does not have a good margin to receive correct
21713                                                      data. This bit is cleared when a command is issued with
21714                                                      setting Execute Tuning in the Host Control 2 register.
21715                                                      Changing of this bit from 0 to 1 generates Re-Tuning Event.
21716                                                      Refer to Normal Interrupt registers for more detail. This
21717                                                      bit isn't set to 1 if Sampling Clock Select in                            */
21718             uint32_t            : 4;
21719       __IOM uint32_t WRXFERACT  : 1;            /*!< [8..8] This status indicates a write transfer is active. If
21720                                                      this bit is 0, it means no valid write data exists in the
21721                                                      HC. This bit is set in either of the following cases: After
21722                                                      the end bit of the write command. When writing a 1 to Continue
21723                                                      Request in the Block Gap Control register to restart a
21724                                                      write transfer. This bit is cleared in either of the following
21725                                                      cases: After getting the CRC status of the last data block
21726                                                      as specified by the transfer count (Single or Multiple)
21727                                                      After getting a CRC status of any block wher                              */
21728       __IOM uint32_t RDXFERACT  : 1;            /*!< [9..9] This status is used for detecting completion of a read
21729                                                      transfer. This bit is set to 1 for either of the following
21730                                                      conditions: After the end bit of the read command When
21731                                                      writing a 1 to continue Request in the Block Gap Control
21732                                                      register to restart a read transfer This bit is cleared
21733                                                      to 0 for either of the following conditions: When the last
21734                                                      data block as specified by block length is transferred
21735                                                      to the system. When all valid data blocks have been transferred
21736                                                      to the system and no current block transfers are be                       */
21737       __IOM uint32_t BUFWREN    : 1;            /*!< [10..10] This status is used for non-DMA write transfers. This
21738                                                      read only flag indicates if space is available for write
21739                                                      data. If this bit is 1, data can be written to the buffer.
21740                                                      A change of this bit from 1 to 0 occurs when all the block
21741                                                      data is written to the buffer. A change of this bit from
21742                                                      0 to 1 occurs when top of block data can be written to
21743                                                      the buffer and generates the Buffer Write Ready Interrupt.                */
21744       __IOM uint32_t BUFRDEN    : 1;            /*!< [11..11] This status is used for non-DMA read transfers. This
21745                                                      read only flag indicates that valid data exists in the
21746                                                      host side buffer status. If this bit is 1, readable data
21747                                                      exists in the buffer. A change of this bit from 1 to 0
21748                                                      occurs when all the block data is read from the buffer.
21749                                                      A change of this bit from 0 to 1 occurs when all the block
21750                                                      data is ready in the buffer and generates the Buffer Read
21751                                                      Ready Interrupt.                                                          */
21752             uint32_t            : 4;
21753       __IOM uint32_t CARDINSERTED : 1;          /*!< [16..16] This bit indicates whether a card has been inserted.
21754                                                      Changing from 0 to 1 generates a Card Insertion interrupt
21755                                                      in the Normal Interrupt Status register and changing from
21756                                                      1 to 0 generates a Card Removal Interrupt in the Normal
21757                                                      Interrupt Status register. The Software Reset For All in
21758                                                      the Software Reset register shall not affect this bit.
21759                                                      If a Card is removed while its power is on and its clock
21760                                                      is oscillating, the HC shall clear SD Bus Power in the
21761                                                      Power Control register and SD Clock Enable in the Clock
21762                                                      contro                                                                    */
21763       __IOM uint32_t CARDSTABLE : 1;            /*!< [17..17] This bit is used for testing. If it is 0, the Card
21764                                                      Detect Pin Level is not stable. If this bit is set to 1,
21765                                                      it means the Card Detect Pin Level is stable. The Software
21766                                                      Reset For All in the Software Reset Register shall not
21767                                                      affect this bit.                                                          */
21768       __IOM uint32_t CARDDET    : 1;            /*!< [18..18] This bit reflects the inverse value of the SDCD# pin.            */
21769       __IOM uint32_t WRPROTSW   : 1;            /*!< [19..19] The Write Protect Switch is supported for memory and
21770                                                      combo cards. This bit reflects the SDWP# pin.                             */
21771       __IOM uint32_t DAT30LINE  : 4;            /*!< [23..20] This status is used to check DAT line level to recover
21772                                                      from errors, and for debugging. This is especially useful
21773                                                      in detecting the busy signal level from DAT[0].                           */
21774       __IOM uint32_t CMDLINE    : 1;            /*!< [24..24] This status is used to check CMD line level to recover
21775                                                      from errors, and for debugging.                                           */
21776       __IOM uint32_t DAT74LINE  : 4;            /*!< [28..25] This status is used to check DAT line level to recover
21777                                                      from errors, and for debugging.                                           */
21778             uint32_t            : 3;
21779     } PRESENT_b;
21780   } ;
21781 
21782   union {
21783     __IOM uint32_t HOSTCTRL1;                   /*!< (@ 0x00000028) Host control 1                                             */
21784 
21785     struct {
21786       __IOM uint32_t LEDCONTROL : 1;            /*!< [0..0] This bit is used to caution the user not to remove the
21787                                                      card while the SD card is being accessed. If the software
21788                                                      is going to issue multiple SD commands, this bit can be
21789                                                      set during all transactions. It is not necessary to change
21790                                                      for each transaction.                                                     */
21791       __IOM uint32_t DATATRANSFERWIDTH : 1;     /*!< [1..1] (SD1 or SD4) This bit selects the data width of the HC.
21792                                                      The HD shall select it to match the data width of the SD
21793                                                      card.                                                                     */
21794       __IOM uint32_t HISPEEDEN  : 1;            /*!< [2..2] This bit is optional. Before setting this bit, the HD
21795                                                      shall check the High Speed Support in the capabilities
21796                                                      register. If this bit is set to 0 (default), the HC outputs
21797                                                      CMD line and DAT lines at the falling edge of the SD clock
21798                                                      (up to 25 MHz/ 20MHz for MMC). If this bit is set to 1,
21799                                                      the HC outputs CMD line and DAT lines at the rising edge
21800                                                      of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz
21801                                                      (for SD3.0) If Preset Value Enable in the Host Control
21802                                                      2 register is set to 1, Host Driver needs to reset SD C                   */
21803       __IOM uint32_t DMASELECT  : 2;            /*!< [4..3] One of supported DMA modes can be selected. The host
21804                                                      driver shall check support of DMA modes by referring the
21805                                                      Capabilities register.                                                    */
21806       __IOM uint32_t XFERWIDTH  : 1;            /*!< [5..5] This bit controls 8-bit bus width mode for embedded device.
21807                                                      Support of this function is indicated in 8-bit Support
21808                                                      for Embedded Device in the Capabilities register. If a
21809                                                      device supports 8-bit bus mode, this bit may be set to
21810                                                      1. If this bit is 0, bus width is controlled by Data Transfer
21811                                                      Width in the Host Control 1 register.This bit is not effective
21812                                                      when multiple devices are installed on a bus slot (Slot
21813                                                      Type is set to 10b in the Capabilities register). In this
21814                                                      case, each device bus width is controlled by Bu                           */
21815       __IOM uint32_t TESTLEVEL  : 1;            /*!< [6..6] This bit is enabled while the Card Detect Signal Selection
21816                                                      is set to 1 and it indicates card inserted or not. Generates
21817                                                      (card ins or card removal) interrupt when the normal int
21818                                                      sts enable bit is set.                                                    */
21819       __IOM uint32_t CARDSRC    : 1;            /*!< [7..7] This bit selects source for card detection.                        */
21820       __IOM uint32_t SDBUSPOWER : 1;            /*!< [8..8] Before setting this bit, the SD host driver shall set
21821                                                      SD Bus Voltage Select. If the HC detects the No Card State,
21822                                                      this bit shall be cleared.                                                */
21823       __IOM uint32_t VOLTSELECT : 3;            /*!< [11..9] By setting these bits, the HD selects the voltage level
21824                                                      for the SD card. Before setting this register, the HD shall
21825                                                      check the voltage support bits in the capabilities register.
21826                                                      If an unsupported voltage is selected, the Host System
21827                                                      shall not supply SD bus voltage. All voltage select values
21828                                                      not enumerated here are reserved.                                         */
21829       __IOM uint32_t HWRESET    : 1;            /*!< [12..12] Hardware reset signal is generated for eMMC card when
21830                                                      this bit is set                                                           */
21831             uint32_t            : 3;
21832       __IOM uint32_t STOPATBLOCKGAPREQUEST : 1; /*!< [16..16] This bit is used to stop executing a transaction at
21833                                                      the next block gap for non- DMA,SDMA and ADMA transfers.
21834                                                      Until the transfer complete is set to 1, indicating a transfer
21835                                                      completion the HD shall leave this bit set to 1. Clearing
21836                                                      both the Stop At Block Gap Request and Continue Request
21837                                                      shall not cause the transaction to restart. Read Wait is
21838                                                      used to stop the read transaction at the block gap. The
21839                                                      HC shall honour Stop At Block Gap Request for write transfers,
21840                                                      but for read transfers it requires that the SD ca                         */
21841       __IOM uint32_t CONTREQ    : 1;            /*!< [17..17] This bit is used to restart a transaction which was
21842                                                      stopped using the Stop At Block Gap Request. To cancel
21843                                                      stop at the block gap, set Stop At block Gap Request to
21844                                                      0 and set this bit to restart the transfer. The HC automatically
21845                                                      clears this bit in either of the following cases: 1) In
21846                                                      the case of a read transaction, the DAT Line Active changes
21847                                                      from 0 to 1 as a read transaction restarts. 2) In the case
21848                                                      of a write transaction, the Write transfer active changes
21849                                                      from 0 to 1 as the write transaction restarts. The                        */
21850       __IOM uint32_t READWAITCTRL : 1;          /*!< [18..18] The read wait function is optional for SDIO cards.
21851                                                      If the card supports read wait, set this bit to enable
21852                                                      use of the read wait protocol to stop read data using DAT[2]
21853                                                      line. Otherwise the HC has to stop the SD clock to hold
21854                                                      read data, which restricts commands generation. When the
21855                                                      HD detects an SD card insertion, it shall set this bit
21856                                                      according to the CCCR of the SDIO card. If the card does
21857                                                      not support read wait, this bit shall never be set to 1
21858                                                      otherwise DAT line conflict may occur. If this bit is set
21859                                                      to 0,                                                                     */
21860       __IOM uint32_t GAP        : 1;            /*!< [19..19] This bit is valid only in 4-bit mode of the SDIO card
21861                                                      and selects a sample point in the interrupt cycle. Setting
21862                                                      to 1 enables interrupt detection at the block gap for a
21863                                                      multiple block transfer. If the SD card cannot signal an
21864                                                      interrupt during a multiple block transfer, this bit should
21865                                                      be set to 0. When the HD detects an SD card insertion,
21866                                                      it shall set this bit according to the CCCR of the SDIO
21867                                                      card.                                                                     */
21868       __IOM uint32_t SPIMODE    : 1;            /*!< [20..20] SPI mode enable bit.                                             */
21869       __IOM uint32_t BOOTEN     : 1;            /*!< [21..21] To start boot code access                                        */
21870       __IOM uint32_t ALTBOOTEN  : 1;            /*!< [22..22] To start boot code access in alternative mode.                   */
21871       __IOM uint32_t BOOTACKCHK : 1;            /*!< [23..23] To check for the boot acknowledge in boot operation.             */
21872       __IOM uint32_t WUENCARDINT : 1;           /*!< [24..24] This bit enables wakeup event via Card Interrupt assertion
21873                                                      in the Normal Interrupt Status register. This bit can be
21874                                                      set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.                  */
21875       __IOM uint32_t WUENCARDINSERT : 1;        /*!< [25..25] This bit enables wakeup event via Card Insertion assertion
21876                                                      in the Normal Interrupt Status register. FN_WUS (Wake up
21877                                                      Support) in CIS does not affect this bit.                                 */
21878       __IOM uint32_t WUENCARDREMOVL : 1;        /*!< [26..26] This bit enables wakeup event via Card Removal assertion
21879                                                      in the Normal Interrupt Status register. FN_WUS (Wake up
21880                                                      Support) in CIS does not affect this bit.                                 */
21881             uint32_t            : 5;
21882     } HOSTCTRL1_b;
21883   } ;
21884 
21885   union {
21886     __IOM uint32_t CLOCKCTRL;                   /*!< (@ 0x0000002C) Clock control                                              */
21887 
21888     struct {
21889       __IOM uint32_t CLKEN      : 1;            /*!< [0..0] This bit is set to 0 when the HD is not using the HC
21890                                                      or the HC awaits a wakeup event. The HC should stop its
21891                                                      internal clock to go very low power state. Still, registers
21892                                                      shall be able to be read and written. Clock starts to oscillate
21893                                                      when this bit is set to 1. When clock oscillation is stable,
21894                                                      the HC shall set Internal Clock Stable in this register
21895                                                      to 1. This bit shall not affect card detection.                           */
21896       __IOM uint32_t CLKSTABLE  : 1;            /*!< [1..1] This bit is set to 1 when SD clock is stable after writing
21897                                                      to Internal Clock Enable in this register to 1. The SD
21898                                                      Host Driver shall wait to set SD Clock Enable until this
21899                                                      bit is set to 1. Note: This is useful when using PLL for
21900                                                      a clock oscillator that requires setup time.                              */
21901       __IOM uint32_t SDCLKEN    : 1;            /*!< [2..2] The HC shall stop SDCLK when writing this bit to 0. SDCLK
21902                                                      frequency Select can be changed when this bit is 0. Then,
21903                                                      the HC shall maintain the same clock frequency until SDCLK
21904                                                      is stopped (Stop at SDCLK = 0). If the HC detects the No
21905                                                      Card state, this bit shall be cleared.                                    */
21906             uint32_t            : 2;
21907       __IOM uint32_t CLKGENSEL  : 1;            /*!< [5..5] This bit is used to select the clock generator mode in
21908                                                      SDCLK Frequency Select. If the Programmable Clock Mode
21909                                                      is supported (non-zero value is set to Clock Multiplier
21910                                                      in the Capabilities register), this bit attribute is RW,
21911                                                      and if not supported, this bit attribute is RO and zero
21912                                                      is read. This bit depends on the setting of Preset Value
21913                                                      Enable in the Host Control 2 register. If the Preset Value
21914                                                      Enable = 0, this bit is set by Host Driver. If the Preset
21915                                                      Value Enable = 1, this bit is automatically set to a value                */
21916       __IOM uint32_t UPRCLKDIV  : 2;            /*!< [7..6] Bit 07-06 is assigned to bit 09-08 of clock divider in
21917                                                      SDCLK Frequency Select                                                    */
21918       __IOM uint32_t FREQSEL    : 8;            /*!< [15..8] This register is used to select the frequency of the
21919                                                      SDCLK pin. The frequency is not programmed directly; rather
21920                                                      this register holds the divisor of the Base Clock Frequency
21921                                                      For SD clock in the capabilities register. Only the following
21922                                                      settings are allowed. (1) 8-bit Divided Clock Mode Setting
21923                                                      00h specifies the highest frequency of the SD Clock. When
21924                                                      setting multiple bits, the most significant bit is used
21925                                                      as the divisor. But multiple bits should not be set. The
21926                                                      two default divider values can be calculated b                            */
21927       __IOM uint32_t TIMEOUTCNT : 4;            /*!< [19..16] This value determines the interval by which DAT line
21928                                                      time-outs are detected. Refer to the Data Time-out Error
21929                                                      in the Error Interrupt Status register for information
21930                                                      on factors that dictate time-out generation. Time-out clock
21931                                                      frequency will be generated by dividing the sdclockTMCLK
21932                                                      by this value. When setting this register, prevent inadvertent
21933                                                      time-out events by clearing the Data Time-out Error Status
21934                                                      Enable (in the Error Interrupt Status Enable register)
21935                                                      At the initialization of the HC, the HD shall set th                      */
21936             uint32_t            : 4;
21937       __IOM uint32_t SWRSTALL   : 1;            /*!< [24..24] This reset affects the entire HC except for the card
21938                                                      detection circuit. Register bits of type ROC, RW, RW1C,
21939                                                      RWAC are cleared to 0. During its initialization, the HD
21940                                                      shall set this bit to 1 to reset the HC. The HC shall reset
21941                                                      this bit to 0 when capabilities registers are valid and
21942                                                      the HD can read them. Additional use of Software Reset
21943                                                      For All may not affect the value of the Capabilities registers.
21944                                                      If this bit is set to 1, the SD card shall reset itself
21945                                                      and must be re initialized by the HD. A reset pulse is                    */
21946       __IOM uint32_t SWRSTCMD   : 1;            /*!< [25..25] Only part of command circuit is reset. The following
21947                                                      registers and bits are cleared by this bit: Present State
21948                                                      register Command Inhibit (CMD) Normal Interrupt Status
21949                                                      register Command Complete                                                 */
21950       __IOM uint32_t SWRSTDAT   : 1;            /*!< [26..26] Only part of data circuit is reset. The following registers
21951                                                      and bits are cleared by this bit: Buffer Data Port Register
21952                                                      Buffer is cleared and Initialized. Present State register
21953                                                      Buffer read Enable Buffer write Enable Read Transfer Active
21954                                                      Write Transfer Active DAT Line Active Command Inhibit (DAT)
21955                                                      Block Gap Control register Continue Request Stop At Block
21956                                                      Gap Request Normal Interrupt Status register Buffer Read
21957                                                      Ready Buffer Write Ready Block Gap Event Transfer Complete                */
21958             uint32_t            : 5;
21959     } CLOCKCTRL_b;
21960   } ;
21961 
21962   union {
21963     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000030) Interrupt enable                                           */
21964 
21965     struct {
21966       __IOM uint32_t COMMANDCOMPLETE : 1;       /*!< [0..0] This bit is set when we get the end bit of the command
21967                                                      response (Except Auto CMD12 and Auto CMD23) Note: Command
21968                                                      Time-out Error has higher priority than Command Complete.
21969                                                      If both are set to 1, it can be considered that the response
21970                                                      was not received correctly.                                               */
21971       __IOM uint32_t TRANSFERCOMPLETE : 1;      /*!< [1..1] This bit is set when a read / write transaction is completed.
21972                                                      Read Transaction: This bit is set at the falling edge of
21973                                                      Read Transfer Active Status. There are two cases in which
21974                                                      the Interrupt is generated. The first is when a data transfer
21975                                                      is completed as specified by data length (After the last
21976                                                      data has been read to the Host System). The second is when
21977                                                      data has stopped at the block gap and completed the data
21978                                                      transfer by setting the Stop At Block Gap Request in the
21979                                                      Block Gap Control Register (After valid da                                */
21980       __IOM uint32_t BLOCKGAPEVENT : 1;         /*!< [2..2] If the Stop At Block Gap Request in the Block Gap Control
21981                                                      Register is set, this bit is set. Read Transaction: This
21982                                                      bit is set at the falling edge of the DAT Line Active Status
21983                                                      (When the transaction is stopped at SD Bus timing. The
21984                                                      Read Wait must be supported inorder to use this function).
21985                                                      Write Transaction: This bit is set at the falling edge
21986                                                      of Write Transfer Active Status (After getting CRC status
21987                                                      at SD Bus timing).                                                        */
21988       __IOM uint32_t DMAINTERRUPT : 1;          /*!< [3..3] This status is set if the HC detects the Host DMA Buffer
21989                                                      Boundary in the Block Size regiser.                                       */
21990       __IOM uint32_t BUFFERWRITEREADY : 1;      /*!< [4..4] This status is set if the Buffer Write Enable changes
21991                                                      from 0 to 1.                                                              */
21992       __IOM uint32_t BUFFERREADREADY : 1;       /*!< [5..5] This status is set if the Buffer Read Enable changes
21993                                                      from 0 to 1. Buffer Read Ready is set to 1 for every CMD19
21994                                                      execution in tuning procedure.                                            */
21995       __IOM uint32_t CARDINSERTION : 1;         /*!< [6..6] This status is set if the Card Inserted in the Present
21996                                                      State register changes from 0 to 1. When the HD writes
21997                                                      this bit to 1 to clear this status the status of the Card
21998                                                      Inserted in the Present State register should be confirmed.
21999                                                      Because the card detect may possibly be changed when the
22000                                                      HD clear this bit an Interrupt event may not be generated.                */
22001       __IOM uint32_t CARDREMOVAL : 1;           /*!< [7..7] This status is set if the Card Inserted in the Present
22002                                                      State register changes from 1 to 0. When the HD writes
22003                                                      this bit to 1 to clear this status the status of the Card
22004                                                      Inserted in the Present State register should be confirmed.
22005                                                      Because the card detect may possibly be changed when the
22006                                                      HD clear this bit an Interrupt event may not be generated.                */
22007       __IOM uint32_t CARDINTERRUPT : 1;         /*!< [8..8] Writing this bit to 1 does not clear this bit. It is
22008                                                      cleared by resetting the SD card interrupt factor. In 1-bit
22009                                                      mode, the HC shall detect the Card Interrupt without SD
22010                                                      Clock to support wakeup. In 4-bit mode, the card interrupt
22011                                                      signal is sampled during the interrupt cycle, so there
22012                                                      are some sample delays between the interrupt signal from
22013                                                      the card and the interrupt to the Host system. when this
22014                                                      status has been set and the HD needs to start this interrupt
22015                                                      service, Card Interrupt Status Enable in the Normal I                     */
22016       __IOM uint32_t INTA       : 1;            /*!< [9..9] This status is set if INT_A is enabled and INT_A# pin
22017                                                      is in low level. Writing this bit to 1 does not clear this
22018                                                      bit. It is cleared by resetting the INT_A interrupt factor                */
22019       __IOM uint32_t INTB       : 1;            /*!< [10..10] This status is set if INT_B is enabled and INT_B# pin
22020                                                      is in low level. Writing this bit to 1 does not clear this
22021                                                      bit. It is cleared by resetting the INT_B interrupt factor                */
22022       __IOM uint32_t INTC       : 1;            /*!< [11..11] This status is set if INT_C is enabled and INT_C# pin
22023                                                      is in low level. Writing this bit to 1 does not clear this
22024                                                      bit. It is cleared by resetting the INT_C interrupt factor                */
22025       __IOM uint32_t RETUNINGEVENT : 1;         /*!< [12..12] This status is set if Re-Tuning Request in the Present
22026                                                      State register changes from 0 to 1. Host Controller requests
22027                                                      Host Driver to perform re-tuning for next data transfer.
22028                                                      Current data transfer (not large block count) can be completed
22029                                                      without re-tuning.                                                        */
22030       __IOM uint32_t BOOTACKRCV : 1;            /*!< [13..13] This status is set if the boot acknowledge is received
22031                                                      from device.                                                              */
22032       __IOM uint32_t BOOTTERMINATE : 1;         /*!< [14..14] Interrupt This status is set if the boot operation
22033                                                      get terminated                                                            */
22034       __IOM uint32_t ERRORINTERRUPT : 1;        /*!< [15..15] If any of the bits in the Error Interrupt Status Register
22035                                                      are set, then this bit is set. Therefore the HD can test
22036                                                      for an error by checking this bit first.                                  */
22037       __IOM uint32_t COMMANDTIMEOUTERROR : 1;   /*!< [16..16] Command CRC Error is generated in two cases. 1. If
22038                                                      a response is returned and the Command Time-out Error is
22039                                                      set to 0, this bit is set to 1 when detecting a CRT error
22040                                                      in the command response 2. The HC detects a CMD line conflict
22041                                                      by monitoring the CMD line when a command is issued. If
22042                                                      the HC drives the CMD line to 1 level, but detects 0 level
22043                                                      on the CMD line at the next SDCLK edge, then the HC shall
22044                                                      abort the command (Stop driving CMD line) and set this
22045                                                      bit to 1. The Command Timeout Error shall also be set t                   */
22046       __IOM uint32_t COMMANDCRCERROR : 1;       /*!< [17..17] Occurs when detecting that the end bit of a command
22047                                                      response is 0.                                                            */
22048       __IOM uint32_t COMMANDENDBITERROR : 1;    /*!< [18..18] Occurs only if the no response is returned within 64
22049                                                      SDCLK cycles from the end bit of the command. If the HC
22050                                                      detects a CMD line conflict, in which case Command CRC
22051                                                      Error shall also be set. This bit shall be set without
22052                                                      waiting for 64 SDCLK cycles because the command will be
22053                                                      aborted by the HC.                                                        */
22054       __IOM uint32_t COMMANDINDEXERROR : 1;     /*!< [19..19] Occurs if a Command Index error occurs in the Command
22055                                                      Response.                                                                 */
22056       __IOM uint32_t DATATIMEOUTERROR : 1;      /*!< [20..20] Occurs when detecting one of following timeout conditions.
22057                                                      1. Busy Timeout for R1b, R5b type. 2. Busy Timeout after
22058                                                      Write CRC status 3. Write CRC status Timeout 4. Read Data
22059                                                      Timeout                                                                   */
22060       __IOM uint32_t DATACRCERROR : 1;          /*!< [21..21] Occurs when detecting CRC error when transferring read
22061                                                      data which uses the DAT line or when detecting the Write
22062                                                      CRC Status having a value of other than 0.                                */
22063       __IOM uint32_t DATAENDBITERROR : 1;       /*!< [22..22] Occurs when detecting 0 at the end bit position of
22064                                                      read data which uses the DAT line or the end bit position
22065                                                      of the CRC status.                                                        */
22066       __IOM uint32_t CURRENTLIMITERROR : 1;     /*!< [23..23] By setting the SD Bus Power bit in the Power Control
22067                                                      Register, the HC is requested to supply power for the SD
22068                                                      Bus. If the HC supports the Current Limit Function, it
22069                                                      can be protected from an Illegal card by stopping power
22070                                                      supply to the card in which case this bit indicates a failure
22071                                                      status. Reading 1 means the HC is not supplying power to
22072                                                      SD card due to some failure. Reading 0 means that the HC
22073                                                      is supplying power and no error has occurred. This bit
22074                                                      shall always set to be 0, if the HC does not support this
22075                                                      f                                                                         */
22076       __IOM uint32_t AUTOCMDERROR : 1;          /*!< [24..24] Auto CMD12 and Auto CMD23 use this error status. This
22077                                                      bit is set when detecting that one of the bits D00-D04
22078                                                      in Auto CMD Error Status register has changed from 0 to
22079                                                      1. In case of Auto CMD12, this bit is set to 1, not only
22080                                                      when the errors in Auto CMD12 occur but also when Auto
22081                                                      CMD12 is not executed due to the previous command error.                  */
22082       __IOM uint32_t ADMAERROR  : 1;            /*!< [25..25] This bit is set when the Host Controller detects errors
22083                                                      during ADMA based data transfer. The state of the ADMA
22084                                                      at an error occurrence is saved in the ADMA Error Status
22085                                                      Register.                                                                 */
22086             uint32_t            : 2;
22087       __IOM uint32_t TGTRESPERR : 1;            /*!< [28..28] Occurs when detecting error in aximst_bresp or aximst_rresp      */
22088       __IOM uint32_t VNDERRSTAT : 3;            /*!< [31..29] Vendor specific error status.                                    */
22089     } INTSTAT_b;
22090   } ;
22091 
22092   union {
22093     __IOM uint32_t INTENABLE;                   /*!< (@ 0x00000034) Normal interrupt status enable                             */
22094 
22095     struct {
22096       __IOM uint32_t COMMANDCOMPLETESTATUSENABLE : 1;/*!< [0..0] Description                                                   */
22097       __IOM uint32_t TRANSFERCOMPLETESTATUSENABLE : 1;/*!< [1..1] Description                                                  */
22098       __IOM uint32_t BLOCKGAPEVENTSTATUSENABLE : 1;/*!< [2..2] Description                                                     */
22099       __IOM uint32_t DMAINTERRUPTSTATUSENABLE : 1;/*!< [3..3] Description                                                      */
22100       __IOM uint32_t BUFFERWRITEREADYSTATUSENABLE : 1;/*!< [4..4] Description                                                  */
22101       __IOM uint32_t BUFFERREADREADYSTATUSENABLE : 1;/*!< [5..5] Description                                                   */
22102       __IOM uint32_t CARDINSERTIONSTATUSENABLE : 1;/*!< [6..6] Description                                                     */
22103       __IOM uint32_t CARDREMOVALSTATUSENABLE : 1;/*!< [7..7] Description                                                       */
22104       __IOM uint32_t CARDINTERRUPTSTATUSENABLE : 1;/*!< [8..8] If this bit is set to 0, the HC shall clear Interrupt
22105                                                      request to the System. The Card Interrupt detection is
22106                                                      stopped when this bit is cleared and restarted when this
22107                                                      bit is set to 1. The HD may clear the Card Interrupt Status
22108                                                      Enable before servicing the Card Interrupt and may set
22109                                                      this bit again after all Interrupt requests from the card
22110                                                      are cleared to prevent inadvertent Interrupts.                            */
22111       __IOM uint32_t INTASTATUSENABLE : 1;      /*!< [9..9] If this bit is set to 0, the Host Controller shall clear
22112                                                      the interrupt request to the System. The Host Driver may
22113                                                      clear this bit before servicing the INT_A and may set this
22114                                                      bit again after all interrupt requests to INT_A pin are
22115                                                      cleared to prevent inadvertent interrupts.                                */
22116       __IOM uint32_t INTBSTATUSENABLE : 1;      /*!< [10..10] If this bit is set to 0, the Host Controller shall
22117                                                      clear the interrupt request to the System. The Host Driver
22118                                                      may clear this bit before servicing the INT_B and may set
22119                                                      this bit again after all interrupt requests to INT_B pin
22120                                                      are cleared to prevent inadvertent interrupts.                            */
22121       __IOM uint32_t INTCSTATUSENABLE : 1;      /*!< [11..11] If this bit is set to 0, the Host Controller shall
22122                                                      clear the interrupt request to the System. The Host Driver
22123                                                      may clear this bit before servicing the INT_C and may set
22124                                                      this bit again after all interrupt requests to INT_C pin
22125                                                      are cleared to prevent inadvertent interrupts. Interrupt
22126                                                      enable                                                                    */
22127       __IOM uint32_t RETUNINGEVENTSTATUSENABLE : 1;/*!< [12..12] Interrupt                                                     */
22128       __IOM uint32_t BOOTACKRCVENABLE : 1;      /*!< [13..13] Interrupt                                                        */
22129       __IOM uint32_t BOOTTERMINATE : 1;         /*!< [14..14] Boot is terminated?                                              */
22130       __IOM uint32_t FIXEDTO0   : 1;            /*!< [15..15] The HC shall control error Interrupts using the Error
22131                                                      Interrupt Status Enable register.                                         */
22132       __IOM uint32_t COMMANDTIMEOUTERRORSTATUSENABLE : 1;/*!< [16..16] Desc                                                    */
22133       __IOM uint32_t COMMANDCRCERRORSTATUSENABLE : 1;/*!< [17..17] Desc                                                        */
22134       __IOM uint32_t COMMANDENDBITERRORSTATUSENABLE : 1;/*!< [18..18] Desc                                                     */
22135       __IOM uint32_t COMMANDINDEXERRORSTATUSENABLE : 1;/*!< [19..19] Desc                                                      */
22136       __IOM uint32_t DATATIMEOUTERRORSTATUSENABLE : 1;/*!< [20..20] Desc                                                       */
22137       __IOM uint32_t DATACRCERRORSTATUSENABLE : 1;/*!< [21..21] Desc                                                           */
22138       __IOM uint32_t DATAENDBITERRORSTATUSENABLE : 1;/*!< [22..22] Desc                                                        */
22139       __IOM uint32_t CURRENTLIMITERRORSTATUSENABLE : 1;/*!< [23..23] Desc                                                      */
22140       __IOM uint32_t AUTOCMD12ERRORSTATUSENABLE : 1;/*!< [24..24] Desc                                                         */
22141       __IOM uint32_t ADMAERRORSTATUSENABLE : 1; /*!< [25..25] Desc                                                             */
22142       __IOM uint32_t TUNINGERRORSTATUS : 1;     /*!< [26..26] enable                                                           */
22143             uint32_t            : 1;
22144       __IOM uint32_t TGTRESPERRHOSTERRSTATEN : 1;/*!< [28..28] Desc                                                            */
22145       __IOM uint32_t VENDORSPECIFICERRORSTATUSENABLE : 3;/*!< [31..29] Vendor-specific error status enable.                    */
22146     } INTENABLE_b;
22147   } ;
22148 
22149   union {
22150     __IOM uint32_t INTSIG;                      /*!< (@ 0x00000038) Normal interrupt signal enable                             */
22151 
22152     struct {
22153       __IOM uint32_t CMDCMPEN   : 1;            /*!< [0..0] Interrupt                                                          */
22154       __IOM uint32_t XFERCMPEN  : 1;            /*!< [1..1] Interrupt                                                          */
22155       __IOM uint32_t BLOCKGAPEN : 1;            /*!< [2..2] Interrupt                                                          */
22156       __IOM uint32_t DMAINTEN   : 1;            /*!< [3..3] Interrupt                                                          */
22157       __IOM uint32_t BUFFERWREN : 1;            /*!< [4..4] Interrupt                                                          */
22158       __IOM uint32_t BUFFERRDEN : 1;            /*!< [5..5] Interrupt                                                          */
22159       __IOM uint32_t CARDINSERTEN : 1;          /*!< [6..6] Interrupt                                                          */
22160       __IOM uint32_t CARDREMOVALEN : 1;         /*!< [7..7] Interrupt                                                          */
22161       __IOM uint32_t CARDINTEN  : 1;            /*!< [8..8] Interrupt                                                          */
22162       __IOM uint32_t INTAEN     : 1;            /*!< [9..9] Interrupt                                                          */
22163       __IOM uint32_t INTBEN     : 1;            /*!< [10..10] Interrupt                                                        */
22164       __IOM uint32_t INTCEN     : 1;            /*!< [11..11] Interrupt                                                        */
22165       __IOM uint32_t RETUNEEVENTEN : 1;         /*!< [12..12] Interrupt signal enable                                          */
22166       __IOM uint32_t BOOTACKEN  : 1;            /*!< [13..13] Interrupt                                                        */
22167       __IOM uint32_t BOOTTERM   : 1;            /*!< [14..14] Boot terminate interrupt signal enable                           */
22168       __IOM uint32_t FIXED0     : 1;            /*!< [15..15] Fixed to 0. The HD shall control error Interrupts using
22169                                                      the Error Interrupt Signal Enable register.                               */
22170       __IOM uint32_t CMDTOERREN : 1;            /*!< [16..16] Desc                                                             */
22171       __IOM uint32_t CMDCRCERREN : 1;           /*!< [17..17] Desc                                                             */
22172       __IOM uint32_t CMDENDBITERREN : 1;        /*!< [18..18] Desc                                                             */
22173       __IOM uint32_t CMDIDXERREN : 1;           /*!< [19..19] Desc                                                             */
22174       __IOM uint32_t DATATOERROREN : 1;         /*!< [20..20] Desc                                                             */
22175       __IOM uint32_t DATACRCERREN : 1;          /*!< [21..21] Desc                                                             */
22176       __IOM uint32_t DATAENDERREN : 1;          /*!< [22..22] Desc                                                             */
22177       __IOM uint32_t CURRLMTERREN : 1;          /*!< [23..23] Desc                                                             */
22178       __IOM uint32_t AUTOCMD12ERREN : 1;        /*!< [24..24] Desc                                                             */
22179       __IOM uint32_t ADMAERREN  : 1;            /*!< [25..25] Desc                                                             */
22180       __IOM uint32_t TUNINGERREN : 1;           /*!< [26..26] Desc                                                             */
22181             uint32_t            : 1;
22182       __IOM uint32_t TGTRESPEN  : 1;            /*!< [28..28] Interrupt                                                        */
22183       __IOM uint32_t VNDERREN   : 3;            /*!< [31..29] VNDERREN field description needed here.                          */
22184     } INTSIG_b;
22185   } ;
22186 
22187   union {
22188     __IOM uint32_t AUTO;                        /*!< (@ 0x0000003C) Auto CMD error status                                      */
22189 
22190     struct {
22191       __IOM uint32_t CMD12NOTEXEC : 1;          /*!< [0..0] If memory multiple block data transfer is not started
22192                                                      due to command error, this bit is not set because it is
22193                                                      not necessary to issue Auto CMD12. Setting this bit to
22194                                                      1 means the HC cannot issue Auto CMD12 to stop memory multiple
22195                                                      block transfer due to some error. If this bit is set to
22196                                                      1, other error status bits (D04 - D01) are meaningless.
22197                                                      This bit is set to 0 when Auto CMD Error is generated by
22198                                                      Auto CMD23                                                                */
22199       __IOM uint32_t CMDTOERR   : 1;            /*!< [1..1] Occurs if the no response is returned within 64 SDCLK
22200                                                      cycles from the end bit of the command. If this bit is
22201                                                      set to 1, the other error status bits (D04 - D02) are meaningless.        */
22202       __IOM uint32_t CMDCRCERR  : 1;            /*!< [2..2] Occurs when detecting a CRC error in the command response.         */
22203       __IOM uint32_t CMDENDERR  : 1;            /*!< [3..3] Occurs when detecting that the end bit of command response
22204                                                      is 0.                                                                     */
22205       __IOM uint32_t CMDIDXERR  : 1;            /*!< [4..4] Occurs if the Command Index error occurs in response
22206                                                      to a command.                                                             */
22207             uint32_t            : 2;
22208       __IOM uint32_t NOTAUTOCMD12ERR : 1;       /*!< [7..7] Setting this bit to 1 means CMD_wo_DAT is not executed
22209                                                      due to an Auto CMD12 error (D04 - D01) in this register.
22210                                                      This bit is set to 0 when Auto CMD Error is generated by
22211                                                      Auto CMD23                                                                */
22212             uint32_t            : 8;
22213       __IOM uint32_t UHSMODESEL : 3;            /*!< [18..16] This field is used to select one of UHS-I modes and
22214                                                      effective when 1.8V Signaling Enable is set to 1. If Preset
22215                                                      Value Enable in the Host Control 2 register is set to 1,
22216                                                      Host Controller sets SDCLK Frequency Select, Clock Generator
22217                                                      Select in the Clock Control register and Driver Strength
22218                                                      Select according to Preset Value registers. In this case,
22219                                                      one of preset value registers is selected by this field.
22220                                                      Host Driver needs to reset SD Clock Enable before changing
22221                                                      this field to avoid generating clock glitch. After                        */
22222       __IOM uint32_t SIGNALVOLT : 1;            /*!< [19..19] This bit controls voltage regulator for I/O cell. 3.3V
22223                                                      is supplied to the card regardless of signaling voltage.
22224                                                      Setting this bit from 0 to 1 starts changing signal voltage
22225                                                      from 3.3V to 1.8V. 1.8V regulator output shall be stable
22226                                                      within 5ms. Host Controller clears this bit if switching
22227                                                      to 1.8V signaling fails. Clearing this bit from 1 to 0
22228                                                      starts changing signal voltage from 1.8V to 3.3V. 3.3V
22229                                                      regulator output shall be stable within 5ms. Host Driver
22230                                                      can set this bit to 1 when Host Controller supports 1.8V
22231                                                      s                                                                         */
22232       __IOM uint32_t DRVRSTRSEL : 2;            /*!< [21..20] Host Controller output driver in 1.8V signaling is
22233                                                      selected by this bit. In 3.3V signaling, this field is
22234                                                      not effective. This field can be set depends on Driver
22235                                                      Type A, C and D support bits in the Capabilities register.
22236                                                      This bit depends on setting of Preset Value Enable. If
22237                                                      Preset Value Enable = 0, this field is set by Host Driver.
22238                                                      If Preset Value Enable = 1, this field is automatically
22239                                                      set by a value specified in the one of Preset Value registers.            */
22240       __IOM uint32_t STARTTUNING : 1;           /*!< [22..22] This bit is set to 1 to start tuning procedure and
22241                                                      automatically cleared when tuning procedure is completed.
22242                                                      The result of tuning is indicated to Sampling Clock Select.
22243                                                      Tuning procedure is aborted by writing 0 for more detail
22244                                                      about tuning procedure.                                                   */
22245       __IOM uint32_t SAMPLCLKSEL : 1;           /*!< [23..23] This bit is set by tuning procedure when Execute Tuning
22246                                                      is cleared. Writing 1 to this bit is meaningless and ignored.
22247                                                      Setting 1 means that tuning is completed successfully and
22248                                                      setting 0 means that tuning is failed. Host Controller
22249                                                      uses this bit to select sampling clock to receive CMD and
22250                                                      DAT. This bit is cleared by writing 0. Change of this bit
22251                                                      is not allowed while the Host Controller is receiving response
22252                                                      or a read data block.                                                     */
22253             uint32_t            : 6;
22254       __IOM uint32_t ASYNCINTEN : 1;            /*!< [30..30] This bit can be set to 1 if a card support asynchronous
22255                                                      interrupt and Asynchronous Interrupt Support is set to
22256                                                      1 in the Capabilities register. Asynchronous interrupt
22257                                                      is effective when DAT[1] interrupt is used in 4-bit SD
22258                                                      mode (and zero is set to Interrupt Pin Select in the Shared
22259                                                      Bus Control register). If this bit is set to 1, the Host
22260                                                      Driver can stop the SDCLK during asynchronous interrupt
22261                                                      period to save power. During this period, the Host Controller
22262                                                      continues to deliver Card Interrupt to the host when it                   */
22263       __IOM uint32_t PRESETEN   : 1;            /*!< [31..31] Host Controller Version 3.00 supports this bit. As
22264                                                      the operating SDCLK frequency and I/O driver strength depend
22265                                                      on the Host System implementation, it is difficult to determine
22266                                                      these parameters in the Standard Host Driver. When Preset
22267                                                      Value Enable is set to automatic. This bit enables the
22268                                                      functions defined in the Preset Value registers. If this
22269                                                      bit is set to 0, SDCLK Frequency Select, Clock Generator
22270                                                      Select in the Clock Control register and Driver Strength
22271                                                      Select in Host Control 2 register are set by Host D                       */
22272     } AUTO_b;
22273   } ;
22274 
22275   union {
22276     __IOM uint32_t CAPABILITIES0;               /*!< (@ 0x00000040) Capabilities                                               */
22277 
22278     struct {
22279       __IOM uint32_t TOCLKFREQ  : 6;            /*!< [5..0] This bit shows the base clock frequency used to detect
22280                                                      Data Timeout Error. Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz
22281                                                      Note: The Host System shall support at least one of these
22282                                                      voltages above. The HD sets the SD Bus Voltage Select in
22283                                                      Power Control register according to these support bits.
22284                                                      If multiple voltages are supported, select the usable lower
22285                                                      voltage by comparing the OCR value from the card. These
22286                                                      registers indicate maximum current capability for each
22287                                                      voltage. The value is meaningful if Voltage Support is
22288                                                                                                                                */
22289             uint32_t            : 1;
22290       __IOM uint32_t TOCLKUNIT  : 1;            /*!< [7..7] This bit shows the unit of base clock frequency used
22291                                                      to detect Data Timeout Error.                                             */
22292       __IOM uint32_t SDCLKFREQ  : 8;            /*!< [15..8] 6-bit Base Clock Frequency This mode is supported by
22293                                                      the Host Controller Version 1.00 and 2.00. Upper 2-bit
22294                                                      is not effective and always 0. Unit values are 1MHz. The
22295                                                      supported clock range is 10MHz to 63MHz. 11xx xxxxb Not
22296                                                      supported 0011 1111b 63MHz 0000 0010b 2MHz 0000 0001b 1MHz
22297                                                      0000 0000b Get information via another method (2) 8-bit
22298                                                      Base Clock Frequency This mode is supported by the Host
22299                                                      Controller Version 3.00.Unit values are 1MHz. The supported
22300                                                      clock range is 10MHz to 255MHz. FFh 255MHz 02h 2MHz 01h
22301                                                      1MH                                                                       */
22302       __IOM uint32_t MAXBLKLEN  : 2;            /*!< [17..16] This value indicates the maximum block size that the
22303                                                      HD can read and write to the buffer in the HC. The buffer
22304                                                      shall transfer this block size without wait cycles. Three
22305                                                      sizes can be defined as indicated below.                                  */
22306       __IOM uint32_t EXTMEDIA   : 1;            /*!< [18..18] This bit indicates whether the Host Controller is capable
22307                                                      of using 8-bit bus width mode. This bit is not effective
22308                                                      when Slot Type is set to 10b. In this case, refer to Bus
22309                                                      Width Preset in the Shared Bus resister. Supported                        */
22310       __IOM uint32_t ADMA2      : 1;            /*!< [19..19] Desc                                                             */
22311             uint32_t            : 1;
22312       __IOM uint32_t HIGHSPEED  : 1;            /*!< [21..21] This bit indicates whether the HC and the Host System
22313                                                      support High Speed mode and they can supply SD Clock frequency
22314                                                      from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC).                  */
22315       __IOM uint32_t SDMA       : 1;            /*!< [22..22] This bit indicates whether the HC is capable of using
22316                                                      DMA to transfer data between system memory and the HC directly.           */
22317       __IOM uint32_t SUSPRES    : 1;            /*!< [23..23] This bit indicates whether the HC supports Suspend
22318                                                      / Resume functionality. If this bit is 0, the Suspend and
22319                                                      Resume mechanism are not supported and the HD shall not
22320                                                      issue either Suspend / Resume commands.                                   */
22321       __IOM uint32_t VOLT33V    : 1;            /*!< [24..24] Desc                                                             */
22322       __IOM uint32_t VOLT30V    : 1;            /*!< [25..25] Voltage support 3.0v                                             */
22323       __IOM uint32_t VOLT18V    : 1;            /*!< [26..26] Voltage support 1.8v                                             */
22324             uint32_t            : 1;
22325       __IOM uint32_t SYSBUS64   : 1;            /*!< [28..28] Desc                                                             */
22326       __IOM uint32_t ASYNCINT   : 1;            /*!< [29..29] Refer to SDIO Specification Version 3.00 about asynchronous
22327                                                      interrupt.                                                                */
22328       __IOM uint32_t SLOTTYPE   : 2;            /*!< [31..30] This field indicates usage of a slot by a specific
22329                                                      Host System. (A host controller register set is defined
22330                                                      per slot.) Embedded slot for one device (01b) means that
22331                                                      only one non-removable device is connected to a SD bus
22332                                                      slot. Shared Bus Slot (10b) can be set if Host Controller
22333                                                      supports Shared Bus Control register. The Standard Host
22334                                                      Driver controls only a removable card or one embedded device
22335                                                      is connected to a SD bus slot. If a slot is configured
22336                                                      for shared bus (10b), the Standard Host Driver does not
22337                                                      contro                                                                    */
22338     } CAPABILITIES0_b;
22339   } ;
22340 
22341   union {
22342     __IOM uint32_t CAPABILITIES1;               /*!< (@ 0x00000044) Capabilities                                               */
22343 
22344     struct {
22345       __IOM uint32_t SDR50      : 1;            /*!< [0..0] 1- SDR50 is Supported                                              */
22346       __IOM uint32_t SDR104     : 1;            /*!< [1..1] 1- SDR104 is Supported                                             */
22347       __IOM uint32_t DDR50      : 1;            /*!< [2..2] DDR50 field description needed here.                               */
22348             uint32_t            : 1;
22349       __IOM uint32_t TYPEA      : 1;            /*!< [4..4] This bit indicates support of Driver Type A for 1.8 Signaling.     */
22350       __IOM uint32_t TYPEC      : 1;            /*!< [5..5] This bit indicates support of Driver Type C for 1.8 Signaling.     */
22351       __IOM uint32_t TYPED      : 1;            /*!< [6..6] Reserved This bit indicates support of Driver Type D
22352                                                      for 1.8 Signaling.                                                        */
22353             uint32_t            : 1;
22354       __IOM uint32_t RETUNINGTMRCNT : 4;        /*!< [11..8] This field indicates an initial value of the Re-Tuning
22355                                                      Timer for Re-Tuning Mode 1 to 3. 0h - Get information via
22356                                                      other source.                                                             */
22357             uint32_t            : 1;
22358       __IOM uint32_t TUNINGSDR50 : 1;           /*!< [13..13] If this bit is set to 1, this Host Controller requires
22359                                                      tuning to operate SDR50. (Tuning is always required to
22360                                                      operate SDR104.)                                                          */
22361       __IOM uint32_t RETUNINGMODES : 2;         /*!< [15..14] This field defines the re-tuning capability of a Host
22362                                                      Controller and how to manage the data transfer length and
22363                                                      a Re-Tuning Timer by the Host Driver There are two re-tuning
22364                                                      timings: Re-Tuning Request and expiration of a Re-Tuning
22365                                                      Timer. By receiving either timing, the Host Driver executes
22366                                                      the re-tuning procedure just before a next command issue                  */
22367       __IOM uint32_t CLKMULT    : 8;            /*!< [23..16] This field indicates clock multiplier value of programmable
22368                                                      clock generator. Refer to Clock Control register. Setting
22369                                                      00h means that Host Controller does not support programmable
22370                                                      clock generator. The multiplier is (CLKMULT+1).                           */
22371       __IOM uint32_t SPIMODE    : 1;            /*!< [24..24] Spi mode                                                         */
22372       __IOM uint32_t SPIBLOCKMODE : 1;          /*!< [25..25] Spi block mode                                                   */
22373             uint32_t            : 6;
22374     } CAPABILITIES1_b;
22375   } ;
22376 
22377   union {
22378     __IOM uint32_t MAXIMUM0;                    /*!< (@ 0x00000048) Maximum current capabilities                               */
22379 
22380     struct {
22381       __IOM uint32_t ALLBITSRSVD : 32;          /*!< [31..0] The entire 32-bits of this register are reserved, do
22382                                                      not read or write.                                                        */
22383     } MAXIMUM0_b;
22384   } ;
22385 
22386   union {
22387     __IOM uint32_t MAXIMUM1;                    /*!< (@ 0x0000004C) Maximum current capabilities                               */
22388 
22389     struct {
22390       __IOM uint32_t MAXCURR33V : 8;            /*!< [7..0] Maximum Current for 3.3V. The current value is specified
22391                                                      as MAXCURR18V * 4mA. Some example enums follow:                           */
22392       __IOM uint32_t MAXCURR30V : 8;            /*!< [15..8] Maximum Current for 3.0V. The current value is specified
22393                                                      as MAXCURR18V * 4mA. Some example enums follow:                           */
22394       __IOM uint32_t MAXCURR18V : 8;            /*!< [23..16] Maximum Current for 1.8V. The current value is specified
22395                                                      as MAXCURR18V * 4mA. Some example enums follow:                           */
22396             uint32_t            : 8;
22397     } MAXIMUM1_b;
22398   } ;
22399 
22400   union {
22401     __IOM uint32_t FORCE;                       /*!< (@ 0x00000050) Force event register for error interrupt status            */
22402 
22403     struct {
22404       __IOM uint32_t FORCEACMD12NOT : 1;        /*!< [0..0] Description                                                        */
22405       __IOM uint32_t FORCEACMDTOERR : 1;        /*!< [1..1] Description                                                        */
22406       __IOM uint32_t FORCEACMDCRCERR : 1;       /*!< [2..2] Description                                                        */
22407       __IOM uint32_t FORCEACMDENDERR : 1;       /*!< [3..3] Description                                                        */
22408       __IOM uint32_t FORCEACMDIDXERR : 1;       /*!< [4..4] Desc                                                               */
22409             uint32_t            : 2;
22410       __IOM uint32_t FORCEACMDISSUEDERR : 1;    /*!< [7..7] 1 - Interrupt is generated                                         */
22411             uint32_t            : 8;
22412       __IOM uint32_t FORCECMDTOERR : 1;         /*!< [16..16] Force Event for Command Timeout Error                            */
22413       __IOM uint32_t FORCECMDCRCERR : 1;        /*!< [17..17] Force Event for Command CRC Error                                */
22414       __IOM uint32_t FORCECMDENDERR : 1;        /*!< [18..18] Force Event for Command End Bit Error                            */
22415       __IOM uint32_t FORCECMDIDXERR : 1;        /*!< [19..19] Force Event for Command Index Error                              */
22416       __IOM uint32_t FORCEDATATOERR : 1;        /*!< [20..20] Force Event for Data Timeout Error                               */
22417       __IOM uint32_t FORCEDATACRCERR : 1;       /*!< [21..21] Force Event for Data CRC Error                                   */
22418       __IOM uint32_t FORCEDATAENDERR : 1;       /*!< [22..22] Force Event for Data End Bit Error                               */
22419       __IOM uint32_t FORCECURRLIMITERR : 1;     /*!< [23..23] Force Event for Current Limit Error                              */
22420       __IOM uint32_t FORCEACMDERR : 1;          /*!< [24..24] Force Event for Auto CMD Error                                   */
22421       __IOM uint32_t FORCEADMAERR : 1;          /*!< [25..25] Force event for ADMA error                                       */
22422             uint32_t            : 6;
22423     } FORCE_b;
22424   } ;
22425 
22426   union {
22427     __IOM uint32_t ADMA;                        /*!< (@ 0x00000054) ADMA error status                                          */
22428 
22429     struct {
22430       __IOM uint32_t ADMAERRORSTATE : 2;        /*!< [1..0] This field indicates the state of ADMA when error is
22431                                                      occurred during ADMA data transfer. This field never indicates
22432                                                      10 because ADMA never stops in this state. D01 - D00 :
22433                                                      ADMA Error State when error occurred Contents of SYS_SDR
22434                                                      register                                                                  */
22435       __IOM uint32_t ADMALENMISMATCHERR : 1;    /*!< [2..2] This error occurs in the following 2 cases. While Block
22436                                                      Count Enable being set, the total data length specified
22437                                                      by the Descriptor table is different from that specified
22438                                                      by the Block Count and Block Length. Total data length
22439                                                      can not be divided by the block length.                                   */
22440             uint32_t            : 29;
22441     } ADMA_b;
22442   } ;
22443 
22444   union {
22445     __IOM uint32_t ADMALOWD;                    /*!< (@ 0x00000058) ADMA system address [31:0]                                 */
22446 
22447     struct {
22448       __IOM uint32_t LOWD       : 32;           /*!< [31..0] This register holds byte address of executing command
22449                                                      of the Descriptor table. 32-bit Address Descriptor uses
22450                                                      lower 32bit of this register. At the start of ADMA, the
22451                                                      Host Driver shall set start address of the Descriptor table.
22452                                                      The ADMA increments this register address, which points
22453                                                      to next line, when every fetching a Descriptor line. When
22454                                                      the ADMA Error Interrupt is generated, this register shall
22455                                                      hold valid Descriptor address depending on the ADMA state.
22456                                                      The Host Driver shall program Descriptor Table on 32                      */
22457     } ADMALOWD_b;
22458   } ;
22459 
22460   union {
22461     __IOM uint32_t ADMAHIWD;                    /*!< (@ 0x0000005C) ADMA system address [63:0]                                 */
22462 
22463     struct {
22464       __IOM uint32_t HIWD       : 32;           /*!< [31..0] This register holds byte address of executing command
22465                                                      of the Descriptor table. 32-bit Address Descriptor uses
22466                                                      lower 32bit of this register. At the start of ADMA, the
22467                                                      Host Driver shall set start address of the Descriptor table.
22468                                                      The ADMA increments this register address, which points
22469                                                      to next line, when every fetching a Descriptor line. When
22470                                                      the ADMA Error Interrupt is generated, this register shall
22471                                                      hold valid Descriptor address depending on the ADMA state.
22472                                                      The Host Driver shall program Descriptor Table on 32                      */
22473     } ADMAHIWD_b;
22474   } ;
22475 
22476   union {
22477     __IOM uint32_t PRESET0;                     /*!< (@ 0x00000060) Preset Value initialization and default speed              */
22478 
22479     struct {
22480       __IOM uint32_t HISPSDCLKFREQSEL : 10;     /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22481                                                      the Clock Control Register is described by a host system.
22482                                                      When Host Controller supports shared bus, a set of Preset
22483                                                      Value registers for each device required and the registers
22484                                                      location are duplicated to the offset 06Fh-060h. A set
22485                                                      of Preset Value registers can be accessible by selecting
22486                                                      Clock Pin Select in the Shared Bus Control register                       */
22487       __IOM uint32_t HISPCLKGENSEL : 1;         /*!< [10..10] This bit is effective when Host Controller supports
22488                                                      programmable clock generator.                                             */
22489             uint32_t            : 3;
22490       __IOM uint32_t HISPDRVRSTRSEL : 2;        /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22491                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22492       __IOM uint32_t DEFSPSDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22493                                                      the Clock Control Register is described by a host system.
22494                                                      When Host Controller supports shared bus, a set of Preset
22495                                                      Value registers for each device required and the registers
22496                                                      location are duplicated to the offset 06Fh-060h. A set
22497                                                      of Preset Value registers can be accessible by selecting
22498                                                      Clock Pin Select in the Shared Bus Control register                       */
22499       __IOM uint32_t DEFSPCLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22500                                                      programmable clock generator.                                             */
22501             uint32_t            : 3;
22502       __IOM uint32_t DEFSPDRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22503                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22504     } PRESET0_b;
22505   } ;
22506 
22507   union {
22508     __IOM uint32_t PRESET1;                     /*!< (@ 0x00000064) Preset Value for high speed and SDR12                      */
22509 
22510     struct {
22511       __IOM uint32_t HSSDCLKFREQSEL : 10;       /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22512                                                      the Clock Control Register is described by a host system.
22513                                                      When Host Controller supports shared bus, a set of Preset
22514                                                      Value registers for each device required and the registers
22515                                                      location are duplicated to the offset 06Fh-060h. A set
22516                                                      of Preset Value registers can be accessible by selecting
22517                                                      Clock Pin Select in the Shared Bus Control register                       */
22518       __IOM uint32_t HSCLKGENSEL : 1;           /*!< [10..10] This bit is effective when Host Controller supports
22519                                                      programmable clock generator.                                             */
22520             uint32_t            : 3;
22521       __IOM uint32_t HSDRVRSTRSEL : 2;          /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22522                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22523       __IOM uint32_t SDR12SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22524                                                      the Clock Control Register is described by a host system.
22525                                                      When Host Controller supports shared bus, a set of Preset
22526                                                      Value registers for each device required and the registers
22527                                                      location are duplicated to the offset 06Fh-060h. A set
22528                                                      of Preset Value registers can be accessible by selecting
22529                                                      Clock Pin Select in the Shared Bus Control register                       */
22530       __IOM uint32_t SDR12CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22531                                                      programmable clock generator.                                             */
22532             uint32_t            : 3;
22533       __IOM uint32_t SDR12DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22534                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22535     } PRESET1_b;
22536   } ;
22537 
22538   union {
22539     __IOM uint32_t PRESET2;                     /*!< (@ 0x00000068) Preset Value for SDR25 and SDR50                           */
22540 
22541     struct {
22542       __IOM uint32_t SDR25SDCLKFREQSEL : 10;    /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22543                                                      the Clock Control Register is described by a host system.
22544                                                      When Host Controller supports shared bus, a set of Preset
22545                                                      Value registers for each device required and the registers
22546                                                      location are duplicated to the offset 06Fh-060h. A set
22547                                                      of Preset Value registers can be accessible by selecting
22548                                                      Clock Pin Select in the Shared Bus Control register                       */
22549       __IOM uint32_t SDR25CLKGENSEL : 1;        /*!< [10..10] This bit is effective when Host Controller supports
22550                                                      programmable clock generator.                                             */
22551             uint32_t            : 3;
22552       __IOM uint32_t SDR25DRVRSTRSEL : 2;       /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22553                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22554       __IOM uint32_t SDR50SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22555                                                      the Clock Control Register is described by a host system.
22556                                                      When Host Controller supports shared bus, a set of Preset
22557                                                      Value registers for each device required and the registers
22558                                                      location are duplicated to the offset 06Fh-060h. A set
22559                                                      of Preset Value registers can be accessible by selecting
22560                                                      Clock Pin Select in the Shared Bus Control register                       */
22561       __IOM uint32_t SDR50CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22562                                                      programmable clock generator.                                             */
22563             uint32_t            : 3;
22564       __IOM uint32_t SDR50DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22565                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22566     } PRESET2_b;
22567   } ;
22568 
22569   union {
22570     __IOM uint32_t PRESET3;                     /*!< (@ 0x0000006C) Preset Value for SDR104 and DDR50                          */
22571 
22572     struct {
22573       __IOM uint32_t SDR104SDCLKFREQSEL : 10;   /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22574                                                      the Clock Control Register is described by a host system.
22575                                                      When Host Controller supports shared bus, a set of Preset
22576                                                      Value registers for each device required and the registers
22577                                                      location are duplicated to the offset 06Fh-060h. A set
22578                                                      of Preset Value registers can be accessible by selecting
22579                                                      Clock Pin Select in the Shared Bus Control register                       */
22580       __IOM uint32_t SDR104CLKGENSEL : 1;       /*!< [10..10] This bit is effective when Host Controller supports
22581                                                      programmable clock generator.                                             */
22582             uint32_t            : 3;
22583       __IOM uint32_t SDR104DRVRSTRSEL : 2;      /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22584                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22585       __IOM uint32_t DDR50SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22586                                                      the Clock Control Register is described by a host system.
22587                                                      When Host Controller supports shared bus, a set of Preset
22588                                                      Value registers for each device required and the registers
22589                                                      location are duplicated to the offset 06Fh-060h. A set
22590                                                      of Preset Value registers can be accessible by selecting
22591                                                      Clock Pin Select in the Shared Bus Control register                       */
22592       __IOM uint32_t DDR50CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22593                                                      programmable clock generator.                                             */
22594             uint32_t            : 3;
22595       __IOM uint32_t DDR50DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22596                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22597     } PRESET3_b;
22598   } ;
22599 
22600   union {
22601     __IOM uint32_t BOOTTOCTRL;                  /*!< (@ 0x00000070) Boot Data Timeout control                                  */
22602 
22603     struct {
22604       __IOM uint32_t BOOTDATATO : 32;           /*!< [31..0] This value determines the interval by which DAT line
22605                                                      time-outs are detected during boot operation for eMMC card.
22606                                                      The value is in number of sd clock.                                       */
22607     } BOOTTOCTRL_b;
22608   } ;
22609   __IM  uint32_t  RESERVED;
22610 
22611   union {
22612     __IOM uint32_t VENDOR;                      /*!< (@ 0x00000078) Vendor                                                     */
22613 
22614     struct {
22615       __IOM uint32_t GATESDCLKEN : 1;           /*!< [0..0] If this bit is 0, SD_CLK to card will not be gated automatically,
22616                                                      when there is no transfer. If this bit set to 1, SD_CLK
22617                                                      to card will be gated automatically,when there is no transfer.            */
22618       __IOM uint32_t DLYDIS     : 1;            /*!< [1..1] Enable/disable the hardware delay added to the sampling
22619                                                      of cmd_in and data_in.                                                    */
22620             uint32_t            : 30;
22621     } VENDOR_b;
22622   } ;
22623   __IM  uint32_t  RESERVED1[32];
22624 
22625   union {
22626     __IOM uint32_t SLOTSTAT;                    /*!< (@ 0x000000FC) Slot interrupt status                                      */
22627 
22628     struct {
22629       __IOM uint32_t INTSLOT0   : 1;            /*!< [0..0] This status bit indicates the OR of Interrupt signal
22630                                                      and Wakeup signal for slot                                                */
22631             uint32_t            : 15;
22632       __IOM uint32_t SPECVER    : 8;            /*!< [23..16] The Host Controller Version Number is set to 0x02 (SD
22633                                                      Host Specification Version 3.00).                                         */
22634       __IOM uint32_t VENDORVER  : 8;            /*!< [31..24] The Vendor Version Number is set to 0x10 (1.0)                   */
22635     } SLOTSTAT_b;
22636   } ;
22637 } SDIO_Type;                                    /*!< Size = 256 (0x100)                                                        */
22638 
22639 
22640 
22641 /* =========================================================================================================================== */
22642 /* ================                                         SECURITY                                          ================ */
22643 /* =========================================================================================================================== */
22644 
22645 
22646 /**
22647   * @brief Security Interfaces (SECURITY)
22648   */
22649 
22650 typedef struct {                                /*!< (@ 0x40030000) SECURITY Structure                                         */
22651 
22652   union {
22653     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Control                                                    */
22654 
22655     struct {
22656       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Function Enable. Software should set the ENABLE bit to
22657                                                      initiate a CRC operation. Hardware will clear the ENABLE
22658                                                      bit upon completion.                                                      */
22659             uint32_t            : 3;
22660       __IOM uint32_t FUNCTION   : 4;            /*!< [7..4] Function Select                                                    */
22661             uint32_t            : 23;
22662       __IOM uint32_t CRCERROR   : 1;            /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during
22663                                                      a CRC operation. Cleared when CTRL register is written
22664                                                      (with any value). Usually indicates an invalid address
22665                                                      range.                                                                    */
22666     } CTRL_b;
22667   } ;
22668   __IM  uint32_t  RESERVED[3];
22669 
22670   union {
22671     __IOM uint32_t SRCADDR;                     /*!< (@ 0x00000010) Source Addresss                                            */
22672 
22673     struct {
22674       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Source Buffer Address. Address may be byte aligned,
22675                                                      but the length must be a multiple of 4 bits.                              */
22676     } SRCADDR_b;
22677   } ;
22678   __IM  uint32_t  RESERVED1[3];
22679 
22680   union {
22681     __IOM uint32_t LEN;                         /*!< (@ 0x00000020) Length                                                     */
22682 
22683     struct {
22684             uint32_t            : 2;
22685       __IOM uint32_t LEN        : 22;           /*!< [23..2] Buffer size (bottom two bits assumed to be zero to ensure
22686                                                      a multiple of 4 bytes)                                                    */
22687             uint32_t            : 8;
22688     } LEN_b;
22689   } ;
22690   __IM  uint32_t  RESERVED2[3];
22691 
22692   union {
22693     __IOM uint32_t RESULT;                      /*!< (@ 0x00000030) CRC Seed/Result                                            */
22694 
22695     struct {
22696       __IOM uint32_t CRC        : 32;           /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF
22697                                                      before starting a CRC operation (unless the CRC is continued
22698                                                      from a previous operation).                                               */
22699     } RESULT_b;
22700   } ;
22701   __IM  uint32_t  RESERVED3[17];
22702 
22703   union {
22704     __IOM uint32_t LOCKCTRL;                    /*!< (@ 0x00000078) LOCK Control                                               */
22705 
22706     struct {
22707       __IOM uint32_t SELECT     : 8;            /*!< [7..0] LOCK Function Select register.                                     */
22708             uint32_t            : 24;
22709     } LOCKCTRL_b;
22710   } ;
22711 
22712   union {
22713     __IOM uint32_t LOCKSTAT;                    /*!< (@ 0x0000007C) LOCK Status                                                */
22714 
22715     struct {
22716       __IOM uint32_t STATUS     : 32;           /*!< [31..0] LOCK Status register. This register is a bitmask for
22717                                                      which resources are currently unlocked. These bits are
22718                                                      one-hot per resource.                                                     */
22719     } LOCKSTAT_b;
22720   } ;
22721 
22722   union {
22723     __IOM uint32_t KEY0;                        /*!< (@ 0x00000080) Key0                                                       */
22724 
22725     struct {
22726       __IOM uint32_t KEY0       : 32;           /*!< [31..0] Bits [31:0] of the 128-bit key should be written to
22727                                                      this register. To protect key values, the register always
22728                                                      returns 0x00000000.                                                       */
22729     } KEY0_b;
22730   } ;
22731 
22732   union {
22733     __IOM uint32_t KEY1;                        /*!< (@ 0x00000084) Key1                                                       */
22734 
22735     struct {
22736       __IOM uint32_t KEY1       : 32;           /*!< [31..0] Bits [63:32] of the 128-bit key should be written to
22737                                                      this register. To protect key values, the register always
22738                                                      returns 0x00000000.                                                       */
22739     } KEY1_b;
22740   } ;
22741 
22742   union {
22743     __IOM uint32_t KEY2;                        /*!< (@ 0x00000088) Key2                                                       */
22744 
22745     struct {
22746       __IOM uint32_t KEY2       : 32;           /*!< [31..0] Bits [95:64] of the 128-bit key should be written to
22747                                                      this register. To protect key values, the register always
22748                                                      returns 0x00000000.                                                       */
22749     } KEY2_b;
22750   } ;
22751 
22752   union {
22753     __IOM uint32_t KEY3;                        /*!< (@ 0x0000008C) Key3                                                       */
22754 
22755     struct {
22756       __IOM uint32_t KEY3       : 32;           /*!< [31..0] Bits [127:96] of the 128-bit key should be written to
22757                                                      this register. To protect key values, the register always
22758                                                      returns 0x00000000.                                                       */
22759     } KEY3_b;
22760   } ;
22761 } SECURITY_Type;                                /*!< Size = 144 (0x90)                                                         */
22762 
22763 
22764 
22765 /* =========================================================================================================================== */
22766 /* ================                                          STIMER                                           ================ */
22767 /* =========================================================================================================================== */
22768 
22769 
22770 /**
22771   * @brief Counter/Timer (STIMER)
22772   */
22773 
22774 typedef struct {                                /*!< (@ 0x40008800) STIMER Structure                                           */
22775 
22776   union {
22777     __IOM uint32_t STCFG;                       /*!< (@ 0x00000000) The STIMER Configuration Register contains the
22778                                                                     software control for selecting the clock
22779                                                                     divider and source feeding the system timer.               */
22780 
22781     struct {
22782       __IOM uint32_t CLKSEL     : 4;            /*!< [3..0] Selects an appropriate clock source and divider to use
22783                                                      for the System Timer clock.                                               */
22784             uint32_t            : 4;
22785       __IOM uint32_t COMPAREAEN : 1;            /*!< [8..8] Selects whether compare is enabled for the corresponding
22786                                                      SCMPR register. If compare is enabled, the interrupt status
22787                                                      is set once the comparision is met.                                       */
22788       __IOM uint32_t COMPAREBEN : 1;            /*!< [9..9] Selects whether compare is enabled for the corresponding
22789                                                      SCMPR register. If compare is enabled, the interrupt status
22790                                                      is set once the comparision is met.                                       */
22791       __IOM uint32_t COMPARECEN : 1;            /*!< [10..10] Selects whether compare is enabled for the corresponding
22792                                                      SCMPR register. If compare is enabled, the interrupt status
22793                                                      is set once the comparision is met.                                       */
22794       __IOM uint32_t COMPAREDEN : 1;            /*!< [11..11] Selects whether compare is enabled for the corresponding
22795                                                      SCMPR register. If compare is enabled, the interrupt status
22796                                                      is set once the comparision is met.                                       */
22797       __IOM uint32_t COMPAREEEN : 1;            /*!< [12..12] Selects whether compare is enabled for the corresponding
22798                                                      SCMPR register. If compare is enabled, the interrupt status
22799                                                      is set once the comparision is met.                                       */
22800       __IOM uint32_t COMPAREFEN : 1;            /*!< [13..13] Selects whether compare is enabled for the corresponding
22801                                                      SCMPR register. If compare is enabled, the interrupt status
22802                                                      is set once the comparision is met.                                       */
22803       __IOM uint32_t COMPAREGEN : 1;            /*!< [14..14] Selects whether compare is enabled for the corresponding
22804                                                      SCMPR register. If compare is enabled, the interrupt status
22805                                                      is set once the comparision is met.                                       */
22806       __IOM uint32_t COMPAREHEN : 1;            /*!< [15..15] Selects whether compare is enabled for the corresponding
22807                                                      SCMPR register. If compare is enabled, the interrupt status
22808                                                      is set once the comparision is met.                                       */
22809             uint32_t            : 14;
22810       __IOM uint32_t CLEAR      : 1;            /*!< [30..30] Set this bit to one to clear the System Timer register.
22811                                                      If this bit is set to '1', the system timer register will
22812                                                      stay cleared. It needs to be set to '0' for the system
22813                                                      timer to start running.                                                   */
22814       __IOM uint32_t FREEZE     : 1;            /*!< [31..31] Set this bit to one to freeze the clock input to the
22815                                                      COUNTER register. Once frozen, the value can be safely
22816                                                      written from the MCU. Unfreeze to resume.                                 */
22817     } STCFG_b;
22818   } ;
22819 
22820   union {
22821     __IOM uint32_t STTMR;                       /*!< (@ 0x00000004) The COUNTER Register contains the running count
22822                                                                     of time as maintained by incrementing for
22823                                                                     every rising clock edge of the clock source
22824                                                                     selected in the configuration register.
22825                                                                     It is this counter value that captured in
22826                                                                     the capture registers and it is this counter
22827                                                                     value that is compared against the various
22828                                                                     compare registers. This register cannot
22829                                                                     be written, but can be cleared to 0 for
22830                                                                     a deterministic value. Use the FREEZE bit
22831                                                                     will stop this counter from incrementing.                  */
22832 
22833     struct {
22834       __IOM uint32_t STTMR      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
22835     } STTMR_b;
22836   } ;
22837   __IM  uint32_t  RESERVED[2];
22838 
22839   union {
22840     __IOM uint32_t SCAPCTRL0;                   /*!< (@ 0x00000010) The STIMER Capture Control Register controls
22841                                                                     each of the 4 capture registers. It selects
22842                                                                     their GPIO pin number for a trigger source,
22843                                                                     enables a capture operation and sets the
22844                                                                     input polarity for the capture. NOTE: 8-bit
22845                                                                     writes can control individual capture registers
22846                                                                     atomically.                                                */
22847 
22848     struct {
22849       __IOM uint32_t STSEL0     : 7;            /*!< [6..0] STIMER Capture 0 Select.                                           */
22850             uint32_t            : 1;
22851       __IOM uint32_t STPOL0     : 1;            /*!< [8..8] STIMER Capture 0 Polarity.                                         */
22852       __IOM uint32_t CAPTURE0   : 1;            /*!< [9..9] Selects whether capture 0 is enabled for the specified
22853                                                      capture register.                                                         */
22854             uint32_t            : 22;
22855     } SCAPCTRL0_b;
22856   } ;
22857 
22858   union {
22859     __IOM uint32_t SCAPCTRL1;                   /*!< (@ 0x00000014) The STIMER Capture Control Register controls
22860                                                                     each of the 4 capture registers. It selects
22861                                                                     their GPIO pin number for a trigger source,
22862                                                                     enables a capture operation and sets the
22863                                                                     input polarity for the capture. NOTE: 8-bit
22864                                                                     writes can control individual capture registers
22865                                                                     atomically.                                                */
22866 
22867     struct {
22868       __IOM uint32_t STSEL1     : 7;            /*!< [6..0] STIMER Capture 1 Select.                                           */
22869             uint32_t            : 1;
22870       __IOM uint32_t STPOL1     : 1;            /*!< [8..8] STIMER Capture 1 Polarity.                                         */
22871       __IOM uint32_t CAPTURE1   : 1;            /*!< [9..9] Selects whether capture 1 is enabled for the specified
22872                                                      capture register.                                                         */
22873             uint32_t            : 22;
22874     } SCAPCTRL1_b;
22875   } ;
22876 
22877   union {
22878     __IOM uint32_t SCAPCTRL2;                   /*!< (@ 0x00000018) The STIMER Capture Control Register controls
22879                                                                     each of the 4 capture registers. It selects
22880                                                                     their GPIO pin number for a trigger source,
22881                                                                     enables a capture operation and sets the
22882                                                                     input polarity for the capture. NOTE: 8-bit
22883                                                                     writes can control individual capture registers
22884                                                                     atomically.                                                */
22885 
22886     struct {
22887       __IOM uint32_t STSEL2     : 7;            /*!< [6..0] STIMER Capture 2 Select.                                           */
22888             uint32_t            : 1;
22889       __IOM uint32_t STPOL2     : 1;            /*!< [8..8] STIMER Capture 2 Polarity.                                         */
22890       __IOM uint32_t CAPTURE2   : 1;            /*!< [9..9] Selects whether capture 2 is enabled for the specified
22891                                                      capture register.                                                         */
22892             uint32_t            : 22;
22893     } SCAPCTRL2_b;
22894   } ;
22895 
22896   union {
22897     __IOM uint32_t SCAPCTRL3;                   /*!< (@ 0x0000001C) The STIMER Capture Control Register controls
22898                                                                     each of the 4 capture registers. It selects
22899                                                                     their GPIO pin number for a trigger source,
22900                                                                     enables a capture operation and sets the
22901                                                                     input polarity for the capture. NOTE: 8-bit
22902                                                                     writes can control individual capture registers
22903                                                                     atomically.                                                */
22904 
22905     struct {
22906       __IOM uint32_t STSEL3     : 7;            /*!< [6..0] STIMER Capture 3 Select.                                           */
22907             uint32_t            : 1;
22908       __IOM uint32_t STPOL3     : 1;            /*!< [8..8] STIMER Capture 3 Polarity.                                         */
22909       __IOM uint32_t CAPTURE3   : 1;            /*!< [9..9] Selects whether capture 3 is enabled for the specified
22910                                                      capture register.                                                         */
22911             uint32_t            : 22;
22912     } SCAPCTRL3_b;
22913   } ;
22914 
22915   union {
22916     __IOM uint32_t SCMPR0;                      /*!< (@ 0x00000020) The VALUE in this bit field is used to compare
22917                                                                     against the VALUE in the COUNTER register.
22918                                                                     If the match criterion in the configuration
22919                                                                     register is met then a corresponding interrupt
22920                                                                     status bit is set. The match criterion is
22921                                                                     defined as COUNTER equal to COMPARE. To
22922                                                                     establish a desired value in this COMPARE
22923                                                                     register, write the number of ticks in the
22924                                                                     future to this register to indicate when
22925                                                                     to interrupt. The hardware does the addition
22926                                                                     to the COUNTER value in the STIMER clock
22927                                                                     domain so that the ma                                      */
22928 
22929     struct {
22930       __IOM uint32_t SCMPR0     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
22931                                                      according to the match criterion, as selected in the COMPARE_A_EN
22932                                                      bit in the REG_CTIMER_STCFG register.                                     */
22933     } SCMPR0_b;
22934   } ;
22935 
22936   union {
22937     __IOM uint32_t SCMPR1;                      /*!< (@ 0x00000024) The VALUE in this bit field is used to compare
22938                                                                     against the VALUE in the COUNTER register.
22939                                                                     If the match criterion in the configuration
22940                                                                     register is met then a corresponding interrupt
22941                                                                     status bit is set. The match criterion is
22942                                                                     defined as COUNTER equal to COMPARE. To
22943                                                                     establish a desired value in this COMPARE
22944                                                                     register, write the number of ticks in the
22945                                                                     future to this register to indicate when
22946                                                                     to interrupt. The hardware does the addition
22947                                                                     to the COUNTER value in the STIMER clock
22948                                                                     domain so that the ma                                      */
22949 
22950     struct {
22951       __IOM uint32_t SCMPR1     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
22952                                                      according to the match criterion, as selected in the COMPARE_A_EN
22953                                                      bit in the REG_CTIMER_STCFG register.                                     */
22954     } SCMPR1_b;
22955   } ;
22956 
22957   union {
22958     __IOM uint32_t SCMPR2;                      /*!< (@ 0x00000028) The VALUE in this bit field is used to compare
22959                                                                     against the VALUE in the COUNTER register.
22960                                                                     If the match criterion in the configuration
22961                                                                     register is met then a corresponding interrupt
22962                                                                     status bit is set. The match criterion is
22963                                                                     defined as COUNTER equal to COMPARE. To
22964                                                                     establish a desired value in this COMPARE
22965                                                                     register, write the number of ticks in the
22966                                                                     future to this register to indicate when
22967                                                                     to interrupt. The hardware does the addition
22968                                                                     to the COUNTER value in the STIMER clock
22969                                                                     domain so that the ma                                      */
22970 
22971     struct {
22972       __IOM uint32_t SCMPR2     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
22973                                                      according to the match criterion, as selected in the COMPARE_A_EN
22974                                                      bit in the REG_CTIMER_STCFG register.                                     */
22975     } SCMPR2_b;
22976   } ;
22977 
22978   union {
22979     __IOM uint32_t SCMPR3;                      /*!< (@ 0x0000002C) The VALUE in this bit field is used to compare
22980                                                                     against the VALUE in the COUNTER register.
22981                                                                     If the match criterion in the configuration
22982                                                                     register is met then a corresponding interrupt
22983                                                                     status bit is set. The match criterion is
22984                                                                     defined as COUNTER equal to COMPARE. To
22985                                                                     establish a desired value in this COMPARE
22986                                                                     register, write the number of ticks in the
22987                                                                     future to this register to indicate when
22988                                                                     to interrupt. The hardware does the addition
22989                                                                     to the COUNTER value in the STIMER clock
22990                                                                     domain so that the ma                                      */
22991 
22992     struct {
22993       __IOM uint32_t SCMPR3     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
22994                                                      according to the match criterion, as selected in the COMPARE_A_EN
22995                                                      bit in the REG_CTIMER_STCFG register.                                     */
22996     } SCMPR3_b;
22997   } ;
22998 
22999   union {
23000     __IOM uint32_t SCMPR4;                      /*!< (@ 0x00000030) The VALUE in this bit field is used to compare
23001                                                                     against the VALUE in the COUNTER register.
23002                                                                     If the match criterion in the configuration
23003                                                                     register is met then a corresponding interrupt
23004                                                                     status bit is set. The match criterion is
23005                                                                     defined as COUNTER equal to COMPARE. To
23006                                                                     establish a desired value in this COMPARE
23007                                                                     register, write the number of ticks in the
23008                                                                     future to this register to indicate when
23009                                                                     to interrupt. The hardware does the addition
23010                                                                     to the COUNTER value in the STIMER clock
23011                                                                     domain so that the ma                                      */
23012 
23013     struct {
23014       __IOM uint32_t SCMPR4     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23015                                                      according to the match criterion, as selected in the COMPARE_A_EN
23016                                                      bit in the REG_CTIMER_STCFG register.                                     */
23017     } SCMPR4_b;
23018   } ;
23019 
23020   union {
23021     __IOM uint32_t SCMPR5;                      /*!< (@ 0x00000034) The VALUE in this bit field is used to compare
23022                                                                     against the VALUE in the COUNTER register.
23023                                                                     If the match criterion in the configuration
23024                                                                     register is met then a corresponding interrupt
23025                                                                     status bit is set. The match criterion is
23026                                                                     defined as COUNTER equal to COMPARE. To
23027                                                                     establish a desired value in this COMPARE
23028                                                                     register, write the number of ticks in the
23029                                                                     future to this register to indicate when
23030                                                                     to interrupt. The hardware does the addition
23031                                                                     to the COUNTER value in the STIMER clock
23032                                                                     domain so that the ma                                      */
23033 
23034     struct {
23035       __IOM uint32_t SCMPR5     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23036                                                      according to the match criterion, as selected in the COMPARE_A_EN
23037                                                      bit in the REG_CTIMER_STCFG register.                                     */
23038     } SCMPR5_b;
23039   } ;
23040 
23041   union {
23042     __IOM uint32_t SCMPR6;                      /*!< (@ 0x00000038) The VALUE in this bit field is used to compare
23043                                                                     against the VALUE in the COUNTER register.
23044                                                                     If the match criterion in the configuration
23045                                                                     register is met then a corresponding interrupt
23046                                                                     status bit is set. The match criterion is
23047                                                                     defined as COUNTER equal to COMPARE. To
23048                                                                     establish a desired value in this COMPARE
23049                                                                     register, write the number of ticks in the
23050                                                                     future to this register to indicate when
23051                                                                     to interrupt. The hardware does the addition
23052                                                                     to the COUNTER value in the STIMER clock
23053                                                                     domain so that the ma                                      */
23054 
23055     struct {
23056       __IOM uint32_t SCMPR6     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23057                                                      according to the match criterion, as selected in the COMPARE_A_EN
23058                                                      bit in the REG_CTIMER_STCFG register.                                     */
23059     } SCMPR6_b;
23060   } ;
23061 
23062   union {
23063     __IOM uint32_t SCMPR7;                      /*!< (@ 0x0000003C) The VALUE in this bit field is used to compare
23064                                                                     against the VALUE in the COUNTER register.
23065                                                                     If the match criterion in the configuration
23066                                                                     register is met then a corresponding interrupt
23067                                                                     status bit is set. The match criterion is
23068                                                                     defined as COUNTER equal to COMPARE. To
23069                                                                     establish a desired value in this COMPARE
23070                                                                     register, write the number of ticks in the
23071                                                                     future to this register to indicate when
23072                                                                     to interrupt. The hardware does the addition
23073                                                                     to the COUNTER value in the STIMER clock
23074                                                                     domain so that the ma                                      */
23075 
23076     struct {
23077       __IOM uint32_t SCMPR7     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23078                                                      according to the match criterion, as selected in the COMPARE_A_EN
23079                                                      bit in the REG_CTIMER_STCFG register.                                     */
23080     } SCMPR7_b;
23081   } ;
23082 
23083   union {
23084     __IOM uint32_t SCAPT0;                      /*!< (@ 0x00000040) The STIMER capture Register 0 captures the VALUE
23085                                                                     in the COUNTER register whenever capture
23086                                                                     condition (event) occurs. This register
23087                                                                     holds a time stamp for the event.                          */
23088 
23089     struct {
23090       __IOM uint32_t SCAPT0     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23091                                                      is copied into this register and the corresponding interrupt
23092                                                      status bit is set.                                                        */
23093     } SCAPT0_b;
23094   } ;
23095 
23096   union {
23097     __IOM uint32_t SCAPT1;                      /*!< (@ 0x00000044) The STIMER capture Register 1 captures the VALUE
23098                                                                     in the COUNTER register whenever capture
23099                                                                     condition (event) occurs. This register
23100                                                                     holds a time stamp for the event.                          */
23101 
23102     struct {
23103       __IOM uint32_t SCAPT1     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23104                                                      is copied into this register and the corresponding interrupt
23105                                                      status bit is set.                                                        */
23106     } SCAPT1_b;
23107   } ;
23108 
23109   union {
23110     __IOM uint32_t SCAPT2;                      /*!< (@ 0x00000048) The STIMER capture Register 2 captures the VALUE
23111                                                                     in the COUNTER register whenever capture
23112                                                                     condition (event) occurs. This register
23113                                                                     holds a time stamp for the event.                          */
23114 
23115     struct {
23116       __IOM uint32_t SCAPT2     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23117                                                      is copied into this register and the corresponding interrupt
23118                                                      status bit is set.                                                        */
23119     } SCAPT2_b;
23120   } ;
23121 
23122   union {
23123     __IOM uint32_t SCAPT3;                      /*!< (@ 0x0000004C) The STIMER capture Register 3 captures the VALUE
23124                                                                     in the COUNTER register whenever capture
23125                                                                     condition (event) occurs. This register
23126                                                                     holds a time stamp for the event.                          */
23127 
23128     struct {
23129       __IOM uint32_t SCAPT3     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23130                                                      is copied into this register and the corresponding interrupt
23131                                                      status bit is set.                                                        */
23132     } SCAPT3_b;
23133   } ;
23134 
23135   union {
23136     __IOM uint32_t SNVR0;                       /*!< (@ 0x00000050) The SNVR0 Register contains a portion of the
23137                                                                     stored epoch offset associated with the
23138                                                                     time in the COUNTER register. This register
23139                                                                     is only reset by POI not by HRESETn. Its
23140                                                                     contents are intended to survive all reset
23141                                                                     level except POI and full power cycles.                    */
23142 
23143     struct {
23144       __IOM uint32_t SNVR0      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
23145     } SNVR0_b;
23146   } ;
23147 
23148   union {
23149     __IOM uint32_t SNVR1;                       /*!< (@ 0x00000054) The SNVR1 Register contains a portion of the
23150                                                                     stored epoch offset associated with the
23151                                                                     time in the COUNTER register. This register
23152                                                                     is only reset by POI not by HRESETn. Its
23153                                                                     contents are intended to survive all reset
23154                                                                     level except POI and full power cycles.                    */
23155 
23156     struct {
23157       __IOM uint32_t SNVR1      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
23158     } SNVR1_b;
23159   } ;
23160 
23161   union {
23162     __IOM uint32_t SNVR2;                       /*!< (@ 0x00000058) The SNVR2 Register contains a portion of the
23163                                                                     stored epoch offset associated with the
23164                                                                     time in the COUNTER register. This register
23165                                                                     is only reset by POI not by HRESETn. Its
23166                                                                     contents are intended to survive all reset
23167                                                                     level except POI and full power cycles.                    */
23168 
23169     struct {
23170       __IOM uint32_t SNVR2      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
23171     } SNVR2_b;
23172   } ;
23173   __IM  uint32_t  RESERVED1[41];
23174 
23175   union {
23176     __IOM uint32_t STMINTEN;                    /*!< (@ 0x00000100) Set bits in this register to allow this module
23177                                                                     to generate the corresponding interrupt.                   */
23178 
23179     struct {
23180       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23181                                                      A.                                                                        */
23182       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23183                                                      B.                                                                        */
23184       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23185                                                      C.                                                                        */
23186       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23187                                                      D.                                                                        */
23188       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23189                                                      E.                                                                        */
23190       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23191                                                      F.                                                                        */
23192       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23193                                                      G.                                                                        */
23194       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23195                                                      H.                                                                        */
23196       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23197       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23198       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23199       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23200       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23201             uint32_t            : 19;
23202     } STMINTEN_b;
23203   } ;
23204 
23205   union {
23206     __IOM uint32_t STMINTSTAT;                  /*!< (@ 0x00000104) Read bits from this register to discover the
23207                                                                     cause of a recent interrupt.                               */
23208 
23209     struct {
23210       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23211                                                      A.                                                                        */
23212       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23213                                                      B.                                                                        */
23214       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23215                                                      C.                                                                        */
23216       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23217                                                      D.                                                                        */
23218       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23219                                                      E.                                                                        */
23220       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23221                                                      F.                                                                        */
23222       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23223                                                      G.                                                                        */
23224       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23225                                                      H.                                                                        */
23226       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23227       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23228       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23229       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23230       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23231             uint32_t            : 19;
23232     } STMINTSTAT_b;
23233   } ;
23234 
23235   union {
23236     __IOM uint32_t STMINTCLR;                   /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
23237                                                                     the interrupt status associated with that
23238                                                                     bit.                                                       */
23239 
23240     struct {
23241       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23242                                                      A.                                                                        */
23243       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23244                                                      B.                                                                        */
23245       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23246                                                      C.                                                                        */
23247       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23248                                                      D.                                                                        */
23249       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23250                                                      E.                                                                        */
23251       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23252                                                      F.                                                                        */
23253       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23254                                                      G.                                                                        */
23255       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23256                                                      H.                                                                        */
23257       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23258       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23259       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23260       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23261       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23262             uint32_t            : 19;
23263     } STMINTCLR_b;
23264   } ;
23265 
23266   union {
23267     __IOM uint32_t STMINTSET;                   /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
23268                                                                     generate an interrupt from this module.
23269                                                                     (Generally used for testing purposes).                     */
23270 
23271     struct {
23272       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23273                                                      A.                                                                        */
23274       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23275                                                      B.                                                                        */
23276       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23277                                                      C.                                                                        */
23278       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23279                                                      D.                                                                        */
23280       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23281                                                      E.                                                                        */
23282       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23283                                                      F.                                                                        */
23284       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23285                                                      G.                                                                        */
23286       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23287                                                      H.                                                                        */
23288       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23289       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23290       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23291       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23292       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23293             uint32_t            : 19;
23294     } STMINTSET_b;
23295   } ;
23296 } STIMER_Type;                                  /*!< Size = 272 (0x110)                                                        */
23297 
23298 
23299 
23300 /* =========================================================================================================================== */
23301 /* ================                                           TIMER                                           ================ */
23302 /* =========================================================================================================================== */
23303 
23304 
23305 /**
23306   * @brief Counter/Timer (TIMER)
23307   */
23308 
23309 typedef struct {                                /*!< (@ 0x40008000) TIMER Structure                                            */
23310 
23311   union {
23312     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) General Timer Controls                                     */
23313 
23314     struct {
23315             uint32_t            : 31;
23316       __IOM uint32_t RESET      : 1;            /*!< [31..31] Write to 1 to reset all timers (self-clearing)                   */
23317     } CTRL_b;
23318   } ;
23319 
23320   union {
23321     __IOM uint32_t STATUS;                      /*!< (@ 0x00000004) General Timer status                                       */
23322 
23323     struct {
23324       __IOM uint32_t ACTIVE     : 16;           /*!< [15..0] Indicates which timers are currnetly active (enabled)             */
23325       __IOM uint32_t NTIMERS    : 5;            /*!< [20..16] Indicates the number of timer blocks present in the
23326                                                      design                                                                    */
23327             uint32_t            : 11;
23328     } STATUS_b;
23329   } ;
23330   __IM  uint32_t  RESERVED[2];
23331 
23332   union {
23333     __IOM uint32_t GLOBEN;                      /*!< (@ 0x00000010) Alternate enables for all TIMERs.                          */
23334 
23335     struct {
23336       __IOM uint32_t ENB0       : 1;            /*!< [0..0] Alternate enable for timer 0                                       */
23337       __IOM uint32_t ENB1       : 1;            /*!< [1..1] Alternate enable for timer 1                                       */
23338       __IOM uint32_t ENB2       : 1;            /*!< [2..2] Alternate enable for timer 2                                       */
23339       __IOM uint32_t ENB3       : 1;            /*!< [3..3] Alternate enable for timer 3                                       */
23340       __IOM uint32_t ENB4       : 1;            /*!< [4..4] Alternate enable for timer 4                                       */
23341       __IOM uint32_t ENB5       : 1;            /*!< [5..5] Alternate enable for timer 5                                       */
23342       __IOM uint32_t ENB6       : 1;            /*!< [6..6] Alternate enable for timer 6                                       */
23343       __IOM uint32_t ENB7       : 1;            /*!< [7..7] Alternate enable for timer 7                                       */
23344       __IOM uint32_t ENB8       : 1;            /*!< [8..8] Alternate enable for timer 8                                       */
23345       __IOM uint32_t ENB9       : 1;            /*!< [9..9] Alternate enable for timer 9                                       */
23346       __IOM uint32_t ENB10      : 1;            /*!< [10..10] Alternate enable for timer 10                                    */
23347       __IOM uint32_t ENB11      : 1;            /*!< [11..11] Alternate enable for timer 11                                    */
23348       __IOM uint32_t ENB12      : 1;            /*!< [12..12] Alternate enable for timer 12                                    */
23349       __IOM uint32_t ENB13      : 1;            /*!< [13..13] Alternate enable for timer 13                                    */
23350       __IOM uint32_t ENB14      : 1;            /*!< [14..14] Alternate enable for timer 14                                    */
23351       __IOM uint32_t ENB15      : 1;            /*!< [15..15] Alternate enable for timer 15                                    */
23352             uint32_t            : 13;
23353       __IOM uint32_t ENABLEALLINPUTS : 1;       /*!< [29..29] Override to enable all GPIO inputs                               */
23354       __IOM uint32_t AUDADCEN   : 1;            /*!< [30..30] Audio ADC controls enable for timer 6                            */
23355       __IOM uint32_t ADCEN      : 1;            /*!< [31..31] ADC controls enable for timer 7                                  */
23356     } GLOBEN_b;
23357   } ;
23358   __IM  uint32_t  RESERVED1[19];
23359 
23360   union {
23361     __IOM uint32_t INTEN;                       /*!< (@ 0x00000060) Set bits in this register to allow this module
23362                                                                     to generate the corresponding interrupt.                   */
23363 
23364     struct {
23365       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23366       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23367       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23368       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23369       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23370       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23371       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23372       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23373       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23374       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23375       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23376       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23377       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23378       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23379       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23380       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23381       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23382       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23383       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23384       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23385       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23386       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23387       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23388       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23389       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23390       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23391       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23392       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23393       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23394       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23395       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23396       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23397     } INTEN_b;
23398   } ;
23399 
23400   union {
23401     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000064) Read bits from this register to discover the
23402                                                                     cause of a recent interrupt.                               */
23403 
23404     struct {
23405       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23406       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23407       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23408       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23409       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23410       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23411       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23412       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23413       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23414       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23415       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23416       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23417       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23418       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23419       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23420       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23421       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23422       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23423       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23424       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23425       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23426       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23427       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23428       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23429       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23430       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23431       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23432       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23433       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23434       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23435       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23436       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23437     } INTSTAT_b;
23438   } ;
23439 
23440   union {
23441     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000068) Write a 1 to a bit in this register to clear
23442                                                                     the interrupt status associated with that
23443                                                                     bit.                                                       */
23444 
23445     struct {
23446       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23447       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23448       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23449       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23450       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23451       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23452       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23453       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23454       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23455       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23456       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23457       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23458       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23459       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23460       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23461       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23462       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23463       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23464       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23465       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23466       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23467       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23468       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23469       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23470       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23471       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23472       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23473       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23474       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23475       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23476       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23477       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23478     } INTCLR_b;
23479   } ;
23480 
23481   union {
23482     __IOM uint32_t INTSET;                      /*!< (@ 0x0000006C) Write a 1 to a bit in this register to instantly
23483                                                                     generate an interrupt from this module.
23484                                                                     (Generally used for testing purposes).                     */
23485 
23486     struct {
23487       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23488       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23489       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23490       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23491       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23492       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23493       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23494       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23495       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23496       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23497       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23498       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23499       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23500       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23501       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23502       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23503       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23504       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23505       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23506       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23507       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23508       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23509       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23510       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23511       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23512       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23513       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23514       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23515       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23516       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23517       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23518       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23519     } INTSET_b;
23520   } ;
23521   __IM  uint32_t  RESERVED2[4];
23522 
23523   union {
23524     __IOM uint32_t OUTCFG0;                     /*!< (@ 0x00000080) Pad output configuration 0.                                */
23525 
23526     struct {
23527       __IOM uint32_t OUTCFG0    : 6;            /*!< [5..0] Pad output 0 configuration                                         */
23528             uint32_t            : 2;
23529       __IOM uint32_t OUTCFG1    : 6;            /*!< [13..8] Pad output 1 configuration                                        */
23530             uint32_t            : 2;
23531       __IOM uint32_t OUTCFG2    : 6;            /*!< [21..16] Pad output 2 configuration                                       */
23532             uint32_t            : 2;
23533       __IOM uint32_t OUTCFG3    : 6;            /*!< [29..24] Pad output 3 configuration                                       */
23534             uint32_t            : 2;
23535     } OUTCFG0_b;
23536   } ;
23537 
23538   union {
23539     __IOM uint32_t OUTCFG1;                     /*!< (@ 0x00000084) Pad output configuration 0.                                */
23540 
23541     struct {
23542       __IOM uint32_t OUTCFG4    : 6;            /*!< [5..0] Pad output 4 configuration                                         */
23543             uint32_t            : 2;
23544       __IOM uint32_t OUTCFG5    : 6;            /*!< [13..8] Pad output 5 configuration                                        */
23545             uint32_t            : 2;
23546       __IOM uint32_t OUTCFG6    : 6;            /*!< [21..16] Pad output 6 configuration                                       */
23547             uint32_t            : 2;
23548       __IOM uint32_t OUTCFG7    : 6;            /*!< [29..24] Pad output 7 configuration                                       */
23549             uint32_t            : 2;
23550     } OUTCFG1_b;
23551   } ;
23552 
23553   union {
23554     __IOM uint32_t OUTCFG2;                     /*!< (@ 0x00000088) Pad output configuration 0.                                */
23555 
23556     struct {
23557       __IOM uint32_t OUTCFG8    : 6;            /*!< [5..0] Pad output 8 configuration                                         */
23558             uint32_t            : 2;
23559       __IOM uint32_t OUTCFG9    : 6;            /*!< [13..8] Pad output 9 configuration                                        */
23560             uint32_t            : 2;
23561       __IOM uint32_t OUTCFG10   : 6;            /*!< [21..16] Pad output 10 configuration                                      */
23562             uint32_t            : 2;
23563       __IOM uint32_t OUTCFG11   : 6;            /*!< [29..24] Pad output 11 configuration                                      */
23564             uint32_t            : 2;
23565     } OUTCFG2_b;
23566   } ;
23567 
23568   union {
23569     __IOM uint32_t OUTCFG3;                     /*!< (@ 0x0000008C) Pad output configuration 0.                                */
23570 
23571     struct {
23572       __IOM uint32_t OUTCFG12   : 6;            /*!< [5..0] Pad output 12 configuration                                        */
23573             uint32_t            : 2;
23574       __IOM uint32_t OUTCFG13   : 6;            /*!< [13..8] Pad output 13 configuration                                       */
23575             uint32_t            : 2;
23576       __IOM uint32_t OUTCFG14   : 6;            /*!< [21..16] Pad output 14 configuration                                      */
23577             uint32_t            : 2;
23578       __IOM uint32_t OUTCFG15   : 6;            /*!< [29..24] Pad output 15 configuration                                      */
23579             uint32_t            : 2;
23580     } OUTCFG3_b;
23581   } ;
23582 
23583   union {
23584     __IOM uint32_t OUTCFG4;                     /*!< (@ 0x00000090) Pad output configuration 0.                                */
23585 
23586     struct {
23587       __IOM uint32_t OUTCFG16   : 6;            /*!< [5..0] Pad output 16 configuration                                        */
23588             uint32_t            : 2;
23589       __IOM uint32_t OUTCFG17   : 6;            /*!< [13..8] Pad output 17 configuration                                       */
23590             uint32_t            : 2;
23591       __IOM uint32_t OUTCFG18   : 6;            /*!< [21..16] Pad output 18 configuration                                      */
23592             uint32_t            : 2;
23593       __IOM uint32_t OUTCFG19   : 6;            /*!< [29..24] Pad output 19 configuration                                      */
23594             uint32_t            : 2;
23595     } OUTCFG4_b;
23596   } ;
23597 
23598   union {
23599     __IOM uint32_t OUTCFG5;                     /*!< (@ 0x00000094) Pad output configuration 0.                                */
23600 
23601     struct {
23602       __IOM uint32_t OUTCFG20   : 6;            /*!< [5..0] Pad output 20 configuration                                        */
23603             uint32_t            : 2;
23604       __IOM uint32_t OUTCFG21   : 6;            /*!< [13..8] Pad output 21 configuration                                       */
23605             uint32_t            : 2;
23606       __IOM uint32_t OUTCFG22   : 6;            /*!< [21..16] Pad output 22 configuration                                      */
23607             uint32_t            : 2;
23608       __IOM uint32_t OUTCFG23   : 6;            /*!< [29..24] Pad output 23 configuration                                      */
23609             uint32_t            : 2;
23610     } OUTCFG5_b;
23611   } ;
23612 
23613   union {
23614     __IOM uint32_t OUTCFG6;                     /*!< (@ 0x00000098) Pad output configuration 0.                                */
23615 
23616     struct {
23617       __IOM uint32_t OUTCFG24   : 6;            /*!< [5..0] Pad output 24 configuration                                        */
23618             uint32_t            : 2;
23619       __IOM uint32_t OUTCFG25   : 6;            /*!< [13..8] Pad output 25 configuration                                       */
23620             uint32_t            : 2;
23621       __IOM uint32_t OUTCFG26   : 6;            /*!< [21..16] Pad output 26 configuration                                      */
23622             uint32_t            : 2;
23623       __IOM uint32_t OUTCFG27   : 6;            /*!< [29..24] Pad output 27 configuration                                      */
23624             uint32_t            : 2;
23625     } OUTCFG6_b;
23626   } ;
23627 
23628   union {
23629     __IOM uint32_t OUTCFG7;                     /*!< (@ 0x0000009C) Pad output configuration 0.                                */
23630 
23631     struct {
23632       __IOM uint32_t OUTCFG28   : 6;            /*!< [5..0] Pad output 28 configuration                                        */
23633             uint32_t            : 2;
23634       __IOM uint32_t OUTCFG29   : 6;            /*!< [13..8] Pad output 29 configuration                                       */
23635             uint32_t            : 2;
23636       __IOM uint32_t OUTCFG30   : 6;            /*!< [21..16] Pad output 30 configuration                                      */
23637             uint32_t            : 2;
23638       __IOM uint32_t OUTCFG31   : 6;            /*!< [29..24] Pad output 31 configuration                                      */
23639             uint32_t            : 2;
23640     } OUTCFG7_b;
23641   } ;
23642 
23643   union {
23644     __IOM uint32_t OUTCFG8;                     /*!< (@ 0x000000A0) Pad output configuration 0.                                */
23645 
23646     struct {
23647       __IOM uint32_t OUTCFG32   : 6;            /*!< [5..0] Pad output 32 configuration                                        */
23648             uint32_t            : 2;
23649       __IOM uint32_t OUTCFG33   : 6;            /*!< [13..8] Pad output 33 configuration                                       */
23650             uint32_t            : 2;
23651       __IOM uint32_t OUTCFG34   : 6;            /*!< [21..16] Pad output 34 configuration                                      */
23652             uint32_t            : 2;
23653       __IOM uint32_t OUTCFG35   : 6;            /*!< [29..24] Pad output 35 configuration                                      */
23654             uint32_t            : 2;
23655     } OUTCFG8_b;
23656   } ;
23657 
23658   union {
23659     __IOM uint32_t OUTCFG9;                     /*!< (@ 0x000000A4) Pad output configuration 0.                                */
23660 
23661     struct {
23662       __IOM uint32_t OUTCFG36   : 6;            /*!< [5..0] Pad output 36 configuration                                        */
23663             uint32_t            : 2;
23664       __IOM uint32_t OUTCFG37   : 6;            /*!< [13..8] Pad output 37 configuration                                       */
23665             uint32_t            : 2;
23666       __IOM uint32_t OUTCFG38   : 6;            /*!< [21..16] Pad output 38 configuration                                      */
23667             uint32_t            : 2;
23668       __IOM uint32_t OUTCFG39   : 6;            /*!< [29..24] Pad output 39 configuration                                      */
23669             uint32_t            : 2;
23670     } OUTCFG9_b;
23671   } ;
23672 
23673   union {
23674     __IOM uint32_t OUTCFG10;                    /*!< (@ 0x000000A8) Pad output configuration 0.                                */
23675 
23676     struct {
23677       __IOM uint32_t OUTCFG40   : 6;            /*!< [5..0] Pad output 40 configuration                                        */
23678             uint32_t            : 2;
23679       __IOM uint32_t OUTCFG41   : 6;            /*!< [13..8] Pad output 41 configuration                                       */
23680             uint32_t            : 2;
23681       __IOM uint32_t OUTCFG42   : 6;            /*!< [21..16] Pad output 42 configuration                                      */
23682             uint32_t            : 2;
23683       __IOM uint32_t OUTCFG43   : 6;            /*!< [29..24] Pad output 43 configuration                                      */
23684             uint32_t            : 2;
23685     } OUTCFG10_b;
23686   } ;
23687 
23688   union {
23689     __IOM uint32_t OUTCFG11;                    /*!< (@ 0x000000AC) Pad output configuration 0.                                */
23690 
23691     struct {
23692       __IOM uint32_t OUTCFG44   : 6;            /*!< [5..0] Pad output 44 configuration                                        */
23693             uint32_t            : 2;
23694       __IOM uint32_t OUTCFG45   : 6;            /*!< [13..8] Pad output 45 configuration                                       */
23695             uint32_t            : 2;
23696       __IOM uint32_t OUTCFG46   : 6;            /*!< [21..16] Pad output 46 configuration                                      */
23697             uint32_t            : 2;
23698       __IOM uint32_t OUTCFG47   : 6;            /*!< [29..24] Pad output 47 configuration                                      */
23699             uint32_t            : 2;
23700     } OUTCFG11_b;
23701   } ;
23702 
23703   union {
23704     __IOM uint32_t OUTCFG12;                    /*!< (@ 0x000000B0) Pad output configuration 0.                                */
23705 
23706     struct {
23707       __IOM uint32_t OUTCFG48   : 6;            /*!< [5..0] Pad output 48 configuration                                        */
23708             uint32_t            : 2;
23709       __IOM uint32_t OUTCFG49   : 6;            /*!< [13..8] Pad output 49 configuration                                       */
23710             uint32_t            : 2;
23711       __IOM uint32_t OUTCFG50   : 6;            /*!< [21..16] Pad output 50 configuration                                      */
23712             uint32_t            : 2;
23713       __IOM uint32_t OUTCFG51   : 6;            /*!< [29..24] Pad output 51 configuration                                      */
23714             uint32_t            : 2;
23715     } OUTCFG12_b;
23716   } ;
23717 
23718   union {
23719     __IOM uint32_t OUTCFG13;                    /*!< (@ 0x000000B4) Pad output configuration 0.                                */
23720 
23721     struct {
23722       __IOM uint32_t OUTCFG52   : 6;            /*!< [5..0] Pad output 52 configuration                                        */
23723             uint32_t            : 2;
23724       __IOM uint32_t OUTCFG53   : 6;            /*!< [13..8] Pad output 53 configuration                                       */
23725             uint32_t            : 2;
23726       __IOM uint32_t OUTCFG54   : 6;            /*!< [21..16] Pad output 54 configuration                                      */
23727             uint32_t            : 2;
23728       __IOM uint32_t OUTCFG55   : 6;            /*!< [29..24] Pad output 55 configuration                                      */
23729             uint32_t            : 2;
23730     } OUTCFG13_b;
23731   } ;
23732 
23733   union {
23734     __IOM uint32_t OUTCFG14;                    /*!< (@ 0x000000B8) Pad output configuration 0.                                */
23735 
23736     struct {
23737       __IOM uint32_t OUTCFG56   : 6;            /*!< [5..0] Pad output 56 configuration                                        */
23738             uint32_t            : 2;
23739       __IOM uint32_t OUTCFG57   : 6;            /*!< [13..8] Pad output 57 configuration                                       */
23740             uint32_t            : 2;
23741       __IOM uint32_t OUTCFG58   : 6;            /*!< [21..16] Pad output 58 configuration                                      */
23742             uint32_t            : 2;
23743       __IOM uint32_t OUTCFG59   : 6;            /*!< [29..24] Pad output 59 configuration                                      */
23744             uint32_t            : 2;
23745     } OUTCFG14_b;
23746   } ;
23747 
23748   union {
23749     __IOM uint32_t OUTCFG15;                    /*!< (@ 0x000000BC) Pad output configuration 0.                                */
23750 
23751     struct {
23752       __IOM uint32_t OUTCFG60   : 6;            /*!< [5..0] Pad output 60 configuration                                        */
23753             uint32_t            : 2;
23754       __IOM uint32_t OUTCFG61   : 6;            /*!< [13..8] Pad output 61 configuration                                       */
23755             uint32_t            : 2;
23756       __IOM uint32_t OUTCFG62   : 6;            /*!< [21..16] Pad output 62 configuration                                      */
23757             uint32_t            : 2;
23758       __IOM uint32_t OUTCFG63   : 6;            /*!< [29..24] Pad output 63 configuration                                      */
23759             uint32_t            : 2;
23760     } OUTCFG15_b;
23761   } ;
23762 
23763   union {
23764     __IOM uint32_t OUTCFG16;                    /*!< (@ 0x000000C0) Pad output configuration 0.                                */
23765 
23766     struct {
23767       __IOM uint32_t OUTCFG64   : 6;            /*!< [5..0] Pad output 64 configuration                                        */
23768             uint32_t            : 2;
23769       __IOM uint32_t OUTCFG65   : 6;            /*!< [13..8] Pad output 65 configuration                                       */
23770             uint32_t            : 2;
23771       __IOM uint32_t OUTCFG66   : 6;            /*!< [21..16] Pad output 66 configuration                                      */
23772             uint32_t            : 2;
23773       __IOM uint32_t OUTCFG67   : 6;            /*!< [29..24] Pad output 67 configuration                                      */
23774             uint32_t            : 2;
23775     } OUTCFG16_b;
23776   } ;
23777 
23778   union {
23779     __IOM uint32_t OUTCFG17;                    /*!< (@ 0x000000C4) Pad output configuration 0.                                */
23780 
23781     struct {
23782       __IOM uint32_t OUTCFG68   : 6;            /*!< [5..0] Pad output 68 configuration                                        */
23783             uint32_t            : 2;
23784       __IOM uint32_t OUTCFG69   : 6;            /*!< [13..8] Pad output 69 configuration                                       */
23785             uint32_t            : 2;
23786       __IOM uint32_t OUTCFG70   : 6;            /*!< [21..16] Pad output 70 configuration                                      */
23787             uint32_t            : 2;
23788       __IOM uint32_t OUTCFG71   : 6;            /*!< [29..24] Pad output 71 configuration                                      */
23789             uint32_t            : 2;
23790     } OUTCFG17_b;
23791   } ;
23792 
23793   union {
23794     __IOM uint32_t OUTCFG18;                    /*!< (@ 0x000000C8) Pad output configuration 0.                                */
23795 
23796     struct {
23797       __IOM uint32_t OUTCFG72   : 6;            /*!< [5..0] Pad output 72 configuration                                        */
23798             uint32_t            : 2;
23799       __IOM uint32_t OUTCFG73   : 6;            /*!< [13..8] Pad output 73 configuration                                       */
23800             uint32_t            : 2;
23801       __IOM uint32_t OUTCFG74   : 6;            /*!< [21..16] Pad output 74 configuration                                      */
23802             uint32_t            : 2;
23803       __IOM uint32_t OUTCFG75   : 6;            /*!< [29..24] Pad output 75 configuration                                      */
23804             uint32_t            : 2;
23805     } OUTCFG18_b;
23806   } ;
23807 
23808   union {
23809     __IOM uint32_t OUTCFG19;                    /*!< (@ 0x000000CC) Pad output configuration 0.                                */
23810 
23811     struct {
23812       __IOM uint32_t OUTCFG76   : 6;            /*!< [5..0] Pad output 76 configuration                                        */
23813             uint32_t            : 2;
23814       __IOM uint32_t OUTCFG77   : 6;            /*!< [13..8] Pad output 77 configuration                                       */
23815             uint32_t            : 2;
23816       __IOM uint32_t OUTCFG78   : 6;            /*!< [21..16] Pad output 78 configuration                                      */
23817             uint32_t            : 2;
23818       __IOM uint32_t OUTCFG79   : 6;            /*!< [29..24] Pad output 79 configuration                                      */
23819             uint32_t            : 2;
23820     } OUTCFG19_b;
23821   } ;
23822 
23823   union {
23824     __IOM uint32_t OUTCFG20;                    /*!< (@ 0x000000D0) Pad output configuration 0.                                */
23825 
23826     struct {
23827       __IOM uint32_t OUTCFG80   : 6;            /*!< [5..0] Pad output 80 configuration                                        */
23828             uint32_t            : 2;
23829       __IOM uint32_t OUTCFG81   : 6;            /*!< [13..8] Pad output 81 configuration                                       */
23830             uint32_t            : 2;
23831       __IOM uint32_t OUTCFG82   : 6;            /*!< [21..16] Pad output 82 configuration                                      */
23832             uint32_t            : 2;
23833       __IOM uint32_t OUTCFG83   : 6;            /*!< [29..24] Pad output 83 configuration                                      */
23834             uint32_t            : 2;
23835     } OUTCFG20_b;
23836   } ;
23837 
23838   union {
23839     __IOM uint32_t OUTCFG21;                    /*!< (@ 0x000000D4) Pad output configuration 0.                                */
23840 
23841     struct {
23842       __IOM uint32_t OUTCFG84   : 6;            /*!< [5..0] Pad output 84 configuration                                        */
23843             uint32_t            : 2;
23844       __IOM uint32_t OUTCFG85   : 6;            /*!< [13..8] Pad output 85 configuration                                       */
23845             uint32_t            : 2;
23846       __IOM uint32_t OUTCFG86   : 6;            /*!< [21..16] Pad output 86 configuration                                      */
23847             uint32_t            : 2;
23848       __IOM uint32_t OUTCFG87   : 6;            /*!< [29..24] Pad output 87 configuration                                      */
23849             uint32_t            : 2;
23850     } OUTCFG21_b;
23851   } ;
23852 
23853   union {
23854     __IOM uint32_t OUTCFG22;                    /*!< (@ 0x000000D8) Pad output configuration 0.                                */
23855 
23856     struct {
23857       __IOM uint32_t OUTCFG88   : 6;            /*!< [5..0] Pad output 88 configuration                                        */
23858             uint32_t            : 2;
23859       __IOM uint32_t OUTCFG89   : 6;            /*!< [13..8] Pad output 89 configuration                                       */
23860             uint32_t            : 2;
23861       __IOM uint32_t OUTCFG90   : 6;            /*!< [21..16] Pad output 90 configuration                                      */
23862             uint32_t            : 2;
23863       __IOM uint32_t OUTCFG91   : 6;            /*!< [29..24] Pad output 91 configuration                                      */
23864             uint32_t            : 2;
23865     } OUTCFG22_b;
23866   } ;
23867 
23868   union {
23869     __IOM uint32_t OUTCFG23;                    /*!< (@ 0x000000DC) Pad output configuration 0.                                */
23870 
23871     struct {
23872       __IOM uint32_t OUTCFG92   : 6;            /*!< [5..0] Pad output 92 configuration                                        */
23873             uint32_t            : 2;
23874       __IOM uint32_t OUTCFG93   : 6;            /*!< [13..8] Pad output 93 configuration                                       */
23875             uint32_t            : 2;
23876       __IOM uint32_t OUTCFG94   : 6;            /*!< [21..16] Pad output 94 configuration                                      */
23877             uint32_t            : 2;
23878       __IOM uint32_t OUTCFG95   : 6;            /*!< [29..24] Pad output 95 configuration                                      */
23879             uint32_t            : 2;
23880     } OUTCFG23_b;
23881   } ;
23882 
23883   union {
23884     __IOM uint32_t OUTCFG24;                    /*!< (@ 0x000000E0) Pad output configuration 0.                                */
23885 
23886     struct {
23887       __IOM uint32_t OUTCFG96   : 6;            /*!< [5..0] Pad output 96 configuration                                        */
23888             uint32_t            : 2;
23889       __IOM uint32_t OUTCFG97   : 6;            /*!< [13..8] Pad output 97 configuration                                       */
23890             uint32_t            : 2;
23891       __IOM uint32_t OUTCFG98   : 6;            /*!< [21..16] Pad output 98 configuration                                      */
23892             uint32_t            : 2;
23893       __IOM uint32_t OUTCFG99   : 6;            /*!< [29..24] Pad output 99 configuration                                      */
23894             uint32_t            : 2;
23895     } OUTCFG24_b;
23896   } ;
23897 
23898   union {
23899     __IOM uint32_t OUTCFG25;                    /*!< (@ 0x000000E4) Pad output configuration 0.                                */
23900 
23901     struct {
23902       __IOM uint32_t OUTCFG100  : 6;            /*!< [5..0] Pad output 100 configuration                                       */
23903             uint32_t            : 2;
23904       __IOM uint32_t OUTCFG101  : 6;            /*!< [13..8] Pad output 101 configuration                                      */
23905             uint32_t            : 2;
23906       __IOM uint32_t OUTCFG102  : 6;            /*!< [21..16] Pad output 102 configuration                                     */
23907             uint32_t            : 2;
23908       __IOM uint32_t OUTCFG103  : 6;            /*!< [29..24] Pad output 103 configuration                                     */
23909             uint32_t            : 2;
23910     } OUTCFG25_b;
23911   } ;
23912 
23913   union {
23914     __IOM uint32_t OUTCFG26;                    /*!< (@ 0x000000E8) Pad output configuration 0.                                */
23915 
23916     struct {
23917       __IOM uint32_t OUTCFG104  : 6;            /*!< [5..0] Pad output 104 configuration                                       */
23918             uint32_t            : 2;
23919       __IOM uint32_t OUTCFG105  : 6;            /*!< [13..8] Pad output 105 configuration                                      */
23920             uint32_t            : 2;
23921       __IOM uint32_t OUTCFG106  : 6;            /*!< [21..16] Pad output 106 configuration                                     */
23922             uint32_t            : 2;
23923       __IOM uint32_t OUTCFG107  : 6;            /*!< [29..24] Pad output 107 configuration                                     */
23924             uint32_t            : 2;
23925     } OUTCFG26_b;
23926   } ;
23927 
23928   union {
23929     __IOM uint32_t OUTCFG27;                    /*!< (@ 0x000000EC) Pad output configuration 0.                                */
23930 
23931     struct {
23932       __IOM uint32_t OUTCFG108  : 6;            /*!< [5..0] Pad output 108 configuration                                       */
23933             uint32_t            : 2;
23934       __IOM uint32_t OUTCFG109  : 6;            /*!< [13..8] Pad output 109 configuration                                      */
23935             uint32_t            : 2;
23936       __IOM uint32_t OUTCFG110  : 6;            /*!< [21..16] Pad output 110 configuration                                     */
23937             uint32_t            : 2;
23938       __IOM uint32_t OUTCFG111  : 6;            /*!< [29..24] Pad output 111 configuration                                     */
23939             uint32_t            : 2;
23940     } OUTCFG27_b;
23941   } ;
23942 
23943   union {
23944     __IOM uint32_t OUTCFG28;                    /*!< (@ 0x000000F0) Pad output configuration 0.                                */
23945 
23946     struct {
23947       __IOM uint32_t OUTCFG112  : 6;            /*!< [5..0] Pad output 112 configuration                                       */
23948             uint32_t            : 2;
23949       __IOM uint32_t OUTCFG113  : 6;            /*!< [13..8] Pad output 113 configuration                                      */
23950             uint32_t            : 2;
23951       __IOM uint32_t OUTCFG114  : 6;            /*!< [21..16] Pad output 114 configuration                                     */
23952             uint32_t            : 2;
23953       __IOM uint32_t OUTCFG115  : 6;            /*!< [29..24] Pad output 115 configuration                                     */
23954             uint32_t            : 2;
23955     } OUTCFG28_b;
23956   } ;
23957 
23958   union {
23959     __IOM uint32_t OUTCFG29;                    /*!< (@ 0x000000F4) Pad output configuration 0.                                */
23960 
23961     struct {
23962       __IOM uint32_t OUTCFG116  : 6;            /*!< [5..0] Pad output 116 configuration                                       */
23963             uint32_t            : 2;
23964       __IOM uint32_t OUTCFG117  : 6;            /*!< [13..8] Pad output 117 configuration                                      */
23965             uint32_t            : 2;
23966       __IOM uint32_t OUTCFG118  : 6;            /*!< [21..16] Pad output 118 configuration                                     */
23967             uint32_t            : 2;
23968       __IOM uint32_t OUTCFG119  : 6;            /*!< [29..24] Pad output 119 configuration                                     */
23969             uint32_t            : 2;
23970     } OUTCFG29_b;
23971   } ;
23972 
23973   union {
23974     __IOM uint32_t OUTCFG30;                    /*!< (@ 0x000000F8) Pad output configuration 0.                                */
23975 
23976     struct {
23977       __IOM uint32_t OUTCFG120  : 6;            /*!< [5..0] Pad output 120 configuration                                       */
23978             uint32_t            : 2;
23979       __IOM uint32_t OUTCFG121  : 6;            /*!< [13..8] Pad output 121 configuration                                      */
23980             uint32_t            : 2;
23981       __IOM uint32_t OUTCFG122  : 6;            /*!< [21..16] Pad output 122 configuration                                     */
23982             uint32_t            : 2;
23983       __IOM uint32_t OUTCFG123  : 6;            /*!< [29..24] Pad output 123 configuration                                     */
23984             uint32_t            : 2;
23985     } OUTCFG30_b;
23986   } ;
23987 
23988   union {
23989     __IOM uint32_t OUTCFG31;                    /*!< (@ 0x000000FC) Pad output configuration 0.                                */
23990 
23991     struct {
23992       __IOM uint32_t OUTCFG124  : 6;            /*!< [5..0] Pad output 124 configuration                                       */
23993             uint32_t            : 2;
23994       __IOM uint32_t OUTCFG125  : 6;            /*!< [13..8] Pad output 125 configuration                                      */
23995             uint32_t            : 2;
23996       __IOM uint32_t OUTCFG126  : 6;            /*!< [21..16] Pad output 126 configuration                                     */
23997             uint32_t            : 2;
23998       __IOM uint32_t OUTCFG127  : 6;            /*!< [29..24] Pad output 127 configuration                                     */
23999             uint32_t            : 2;
24000     } OUTCFG31_b;
24001   } ;
24002   __IM  uint32_t  RESERVED3;
24003 
24004   union {
24005     __IOM uint32_t AUXEN;                       /*!< (@ 0x00000104) Pattern Address                                            */
24006 
24007     struct {
24008       __IOM uint32_t TMR00EN    : 1;            /*!< [0..0] Rev B1 TIMER00 auxiliary enable.                                   */
24009       __IOM uint32_t TMR01EN    : 1;            /*!< [1..1] Rev B1 TIMER01 auxiliary enable.                                   */
24010       __IOM uint32_t TMR02EN    : 1;            /*!< [2..2] Rev B1 TIMER02 auxiliary enable.                                   */
24011       __IOM uint32_t TMR03EN    : 1;            /*!< [3..3] Rev B1 TIMER03 auxiliary enable.                                   */
24012       __IOM uint32_t TMR04EN    : 1;            /*!< [4..4] Rev B1 TIMER04 auxiliary enable.                                   */
24013       __IOM uint32_t TMR05EN    : 1;            /*!< [5..5] Rev B1 TIMER05 auxiliary enable.                                   */
24014       __IOM uint32_t TMR06EN    : 1;            /*!< [6..6] Rev B1 TIMER06 auxiliary enable.                                   */
24015       __IOM uint32_t TMR07EN    : 1;            /*!< [7..7] Rev B1 TIMER07 auxiliary enable.                                   */
24016       __IOM uint32_t TMR08EN    : 1;            /*!< [8..8] Rev B1 TIMER08 auxiliary enable.                                   */
24017       __IOM uint32_t TMR09EN    : 1;            /*!< [9..9] Rev B1 TIMER09 auxiliary enable.                                   */
24018       __IOM uint32_t TMR10EN    : 1;            /*!< [10..10] Rev B1 TIMER10 auxiliary enable.                                 */
24019       __IOM uint32_t TMR11EN    : 1;            /*!< [11..11] Rev B1 TIMER11 auxiliary enable.                                 */
24020       __IOM uint32_t TMR12EN    : 1;            /*!< [12..12] Rev B1 TIMER12 auxiliary enable.                                 */
24021       __IOM uint32_t TMR13EN    : 1;            /*!< [13..13] Rev B1 TIMER13 auxiliary enable.                                 */
24022       __IOM uint32_t TMR14EN    : 1;            /*!< [14..14] Rev B1 TIMER14 auxiliary enable.                                 */
24023       __IOM uint32_t TMR15EN    : 1;            /*!< [15..15] Rev B1 TIMER15 auxiliary enable.                                 */
24024       __IOM uint32_t STMREN     : 1;            /*!< [16..16] Rev B1 STIMER auxiliary enable.                                  */
24025             uint32_t            : 15;
24026     } AUXEN_b;
24027   } ;
24028   __IM  uint32_t  RESERVED4[62];
24029 
24030   union {
24031     __IOM uint32_t CTRL0;                       /*!< (@ 0x00000200) This includes the Control bit fields for timer
24032                                                                     0.                                                         */
24033 
24034     struct {
24035       __IOM uint32_t TMR0EN     : 1;            /*!< [0..0] Counter/Timer 0 Enable bit.                                        */
24036       __IOM uint32_t TMR0CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24037       __IOM uint32_t TMR0POL0   : 1;            /*!< [2..2] Counter/Timer 0 output 0 polarity.                                 */
24038       __IOM uint32_t TMR0POL1   : 1;            /*!< [3..3] Counter/Timer 0 output 1 polarity.                                 */
24039       __IOM uint32_t TMR0FN     : 4;            /*!< [7..4] Counter/Timer 0 Function Select.                                   */
24040       __IOM uint32_t TMR0CLK    : 8;            /*!< [15..8] Counter/Timer 0 Clock Select.                                     */
24041       __IOM uint32_t TMR0TMODE  : 2;            /*!< [17..16] Counter/Timer 0 Trigger Mode                                     */
24042             uint32_t            : 6;
24043       __IOM uint32_t TMR0LMT    : 8;            /*!< [31..24] Counter/Timer 0 Pattern Limit Count.                             */
24044     } CTRL0_b;
24045   } ;
24046 
24047   union {
24048     __IOM uint32_t TIMER0;                      /*!< (@ 0x00000204) This register holds the running time or event
24049                                                                     count for timer 0.                                         */
24050 
24051     struct {
24052       __IOM uint32_t TIMER0     : 32;           /*!< [31..0] Counter/Timer 0                                                   */
24053     } TIMER0_b;
24054   } ;
24055 
24056   union {
24057     __IOM uint32_t TMR0CMP0;                    /*!< (@ 0x00000208) This contains the Compare limits for timer 0.
24058                                                                     This is the primary comparator that can
24059                                                                     be used to mark the END of a timer cycle
24060                                                                     (and thus restart the timer for repeat modes)              */
24061 
24062     struct {
24063       __IOM uint32_t TMR0CMP0   : 32;           /*!< [31..0] Counter/Timer 0 End Compare Register. For MEASURE mode
24064                                                      indicates the high phase sample count.                                    */
24065     } TMR0CMP0_b;
24066   } ;
24067 
24068   union {
24069     __IOM uint32_t TMR0CMP1;                    /*!< (@ 0x0000020C) This comparator is used as a secondary compare
24070                                                                     count for modes that generate pulses. For
24071                                                                     MEASURE mode indicates the low phase sample
24072                                                                     count.                                                     */
24073 
24074     struct {
24075       __IOM uint32_t TMR0CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24076                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24077                                                      be used first.                                                            */
24078     } TMR0CMP1_b;
24079   } ;
24080 
24081   union {
24082     __IOM uint32_t MODE0;                       /*!< (@ 0x00000210) The mode register contains optional mode controls
24083                                                                     for the timer                                              */
24084 
24085     struct {
24086             uint32_t            : 8;
24087       __IOM uint32_t TMR0TRIGSEL : 8;           /*!< [15..8] Counter/Timer 0 Trigger Source Selection                          */
24088             uint32_t            : 16;
24089     } MODE0_b;
24090   } ;
24091   __IM  uint32_t  RESERVED5[3];
24092 
24093   union {
24094     __IOM uint32_t CTRL1;                       /*!< (@ 0x00000220) This includes the Control bit fields for timer
24095                                                                     1.                                                         */
24096 
24097     struct {
24098       __IOM uint32_t TMR1EN     : 1;            /*!< [0..0] Counter/Timer 1 Enable bit.                                        */
24099       __IOM uint32_t TMR1CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24100       __IOM uint32_t TMR1POL0   : 1;            /*!< [2..2] Counter/Timer 1 output 0 polarity.                                 */
24101       __IOM uint32_t TMR1POL1   : 1;            /*!< [3..3] Counter/Timer 1 output 1 polarity.                                 */
24102       __IOM uint32_t TMR1FN     : 4;            /*!< [7..4] Counter/Timer 1 Function Select.                                   */
24103       __IOM uint32_t TMR1CLK    : 8;            /*!< [15..8] Counter/Timer 1 Clock Select.                                     */
24104       __IOM uint32_t TMR1TMODE  : 2;            /*!< [17..16] Counter/Timer 1 Trigger Mode                                     */
24105             uint32_t            : 6;
24106       __IOM uint32_t TMR1LMT    : 8;            /*!< [31..24] Counter/Timer 1 Pattern Limit Count.                             */
24107     } CTRL1_b;
24108   } ;
24109 
24110   union {
24111     __IOM uint32_t TIMER1;                      /*!< (@ 0x00000224) This register holds the running time or event
24112                                                                     count for timer 1.                                         */
24113 
24114     struct {
24115       __IOM uint32_t TIMER1     : 32;           /*!< [31..0] Counter/Timer 1                                                   */
24116     } TIMER1_b;
24117   } ;
24118 
24119   union {
24120     __IOM uint32_t TMR1CMP0;                    /*!< (@ 0x00000228) This contains the Compare limits for timer 1.
24121                                                                     This is the primary comparator that can
24122                                                                     be used to mark the END of a timer cycle
24123                                                                     (and thus restart the timer for repeat modes)              */
24124 
24125     struct {
24126       __IOM uint32_t TMR1CMP0   : 32;           /*!< [31..0] Counter/Timer 1 End Compare Register. For MEASURE mode
24127                                                      indicates the high phase sample count.                                    */
24128     } TMR1CMP0_b;
24129   } ;
24130 
24131   union {
24132     __IOM uint32_t TMR1CMP1;                    /*!< (@ 0x0000022C) This comparator is used as a secondary compare
24133                                                                     count for modes that generate pulses. For
24134                                                                     MEASURE mode indicates the low phase sample
24135                                                                     count.                                                     */
24136 
24137     struct {
24138       __IOM uint32_t TMR1CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24139                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24140                                                      be used first.                                                            */
24141     } TMR1CMP1_b;
24142   } ;
24143 
24144   union {
24145     __IOM uint32_t MODE1;                       /*!< (@ 0x00000230) The mode register contains optional mode controls
24146                                                                     for the timer                                              */
24147 
24148     struct {
24149             uint32_t            : 8;
24150       __IOM uint32_t TMR1TRIGSEL : 8;           /*!< [15..8] Counter/Timer 1 Trigger Source Selection                          */
24151             uint32_t            : 16;
24152     } MODE1_b;
24153   } ;
24154   __IM  uint32_t  RESERVED6[3];
24155 
24156   union {
24157     __IOM uint32_t CTRL2;                       /*!< (@ 0x00000240) This includes the Control bit fields for timer
24158                                                                     2.                                                         */
24159 
24160     struct {
24161       __IOM uint32_t TMR2EN     : 1;            /*!< [0..0] Counter/Timer 2 Enable bit.                                        */
24162       __IOM uint32_t TMR2CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24163       __IOM uint32_t TMR2POL0   : 1;            /*!< [2..2] Counter/Timer 2 output 0 polarity.                                 */
24164       __IOM uint32_t TMR2POL1   : 1;            /*!< [3..3] Counter/Timer 2 output 1 polarity.                                 */
24165       __IOM uint32_t TMR2FN     : 4;            /*!< [7..4] Counter/Timer 2 Function Select.                                   */
24166       __IOM uint32_t TMR2CLK    : 8;            /*!< [15..8] Counter/Timer 2 Clock Select.                                     */
24167       __IOM uint32_t TMR2TMODE  : 2;            /*!< [17..16] Counter/Timer 2 Trigger Mode                                     */
24168             uint32_t            : 6;
24169       __IOM uint32_t TMR2LMT    : 8;            /*!< [31..24] Counter/Timer 2 Pattern Limit Count.                             */
24170     } CTRL2_b;
24171   } ;
24172 
24173   union {
24174     __IOM uint32_t TIMER2;                      /*!< (@ 0x00000244) This register holds the running time or event
24175                                                                     count for timer 2.                                         */
24176 
24177     struct {
24178       __IOM uint32_t TIMER2     : 32;           /*!< [31..0] Counter/Timer 2                                                   */
24179     } TIMER2_b;
24180   } ;
24181 
24182   union {
24183     __IOM uint32_t TMR2CMP0;                    /*!< (@ 0x00000248) This contains the Compare limits for timer 2.
24184                                                                     This is the primary comparator that can
24185                                                                     be used to mark the END of a timer cycle
24186                                                                     (and thus restart the timer for repeat modes)              */
24187 
24188     struct {
24189       __IOM uint32_t TMR2CMP0   : 32;           /*!< [31..0] Counter/Timer 2 End Compare Register. For MEASURE mode
24190                                                      indicates the high phase sample count.                                    */
24191     } TMR2CMP0_b;
24192   } ;
24193 
24194   union {
24195     __IOM uint32_t TMR2CMP1;                    /*!< (@ 0x0000024C) This comparator is used as a secondary compare
24196                                                                     count for modes that generate pulses. For
24197                                                                     MEASURE mode indicates the low phase sample
24198                                                                     count.                                                     */
24199 
24200     struct {
24201       __IOM uint32_t TMR2CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24202                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24203                                                      be used first.                                                            */
24204     } TMR2CMP1_b;
24205   } ;
24206 
24207   union {
24208     __IOM uint32_t MODE2;                       /*!< (@ 0x00000250) The mode register contains optional mode controls
24209                                                                     for the timer                                              */
24210 
24211     struct {
24212             uint32_t            : 8;
24213       __IOM uint32_t TMR2TRIGSEL : 8;           /*!< [15..8] Counter/Timer 2 Trigger Source Selection                          */
24214             uint32_t            : 16;
24215     } MODE2_b;
24216   } ;
24217   __IM  uint32_t  RESERVED7[3];
24218 
24219   union {
24220     __IOM uint32_t CTRL3;                       /*!< (@ 0x00000260) This includes the Control bit fields for timer
24221                                                                     3.                                                         */
24222 
24223     struct {
24224       __IOM uint32_t TMR3EN     : 1;            /*!< [0..0] Counter/Timer 3 Enable bit.                                        */
24225       __IOM uint32_t TMR3CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24226       __IOM uint32_t TMR3POL0   : 1;            /*!< [2..2] Counter/Timer 3 output 0 polarity.                                 */
24227       __IOM uint32_t TMR3POL1   : 1;            /*!< [3..3] Counter/Timer 3 output 1 polarity.                                 */
24228       __IOM uint32_t TMR3FN     : 4;            /*!< [7..4] Counter/Timer 3 Function Select.                                   */
24229       __IOM uint32_t TMR3CLK    : 8;            /*!< [15..8] Counter/Timer 3 Clock Select.                                     */
24230       __IOM uint32_t TMR3TMODE  : 2;            /*!< [17..16] Counter/Timer 3 Trigger Mode                                     */
24231             uint32_t            : 6;
24232       __IOM uint32_t TMR3LMT    : 8;            /*!< [31..24] Counter/Timer 3 Pattern Limit Count.                             */
24233     } CTRL3_b;
24234   } ;
24235 
24236   union {
24237     __IOM uint32_t TIMER3;                      /*!< (@ 0x00000264) This register holds the running time or event
24238                                                                     count for timer 3.                                         */
24239 
24240     struct {
24241       __IOM uint32_t TIMER3     : 32;           /*!< [31..0] Counter/Timer 3                                                   */
24242     } TIMER3_b;
24243   } ;
24244 
24245   union {
24246     __IOM uint32_t TMR3CMP0;                    /*!< (@ 0x00000268) This contains the Compare limits for timer 3.
24247                                                                     This is the primary comparator that can
24248                                                                     be used to mark the END of a timer cycle
24249                                                                     (and thus restart the timer for repeat modes)              */
24250 
24251     struct {
24252       __IOM uint32_t TMR3CMP0   : 32;           /*!< [31..0] Counter/Timer 3 End Compare Register. For MEASURE mode
24253                                                      indicates the high phase sample count.                                    */
24254     } TMR3CMP0_b;
24255   } ;
24256 
24257   union {
24258     __IOM uint32_t TMR3CMP1;                    /*!< (@ 0x0000026C) This comparator is used as a secondary compare
24259                                                                     count for modes that generate pulses. For
24260                                                                     MEASURE mode indicates the low phase sample
24261                                                                     count.                                                     */
24262 
24263     struct {
24264       __IOM uint32_t TMR3CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24265                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24266                                                      be used first.                                                            */
24267     } TMR3CMP1_b;
24268   } ;
24269 
24270   union {
24271     __IOM uint32_t MODE3;                       /*!< (@ 0x00000270) The mode register contains optional mode controls
24272                                                                     for the timer                                              */
24273 
24274     struct {
24275             uint32_t            : 8;
24276       __IOM uint32_t TMR3TRIGSEL : 8;           /*!< [15..8] Counter/Timer 3 Trigger Source Selection                          */
24277             uint32_t            : 16;
24278     } MODE3_b;
24279   } ;
24280   __IM  uint32_t  RESERVED8[3];
24281 
24282   union {
24283     __IOM uint32_t CTRL4;                       /*!< (@ 0x00000280) This includes the Control bit fields for timer
24284                                                                     4.                                                         */
24285 
24286     struct {
24287       __IOM uint32_t TMR4EN     : 1;            /*!< [0..0] Counter/Timer 4 Enable bit.                                        */
24288       __IOM uint32_t TMR4CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24289       __IOM uint32_t TMR4POL0   : 1;            /*!< [2..2] Counter/Timer 4 output 0 polarity.                                 */
24290       __IOM uint32_t TMR4POL1   : 1;            /*!< [3..3] Counter/Timer 4 output 1 polarity.                                 */
24291       __IOM uint32_t TMR4FN     : 4;            /*!< [7..4] Counter/Timer 4 Function Select.                                   */
24292       __IOM uint32_t TMR4CLK    : 8;            /*!< [15..8] Counter/Timer 4 Clock Select.                                     */
24293       __IOM uint32_t TMR4TMODE  : 2;            /*!< [17..16] Counter/Timer 4 Trigger Mode                                     */
24294             uint32_t            : 6;
24295       __IOM uint32_t TMR4LMT    : 8;            /*!< [31..24] Counter/Timer 4 Pattern Limit Count.                             */
24296     } CTRL4_b;
24297   } ;
24298 
24299   union {
24300     __IOM uint32_t TIMER4;                      /*!< (@ 0x00000284) This register holds the running time or event
24301                                                                     count for timer 4.                                         */
24302 
24303     struct {
24304       __IOM uint32_t TIMER4     : 32;           /*!< [31..0] Counter/Timer 4                                                   */
24305     } TIMER4_b;
24306   } ;
24307 
24308   union {
24309     __IOM uint32_t TMR4CMP0;                    /*!< (@ 0x00000288) This contains the Compare limits for timer 4.
24310                                                                     This is the primary comparator that can
24311                                                                     be used to mark the END of a timer cycle
24312                                                                     (and thus restart the timer for repeat modes)              */
24313 
24314     struct {
24315       __IOM uint32_t TMR4CMP0   : 32;           /*!< [31..0] Counter/Timer 4 End Compare Register. For MEASURE mode
24316                                                      indicates the high phase sample count.                                    */
24317     } TMR4CMP0_b;
24318   } ;
24319 
24320   union {
24321     __IOM uint32_t TMR4CMP1;                    /*!< (@ 0x0000028C) This comparator is used as a secondary compare
24322                                                                     count for modes that generate pulses. For
24323                                                                     MEASURE mode indicates the low phase sample
24324                                                                     count.                                                     */
24325 
24326     struct {
24327       __IOM uint32_t TMR4CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24328                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24329                                                      be used first.                                                            */
24330     } TMR4CMP1_b;
24331   } ;
24332 
24333   union {
24334     __IOM uint32_t MODE4;                       /*!< (@ 0x00000290) The mode register contains optional mode controls
24335                                                                     for the timer                                              */
24336 
24337     struct {
24338             uint32_t            : 8;
24339       __IOM uint32_t TMR4TRIGSEL : 8;           /*!< [15..8] Counter/Timer 4 Trigger Source Selection                          */
24340             uint32_t            : 16;
24341     } MODE4_b;
24342   } ;
24343   __IM  uint32_t  RESERVED9[3];
24344 
24345   union {
24346     __IOM uint32_t CTRL5;                       /*!< (@ 0x000002A0) This includes the Control bit fields for timer
24347                                                                     5.                                                         */
24348 
24349     struct {
24350       __IOM uint32_t TMR5EN     : 1;            /*!< [0..0] Counter/Timer 5 Enable bit.                                        */
24351       __IOM uint32_t TMR5CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24352       __IOM uint32_t TMR5POL0   : 1;            /*!< [2..2] Counter/Timer 5 output 0 polarity.                                 */
24353       __IOM uint32_t TMR5POL1   : 1;            /*!< [3..3] Counter/Timer 5 output 1 polarity.                                 */
24354       __IOM uint32_t TMR5FN     : 4;            /*!< [7..4] Counter/Timer 5 Function Select.                                   */
24355       __IOM uint32_t TMR5CLK    : 8;            /*!< [15..8] Counter/Timer 5 Clock Select.                                     */
24356       __IOM uint32_t TMR5TMODE  : 2;            /*!< [17..16] Counter/Timer 5 Trigger Mode                                     */
24357             uint32_t            : 6;
24358       __IOM uint32_t TMR5LMT    : 8;            /*!< [31..24] Counter/Timer 5 Pattern Limit Count.                             */
24359     } CTRL5_b;
24360   } ;
24361 
24362   union {
24363     __IOM uint32_t TIMER5;                      /*!< (@ 0x000002A4) This register holds the running time or event
24364                                                                     count for timer 5.                                         */
24365 
24366     struct {
24367       __IOM uint32_t TIMER5     : 32;           /*!< [31..0] Counter/Timer 5                                                   */
24368     } TIMER5_b;
24369   } ;
24370 
24371   union {
24372     __IOM uint32_t TMR5CMP0;                    /*!< (@ 0x000002A8) This contains the Compare limits for timer 5.
24373                                                                     This is the primary comparator that can
24374                                                                     be used to mark the END of a timer cycle
24375                                                                     (and thus restart the timer for repeat modes)              */
24376 
24377     struct {
24378       __IOM uint32_t TMR5CMP0   : 32;           /*!< [31..0] Counter/Timer 5 End Compare Register. For MEASURE mode
24379                                                      indicates the high phase sample count.                                    */
24380     } TMR5CMP0_b;
24381   } ;
24382 
24383   union {
24384     __IOM uint32_t TMR5CMP1;                    /*!< (@ 0x000002AC) This comparator is used as a secondary compare
24385                                                                     count for modes that generate pulses. For
24386                                                                     MEASURE mode indicates the low phase sample
24387                                                                     count.                                                     */
24388 
24389     struct {
24390       __IOM uint32_t TMR5CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24391                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24392                                                      be used first.                                                            */
24393     } TMR5CMP1_b;
24394   } ;
24395 
24396   union {
24397     __IOM uint32_t MODE5;                       /*!< (@ 0x000002B0) The mode register contains optional mode controls
24398                                                                     for the timer                                              */
24399 
24400     struct {
24401             uint32_t            : 8;
24402       __IOM uint32_t TMR5TRIGSEL : 8;           /*!< [15..8] Counter/Timer 5 Trigger Source Selection                          */
24403             uint32_t            : 16;
24404     } MODE5_b;
24405   } ;
24406   __IM  uint32_t  RESERVED10[3];
24407 
24408   union {
24409     __IOM uint32_t CTRL6;                       /*!< (@ 0x000002C0) This includes the Control bit fields for timer
24410                                                                     6.                                                         */
24411 
24412     struct {
24413       __IOM uint32_t TMR6EN     : 1;            /*!< [0..0] Counter/Timer 6 Enable bit.                                        */
24414       __IOM uint32_t TMR6CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24415       __IOM uint32_t TMR6POL0   : 1;            /*!< [2..2] Counter/Timer 6 output 0 polarity.                                 */
24416       __IOM uint32_t TMR6POL1   : 1;            /*!< [3..3] Counter/Timer 6 output 1 polarity.                                 */
24417       __IOM uint32_t TMR6FN     : 4;            /*!< [7..4] Counter/Timer 6 Function Select.                                   */
24418       __IOM uint32_t TMR6CLK    : 8;            /*!< [15..8] Counter/Timer 6 Clock Select.                                     */
24419       __IOM uint32_t TMR6TMODE  : 2;            /*!< [17..16] Counter/Timer 6 Trigger Mode                                     */
24420             uint32_t            : 6;
24421       __IOM uint32_t TMR6LMT    : 8;            /*!< [31..24] Counter/Timer 6 Pattern Limit Count.                             */
24422     } CTRL6_b;
24423   } ;
24424 
24425   union {
24426     __IOM uint32_t TIMER6;                      /*!< (@ 0x000002C4) This register holds the running time or event
24427                                                                     count for timer 6.                                         */
24428 
24429     struct {
24430       __IOM uint32_t TIMER6     : 32;           /*!< [31..0] Counter/Timer 6                                                   */
24431     } TIMER6_b;
24432   } ;
24433 
24434   union {
24435     __IOM uint32_t TMR6CMP0;                    /*!< (@ 0x000002C8) This contains the Compare limits for timer 6.
24436                                                                     This is the primary comparator that can
24437                                                                     be used to mark the END of a timer cycle
24438                                                                     (and thus restart the timer for repeat modes)              */
24439 
24440     struct {
24441       __IOM uint32_t TMR6CMP0   : 32;           /*!< [31..0] Counter/Timer 6 End Compare Register. For MEASURE mode
24442                                                      indicates the high phase sample count.                                    */
24443     } TMR6CMP0_b;
24444   } ;
24445 
24446   union {
24447     __IOM uint32_t TMR6CMP1;                    /*!< (@ 0x000002CC) This comparator is used as a secondary compare
24448                                                                     count for modes that generate pulses. For
24449                                                                     MEASURE mode indicates the low phase sample
24450                                                                     count.                                                     */
24451 
24452     struct {
24453       __IOM uint32_t TMR6CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24454                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24455                                                      be used first.                                                            */
24456     } TMR6CMP1_b;
24457   } ;
24458 
24459   union {
24460     __IOM uint32_t MODE6;                       /*!< (@ 0x000002D0) The mode register contains optional mode controls
24461                                                                     for the timer                                              */
24462 
24463     struct {
24464             uint32_t            : 8;
24465       __IOM uint32_t TMR6TRIGSEL : 8;           /*!< [15..8] Counter/Timer 6 Trigger Source Selection                          */
24466             uint32_t            : 16;
24467     } MODE6_b;
24468   } ;
24469   __IM  uint32_t  RESERVED11[3];
24470 
24471   union {
24472     __IOM uint32_t CTRL7;                       /*!< (@ 0x000002E0) This includes the Control bit fields for timer
24473                                                                     7.                                                         */
24474 
24475     struct {
24476       __IOM uint32_t TMR7EN     : 1;            /*!< [0..0] Counter/Timer 7 Enable bit.                                        */
24477       __IOM uint32_t TMR7CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24478       __IOM uint32_t TMR7POL0   : 1;            /*!< [2..2] Counter/Timer 7 output 0 polarity.                                 */
24479       __IOM uint32_t TMR7POL1   : 1;            /*!< [3..3] Counter/Timer 7 output 1 polarity.                                 */
24480       __IOM uint32_t TMR7FN     : 4;            /*!< [7..4] Counter/Timer 7 Function Select.                                   */
24481       __IOM uint32_t TMR7CLK    : 8;            /*!< [15..8] Counter/Timer 7 Clock Select.                                     */
24482       __IOM uint32_t TMR7TMODE  : 2;            /*!< [17..16] Counter/Timer 7 Trigger Mode                                     */
24483             uint32_t            : 6;
24484       __IOM uint32_t TMR7LMT    : 8;            /*!< [31..24] Counter/Timer 7 Pattern Limit Count.                             */
24485     } CTRL7_b;
24486   } ;
24487 
24488   union {
24489     __IOM uint32_t TIMER7;                      /*!< (@ 0x000002E4) This register holds the running time or event
24490                                                                     count for timer 7.                                         */
24491 
24492     struct {
24493       __IOM uint32_t TIMER7     : 32;           /*!< [31..0] Counter/Timer 7                                                   */
24494     } TIMER7_b;
24495   } ;
24496 
24497   union {
24498     __IOM uint32_t TMR7CMP0;                    /*!< (@ 0x000002E8) This contains the Compare limits for timer 7.
24499                                                                     This is the primary comparator that can
24500                                                                     be used to mark the END of a timer cycle
24501                                                                     (and thus restart the timer for repeat modes)              */
24502 
24503     struct {
24504       __IOM uint32_t TMR7CMP0   : 32;           /*!< [31..0] Counter/Timer 7 End Compare Register. For MEASURE mode
24505                                                      indicates the high phase sample count.                                    */
24506     } TMR7CMP0_b;
24507   } ;
24508 
24509   union {
24510     __IOM uint32_t TMR7CMP1;                    /*!< (@ 0x000002EC) This comparator is used as a secondary compare
24511                                                                     count for modes that generate pulses. For
24512                                                                     MEASURE mode indicates the low phase sample
24513                                                                     count.                                                     */
24514 
24515     struct {
24516       __IOM uint32_t TMR7CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24517                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24518                                                      be used first.                                                            */
24519     } TMR7CMP1_b;
24520   } ;
24521 
24522   union {
24523     __IOM uint32_t MODE7;                       /*!< (@ 0x000002F0) The mode register contains optional mode controls
24524                                                                     for the timer                                              */
24525 
24526     struct {
24527             uint32_t            : 8;
24528       __IOM uint32_t TMR7TRIGSEL : 8;           /*!< [15..8] Counter/Timer 7 Trigger Source Selection                          */
24529             uint32_t            : 16;
24530     } MODE7_b;
24531   } ;
24532   __IM  uint32_t  RESERVED12[3];
24533 
24534   union {
24535     __IOM uint32_t CTRL8;                       /*!< (@ 0x00000300) This includes the Control bit fields for timer
24536                                                                     8.                                                         */
24537 
24538     struct {
24539       __IOM uint32_t TMR8EN     : 1;            /*!< [0..0] Counter/Timer 8 Enable bit.                                        */
24540       __IOM uint32_t TMR8CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24541       __IOM uint32_t TMR8POL0   : 1;            /*!< [2..2] Counter/Timer 8 output 0 polarity.                                 */
24542       __IOM uint32_t TMR8POL1   : 1;            /*!< [3..3] Counter/Timer 8 output 1 polarity.                                 */
24543       __IOM uint32_t TMR8FN     : 4;            /*!< [7..4] Counter/Timer 8 Function Select.                                   */
24544       __IOM uint32_t TMR8CLK    : 8;            /*!< [15..8] Counter/Timer 8 Clock Select.                                     */
24545       __IOM uint32_t TMR8TMODE  : 2;            /*!< [17..16] Counter/Timer 8 Trigger Mode                                     */
24546             uint32_t            : 6;
24547       __IOM uint32_t TMR8LMT    : 8;            /*!< [31..24] Counter/Timer 8 Pattern Limit Count.                             */
24548     } CTRL8_b;
24549   } ;
24550 
24551   union {
24552     __IOM uint32_t TIMER8;                      /*!< (@ 0x00000304) This register holds the running time or event
24553                                                                     count for timer 8.                                         */
24554 
24555     struct {
24556       __IOM uint32_t TIMER8     : 32;           /*!< [31..0] Counter/Timer 8                                                   */
24557     } TIMER8_b;
24558   } ;
24559 
24560   union {
24561     __IOM uint32_t TMR8CMP0;                    /*!< (@ 0x00000308) This contains the Compare limits for timer 8.
24562                                                                     This is the primary comparator that can
24563                                                                     be used to mark the END of a timer cycle
24564                                                                     (and thus restart the timer for repeat modes)              */
24565 
24566     struct {
24567       __IOM uint32_t TMR8CMP0   : 32;           /*!< [31..0] Counter/Timer 8 End Compare Register. For MEASURE mode
24568                                                      indicates the high phase sample count.                                    */
24569     } TMR8CMP0_b;
24570   } ;
24571 
24572   union {
24573     __IOM uint32_t TMR8CMP1;                    /*!< (@ 0x0000030C) This comparator is used as a secondary compare
24574                                                                     count for modes that generate pulses. For
24575                                                                     MEASURE mode indicates the low phase sample
24576                                                                     count.                                                     */
24577 
24578     struct {
24579       __IOM uint32_t TMR8CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24580                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24581                                                      be used first.                                                            */
24582     } TMR8CMP1_b;
24583   } ;
24584 
24585   union {
24586     __IOM uint32_t MODE8;                       /*!< (@ 0x00000310) The mode register contains optional mode controls
24587                                                                     for the timer                                              */
24588 
24589     struct {
24590             uint32_t            : 8;
24591       __IOM uint32_t TMR8TRIGSEL : 8;           /*!< [15..8] Counter/Timer 8 Trigger Source Selection                          */
24592             uint32_t            : 16;
24593     } MODE8_b;
24594   } ;
24595   __IM  uint32_t  RESERVED13[3];
24596 
24597   union {
24598     __IOM uint32_t CTRL9;                       /*!< (@ 0x00000320) This includes the Control bit fields for timer
24599                                                                     9.                                                         */
24600 
24601     struct {
24602       __IOM uint32_t TMR9EN     : 1;            /*!< [0..0] Counter/Timer 9 Enable bit.                                        */
24603       __IOM uint32_t TMR9CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24604       __IOM uint32_t TMR9POL0   : 1;            /*!< [2..2] Counter/Timer 9 output 0 polarity.                                 */
24605       __IOM uint32_t TMR9POL1   : 1;            /*!< [3..3] Counter/Timer 9 output 1 polarity.                                 */
24606       __IOM uint32_t TMR9FN     : 4;            /*!< [7..4] Counter/Timer 9 Function Select.                                   */
24607       __IOM uint32_t TMR9CLK    : 8;            /*!< [15..8] Counter/Timer 9 Clock Select.                                     */
24608       __IOM uint32_t TMR9TMODE  : 2;            /*!< [17..16] Counter/Timer 9 Trigger Mode                                     */
24609             uint32_t            : 6;
24610       __IOM uint32_t TMR9LMT    : 8;            /*!< [31..24] Counter/Timer 9 Pattern Limit Count.                             */
24611     } CTRL9_b;
24612   } ;
24613 
24614   union {
24615     __IOM uint32_t TIMER9;                      /*!< (@ 0x00000324) This register holds the running time or event
24616                                                                     count for timer 9.                                         */
24617 
24618     struct {
24619       __IOM uint32_t TIMER9     : 32;           /*!< [31..0] Counter/Timer 9                                                   */
24620     } TIMER9_b;
24621   } ;
24622 
24623   union {
24624     __IOM uint32_t TMR9CMP0;                    /*!< (@ 0x00000328) This contains the Compare limits for timer 9.
24625                                                                     This is the primary comparator that can
24626                                                                     be used to mark the END of a timer cycle
24627                                                                     (and thus restart the timer for repeat modes)              */
24628 
24629     struct {
24630       __IOM uint32_t TMR9CMP0   : 32;           /*!< [31..0] Counter/Timer 9 End Compare Register. For MEASURE mode
24631                                                      indicates the high phase sample count.                                    */
24632     } TMR9CMP0_b;
24633   } ;
24634 
24635   union {
24636     __IOM uint32_t TMR9CMP1;                    /*!< (@ 0x0000032C) This comparator is used as a secondary compare
24637                                                                     count for modes that generate pulses. For
24638                                                                     MEASURE mode indicates the low phase sample
24639                                                                     count.                                                     */
24640 
24641     struct {
24642       __IOM uint32_t TMR9CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24643                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24644                                                      be used first.                                                            */
24645     } TMR9CMP1_b;
24646   } ;
24647 
24648   union {
24649     __IOM uint32_t MODE9;                       /*!< (@ 0x00000330) The mode register contains optional mode controls
24650                                                                     for the timer                                              */
24651 
24652     struct {
24653             uint32_t            : 8;
24654       __IOM uint32_t TMR9TRIGSEL : 8;           /*!< [15..8] Counter/Timer 9 Trigger Source Selection                          */
24655             uint32_t            : 16;
24656     } MODE9_b;
24657   } ;
24658   __IM  uint32_t  RESERVED14[3];
24659 
24660   union {
24661     __IOM uint32_t CTRL10;                      /*!< (@ 0x00000340) This includes the Control bit fields for timer
24662                                                                     10.                                                        */
24663 
24664     struct {
24665       __IOM uint32_t TMR10EN    : 1;            /*!< [0..0] Counter/Timer 10 Enable bit.                                       */
24666       __IOM uint32_t TMR10CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24667       __IOM uint32_t TMR10POL0  : 1;            /*!< [2..2] Counter/Timer 10 output 0 polarity.                                */
24668       __IOM uint32_t TMR10POL1  : 1;            /*!< [3..3] Counter/Timer 10 output 1 polarity.                                */
24669       __IOM uint32_t TMR10FN    : 4;            /*!< [7..4] Counter/Timer 10 Function Select.                                  */
24670       __IOM uint32_t TMR10CLK   : 8;            /*!< [15..8] Counter/Timer 10 Clock Select.                                    */
24671       __IOM uint32_t TMR10TMODE : 2;            /*!< [17..16] Counter/Timer 10 Trigger Mode                                    */
24672             uint32_t            : 6;
24673       __IOM uint32_t TMR10LMT   : 8;            /*!< [31..24] Counter/Timer 10 Pattern Limit Count.                            */
24674     } CTRL10_b;
24675   } ;
24676 
24677   union {
24678     __IOM uint32_t TIMER10;                     /*!< (@ 0x00000344) This register holds the running time or event
24679                                                                     count for timer 10.                                        */
24680 
24681     struct {
24682       __IOM uint32_t TIMER10    : 32;           /*!< [31..0] Counter/Timer 10                                                  */
24683     } TIMER10_b;
24684   } ;
24685 
24686   union {
24687     __IOM uint32_t TMR10CMP0;                   /*!< (@ 0x00000348) This contains the Compare limits for timer 10.
24688                                                                     This is the primary comparator that can
24689                                                                     be used to mark the END of a timer cycle
24690                                                                     (and thus restart the timer for repeat modes)              */
24691 
24692     struct {
24693       __IOM uint32_t TMR10CMP0  : 32;           /*!< [31..0] Counter/Timer 10 End Compare Register. For MEASURE mode
24694                                                      indicates the high phase sample count.                                    */
24695     } TMR10CMP0_b;
24696   } ;
24697 
24698   union {
24699     __IOM uint32_t TMR10CMP1;                   /*!< (@ 0x0000034C) This comparator is used as a secondary compare
24700                                                                     count for modes that generate pulses. For
24701                                                                     MEASURE mode indicates the low phase sample
24702                                                                     count.                                                     */
24703 
24704     struct {
24705       __IOM uint32_t TMR10CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24706                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24707                                                      be used first.                                                            */
24708     } TMR10CMP1_b;
24709   } ;
24710 
24711   union {
24712     __IOM uint32_t MODE10;                      /*!< (@ 0x00000350) The mode register contains optional mode controls
24713                                                                     for the timer                                              */
24714 
24715     struct {
24716             uint32_t            : 8;
24717       __IOM uint32_t TMR10TRIGSEL : 8;          /*!< [15..8] Counter/Timer 10 Trigger Source Selection                         */
24718             uint32_t            : 16;
24719     } MODE10_b;
24720   } ;
24721   __IM  uint32_t  RESERVED15[3];
24722 
24723   union {
24724     __IOM uint32_t CTRL11;                      /*!< (@ 0x00000360) This includes the Control bit fields for timer
24725                                                                     11.                                                        */
24726 
24727     struct {
24728       __IOM uint32_t TMR11EN    : 1;            /*!< [0..0] Counter/Timer 11 Enable bit.                                       */
24729       __IOM uint32_t TMR11CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24730       __IOM uint32_t TMR11POL0  : 1;            /*!< [2..2] Counter/Timer 11 output 0 polarity.                                */
24731       __IOM uint32_t TMR11POL1  : 1;            /*!< [3..3] Counter/Timer 11 output 1 polarity.                                */
24732       __IOM uint32_t TMR11FN    : 4;            /*!< [7..4] Counter/Timer 11 Function Select.                                  */
24733       __IOM uint32_t TMR11CLK   : 8;            /*!< [15..8] Counter/Timer 11 Clock Select.                                    */
24734       __IOM uint32_t TMR11TMODE : 2;            /*!< [17..16] Counter/Timer 11 Trigger Mode                                    */
24735             uint32_t            : 6;
24736       __IOM uint32_t TMR11LMT   : 8;            /*!< [31..24] Counter/Timer 11 Pattern Limit Count.                            */
24737     } CTRL11_b;
24738   } ;
24739 
24740   union {
24741     __IOM uint32_t TIMER11;                     /*!< (@ 0x00000364) This register holds the running time or event
24742                                                                     count for timer 11.                                        */
24743 
24744     struct {
24745       __IOM uint32_t TIMER11    : 32;           /*!< [31..0] Counter/Timer 11                                                  */
24746     } TIMER11_b;
24747   } ;
24748 
24749   union {
24750     __IOM uint32_t TMR11CMP0;                   /*!< (@ 0x00000368) This contains the Compare limits for timer 11.
24751                                                                     This is the primary comparator that can
24752                                                                     be used to mark the END of a timer cycle
24753                                                                     (and thus restart the timer for repeat modes)              */
24754 
24755     struct {
24756       __IOM uint32_t TMR11CMP0  : 32;           /*!< [31..0] Counter/Timer 11 End Compare Register. For MEASURE mode
24757                                                      indicates the high phase sample count.                                    */
24758     } TMR11CMP0_b;
24759   } ;
24760 
24761   union {
24762     __IOM uint32_t TMR11CMP1;                   /*!< (@ 0x0000036C) This comparator is used as a secondary compare
24763                                                                     count for modes that generate pulses. For
24764                                                                     MEASURE mode indicates the low phase sample
24765                                                                     count.                                                     */
24766 
24767     struct {
24768       __IOM uint32_t TMR11CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24769                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24770                                                      be used first.                                                            */
24771     } TMR11CMP1_b;
24772   } ;
24773 
24774   union {
24775     __IOM uint32_t MODE11;                      /*!< (@ 0x00000370) The mode register contains optional mode controls
24776                                                                     for the timer                                              */
24777 
24778     struct {
24779             uint32_t            : 8;
24780       __IOM uint32_t TMR11TRIGSEL : 8;          /*!< [15..8] Counter/Timer 11 Trigger Source Selection                         */
24781             uint32_t            : 16;
24782     } MODE11_b;
24783   } ;
24784   __IM  uint32_t  RESERVED16[3];
24785 
24786   union {
24787     __IOM uint32_t CTRL12;                      /*!< (@ 0x00000380) This includes the Control bit fields for timer
24788                                                                     12.                                                        */
24789 
24790     struct {
24791       __IOM uint32_t TMR12EN    : 1;            /*!< [0..0] Counter/Timer 12 Enable bit.                                       */
24792       __IOM uint32_t TMR12CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24793       __IOM uint32_t TMR12POL0  : 1;            /*!< [2..2] Counter/Timer 12 output 0 polarity.                                */
24794       __IOM uint32_t TMR12POL1  : 1;            /*!< [3..3] Counter/Timer 12 output 1 polarity.                                */
24795       __IOM uint32_t TMR12FN    : 4;            /*!< [7..4] Counter/Timer 12 Function Select.                                  */
24796       __IOM uint32_t TMR12CLK   : 8;            /*!< [15..8] Counter/Timer 12 Clock Select.                                    */
24797       __IOM uint32_t TMR12TMODE : 2;            /*!< [17..16] Counter/Timer 12 Trigger Mode                                    */
24798             uint32_t            : 6;
24799       __IOM uint32_t TMR12LMT   : 8;            /*!< [31..24] Counter/Timer 12 Pattern Limit Count.                            */
24800     } CTRL12_b;
24801   } ;
24802 
24803   union {
24804     __IOM uint32_t TIMER12;                     /*!< (@ 0x00000384) This register holds the running time or event
24805                                                                     count for timer 12.                                        */
24806 
24807     struct {
24808       __IOM uint32_t TIMER12    : 32;           /*!< [31..0] Counter/Timer 12                                                  */
24809     } TIMER12_b;
24810   } ;
24811 
24812   union {
24813     __IOM uint32_t TMR12CMP0;                   /*!< (@ 0x00000388) This contains the Compare limits for timer 12.
24814                                                                     This is the primary comparator that can
24815                                                                     be used to mark the END of a timer cycle
24816                                                                     (and thus restart the timer for repeat modes)              */
24817 
24818     struct {
24819       __IOM uint32_t TMR12CMP0  : 32;           /*!< [31..0] Counter/Timer 12 End Compare Register. For MEASURE mode
24820                                                      indicates the high phase sample count.                                    */
24821     } TMR12CMP0_b;
24822   } ;
24823 
24824   union {
24825     __IOM uint32_t TMR12CMP1;                   /*!< (@ 0x0000038C) This comparator is used as a secondary compare
24826                                                                     count for modes that generate pulses. For
24827                                                                     MEASURE mode indicates the low phase sample
24828                                                                     count.                                                     */
24829 
24830     struct {
24831       __IOM uint32_t TMR12CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24832                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24833                                                      be used first.                                                            */
24834     } TMR12CMP1_b;
24835   } ;
24836 
24837   union {
24838     __IOM uint32_t MODE12;                      /*!< (@ 0x00000390) The mode register contains optional mode controls
24839                                                                     for the timer                                              */
24840 
24841     struct {
24842             uint32_t            : 8;
24843       __IOM uint32_t TMR12TRIGSEL : 8;          /*!< [15..8] Counter/Timer 12 Trigger Source Selection                         */
24844             uint32_t            : 16;
24845     } MODE12_b;
24846   } ;
24847   __IM  uint32_t  RESERVED17[3];
24848 
24849   union {
24850     __IOM uint32_t CTRL13;                      /*!< (@ 0x000003A0) This includes the Control bit fields for timer
24851                                                                     13.                                                        */
24852 
24853     struct {
24854       __IOM uint32_t TMR13EN    : 1;            /*!< [0..0] Counter/Timer 13 Enable bit.                                       */
24855       __IOM uint32_t TMR13CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24856       __IOM uint32_t TMR13POL0  : 1;            /*!< [2..2] Counter/Timer 13 output 0 polarity.                                */
24857       __IOM uint32_t TMR13POL1  : 1;            /*!< [3..3] Counter/Timer 13 output 1 polarity.                                */
24858       __IOM uint32_t TMR13FN    : 4;            /*!< [7..4] Counter/Timer 13 Function Select.                                  */
24859       __IOM uint32_t TMR13CLK   : 8;            /*!< [15..8] Counter/Timer 13 Clock Select.                                    */
24860       __IOM uint32_t TMR13TMODE : 2;            /*!< [17..16] Counter/Timer 13 Trigger Mode                                    */
24861             uint32_t            : 6;
24862       __IOM uint32_t TMR13LMT   : 8;            /*!< [31..24] Counter/Timer 13 Pattern Limit Count.                            */
24863     } CTRL13_b;
24864   } ;
24865 
24866   union {
24867     __IOM uint32_t TIMER13;                     /*!< (@ 0x000003A4) This register holds the running time or event
24868                                                                     count for timer 13.                                        */
24869 
24870     struct {
24871       __IOM uint32_t TIMER13    : 32;           /*!< [31..0] Counter/Timer 13                                                  */
24872     } TIMER13_b;
24873   } ;
24874 
24875   union {
24876     __IOM uint32_t TMR13CMP0;                   /*!< (@ 0x000003A8) This contains the Compare limits for timer 13.
24877                                                                     This is the primary comparator that can
24878                                                                     be used to mark the END of a timer cycle
24879                                                                     (and thus restart the timer for repeat modes)              */
24880 
24881     struct {
24882       __IOM uint32_t TMR13CMP0  : 32;           /*!< [31..0] Counter/Timer 13 End Compare Register. For MEASURE mode
24883                                                      indicates the high phase sample count.                                    */
24884     } TMR13CMP0_b;
24885   } ;
24886 
24887   union {
24888     __IOM uint32_t TMR13CMP1;                   /*!< (@ 0x000003AC) This comparator is used as a secondary compare
24889                                                                     count for modes that generate pulses. For
24890                                                                     MEASURE mode indicates the low phase sample
24891                                                                     count.                                                     */
24892 
24893     struct {
24894       __IOM uint32_t TMR13CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24895                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24896                                                      be used first.                                                            */
24897     } TMR13CMP1_b;
24898   } ;
24899 
24900   union {
24901     __IOM uint32_t MODE13;                      /*!< (@ 0x000003B0) The mode register contains optional mode controls
24902                                                                     for the timer                                              */
24903 
24904     struct {
24905             uint32_t            : 8;
24906       __IOM uint32_t TMR13TRIGSEL : 8;          /*!< [15..8] Counter/Timer 13 Trigger Source Selection                         */
24907             uint32_t            : 16;
24908     } MODE13_b;
24909   } ;
24910   __IM  uint32_t  RESERVED18[3];
24911 
24912   union {
24913     __IOM uint32_t CTRL14;                      /*!< (@ 0x000003C0) This includes the Control bit fields for timer
24914                                                                     14.                                                        */
24915 
24916     struct {
24917       __IOM uint32_t TMR14EN    : 1;            /*!< [0..0] Counter/Timer 14 Enable bit.                                       */
24918       __IOM uint32_t TMR14CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24919       __IOM uint32_t TMR14POL0  : 1;            /*!< [2..2] Counter/Timer 14 output 0 polarity.                                */
24920       __IOM uint32_t TMR14POL1  : 1;            /*!< [3..3] Counter/Timer 14 output 1 polarity.                                */
24921       __IOM uint32_t TMR14FN    : 4;            /*!< [7..4] Counter/Timer 14 Function Select.                                  */
24922       __IOM uint32_t TMR14CLK   : 8;            /*!< [15..8] Counter/Timer 14 Clock Select.                                    */
24923       __IOM uint32_t TMR14TMODE : 2;            /*!< [17..16] Counter/Timer 14 Trigger Mode                                    */
24924             uint32_t            : 6;
24925       __IOM uint32_t TMR14LMT   : 8;            /*!< [31..24] Counter/Timer 14 Pattern Limit Count.                            */
24926     } CTRL14_b;
24927   } ;
24928 
24929   union {
24930     __IOM uint32_t TIMER14;                     /*!< (@ 0x000003C4) This register holds the running time or event
24931                                                                     count for timer 14.                                        */
24932 
24933     struct {
24934       __IOM uint32_t TIMER14    : 32;           /*!< [31..0] Counter/Timer 14                                                  */
24935     } TIMER14_b;
24936   } ;
24937 
24938   union {
24939     __IOM uint32_t TMR14CMP0;                   /*!< (@ 0x000003C8) This contains the Compare limits for timer 14.
24940                                                                     This is the primary comparator that can
24941                                                                     be used to mark the END of a timer cycle
24942                                                                     (and thus restart the timer for repeat modes)              */
24943 
24944     struct {
24945       __IOM uint32_t TMR14CMP0  : 32;           /*!< [31..0] Counter/Timer 14 End Compare Register. For MEASURE mode
24946                                                      indicates the high phase sample count.                                    */
24947     } TMR14CMP0_b;
24948   } ;
24949 
24950   union {
24951     __IOM uint32_t TMR14CMP1;                   /*!< (@ 0x000003CC) This comparator is used as a secondary compare
24952                                                                     count for modes that generate pulses. For
24953                                                                     MEASURE mode indicates the low phase sample
24954                                                                     count.                                                     */
24955 
24956     struct {
24957       __IOM uint32_t TMR14CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24958                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24959                                                      be used first.                                                            */
24960     } TMR14CMP1_b;
24961   } ;
24962 
24963   union {
24964     __IOM uint32_t MODE14;                      /*!< (@ 0x000003D0) The mode register contains optional mode controls
24965                                                                     for the timer                                              */
24966 
24967     struct {
24968             uint32_t            : 8;
24969       __IOM uint32_t TMR14TRIGSEL : 8;          /*!< [15..8] Counter/Timer 14 Trigger Source Selection                         */
24970             uint32_t            : 16;
24971     } MODE14_b;
24972   } ;
24973   __IM  uint32_t  RESERVED19[3];
24974 
24975   union {
24976     __IOM uint32_t CTRL15;                      /*!< (@ 0x000003E0) This includes the Control bit fields for timer
24977                                                                     15.                                                        */
24978 
24979     struct {
24980       __IOM uint32_t TMR15EN    : 1;            /*!< [0..0] Counter/Timer 15 Enable bit.                                       */
24981       __IOM uint32_t TMR15CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24982       __IOM uint32_t TMR15POL0  : 1;            /*!< [2..2] Counter/Timer 15 output 0 polarity.                                */
24983       __IOM uint32_t TMR15POL1  : 1;            /*!< [3..3] Counter/Timer 15 output 1 polarity.                                */
24984       __IOM uint32_t TMR15FN    : 4;            /*!< [7..4] Counter/Timer 15 Function Select.                                  */
24985       __IOM uint32_t TMR15CLK   : 8;            /*!< [15..8] Counter/Timer 15 Clock Select.                                    */
24986       __IOM uint32_t TMR15TMODE : 2;            /*!< [17..16] Counter/Timer 15 Trigger Mode                                    */
24987             uint32_t            : 6;
24988       __IOM uint32_t TMR15LMT   : 8;            /*!< [31..24] Counter/Timer 15 Pattern Limit Count.                            */
24989     } CTRL15_b;
24990   } ;
24991 
24992   union {
24993     __IOM uint32_t TIMER15;                     /*!< (@ 0x000003E4) This register holds the running time or event
24994                                                                     count for timer 15.                                        */
24995 
24996     struct {
24997       __IOM uint32_t TIMER15    : 32;           /*!< [31..0] Counter/Timer 15                                                  */
24998     } TIMER15_b;
24999   } ;
25000 
25001   union {
25002     __IOM uint32_t TMR15CMP0;                   /*!< (@ 0x000003E8) This contains the Compare limits for timer 15.
25003                                                                     This is the primary comparator that can
25004                                                                     be used to mark the END of a timer cycle
25005                                                                     (and thus restart the timer for repeat modes)              */
25006 
25007     struct {
25008       __IOM uint32_t TMR15CMP0  : 32;           /*!< [31..0] Counter/Timer 15 End Compare Register. For MEASURE mode
25009                                                      indicates the high phase sample count.                                    */
25010     } TMR15CMP0_b;
25011   } ;
25012 
25013   union {
25014     __IOM uint32_t TMR15CMP1;                   /*!< (@ 0x000003EC) This comparator is used as a secondary compare
25015                                                                     count for modes that generate pulses. For
25016                                                                     MEASURE mode indicates the low phase sample
25017                                                                     count.                                                     */
25018 
25019     struct {
25020       __IOM uint32_t TMR15CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25021                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25022                                                      be used first.                                                            */
25023     } TMR15CMP1_b;
25024   } ;
25025 
25026   union {
25027     __IOM uint32_t MODE15;                      /*!< (@ 0x000003F0) The mode register contains optional mode controls
25028                                                                     for the timer                                              */
25029 
25030     struct {
25031             uint32_t            : 8;
25032       __IOM uint32_t TMR15TRIGSEL : 8;          /*!< [15..8] Counter/Timer 15 Trigger Source Selection                         */
25033             uint32_t            : 16;
25034     } MODE15_b;
25035   } ;
25036 } TIMER_Type;                                   /*!< Size = 1012 (0x3f4)                                                       */
25037 
25038 
25039 
25040 /* =========================================================================================================================== */
25041 /* ================                                           UART0                                           ================ */
25042 /* =========================================================================================================================== */
25043 
25044 
25045 /**
25046   * @brief Serial UART (UART0)
25047   */
25048 
25049 typedef struct {                                /*!< (@ 0x4001C000) UART0 Structure                                            */
25050 
25051   union {
25052     __IOM uint32_t DR;                          /*!< (@ 0x00000000) UART Data                                                  */
25053 
25054     struct {
25055       __IOM uint32_t DATA       : 8;            /*!< [7..0] Receive (read) data character. Transmit (write) data
25056                                                      character.                                                                */
25057       __IOM uint32_t FEDATA     : 1;            /*!< [8..8] Framing error. When set to 1, it indicates that the received
25058                                                      character did not have a valid stop bit (a valid stop bit
25059                                                      is 1). In FIFO mode, this error is associated with the
25060                                                      character at the top of the FIFO.                                         */
25061       __IOM uint32_t PEDATA     : 1;            /*!< [9..9] Parity error. When set to 1, it indicates that the parity
25062                                                      of the received data character does not match the parity
25063                                                      that the EPS and SPS bits in the Line Control Register,
25064                                                      UARTLCRH select. In FIFO mode, this error is associated
25065                                                      with the character at the top of the FIFO.                                */
25066       __IOM uint32_t BEDATA     : 1;            /*!< [10..10] Break error. This bit is set to 1 if a break condition
25067                                                      was detected, indicating that the received data input was
25068                                                      held LOW for longer than a full-word transmission time
25069                                                      (defined as start, data, parity and stop bits). In FIFO
25070                                                      mode, this error is associated with the character at the
25071                                                      top of the FIFO. When a break occurs, only one 0 character
25072                                                      is loaded into the FIFO. The next character is only enabled
25073                                                      after the receive data input goes to a 1 (marking state),
25074                                                      and the next valid start bit is received.                                 */
25075       __IOM uint32_t OEDATA     : 1;            /*!< [11..11] Overrun error. This bit is set to 1 if data is received
25076                                                      and the receive FIFO is already full. This is cleared to
25077                                                      0 once there is an empty space in the FIFO and a new character
25078                                                      can be written to it.                                                     */
25079             uint32_t            : 20;
25080     } DR_b;
25081   } ;
25082 
25083   union {
25084     __IOM uint32_t RSR;                         /*!< (@ 0x00000004) UART Status                                                */
25085 
25086     struct {
25087       __IOM uint32_t FESTAT     : 1;            /*!< [0..0] Framing error. When set to 1, it indicates that the received
25088                                                      character did not have a valid stop bit (a valid stop bit
25089                                                      is 1). This bit is cleared to 0 by a write to UARTECR.
25090                                                      In FIFO mode, this error is associated with the character
25091                                                      at the top of the FIFO.                                                   */
25092       __IOM uint32_t PESTAT     : 1;            /*!< [1..1] Parity error. When set to 1, it indicates that the parity
25093                                                      of the received data character does not match the parity
25094                                                      that the EPS and SPS bits in the Line Control Register,
25095                                                      UARTLCRH select. This bit is cleared to 0 by a write to
25096                                                      UARTECR. In FIFO mode, this error is associated with the
25097                                                      character at the top of the FIFO.                                         */
25098       __IOM uint32_t BESTAT     : 1;            /*!< [2..2] Break error. This bit is set to 1 if a break condition
25099                                                      was detected, indicating that the received data input was
25100                                                      held LOW for longer than a full-word transmission time
25101                                                      (defined as start, data, parity, and stop bits). This bit
25102                                                      is cleared to 0 after a write to UARTECR. In FIFO mode,
25103                                                      this error is associated with the character at the top
25104                                                      of the FIFO. When a break occurs, only one 0 character
25105                                                      is loaded into the FIFO. The next character is only enabled
25106                                                      after the receive data input goes to a 1 (marking state)
25107                                                      an                                                                        */
25108       __IOM uint32_t OESTAT     : 1;            /*!< [3..3] Overrun error. This bit is set to 1 if data is received
25109                                                      and the FIFO is already full. This bit is cleared to 0
25110                                                      by a write to UARTECR. The FIFO contents remain valid because
25111                                                      no more data is written when the FIFO is full, only the
25112                                                      contents of the shift register are overwritten. The CPU
25113                                                      must now read the data, to empty the FIFO.                                */
25114             uint32_t            : 28;
25115     } RSR_b;
25116   } ;
25117   __IM  uint32_t  RESERVED[4];
25118 
25119   union {
25120     __IOM uint32_t FR;                          /*!< (@ 0x00000018) Flags                                                      */
25121 
25122     struct {
25123       __IOM uint32_t CTS        : 1;            /*!< [0..0] Clear to send. This bit is the complement of the UART
25124                                                      clear to send, nUARTCTS, modem status input. That is, the
25125                                                      bit is 1 when nUARTCTS is LOW.                                            */
25126       __IOM uint32_t DSR        : 1;            /*!< [1..1] Data set ready. This bit is the complement of the UART
25127                                                      data set ready, nUARTDSR, modem status input. That is,
25128                                                      the bit is 1 when nUARTDSR is LOW.                                        */
25129       __IOM uint32_t DCD        : 1;            /*!< [2..2] Data carrier detect. This bit is the complement of the
25130                                                      UART data carrier detect, nUARTDCD, modem status input.
25131                                                      That is, the bit is 1 when nUARTDCD is LOW.                               */
25132       __IOM uint32_t BUSY       : 1;            /*!< [3..3] UART busy. If this bit is set to 1, the UART is busy
25133                                                      transmitting data. This bit remains set until the complete
25134                                                      byte, including all the stop bits, has been sent from the
25135                                                      shift register. This bit is set as soon as the transmit
25136                                                      FIFO becomes non-empty, regardless of whether the UART
25137                                                      is enabled or not.                                                        */
25138       __IOM uint32_t RXFE       : 1;            /*!< [4..4] Receive FIFO empty. The meaning of this bit depends on
25139                                                      the state of the FEN bit in the UARTLCRH Register. If the
25140                                                      FIFO is disabled, this bit is set when the receive holding
25141                                                      register is empty. If the FIFO is enabled, the RXFE bit
25142                                                      is set when the receive FIFO is empty.                                    */
25143       __IOM uint32_t TXFF       : 1;            /*!< [5..5] Transmit FIFO full. The meaning of this bit depends on
25144                                                      the state of the FEN bit in the UARTLCRH Register. If the
25145                                                      FIFO is disabled, this bit is set when the transmit holding
25146                                                      register is full. If the FIFO is enabled, the TXFF bit
25147                                                      is set when the transmit FIFO is full.                                    */
25148       __IOM uint32_t RXFF       : 1;            /*!< [6..6] Receive FIFO full. The meaning of this bit depends on
25149                                                      the state of the FEN bit in the UARTLCRH Register. If the
25150                                                      FIFO is disabled, this bit is set when the receive holding
25151                                                      register is full. If the FIFO is enabled, the RXFF bit
25152                                                      is set when the receive FIFO is full.                                     */
25153       __IOM uint32_t TXFE       : 1;            /*!< [7..7] Transmit FIFO empty. The meaning of this bit depends
25154                                                      on the state of the FEN bit in the Line Control Register,
25155                                                      UARTLCRH. If the FIFO is disabled, this bit is set when
25156                                                      the transmit holding register is empty. If the FIFO is
25157                                                      enabled, the TXFE bit is set when the transmit FIFO is
25158                                                      empty. This bit does not indicate if there is data in the
25159                                                      transmit shift register.                                                  */
25160       __IOM uint32_t TXBUSY     : 1;            /*!< [8..8] This bit holds the transmit BUSY indicator.                        */
25161             uint32_t            : 23;
25162     } FR_b;
25163   } ;
25164   __IM  uint32_t  RESERVED1;
25165 
25166   union {
25167     __IOM uint32_t ILPR;                        /*!< (@ 0x00000020) IrDA Counter                                               */
25168 
25169     struct {
25170       __IOM uint32_t ILPDVSR    : 8;            /*!< [7..0] 8-bit low-power divisor value. These bits are cleared
25171                                                      to 0 at reset. Programming a zero value results in no IrLPBaud16
25172                                                      pulses being generated.                                                   */
25173             uint32_t            : 24;
25174     } ILPR_b;
25175   } ;
25176 
25177   union {
25178     __IOM uint32_t IBRD;                        /*!< (@ 0x00000024) Integer Baud Rate Divisor                                  */
25179 
25180     struct {
25181       __IOM uint32_t DIVINT     : 16;           /*!< [15..0] These bits hold the baud integer divisor. These bits
25182                                                      are cleared to 0 on reset.                                                */
25183             uint32_t            : 16;
25184     } IBRD_b;
25185   } ;
25186 
25187   union {
25188     __IOM uint32_t FBRD;                        /*!< (@ 0x00000028) Fractional Baud Rate Divisor                               */
25189 
25190     struct {
25191       __IOM uint32_t DIVFRAC    : 6;            /*!< [5..0] These bits hold the baud fractional divisor. These bits
25192                                                      are cleared to 0 on reset.                                                */
25193             uint32_t            : 26;
25194     } FBRD_b;
25195   } ;
25196 
25197   union {
25198     __IOM uint32_t LCRH;                        /*!< (@ 0x0000002C) Line Control High                                          */
25199 
25200     struct {
25201       __IOM uint32_t BRK        : 1;            /*!< [0..0] This bit holds the break set. If this bit is set to 1,
25202                                                      a low-level is continually output on the UARTTXD output,
25203                                                      after completing transmission of the current character.
25204                                                      For the proper execution of the break command, the software
25205                                                      must set this bit for at least two complete frames. For
25206                                                      normal use, this bit must be cleared to 0.                                */
25207       __IOM uint32_t PEN        : 1;            /*!< [1..1] This bit holds the parity enable. 0 = parity is disabled
25208                                                      and no parity bit added to the data frame. 1 = parity checking
25209                                                      and generation is enabled.                                                */
25210       __IOM uint32_t EPS        : 1;            /*!< [2..2] This bit holds the even parity select. Controls the type
25211                                                      of parity the UART uses during transmission and reception:
25212                                                      0 = odd parity. The UART generates or checks for an odd
25213                                                      number of 1s in the data and parity bits. 1 = even parity.
25214                                                      The UART generates or checks for an even number of 1s in
25215                                                      the data and parity bits. This bit has no effect when the
25216                                                      PEN bit disables parity checking and generation.                          */
25217       __IOM uint32_t STP2       : 1;            /*!< [3..3] This bit holds the two stop bits select. If this bit
25218                                                      is set to 1, two stop bits are transmitted at the end of
25219                                                      the frame. The receive logic does not check for two stop
25220                                                      bits being received.                                                      */
25221       __IOM uint32_t FEN        : 1;            /*!< [4..4] This bit holds the FIFO enable. 0 = FIFOs are disabled
25222                                                      (character mode) that is, the FIFOs become 1-byte-deep
25223                                                      holding registers. 1 = transmit and receive FIFO buffers
25224                                                      are enabled (FIFO mode).                                                  */
25225       __IOM uint32_t WLEN       : 2;            /*!< [6..5] These bits hold the write length. These bits indicate
25226                                                      the number of data bits transmitted or received in a frame
25227                                                      as follows: b11 = 8 bits, b10 = 7 bits, b01 = 6 bits, b00
25228                                                      = 5 bits.                                                                 */
25229       __IOM uint32_t SPS        : 1;            /*!< [7..7] This bit holds the stick parity select. If the EPS bit
25230                                                      is 0 then the parity bit is transmitted and checked as
25231                                                      a 1. If the EPS bit is 1 then the parity bit is transmitted
25232                                                      and checked as a 0. This bit has no effect when the PEN
25233                                                      bit disables parity checking and generation.                              */
25234             uint32_t            : 24;
25235     } LCRH_b;
25236   } ;
25237 
25238   union {
25239     __IOM uint32_t CR;                          /*!< (@ 0x00000030) Control                                                    */
25240 
25241     struct {
25242       __IOM uint32_t UARTEN     : 1;            /*!< [0..0] This bit is the UART enable. 0 = UART is disabled. If
25243                                                      the UART is disabled in the middle of transmission or reception,
25244                                                      it completes the current character before stopping. 1 =
25245                                                      the UART is enabled. Data transmission and reception occurs
25246                                                      for either UART signals or SIR signals depending on the
25247                                                      setting of the SIREN bit.                                                 */
25248       __IOM uint32_t SIREN      : 1;            /*!< [1..1] This bit is the SIR ENDEC enable. If this bit is set
25249                                                      to 1, the IrDA SIR ENDEC is enabled. This bit has no effect
25250                                                      if the UART is not enabled by bit 0 being set to 1. When
25251                                                      the IrDA SIR ENDEC is enabled, data is transmitted and
25252                                                      received on nSIROUT and SIRIN. UARTTXD remains in the marking
25253                                                      state (set to 1). Signal transitions on UARTRXD or modem
25254                                                      status inputs have no effect. When the IrDA SIR ENDEC is
25255                                                      disabled, nSIROUT remains cleared to 0 (no light pulse
25256                                                      generated), and signal transitions on SIRIN have no eff                   */
25257       __IOM uint32_t SIRLP      : 1;            /*!< [2..2] This bit is the SIR low power select. This bit selects
25258                                                      the IrDA encoding mode. If this bit is cleared to 0, low-level
25259                                                      bits are transmitted as an active high pulse with a width
25260                                                      of 3/16th of the bit period. If this bit is set to 1, low-level
25261                                                      bits are transmitted with a pulse width which is 3 times
25262                                                      the period of the IrLPBaud16 input signal, regardless of
25263                                                      the selected bit rate. Setting this bit uses less power,
25264                                                      but might reduce transmission distances.                                  */
25265       __IOM uint32_t CLKEN      : 1;            /*!< [3..3] This bit is the UART clock enable.                                 */
25266       __IOM uint32_t CLKSEL     : 3;            /*!< [6..4] This bitfield is the UART clock select.                            */
25267       __IOM uint32_t LBE        : 1;            /*!< [7..7] This bit is the loopback enable. If this bit is set to
25268                                                      1 and the SIREN bit is set to 1 and the SIRTEST bit in
25269                                                      the Test Control Register, UARTTCR is set to 1, then the
25270                                                      nSIROUT path is inverted, and fed through to the SIRIN
25271                                                      path. The SIRTEST bit in the test register must be set
25272                                                      to 1 to override the normal half-duplex SIR operation.
25273                                                      This must be the requirement for accessing the test registers
25274                                                      during normal operation, and SIRTEST must be cleared to
25275                                                      0 when loopback testing is finished. This feature reduces
25276                                                      the                                                                       */
25277       __IOM uint32_t TXE        : 1;            /*!< [8..8] This bit is the transmit enable. If this bit is set to
25278                                                      1, the transmit section of the UART is enabled. Data transmission
25279                                                      occurs for either UART signals, or SIR signals depending
25280                                                      on the setting of the SIREN bit. When the UART is disabled
25281                                                      in the middle of transmission, it completes the current
25282                                                      character before stopping.                                                */
25283       __IOM uint32_t RXE        : 1;            /*!< [9..9] This bit is the receive enable. If this bit is set to
25284                                                      1, the receive section of the UART is enabled. Data reception
25285                                                      occurs for either UART signals or SIR signals depending
25286                                                      on the setting of the SIREN bit. When the UART is disabled
25287                                                      in the middle of reception, it completes the current character
25288                                                      before stopping.                                                          */
25289       __IOM uint32_t DTR        : 1;            /*!< [10..10] This bit enables data transmit ready. This bit is the
25290                                                      complement of the UART data transmit ready, nUARTDTR, modem
25291                                                      status output. That is, when the bit is programmed to a
25292                                                      1 then nUARTDTR is LOW.                                                   */
25293       __IOM uint32_t RTS        : 1;            /*!< [11..11] This bit enables request to send. This bit is the complement
25294                                                      of the UART request to send, nUARTRTS, modem status output.
25295                                                      That is, when the bit is programmed to a 1 then nUARTRTS
25296                                                      is LOW.                                                                   */
25297       __IOM uint32_t OUT1       : 1;            /*!< [12..12] This bit is the complement of the UART Out1 (nUARTOut1)
25298                                                      modem status output. That is, when the bit is programmed
25299                                                      to a 1 the output is 0. For DTE this can be used as Data
25300                                                      Carrier Detect (DCD).                                                     */
25301       __IOM uint32_t OUT2       : 1;            /*!< [13..13] This bit is the complement of the UART Out2 (nUARTOut2)
25302                                                      modem status output. That is, when the bit is programmed
25303                                                      to a 1, the output is 0. For DTE this can be used as Ring
25304                                                      Indicator (RI).                                                           */
25305       __IOM uint32_t RTSEN      : 1;            /*!< [14..14] This bit enables RTS hardware flow control. If this
25306                                                      bit is set to 1, RTS hardware flow control is enabled.
25307                                                      Data is only requested when there is space in the receive
25308                                                      FIFO for it to be received.                                               */
25309       __IOM uint32_t CTSEN      : 1;            /*!< [15..15] This bit enables CTS hardware flow control. If this
25310                                                      bit is set to 1, CTS hardware flow control is enabled.
25311                                                      Data is only transmitted when the nUARTCTS signal is asserted.            */
25312             uint32_t            : 16;
25313     } CR_b;
25314   } ;
25315 
25316   union {
25317     __IOM uint32_t IFLS;                        /*!< (@ 0x00000034) FIFO Interrupt Level Select                                */
25318 
25319     struct {
25320       __IOM uint32_t TXIFLSEL   : 3;            /*!< [2..0] These bits hold the transmit FIFO interrupt level.                 */
25321       __IOM uint32_t RXIFLSEL   : 3;            /*!< [5..3] These bits hold the receive FIFO interrupt level.                  */
25322             uint32_t            : 26;
25323     } IFLS_b;
25324   } ;
25325 
25326   union {
25327     __IOM uint32_t IER;                         /*!< (@ 0x00000038) Interrupt Enable                                           */
25328 
25329     struct {
25330       __IOM uint32_t TXCMPMIM   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt enable.                   */
25331       __IOM uint32_t CTSMIM     : 1;            /*!< [1..1] This bit holds the modem CTS interrupt enable.                     */
25332       __IOM uint32_t DCDMIM     : 1;            /*!< [2..2] This bit holds the modem DCD interrupt enable.                     */
25333       __IOM uint32_t DSRMIM     : 1;            /*!< [3..3] This bit holds the modem DSR interrupt enable.                     */
25334       __IOM uint32_t RXIM       : 1;            /*!< [4..4] This bit holds the receive interrupt enable.                       */
25335       __IOM uint32_t TXIM       : 1;            /*!< [5..5] This bit holds the transmit interrupt enable.                      */
25336       __IOM uint32_t RTIM       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt enable.               */
25337       __IOM uint32_t FEIM       : 1;            /*!< [7..7] This bit holds the framing error interrupt enable.                 */
25338       __IOM uint32_t PEIM       : 1;            /*!< [8..8] This bit holds the parity error interrupt enable.                  */
25339       __IOM uint32_t BEIM       : 1;            /*!< [9..9] This bit holds the break error interrupt enable.                   */
25340       __IOM uint32_t OEIM       : 1;            /*!< [10..10] This bit holds the overflow interrupt enable.                    */
25341             uint32_t            : 21;
25342     } IER_b;
25343   } ;
25344 
25345   union {
25346     __IOM uint32_t IES;                         /*!< (@ 0x0000003C) Interrupt Status                                           */
25347 
25348     struct {
25349       __IOM uint32_t TXCMPMRIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status.                   */
25350       __IOM uint32_t CTSMRIS    : 1;            /*!< [1..1] This bit holds the nUARTCTS modem interrupt status. Returns
25351                                                      the raw interrupt state of the UARTCTSINTR interrupt.                     */
25352       __IOM uint32_t DCDMRIS    : 1;            /*!< [2..2] This bit holds the nUARTDCD modem interrupt status. Returns
25353                                                      the raw interrupt state of the UARTDCDINTR interrupt.                     */
25354       __IOM uint32_t DSRMRIS    : 1;            /*!< [3..3] This bit holds the nUARTDSR modem interrupt status. Returns
25355                                                      the raw interrupt state of the UARTDSRINTR interrupt.                     */
25356       __IOM uint32_t RXRIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status. Returns
25357                                                      the raw interrupt state of the UARTRXINTR interrupt.                      */
25358       __IOM uint32_t TXRIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status. Returns
25359                                                      the raw interrupt state of the UARTTXINTR interrupt.                      */
25360       __IOM uint32_t RTRIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status.
25361                                                      Returns the raw interrupt state of the UARTRTINTR interrupt.              */
25362       __IOM uint32_t FERIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status. Returns
25363                                                      the raw interrupt state of the UARTFEINTR interrupt.                      */
25364       __IOM uint32_t PERIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status. Returns
25365                                                      the raw interrupt state of the UARTPEINTR interrupt.                      */
25366       __IOM uint32_t BERIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status. Returns
25367                                                      the raw interrupt state of the UARTBEINTR interrupt.                      */
25368       __IOM uint32_t OERIS      : 1;            /*!< [10..10] This bit holds the overrun interrupt status. Returns
25369                                                      the raw interrupt state of the UARTOEINTR interrupt.                      */
25370             uint32_t            : 21;
25371     } IES_b;
25372   } ;
25373 
25374   union {
25375     __IOM uint32_t MIS;                         /*!< (@ 0x00000040) Masked Interrupt Status                                    */
25376 
25377     struct {
25378       __IOM uint32_t TXCMPMMIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status masked.            */
25379       __IOM uint32_t CTSMMIS    : 1;            /*!< [1..1] This bit holds the nUARTCTS modem masked interrupt status.
25380                                                      Returns the masked interrupt state of the UARTCTSINTR interrupt.          */
25381       __IOM uint32_t DCDMMIS    : 1;            /*!< [2..2] This bit holds the nUARTDCD modem masked interrupt status.
25382                                                      Returns the masked interrupt state of the UARTDCDINTR interrupt.          */
25383       __IOM uint32_t DSRMMIS    : 1;            /*!< [3..3] This bit holds the nUARTDSR modem masked interrupt status.
25384                                                      Returns the masked interrupt state of the UARTDSRINTR interrupt.          */
25385       __IOM uint32_t RXMIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status masked. Returns
25386                                                      the masked interrupt state of the UARTRXINTR interrupt.                   */
25387       __IOM uint32_t TXMIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status masked.
25388                                                      Returns the masked interrupt state of the UARTTXINTR interrupt.           */
25389       __IOM uint32_t RTMIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status masked.
25390                                                      Returns the masked interrupt state of the UARTRTINTR interrupt.           */
25391       __IOM uint32_t FEMIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status masked.
25392                                                      Returns the masked interrupt state of the UARTFEINTR interrupt.           */
25393       __IOM uint32_t PEMIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status masked.
25394                                                      Returns the masked interrupt state of the UARTPEINTR interrupt.           */
25395       __IOM uint32_t BEMIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status masked.
25396                                                      Returns the masked interrupt state of the UARTBEINTR interrupt.           */
25397       __IOM uint32_t OEMIS      : 1;            /*!< [10..10] This bit holds the overrun interrupt status masked.
25398                                                      Returns the masked interrupt state of the UARTOEINTR interrupt.           */
25399             uint32_t            : 21;
25400     } MIS_b;
25401   } ;
25402 
25403   union {
25404     __IOM uint32_t IEC;                         /*!< (@ 0x00000044) Interrupt Clear                                            */
25405 
25406     struct {
25407       __IOM uint32_t TXCMPMIC   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt clear.                    */
25408       __IOM uint32_t CTSMIC     : 1;            /*!< [1..1] This bit holds the nUARTCTS modem interrupt clear. Clears
25409                                                      the UARTCTSINTR interrupt.                                                */
25410       __IOM uint32_t DCDMIC     : 1;            /*!< [2..2] This bit holds the nUARTDCD modem interrupt clear. Clears
25411                                                      the UARTDCDINTR interrupt.                                                */
25412       __IOM uint32_t DSRMIC     : 1;            /*!< [3..3] This bit holds the nUARTDSR modem interrupt clear. Clears
25413                                                      the UARTDSRINTR interrupt.                                                */
25414       __IOM uint32_t RXIC       : 1;            /*!< [4..4] This bit holds the receive interrupt clear. Clears the
25415                                                      UARTRXINTR interrupt.                                                     */
25416       __IOM uint32_t TXIC       : 1;            /*!< [5..5] This bit holds the transmit interrupt clear. Clears the
25417                                                      UARTTXINTR interrupt.                                                     */
25418       __IOM uint32_t RTIC       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt clear. Clears
25419                                                      the UARTRTINTR interrupt.                                                 */
25420       __IOM uint32_t FEIC       : 1;            /*!< [7..7] This bit holds the framing error interrupt clear. Clears
25421                                                      the UARTFEINTR interrupt.                                                 */
25422       __IOM uint32_t PEIC       : 1;            /*!< [8..8] This bit holds the parity error interrupt clear. Clears
25423                                                      the UARTPEINTR interrupt.                                                 */
25424       __IOM uint32_t BEIC       : 1;            /*!< [9..9] This bit holds the break error interrupt clear. Clears
25425                                                      the UARTBEINTR interrupt.                                                 */
25426       __IOM uint32_t OEIC       : 1;            /*!< [10..10] This bit holds the overrun interrupt clear. Clears
25427                                                      the UARTOEINTR interrupt.                                                 */
25428             uint32_t            : 21;
25429     } IEC_b;
25430   } ;
25431 } UART0_Type;                                   /*!< Size = 72 (0x48)                                                          */
25432 
25433 
25434 
25435 /* =========================================================================================================================== */
25436 /* ================                                          USBPHY                                           ================ */
25437 /* =========================================================================================================================== */
25438 
25439 
25440 /**
25441   * @brief USBPHY device register descriptions. (USBPHY)
25442   */
25443 
25444 typedef struct {                                /*!< (@ 0x400B4000) USBPHY Structure                                           */
25445 
25446   union {
25447     __IOM uint32_t REG00;                       /*!< (@ 0x00000000) Register description here                                  */
25448 
25449     struct {
25450       __IOM uint32_t BF20       : 3;            /*!< [2..0] This bitfield is reserved.                                         */
25451       __IOM uint32_t BF43       : 2;            /*!< [4..3] BG observation enable signal. Active low. When enabled,
25452                                                      vref 400mV can be observed through USB0PP/USB0PN                          */
25453       __IOM uint32_t BF75       : 3;            /*!< [7..5] Manually set the Rx Clock phase select. These bits will
25454                                                      tune the HS RX path sample timing between digital and analog
25455                                                      inside PHY: 3'b000 represents the earliest phase 3'b111
25456                                                      represents the latest phase The delay associated with each
25457                                                      step is 256ps                                                             */
25458             uint32_t            : 24;
25459     } REG00_b;
25460   } ;
25461 
25462   union {
25463     __IOM uint32_t REG04;                       /*!< (@ 0x00000004) Register description here                                  */
25464 
25465     struct {
25466       __IOM uint32_t BF20       : 3;            /*!< [2..0] Manually set the Tx Clock phase select. These bits will
25467                                                      tune the HS TX path sample timing between digital and analog
25468                                                      inside PHY 3'b000 represents the earliest phase 3'b111
25469                                                      represents the latest phase The delay associated with each
25470                                                      step is 256ps                                                             */
25471       __IOM uint32_t BF43       : 2;            /*!< [4..3] Squelch detector bias current tuning, 2'b00 represents
25472                                                      the minimum bias current 2'b11 represents the maximum bias
25473                                                      current                                                                   */
25474       __IOM uint32_t BF55       : 1;            /*!< [5..5] This bitfield is reserved.                                         */
25475       __IOM uint32_t BF76       : 2;            /*!< [7..6] disconnect detector bias current tuning                            */
25476             uint32_t            : 24;
25477     } REG04_b;
25478   } ;
25479 
25480   union {
25481     __IOM uint32_t REG08;                       /*!< (@ 0x00000008) Register description here                                  */
25482 
25483     struct {
25484       __IOM uint32_t BF30       : 4;            /*!< [3..0] 2'b00 represents the minimum bias current 2'b11 represents
25485                                                      the maximum bias current Rx squelch trigger point configures.
25486                                                      Allows tuning of the squelch trigger point in order to
25487                                                      compensate for package and board level parasitic. 4'b0000:112.5mV
25488                                                      4'b0001:150mV 4'b0010:87.5mV 4'b0011:162.5mV 4'b0100:100mV
25489                                                      4'b0101:137.5mV 4'b0110:75mV 4'b0111:150mV 4'b1000:125mV
25490                                                      4'b1001:162.5mV 4'b1010:100mV 4'b1011:175mV 4'b1100:150mV(default)
25491                                                      4'b1101:187.5mV 4'b1110:125mV 4'b1111:200mV                               */
25492       __IOM uint32_t BF64       : 3;            /*!< [6..4] HS eye height tuning 3'b000:400mV(default) 3'b001:475mV
25493                                                      3'b010:350mV 3'b011:500mV 3'b100:412.5mV 3'b101:425mV 3'b110:437.5mV
25494                                                      3'b111:450mV                                                              */
25495       __IOM uint32_t BF77       : 1;            /*!< [7..7] digital squelch filter select, this bit is used to filter
25496                                                      the glitch on the HS RX squelch signal. 1: 1 clock cycle
25497                                                      filter 0: 2 clock cycle fitter                                            */
25498             uint32_t            : 24;
25499     } REG08_b;
25500   } ;
25501 
25502   union {
25503     __IOM uint32_t REG0C;                       /*!< (@ 0x0000000C) Register description here                                  */
25504 
25505     struct {
25506       __IOM uint32_t BF10       : 2;            /*!< [1..0] BG output voltage reference adjust, normally these bits
25507                                                      are recommended to be kept as the default values. 00: standard
25508                                                      center level around 1.25v output, recommended 01: relative
25509                                                      higher output 1x: relative higher output                                  */
25510       __IOM uint32_t BF62       : 5;            /*!< [6..2] 45ohm HS ODT value tuning and FS/LS driver strength tuning
25511                                                      5'b11111: smallest HS ODT value and largest FS/LS driver
25512                                                      strength and fastest FS/LS slew rate 5'b10000: biggest
25513                                                      HS ODT value and smallest FS/LS driver strength and slowest
25514                                                      FS/LS slew rate                                                           */
25515       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
25516             uint32_t            : 24;
25517     } REG0C_b;
25518   } ;
25519 
25520   union {
25521     __IOM uint32_t REG10;                       /*!< (@ 0x00000010) Register description here                                  */
25522 
25523     struct {
25524       __IOM uint32_t BF00       : 1;            /*!< [0..0] Bypass squelch trigger point configure in chirp modes
25525                                                      , active high, keep the default value is strongly recommended
25526                                                      . 1: Bypass squelch trigger point configure in chirp modes
25527                                                      , 0: squelch trigger point set to 250mV in chirp modes.                   */
25528       __IOM uint32_t BF11       : 1;            /*!< [1..1] Turn off LS/FS differential receiver in suspend mode,
25529                                                      active low 1: keep the LS/FS differential receiver , pin
25530                                                      fss_rxrcv will toggling according to the DP/DM state 0:
25531                                                      turn off the LS/FS differential receiver, pin fss_rxrcv
25532                                                      will not toggling according to the DP/DM state                            */
25533       __IOM uint32_t BF22       : 1;            /*!< [2..2] Half bit pre-emphasis enable. Active high 1: half bit
25534                                                      pre-emphasize mode, recommended 0: full bit pre-emphasize
25535                                                      mode                                                                      */
25536       __IOM uint32_t BF33       : 1;            /*!< [3..3] Single ended disconnect detection enable, active high.
25537                                                      1: enable Single ended disconnect detection 0: disenable
25538                                                      Single ended disconnect detection                                         */
25539       __IOM uint32_t BF74       : 4;            /*!< [7..4] HOST disconnect detection trigger point. Only valid in
25540                                                      host mode. Allows compensation for package and board level
25541                                                      parasitics which tend to drop in the input voltage. 4'b0000:625mV
25542                                                      4'b0001:675mV 4'b0010:612.5mV 4'b0011:575mV 4'b0100:550mV
25543                                                      4'b0101:600mV (default) 4'b0110:537.5mV 4'b0111:500mV 4'b1000:600mV
25544                                                      4'b1001:650mV 4'b1010:587.5mV 4'b1011:550mV 4'b1100:575mV
25545                                                      4'b1101:625mV 4'b1110:562.5mV 4'b1111:525mV                               */
25546             uint32_t            : 24;
25547     } REG10_b;
25548   } ;
25549 
25550   union {
25551     __IOM uint32_t REG14;                       /*!< (@ 0x00000014) Register description here                                  */
25552 
25553     struct {
25554       __IOM uint32_t BF00       : 1;            /*!< [0..0] Dflop output select signal delay compared with digital
25555                                                      clock enable signal 1'b0:3 clocks 1'b1:2 clocks                           */
25556       __IOM uint32_t BF11       : 1;            /*!< [1..1] PLL bandwidth option 1'b0 default 1'b1 increases the
25557                                                      PLL bandwidth                                                             */
25558       __IOM uint32_t BF42       : 3;            /*!< [4..2] Tx HS pre-emphasis strength 3'b111 represents the strongest
25559                                                      , 3'b000 the weakest                                                      */
25560       __IOM uint32_t BF55       : 1;            /*!< [5..5] PLL feedback divider ratio option.                                 */
25561       __IOM uint32_t BF66       : 1;            /*!< [6..6] BF66 field description needed.                                     */
25562       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
25563             uint32_t            : 24;
25564     } REG14_b;
25565   } ;
25566 
25567   union {
25568     __IOM uint32_t REG18;                       /*!< (@ 0x00000018) Register description here                                  */
25569 
25570     struct {
25571       __IOM uint32_t BF10       : 2;            /*!< [1..0] HS receiver bias current tuning. 2'b00 represents the
25572                                                      minimum bias current 2'b11 represents the maximum bias
25573                                                      current                                                                   */
25574       __IOM uint32_t BF22       : 1;            /*!< [2..2] Clk60m, clk12m and clk48m enable. 1'b0:disables the clocks
25575                                                      1'b1:enables the clocks                                                   */
25576       __IOM uint32_t BF73       : 5;            /*!< [7..3] This bitfield is reserved.                                         */
25577             uint32_t            : 24;
25578     } REG18_b;
25579   } ;
25580 
25581   union {
25582     __IOM uint32_t REG1C;                       /*!< (@ 0x0000001C) Register description here                                  */
25583 
25584     struct {
25585       __IOM uint32_t BF00       : 1;            /*!< [0..0] Set IO high-Z state. Active high                                   */
25586       __IOM uint32_t BF11       : 1;            /*!< [1..1] Tx power down in suspend state. Active low.                        */
25587       __IOM uint32_t BF22       : 1;            /*!< [2..2] PLL enable bypass from suspend module. 1'b1: bypass enable
25588                                                      1'b0:bypass disable                                                       */
25589       __IOM uint32_t BF33       : 1;            /*!< [3..3] PLL enable value from suspend module. 1'b1:pll enable              */
25590       __IOM uint32_t BF44       : 1;            /*!< [4..4] 480M clock out enable. 1'b0:pll disable 1'b1: 480M clock
25591                                                      out enable 1'b0: 480M clock out disable                                   */
25592       __IOM uint32_t BF55       : 1;            /*!< [5..5] BG power down control bit, active high 1: power down
25593                                                      band-gap 0: normal operation mode                                         */
25594       __IOM uint32_t BF66       : 1;            /*!< [6..6] This bitfield is reserved.                                         */
25595       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
25596             uint32_t            : 24;
25597     } REG1C_b;
25598   } ;
25599 
25600   union {
25601     __IOM uint32_t REG20;                       /*!< (@ 0x00000020) Register description here                                  */
25602 
25603     struct {
25604       __IOM uint32_t BF20       : 3;            /*!< [2..0] Rx enable delay select. 3'b000: 4 clocks (480Mhz clock)
25605                                                      3'b001: 5 clocks 3'b010: 6 clocks 3'b011: 7 clocks 3'b100:
25606                                                      8 clocks 3'b101: 9 clocks 3'b110: 10 clocks 3'b111: 12
25607                                                      clocks                                                                    */
25608       __IOM uint32_t BF33       : 1;            /*!< [3..3] This bitfield is reserved.                                         */
25609       __IOM uint32_t BF54       : 2;            /*!< [5..4] Analog observation port select. for detailed information,
25610                                                      please refer to section 10.3 , Table 30 : Debug and OBS
25611                                                      port                                                                      */
25612       __IOM uint32_t BF76       : 2;            /*!< [7..6] This bitfield is reserved.                                         */
25613             uint32_t            : 24;
25614     } REG20_b;
25615   } ;
25616 
25617   union {
25618     __IOM uint32_t REG24;                       /*!< (@ 0x00000024) Register description here                                  */
25619 
25620     struct {
25621       __IOM uint32_t BF00       : 1;            /*!< [0..0] it0                                                                */
25622       __IOM uint32_t BF71       : 7;            /*!< [7..1] This bitfield is reserved.                                         */
25623             uint32_t            : 24;
25624     } REG24_b;
25625   } ;
25626 
25627   union {
25628     __IOM uint32_t REG28;                       /*!< (@ 0x00000028) Register description here                                  */
25629 
25630     struct {
25631       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25632             uint32_t            : 24;
25633     } REG28_b;
25634   } ;
25635 
25636   union {
25637     __IOM uint32_t REG2C;                       /*!< (@ 0x0000002C) Register description here                                  */
25638 
25639     struct {
25640       __IOM uint32_t BF00       : 1;            /*!< [0..0] All port z bypass value. 1'b1: bypass enable 1'b0:bypass
25641                                                      disable                                                                   */
25642       __IOM uint32_t BF11       : 1;            /*!< [1..1] This bitfield is reserved.                                         */
25643       __IOM uint32_t BF22       : 1;            /*!< [2..2] HS keep alive enable. 1'b1: HS keep alive enable 1'b0:
25644                                                      HS keep alive disable                                                     */
25645       __IOM uint32_t BF33       : 1;            /*!< [3..3] This bitfield is reserved.                                         */
25646       __IOM uint32_t BF44       : 1;            /*!< [4..4] This bitfield is reserved.                                         */
25647       __IOM uint32_t BF75       : 3;            /*!< [7..5] This bitfield is reserved.                                         */
25648             uint32_t            : 24;
25649     } REG2C_b;
25650   } ;
25651 
25652   union {
25653     __IOM uint32_t REG30;                       /*!< (@ 0x00000030) Register description here                                  */
25654 
25655     struct {
25656       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25657             uint32_t            : 24;
25658     } REG30_b;
25659   } ;
25660 
25661   union {
25662     __IOM uint32_t REG34;                       /*!< (@ 0x00000034) Register description here                                  */
25663 
25664     struct {
25665       __IOM uint32_t BF70       : 8;            /*!< [7..0] BF70 field description needed.                                     */
25666             uint32_t            : 24;
25667     } REG34_b;
25668   } ;
25669 
25670   union {
25671     __IOM uint32_t REG38;                       /*!< (@ 0x00000038) Register description here                                  */
25672 
25673     struct {
25674       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25675             uint32_t            : 24;
25676     } REG38_b;
25677   } ;
25678 
25679   union {
25680     __IOM uint32_t REG3C;                       /*!< (@ 0x0000003C) Register description here                                  */
25681 
25682     struct {
25683       __IOM uint32_t BF10       : 2;            /*!< [1..0] BF10 field description needed.                                     */
25684       __IOM uint32_t BF42       : 3;            /*!< [4..2] This bitfield is reserved.                                         */
25685       __IOM uint32_t BF75       : 3;            /*!< [7..5] Host disconnect filter select. 3'b100:6 clocks(480M clock)
25686                                                      3'b101:8 clocks 3'b111:disconnect disable Other: invalid                  */
25687             uint32_t            : 24;
25688     } REG3C_b;
25689   } ;
25690 
25691   union {
25692     __IOM uint32_t REG40;                       /*!< (@ 0x00000040) Register description here                                  */
25693 
25694     struct {
25695       __IOM uint32_t BF60       : 7;            /*!< [6..0] This bitfield is reserved.                                         */
25696       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
25697             uint32_t            : 24;
25698     } REG40_b;
25699   } ;
25700 
25701   union {
25702     __IOM uint32_t REG44;                       /*!< (@ 0x00000044) Register description here                                  */
25703 
25704     struct {
25705       __IOM uint32_t BF00       : 1;            /*!< [0..0] 1: DP/DM will be sampled in HS Tx or Rx state 0: DP/DM
25706                                                      will be sampled only in Hs Rx state                                       */
25707       __IOM uint32_t BF11       : 1;            /*!< [1..1] Disconnect squelch and comparator calibration bypass,
25708                                                      active high                                                               */
25709       __IOM uint32_t BF42       : 3;            /*!< [4..2] This bitfield is reserved.                                         */
25710       __IOM uint32_t BF65       : 2;            /*!< [6..5] This bitfield is reserved.                                         */
25711       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
25712             uint32_t            : 24;
25713     } REG44_b;
25714   } ;
25715 
25716   union {
25717     __IOM uint32_t REG48;                       /*!< (@ 0x00000048) Register description here                                  */
25718 
25719     struct {
25720       __IOM uint32_t BF00       : 1;            /*!< [0..0] Enable TX shutdown, active LOW. This bit is only used
25721                                                      for debug purpose , nothing to do with the normal operation
25722                                                      and signal quality, keeping the default value is strongly
25723                                                      recommended.                                                              */
25724       __IOM uint32_t BF71       : 7;            /*!< [7..1] This bitfield is reserved.                                         */
25725             uint32_t            : 24;
25726     } REG48_b;
25727   } ;
25728 
25729   union {
25730     __IOM uint32_t REG4C;                       /*!< (@ 0x0000004C) Register description here                                  */
25731 
25732     struct {
25733       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25734             uint32_t            : 24;
25735     } REG4C_b;
25736   } ;
25737 
25738   union {
25739     __IOM uint32_t REG50;                       /*!< (@ 0x00000050) Register description here                                  */
25740 
25741     struct {
25742       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25743             uint32_t            : 24;
25744     } REG50_b;
25745   } ;
25746 
25747   union {
25748     __IOM uint32_t REG54;                       /*!< (@ 0x00000054) Register description here                                  */
25749 
25750     struct {
25751       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25752             uint32_t            : 24;
25753     } REG54_b;
25754   } ;
25755 
25756   union {
25757     __IOM uint32_t REG58;                       /*!< (@ 0x00000058) Register description here                                  */
25758 
25759     struct {
25760       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25761             uint32_t            : 24;
25762     } REG58_b;
25763   } ;
25764 
25765   union {
25766     __IOM uint32_t REG5C;                       /*!< (@ 0x0000005C) Register description here                                  */
25767 
25768     struct {
25769       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25770             uint32_t            : 24;
25771     } REG5C_b;
25772   } ;
25773 
25774   union {
25775     __IOM uint32_t REG60;                       /*!< (@ 0x00000060) Register description here                                  */
25776 
25777     struct {
25778       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25779             uint32_t            : 24;
25780     } REG60_b;
25781   } ;
25782 
25783   union {
25784     __IOM uint32_t REG64;                       /*!< (@ 0x00000064) Register description here                                  */
25785 
25786     struct {
25787       __IOM uint32_t BF00       : 1;            /*!< [0..0] This bitfield is reserved.                                         */
25788             uint32_t            : 31;
25789     } REG64_b;
25790   } ;
25791 
25792   union {
25793     __IOM uint32_t REG68;                       /*!< (@ 0x00000068) Register description here                                  */
25794 
25795     struct {
25796       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25797             uint32_t            : 24;
25798     } REG68_b;
25799   } ;
25800 
25801   union {
25802     __IOM uint32_t REG6C;                       /*!< (@ 0x0000006C) Register description here                                  */
25803 
25804     struct {
25805       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25806             uint32_t            : 24;
25807     } REG6C_b;
25808   } ;
25809 
25810   union {
25811     __IOM uint32_t REG70;                       /*!< (@ 0x00000070) Register description here                                  */
25812 
25813     struct {
25814       __IOM uint32_t BF70       : 8;            /*!< [7..0] BF70 field description needed.                                     */
25815             uint32_t            : 24;
25816     } REG70_b;
25817   } ;
25818 
25819   union {
25820     __IOM uint32_t REG74;                       /*!< (@ 0x00000074) Register description here                                  */
25821 
25822     struct {
25823       __IOM uint32_t BF00       : 1;            /*!< [0..0] Disconnect detection block input res load sel. 1'b0:
25824                                                      disconnect detection block input res load bypass 1'b1:
25825                                                      disconnect detection block input res load enable                          */
25826       __IOM uint32_t BF31       : 3;            /*!< [3..1] HS driver slew rate tuning 001:SR is weakest 111:SR is
25827                                                      strongest.000 is forbidden.                                               */
25828       __IOM uint32_t BF74       : 4;            /*!< [7..4] This bitfield is reserved.                                         */
25829             uint32_t            : 24;
25830     } REG74_b;
25831   } ;
25832 
25833   union {
25834     __IOM uint32_t REG78;                       /*!< (@ 0x00000078) Register description here                                  */
25835 
25836     struct {
25837       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25838             uint32_t            : 24;
25839     } REG78_b;
25840   } ;
25841 
25842   union {
25843     __IOM uint32_t REG7C;                       /*!< (@ 0x0000007C) Register description here                                  */
25844 
25845     struct {
25846       __IOM uint32_t BF40       : 5;            /*!< [4..0] This bitfield is reserved.                                         */
25847       __IOM uint32_t BF55       : 1;            /*!< [5..5] No leakage current on DP/DM pin when VCCA3P3 power down,
25848                                                      active low. Keeping the default value was greatly appreciated             */
25849       __IOM uint32_t BF66       : 1;            /*!< [6..6] Hs chirp mode amplitude increasing register, active high.          */
25850       __IOM uint32_t BF77       : 1;            /*!< [7..7] Clk60m source clock select. 1'b1: free clock 60M 1'b0:
25851                                                      utmi_clk                                                                  */
25852             uint32_t            : 24;
25853     } REG7C_b;
25854   } ;
25855 
25856   union {
25857     __IOM uint32_t REG80;                       /*!< (@ 0x00000080) Register description here                                  */
25858 
25859     struct {
25860       __IOM uint32_t BF00       : 1;            /*!< [0..0] Digital clock enable bypass 1'b1: digital clock bypass
25861                                                      enable 1'b0: digital clock bypass disable                                 */
25862       __IOM uint32_t BF11       : 1;            /*!< [1..1] Digital clock enable bypass value 1'b1: digital clock
25863                                                      enable 1'b0: digital clock disable                                        */
25864       __IOM uint32_t BF22       : 1;            /*!< [2..2] utmi clock always on 1'b1: utmi clock always on 1'b0:
25865                                                      utmi clock relative to suspendm                                           */
25866       __IOM uint32_t BF73       : 5;            /*!< [7..3] This bitfield is reserved.                                         */
25867             uint32_t            : 24;
25868     } REG80_b;
25869   } ;
25870 
25871   union {
25872     __IOM uint32_t REG84;                       /*!< (@ 0x00000084) Register description here                                  */
25873 
25874     struct {
25875       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
25876             uint32_t            : 24;
25877     } REG84_b;
25878   } ;
25879 } USBPHY_Type;                                  /*!< Size = 136 (0x88)                                                         */
25880 
25881 
25882 
25883 /* =========================================================================================================================== */
25884 /* ================                                            USB                                            ================ */
25885 /* =========================================================================================================================== */
25886 
25887 
25888 /**
25889   * @brief USB device register descriptions. (USB)
25890   */
25891 
25892 typedef struct {                                /*!< (@ 0x400B0000) USB Structure                                              */
25893 
25894   union {
25895     __IOM uint32_t CFG0;                        /*!< (@ 0x00000000) Function address, power management, interrupt
25896                                                                     status register for EP0 and IN Endpoints
25897                                                                     1 to 5                                                     */
25898 
25899     struct {
25900       __IOM uint32_t FuncAddr   : 7;            /*!< [6..0] The function address. This field should be written with
25901                                                      the address value contained in the SET_ADDRESS standard
25902                                                      device request, when it is received on Endpoint 0. The
25903                                                      new address will not take effect immediately as the host
25904                                                      will still be using the old address for the Status stage
25905                                                      of the device request. The USB Controller will continue
25906                                                      to use the old address for decoding packets until the device
25907                                                      request has completed. The status of the device request
25908                                                      can be determined by reading the Update bit. When a new
25909                                                      a                                                                         */
25910       __IOM uint32_t Update     : 1;            /*!< [7..7] Function Address Update. Set when FuncAddr is written.
25911                                                      Cleared when the new address takes effect (at the end of
25912                                                      the current transfer).                                                    */
25913       __IOM uint32_t Enabl      : 1;            /*!< [8..8] Set by the CPU to enable the SUSPENDM signal. The Enabl
25914                                                      bit is set to enable the SUSPENDM signal to put the UTM
25915                                                      (and any other hardware which uses the SUSPENDM signal)
25916                                                      into Suspend mode. If this bit is not set, Suspend mode
25917                                                      will be detected as normal but the SUSPENDM signal will
25918                                                      remain high so that the UTM does not go into its low-power
25919                                                      mode.                                                                     */
25920       __IOM uint32_t Suspen     : 1;            /*!< [9..9] Suspend Status. This read-only bit is set when Suspend
25921                                                      mode is entered. It is cleared when the CPU reads the interrupt
25922                                                      register, or sets the Resume bit of this register. The
25923                                                      Suspen bit is set by the USB Controller when Suspend mode
25924                                                      is entered. It will be cleared when the CFG2_Suspend field
25925                                                      is read (as a result of receiving a Suspend interrupt).
25926                                                      It will also be cleared if Suspend mode is left by setting
25927                                                      the Resume bit to initiate a remote wake-up.                              */
25928       __IOM uint32_t Resume     : 1;            /*!< [10..10] Resume. Set should clear this bit after 10 ms (a maximum
25929                                                      of 15 ms) to end Resume signaling. The Resume bit is used
25930                                                      to force the USB Controller to generate Resume signaling
25931                                                      on the USB to perform remote wake-up from Suspend mode.
25932                                                      Once set high, it should be left high for approximately
25933                                                      10 ms (at least 1 ms and no more than 15 ms), then cleared.               */
25934       __IOM uint32_t Reset      : 1;            /*!< [11..11] Reset Status. Cleared when either HS negotiation has
25935                                                      completed successfully or after 2.1 ms of reset signaling
25936                                                      if HS negotiation fails. The Reset bit can be used to determine
25937                                                      when reset signaling is present on the USB. Set when Reset
25938                                                      signaling is detected and remains high until the bus reverts
25939                                                      to an idle state.                                                         */
25940       __IOM uint32_t HSMode     : 1;            /*!< [12..12] This read-only bit is set when the USB Controller has
25941                                                      successfully negotiated for High-speed mode. The HSMode
25942                                                      bit can be used to determine whether the USB Controller
25943                                                      is in High-speed mode or Full-speed mode. It will go high
25944                                                      when the function has successfully negotiated for high-speed
25945                                                      operation during a USB reset.                                             */
25946       __IOM uint32_t HSEnab     : 1;            /*!< [13..13] High-speed Enable. When set by the CPU, the USB Controller
25947                                                      will negotiate for high-speed mode when the device is reset
25948                                                      by the hub. If not set, the device will only operate in
25949                                                      Full-speed mode. The HSEnab bit can be used to disable
25950                                                      high-speed operation. Normally the USB Controller will
25951                                                      automatically negotiate for high speed operation, when
25952                                                      it is reset, by sending a 'chirp' to the hub. However if
25953                                                      this bit is cleared then the USB Controller will not send
25954                                                      any 'chirps' to the hub so the function will remain in
25955                                                      F                                                                         */
25956       __IOM uint32_t AMSPECIFIC : 1;            /*!< [14..14] Software-enabled Connection (SoftConn). When set to
25957                                                      1, the PHY is placed in its normal mode and the D+/D- lines
25958                                                      of the USB bus are enabled. When bit is cleared, the PHY
25959                                                      is put into non-driving mode and D+ and D- are tri-stated.                */
25960       __IOM uint32_t ISOUpdate  : 1;            /*!< [15..15] Isochronous Transfer Update. When set by the CPU, the
25961                                                      USB Controller will wait for an SOF token from the time
25962                                                      InPktRdy is set before sending the packet. If an IN token
25963                                                      is received before an SOF token, then a zero length data
25964                                                      packet will be sent. Note: This bit only affects endpoints
25965                                                      performing Isochronous transfers. The ISOUpdate bit affects
25966                                                      all IN Isochronous endpoints in the USB Controller. It
25967                                                      is normally used as a method of ensuring 'clean' start-up
25968                                                      of an IN Isochronous pipe.                                                */
25969       __IOM uint32_t EP0InIntStat : 1;          /*!< [16..16] IN Endpoint 0 interrupt status. All interrupts are
25970                                                      cleared when the register is read.                                        */
25971       __IOM uint32_t EP1InIntStat : 1;          /*!< [17..17] IN Endpoint 1 interrupt status. All interrupts are
25972                                                      cleared when the register is read.                                        */
25973       __IOM uint32_t EP2InIntStat : 1;          /*!< [18..18] IN Endpoint 2 interrupt status. All interrupts are
25974                                                      cleared when the register is read.                                        */
25975       __IOM uint32_t EP3InIntStat : 1;          /*!< [19..19] IN Endpoint 3 interrupt status. All interrupts are
25976                                                      cleared when the register is read.                                        */
25977       __IOM uint32_t EP4InIntStat : 1;          /*!< [20..20] IN Endpoint 4 interrupt status. All interrupts are
25978                                                      cleared when the register is read.                                        */
25979       __IOM uint32_t EP5InIntStat : 1;          /*!< [21..21] IN Endpoint 5 interrupt status. All interrupts are
25980                                                      cleared when the register is read.                                        */
25981             uint32_t            : 10;
25982     } CFG0_b;
25983   } ;
25984 
25985   union {
25986     __IOM uint32_t CFG1;                        /*!< (@ 0x00000004) Indicates which of the IN Endpoint 1 - 5 interrupts
25987                                                                     and the single Endpoint 0 interrupt are
25988                                                                     currently active. Also indicates which of
25989                                                                     the interrupts for OUT Endpoint 1 - 5 are
25990                                                                     currently active. All active interrupts
25991                                                                     are cleared when this register is read.                    */
25992 
25993     struct {
25994       __IOM uint32_t EP0OutIntStat : 1;         /*!< [0..0] OUT Endpoint 0 interrupt status. All interrupts are cleared
25995                                                      when the register is read.                                                */
25996       __IOM uint32_t EP1OutIntStat : 1;         /*!< [1..1] OUT Endpoint 1 interrupt status. All interrupts are cleared
25997                                                      when the register is read.                                                */
25998       __IOM uint32_t EP2OutIntStat : 1;         /*!< [2..2] OUT Endpoint 2 interrupt status. All interrupts are cleared
25999                                                      when the register is read.                                                */
26000       __IOM uint32_t EP3OutIntStat : 1;         /*!< [3..3] OUT Endpoint 3 interrupt status. All interrupts are cleared
26001                                                      when the register is read.                                                */
26002       __IOM uint32_t EP4OutIntStat : 1;         /*!< [4..4] OUT Endpoint 4 interrupt status. All interrupts are cleared
26003                                                      when the register is read.                                                */
26004       __IOM uint32_t EP5OutIntStat : 1;         /*!< [5..5] OUT Endpoint 5 interrupt status. All interrupts are cleared
26005                                                      when the register is read.                                                */
26006             uint32_t            : 10;
26007       __IOM uint32_t EP0InIntEn : 1;            /*!< [16..16] IN Endpoint 0 Interrupt Enable                                   */
26008       __IOM uint32_t EP1InIntEn : 1;            /*!< [17..17] IN Endpoint 1 Interrupt Enable                                   */
26009       __IOM uint32_t EP2InIntEn : 1;            /*!< [18..18] IN Endpoint 2 Interrupt Enable                                   */
26010       __IOM uint32_t EP3InIntEn : 1;            /*!< [19..19] IN Endpoint 3 Interrupt Enable                                   */
26011       __IOM uint32_t EP4InIntEn : 1;            /*!< [20..20] IN Endpoint 4 Interrupt Enable                                   */
26012       __IOM uint32_t EP5InIntEn : 1;            /*!< [21..21] IN Endpoint 5 Interrupt Enable                                   */
26013             uint32_t            : 10;
26014     } CFG1_b;
26015   } ;
26016 
26017   union {
26018     __IOM uint32_t CFG2;                        /*!< (@ 0x00000008) Provides interrupt enable and (currently active)
26019                                                                     status bits for each of the state interrupts,
26020                                                                     as well as the IN Endpoint and OUT Endpoint
26021                                                                     nterrupts. All active interrupts are cleared
26022                                                                     when this register is read. On reset, all
26023                                                                     IN and OUT Endpoint interrupts, in addition
26024                                                                     to Endpoint 0, are set to 1 while the remaining
26025                                                                     bits are set to 0.                                         */
26026 
26027     struct {
26028       __IOM uint32_t EP0OutIntEn : 1;           /*!< [0..0] Out Endpoint 0 Interrupt Enable.                                   */
26029       __IOM uint32_t EP1OutIntEn : 1;           /*!< [1..1] Out Endpoint 1 Interrupt Enable.                                   */
26030       __IOM uint32_t EP2OutIntEn : 1;           /*!< [2..2] Out Endpoint 2 Interrupt Enable.                                   */
26031       __IOM uint32_t EP3OutIntEn : 1;           /*!< [3..3] Out Endpoint 3 Interrupt Enable.                                   */
26032       __IOM uint32_t EP4OutIntEn : 1;           /*!< [4..4] Out Endpoint 4 Interrupt Enable.                                   */
26033       __IOM uint32_t EP5OutIntEn : 1;           /*!< [5..5] Out Endpoint 5 Interrupt Enable.                                   */
26034             uint32_t            : 10;
26035       __IOM uint32_t Suspend    : 1;            /*!< [16..16] Suspend Interrupt Status. Set when suspend signaling
26036                                                      is detected on the bus.                                                   */
26037       __IOM uint32_t Resume     : 1;            /*!< [17..17] Resume Interrupt Status. Set when resume signaling
26038                                                      is detected on the bus while the USB Controller is in Suspend
26039                                                      mode.                                                                     */
26040       __IOM uint32_t Reset      : 1;            /*!< [18..18] Reset Detect Interrupt Status. Set when reset signaling
26041                                                      is detected on the bus.                                                   */
26042       __IOM uint32_t SOF        : 1;            /*!< [19..19] Start of Frame Interrupt Status. Set at the start of
26043                                                      frame.                                                                    */
26044             uint32_t            : 4;
26045       __IOM uint32_t SuspendE   : 1;            /*!< [24..24] Suspend Interrupt Enable.                                        */
26046       __IOM uint32_t ResumeE    : 1;            /*!< [25..25] Resume Interrupt Enable.                                         */
26047       __IOM uint32_t ResetE     : 1;            /*!< [26..26] Reset Detect Interrupt Enable.                                   */
26048       __IOM uint32_t SOFE       : 1;            /*!< [27..27] Start of Frame interrupt enable.                                 */
26049             uint32_t            : 4;
26050     } CFG2_b;
26051   } ;
26052 
26053   union {
26054     __IOM uint32_t CFG3;                        /*!< (@ 0x0000000C) Provides Test fields to put the USB Controller
26055                                                                     into one of four test modes described in
26056                                                                     the USB 2.0 specification. Only one of the
26057                                                                     Test fields should be set at any time. (Not
26058                                                                     used in normal operation.) Also includes
26059                                                                     an index field that determines which endpoint
26060                                                                     control,status registers are accessed via
26061                                                                     the IDXn register fields, and a Frame field
26062                                                                     that holds the last received frame number.                 */
26063 
26064     struct {
26065       __IOM uint32_t FRMNUM     : 16;           /*!< [15..0] Frame Number. Read-only field containing the last received
26066                                                      frame number in bits 10:0, 15:11 read 0.                                  */
26067       __IOM uint32_t ENDPOINT   : 4;            /*!< [19..16] Index selected endpoint.                                         */
26068             uint32_t            : 4;
26069       __IOM uint32_t TestSE0NAK : 1;            /*!< [24..24] Test_SE0_NAK Test Mode. The CPU sets this bit to enter
26070                                                      the Test_SE0_NAK test mode. In this mode, the USB Controller
26071                                                      remains in high-speed mode and responds to any valid IN
26072                                                      token with a NAK.                                                         */
26073       __IOM uint32_t TestJ      : 1;            /*!< [25..25] Test_J Test Mode. The CPU sets this bit to enter the
26074                                                      Test_J test mode. In this mode, the USB Controller - in
26075                                                      high-speed mode - transmits a continuous J on the bus.                    */
26076       __IOM uint32_t TestK      : 1;            /*!< [26..26] Test_K Test Mode. The CPU sets this bit to enter the
26077                                                      Test_K test mode. In this mode, the USB Controller - in
26078                                                      high-speed mode - transmits a continuous K on the bus.                    */
26079       __IOM uint32_t TestPacket : 1;            /*!< [27..27] Test Packet Test Mode. The CPU sets this bit to enter
26080                                                      the Test_Packet test mode. In this mode, the USB Controller
26081                                                      - in high-speed mode - repetitively transmits on the bus
26082                                                      a 53-byte test packet. Note: The 53-byte test packet must
26083                                                      be loaded into the Endpoint 0 FIFO before the test mode
26084                                                      is entered.                                                               */
26085       __IOM uint32_t ForceHS    : 1;            /*!< [28..28] Force High-speed Mode. The CPU sets this bit to force
26086                                                      the USB Controller into High-speed mode when it receives
26087                                                      a USB reset.                                                              */
26088       __IOM uint32_t ForceFS    : 1;            /*!< [29..29] Force Full-speed Mode. The CPU sets this bit to force
26089                                                      the USB Controller into Full-speed mode when it receives
26090                                                      a USB reset.                                                              */
26091             uint32_t            : 2;
26092     } CFG3_b;
26093   } ;
26094 
26095   union {
26096     __IOM uint32_t IDX0;                        /*!< (@ 0x00000010) Provides additional control and status for IN
26097                                                                     transactions through the currently-selected
26098                                                                     endpoint. (To avoid CMSIS conflicts, the
26099                                                                     address here includes an additional offset
26100                                                                     of 0x1000. Access to this register must
26101                                                                     take this into account.) The value returned
26102                                                                     when this register is read reflects the
26103                                                                     status of an endpoint specified by setting
26104                                                                     the endpoint index in the CFG3_ENDPOINT
26105                                                                     field. When the endpoint index (CFG3_ENDPOINT)
26106                                                                     = 0, this field provides status and control
26107                                                                     of Endpoint 0. Also, the                                   */
26108 
26109     struct {
26110       __IOM uint32_t MAXPAYLOAD : 11;           /*!< [10..0] Maximum Payload transmitted in a single transaction.
26111                                                      The total amount of data represented by MAXPAYLOAD x (PKTSPLITOPTION
26112                                                      + 1) must not exceed the FIFO size for the IN endpoint,
26113                                                      and should not exceed half the FIFO size if double-buffering
26114                                                      is required. Note: The value written here (multiplied by
26115                                                      PKTSPLITOPTION + 1 in the case of high-bandwidth Isochronous
26116                                                      transfers) must match the value given in the wMaxPacketSize
26117                                                      field of the Standard Endpoint Descriptor for the associated
26118                                                      endpoint (see USB Specification R                                         */
26119       __IOM uint32_t PKTSPLITOPTION : 5;        /*!< [15..11] Packet Split Option. When IDX0_ISO = 1, this bit serves
26120                                                      as the MAXPAYLOAD multiplier for Isochronous IN transfers.
26121                                                      When IDX0_ISO = 0, this bit serves as the MAXPAYLOAD multiplier
26122                                                      for Bulk IN transfers.If IDX0_ISO = 0x1, this field sets
26123                                                      the multiplier for Isochronous transfers. For Isochronous
26124                                                      endpoints operating in High-Speed mode and with the High-bandwidth
26125                                                      option enabled, PKTSPLITOPTION may be either 2 or 3 (corresponding
26126                                                      to this field's bit 0 set or bit 1 set, respectively, and
26127                                                      bits[4:2] are ignored) an                                                 */
26128       __IOM uint32_t InPktRdyOutPktRdy : 1;     /*!< [16..16] IN Packet Ready / OUT Packet Ready. When CFG3_ENDPOINT
26129                                                      > 0, this bit serves as the InPktRdy field. When CFG3_ENDPOINT
26130                                                      = 0, this bit serves as the OutPkyRdy bit.If CFG3_ENDPOINT
26131                                                      = 0x1-0x5, this bit serves as the InPktRdy field. Set this
26132                                                      bit after loading a data packet into the FIFO. It is cleared
26133                                                      automatically when a data packet has been transmitted.
26134                                                      If the FIFO is double-buffered, it is also automatically
26135                                                      cleared when there is space for a second packet in the
26136                                                      FIFO. An interrupt is generate (if enabled) whe                           */
26137       __IOM uint32_t FIFONotEmptyInPktRdy : 1;  /*!< [17..17] FIFO Not Empty / IN Packet Ready. When CFG3_ENDPOINT
26138                                                      = 1 to 5, this bit serves as the FIFONotEmpty field. When
26139                                                      CFG3_ENDPOINT = 0, this bit serves as the InPktRdy bit.If
26140                                                      CFG3_ENDPOINT = 0x1-0x5, this bit serves as the FIFONotEmpty
26141                                                      field. It is set when there is at least 1 packet in the
26142                                                      IN FIFO.If CFG3_ENDPOINT = 0x0, this bit serves as the
26143                                                      InPktRdy bit. Set this bit after loading a data packet
26144                                                      into the FIFO. It is cleared automatically when the data
26145                                                      packet has been transmitted. An interrupt is generated
26146                                                      whe                                                                       */
26147       __IOM uint32_t UnderRunSentStall : 1;     /*!< [18..18] Under Run / Sent Stall. When CFG3_ENDPOINT = 1 to 5,
26148                                                      this bit serves as the UnderRun field. When CFG3_ENDPOINT
26149                                                      = 0, this bit serves as the SentStall field.If CFG3_ENDPOINT
26150                                                      = 0x1-0x5, this bit serves as the UnderRun field. In ISO
26151                                                      mode this bit is set when a zero length data packet is
26152                                                      sent after receiving an IN token with the InPktRdy bit
26153                                                      not set. In Bulk/Interrupt mode, this bit is set when a
26154                                                      NAK is returned in response to an IN token. The CPU should
26155                                                      clear this bit.If CFG3_ENDPOINT = 0x0, this bit serves
26156                                                      as                                                                        */
26157       __IOM uint32_t FlushFIFODataEnd : 1;      /*!< [19..19] When CFG3_ENDPOINT = 1 to 5, this bit serves as the
26158                                                      FlushFIFO field. When CFG3_ENDPOINT = 0, this bit serves
26159                                                      as the DataEnd bit.If CFG3_ENDPOINT = 0x1-0x5, this bit
26160                                                      serves as the FlushFIFO field. Setting this bit flushes
26161                                                      the next packet to be transmitted from the endpoint IN
26162                                                      FIFO. The FIFO pointer is reset and the InPktRdy bit is
26163                                                      cleared. May be set simultaneously with InPktRdy to abort
26164                                                      the packet that has just been loaded into the FIFO.Note
26165                                                      1: FlushFIFO should only be set when InPktRdy is set (at
26166                                                      other ti                                                                  */
26167       __IOM uint32_t SendStallSetupEnd : 1;     /*!< [20..20] When CFG3_ENDPOINT = 1 to 5, this bit serves as the
26168                                                      SendStall field. When CFG3_ENDPOINT = 0, this bit serves
26169                                                      as the SetupEnd field.If CFG3_ENDPOINT = 0x1-0x5, this
26170                                                      bit serves as the SendStall field. Setting this bit issues
26171                                                      a STALL handshake to an IN token. The CPU clears this bit
26172                                                      to terminate the stall condition.Note: This bit has no
26173                                                      effect when the endpoint is being used for Isochronous
26174                                                      transfers.If CFG3_ENDPOINT = 0x0, this bit serves as the
26175                                                      SetupEnd field. It is set when a control transaction ends
26176                                                      befor                                                                     */
26177       __IOM uint32_t SentStallSendStall : 1;    /*!< [21..21] Sent Stall / Send Stall. When CFG3_ENDPOINT = 1 to
26178                                                      5, this bit serves as the SentStall field. When CFG3_ENDPOINT
26179                                                      = 0, this bit serves as the SendStall function.If CFG3_ENDPOINT
26180                                                      = 0x1-0x5, this bit serves as the SentStall field. It is
26181                                                      set when a STALL handshake is transmitted. The FIFO is
26182                                                      flushed and the InPktRdy bit is cleared. The CPU should
26183                                                      clear this bit.If CFG3_ENDPOINT = 0x0, this bit serves
26184                                                      as the SendStall field. The CPU sets this bit to terminate
26185                                                      the current transaction. The STALL handshake will be                      */
26186       __IOM uint32_t ClrDataTogServicedOutPktRdy : 1;/*!< [22..22] Clear Data Toggle / Serviced OUT Packet Ready. When
26187                                                      CFG3_ENDPOINT = 1 to 5, this bit serves as the ClrDataTog
26188                                                      field. When CFG3_ENDPOINT = 0, this bit serves as the ServicedOutPktReady
26189                                                      field.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the
26190                                                      ClrDataTog field. Setting this bit resets the endpoint
26191                                                      IN data toggle to 0.If CFG3_ENDPOINT = 0x0, this bit serves
26192                                                      as the ServicedOutPktReady field. The CPU writes a 1 to
26193                                                      this bit to clear the OutPktRdy bit. This bit is cleared
26194                                                      automatically.                                                            */
26195       __IOM uint32_t IncompTxServiceSetupEnd : 1;/*!< [23..23] Incomplete Transmission / Service Setup End. When CFG3_ENDPOINT
26196                                                      = 1 to 5, this bit serves as the IncompTx field. When CFG3_ENDPOINT
26197                                                      = 0, this bit serves as the ServiceSetupEnd field.If CFG3_ENDPOINT
26198                                                      = 0x1-0x5, then this bit serves as the IncompTx field.
26199                                                      If the endpoint is being used for high-bandwidth Isochronous
26200                                                      transfers, this bit is set to indicate when a large packet
26201                                                      has been split into 2 or 3 packets for transmission but
26202                                                      insufficient IN tokens have been received to send all the
26203                                                      parts. The remainder of                                                   */
26204       __IOM uint32_t D0         : 1;            /*!< [24..24] Unused, always return 0.                                         */
26205       __IOM uint32_t DPktBufDis : 1;            /*!< [25..25] Double Packet Buffer Disable. This bit is used to control
26206                                                      the use of Double Packet Buffering. It is ignored when
26207                                                      Dynamic FIFO sizing is enabled. Clearing this bit does
26208                                                      NOT necessarily enable Double Packet Buffering but rather
26209                                                      allows Double Packet Buffering to be determined by the
26210                                                      Endpoint's IDX2_INFIFOSZ setting and MAXPAYLOAD size relationship.
26211                                                      Default is enabled.                                                       */
26212             uint32_t            : 1;
26213       __IOM uint32_t FrcDataTog : 1;            /*!< [27..27] Force Data Toggle. The CPU sets this bit to force the
26214                                                      endpoint's IN data toggle to switch after each data packet
26215                                                      is sent regardless of whether an ACK was received. This
26216                                                      can be used by Interrupt IN endpoints that are used to
26217                                                      communicate rate feedback for Isochronous endpoints.                      */
26218             uint32_t            : 1;
26219       __IOM uint32_t Mode       : 1;            /*!< [29..29] OUT/IN Mode. The CPU sets this bit to enable the endpoint
26220                                                      direction as IN or OUT. Note: Only valid where the endpoint
26221                                                      FIFO is used for both IN and OUT transactions, otherwise
26222                                                      ignored.                                                                  */
26223       __IOM uint32_t ISO        : 1;            /*!< [30..30] Isochronous Transfers. The CPU sets this bit to enable
26224                                                      the IN endpoint for Isochronous transfers (ISO mode) or
26225                                                      for Bulk/Interrupt transfers.                                             */
26226       __IOM uint32_t AutoSet    : 1;            /*!< [31..31] Automatically Set InPktRdy. When set, the FIFONotEmptyInPktRdy
26227                                                      field (for IN Endpoint 0) or InPktRdyOutPktRdy field (for
26228                                                      IN Endpoint 1-5) in this register will be automatically
26229                                                      set when data of the maximum packet size (set in MAXPAYLOAD
26230                                                      field) is loaded into the IN FIFO.                                        */
26231     } IDX0_b;
26232   } ;
26233 
26234   union {
26235     __IOM uint32_t IDX1;                        /*!< (@ 0x00000014) Provides control and status bits for OUT transactions
26236                                                                     through the currently-selected endpoint.
26237                                                                     It is reset to 0. The value returned when
26238                                                                     this register is read reflects the status
26239                                                                     of an endpoint specified by setting the
26240                                                                     endpoint index in the CFG3_ENDPOINT field.
26241                                                                     Also, the MAXPAYLOAD field defines the maximum
26242                                                                     amount of data that can be transferred through
26243                                                                     the selected OUT endpoint in a single operation.
26244                                                                     There is a MAXPAYLOAD for each OUT endpoint
26245                                                                     (except Endpoint 0). Note that the action
26246                                                                     initi                                                      */
26247 
26248     struct {
26249       __IOM uint32_t MAXPAYLOAD : 11;           /*!< [10..0] Maximum Payload transmitted in a single transaction.
26250                                                      The value set can be up to 1024 bytes but is subject to
26251                                                      the constraints placed by the USB Specification on packet
26252                                                      sizes for Bulk, Interrupt and Isochronous transfers in
26253                                                      Fullspeed and High-speed operations. The total amount of
26254                                                      data represented by MAXPAYLOAD x (PKTSPLITOPTION + 1) must
26255                                                      not exceed the FIFO size for the OUT endpoint, and should
26256                                                      not exceed half the FIFO size if double-buffering is required.
26257                                                      Note: The value written here (multiplied by m in the                      */
26258       __IOM uint32_t PKTSPLITOPTION : 5;        /*!< [15..11] Packet Split Option. When IDX1_ISO = 1, this bit serves
26259                                                      as the MAXPAYLOAD multiplier for Isochronous OUT transfers.
26260                                                      When IDX1_ISO = 0, this bit serves as the MAXPAYLOAD multiplier
26261                                                      for Bulk IN transfers.If IDX1_ISO = 0x1, this field sets
26262                                                      the multiplier for Isochronous transfers. For Isochronous
26263                                                      endpoints operating in High-Speed mode and with the High-bandwidth
26264                                                      option enabled, PKTSPLITOPTION may be either 2 or 3 (corresponding
26265                                                      to this field's bit 0 set or bit 1 set, respectively, and
26266                                                      bits[4:2] are ignored) a                                                  */
26267       __IOM uint32_t OutPktRdy  : 1;            /*!< [16..16] OUT Packet Ready. This bit is set when a data packet
26268                                                      has been received. Clear this bit when the packet has been
26269                                                      unloaded from the OUT FIFO. An interrupt is generated (if
26270                                                      enabled) when the bit is set.                                             */
26271       __IOM uint32_t FIFOFull   : 1;            /*!< [17..17] FIFO Full. When set, this bit indicates that no more
26272                                                      packets can be loaded into the OUT FIFO.                                  */
26273       __IOM uint32_t OverRun    : 1;            /*!< [18..18] Overrun Condition. Indicates an overrun.If IDX1_ISO
26274                                                      = 0x1 (ISO mode), this bit is set if an OUT packet arrives
26275                                                      while FIFOFull is set, i.e., the OUT packet cannot be loaded
26276                                                      into the OUT FIFO. The CPU should clear this bit.If IDX1_ISO
26277                                                      = 0x0 (Bulk mode), this field always returns zero. This
26278                                                      field is only valid when the endpoint is operating in ISO
26279                                                      mode.                                                                     */
26280       __IOM uint32_t DataError  : 1;            /*!< [19..19] Data Error. Indicates a CRC error.If IDX1_ISO = 0x1
26281                                                      (ISO mode), this bit is set at the same time that OutPktRdy
26282                                                      is set if the data packet has a CRC error. It is cleared
26283                                                      when OutPktRdy is cleared.If IDX1_ISO = 0x0 (Bulk mode),
26284                                                      this field always returns zero. This field is only valid
26285                                                      when the endpoint is operating in ISO mode.                               */
26286       __IOM uint32_t FlushFIFO  : 1;            /*!< [20..20] Flush FIFO. Set this bit to flush the next packet to
26287                                                      be read from the endpoint OUT FIFO. The FIFO pointer is
26288                                                      reset and the OutPktRdy bit is cleared. FlushFIFO should
26289                                                      only be used when OutPktRdy is set. At other times, it
26290                                                      may cause data to be corrupted. If the FIFO is double-buffered,
26291                                                      FlushFIFO may need to be set twice to completely clear
26292                                                      the FIFO.                                                                 */
26293       __IOM uint32_t SendStall  : 1;            /*!< [21..21] Send Stall. Issues a STALL handshake to a DATA packet.If
26294                                                      IDX1_ISO = 0x1, this bit has no effect when the endpoint
26295                                                      is being used for Isochronous transfers.If IDX1_ISO = 0x0,
26296                                                      this field enables Stall Handshakes for Bulk/Interrupt
26297                                                      transactions. Set this bit to issue a STALL handshake to
26298                                                      a DATA packet. Clear this bit to terminate the stall condition.           */
26299       __IOM uint32_t SentStall  : 1;            /*!< [22..22] Sent Stall. This bit is set when a STALL handshake
26300                                                      is transmitted. The CPU should clear this bit.                            */
26301       __IOM uint32_t ClrDataTog : 1;            /*!< [23..23] Clear Data Toggle. Set this bit to reset the endpoint
26302                                                      data toggle to 0.                                                         */
26303       __IOM uint32_t IncompRx   : 1;            /*!< [24..24] Incomplete Receive. This bit is set in a high-bandwidth
26304                                                      Isochronous transfer if the packet in the OUT FIFO is incomplete
26305                                                      because parts of the data were not received. It is cleared
26306                                                      when OutPktRdy is cleared. Note: In anything other than
26307                                                      a high-bandwidth Isochronous transfer, this bit will always
26308                                                      return 0.                                                                 */
26309       __IOM uint32_t DPktBufDis : 1;            /*!< [25..25] Double Packet Buffer Disable. This bit is used to control
26310                                                      the use of Double Packet Buffering. It is ignored when
26311                                                      Dynamic FIFO sizing is enabled. Clearing this bit does
26312                                                      NOT necessarily enable Double Packet Buffering but rather
26313                                                      allows Double Packet Buffering to be determined by the
26314                                                      Endpoint's IDX2_OUTFIFOSZ setting and MAXPAYLOAD size relationship.
26315                                                      Default is enabled.                                                       */
26316             uint32_t            : 2;
26317       __IOM uint32_t DisNye     : 1;            /*!< [28..28] Disable NYET Handshakes / PID Error. For Bulk/Interrupt
26318                                                      transactions, this bit disable the sending of NYET handshakes.
26319                                                      For Bulk/Interrupt transactions, indicates PID errors.If
26320                                                      IDX1_ISO = 0x1, this field is read-only and, when set,
26321                                                      indicates a PID error in the received packet for Isochronous
26322                                                      transfers.If IDX1_ISO = 0x0, this field disables NYET Handshakes
26323                                                      for Bulk/Interrupt transactions. Set this bit to disable
26324                                                      the sending of NYET handshakes. When set, all successfully
26325                                                      received OUT packets are ACK'd includi                                    */
26326             uint32_t            : 1;
26327       __IOM uint32_t ISO        : 1;            /*!< [30..30] Isochronous Transfers. The CPU sets this bit to enable
26328                                                      the OUT endpoint for either Isochronous transfers (ISO
26329                                                      mode) or for Bulk/Interrupt transfers.                                    */
26330       __IOM uint32_t AutoClear  : 1;            /*!< [31..31] Automatically Clear OutPktRdy.                                   */
26331     } IDX1_b;
26332   } ;
26333 
26334   union {
26335     __IOM uint32_t IDX2;                        /*!< (@ 0x00000018) Contains the outcount value for number of received
26336                                                                     bytes in the packet in the OUT FIFO, and
26337                                                                     the configurable IN and OUT Endpoint FIFO
26338                                                                     size.                                                      */
26339 
26340     struct {
26341       __IOM uint32_t ENDPTOUTCOUNT : 13;        /*!< [12..0] Endpoint OUT Count. When CFG3_ENDPOINT = 1 to 5, this
26342                                                      read-only field holds the number of received data bytes
26343                                                      in the packet in the Endpoint's OUT FIFO. When CFG3_ENDPOINT
26344                                                      = 0, this read-only field holds 7-bit data for number of
26345                                                      received data bytes in Endpoint 0 FIFO (OUT count). In
26346                                                      either case, the value returned changes as the contents
26347                                                      of the FIFO change and is only valid while OutPktRdy is
26348                                                      set. (IMPORTANT: The address for the OUTCOUNT register
26349                                                      is actually the same as COUNT0. However to avoid CMSIS
26350                                                      confli                                                                    */
26351             uint32_t            : 3;
26352       __IOM uint32_t INFIFOSZ   : 5;            /*!< [20..16] IN FIFO Size. Sets the size of the selected IN endpoint
26353                                                      FIFO. Bit 4 of this field defines whether double-packet
26354                                                      buffering supported. When set, double-packet buffering
26355                                                      is supported. When cleared, only single-packet buffering
26356                                                      is supported. Bits [3:0] of this field determine maximum
26357                                                      packet size, where 2^^(b3:b0 + 3) is the maximum packet
26358                                                      size to be allowed (before any splitting within the FIFO
26359                                                      of Bulk/High-Bandwidth packets prior to transmission).                    */
26360             uint32_t            : 3;
26361       __IOM uint32_t OUTFIFOSZ  : 5;            /*!< [28..24] OUT FIFO Size. Sets the size of the selected OUT endpoint
26362                                                      FIFO. Bit 4 of this field defines whether double-packet
26363                                                      buffering is supported. When set, double-packet buffering
26364                                                      is supported. When cleared, only single-packet buffering
26365                                                      is supported. Bits [3:0] of this field determine maximum
26366                                                      packet size, where 2^^(b3:b0 + 3) is the maximum packet
26367                                                      size to be allowed (before any splitting within the FIFO
26368                                                      of Bulk/High-Bandwidth packets prior to transmission).                    */
26369             uint32_t            : 3;
26370     } IDX2_b;
26371   } ;
26372 
26373   union {
26374     __IOM uint32_t FIFOADD;                     /*!< (@ 0x0000001C) Sets the start address of the selected IN and
26375                                                                     OUT endpoint FIFOs.                                        */
26376 
26377     struct {
26378       __IOM uint32_t INFIFOADD  : 13;           /*!< [12..0] Sets the start address of the selected IN endpoint FIFO.          */
26379             uint32_t            : 3;
26380       __IOM uint32_t OUTFIFOADD : 13;           /*!< [28..16] Sets the start address of the selected OUT endpoint
26381                                                      FIFO.                                                                     */
26382             uint32_t            : 3;
26383     } FIFOADD_b;
26384   } ;
26385 
26386   union {
26387     __IOM uint32_t FIFO0;                       /*!< (@ 0x00000020) Endpoint 0 FIFO register                                   */
26388 
26389     struct {
26390       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26391                                                      and reading from this register unloads data from the OUT
26392                                                      FIFO for endpoint 0.                                                      */
26393     } FIFO0_b;
26394   } ;
26395 
26396   union {
26397     __IOM uint32_t FIFO1;                       /*!< (@ 0x00000024) Endpoint 1 FIFO register                                   */
26398 
26399     struct {
26400       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26401                                                      and reading from this register unloads data from the OUT
26402                                                      FIFO for endpoint 1.                                                      */
26403     } FIFO1_b;
26404   } ;
26405 
26406   union {
26407     __IOM uint32_t FIFO2;                       /*!< (@ 0x00000028) Endpoint 2 FIFO register                                   */
26408 
26409     struct {
26410       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26411                                                      and reading from this register unloads data from the OUT
26412                                                      FIFO for endpoint 2.                                                      */
26413     } FIFO2_b;
26414   } ;
26415 
26416   union {
26417     __IOM uint32_t FIFO3;                       /*!< (@ 0x0000002C) Endpoint 3 FIFO register                                   */
26418 
26419     struct {
26420       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26421                                                      and reading from this register unloads data from the OUT
26422                                                      FIFO for endpoint 3.                                                      */
26423     } FIFO3_b;
26424   } ;
26425 
26426   union {
26427     __IOM uint32_t FIFO4;                       /*!< (@ 0x00000030) Endpoint 4 FIFO register                                   */
26428 
26429     struct {
26430       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26431                                                      and reading from this register unloads data from the OUT
26432                                                      FIFO for endpoint 4.                                                      */
26433     } FIFO4_b;
26434   } ;
26435 
26436   union {
26437     __IOM uint32_t FIFO5;                       /*!< (@ 0x00000034) Endpoint 5 FIFO register                                   */
26438 
26439     struct {
26440       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26441                                                      and reading from this register unloads data from the OUT
26442                                                      FIFO for endpoint 5.                                                      */
26443     } FIFO5_b;
26444   } ;
26445   __IM  uint32_t  RESERVED[13];
26446 
26447   union {
26448     __IOM uint32_t HWVERS;                      /*!< (@ 0x0000006C) Read-only register that returns version number
26449                                                                     (xx.yyy) of the core hardware.                             */
26450 
26451     struct {
26452       __IOM uint32_t yyy        : 10;           /*!< [9..0] Minor Version Number (Range 0 - 999).                              */
26453       __IOM uint32_t xx         : 5;            /*!< [14..10] Major Version Number (Range 0 - 31).                             */
26454       __IOM uint32_t RC         : 1;            /*!< [15..15] Unused                                                           */
26455             uint32_t            : 16;
26456     } HWVERS_b;
26457   } ;
26458   __IM  uint32_t  RESERVED1[2];
26459 
26460   union {
26461     __IOM uint32_t INFO;                        /*!< (@ 0x00000078) Contains read-only info of the number of IN and
26462                                                                     OUT endpoints included in the design, width
26463                                                                     of the RAM, the ability to reset the USB
26464                                                                     Controller via software, a soft reset bit
26465                                                                     for the CLK clock domain and a soft reset
26466                                                                     bit for the XCLK clock domain.                             */
26467 
26468     struct {
26469       __IOM uint32_t InEndPoints : 4;           /*!< [3..0] Provides the number of implemented IN Endpoints.                   */
26470       __IOM uint32_t OutEndPoints : 4;          /*!< [7..4] Provides the number of implemented OUT Endpoints.                  */
26471       __IOM uint32_t RamBits    : 4;            /*!< [11..8] Provides the width of the RAM address bus.                        */
26472             uint32_t            : 4;
26473       __IOM uint32_t RSTS       : 1;            /*!< [16..16] Soft reset for the CLK domain. cause the output signal
26474                                                      NRSTO to be asserted low. This bit is self-clearing. For
26475                                                      reset to actually occur, the output NRSTO must be connected
26476                                                      to the input NRST.                                                        */
26477       __IOM uint32_t RSTXS      : 1;            /*!< [17..17] Soft reset for the XCLK domain. will cause the output
26478                                                      signal NRSTXO to be asserted low. This bit is self-clearing.
26479                                                      For reset to actually occur, the output NRSTXO must be
26480                                                      connected to the input NRSTX.                                             */
26481             uint32_t            : 14;
26482     } INFO_b;
26483   } ;
26484   __IM  uint32_t  RESERVED2;
26485 
26486   union {
26487     __IOM uint32_t TIMEOUT1;                    /*!< (@ 0x00000080) Holds the configurable chirp timeout value.                */
26488 
26489     struct {
26490       __IOM uint32_t CTUCH      : 16;           /*!< [15..0] Configurable Chirp Timeout timer; default value of 0x4074
26491                                                      corresponds to a delay of 1.1ms (60Mhz clock cycles * 4
26492                                                      * 0x4074).                                                                */
26493             uint32_t            : 16;
26494     } TIMEOUT1_b;
26495   } ;
26496 
26497   union {
26498     __IOM uint32_t TIMEOUT2;                    /*!< (@ 0x00000084) Holds the configurable delay from the end of
26499                                                                     High Speed resume signal to enable UTM normal
26500                                                                     operating mode.                                            */
26501 
26502     struct {
26503       __IOM uint32_t CTHRSTN    : 16;           /*!< [15..0] Configurable delay from the end of High Speed resume
26504                                                      signaling to enabling UTM normal operating mode. Default
26505                                                      value of 0x32 corresponds to a delay of 3us. This programmed
26506                                                      delay is equivalent to the number of 60MHz clock cycles
26507                                                      * 4.                                                                      */
26508             uint32_t            : 16;
26509     } TIMEOUT2_b;
26510   } ;
26511   __IM  uint32_t  RESERVED3[2014];
26512 
26513   union {
26514     __IOM uint32_t CLKCTRL;                     /*!< (@ 0x00002000) Provides optional control for turning off the
26515                                                                     interface clocks to USB Controller and PHY
26516                                                                     as well as the reference clock to the USB
26517                                                                     PHY.                                                       */
26518 
26519     struct {
26520       __IOM uint32_t PHYREFCLKDIS : 1;          /*!< [0..0] Setting this bit turns off the PHY reference clock.                */
26521             uint32_t            : 7;
26522       __IOM uint32_t CTRLAPBCLKDIS : 1;         /*!< [8..8] Setting this bit turns off the Controller logic clock.             */
26523             uint32_t            : 7;
26524       __IOM uint32_t PHYAPBLCLKDIS : 1;         /*!< [16..16] Setting this bit turns off PHY control logic clock.              */
26525             uint32_t            : 7;
26526       __IOM uint32_t PHYREFCLKSEL : 2;          /*!< [25..24] USB PHY reference clock select.For Full_Speed Mode,
26527                                                      set the reference CLKSEL to use HFRC-based clock. For High-Speed
26528                                                      Mode, set the reference CLKSEL to use HFRC2-based clock.
26529                                                      The HFRC2-based clock is higher power, but meets the low-jitter
26530                                                      requirement for High-Speed Mode.                                          */
26531             uint32_t            : 6;
26532     } CLKCTRL_b;
26533   } ;
26534 
26535   union {
26536     __IOM uint32_t SRAMCTRL;                    /*!< (@ 0x00002004) Provides optional SRAM tuning control.                     */
26537 
26538     struct {
26539       __IOM uint32_t RET1N      : 1;            /*!< [0..0] Retention mode 1 enable, active-LOW                                */
26540       __IOM uint32_t EMA        : 3;            /*!< [3..1] Extra margin adjustment                                            */
26541       __IOM uint32_t EMAS       : 1;            /*!< [4..4] Extra margin adjustment sense amplifier pulse                      */
26542       __IOM uint32_t EMAW       : 2;            /*!< [6..5] Extra margin adjustment for write operations                       */
26543       __IOM uint32_t RAWLM      : 2;            /*!< [8..7] SRAM Adjustment for margin for this read assist scheme             */
26544       __IOM uint32_t RAWL       : 1;            /*!< [9..9] SRAM Read assist enable                                            */
26545       __IOM uint32_t WABLM      : 3;            /*!< [12..10] SRAM No margin adjustment                                        */
26546       __IOM uint32_t WABL       : 1;            /*!< [13..13] SRAM write assist enable                                         */
26547       __IOM uint32_t STOV       : 1;            /*!< [14..14] SRAM self-timed override                                         */
26548             uint32_t            : 17;
26549     } SRAMCTRL_b;
26550   } ;
26551   __IM  uint32_t  RESERVED4[3];
26552 
26553   union {
26554     __IOM uint32_t UTMISTICKYSTATUS;            /*!< (@ 0x00002014) This read only register provides the results
26555                                                                     from the PHY OBS port controlled by reg
26556                                                                     0x20[5:4]. IF any bits are set, the bits
26557                                                                     are sticky. Clear this register using the
26558                                                                     OBSCLRSTAT register.                                       */
26559 
26560     struct {
26561       __IOM uint32_t obsportstciky : 2;         /*!< [1..0] These bits are read only status bits from the PHY OBS
26562                                                      port                                                                      */
26563             uint32_t            : 30;
26564     } UTMISTICKYSTATUS_b;
26565   } ;
26566 
26567   union {
26568     __IOM uint32_t OBSCLRSTAT;                  /*!< (@ 0x00002018) Clears all bits in the sticky obs status register.         */
26569 
26570     struct {
26571       __IOM uint32_t CLRSTAT    : 1;            /*!< [0..0] Writing a 1 to this bit clears all bits in the UTMISTICKYSTATUS
26572                                                      register.                                                                 */
26573             uint32_t            : 31;
26574     } OBSCLRSTAT_b;
26575   } ;
26576 
26577   union {
26578     __IOM uint32_t DPDMPULLDOWN;                /*!< (@ 0x0000201C) Enables a pulldown resistor(15K) on D+ or D-               */
26579 
26580     struct {
26581       __IOM uint32_t DMPULLDOWN : 1;            /*!< [0..0] Enables a pulldown resistor(15K) on D-                             */
26582       __IOM uint32_t DPPULLDOWN : 1;            /*!< [1..1] Enables a pulldown resistor(15K) on D+                             */
26583             uint32_t            : 30;
26584     } DPDMPULLDOWN_b;
26585   } ;
26586 
26587   union {
26588     __IOM uint32_t BCDETSTATUS;                 /*!< (@ 0x00002020) USB Battery Charge Detenction Registers                    */
26589 
26590     struct {
26591       __IOM uint32_t DPATTACHED : 1;            /*!< [0..0] Data pin attachment detected                                       */
26592       __IOM uint32_t CPDETECTED : 1;            /*!< [1..1] Charging port detected                                             */
26593       __IOM uint32_t DCPDETECTED : 1;           /*!< [2..2] Dedicated charging port detected                                   */
26594             uint32_t            : 1;
26595       __IOM uint32_t DPCOMPOUT  : 1;            /*!< [4..4] DP comparator output                                               */
26596       __IOM uint32_t DMCOMPOUT  : 1;            /*!< [5..5] DM comparator output                                               */
26597             uint32_t            : 26;
26598     } BCDETSTATUS_b;
26599   } ;
26600 
26601   union {
26602     __IOM uint32_t BCDETCRTL1;                  /*!< (@ 0x00002024) Battery Charging detection main control register           */
26603 
26604     struct {
26605       __IOM uint32_t BCWEAKPULLUPEN : 1;        /*!< [0..0] Enables weak source current to DP and DM                           */
26606       __IOM uint32_t BCWEAKPULLDOWNEN : 1;      /*!< [1..1] Enables weak sink current on DP and DM                             */
26607       __IOM uint32_t IDMSINKEN  : 1;            /*!< [2..2] Enables DM current sink                                            */
26608       __IOM uint32_t IDPSRCEN   : 1;            /*!< [3..3] Enables DP current source                                          */
26609       __IOM uint32_t VDPSRCEN   : 1;            /*!< [4..4] Enables DP voltage source                                          */
26610       __IOM uint32_t RDMPDWNEN  : 1;            /*!< [5..5] Enables DM BC 1.2 pull-down resistor                               */
26611       __IOM uint32_t VDMSRCEN   : 1;            /*!< [6..6] Enables DM voltage source                                          */
26612       __IOM uint32_t IDPSINKEN  : 1;            /*!< [7..7] Enables DP current sink                                            */
26613       __IOM uint32_t USBDCOMPREF : 2;           /*!< [9..8] Sets DP/DM vendor-specific comparator ref voltage                  */
26614             uint32_t            : 1;
26615       __IOM uint32_t USBDCOMPEN : 1;            /*!< [11..11] Enables DP/DM vendor-specific detection comparator               */
26616             uint32_t            : 19;
26617       __IOM uint32_t USBSWRESET : 1;            /*!< [31..31] Holds a USB controller and PHY in the reset for BC
26618                                                      detection                                                                 */
26619     } BCDETCRTL1_b;
26620   } ;
26621 
26622   union {
26623     __IOM uint32_t BCDETCRTL2;                  /*!< (@ 0x00002028) Battery Charging auxillary detection control
26624                                                                     register                                                   */
26625 
26626     struct {
26627       __IOM uint32_t CHARGEDETBYP : 1;          /*!< [0..0] BC detection bypass                                                */
26628       __IOM uint32_t FORCEDPATTACHED : 1;       /*!< [1..1] Force output dp_attached                                           */
26629       __IOM uint32_t FORCECPDET : 1;            /*!< [2..2] Force output charging port detected                                */
26630       __IOM uint32_t FORCEDCPDET : 1;           /*!< [3..3] Force output dedicated charging port detected                      */
26631             uint32_t            : 4;
26632       __IOM uint32_t BCWEAKPULLUPTUNE : 2;      /*!< [9..8] Weak source resistor to both DP and DM tuning. Trimmable.          */
26633       __IOM uint32_t BCWEAKPULLDOWNTUNE : 2;    /*!< [11..10] Weak sink resistor to both DP and DM tuning. Trimmable.          */
26634             uint32_t            : 20;
26635     } BCDETCRTL2_b;
26636   } ;
26637 } USB_Type;                                     /*!< Size = 8236 (0x202c)                                                      */
26638 
26639 
26640 
26641 /* =========================================================================================================================== */
26642 /* ================                                           VCOMP                                           ================ */
26643 /* =========================================================================================================================== */
26644 
26645 
26646 /**
26647   * @brief Voltage Comparator (VCOMP)
26648   */
26649 
26650 typedef struct {                                /*!< (@ 0x4000C000) VCOMP Structure                                            */
26651 
26652   union {
26653     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The Voltage Comparator Configuration Register
26654                                                                     contains the software control for selecting
26655                                                                     beween the 4 options for the positive input
26656                                                                     as well as the multiple options for the
26657                                                                     reference input.                                           */
26658 
26659     struct {
26660       __IOM uint32_t PSEL       : 2;            /*!< [1..0] This bitfield selects the positive input to the comparator.        */
26661             uint32_t            : 6;
26662       __IOM uint32_t NSEL       : 2;            /*!< [9..8] This bitfield selects the negative input to the comparator.        */
26663             uint32_t            : 6;
26664       __IOM uint32_t LVLSEL     : 4;            /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this
26665                                                      bitfield selects the voltage level for the negative input
26666                                                      to the comparator.                                                        */
26667             uint32_t            : 12;
26668     } CFG_b;
26669   } ;
26670 
26671   union {
26672     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) Status                                                     */
26673 
26674     struct {
26675       __IOM uint32_t CMPOUT     : 1;            /*!< [0..0] This bit is 1 if the positive input of the comparator
26676                                                      is greater than the negative input.                                       */
26677       __IOM uint32_t PWDSTAT    : 1;            /*!< [1..1] This bit indicates the power down state of the voltage
26678                                                      comparator.                                                               */
26679             uint32_t            : 30;
26680     } STAT_b;
26681   } ;
26682 
26683   union {
26684     __IOM uint32_t PWDKEY;                      /*!< (@ 0x00000008) Write a value of 0x37 to unlock, write any other
26685                                                                     value to lock. This register also indicates
26686                                                                     lock status when read. When in the unlccked
26687                                                                     state (i.e. 0x37 has been written), it reads
26688                                                                     as 1. When in the locked state, it reads
26689                                                                     as 0.                                                      */
26690 
26691     struct {
26692       __IOM uint32_t PWDKEY     : 32;           /*!< [31..0] Key register value.                                               */
26693     } PWDKEY_b;
26694   } ;
26695   __IM  uint32_t  RESERVED[125];
26696 
26697   union {
26698     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
26699                                                                     to generate the corresponding interrupt.                   */
26700 
26701     struct {
26702       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
26703       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
26704             uint32_t            : 30;
26705     } INTEN_b;
26706   } ;
26707 
26708   union {
26709     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
26710                                                                     cause of a recent interrupt.                               */
26711 
26712     struct {
26713       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
26714       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
26715             uint32_t            : 30;
26716     } INTSTAT_b;
26717   } ;
26718 
26719   union {
26720     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
26721                                                                     the interrupt status associated with that
26722                                                                     bit.                                                       */
26723 
26724     struct {
26725       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
26726       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
26727             uint32_t            : 30;
26728     } INTCLR_b;
26729   } ;
26730 
26731   union {
26732     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
26733                                                                     generate an interrupt from this module.
26734                                                                     (Generally used for testing purposes).                     */
26735 
26736     struct {
26737       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
26738       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
26739             uint32_t            : 30;
26740     } INTSET_b;
26741   } ;
26742 } VCOMP_Type;                                   /*!< Size = 528 (0x210)                                                        */
26743 
26744 
26745 
26746 /* =========================================================================================================================== */
26747 /* ================                                            WDT                                            ================ */
26748 /* =========================================================================================================================== */
26749 
26750 
26751 /**
26752   * @brief Watchdog Timer (WDT)
26753   */
26754 
26755 typedef struct {                                /*!< (@ 0x40024000) WDT Structure                                              */
26756 
26757   union {
26758     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) This is the configuration register for the watch
26759                                                                     dog timer. It controls the enable, interrupt
26760                                                                     set, clocks for the timer, the compare values
26761                                                                     for the counters to trigger a reset or interrupt.
26762                                                                     This register can only be written to if
26763                                                                     the watch dog timer is unlocked (WDTLOCK
26764                                                                     is not set).                                               */
26765 
26766     struct {
26767       __IOM uint32_t WDTEN      : 1;            /*!< [0..0] This bitfield enables the WDT.                                     */
26768       __IOM uint32_t INTEN      : 1;            /*!< [1..1] This bitfield enables the WDT interrupt. Note : This
26769                                                      bit must be set before the interrupt status bit will reflect
26770                                                      a watchdog timer expiration. The IER interrupt register
26771                                                      must also be enabled for a WDT interrupt to be sent to
26772                                                      the NVIC.                                                                 */
26773       __IOM uint32_t RESEN      : 1;            /*!< [2..2] This bitfield enables the WDT reset. This needs to be
26774                                                      set together with the WDREN bit in REG_RSTGEN_CFG register
26775                                                      (in reset gen) to trigger the reset.                                      */
26776       __IOM uint32_t DSPRESETINTEN : 1;         /*!< [3..3] This bitfield enables the DSP Reset Interrupt. This interrupt
26777                                                      is provided to the ARM CPU to notify it that a DSP's WDT
26778                                                      has expired and a reset has been issued to one of the DSP
26779                                                      cores.                                                                    */
26780             uint32_t            : 4;
26781       __IOM uint32_t RESVAL     : 8;            /*!< [15..8] This bitfield is the compare value for counter bits
26782                                                      7:0 to generate a watchdog reset. This will cause a software
26783                                                      reset.                                                                    */
26784       __IOM uint32_t INTVAL     : 8;            /*!< [23..16] This bitfield is the compare value for counter bits
26785                                                      7:0 to generate a watchdog interrupt.                                     */
26786       __IOM uint32_t CLKSEL     : 3;            /*!< [26..24] Select the frequency for the WDT. All values not enumerated
26787                                                      below are undefined.                                                      */
26788             uint32_t            : 5;
26789     } CFG_b;
26790   } ;
26791 
26792   union {
26793     __IOM uint32_t RSTRT;                       /*!< (@ 0x00000004) This register will Restart the watchdog timer.
26794                                                                     Writing a special key value into this register
26795                                                                     will result in the watch dog timer being
26796                                                                     reset, so that the count will start again.
26797                                                                     It is expected that the software will periodically
26798                                                                     write to this register to indicate that
26799                                                                     the system is functional. The watch dog
26800                                                                     timer can continue running when the system
26801                                                                     is in deep sleep, and the interrupt will
26802                                                                     trigger the wake. After the wake, the core
26803                                                                     can reset the watch dog timer.                             */
26804 
26805     struct {
26806       __IOM uint32_t RSTRT      : 8;            /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
26807                                                      This is a write only register. Reading this register will
26808                                                      only provide all 0.                                                       */
26809             uint32_t            : 24;
26810     } RSTRT_b;
26811   } ;
26812 
26813   union {
26814     __IOM uint32_t LOCK;                        /*!< (@ 0x00000008) This register locks the watch dog timer. Once
26815                                                                     it is locked, the configuration register
26816                                                                     (WDTCFG) for watch dog timer cannot be written
26817                                                                     to.                                                        */
26818 
26819     struct {
26820       __IOM uint32_t LOCK       : 8;            /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the
26821                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
26822             uint32_t            : 24;
26823     } LOCK_b;
26824   } ;
26825 
26826   union {
26827     __IOM uint32_t COUNT;                       /*!< (@ 0x0000000C) This register holds the current count for the
26828                                                                     watch dog timer. This is a read only register.
26829                                                                     SW cannot set the value in the counter,
26830                                                                     but can reset it.                                          */
26831 
26832     struct {
26833       __IOM uint32_t COUNT      : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
26834             uint32_t            : 24;
26835     } COUNT_b;
26836   } ;
26837 
26838   union {
26839     __IOM uint32_t DSP0CFG;                     /*!< (@ 0x00000010) This is the configuration register for the DSP0
26840                                                                     watch dog timer. It controls the enable,
26841                                                                     interrupt set, clocks for the timer, the
26842                                                                     compare values for the counters to trigger
26843                                                                     a reset or interrupt. This register can
26844                                                                     only be written to if the associated DSP0TLOCK
26845                                                                     is not set.                                                */
26846 
26847     struct {
26848       __IOM uint32_t DSP0WDTEN  : 1;            /*!< [0..0] This bitfield enables the WDT. Setting the lock implicitly
26849                                                      sets the WTDEN bit as well.                                               */
26850       __IOM uint32_t DSP0INTEN  : 1;            /*!< [1..1] This bitfield enables the DSP0 WDT interrupt. Note :
26851                                                      This bit must be set before the interrupt status bit will
26852                                                      reflect a watchdog timer expiration. The IER interrupt
26853                                                      register must also be enabled for a WDT interrupt to be
26854                                                      sent to the NVIC.                                                         */
26855       __IOM uint32_t DSP0RESEN  : 1;            /*!< [2..2] This bitfield enables the DSP0 reset.                              */
26856       __IOM uint32_t DSP0PMRESEN : 1;           /*!< [3..3] This bitfield enables the DSP0 Power Controller (PM)
26857                                                      reset. This needs to be set together with the DSP0WDTEN
26858                                                      bit to allow the reset to trigger.                                        */
26859             uint32_t            : 4;
26860       __IOM uint32_t DSP0RESVAL : 8;            /*!< [15..8] This bitfield is the compare value for counter bits
26861                                                      7:0 to generate a watchdog reset for the DSP logic. This
26862                                                      will cause a software reset to the DSP core if the RESEN
26863                                                      bit is set and optionally interrupt the CPU.                              */
26864       __IOM uint32_t DSP0INTVAL : 8;            /*!< [23..16] This bitfield is the compare value for counter bits
26865                                                      7:0 to generate a watchdog interrupt.                                     */
26866       __IOM uint32_t DSP0PMRESVAL : 8;          /*!< [31..24] This bitfield is the compare value for counter bits
26867                                                      7:0 to generate a watchdog reset. This will cause a software
26868                                                      reset to the DSP Power Management logic if the PMRESEN
26869                                                      bit is set and optionally interrupt the CPU.                              */
26870     } DSP0CFG_b;
26871   } ;
26872 
26873   union {
26874     __IOM uint32_t DSP0RSTRT;                   /*!< (@ 0x00000014) This register will restart the watchdog timer.
26875                                                                     Writing a special key value into this register
26876                                                                     will result in the watch dog timer being
26877                                                                     reset, so that the count will start again.
26878                                                                     It is expected that the software will periodically
26879                                                                     write to this register to indicate that
26880                                                                     the system is functional. The watch dog
26881                                                                     timer can continue running when the system
26882                                                                     is in deep sleep, and the interrupt will
26883                                                                     trigger the wake. After the wake, the core
26884                                                                     can reset the watch dog timer.                             */
26885 
26886     struct {
26887       __IOM uint32_t DSP0RSTART : 8;            /*!< [7..0] Writing 0x69 to DSP0RSTRT restarts the watchdog timer.
26888                                                      This is a write only register. Reading this register will
26889                                                      return 0.                                                                 */
26890             uint32_t            : 24;
26891     } DSP0RSTRT_b;
26892   } ;
26893 
26894   union {
26895     __IOM uint32_t DSP0TLOCK;                   /*!< (@ 0x00000018) This register locks the watch dog timer. Once
26896                                                                     it is locked, the configuration register
26897                                                                     (DSP0CFG) for watch dog timer cannot be
26898                                                                     written to and the timer is automatically
26899                                                                     enabled (WDTEN is set).                                    */
26900 
26901     struct {
26902       __IOM uint32_t DSP0LOCK   : 8;            /*!< [7..0] Writing 0xa7 locks the watchdog timer. Once locked, the
26903                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
26904             uint32_t            : 24;
26905     } DSP0TLOCK_b;
26906   } ;
26907 
26908   union {
26909     __IOM uint32_t DSP0COUNT;                   /*!< (@ 0x0000001C) This register holds the current count for the
26910                                                                     watch dog timer. This is a read only register.
26911                                                                     SW cannot set the value in the counter,
26912                                                                     but can reset it.                                          */
26913 
26914     struct {
26915       __IOM uint32_t DSP0COUNT  : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
26916             uint32_t            : 24;
26917     } DSP0COUNT_b;
26918   } ;
26919 
26920   union {
26921     __IOM uint32_t DSP1CFG;                     /*!< (@ 0x00000020) This is the configuration register for the DSP1
26922                                                                     watch dog timer. It controls the enable,
26923                                                                     interrupt set, clocks for the timer, the
26924                                                                     compare values for the counters to trigger
26925                                                                     a reset or interrupt. This register can
26926                                                                     only be written to if the associated DSP1TLOCK
26927                                                                     is not set.                                                */
26928 
26929     struct {
26930       __IOM uint32_t DSP1WDTEN  : 1;            /*!< [0..0] This bitfield enables the WDT. Setting the lock implicitly
26931                                                      sets the WTDEN bit as well.                                               */
26932       __IOM uint32_t DSP1INTEN  : 1;            /*!< [1..1] This bitfield enables the DSP1 WDT interrupt. Note :
26933                                                      This bit must be set before the interrupt status bit will
26934                                                      reflect a watchdog timer expiration. The IER interrupt
26935                                                      register must also be enabled for a WDT interrupt to be
26936                                                      sent to the NVIC.                                                         */
26937       __IOM uint32_t DSP1RESEN  : 1;            /*!< [2..2] This bitfield enables the DSP1 reset.                              */
26938       __IOM uint32_t DSP1PMRESEN : 1;           /*!< [3..3] This bitfield enables the DSP1 Power Controller (PM)
26939                                                      reset. This needs to be set together with the DSP1WDTEN
26940                                                      bit to allow the reset to trigger.                                        */
26941             uint32_t            : 4;
26942       __IOM uint32_t DSP1RESVAL : 8;            /*!< [15..8] This bitfield is the compare value for counter bits
26943                                                      7:0 to generate a watchdog reset for the DSP logic. This
26944                                                      will cause a software reset to the DSP core if the RESEN
26945                                                      bit is set and optionally interrupt the CPU.                              */
26946       __IOM uint32_t DSP1INTVAL : 8;            /*!< [23..16] This bitfield is the compare value for counter bits
26947                                                      7:0 to generate a watchdog interrupt.                                     */
26948       __IOM uint32_t DSP1PMRESVAL : 8;          /*!< [31..24] This bitfield is the compare value for counter bits
26949                                                      7:0 to generate a watchdog reset. This will cause a software
26950                                                      reset to the DSP Power Management logic if the PMRESEN
26951                                                      bit is set and optionally interrupt the CPU.                              */
26952     } DSP1CFG_b;
26953   } ;
26954 
26955   union {
26956     __IOM uint32_t DSP1RSTRT;                   /*!< (@ 0x00000024) This register will restart the watchdog timer.
26957                                                                     Writing a special key value into this register
26958                                                                     will result in the watch dog timer being
26959                                                                     reset, so that the count will start again.
26960                                                                     It is expected that the software will periodically
26961                                                                     write to this register to indicate that
26962                                                                     the system is functional. The watch dog
26963                                                                     timer can continue running when the system
26964                                                                     is in deep sleep, and the interrupt will
26965                                                                     trigger the wake. After the wake, the core
26966                                                                     can reset the watch dog timer.                             */
26967 
26968     struct {
26969       __IOM uint32_t DSP1RSTART : 8;            /*!< [7..0] Writing 0xd2 to DSP1RSTRT restarts the watchdog timer.
26970                                                      This is a write only register. Reading this register will
26971                                                      return 0.                                                                 */
26972             uint32_t            : 24;
26973     } DSP1RSTRT_b;
26974   } ;
26975 
26976   union {
26977     __IOM uint32_t DSP1TLOCK;                   /*!< (@ 0x00000028) This register locks the watch dog timer. Once
26978                                                                     it is locked, the configuration register
26979                                                                     (DSP1CFG) for watch dog timer cannot be
26980                                                                     written to and the timer is automatically
26981                                                                     enabled (WDTEN is set).                                    */
26982 
26983     struct {
26984       __IOM uint32_t DSP1LOCK   : 8;            /*!< [7..0] Writing 0x4e locks the watchdog timer. Once locked, the
26985                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
26986             uint32_t            : 24;
26987     } DSP1TLOCK_b;
26988   } ;
26989 
26990   union {
26991     __IOM uint32_t DSP1COUNT;                   /*!< (@ 0x0000002C) This register holds the current count for the
26992                                                                     watch dog timer. This is a read only register.
26993                                                                     SW cannot set the value in the counter,
26994                                                                     but can reset it.                                          */
26995 
26996     struct {
26997       __IOM uint32_t DSP1COUNT  : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
26998             uint32_t            : 24;
26999     } DSP1COUNT_b;
27000   } ;
27001   __IM  uint32_t  RESERVED[116];
27002 
27003   union {
27004     __IOM uint32_t WDTIEREN;                    /*!< (@ 0x00000200) Set bits in this register to allow this module
27005                                                                     to generate the corresponding interrupt.                   */
27006 
27007     struct {
27008       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27009       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27010                                                      or pmreset to the DSP core. This is used to interrupt the
27011                                                      main CPU.                                                                 */
27012             uint32_t            : 30;
27013     } WDTIEREN_b;
27014   } ;
27015 
27016   union {
27017     __IOM uint32_t WDTIERSTAT;                  /*!< (@ 0x00000204) Read bits from this register to discover the
27018                                                                     cause of a recent interrupt.                               */
27019 
27020     struct {
27021       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27022       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27023                                                      or pmreset to the DSP core. This is used to interrupt the
27024                                                      main CPU.                                                                 */
27025             uint32_t            : 30;
27026     } WDTIERSTAT_b;
27027   } ;
27028 
27029   union {
27030     __IOM uint32_t WDTIERCLR;                   /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
27031                                                                     the interrupt status associated with that
27032                                                                     bit.                                                       */
27033 
27034     struct {
27035       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27036       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27037                                                      or pmreset to the DSP core. This is used to interrupt the
27038                                                      main CPU.                                                                 */
27039             uint32_t            : 30;
27040     } WDTIERCLR_b;
27041   } ;
27042 
27043   union {
27044     __IOM uint32_t WDTIERSET;                   /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
27045                                                                     generate an interrupt from this module.
27046                                                                     (Generally used for testing purposes).                     */
27047 
27048     struct {
27049       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27050       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27051                                                      or pmreset to the DSP core. This is used to interrupt the
27052                                                      main CPU.                                                                 */
27053             uint32_t            : 30;
27054     } WDTIERSET_b;
27055   } ;
27056 
27057   union {
27058     __IOM uint32_t DSP0IEREN;                   /*!< (@ 0x00000210) Set bits in this register to allow this module
27059                                                                     to generate the corresponding interrupt.                   */
27060 
27061     struct {
27062       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27063             uint32_t            : 31;
27064     } DSP0IEREN_b;
27065   } ;
27066 
27067   union {
27068     __IOM uint32_t DSP0IERSTAT;                 /*!< (@ 0x00000214) Read bits from this register to discover the
27069                                                                     cause of a recent interrupt.                               */
27070 
27071     struct {
27072       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27073             uint32_t            : 31;
27074     } DSP0IERSTAT_b;
27075   } ;
27076 
27077   union {
27078     __IOM uint32_t DSP0IERCLR;                  /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
27079                                                                     the interrupt status associated with that
27080                                                                     bit.                                                       */
27081 
27082     struct {
27083       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27084             uint32_t            : 31;
27085     } DSP0IERCLR_b;
27086   } ;
27087 
27088   union {
27089     __IOM uint32_t DSP0IERSET;                  /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
27090                                                                     generate an interrupt from this module.
27091                                                                     (Generally used for testing purposes).                     */
27092 
27093     struct {
27094       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27095             uint32_t            : 31;
27096     } DSP0IERSET_b;
27097   } ;
27098 
27099   union {
27100     __IOM uint32_t DSP1IEREN;                   /*!< (@ 0x00000220) Set bits in this register to allow this module
27101                                                                     to generate the corresponding interrupt.                   */
27102 
27103     struct {
27104       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27105             uint32_t            : 31;
27106     } DSP1IEREN_b;
27107   } ;
27108 
27109   union {
27110     __IOM uint32_t DSP1IERSTAT;                 /*!< (@ 0x00000224) Read bits from this register to discover the
27111                                                                     cause of a recent interrupt.                               */
27112 
27113     struct {
27114       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27115             uint32_t            : 31;
27116     } DSP1IERSTAT_b;
27117   } ;
27118 
27119   union {
27120     __IOM uint32_t DSP1IERCLR;                  /*!< (@ 0x00000228) Write a 1 to a bit in this register to clear
27121                                                                     the interrupt status associated with that
27122                                                                     bit.                                                       */
27123 
27124     struct {
27125       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27126             uint32_t            : 31;
27127     } DSP1IERCLR_b;
27128   } ;
27129 
27130   union {
27131     __IOM uint32_t DSP1IERSET;                  /*!< (@ 0x0000022C) Write a 1 to a bit in this register to instantly
27132                                                                     generate an interrupt from this module.
27133                                                                     (Generally used for testing purposes).                     */
27134 
27135     struct {
27136       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27137             uint32_t            : 31;
27138     } DSP1IERSET_b;
27139   } ;
27140 } WDT_Type;                                     /*!< Size = 560 (0x230)                                                        */
27141 
27142 
27143 /** @} */ /* End of group Device_Peripheral_peripherals */
27144 
27145 
27146 /* =========================================================================================================================== */
27147 /* ================                          Device Specific Peripheral Address Map                           ================ */
27148 /* =========================================================================================================================== */
27149 
27150 
27151 /** @addtogroup Device_Peripheral_peripheralAddr
27152   * @{
27153   */
27154 
27155 #define ADC_BASE                    0x40038000UL
27156 #define APBDMA_BASE                 0x40011000UL
27157 #define AUDADC_BASE                 0x40210000UL
27158 #define CLKGEN_BASE                 0x40004000UL
27159 #define CPU_BASE                    0x48000000UL
27160 #define CRYPTO_BASE                 0x400C0000UL
27161 #define DC_BASE                     0x400A0000UL
27162 #define DSI_BASE                    0x400A8000UL
27163 #define DSP_BASE                    0x40100000UL
27164 #define FPIO_BASE                   0x48001000UL
27165 #define GPIO_BASE                   0x40010000UL
27166 #define GPU_BASE                    0x40090000UL
27167 #define I2S0_BASE                   0x40208000UL
27168 #define I2S1_BASE                   0x40209000UL
27169 #define IOM0_BASE                   0x40050000UL
27170 #define IOM1_BASE                   0x40051000UL
27171 #define IOM2_BASE                   0x40052000UL
27172 #define IOM3_BASE                   0x40053000UL
27173 #define IOM4_BASE                   0x40054000UL
27174 #define IOM5_BASE                   0x40055000UL
27175 #define IOM6_BASE                   0x40056000UL
27176 #define IOM7_BASE                   0x40057000UL
27177 #define IOSLAVE_BASE                0x40034000UL
27178 #define MCUCTRL_BASE                0x40020000UL
27179 #define MSPI0_BASE                  0x40060000UL
27180 #define MSPI1_BASE                  0x40061000UL
27181 #define MSPI2_BASE                  0x40062000UL
27182 #define PDM0_BASE                   0x40201000UL
27183 #define PDM1_BASE                   0x40202000UL
27184 #define PDM2_BASE                   0x40203000UL
27185 #define PDM3_BASE                   0x40204000UL
27186 #define PWRCTRL_BASE                0x40021000UL
27187 #define RSTGEN_BASE                 0x40000000UL
27188 #define RTC_BASE                    0x40004800UL
27189 #define SDIO_BASE                   0x40070000UL
27190 #define SECURITY_BASE               0x40030000UL
27191 #define STIMER_BASE                 0x40008800UL
27192 #define TIMER_BASE                  0x40008000UL
27193 #define UART0_BASE                  0x4001C000UL
27194 #define UART1_BASE                  0x4001D000UL
27195 #define UART2_BASE                  0x4001E000UL
27196 #define UART3_BASE                  0x4001F000UL
27197 #define USBPHY_BASE                 0x400B4000UL
27198 #define USB_BASE                    0x400B0000UL
27199 #define VCOMP_BASE                  0x4000C000UL
27200 #define WDT_BASE                    0x40024000UL
27201 
27202 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
27203 
27204 
27205 /* =========================================================================================================================== */
27206 /* ================                                  Peripheral declaration                                   ================ */
27207 /* =========================================================================================================================== */
27208 
27209 
27210 /** @addtogroup Device_Peripheral_declaration
27211   * @{
27212   */
27213 
27214 #define ADC                         ((ADC_Type*)               ADC_BASE)
27215 #define APBDMA                      ((APBDMA_Type*)            APBDMA_BASE)
27216 #define AUDADC                      ((AUDADC_Type*)            AUDADC_BASE)
27217 #define CLKGEN                      ((CLKGEN_Type*)            CLKGEN_BASE)
27218 #define CPU                         ((CPU_Type*)               CPU_BASE)
27219 #define CRYPTO                      ((CRYPTO_Type*)            CRYPTO_BASE)
27220 #define DC                          ((DC_Type*)                DC_BASE)
27221 #define DSI                         ((DSI_Type*)               DSI_BASE)
27222 #define DSP                         ((DSP_Type*)               DSP_BASE)
27223 #define FPIO                        ((FPIO_Type*)              FPIO_BASE)
27224 #define GPIO                        ((GPIO_Type*)              GPIO_BASE)
27225 #define GPU                         ((GPU_Type*)               GPU_BASE)
27226 #define I2S0                        ((I2S0_Type*)              I2S0_BASE)
27227 #define I2S1                        ((I2S0_Type*)              I2S1_BASE)
27228 #define IOM0                        ((IOM0_Type*)              IOM0_BASE)
27229 #define IOM1                        ((IOM0_Type*)              IOM1_BASE)
27230 #define IOM2                        ((IOM0_Type*)              IOM2_BASE)
27231 #define IOM3                        ((IOM0_Type*)              IOM3_BASE)
27232 #define IOM4                        ((IOM0_Type*)              IOM4_BASE)
27233 #define IOM5                        ((IOM0_Type*)              IOM5_BASE)
27234 #define IOM6                        ((IOM0_Type*)              IOM6_BASE)
27235 #define IOM7                        ((IOM0_Type*)              IOM7_BASE)
27236 #define IOSLAVE                     ((IOSLAVE_Type*)           IOSLAVE_BASE)
27237 #define MCUCTRL                     ((MCUCTRL_Type*)           MCUCTRL_BASE)
27238 #define MSPI0                       ((MSPI0_Type*)             MSPI0_BASE)
27239 #define MSPI1                       ((MSPI0_Type*)             MSPI1_BASE)
27240 #define MSPI2                       ((MSPI0_Type*)             MSPI2_BASE)
27241 #define PDM0                        ((PDM0_Type*)              PDM0_BASE)
27242 #define PDM1                        ((PDM0_Type*)              PDM1_BASE)
27243 #define PDM2                        ((PDM0_Type*)              PDM2_BASE)
27244 #define PDM3                        ((PDM0_Type*)              PDM3_BASE)
27245 #define PWRCTRL                     ((PWRCTRL_Type*)           PWRCTRL_BASE)
27246 #define RSTGEN                      ((RSTGEN_Type*)            RSTGEN_BASE)
27247 #define RTC                         ((RTC_Type*)               RTC_BASE)
27248 #define SDIO                        ((SDIO_Type*)              SDIO_BASE)
27249 #define SECURITY                    ((SECURITY_Type*)          SECURITY_BASE)
27250 #define STIMER                      ((STIMER_Type*)            STIMER_BASE)
27251 #define TIMER                       ((TIMER_Type*)             TIMER_BASE)
27252 #define UART0                       ((UART0_Type*)             UART0_BASE)
27253 #define UART1                       ((UART0_Type*)             UART1_BASE)
27254 #define UART2                       ((UART0_Type*)             UART2_BASE)
27255 #define UART3                       ((UART0_Type*)             UART3_BASE)
27256 #define USBPHY                      ((USBPHY_Type*)            USBPHY_BASE)
27257 #define USB                         ((USB_Type*)               USB_BASE)
27258 #define VCOMP                       ((VCOMP_Type*)             VCOMP_BASE)
27259 #define WDT                         ((WDT_Type*)               WDT_BASE)
27260 
27261 /** @} */ /* End of group Device_Peripheral_declaration */
27262 
27263 
27264 /* =========================================  End of section using anonymous unions  ========================================= */
27265 #if defined (__CC_ARM)
27266   #pragma pop
27267 #elif defined (__ICCARM__)
27268   /* leave anonymous unions enabled */
27269 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
27270   #pragma clang diagnostic pop
27271 #elif defined (__GNUC__)
27272   /* anonymous unions are enabled by default */
27273 #elif defined (__TMS470__)
27274   /* anonymous unions are enabled by default */
27275 #elif defined (__TASKING__)
27276   #pragma warning restore
27277 #elif defined (__CSMC__)
27278   /* anonymous unions are enabled by default */
27279 #endif
27280 
27281 
27282 /* =========================================================================================================================== */
27283 /* ================                                Pos/Mask Peripheral Section                                ================ */
27284 /* =========================================================================================================================== */
27285 
27286 
27287 /** @addtogroup PosMask_peripherals
27288   * @{
27289   */
27290 
27291 
27292 
27293 /* =========================================================================================================================== */
27294 /* ================                                            ADC                                            ================ */
27295 /* =========================================================================================================================== */
27296 
27297 /* ==========================================================  CFG  ========================================================== */
27298 #define ADC_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
27299 #define ADC_CFG_CLKSEL_Msk                (0x3000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
27300 #define ADC_CFG_RPTTRIGSEL_Pos            (20UL)                    /*!< RPTTRIGSEL (Bit 20)                                   */
27301 #define ADC_CFG_RPTTRIGSEL_Msk            (0x100000UL)              /*!< RPTTRIGSEL (Bitfield-Mask: 0x01)                      */
27302 #define ADC_CFG_TRIGPOL_Pos               (19UL)                    /*!< TRIGPOL (Bit 19)                                      */
27303 #define ADC_CFG_TRIGPOL_Msk               (0x80000UL)               /*!< TRIGPOL (Bitfield-Mask: 0x01)                         */
27304 #define ADC_CFG_TRIGSEL_Pos               (16UL)                    /*!< TRIGSEL (Bit 16)                                      */
27305 #define ADC_CFG_TRIGSEL_Msk               (0x70000UL)               /*!< TRIGSEL (Bitfield-Mask: 0x07)                         */
27306 #define ADC_CFG_DFIFORDEN_Pos             (12UL)                    /*!< DFIFORDEN (Bit 12)                                    */
27307 #define ADC_CFG_DFIFORDEN_Msk             (0x1000UL)                /*!< DFIFORDEN (Bitfield-Mask: 0x01)                       */
27308 #define ADC_CFG_CKMODE_Pos                (4UL)                     /*!< CKMODE (Bit 4)                                        */
27309 #define ADC_CFG_CKMODE_Msk                (0x10UL)                  /*!< CKMODE (Bitfield-Mask: 0x01)                          */
27310 #define ADC_CFG_LPMODE_Pos                (3UL)                     /*!< LPMODE (Bit 3)                                        */
27311 #define ADC_CFG_LPMODE_Msk                (0x8UL)                   /*!< LPMODE (Bitfield-Mask: 0x01)                          */
27312 #define ADC_CFG_RPTEN_Pos                 (2UL)                     /*!< RPTEN (Bit 2)                                         */
27313 #define ADC_CFG_RPTEN_Msk                 (0x4UL)                   /*!< RPTEN (Bitfield-Mask: 0x01)                           */
27314 #define ADC_CFG_ADCEN_Pos                 (0UL)                     /*!< ADCEN (Bit 0)                                         */
27315 #define ADC_CFG_ADCEN_Msk                 (0x1UL)                   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
27316 /* =========================================================  STAT  ========================================================== */
27317 #define ADC_STAT_PWDSTAT_Pos              (0UL)                     /*!< PWDSTAT (Bit 0)                                       */
27318 #define ADC_STAT_PWDSTAT_Msk              (0x1UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
27319 /* ==========================================================  SWT  ========================================================== */
27320 #define ADC_SWT_SWT_Pos                   (0UL)                     /*!< SWT (Bit 0)                                           */
27321 #define ADC_SWT_SWT_Msk                   (0xffUL)                  /*!< SWT (Bitfield-Mask: 0xff)                             */
27322 /* ========================================================  SL0CFG  ========================================================= */
27323 #define ADC_SL0CFG_ADSEL0_Pos             (24UL)                    /*!< ADSEL0 (Bit 24)                                       */
27324 #define ADC_SL0CFG_ADSEL0_Msk             (0x7000000UL)             /*!< ADSEL0 (Bitfield-Mask: 0x07)                          */
27325 #define ADC_SL0CFG_TRKCYC0_Pos            (18UL)                    /*!< TRKCYC0 (Bit 18)                                      */
27326 #define ADC_SL0CFG_TRKCYC0_Msk            (0xfc0000UL)              /*!< TRKCYC0 (Bitfield-Mask: 0x3f)                         */
27327 #define ADC_SL0CFG_PRMODE0_Pos            (16UL)                    /*!< PRMODE0 (Bit 16)                                      */
27328 #define ADC_SL0CFG_PRMODE0_Msk            (0x30000UL)               /*!< PRMODE0 (Bitfield-Mask: 0x03)                         */
27329 #define ADC_SL0CFG_CHSEL0_Pos             (8UL)                     /*!< CHSEL0 (Bit 8)                                        */
27330 #define ADC_SL0CFG_CHSEL0_Msk             (0xf00UL)                 /*!< CHSEL0 (Bitfield-Mask: 0x0f)                          */
27331 #define ADC_SL0CFG_WCEN0_Pos              (1UL)                     /*!< WCEN0 (Bit 1)                                         */
27332 #define ADC_SL0CFG_WCEN0_Msk              (0x2UL)                   /*!< WCEN0 (Bitfield-Mask: 0x01)                           */
27333 #define ADC_SL0CFG_SLEN0_Pos              (0UL)                     /*!< SLEN0 (Bit 0)                                         */
27334 #define ADC_SL0CFG_SLEN0_Msk              (0x1UL)                   /*!< SLEN0 (Bitfield-Mask: 0x01)                           */
27335 /* ========================================================  SL1CFG  ========================================================= */
27336 #define ADC_SL1CFG_ADSEL1_Pos             (24UL)                    /*!< ADSEL1 (Bit 24)                                       */
27337 #define ADC_SL1CFG_ADSEL1_Msk             (0x7000000UL)             /*!< ADSEL1 (Bitfield-Mask: 0x07)                          */
27338 #define ADC_SL1CFG_TRKCYC1_Pos            (18UL)                    /*!< TRKCYC1 (Bit 18)                                      */
27339 #define ADC_SL1CFG_TRKCYC1_Msk            (0xfc0000UL)              /*!< TRKCYC1 (Bitfield-Mask: 0x3f)                         */
27340 #define ADC_SL1CFG_PRMODE1_Pos            (16UL)                    /*!< PRMODE1 (Bit 16)                                      */
27341 #define ADC_SL1CFG_PRMODE1_Msk            (0x30000UL)               /*!< PRMODE1 (Bitfield-Mask: 0x03)                         */
27342 #define ADC_SL1CFG_CHSEL1_Pos             (8UL)                     /*!< CHSEL1 (Bit 8)                                        */
27343 #define ADC_SL1CFG_CHSEL1_Msk             (0xf00UL)                 /*!< CHSEL1 (Bitfield-Mask: 0x0f)                          */
27344 #define ADC_SL1CFG_WCEN1_Pos              (1UL)                     /*!< WCEN1 (Bit 1)                                         */
27345 #define ADC_SL1CFG_WCEN1_Msk              (0x2UL)                   /*!< WCEN1 (Bitfield-Mask: 0x01)                           */
27346 #define ADC_SL1CFG_SLEN1_Pos              (0UL)                     /*!< SLEN1 (Bit 0)                                         */
27347 #define ADC_SL1CFG_SLEN1_Msk              (0x1UL)                   /*!< SLEN1 (Bitfield-Mask: 0x01)                           */
27348 /* ========================================================  SL2CFG  ========================================================= */
27349 #define ADC_SL2CFG_ADSEL2_Pos             (24UL)                    /*!< ADSEL2 (Bit 24)                                       */
27350 #define ADC_SL2CFG_ADSEL2_Msk             (0x7000000UL)             /*!< ADSEL2 (Bitfield-Mask: 0x07)                          */
27351 #define ADC_SL2CFG_TRKCYC2_Pos            (18UL)                    /*!< TRKCYC2 (Bit 18)                                      */
27352 #define ADC_SL2CFG_TRKCYC2_Msk            (0xfc0000UL)              /*!< TRKCYC2 (Bitfield-Mask: 0x3f)                         */
27353 #define ADC_SL2CFG_PRMODE2_Pos            (16UL)                    /*!< PRMODE2 (Bit 16)                                      */
27354 #define ADC_SL2CFG_PRMODE2_Msk            (0x30000UL)               /*!< PRMODE2 (Bitfield-Mask: 0x03)                         */
27355 #define ADC_SL2CFG_CHSEL2_Pos             (8UL)                     /*!< CHSEL2 (Bit 8)                                        */
27356 #define ADC_SL2CFG_CHSEL2_Msk             (0xf00UL)                 /*!< CHSEL2 (Bitfield-Mask: 0x0f)                          */
27357 #define ADC_SL2CFG_WCEN2_Pos              (1UL)                     /*!< WCEN2 (Bit 1)                                         */
27358 #define ADC_SL2CFG_WCEN2_Msk              (0x2UL)                   /*!< WCEN2 (Bitfield-Mask: 0x01)                           */
27359 #define ADC_SL2CFG_SLEN2_Pos              (0UL)                     /*!< SLEN2 (Bit 0)                                         */
27360 #define ADC_SL2CFG_SLEN2_Msk              (0x1UL)                   /*!< SLEN2 (Bitfield-Mask: 0x01)                           */
27361 /* ========================================================  SL3CFG  ========================================================= */
27362 #define ADC_SL3CFG_ADSEL3_Pos             (24UL)                    /*!< ADSEL3 (Bit 24)                                       */
27363 #define ADC_SL3CFG_ADSEL3_Msk             (0x7000000UL)             /*!< ADSEL3 (Bitfield-Mask: 0x07)                          */
27364 #define ADC_SL3CFG_TRKCYC3_Pos            (18UL)                    /*!< TRKCYC3 (Bit 18)                                      */
27365 #define ADC_SL3CFG_TRKCYC3_Msk            (0xfc0000UL)              /*!< TRKCYC3 (Bitfield-Mask: 0x3f)                         */
27366 #define ADC_SL3CFG_PRMODE3_Pos            (16UL)                    /*!< PRMODE3 (Bit 16)                                      */
27367 #define ADC_SL3CFG_PRMODE3_Msk            (0x30000UL)               /*!< PRMODE3 (Bitfield-Mask: 0x03)                         */
27368 #define ADC_SL3CFG_CHSEL3_Pos             (8UL)                     /*!< CHSEL3 (Bit 8)                                        */
27369 #define ADC_SL3CFG_CHSEL3_Msk             (0xf00UL)                 /*!< CHSEL3 (Bitfield-Mask: 0x0f)                          */
27370 #define ADC_SL3CFG_WCEN3_Pos              (1UL)                     /*!< WCEN3 (Bit 1)                                         */
27371 #define ADC_SL3CFG_WCEN3_Msk              (0x2UL)                   /*!< WCEN3 (Bitfield-Mask: 0x01)                           */
27372 #define ADC_SL3CFG_SLEN3_Pos              (0UL)                     /*!< SLEN3 (Bit 0)                                         */
27373 #define ADC_SL3CFG_SLEN3_Msk              (0x1UL)                   /*!< SLEN3 (Bitfield-Mask: 0x01)                           */
27374 /* ========================================================  SL4CFG  ========================================================= */
27375 #define ADC_SL4CFG_ADSEL4_Pos             (24UL)                    /*!< ADSEL4 (Bit 24)                                       */
27376 #define ADC_SL4CFG_ADSEL4_Msk             (0x7000000UL)             /*!< ADSEL4 (Bitfield-Mask: 0x07)                          */
27377 #define ADC_SL4CFG_TRKCYC4_Pos            (18UL)                    /*!< TRKCYC4 (Bit 18)                                      */
27378 #define ADC_SL4CFG_TRKCYC4_Msk            (0xfc0000UL)              /*!< TRKCYC4 (Bitfield-Mask: 0x3f)                         */
27379 #define ADC_SL4CFG_PRMODE4_Pos            (16UL)                    /*!< PRMODE4 (Bit 16)                                      */
27380 #define ADC_SL4CFG_PRMODE4_Msk            (0x30000UL)               /*!< PRMODE4 (Bitfield-Mask: 0x03)                         */
27381 #define ADC_SL4CFG_CHSEL4_Pos             (8UL)                     /*!< CHSEL4 (Bit 8)                                        */
27382 #define ADC_SL4CFG_CHSEL4_Msk             (0xf00UL)                 /*!< CHSEL4 (Bitfield-Mask: 0x0f)                          */
27383 #define ADC_SL4CFG_WCEN4_Pos              (1UL)                     /*!< WCEN4 (Bit 1)                                         */
27384 #define ADC_SL4CFG_WCEN4_Msk              (0x2UL)                   /*!< WCEN4 (Bitfield-Mask: 0x01)                           */
27385 #define ADC_SL4CFG_SLEN4_Pos              (0UL)                     /*!< SLEN4 (Bit 0)                                         */
27386 #define ADC_SL4CFG_SLEN4_Msk              (0x1UL)                   /*!< SLEN4 (Bitfield-Mask: 0x01)                           */
27387 /* ========================================================  SL5CFG  ========================================================= */
27388 #define ADC_SL5CFG_ADSEL5_Pos             (24UL)                    /*!< ADSEL5 (Bit 24)                                       */
27389 #define ADC_SL5CFG_ADSEL5_Msk             (0x7000000UL)             /*!< ADSEL5 (Bitfield-Mask: 0x07)                          */
27390 #define ADC_SL5CFG_TRKCYC5_Pos            (18UL)                    /*!< TRKCYC5 (Bit 18)                                      */
27391 #define ADC_SL5CFG_TRKCYC5_Msk            (0xfc0000UL)              /*!< TRKCYC5 (Bitfield-Mask: 0x3f)                         */
27392 #define ADC_SL5CFG_PRMODE5_Pos            (16UL)                    /*!< PRMODE5 (Bit 16)                                      */
27393 #define ADC_SL5CFG_PRMODE5_Msk            (0x30000UL)               /*!< PRMODE5 (Bitfield-Mask: 0x03)                         */
27394 #define ADC_SL5CFG_CHSEL5_Pos             (8UL)                     /*!< CHSEL5 (Bit 8)                                        */
27395 #define ADC_SL5CFG_CHSEL5_Msk             (0xf00UL)                 /*!< CHSEL5 (Bitfield-Mask: 0x0f)                          */
27396 #define ADC_SL5CFG_WCEN5_Pos              (1UL)                     /*!< WCEN5 (Bit 1)                                         */
27397 #define ADC_SL5CFG_WCEN5_Msk              (0x2UL)                   /*!< WCEN5 (Bitfield-Mask: 0x01)                           */
27398 #define ADC_SL5CFG_SLEN5_Pos              (0UL)                     /*!< SLEN5 (Bit 0)                                         */
27399 #define ADC_SL5CFG_SLEN5_Msk              (0x1UL)                   /*!< SLEN5 (Bitfield-Mask: 0x01)                           */
27400 /* ========================================================  SL6CFG  ========================================================= */
27401 #define ADC_SL6CFG_ADSEL6_Pos             (24UL)                    /*!< ADSEL6 (Bit 24)                                       */
27402 #define ADC_SL6CFG_ADSEL6_Msk             (0x7000000UL)             /*!< ADSEL6 (Bitfield-Mask: 0x07)                          */
27403 #define ADC_SL6CFG_TRKCYC6_Pos            (18UL)                    /*!< TRKCYC6 (Bit 18)                                      */
27404 #define ADC_SL6CFG_TRKCYC6_Msk            (0xfc0000UL)              /*!< TRKCYC6 (Bitfield-Mask: 0x3f)                         */
27405 #define ADC_SL6CFG_PRMODE6_Pos            (16UL)                    /*!< PRMODE6 (Bit 16)                                      */
27406 #define ADC_SL6CFG_PRMODE6_Msk            (0x30000UL)               /*!< PRMODE6 (Bitfield-Mask: 0x03)                         */
27407 #define ADC_SL6CFG_CHSEL6_Pos             (8UL)                     /*!< CHSEL6 (Bit 8)                                        */
27408 #define ADC_SL6CFG_CHSEL6_Msk             (0xf00UL)                 /*!< CHSEL6 (Bitfield-Mask: 0x0f)                          */
27409 #define ADC_SL6CFG_WCEN6_Pos              (1UL)                     /*!< WCEN6 (Bit 1)                                         */
27410 #define ADC_SL6CFG_WCEN6_Msk              (0x2UL)                   /*!< WCEN6 (Bitfield-Mask: 0x01)                           */
27411 #define ADC_SL6CFG_SLEN6_Pos              (0UL)                     /*!< SLEN6 (Bit 0)                                         */
27412 #define ADC_SL6CFG_SLEN6_Msk              (0x1UL)                   /*!< SLEN6 (Bitfield-Mask: 0x01)                           */
27413 /* ========================================================  SL7CFG  ========================================================= */
27414 #define ADC_SL7CFG_ADSEL7_Pos             (24UL)                    /*!< ADSEL7 (Bit 24)                                       */
27415 #define ADC_SL7CFG_ADSEL7_Msk             (0x7000000UL)             /*!< ADSEL7 (Bitfield-Mask: 0x07)                          */
27416 #define ADC_SL7CFG_TRKCYC7_Pos            (18UL)                    /*!< TRKCYC7 (Bit 18)                                      */
27417 #define ADC_SL7CFG_TRKCYC7_Msk            (0xfc0000UL)              /*!< TRKCYC7 (Bitfield-Mask: 0x3f)                         */
27418 #define ADC_SL7CFG_PRMODE7_Pos            (16UL)                    /*!< PRMODE7 (Bit 16)                                      */
27419 #define ADC_SL7CFG_PRMODE7_Msk            (0x30000UL)               /*!< PRMODE7 (Bitfield-Mask: 0x03)                         */
27420 #define ADC_SL7CFG_CHSEL7_Pos             (8UL)                     /*!< CHSEL7 (Bit 8)                                        */
27421 #define ADC_SL7CFG_CHSEL7_Msk             (0xf00UL)                 /*!< CHSEL7 (Bitfield-Mask: 0x0f)                          */
27422 #define ADC_SL7CFG_WCEN7_Pos              (1UL)                     /*!< WCEN7 (Bit 1)                                         */
27423 #define ADC_SL7CFG_WCEN7_Msk              (0x2UL)                   /*!< WCEN7 (Bitfield-Mask: 0x01)                           */
27424 #define ADC_SL7CFG_SLEN7_Pos              (0UL)                     /*!< SLEN7 (Bit 0)                                         */
27425 #define ADC_SL7CFG_SLEN7_Msk              (0x1UL)                   /*!< SLEN7 (Bitfield-Mask: 0x01)                           */
27426 /* =========================================================  WULIM  ========================================================= */
27427 #define ADC_WULIM_ULIM_Pos                (0UL)                     /*!< ULIM (Bit 0)                                          */
27428 #define ADC_WULIM_ULIM_Msk                (0xfffffUL)               /*!< ULIM (Bitfield-Mask: 0xfffff)                         */
27429 /* =========================================================  WLLIM  ========================================================= */
27430 #define ADC_WLLIM_LLIM_Pos                (0UL)                     /*!< LLIM (Bit 0)                                          */
27431 #define ADC_WLLIM_LLIM_Msk                (0xfffffUL)               /*!< LLIM (Bitfield-Mask: 0xfffff)                         */
27432 /* ========================================================  SCWLIM  ========================================================= */
27433 #define ADC_SCWLIM_SCWLIMEN_Pos           (0UL)                     /*!< SCWLIMEN (Bit 0)                                      */
27434 #define ADC_SCWLIM_SCWLIMEN_Msk           (0x1UL)                   /*!< SCWLIMEN (Bitfield-Mask: 0x01)                        */
27435 /* =========================================================  FIFO  ========================================================== */
27436 #define ADC_FIFO_RSVD_Pos                 (31UL)                    /*!< RSVD (Bit 31)                                         */
27437 #define ADC_FIFO_RSVD_Msk                 (0x80000000UL)            /*!< RSVD (Bitfield-Mask: 0x01)                            */
27438 #define ADC_FIFO_SLOTNUM_Pos              (28UL)                    /*!< SLOTNUM (Bit 28)                                      */
27439 #define ADC_FIFO_SLOTNUM_Msk              (0x70000000UL)            /*!< SLOTNUM (Bitfield-Mask: 0x07)                         */
27440 #define ADC_FIFO_COUNT_Pos                (20UL)                    /*!< COUNT (Bit 20)                                        */
27441 #define ADC_FIFO_COUNT_Msk                (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
27442 #define ADC_FIFO_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
27443 #define ADC_FIFO_DATA_Msk                 (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
27444 /* ========================================================  FIFOPR  ========================================================= */
27445 #define ADC_FIFOPR_RSVDPR_Pos             (31UL)                    /*!< RSVDPR (Bit 31)                                       */
27446 #define ADC_FIFOPR_RSVDPR_Msk             (0x80000000UL)            /*!< RSVDPR (Bitfield-Mask: 0x01)                          */
27447 #define ADC_FIFOPR_SLOTNUMPR_Pos          (28UL)                    /*!< SLOTNUMPR (Bit 28)                                    */
27448 #define ADC_FIFOPR_SLOTNUMPR_Msk          (0x70000000UL)            /*!< SLOTNUMPR (Bitfield-Mask: 0x07)                       */
27449 #define ADC_FIFOPR_COUNT_Pos              (20UL)                    /*!< COUNT (Bit 20)                                        */
27450 #define ADC_FIFOPR_COUNT_Msk              (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
27451 #define ADC_FIFOPR_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
27452 #define ADC_FIFOPR_DATA_Msk               (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
27453 /* =====================================================  INTTRIGTIMER  ====================================================== */
27454 #define ADC_INTTRIGTIMER_TIMEREN_Pos      (31UL)                    /*!< TIMEREN (Bit 31)                                      */
27455 #define ADC_INTTRIGTIMER_TIMEREN_Msk      (0x80000000UL)            /*!< TIMEREN (Bitfield-Mask: 0x01)                         */
27456 #define ADC_INTTRIGTIMER_CLKDIV_Pos       (16UL)                    /*!< CLKDIV (Bit 16)                                       */
27457 #define ADC_INTTRIGTIMER_CLKDIV_Msk       (0x70000UL)               /*!< CLKDIV (Bitfield-Mask: 0x07)                          */
27458 #define ADC_INTTRIGTIMER_TIMERMAX_Pos     (0UL)                     /*!< TIMERMAX (Bit 0)                                      */
27459 #define ADC_INTTRIGTIMER_TIMERMAX_Msk     (0x3ffUL)                 /*!< TIMERMAX (Bitfield-Mask: 0x3ff)                       */
27460 /* =========================================================  ZXCFG  ========================================================= */
27461 #define ADC_ZXCFG_ZXCHANSEL_Pos           (4UL)                     /*!< ZXCHANSEL (Bit 4)                                     */
27462 #define ADC_ZXCFG_ZXCHANSEL_Msk           (0x10UL)                  /*!< ZXCHANSEL (Bitfield-Mask: 0x01)                       */
27463 #define ADC_ZXCFG_ZXEN_Pos                (0UL)                     /*!< ZXEN (Bit 0)                                          */
27464 #define ADC_ZXCFG_ZXEN_Msk                (0x1UL)                   /*!< ZXEN (Bitfield-Mask: 0x01)                            */
27465 /* =========================================================  ZXLIM  ========================================================= */
27466 #define ADC_ZXLIM_UZXC_Pos                (16UL)                    /*!< UZXC (Bit 16)                                         */
27467 #define ADC_ZXLIM_UZXC_Msk                (0xfff0000UL)             /*!< UZXC (Bitfield-Mask: 0xfff)                           */
27468 #define ADC_ZXLIM_LZXC_Pos                (0UL)                     /*!< LZXC (Bit 0)                                          */
27469 #define ADC_ZXLIM_LZXC_Msk                (0xfffUL)                 /*!< LZXC (Bitfield-Mask: 0xfff)                           */
27470 /* ========================================================  GAINCFG  ======================================================== */
27471 #define ADC_GAINCFG_UPDATEMODE_Pos        (4UL)                     /*!< UPDATEMODE (Bit 4)                                    */
27472 #define ADC_GAINCFG_UPDATEMODE_Msk        (0x10UL)                  /*!< UPDATEMODE (Bitfield-Mask: 0x01)                      */
27473 #define ADC_GAINCFG_PGACTRLEN_Pos         (0UL)                     /*!< PGACTRLEN (Bit 0)                                     */
27474 #define ADC_GAINCFG_PGACTRLEN_Msk         (0x1UL)                   /*!< PGACTRLEN (Bitfield-Mask: 0x01)                       */
27475 /* =========================================================  GAIN  ========================================================== */
27476 #define ADC_GAIN_HGBDELTA_Pos             (24UL)                    /*!< HGBDELTA (Bit 24)                                     */
27477 #define ADC_GAIN_HGBDELTA_Msk             (0x7f000000UL)            /*!< HGBDELTA (Bitfield-Mask: 0x7f)                        */
27478 #define ADC_GAIN_LGB_Pos                  (16UL)                    /*!< LGB (Bit 16)                                          */
27479 #define ADC_GAIN_LGB_Msk                  (0x7f0000UL)              /*!< LGB (Bitfield-Mask: 0x7f)                             */
27480 #define ADC_GAIN_HGADELTA_Pos             (8UL)                     /*!< HGADELTA (Bit 8)                                      */
27481 #define ADC_GAIN_HGADELTA_Msk             (0x7f00UL)                /*!< HGADELTA (Bitfield-Mask: 0x7f)                        */
27482 #define ADC_GAIN_LGA_Pos                  (0UL)                     /*!< LGA (Bit 0)                                           */
27483 #define ADC_GAIN_LGA_Msk                  (0x7fUL)                  /*!< LGA (Bitfield-Mask: 0x7f)                             */
27484 /* ========================================================  SATCFG  ========================================================= */
27485 #define ADC_SATCFG_SATCHANSEL_Pos         (4UL)                     /*!< SATCHANSEL (Bit 4)                                    */
27486 #define ADC_SATCFG_SATCHANSEL_Msk         (0x10UL)                  /*!< SATCHANSEL (Bitfield-Mask: 0x01)                      */
27487 #define ADC_SATCFG_SATEN_Pos              (0UL)                     /*!< SATEN (Bit 0)                                         */
27488 #define ADC_SATCFG_SATEN_Msk              (0x1UL)                   /*!< SATEN (Bitfield-Mask: 0x01)                           */
27489 /* ========================================================  SATLIM  ========================================================= */
27490 #define ADC_SATLIM_USATC_Pos              (16UL)                    /*!< USATC (Bit 16)                                        */
27491 #define ADC_SATLIM_USATC_Msk              (0xfff0000UL)             /*!< USATC (Bitfield-Mask: 0xfff)                          */
27492 #define ADC_SATLIM_LSATC_Pos              (0UL)                     /*!< LSATC (Bit 0)                                         */
27493 #define ADC_SATLIM_LSATC_Msk              (0xfffUL)                 /*!< LSATC (Bitfield-Mask: 0xfff)                          */
27494 /* ========================================================  SATMAX  ========================================================= */
27495 #define ADC_SATMAX_SATCBMAX_Pos           (16UL)                    /*!< SATCBMAX (Bit 16)                                     */
27496 #define ADC_SATMAX_SATCBMAX_Msk           (0xfff0000UL)             /*!< SATCBMAX (Bitfield-Mask: 0xfff)                       */
27497 #define ADC_SATMAX_SATCAMAX_Pos           (0UL)                     /*!< SATCAMAX (Bit 0)                                      */
27498 #define ADC_SATMAX_SATCAMAX_Msk           (0xfffUL)                 /*!< SATCAMAX (Bitfield-Mask: 0xfff)                       */
27499 /* ========================================================  SATCLR  ========================================================= */
27500 #define ADC_SATCLR_SATCBCLR_Pos           (1UL)                     /*!< SATCBCLR (Bit 1)                                      */
27501 #define ADC_SATCLR_SATCBCLR_Msk           (0x2UL)                   /*!< SATCBCLR (Bitfield-Mask: 0x01)                        */
27502 #define ADC_SATCLR_SATCACLR_Pos           (0UL)                     /*!< SATCACLR (Bit 0)                                      */
27503 #define ADC_SATCLR_SATCACLR_Msk           (0x1UL)                   /*!< SATCACLR (Bitfield-Mask: 0x01)                        */
27504 /* =========================================================  INTEN  ========================================================= */
27505 #define ADC_INTEN_SATCB_Pos               (11UL)                    /*!< SATCB (Bit 11)                                        */
27506 #define ADC_INTEN_SATCB_Msk               (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27507 #define ADC_INTEN_SATCA_Pos               (10UL)                    /*!< SATCA (Bit 10)                                        */
27508 #define ADC_INTEN_SATCA_Msk               (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27509 #define ADC_INTEN_ZXCB_Pos                (9UL)                     /*!< ZXCB (Bit 9)                                          */
27510 #define ADC_INTEN_ZXCB_Msk                (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27511 #define ADC_INTEN_ZXCA_Pos                (8UL)                     /*!< ZXCA (Bit 8)                                          */
27512 #define ADC_INTEN_ZXCA_Msk                (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27513 #define ADC_INTEN_DERR_Pos                (7UL)                     /*!< DERR (Bit 7)                                          */
27514 #define ADC_INTEN_DERR_Msk                (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27515 #define ADC_INTEN_DCMP_Pos                (6UL)                     /*!< DCMP (Bit 6)                                          */
27516 #define ADC_INTEN_DCMP_Msk                (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27517 #define ADC_INTEN_WCINC_Pos               (5UL)                     /*!< WCINC (Bit 5)                                         */
27518 #define ADC_INTEN_WCINC_Msk               (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27519 #define ADC_INTEN_WCEXC_Pos               (4UL)                     /*!< WCEXC (Bit 4)                                         */
27520 #define ADC_INTEN_WCEXC_Msk               (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27521 #define ADC_INTEN_FIFOOVR2_Pos            (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27522 #define ADC_INTEN_FIFOOVR2_Msk            (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27523 #define ADC_INTEN_FIFOOVR1_Pos            (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27524 #define ADC_INTEN_FIFOOVR1_Msk            (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27525 #define ADC_INTEN_SCNCMP_Pos              (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27526 #define ADC_INTEN_SCNCMP_Msk              (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27527 #define ADC_INTEN_CNVCMP_Pos              (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27528 #define ADC_INTEN_CNVCMP_Msk              (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27529 /* ========================================================  INTSTAT  ======================================================== */
27530 #define ADC_INTSTAT_SATCB_Pos             (11UL)                    /*!< SATCB (Bit 11)                                        */
27531 #define ADC_INTSTAT_SATCB_Msk             (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27532 #define ADC_INTSTAT_SATCA_Pos             (10UL)                    /*!< SATCA (Bit 10)                                        */
27533 #define ADC_INTSTAT_SATCA_Msk             (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27534 #define ADC_INTSTAT_ZXCB_Pos              (9UL)                     /*!< ZXCB (Bit 9)                                          */
27535 #define ADC_INTSTAT_ZXCB_Msk              (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27536 #define ADC_INTSTAT_ZXCA_Pos              (8UL)                     /*!< ZXCA (Bit 8)                                          */
27537 #define ADC_INTSTAT_ZXCA_Msk              (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27538 #define ADC_INTSTAT_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
27539 #define ADC_INTSTAT_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27540 #define ADC_INTSTAT_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
27541 #define ADC_INTSTAT_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27542 #define ADC_INTSTAT_WCINC_Pos             (5UL)                     /*!< WCINC (Bit 5)                                         */
27543 #define ADC_INTSTAT_WCINC_Msk             (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27544 #define ADC_INTSTAT_WCEXC_Pos             (4UL)                     /*!< WCEXC (Bit 4)                                         */
27545 #define ADC_INTSTAT_WCEXC_Msk             (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27546 #define ADC_INTSTAT_FIFOOVR2_Pos          (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27547 #define ADC_INTSTAT_FIFOOVR2_Msk          (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27548 #define ADC_INTSTAT_FIFOOVR1_Pos          (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27549 #define ADC_INTSTAT_FIFOOVR1_Msk          (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27550 #define ADC_INTSTAT_SCNCMP_Pos            (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27551 #define ADC_INTSTAT_SCNCMP_Msk            (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27552 #define ADC_INTSTAT_CNVCMP_Pos            (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27553 #define ADC_INTSTAT_CNVCMP_Msk            (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27554 /* ========================================================  INTCLR  ========================================================= */
27555 #define ADC_INTCLR_SATCB_Pos              (11UL)                    /*!< SATCB (Bit 11)                                        */
27556 #define ADC_INTCLR_SATCB_Msk              (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27557 #define ADC_INTCLR_SATCA_Pos              (10UL)                    /*!< SATCA (Bit 10)                                        */
27558 #define ADC_INTCLR_SATCA_Msk              (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27559 #define ADC_INTCLR_ZXCB_Pos               (9UL)                     /*!< ZXCB (Bit 9)                                          */
27560 #define ADC_INTCLR_ZXCB_Msk               (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27561 #define ADC_INTCLR_ZXCA_Pos               (8UL)                     /*!< ZXCA (Bit 8)                                          */
27562 #define ADC_INTCLR_ZXCA_Msk               (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27563 #define ADC_INTCLR_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
27564 #define ADC_INTCLR_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27565 #define ADC_INTCLR_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
27566 #define ADC_INTCLR_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27567 #define ADC_INTCLR_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
27568 #define ADC_INTCLR_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27569 #define ADC_INTCLR_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
27570 #define ADC_INTCLR_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27571 #define ADC_INTCLR_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27572 #define ADC_INTCLR_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27573 #define ADC_INTCLR_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27574 #define ADC_INTCLR_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27575 #define ADC_INTCLR_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27576 #define ADC_INTCLR_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27577 #define ADC_INTCLR_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27578 #define ADC_INTCLR_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27579 /* ========================================================  INTSET  ========================================================= */
27580 #define ADC_INTSET_SATCB_Pos              (11UL)                    /*!< SATCB (Bit 11)                                        */
27581 #define ADC_INTSET_SATCB_Msk              (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27582 #define ADC_INTSET_SATCA_Pos              (10UL)                    /*!< SATCA (Bit 10)                                        */
27583 #define ADC_INTSET_SATCA_Msk              (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27584 #define ADC_INTSET_ZXCB_Pos               (9UL)                     /*!< ZXCB (Bit 9)                                          */
27585 #define ADC_INTSET_ZXCB_Msk               (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27586 #define ADC_INTSET_ZXCA_Pos               (8UL)                     /*!< ZXCA (Bit 8)                                          */
27587 #define ADC_INTSET_ZXCA_Msk               (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27588 #define ADC_INTSET_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
27589 #define ADC_INTSET_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27590 #define ADC_INTSET_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
27591 #define ADC_INTSET_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27592 #define ADC_INTSET_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
27593 #define ADC_INTSET_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27594 #define ADC_INTSET_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
27595 #define ADC_INTSET_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27596 #define ADC_INTSET_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27597 #define ADC_INTSET_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27598 #define ADC_INTSET_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27599 #define ADC_INTSET_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27600 #define ADC_INTSET_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27601 #define ADC_INTSET_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27602 #define ADC_INTSET_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27603 #define ADC_INTSET_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27604 /* =======================================================  DMATRIGEN  ======================================================= */
27605 #define ADC_DMATRIGEN_DFIFOFULL_Pos       (1UL)                     /*!< DFIFOFULL (Bit 1)                                     */
27606 #define ADC_DMATRIGEN_DFIFOFULL_Msk       (0x2UL)                   /*!< DFIFOFULL (Bitfield-Mask: 0x01)                       */
27607 #define ADC_DMATRIGEN_DFIFO75_Pos         (0UL)                     /*!< DFIFO75 (Bit 0)                                       */
27608 #define ADC_DMATRIGEN_DFIFO75_Msk         (0x1UL)                   /*!< DFIFO75 (Bitfield-Mask: 0x01)                         */
27609 /* ======================================================  DMATRIGSTAT  ====================================================== */
27610 #define ADC_DMATRIGSTAT_DFULLSTAT_Pos     (1UL)                     /*!< DFULLSTAT (Bit 1)                                     */
27611 #define ADC_DMATRIGSTAT_DFULLSTAT_Msk     (0x2UL)                   /*!< DFULLSTAT (Bitfield-Mask: 0x01)                       */
27612 #define ADC_DMATRIGSTAT_D75STAT_Pos       (0UL)                     /*!< D75STAT (Bit 0)                                       */
27613 #define ADC_DMATRIGSTAT_D75STAT_Msk       (0x1UL)                   /*!< D75STAT (Bitfield-Mask: 0x01)                         */
27614 /* ========================================================  DMACFG  ========================================================= */
27615 #define ADC_DMACFG_DPWROFF_Pos            (18UL)                    /*!< DPWROFF (Bit 18)                                      */
27616 #define ADC_DMACFG_DPWROFF_Msk            (0x40000UL)               /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
27617 #define ADC_DMACFG_DMAMSK_Pos             (17UL)                    /*!< DMAMSK (Bit 17)                                       */
27618 #define ADC_DMACFG_DMAMSK_Msk             (0x20000UL)               /*!< DMAMSK (Bitfield-Mask: 0x01)                          */
27619 #define ADC_DMACFG_DMADYNPRI_Pos          (9UL)                     /*!< DMADYNPRI (Bit 9)                                     */
27620 #define ADC_DMACFG_DMADYNPRI_Msk          (0x200UL)                 /*!< DMADYNPRI (Bitfield-Mask: 0x01)                       */
27621 #define ADC_DMACFG_DMAPRI_Pos             (8UL)                     /*!< DMAPRI (Bit 8)                                        */
27622 #define ADC_DMACFG_DMAPRI_Msk             (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
27623 #define ADC_DMACFG_DMADIR_Pos             (2UL)                     /*!< DMADIR (Bit 2)                                        */
27624 #define ADC_DMACFG_DMADIR_Msk             (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
27625 #define ADC_DMACFG_DMAEN_Pos              (0UL)                     /*!< DMAEN (Bit 0)                                         */
27626 #define ADC_DMACFG_DMAEN_Msk              (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
27627 /* ======================================================  DMATOTCOUNT  ====================================================== */
27628 #define ADC_DMATOTCOUNT_TOTCOUNT_Pos      (2UL)                     /*!< TOTCOUNT (Bit 2)                                      */
27629 #define ADC_DMATOTCOUNT_TOTCOUNT_Msk      (0x3fffcUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
27630 /* ======================================================  DMATARGADDR  ====================================================== */
27631 #define ADC_DMATARGADDR_UTARGADDR_Pos     (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
27632 #define ADC_DMATARGADDR_UTARGADDR_Msk     (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
27633 #define ADC_DMATARGADDR_LTARGADDR_Pos     (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
27634 #define ADC_DMATARGADDR_LTARGADDR_Msk     (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
27635 /* ========================================================  DMASTAT  ======================================================== */
27636 #define ADC_DMASTAT_DMAERR_Pos            (2UL)                     /*!< DMAERR (Bit 2)                                        */
27637 #define ADC_DMASTAT_DMAERR_Msk            (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
27638 #define ADC_DMASTAT_DMACPL_Pos            (1UL)                     /*!< DMACPL (Bit 1)                                        */
27639 #define ADC_DMASTAT_DMACPL_Msk            (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
27640 #define ADC_DMASTAT_DMATIP_Pos            (0UL)                     /*!< DMATIP (Bit 0)                                        */
27641 #define ADC_DMASTAT_DMATIP_Msk            (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
27642 
27643 
27644 /* =========================================================================================================================== */
27645 /* ================                                          APBDMA                                           ================ */
27646 /* =========================================================================================================================== */
27647 
27648 /* ========================================================  BBVALUE  ======================================================== */
27649 #define APBDMA_BBVALUE_PIN_Pos            (16UL)                    /*!< PIN (Bit 16)                                          */
27650 #define APBDMA_BBVALUE_PIN_Msk            (0xff0000UL)              /*!< PIN (Bitfield-Mask: 0xff)                             */
27651 #define APBDMA_BBVALUE_DATAOUT_Pos        (0UL)                     /*!< DATAOUT (Bit 0)                                       */
27652 #define APBDMA_BBVALUE_DATAOUT_Msk        (0xffUL)                  /*!< DATAOUT (Bitfield-Mask: 0xff)                         */
27653 /* ======================================================  BBSETCLEAR  ======================================================= */
27654 #define APBDMA_BBSETCLEAR_CLEAR_Pos       (16UL)                    /*!< CLEAR (Bit 16)                                        */
27655 #define APBDMA_BBSETCLEAR_CLEAR_Msk       (0xff0000UL)              /*!< CLEAR (Bitfield-Mask: 0xff)                           */
27656 #define APBDMA_BBSETCLEAR_SET_Pos         (0UL)                     /*!< SET (Bit 0)                                           */
27657 #define APBDMA_BBSETCLEAR_SET_Msk         (0xffUL)                  /*!< SET (Bitfield-Mask: 0xff)                             */
27658 /* ========================================================  BBINPUT  ======================================================== */
27659 #define APBDMA_BBINPUT_DATAIN_Pos         (0UL)                     /*!< DATAIN (Bit 0)                                        */
27660 #define APBDMA_BBINPUT_DATAIN_Msk         (0xffUL)                  /*!< DATAIN (Bitfield-Mask: 0xff)                          */
27661 /* =======================================================  DEBUGDATA  ======================================================= */
27662 #define APBDMA_DEBUGDATA_DEBUGDATA_Pos    (0UL)                     /*!< DEBUGDATA (Bit 0)                                     */
27663 #define APBDMA_DEBUGDATA_DEBUGDATA_Msk    (0xffffffffUL)            /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff)                 */
27664 /* =========================================================  DEBUG  ========================================================= */
27665 #define APBDMA_DEBUG_DEBUGEN_Pos          (0UL)                     /*!< DEBUGEN (Bit 0)                                       */
27666 #define APBDMA_DEBUG_DEBUGEN_Msk          (0xfUL)                   /*!< DEBUGEN (Bitfield-Mask: 0x0f)                         */
27667 
27668 
27669 /* =========================================================================================================================== */
27670 /* ================                                          AUDADC                                           ================ */
27671 /* =========================================================================================================================== */
27672 
27673 /* ==========================================================  CFG  ========================================================== */
27674 #define AUDADC_CFG_CLKSEL_Pos             (24UL)                    /*!< CLKSEL (Bit 24)                                       */
27675 #define AUDADC_CFG_CLKSEL_Msk             (0x3000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
27676 #define AUDADC_CFG_RPTTRIGSEL_Pos         (20UL)                    /*!< RPTTRIGSEL (Bit 20)                                   */
27677 #define AUDADC_CFG_RPTTRIGSEL_Msk         (0x100000UL)              /*!< RPTTRIGSEL (Bitfield-Mask: 0x01)                      */
27678 #define AUDADC_CFG_TRIGPOL_Pos            (19UL)                    /*!< TRIGPOL (Bit 19)                                      */
27679 #define AUDADC_CFG_TRIGPOL_Msk            (0x80000UL)               /*!< TRIGPOL (Bitfield-Mask: 0x01)                         */
27680 #define AUDADC_CFG_TRIGSEL_Pos            (16UL)                    /*!< TRIGSEL (Bit 16)                                      */
27681 #define AUDADC_CFG_TRIGSEL_Msk            (0x70000UL)               /*!< TRIGSEL (Bitfield-Mask: 0x07)                         */
27682 #define AUDADC_CFG_SAMPMODE_Pos           (13UL)                    /*!< SAMPMODE (Bit 13)                                     */
27683 #define AUDADC_CFG_SAMPMODE_Msk           (0x2000UL)                /*!< SAMPMODE (Bitfield-Mask: 0x01)                        */
27684 #define AUDADC_CFG_DFIFORDEN_Pos          (12UL)                    /*!< DFIFORDEN (Bit 12)                                    */
27685 #define AUDADC_CFG_DFIFORDEN_Msk          (0x1000UL)                /*!< DFIFORDEN (Bitfield-Mask: 0x01)                       */
27686 #define AUDADC_CFG_CKMODE_Pos             (4UL)                     /*!< CKMODE (Bit 4)                                        */
27687 #define AUDADC_CFG_CKMODE_Msk             (0x10UL)                  /*!< CKMODE (Bitfield-Mask: 0x01)                          */
27688 #define AUDADC_CFG_LPMODE_Pos             (3UL)                     /*!< LPMODE (Bit 3)                                        */
27689 #define AUDADC_CFG_LPMODE_Msk             (0x8UL)                   /*!< LPMODE (Bitfield-Mask: 0x01)                          */
27690 #define AUDADC_CFG_RPTEN_Pos              (2UL)                     /*!< RPTEN (Bit 2)                                         */
27691 #define AUDADC_CFG_RPTEN_Msk              (0x4UL)                   /*!< RPTEN (Bitfield-Mask: 0x01)                           */
27692 #define AUDADC_CFG_ADCEN_Pos              (0UL)                     /*!< ADCEN (Bit 0)                                         */
27693 #define AUDADC_CFG_ADCEN_Msk              (0x1UL)                   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
27694 /* =========================================================  STAT  ========================================================== */
27695 #define AUDADC_STAT_PWDSTAT_Pos           (0UL)                     /*!< PWDSTAT (Bit 0)                                       */
27696 #define AUDADC_STAT_PWDSTAT_Msk           (0x1UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
27697 /* ==========================================================  SWT  ========================================================== */
27698 #define AUDADC_SWT_SWT_Pos                (0UL)                     /*!< SWT (Bit 0)                                           */
27699 #define AUDADC_SWT_SWT_Msk                (0xffUL)                  /*!< SWT (Bitfield-Mask: 0xff)                             */
27700 /* ========================================================  SL0CFG  ========================================================= */
27701 #define AUDADC_SL0CFG_ADSEL0_Pos          (24UL)                    /*!< ADSEL0 (Bit 24)                                       */
27702 #define AUDADC_SL0CFG_ADSEL0_Msk          (0x7000000UL)             /*!< ADSEL0 (Bitfield-Mask: 0x07)                          */
27703 #define AUDADC_SL0CFG_TRKCYC0_Pos         (18UL)                    /*!< TRKCYC0 (Bit 18)                                      */
27704 #define AUDADC_SL0CFG_TRKCYC0_Msk         (0xfc0000UL)              /*!< TRKCYC0 (Bitfield-Mask: 0x3f)                         */
27705 #define AUDADC_SL0CFG_PRMODE0_Pos         (16UL)                    /*!< PRMODE0 (Bit 16)                                      */
27706 #define AUDADC_SL0CFG_PRMODE0_Msk         (0x30000UL)               /*!< PRMODE0 (Bitfield-Mask: 0x03)                         */
27707 #define AUDADC_SL0CFG_CHSEL0_Pos          (8UL)                     /*!< CHSEL0 (Bit 8)                                        */
27708 #define AUDADC_SL0CFG_CHSEL0_Msk          (0xf00UL)                 /*!< CHSEL0 (Bitfield-Mask: 0x0f)                          */
27709 #define AUDADC_SL0CFG_WCEN0_Pos           (1UL)                     /*!< WCEN0 (Bit 1)                                         */
27710 #define AUDADC_SL0CFG_WCEN0_Msk           (0x2UL)                   /*!< WCEN0 (Bitfield-Mask: 0x01)                           */
27711 #define AUDADC_SL0CFG_SLEN0_Pos           (0UL)                     /*!< SLEN0 (Bit 0)                                         */
27712 #define AUDADC_SL0CFG_SLEN0_Msk           (0x1UL)                   /*!< SLEN0 (Bitfield-Mask: 0x01)                           */
27713 /* ========================================================  SL1CFG  ========================================================= */
27714 #define AUDADC_SL1CFG_ADSEL1_Pos          (24UL)                    /*!< ADSEL1 (Bit 24)                                       */
27715 #define AUDADC_SL1CFG_ADSEL1_Msk          (0x7000000UL)             /*!< ADSEL1 (Bitfield-Mask: 0x07)                          */
27716 #define AUDADC_SL1CFG_TRKCYC1_Pos         (18UL)                    /*!< TRKCYC1 (Bit 18)                                      */
27717 #define AUDADC_SL1CFG_TRKCYC1_Msk         (0xfc0000UL)              /*!< TRKCYC1 (Bitfield-Mask: 0x3f)                         */
27718 #define AUDADC_SL1CFG_PRMODE1_Pos         (16UL)                    /*!< PRMODE1 (Bit 16)                                      */
27719 #define AUDADC_SL1CFG_PRMODE1_Msk         (0x30000UL)               /*!< PRMODE1 (Bitfield-Mask: 0x03)                         */
27720 #define AUDADC_SL1CFG_CHSEL1_Pos          (8UL)                     /*!< CHSEL1 (Bit 8)                                        */
27721 #define AUDADC_SL1CFG_CHSEL1_Msk          (0xf00UL)                 /*!< CHSEL1 (Bitfield-Mask: 0x0f)                          */
27722 #define AUDADC_SL1CFG_WCEN1_Pos           (1UL)                     /*!< WCEN1 (Bit 1)                                         */
27723 #define AUDADC_SL1CFG_WCEN1_Msk           (0x2UL)                   /*!< WCEN1 (Bitfield-Mask: 0x01)                           */
27724 #define AUDADC_SL1CFG_SLEN1_Pos           (0UL)                     /*!< SLEN1 (Bit 0)                                         */
27725 #define AUDADC_SL1CFG_SLEN1_Msk           (0x1UL)                   /*!< SLEN1 (Bitfield-Mask: 0x01)                           */
27726 /* ========================================================  SL2CFG  ========================================================= */
27727 #define AUDADC_SL2CFG_ADSEL2_Pos          (24UL)                    /*!< ADSEL2 (Bit 24)                                       */
27728 #define AUDADC_SL2CFG_ADSEL2_Msk          (0x7000000UL)             /*!< ADSEL2 (Bitfield-Mask: 0x07)                          */
27729 #define AUDADC_SL2CFG_TRKCYC2_Pos         (18UL)                    /*!< TRKCYC2 (Bit 18)                                      */
27730 #define AUDADC_SL2CFG_TRKCYC2_Msk         (0xfc0000UL)              /*!< TRKCYC2 (Bitfield-Mask: 0x3f)                         */
27731 #define AUDADC_SL2CFG_PRMODE2_Pos         (16UL)                    /*!< PRMODE2 (Bit 16)                                      */
27732 #define AUDADC_SL2CFG_PRMODE2_Msk         (0x30000UL)               /*!< PRMODE2 (Bitfield-Mask: 0x03)                         */
27733 #define AUDADC_SL2CFG_CHSEL2_Pos          (8UL)                     /*!< CHSEL2 (Bit 8)                                        */
27734 #define AUDADC_SL2CFG_CHSEL2_Msk          (0xf00UL)                 /*!< CHSEL2 (Bitfield-Mask: 0x0f)                          */
27735 #define AUDADC_SL2CFG_WCEN2_Pos           (1UL)                     /*!< WCEN2 (Bit 1)                                         */
27736 #define AUDADC_SL2CFG_WCEN2_Msk           (0x2UL)                   /*!< WCEN2 (Bitfield-Mask: 0x01)                           */
27737 #define AUDADC_SL2CFG_SLEN2_Pos           (0UL)                     /*!< SLEN2 (Bit 0)                                         */
27738 #define AUDADC_SL2CFG_SLEN2_Msk           (0x1UL)                   /*!< SLEN2 (Bitfield-Mask: 0x01)                           */
27739 /* ========================================================  SL3CFG  ========================================================= */
27740 #define AUDADC_SL3CFG_ADSEL3_Pos          (24UL)                    /*!< ADSEL3 (Bit 24)                                       */
27741 #define AUDADC_SL3CFG_ADSEL3_Msk          (0x7000000UL)             /*!< ADSEL3 (Bitfield-Mask: 0x07)                          */
27742 #define AUDADC_SL3CFG_TRKCYC3_Pos         (18UL)                    /*!< TRKCYC3 (Bit 18)                                      */
27743 #define AUDADC_SL3CFG_TRKCYC3_Msk         (0xfc0000UL)              /*!< TRKCYC3 (Bitfield-Mask: 0x3f)                         */
27744 #define AUDADC_SL3CFG_PRMODE3_Pos         (16UL)                    /*!< PRMODE3 (Bit 16)                                      */
27745 #define AUDADC_SL3CFG_PRMODE3_Msk         (0x30000UL)               /*!< PRMODE3 (Bitfield-Mask: 0x03)                         */
27746 #define AUDADC_SL3CFG_CHSEL3_Pos          (8UL)                     /*!< CHSEL3 (Bit 8)                                        */
27747 #define AUDADC_SL3CFG_CHSEL3_Msk          (0xf00UL)                 /*!< CHSEL3 (Bitfield-Mask: 0x0f)                          */
27748 #define AUDADC_SL3CFG_WCEN3_Pos           (1UL)                     /*!< WCEN3 (Bit 1)                                         */
27749 #define AUDADC_SL3CFG_WCEN3_Msk           (0x2UL)                   /*!< WCEN3 (Bitfield-Mask: 0x01)                           */
27750 #define AUDADC_SL3CFG_SLEN3_Pos           (0UL)                     /*!< SLEN3 (Bit 0)                                         */
27751 #define AUDADC_SL3CFG_SLEN3_Msk           (0x1UL)                   /*!< SLEN3 (Bitfield-Mask: 0x01)                           */
27752 /* ========================================================  SL4CFG  ========================================================= */
27753 #define AUDADC_SL4CFG_ADSEL4_Pos          (24UL)                    /*!< ADSEL4 (Bit 24)                                       */
27754 #define AUDADC_SL4CFG_ADSEL4_Msk          (0x7000000UL)             /*!< ADSEL4 (Bitfield-Mask: 0x07)                          */
27755 #define AUDADC_SL4CFG_TRKCYC4_Pos         (18UL)                    /*!< TRKCYC4 (Bit 18)                                      */
27756 #define AUDADC_SL4CFG_TRKCYC4_Msk         (0xfc0000UL)              /*!< TRKCYC4 (Bitfield-Mask: 0x3f)                         */
27757 #define AUDADC_SL4CFG_PRMODE4_Pos         (16UL)                    /*!< PRMODE4 (Bit 16)                                      */
27758 #define AUDADC_SL4CFG_PRMODE4_Msk         (0x30000UL)               /*!< PRMODE4 (Bitfield-Mask: 0x03)                         */
27759 #define AUDADC_SL4CFG_CHSEL4_Pos          (8UL)                     /*!< CHSEL4 (Bit 8)                                        */
27760 #define AUDADC_SL4CFG_CHSEL4_Msk          (0xf00UL)                 /*!< CHSEL4 (Bitfield-Mask: 0x0f)                          */
27761 #define AUDADC_SL4CFG_WCEN4_Pos           (1UL)                     /*!< WCEN4 (Bit 1)                                         */
27762 #define AUDADC_SL4CFG_WCEN4_Msk           (0x2UL)                   /*!< WCEN4 (Bitfield-Mask: 0x01)                           */
27763 #define AUDADC_SL4CFG_SLEN4_Pos           (0UL)                     /*!< SLEN4 (Bit 0)                                         */
27764 #define AUDADC_SL4CFG_SLEN4_Msk           (0x1UL)                   /*!< SLEN4 (Bitfield-Mask: 0x01)                           */
27765 /* ========================================================  SL5CFG  ========================================================= */
27766 #define AUDADC_SL5CFG_ADSEL5_Pos          (24UL)                    /*!< ADSEL5 (Bit 24)                                       */
27767 #define AUDADC_SL5CFG_ADSEL5_Msk          (0x7000000UL)             /*!< ADSEL5 (Bitfield-Mask: 0x07)                          */
27768 #define AUDADC_SL5CFG_TRKCYC5_Pos         (18UL)                    /*!< TRKCYC5 (Bit 18)                                      */
27769 #define AUDADC_SL5CFG_TRKCYC5_Msk         (0xfc0000UL)              /*!< TRKCYC5 (Bitfield-Mask: 0x3f)                         */
27770 #define AUDADC_SL5CFG_PRMODE5_Pos         (16UL)                    /*!< PRMODE5 (Bit 16)                                      */
27771 #define AUDADC_SL5CFG_PRMODE5_Msk         (0x30000UL)               /*!< PRMODE5 (Bitfield-Mask: 0x03)                         */
27772 #define AUDADC_SL5CFG_CHSEL5_Pos          (8UL)                     /*!< CHSEL5 (Bit 8)                                        */
27773 #define AUDADC_SL5CFG_CHSEL5_Msk          (0xf00UL)                 /*!< CHSEL5 (Bitfield-Mask: 0x0f)                          */
27774 #define AUDADC_SL5CFG_WCEN5_Pos           (1UL)                     /*!< WCEN5 (Bit 1)                                         */
27775 #define AUDADC_SL5CFG_WCEN5_Msk           (0x2UL)                   /*!< WCEN5 (Bitfield-Mask: 0x01)                           */
27776 #define AUDADC_SL5CFG_SLEN5_Pos           (0UL)                     /*!< SLEN5 (Bit 0)                                         */
27777 #define AUDADC_SL5CFG_SLEN5_Msk           (0x1UL)                   /*!< SLEN5 (Bitfield-Mask: 0x01)                           */
27778 /* ========================================================  SL6CFG  ========================================================= */
27779 #define AUDADC_SL6CFG_ADSEL6_Pos          (24UL)                    /*!< ADSEL6 (Bit 24)                                       */
27780 #define AUDADC_SL6CFG_ADSEL6_Msk          (0x7000000UL)             /*!< ADSEL6 (Bitfield-Mask: 0x07)                          */
27781 #define AUDADC_SL6CFG_TRKCYC6_Pos         (18UL)                    /*!< TRKCYC6 (Bit 18)                                      */
27782 #define AUDADC_SL6CFG_TRKCYC6_Msk         (0xfc0000UL)              /*!< TRKCYC6 (Bitfield-Mask: 0x3f)                         */
27783 #define AUDADC_SL6CFG_PRMODE6_Pos         (16UL)                    /*!< PRMODE6 (Bit 16)                                      */
27784 #define AUDADC_SL6CFG_PRMODE6_Msk         (0x30000UL)               /*!< PRMODE6 (Bitfield-Mask: 0x03)                         */
27785 #define AUDADC_SL6CFG_CHSEL6_Pos          (8UL)                     /*!< CHSEL6 (Bit 8)                                        */
27786 #define AUDADC_SL6CFG_CHSEL6_Msk          (0xf00UL)                 /*!< CHSEL6 (Bitfield-Mask: 0x0f)                          */
27787 #define AUDADC_SL6CFG_WCEN6_Pos           (1UL)                     /*!< WCEN6 (Bit 1)                                         */
27788 #define AUDADC_SL6CFG_WCEN6_Msk           (0x2UL)                   /*!< WCEN6 (Bitfield-Mask: 0x01)                           */
27789 #define AUDADC_SL6CFG_SLEN6_Pos           (0UL)                     /*!< SLEN6 (Bit 0)                                         */
27790 #define AUDADC_SL6CFG_SLEN6_Msk           (0x1UL)                   /*!< SLEN6 (Bitfield-Mask: 0x01)                           */
27791 /* ========================================================  SL7CFG  ========================================================= */
27792 #define AUDADC_SL7CFG_ADSEL7_Pos          (24UL)                    /*!< ADSEL7 (Bit 24)                                       */
27793 #define AUDADC_SL7CFG_ADSEL7_Msk          (0x7000000UL)             /*!< ADSEL7 (Bitfield-Mask: 0x07)                          */
27794 #define AUDADC_SL7CFG_TRKCYC7_Pos         (18UL)                    /*!< TRKCYC7 (Bit 18)                                      */
27795 #define AUDADC_SL7CFG_TRKCYC7_Msk         (0xfc0000UL)              /*!< TRKCYC7 (Bitfield-Mask: 0x3f)                         */
27796 #define AUDADC_SL7CFG_PRMODE7_Pos         (16UL)                    /*!< PRMODE7 (Bit 16)                                      */
27797 #define AUDADC_SL7CFG_PRMODE7_Msk         (0x30000UL)               /*!< PRMODE7 (Bitfield-Mask: 0x03)                         */
27798 #define AUDADC_SL7CFG_CHSEL7_Pos          (8UL)                     /*!< CHSEL7 (Bit 8)                                        */
27799 #define AUDADC_SL7CFG_CHSEL7_Msk          (0xf00UL)                 /*!< CHSEL7 (Bitfield-Mask: 0x0f)                          */
27800 #define AUDADC_SL7CFG_WCEN7_Pos           (1UL)                     /*!< WCEN7 (Bit 1)                                         */
27801 #define AUDADC_SL7CFG_WCEN7_Msk           (0x2UL)                   /*!< WCEN7 (Bitfield-Mask: 0x01)                           */
27802 #define AUDADC_SL7CFG_SLEN7_Pos           (0UL)                     /*!< SLEN7 (Bit 0)                                         */
27803 #define AUDADC_SL7CFG_SLEN7_Msk           (0x1UL)                   /*!< SLEN7 (Bitfield-Mask: 0x01)                           */
27804 /* =========================================================  WULIM  ========================================================= */
27805 #define AUDADC_WULIM_ULIM_Pos             (0UL)                     /*!< ULIM (Bit 0)                                          */
27806 #define AUDADC_WULIM_ULIM_Msk             (0xfffffUL)               /*!< ULIM (Bitfield-Mask: 0xfffff)                         */
27807 /* =========================================================  WLLIM  ========================================================= */
27808 #define AUDADC_WLLIM_LLIM_Pos             (0UL)                     /*!< LLIM (Bit 0)                                          */
27809 #define AUDADC_WLLIM_LLIM_Msk             (0xfffffUL)               /*!< LLIM (Bitfield-Mask: 0xfffff)                         */
27810 /* ========================================================  SCWLIM  ========================================================= */
27811 #define AUDADC_SCWLIM_SCWLIMEN_Pos        (0UL)                     /*!< SCWLIMEN (Bit 0)                                      */
27812 #define AUDADC_SCWLIM_SCWLIMEN_Msk        (0x1UL)                   /*!< SCWLIMEN (Bitfield-Mask: 0x01)                        */
27813 /* =========================================================  FIFO  ========================================================== */
27814 #define AUDADC_FIFO_HGDATA_Pos            (20UL)                    /*!< HGDATA (Bit 20)                                       */
27815 #define AUDADC_FIFO_HGDATA_Msk            (0xfff00000UL)            /*!< HGDATA (Bitfield-Mask: 0xfff)                         */
27816 #define AUDADC_FIFO_MIC_Pos               (19UL)                    /*!< MIC (Bit 19)                                          */
27817 #define AUDADC_FIFO_MIC_Msk               (0x80000UL)               /*!< MIC (Bitfield-Mask: 0x01)                             */
27818 #define AUDADC_FIFO_METAHI_Pos            (16UL)                    /*!< METAHI (Bit 16)                                       */
27819 #define AUDADC_FIFO_METAHI_Msk            (0x70000UL)               /*!< METAHI (Bitfield-Mask: 0x07)                          */
27820 #define AUDADC_FIFO_LGDATA_Pos            (4UL)                     /*!< LGDATA (Bit 4)                                        */
27821 #define AUDADC_FIFO_LGDATA_Msk            (0xfff0UL)                /*!< LGDATA (Bitfield-Mask: 0xfff)                         */
27822 #define AUDADC_FIFO_METALO_Pos            (0UL)                     /*!< METALO (Bit 0)                                        */
27823 #define AUDADC_FIFO_METALO_Msk            (0xfUL)                   /*!< METALO (Bitfield-Mask: 0x0f)                          */
27824 /* ========================================================  FIFOPR  ========================================================= */
27825 #define AUDADC_FIFOPR_HGDATAPR_Pos        (20UL)                    /*!< HGDATAPR (Bit 20)                                     */
27826 #define AUDADC_FIFOPR_HGDATAPR_Msk        (0xfff00000UL)            /*!< HGDATAPR (Bitfield-Mask: 0xfff)                       */
27827 #define AUDADC_FIFOPR_MICPR_Pos           (19UL)                    /*!< MICPR (Bit 19)                                        */
27828 #define AUDADC_FIFOPR_MICPR_Msk           (0x80000UL)               /*!< MICPR (Bitfield-Mask: 0x01)                           */
27829 #define AUDADC_FIFOPR_METAHIPR_Pos        (16UL)                    /*!< METAHIPR (Bit 16)                                     */
27830 #define AUDADC_FIFOPR_METAHIPR_Msk        (0x70000UL)               /*!< METAHIPR (Bitfield-Mask: 0x07)                        */
27831 #define AUDADC_FIFOPR_LGDATAPR_Pos        (4UL)                     /*!< LGDATAPR (Bit 4)                                      */
27832 #define AUDADC_FIFOPR_LGDATAPR_Msk        (0xfff0UL)                /*!< LGDATAPR (Bitfield-Mask: 0xfff)                       */
27833 #define AUDADC_FIFOPR_METALOPR_Pos        (0UL)                     /*!< METALOPR (Bit 0)                                      */
27834 #define AUDADC_FIFOPR_METALOPR_Msk        (0xfUL)                   /*!< METALOPR (Bitfield-Mask: 0x0f)                        */
27835 /* =====================================================  INTTRIGTIMER  ====================================================== */
27836 #define AUDADC_INTTRIGTIMER_TIMEREN_Pos   (31UL)                    /*!< TIMEREN (Bit 31)                                      */
27837 #define AUDADC_INTTRIGTIMER_TIMEREN_Msk   (0x80000000UL)            /*!< TIMEREN (Bitfield-Mask: 0x01)                         */
27838 #define AUDADC_INTTRIGTIMER_CLKDIV_Pos    (16UL)                    /*!< CLKDIV (Bit 16)                                       */
27839 #define AUDADC_INTTRIGTIMER_CLKDIV_Msk    (0x70000UL)               /*!< CLKDIV (Bitfield-Mask: 0x07)                          */
27840 #define AUDADC_INTTRIGTIMER_TIMERMAX_Pos  (0UL)                     /*!< TIMERMAX (Bit 0)                                      */
27841 #define AUDADC_INTTRIGTIMER_TIMERMAX_Msk  (0x3ffUL)                 /*!< TIMERMAX (Bitfield-Mask: 0x3ff)                       */
27842 /* =======================================================  FIFOSTAT  ======================================================== */
27843 #define AUDADC_FIFOSTAT_FIFOCNT_Pos       (0UL)                     /*!< FIFOCNT (Bit 0)                                       */
27844 #define AUDADC_FIFOSTAT_FIFOCNT_Msk       (0xffUL)                  /*!< FIFOCNT (Bitfield-Mask: 0xff)                         */
27845 /* ======================================================  DATAOFFSET  ======================================================= */
27846 #define AUDADC_DATAOFFSET_OFFSET_Pos      (0UL)                     /*!< OFFSET (Bit 0)                                        */
27847 #define AUDADC_DATAOFFSET_OFFSET_Msk      (0x1fffUL)                /*!< OFFSET (Bitfield-Mask: 0x1fff)                        */
27848 /* =========================================================  ZXCFG  ========================================================= */
27849 #define AUDADC_ZXCFG_ZXCHANSEL_Pos        (4UL)                     /*!< ZXCHANSEL (Bit 4)                                     */
27850 #define AUDADC_ZXCFG_ZXCHANSEL_Msk        (0x10UL)                  /*!< ZXCHANSEL (Bitfield-Mask: 0x01)                       */
27851 #define AUDADC_ZXCFG_ZXEN_Pos             (0UL)                     /*!< ZXEN (Bit 0)                                          */
27852 #define AUDADC_ZXCFG_ZXEN_Msk             (0x1UL)                   /*!< ZXEN (Bitfield-Mask: 0x01)                            */
27853 /* =========================================================  ZXLIM  ========================================================= */
27854 #define AUDADC_ZXLIM_UZXC_Pos             (16UL)                    /*!< UZXC (Bit 16)                                         */
27855 #define AUDADC_ZXLIM_UZXC_Msk             (0xfff0000UL)             /*!< UZXC (Bitfield-Mask: 0xfff)                           */
27856 #define AUDADC_ZXLIM_LZXC_Pos             (0UL)                     /*!< LZXC (Bit 0)                                          */
27857 #define AUDADC_ZXLIM_LZXC_Msk             (0xfffUL)                 /*!< LZXC (Bitfield-Mask: 0xfff)                           */
27858 /* ========================================================  GAINCFG  ======================================================== */
27859 #define AUDADC_GAINCFG_UPDATEMODE_Pos     (4UL)                     /*!< UPDATEMODE (Bit 4)                                    */
27860 #define AUDADC_GAINCFG_UPDATEMODE_Msk     (0x10UL)                  /*!< UPDATEMODE (Bitfield-Mask: 0x01)                      */
27861 #define AUDADC_GAINCFG_PGACTRLEN_Pos      (0UL)                     /*!< PGACTRLEN (Bit 0)                                     */
27862 #define AUDADC_GAINCFG_PGACTRLEN_Msk      (0x1UL)                   /*!< PGACTRLEN (Bitfield-Mask: 0x01)                       */
27863 /* =========================================================  GAIN  ========================================================== */
27864 #define AUDADC_GAIN_HGBDELTA_Pos          (24UL)                    /*!< HGBDELTA (Bit 24)                                     */
27865 #define AUDADC_GAIN_HGBDELTA_Msk          (0x7f000000UL)            /*!< HGBDELTA (Bitfield-Mask: 0x7f)                        */
27866 #define AUDADC_GAIN_LGB_Pos               (16UL)                    /*!< LGB (Bit 16)                                          */
27867 #define AUDADC_GAIN_LGB_Msk               (0x7f0000UL)              /*!< LGB (Bitfield-Mask: 0x7f)                             */
27868 #define AUDADC_GAIN_HGADELTA_Pos          (8UL)                     /*!< HGADELTA (Bit 8)                                      */
27869 #define AUDADC_GAIN_HGADELTA_Msk          (0x7f00UL)                /*!< HGADELTA (Bitfield-Mask: 0x7f)                        */
27870 #define AUDADC_GAIN_LGA_Pos               (0UL)                     /*!< LGA (Bit 0)                                           */
27871 #define AUDADC_GAIN_LGA_Msk               (0x7fUL)                  /*!< LGA (Bitfield-Mask: 0x7f)                             */
27872 /* ========================================================  SATCFG  ========================================================= */
27873 #define AUDADC_SATCFG_SATCHANSEL_Pos      (4UL)                     /*!< SATCHANSEL (Bit 4)                                    */
27874 #define AUDADC_SATCFG_SATCHANSEL_Msk      (0x10UL)                  /*!< SATCHANSEL (Bitfield-Mask: 0x01)                      */
27875 #define AUDADC_SATCFG_SATEN_Pos           (0UL)                     /*!< SATEN (Bit 0)                                         */
27876 #define AUDADC_SATCFG_SATEN_Msk           (0x1UL)                   /*!< SATEN (Bitfield-Mask: 0x01)                           */
27877 /* ========================================================  SATLIM  ========================================================= */
27878 #define AUDADC_SATLIM_USATC_Pos           (16UL)                    /*!< USATC (Bit 16)                                        */
27879 #define AUDADC_SATLIM_USATC_Msk           (0xfff0000UL)             /*!< USATC (Bitfield-Mask: 0xfff)                          */
27880 #define AUDADC_SATLIM_LSATC_Pos           (0UL)                     /*!< LSATC (Bit 0)                                         */
27881 #define AUDADC_SATLIM_LSATC_Msk           (0xfffUL)                 /*!< LSATC (Bitfield-Mask: 0xfff)                          */
27882 /* ========================================================  SATMAX  ========================================================= */
27883 #define AUDADC_SATMAX_SATCBMAX_Pos        (16UL)                    /*!< SATCBMAX (Bit 16)                                     */
27884 #define AUDADC_SATMAX_SATCBMAX_Msk        (0xfff0000UL)             /*!< SATCBMAX (Bitfield-Mask: 0xfff)                       */
27885 #define AUDADC_SATMAX_SATCAMAX_Pos        (0UL)                     /*!< SATCAMAX (Bit 0)                                      */
27886 #define AUDADC_SATMAX_SATCAMAX_Msk        (0xfffUL)                 /*!< SATCAMAX (Bitfield-Mask: 0xfff)                       */
27887 /* ========================================================  SATCLR  ========================================================= */
27888 #define AUDADC_SATCLR_SATCBCLR_Pos        (1UL)                     /*!< SATCBCLR (Bit 1)                                      */
27889 #define AUDADC_SATCLR_SATCBCLR_Msk        (0x2UL)                   /*!< SATCBCLR (Bitfield-Mask: 0x01)                        */
27890 #define AUDADC_SATCLR_SATCACLR_Pos        (0UL)                     /*!< SATCACLR (Bit 0)                                      */
27891 #define AUDADC_SATCLR_SATCACLR_Msk        (0x1UL)                   /*!< SATCACLR (Bitfield-Mask: 0x01)                        */
27892 /* =========================================================  INTEN  ========================================================= */
27893 #define AUDADC_INTEN_SATCB_Pos            (11UL)                    /*!< SATCB (Bit 11)                                        */
27894 #define AUDADC_INTEN_SATCB_Msk            (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27895 #define AUDADC_INTEN_SATCA_Pos            (10UL)                    /*!< SATCA (Bit 10)                                        */
27896 #define AUDADC_INTEN_SATCA_Msk            (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27897 #define AUDADC_INTEN_ZXCB_Pos             (9UL)                     /*!< ZXCB (Bit 9)                                          */
27898 #define AUDADC_INTEN_ZXCB_Msk             (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27899 #define AUDADC_INTEN_ZXCA_Pos             (8UL)                     /*!< ZXCA (Bit 8)                                          */
27900 #define AUDADC_INTEN_ZXCA_Msk             (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27901 #define AUDADC_INTEN_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
27902 #define AUDADC_INTEN_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27903 #define AUDADC_INTEN_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
27904 #define AUDADC_INTEN_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27905 #define AUDADC_INTEN_WCINC_Pos            (5UL)                     /*!< WCINC (Bit 5)                                         */
27906 #define AUDADC_INTEN_WCINC_Msk            (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27907 #define AUDADC_INTEN_WCEXC_Pos            (4UL)                     /*!< WCEXC (Bit 4)                                         */
27908 #define AUDADC_INTEN_WCEXC_Msk            (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27909 #define AUDADC_INTEN_FIFOOVR2_Pos         (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27910 #define AUDADC_INTEN_FIFOOVR2_Msk         (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27911 #define AUDADC_INTEN_FIFOOVR1_Pos         (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27912 #define AUDADC_INTEN_FIFOOVR1_Msk         (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27913 #define AUDADC_INTEN_SCNCMP_Pos           (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27914 #define AUDADC_INTEN_SCNCMP_Msk           (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27915 #define AUDADC_INTEN_CNVCMP_Pos           (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27916 #define AUDADC_INTEN_CNVCMP_Msk           (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27917 /* ========================================================  INTSTAT  ======================================================== */
27918 #define AUDADC_INTSTAT_SATCB_Pos          (11UL)                    /*!< SATCB (Bit 11)                                        */
27919 #define AUDADC_INTSTAT_SATCB_Msk          (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27920 #define AUDADC_INTSTAT_SATCA_Pos          (10UL)                    /*!< SATCA (Bit 10)                                        */
27921 #define AUDADC_INTSTAT_SATCA_Msk          (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27922 #define AUDADC_INTSTAT_ZXCB_Pos           (9UL)                     /*!< ZXCB (Bit 9)                                          */
27923 #define AUDADC_INTSTAT_ZXCB_Msk           (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27924 #define AUDADC_INTSTAT_ZXCA_Pos           (8UL)                     /*!< ZXCA (Bit 8)                                          */
27925 #define AUDADC_INTSTAT_ZXCA_Msk           (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27926 #define AUDADC_INTSTAT_DERR_Pos           (7UL)                     /*!< DERR (Bit 7)                                          */
27927 #define AUDADC_INTSTAT_DERR_Msk           (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27928 #define AUDADC_INTSTAT_DCMP_Pos           (6UL)                     /*!< DCMP (Bit 6)                                          */
27929 #define AUDADC_INTSTAT_DCMP_Msk           (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27930 #define AUDADC_INTSTAT_WCINC_Pos          (5UL)                     /*!< WCINC (Bit 5)                                         */
27931 #define AUDADC_INTSTAT_WCINC_Msk          (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27932 #define AUDADC_INTSTAT_WCEXC_Pos          (4UL)                     /*!< WCEXC (Bit 4)                                         */
27933 #define AUDADC_INTSTAT_WCEXC_Msk          (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27934 #define AUDADC_INTSTAT_FIFOOVR2_Pos       (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27935 #define AUDADC_INTSTAT_FIFOOVR2_Msk       (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27936 #define AUDADC_INTSTAT_FIFOOVR1_Pos       (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27937 #define AUDADC_INTSTAT_FIFOOVR1_Msk       (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27938 #define AUDADC_INTSTAT_SCNCMP_Pos         (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27939 #define AUDADC_INTSTAT_SCNCMP_Msk         (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27940 #define AUDADC_INTSTAT_CNVCMP_Pos         (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27941 #define AUDADC_INTSTAT_CNVCMP_Msk         (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27942 /* ========================================================  INTCLR  ========================================================= */
27943 #define AUDADC_INTCLR_SATCB_Pos           (11UL)                    /*!< SATCB (Bit 11)                                        */
27944 #define AUDADC_INTCLR_SATCB_Msk           (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27945 #define AUDADC_INTCLR_SATCA_Pos           (10UL)                    /*!< SATCA (Bit 10)                                        */
27946 #define AUDADC_INTCLR_SATCA_Msk           (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27947 #define AUDADC_INTCLR_ZXCB_Pos            (9UL)                     /*!< ZXCB (Bit 9)                                          */
27948 #define AUDADC_INTCLR_ZXCB_Msk            (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27949 #define AUDADC_INTCLR_ZXCA_Pos            (8UL)                     /*!< ZXCA (Bit 8)                                          */
27950 #define AUDADC_INTCLR_ZXCA_Msk            (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27951 #define AUDADC_INTCLR_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
27952 #define AUDADC_INTCLR_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27953 #define AUDADC_INTCLR_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
27954 #define AUDADC_INTCLR_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27955 #define AUDADC_INTCLR_WCINC_Pos           (5UL)                     /*!< WCINC (Bit 5)                                         */
27956 #define AUDADC_INTCLR_WCINC_Msk           (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27957 #define AUDADC_INTCLR_WCEXC_Pos           (4UL)                     /*!< WCEXC (Bit 4)                                         */
27958 #define AUDADC_INTCLR_WCEXC_Msk           (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27959 #define AUDADC_INTCLR_FIFOOVR2_Pos        (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27960 #define AUDADC_INTCLR_FIFOOVR2_Msk        (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27961 #define AUDADC_INTCLR_FIFOOVR1_Pos        (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27962 #define AUDADC_INTCLR_FIFOOVR1_Msk        (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27963 #define AUDADC_INTCLR_SCNCMP_Pos          (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27964 #define AUDADC_INTCLR_SCNCMP_Msk          (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27965 #define AUDADC_INTCLR_CNVCMP_Pos          (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27966 #define AUDADC_INTCLR_CNVCMP_Msk          (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27967 /* ========================================================  INTSET  ========================================================= */
27968 #define AUDADC_INTSET_SATCB_Pos           (11UL)                    /*!< SATCB (Bit 11)                                        */
27969 #define AUDADC_INTSET_SATCB_Msk           (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
27970 #define AUDADC_INTSET_SATCA_Pos           (10UL)                    /*!< SATCA (Bit 10)                                        */
27971 #define AUDADC_INTSET_SATCA_Msk           (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
27972 #define AUDADC_INTSET_ZXCB_Pos            (9UL)                     /*!< ZXCB (Bit 9)                                          */
27973 #define AUDADC_INTSET_ZXCB_Msk            (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
27974 #define AUDADC_INTSET_ZXCA_Pos            (8UL)                     /*!< ZXCA (Bit 8)                                          */
27975 #define AUDADC_INTSET_ZXCA_Msk            (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
27976 #define AUDADC_INTSET_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
27977 #define AUDADC_INTSET_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
27978 #define AUDADC_INTSET_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
27979 #define AUDADC_INTSET_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
27980 #define AUDADC_INTSET_WCINC_Pos           (5UL)                     /*!< WCINC (Bit 5)                                         */
27981 #define AUDADC_INTSET_WCINC_Msk           (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
27982 #define AUDADC_INTSET_WCEXC_Pos           (4UL)                     /*!< WCEXC (Bit 4)                                         */
27983 #define AUDADC_INTSET_WCEXC_Msk           (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
27984 #define AUDADC_INTSET_FIFOOVR2_Pos        (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
27985 #define AUDADC_INTSET_FIFOOVR2_Msk        (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
27986 #define AUDADC_INTSET_FIFOOVR1_Pos        (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
27987 #define AUDADC_INTSET_FIFOOVR1_Msk        (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
27988 #define AUDADC_INTSET_SCNCMP_Pos          (1UL)                     /*!< SCNCMP (Bit 1)                                        */
27989 #define AUDADC_INTSET_SCNCMP_Msk          (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
27990 #define AUDADC_INTSET_CNVCMP_Pos          (0UL)                     /*!< CNVCMP (Bit 0)                                        */
27991 #define AUDADC_INTSET_CNVCMP_Msk          (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
27992 /* =======================================================  DMATRIGEN  ======================================================= */
27993 #define AUDADC_DMATRIGEN_DFIFOFULL_Pos    (1UL)                     /*!< DFIFOFULL (Bit 1)                                     */
27994 #define AUDADC_DMATRIGEN_DFIFOFULL_Msk    (0x2UL)                   /*!< DFIFOFULL (Bitfield-Mask: 0x01)                       */
27995 #define AUDADC_DMATRIGEN_DFIFO75_Pos      (0UL)                     /*!< DFIFO75 (Bit 0)                                       */
27996 #define AUDADC_DMATRIGEN_DFIFO75_Msk      (0x1UL)                   /*!< DFIFO75 (Bitfield-Mask: 0x01)                         */
27997 /* ======================================================  DMATRIGSTAT  ====================================================== */
27998 #define AUDADC_DMATRIGSTAT_DFULLSTAT_Pos  (1UL)                     /*!< DFULLSTAT (Bit 1)                                     */
27999 #define AUDADC_DMATRIGSTAT_DFULLSTAT_Msk  (0x2UL)                   /*!< DFULLSTAT (Bitfield-Mask: 0x01)                       */
28000 #define AUDADC_DMATRIGSTAT_D75STAT_Pos    (0UL)                     /*!< D75STAT (Bit 0)                                       */
28001 #define AUDADC_DMATRIGSTAT_D75STAT_Msk    (0x1UL)                   /*!< D75STAT (Bitfield-Mask: 0x01)                         */
28002 /* ========================================================  DMACFG  ========================================================= */
28003 #define AUDADC_DMACFG_DPWROFF_Pos         (18UL)                    /*!< DPWROFF (Bit 18)                                      */
28004 #define AUDADC_DMACFG_DPWROFF_Msk         (0x40000UL)               /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
28005 #define AUDADC_DMACFG_DMADYNPRI_Pos       (9UL)                     /*!< DMADYNPRI (Bit 9)                                     */
28006 #define AUDADC_DMACFG_DMADYNPRI_Msk       (0x200UL)                 /*!< DMADYNPRI (Bitfield-Mask: 0x01)                       */
28007 #define AUDADC_DMACFG_DMAPRI_Pos          (8UL)                     /*!< DMAPRI (Bit 8)                                        */
28008 #define AUDADC_DMACFG_DMAPRI_Msk          (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
28009 #define AUDADC_DMACFG_DMADIR_Pos          (2UL)                     /*!< DMADIR (Bit 2)                                        */
28010 #define AUDADC_DMACFG_DMADIR_Msk          (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
28011 #define AUDADC_DMACFG_DMAEN_Pos           (0UL)                     /*!< DMAEN (Bit 0)                                         */
28012 #define AUDADC_DMACFG_DMAEN_Msk           (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
28013 /* ======================================================  DMATOTCOUNT  ====================================================== */
28014 #define AUDADC_DMATOTCOUNT_TOTCOUNT_Pos   (2UL)                     /*!< TOTCOUNT (Bit 2)                                      */
28015 #define AUDADC_DMATOTCOUNT_TOTCOUNT_Msk   (0x3fffcUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
28016 /* ======================================================  DMATARGADDR  ====================================================== */
28017 #define AUDADC_DMATARGADDR_UTARGADDR_Pos  (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
28018 #define AUDADC_DMATARGADDR_UTARGADDR_Msk  (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
28019 #define AUDADC_DMATARGADDR_LTARGADDR_Pos  (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
28020 #define AUDADC_DMATARGADDR_LTARGADDR_Msk  (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
28021 /* ========================================================  DMASTAT  ======================================================== */
28022 #define AUDADC_DMASTAT_DMAERR_Pos         (2UL)                     /*!< DMAERR (Bit 2)                                        */
28023 #define AUDADC_DMASTAT_DMAERR_Msk         (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
28024 #define AUDADC_DMASTAT_DMACPL_Pos         (1UL)                     /*!< DMACPL (Bit 1)                                        */
28025 #define AUDADC_DMASTAT_DMACPL_Msk         (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
28026 #define AUDADC_DMASTAT_DMATIP_Pos         (0UL)                     /*!< DMATIP (Bit 0)                                        */
28027 #define AUDADC_DMASTAT_DMATIP_Msk         (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
28028 
28029 
28030 /* =========================================================================================================================== */
28031 /* ================                                          CLKGEN                                           ================ */
28032 /* =========================================================================================================================== */
28033 
28034 /* =========================================================  OCTRL  ========================================================= */
28035 #define CLKGEN_OCTRL_OSEL_Pos             (7UL)                     /*!< OSEL (Bit 7)                                          */
28036 #define CLKGEN_OCTRL_OSEL_Msk             (0x80UL)                  /*!< OSEL (Bitfield-Mask: 0x01)                            */
28037 /* ========================================================  CLKOUT  ========================================================= */
28038 #define CLKGEN_CLKOUT_CKEN_Pos            (7UL)                     /*!< CKEN (Bit 7)                                          */
28039 #define CLKGEN_CLKOUT_CKEN_Msk            (0x80UL)                  /*!< CKEN (Bitfield-Mask: 0x01)                            */
28040 #define CLKGEN_CLKOUT_CKSEL_Pos           (0UL)                     /*!< CKSEL (Bit 0)                                         */
28041 #define CLKGEN_CLKOUT_CKSEL_Msk           (0x3fUL)                  /*!< CKSEL (Bitfield-Mask: 0x3f)                           */
28042 /* =========================================================  HFADJ  ========================================================= */
28043 #define CLKGEN_HFADJ_HFADJMAXDELTA_Pos    (24UL)                    /*!< HFADJMAXDELTA (Bit 24)                                */
28044 #define CLKGEN_HFADJ_HFADJMAXDELTA_Msk    (0x1f000000UL)            /*!< HFADJMAXDELTA (Bitfield-Mask: 0x1f)                   */
28045 #define CLKGEN_HFADJ_HFADJGAIN_Pos        (21UL)                    /*!< HFADJGAIN (Bit 21)                                    */
28046 #define CLKGEN_HFADJ_HFADJGAIN_Msk        (0xe00000UL)              /*!< HFADJGAIN (Bitfield-Mask: 0x07)                       */
28047 #define CLKGEN_HFADJ_HFWARMUP_Pos         (20UL)                    /*!< HFWARMUP (Bit 20)                                     */
28048 #define CLKGEN_HFADJ_HFWARMUP_Msk         (0x100000UL)              /*!< HFWARMUP (Bitfield-Mask: 0x01)                        */
28049 #define CLKGEN_HFADJ_HFXTADJ_Pos          (8UL)                     /*!< HFXTADJ (Bit 8)                                       */
28050 #define CLKGEN_HFADJ_HFXTADJ_Msk          (0xfff00UL)               /*!< HFXTADJ (Bitfield-Mask: 0xfff)                        */
28051 #define CLKGEN_HFADJ_HFADJCK_Pos          (1UL)                     /*!< HFADJCK (Bit 1)                                       */
28052 #define CLKGEN_HFADJ_HFADJCK_Msk          (0xeUL)                   /*!< HFADJCK (Bitfield-Mask: 0x07)                         */
28053 #define CLKGEN_HFADJ_HFADJEN_Pos          (0UL)                     /*!< HFADJEN (Bit 0)                                       */
28054 #define CLKGEN_HFADJ_HFADJEN_Msk          (0x1UL)                   /*!< HFADJEN (Bitfield-Mask: 0x01)                         */
28055 /* ======================================================  CLOCKENSTAT  ====================================================== */
28056 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL)                    /*!< CLOCKENSTAT (Bit 0)                                   */
28057 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL)           /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff)               */
28058 /* =====================================================  CLOCKEN2STAT  ====================================================== */
28059 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL)                  /*!< CLOCKEN2STAT (Bit 0)                                  */
28060 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL)         /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff)              */
28061 /* =====================================================  CLOCKEN3STAT  ====================================================== */
28062 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL)                  /*!< CLOCKEN3STAT (Bit 0)                                  */
28063 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL)         /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff)              */
28064 /* =========================================================  MISC  ========================================================== */
28065 #define CLKGEN_MISC_CLKGENMISCSPARES_Pos  (18UL)                    /*!< CLKGENMISCSPARES (Bit 18)                             */
28066 #define CLKGEN_MISC_CLKGENMISCSPARES_Msk  (0x3fc0000UL)             /*!< CLKGENMISCSPARES (Bitfield-Mask: 0xff)                */
28067 #define CLKGEN_MISC_PWRONCLKENDISP_Pos    (6UL)                     /*!< PWRONCLKENDISP (Bit 6)                                */
28068 #define CLKGEN_MISC_PWRONCLKENDISP_Msk    (0x40UL)                  /*!< PWRONCLKENDISP (Bitfield-Mask: 0x01)                  */
28069 #define CLKGEN_MISC_FRCHFRC2_Pos          (5UL)                     /*!< FRCHFRC2 (Bit 5)                                      */
28070 #define CLKGEN_MISC_FRCHFRC2_Msk          (0x20UL)                  /*!< FRCHFRC2 (Bitfield-Mask: 0x01)                        */
28071 #define CLKGEN_MISC_USEHFRC2FQ192MHZ_Pos  (4UL)                     /*!< USEHFRC2FQ192MHZ (Bit 4)                              */
28072 #define CLKGEN_MISC_USEHFRC2FQ192MHZ_Msk  (0x10UL)                  /*!< USEHFRC2FQ192MHZ (Bitfield-Mask: 0x01)                */
28073 #define CLKGEN_MISC_USEHFRC2FQ96MHZ_Pos   (3UL)                     /*!< USEHFRC2FQ96MHZ (Bit 3)                               */
28074 #define CLKGEN_MISC_USEHFRC2FQ96MHZ_Msk   (0x8UL)                   /*!< USEHFRC2FQ96MHZ (Bitfield-Mask: 0x01)                 */
28075 #define CLKGEN_MISC_FRCHFRC_Pos           (0UL)                     /*!< FRCHFRC (Bit 0)                                       */
28076 #define CLKGEN_MISC_FRCHFRC_Msk           (0x1UL)                   /*!< FRCHFRC (Bitfield-Mask: 0x01)                         */
28077 /* ========================================================  HF2ADJ0  ======================================================== */
28078 #define CLKGEN_HF2ADJ0_HF2ADJXTHSMUXSEL_Pos (29UL)                  /*!< HF2ADJXTHSMUXSEL (Bit 29)                             */
28079 #define CLKGEN_HF2ADJ0_HF2ADJXTHSMUXSEL_Msk (0x20000000UL)          /*!< HF2ADJXTHSMUXSEL (Bitfield-Mask: 0x01)                */
28080 #define CLKGEN_HF2ADJ0_HF2ADJCNTINOFFSET_Pos (15UL)                 /*!< HF2ADJCNTINOFFSET (Bit 15)                            */
28081 #define CLKGEN_HF2ADJ0_HF2ADJCNTINOFFSET_Msk (0x1fff8000UL)         /*!< HF2ADJCNTINOFFSET (Bitfield-Mask: 0x3fff)             */
28082 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTRDLY_Pos (2UL)                   /*!< HF2ADJFASTSTRDLY (Bit 2)                              */
28083 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTRDLY_Msk (0x7ffcUL)              /*!< HF2ADJFASTSTRDLY (Bitfield-Mask: 0x1fff)              */
28084 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Pos (1UL)                    /*!< HF2ADJFASTSTREN (Bit 1)                               */
28085 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Msk (0x2UL)                  /*!< HF2ADJFASTSTREN (Bitfield-Mask: 0x01)                 */
28086 #define CLKGEN_HF2ADJ0_HF2ADJEN_Pos       (0UL)                     /*!< HF2ADJEN (Bit 0)                                      */
28087 #define CLKGEN_HF2ADJ0_HF2ADJEN_Msk       (0x1UL)                   /*!< HF2ADJEN (Bitfield-Mask: 0x01)                        */
28088 /* ========================================================  HF2ADJ1  ======================================================== */
28089 #define CLKGEN_HF2ADJ1_HF2ADJTRIMOFFSET_Pos (3UL)                   /*!< HF2ADJTRIMOFFSET (Bit 3)                              */
28090 #define CLKGEN_HF2ADJ1_HF2ADJTRIMOFFSET_Msk (0x3ff8UL)              /*!< HF2ADJTRIMOFFSET (Bitfield-Mask: 0x7ff)               */
28091 #define CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Pos   (0UL)                     /*!< HF2ADJTRIMEN (Bit 0)                                  */
28092 #define CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Msk   (0x7UL)                   /*!< HF2ADJTRIMEN (Bitfield-Mask: 0x07)                    */
28093 /* ========================================================  HF2ADJ2  ======================================================== */
28094 #define CLKGEN_HF2ADJ2_HF2ADJRATIO_Pos    (2UL)                     /*!< HF2ADJRATIO (Bit 2)                                   */
28095 #define CLKGEN_HF2ADJ2_HF2ADJRATIO_Msk    (0x7ffffffcUL)            /*!< HF2ADJRATIO (Bitfield-Mask: 0x1fffffff)               */
28096 #define CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Pos (0UL)                 /*!< HF2ADJXTALDIVRATIO (Bit 0)                            */
28097 #define CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Msk (0x3UL)               /*!< HF2ADJXTALDIVRATIO (Bitfield-Mask: 0x03)              */
28098 /* ========================================================  HF2VAL  ========================================================= */
28099 #define CLKGEN_HF2VAL_HF2ADJTRIMOUT_Pos   (0UL)                     /*!< HF2ADJTRIMOUT (Bit 0)                                 */
28100 #define CLKGEN_HF2VAL_HF2ADJTRIMOUT_Msk   (0x7ffUL)                 /*!< HF2ADJTRIMOUT (Bitfield-Mask: 0x7ff)                  */
28101 /* =======================================================  LFRCCTRL  ======================================================== */
28102 #define CLKGEN_LFRCCTRL_LFRCPWD_Pos       (1UL)                     /*!< LFRCPWD (Bit 1)                                       */
28103 #define CLKGEN_LFRCCTRL_LFRCPWD_Msk       (0x2UL)                   /*!< LFRCPWD (Bitfield-Mask: 0x01)                         */
28104 #define CLKGEN_LFRCCTRL_LFRCOUT_Pos       (0UL)                     /*!< LFRCOUT (Bit 0)                                       */
28105 #define CLKGEN_LFRCCTRL_LFRCOUT_Msk       (0x1UL)                   /*!< LFRCOUT (Bitfield-Mask: 0x01)                         */
28106 /* ======================================================  DISPCLKCTRL  ====================================================== */
28107 #define CLKGEN_DISPCLKCTRL_DCCLKEN_Pos    (7UL)                     /*!< DCCLKEN (Bit 7)                                       */
28108 #define CLKGEN_DISPCLKCTRL_DCCLKEN_Msk    (0x80UL)                  /*!< DCCLKEN (Bitfield-Mask: 0x01)                         */
28109 #define CLKGEN_DISPCLKCTRL_DISPCLKSEL_Pos (4UL)                     /*!< DISPCLKSEL (Bit 4)                                    */
28110 #define CLKGEN_DISPCLKCTRL_DISPCLKSEL_Msk (0x30UL)                  /*!< DISPCLKSEL (Bitfield-Mask: 0x03)                      */
28111 #define CLKGEN_DISPCLKCTRL_PLLCLKEN_Pos   (3UL)                     /*!< PLLCLKEN (Bit 3)                                      */
28112 #define CLKGEN_DISPCLKCTRL_PLLCLKEN_Msk   (0x8UL)                   /*!< PLLCLKEN (Bitfield-Mask: 0x01)                        */
28113 #define CLKGEN_DISPCLKCTRL_PLLCLKSEL_Pos  (0UL)                     /*!< PLLCLKSEL (Bit 0)                                     */
28114 #define CLKGEN_DISPCLKCTRL_PLLCLKSEL_Msk  (0x3UL)                   /*!< PLLCLKSEL (Bitfield-Mask: 0x03)                       */
28115 
28116 
28117 /* =========================================================================================================================== */
28118 /* ================                                            CPU                                            ================ */
28119 /* =========================================================================================================================== */
28120 
28121 /* =======================================================  CACHECFG  ======================================================== */
28122 #define CPU_CACHECFG_ENABLEMONITOR_Pos    (24UL)                    /*!< ENABLEMONITOR (Bit 24)                                */
28123 #define CPU_CACHECFG_ENABLEMONITOR_Msk    (0x1000000UL)             /*!< ENABLEMONITOR (Bitfield-Mask: 0x01)                   */
28124 #define CPU_CACHECFG_DATACLKGATE_Pos      (20UL)                    /*!< DATACLKGATE (Bit 20)                                  */
28125 #define CPU_CACHECFG_DATACLKGATE_Msk      (0x100000UL)              /*!< DATACLKGATE (Bitfield-Mask: 0x01)                     */
28126 #define CPU_CACHECFG_NC0CACHELOCK_Pos     (13UL)                    /*!< NC0CACHELOCK (Bit 13)                                 */
28127 #define CPU_CACHECFG_NC0CACHELOCK_Msk     (0x2000UL)                /*!< NC0CACHELOCK (Bitfield-Mask: 0x01)                    */
28128 #define CPU_CACHECFG_NC1CACHELOCK_Pos     (12UL)                    /*!< NC1CACHELOCK (Bit 12)                                 */
28129 #define CPU_CACHECFG_NC1CACHELOCK_Msk     (0x1000UL)                /*!< NC1CACHELOCK (Bitfield-Mask: 0x01)                    */
28130 #define CPU_CACHECFG_LS_Pos               (11UL)                    /*!< LS (Bit 11)                                           */
28131 #define CPU_CACHECFG_LS_Msk               (0x800UL)                 /*!< LS (Bitfield-Mask: 0x01)                              */
28132 #define CPU_CACHECFG_CLKGATE_Pos          (10UL)                    /*!< CLKGATE (Bit 10)                                      */
28133 #define CPU_CACHECFG_CLKGATE_Msk          (0x400UL)                 /*!< CLKGATE (Bitfield-Mask: 0x01)                         */
28134 #define CPU_CACHECFG_DENABLE_Pos          (9UL)                     /*!< DENABLE (Bit 9)                                       */
28135 #define CPU_CACHECFG_DENABLE_Msk          (0x200UL)                 /*!< DENABLE (Bitfield-Mask: 0x01)                         */
28136 #define CPU_CACHECFG_IENABLE_Pos          (8UL)                     /*!< IENABLE (Bit 8)                                       */
28137 #define CPU_CACHECFG_IENABLE_Msk          (0x100UL)                 /*!< IENABLE (Bitfield-Mask: 0x01)                         */
28138 #define CPU_CACHECFG_CONFIG_Pos           (4UL)                     /*!< CONFIG (Bit 4)                                        */
28139 #define CPU_CACHECFG_CONFIG_Msk           (0xf0UL)                  /*!< CONFIG (Bitfield-Mask: 0x0f)                          */
28140 #define CPU_CACHECFG_NC1ENABLE_Pos        (3UL)                     /*!< NC1ENABLE (Bit 3)                                     */
28141 #define CPU_CACHECFG_NC1ENABLE_Msk        (0x8UL)                   /*!< NC1ENABLE (Bitfield-Mask: 0x01)                       */
28142 #define CPU_CACHECFG_NC0ENABLE_Pos        (2UL)                     /*!< NC0ENABLE (Bit 2)                                     */
28143 #define CPU_CACHECFG_NC0ENABLE_Msk        (0x4UL)                   /*!< NC0ENABLE (Bitfield-Mask: 0x01)                       */
28144 #define CPU_CACHECFG_LRU_Pos              (1UL)                     /*!< LRU (Bit 1)                                           */
28145 #define CPU_CACHECFG_LRU_Msk              (0x2UL)                   /*!< LRU (Bitfield-Mask: 0x01)                             */
28146 #define CPU_CACHECFG_ENABLE_Pos           (0UL)                     /*!< ENABLE (Bit 0)                                        */
28147 #define CPU_CACHECFG_ENABLE_Msk           (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
28148 /* =======================================================  CACHECTRL  ======================================================= */
28149 #define CPU_CACHECTRL_CACHEREADY_Pos      (2UL)                     /*!< CACHEREADY (Bit 2)                                    */
28150 #define CPU_CACHECTRL_CACHEREADY_Msk      (0x4UL)                   /*!< CACHEREADY (Bitfield-Mask: 0x01)                      */
28151 #define CPU_CACHECTRL_RESETSTAT_Pos       (1UL)                     /*!< RESETSTAT (Bit 1)                                     */
28152 #define CPU_CACHECTRL_RESETSTAT_Msk       (0x2UL)                   /*!< RESETSTAT (Bitfield-Mask: 0x01)                       */
28153 #define CPU_CACHECTRL_INVALIDATE_Pos      (0UL)                     /*!< INVALIDATE (Bit 0)                                    */
28154 #define CPU_CACHECTRL_INVALIDATE_Msk      (0x1UL)                   /*!< INVALIDATE (Bitfield-Mask: 0x01)                      */
28155 /* =======================================================  NCR0START  ======================================================= */
28156 #define CPU_NCR0START_ADDR_Pos            (4UL)                     /*!< ADDR (Bit 4)                                          */
28157 #define CPU_NCR0START_ADDR_Msk            (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28158 /* ========================================================  NCR0END  ======================================================== */
28159 #define CPU_NCR0END_ADDR_Pos              (4UL)                     /*!< ADDR (Bit 4)                                          */
28160 #define CPU_NCR0END_ADDR_Msk              (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28161 /* =======================================================  NCR1START  ======================================================= */
28162 #define CPU_NCR1START_ADDR_Pos            (4UL)                     /*!< ADDR (Bit 4)                                          */
28163 #define CPU_NCR1START_ADDR_Msk            (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28164 /* ========================================================  NCR1END  ======================================================== */
28165 #define CPU_NCR1END_ADDR_Pos              (4UL)                     /*!< ADDR (Bit 4)                                          */
28166 #define CPU_NCR1END_ADDR_Msk              (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28167 /* ========================================================  DAXICFG  ======================================================== */
28168 #define CPU_DAXICFG_AGINGCOUNTER_Pos      (16UL)                    /*!< AGINGCOUNTER (Bit 16)                                 */
28169 #define CPU_DAXICFG_AGINGCOUNTER_Msk      (0xff0000UL)              /*!< AGINGCOUNTER (Bitfield-Mask: 0xff)                    */
28170 #define CPU_DAXICFG_BUFFERENABLE_Pos      (8UL)                     /*!< BUFFERENABLE (Bit 8)                                  */
28171 #define CPU_DAXICFG_BUFFERENABLE_Msk      (0x300UL)                 /*!< BUFFERENABLE (Bitfield-Mask: 0x03)                    */
28172 #define CPU_DAXICFG_FLUSHLEVEL_Pos        (0UL)                     /*!< FLUSHLEVEL (Bit 0)                                    */
28173 #define CPU_DAXICFG_FLUSHLEVEL_Msk        (0x1UL)                   /*!< FLUSHLEVEL (Bitfield-Mask: 0x01)                      */
28174 /* =======================================================  DAXICTRL  ======================================================== */
28175 #define CPU_DAXICTRL_DAXIINVALIDATE_Pos   (1UL)                     /*!< DAXIINVALIDATE (Bit 1)                                */
28176 #define CPU_DAXICTRL_DAXIINVALIDATE_Msk   (0x2UL)                   /*!< DAXIINVALIDATE (Bitfield-Mask: 0x01)                  */
28177 #define CPU_DAXICTRL_DAXIFLUSHWRITE_Pos   (0UL)                     /*!< DAXIFLUSHWRITE (Bit 0)                                */
28178 #define CPU_DAXICTRL_DAXIFLUSHWRITE_Msk   (0x1UL)                   /*!< DAXIFLUSHWRITE (Bitfield-Mask: 0x01)                  */
28179 /* ====================================================  ICODEFAULTADDR  ===================================================== */
28180 #define CPU_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL)                 /*!< ICODEFAULTADDR (Bit 0)                                */
28181 #define CPU_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL)        /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
28182 /* ====================================================  DCODEFAULTADDR  ===================================================== */
28183 #define CPU_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL)                 /*!< DCODEFAULTADDR (Bit 0)                                */
28184 #define CPU_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL)        /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
28185 /* =====================================================  SYSFAULTADDR  ====================================================== */
28186 #define CPU_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL)                     /*!< SYSFAULTADDR (Bit 0)                                  */
28187 #define CPU_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL)            /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff)              */
28188 /* ======================================================  FAULTSTATUS  ====================================================== */
28189 #define CPU_FAULTSTATUS_SYSFAULT_Pos      (2UL)                     /*!< SYSFAULT (Bit 2)                                      */
28190 #define CPU_FAULTSTATUS_SYSFAULT_Msk      (0x4UL)                   /*!< SYSFAULT (Bitfield-Mask: 0x01)                        */
28191 #define CPU_FAULTSTATUS_DCODEFAULT_Pos    (1UL)                     /*!< DCODEFAULT (Bit 1)                                    */
28192 #define CPU_FAULTSTATUS_DCODEFAULT_Msk    (0x2UL)                   /*!< DCODEFAULT (Bitfield-Mask: 0x01)                      */
28193 #define CPU_FAULTSTATUS_ICODEFAULT_Pos    (0UL)                     /*!< ICODEFAULT (Bit 0)                                    */
28194 #define CPU_FAULTSTATUS_ICODEFAULT_Msk    (0x1UL)                   /*!< ICODEFAULT (Bitfield-Mask: 0x01)                      */
28195 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
28196 #define CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL)                 /*!< FAULTCAPTUREEN (Bit 0)                                */
28197 #define CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL)               /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01)                  */
28198 /* =========================================================  INTEN  ========================================================= */
28199 #define CPU_INTEN_AXIWERROR_Pos           (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28200 #define CPU_INTEN_AXIWERROR_Msk           (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28201 /* ========================================================  INTSTAT  ======================================================== */
28202 #define CPU_INTSTAT_AXIWERROR_Pos         (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28203 #define CPU_INTSTAT_AXIWERROR_Msk         (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28204 /* ========================================================  INTCLR  ========================================================= */
28205 #define CPU_INTCLR_AXIWERROR_Pos          (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28206 #define CPU_INTCLR_AXIWERROR_Msk          (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28207 /* ========================================================  INTSET  ========================================================= */
28208 #define CPU_INTSET_AXIWERROR_Pos          (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28209 #define CPU_INTSET_AXIWERROR_Msk          (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28210 /* =====================================================  WRITEERRADDR  ====================================================== */
28211 #define CPU_WRITEERRADDR_WERRADDR_Pos     (0UL)                     /*!< WERRADDR (Bit 0)                                      */
28212 #define CPU_WRITEERRADDR_WERRADDR_Msk     (0xffffffffUL)            /*!< WERRADDR (Bitfield-Mask: 0xffffffff)                  */
28213 /* =========================================================  DMON0  ========================================================= */
28214 #define CPU_DMON0_DACCESS_Pos             (0UL)                     /*!< DACCESS (Bit 0)                                       */
28215 #define CPU_DMON0_DACCESS_Msk             (0xffffffffUL)            /*!< DACCESS (Bitfield-Mask: 0xffffffff)                   */
28216 /* =========================================================  DMON1  ========================================================= */
28217 #define CPU_DMON1_DLOOKUP_Pos             (0UL)                     /*!< DLOOKUP (Bit 0)                                       */
28218 #define CPU_DMON1_DLOOKUP_Msk             (0xffffffffUL)            /*!< DLOOKUP (Bitfield-Mask: 0xffffffff)                   */
28219 /* =========================================================  DMON2  ========================================================= */
28220 #define CPU_DMON2_DHIT_Pos                (0UL)                     /*!< DHIT (Bit 0)                                          */
28221 #define CPU_DMON2_DHIT_Msk                (0xffffffffUL)            /*!< DHIT (Bitfield-Mask: 0xffffffff)                      */
28222 /* =========================================================  DMON3  ========================================================= */
28223 #define CPU_DMON3_DLINE_Pos               (0UL)                     /*!< DLINE (Bit 0)                                         */
28224 #define CPU_DMON3_DLINE_Msk               (0xffffffffUL)            /*!< DLINE (Bitfield-Mask: 0xffffffff)                     */
28225 /* =========================================================  IMON0  ========================================================= */
28226 #define CPU_IMON0_IACCESS_Pos             (0UL)                     /*!< IACCESS (Bit 0)                                       */
28227 #define CPU_IMON0_IACCESS_Msk             (0xffffffffUL)            /*!< IACCESS (Bitfield-Mask: 0xffffffff)                   */
28228 /* =========================================================  IMON1  ========================================================= */
28229 #define CPU_IMON1_ILOOKUP_Pos             (0UL)                     /*!< ILOOKUP (Bit 0)                                       */
28230 #define CPU_IMON1_ILOOKUP_Msk             (0xffffffffUL)            /*!< ILOOKUP (Bitfield-Mask: 0xffffffff)                   */
28231 /* =========================================================  IMON2  ========================================================= */
28232 #define CPU_IMON2_IHIT_Pos                (0UL)                     /*!< IHIT (Bit 0)                                          */
28233 #define CPU_IMON2_IHIT_Msk                (0xffffffffUL)            /*!< IHIT (Bitfield-Mask: 0xffffffff)                      */
28234 /* =========================================================  IMON3  ========================================================= */
28235 #define CPU_IMON3_ILINE_Pos               (0UL)                     /*!< ILINE (Bit 0)                                         */
28236 #define CPU_IMON3_ILINE_Msk               (0xffffffffUL)            /*!< ILINE (Bitfield-Mask: 0xffffffff)                     */
28237 
28238 
28239 /* =========================================================================================================================== */
28240 /* ================                                          CRYPTO                                           ================ */
28241 /* =========================================================================================================================== */
28242 
28243 /* ======================================================  MEMORYMAP0  ======================================================= */
28244 #define CRYPTO_MEMORYMAP0_PHYSADDRMAP0_Pos (1UL)                    /*!< PHYSADDRMAP0 (Bit 1)                                  */
28245 #define CRYPTO_MEMORYMAP0_PHYSADDRMAP0_Msk (0x7feUL)                /*!< PHYSADDRMAP0 (Bitfield-Mask: 0x3ff)                   */
28246 /* ======================================================  MEMORYMAP1  ======================================================= */
28247 #define CRYPTO_MEMORYMAP1_PHYSADDRMAP1_Pos (1UL)                    /*!< PHYSADDRMAP1 (Bit 1)                                  */
28248 #define CRYPTO_MEMORYMAP1_PHYSADDRMAP1_Msk (0x7feUL)                /*!< PHYSADDRMAP1 (Bitfield-Mask: 0x3ff)                   */
28249 /* ======================================================  MEMORYMAP2  ======================================================= */
28250 #define CRYPTO_MEMORYMAP2_PHYSADDRMAP2_Pos (1UL)                    /*!< PHYSADDRMAP2 (Bit 1)                                  */
28251 #define CRYPTO_MEMORYMAP2_PHYSADDRMAP2_Msk (0x7feUL)                /*!< PHYSADDRMAP2 (Bitfield-Mask: 0x3ff)                   */
28252 /* ======================================================  MEMORYMAP3  ======================================================= */
28253 #define CRYPTO_MEMORYMAP3_PHYSADDRMAP3_Pos (1UL)                    /*!< PHYSADDRMAP3 (Bit 1)                                  */
28254 #define CRYPTO_MEMORYMAP3_PHYSADDRMAP3_Msk (0x7feUL)                /*!< PHYSADDRMAP3 (Bitfield-Mask: 0x3ff)                   */
28255 /* ======================================================  MEMORYMAP4  ======================================================= */
28256 #define CRYPTO_MEMORYMAP4_PHYSADDRMAP4_Pos (1UL)                    /*!< PHYSADDRMAP4 (Bit 1)                                  */
28257 #define CRYPTO_MEMORYMAP4_PHYSADDRMAP4_Msk (0x7feUL)                /*!< PHYSADDRMAP4 (Bitfield-Mask: 0x3ff)                   */
28258 /* ======================================================  MEMORYMAP5  ======================================================= */
28259 #define CRYPTO_MEMORYMAP5_PHYSADDRMAP5_Pos (1UL)                    /*!< PHYSADDRMAP5 (Bit 1)                                  */
28260 #define CRYPTO_MEMORYMAP5_PHYSADDRMAP5_Msk (0x7feUL)                /*!< PHYSADDRMAP5 (Bitfield-Mask: 0x3ff)                   */
28261 /* ======================================================  MEMORYMAP6  ======================================================= */
28262 #define CRYPTO_MEMORYMAP6_PHYSADDRMAP6_Pos (1UL)                    /*!< PHYSADDRMAP6 (Bit 1)                                  */
28263 #define CRYPTO_MEMORYMAP6_PHYSADDRMAP6_Msk (0x7feUL)                /*!< PHYSADDRMAP6 (Bitfield-Mask: 0x3ff)                   */
28264 /* ======================================================  MEMORYMAP7  ======================================================= */
28265 #define CRYPTO_MEMORYMAP7_PHYSADDRMAP7_Pos (1UL)                    /*!< PHYSADDRMAP7 (Bit 1)                                  */
28266 #define CRYPTO_MEMORYMAP7_PHYSADDRMAP7_Msk (0x7feUL)                /*!< PHYSADDRMAP7 (Bitfield-Mask: 0x3ff)                   */
28267 /* ======================================================  MEMORYMAP8  ======================================================= */
28268 #define CRYPTO_MEMORYMAP8_PHYSADDRMAP8_Pos (1UL)                    /*!< PHYSADDRMAP8 (Bit 1)                                  */
28269 #define CRYPTO_MEMORYMAP8_PHYSADDRMAP8_Msk (0x7feUL)                /*!< PHYSADDRMAP8 (Bitfield-Mask: 0x3ff)                   */
28270 /* ======================================================  MEMORYMAP9  ======================================================= */
28271 #define CRYPTO_MEMORYMAP9_PHYSADDRMAP9_Pos (1UL)                    /*!< PHYSADDRMAP9 (Bit 1)                                  */
28272 #define CRYPTO_MEMORYMAP9_PHYSADDRMAP9_Msk (0x7feUL)                /*!< PHYSADDRMAP9 (Bitfield-Mask: 0x3ff)                   */
28273 /* ======================================================  MEMORYMAP10  ====================================================== */
28274 #define CRYPTO_MEMORYMAP10_PHYSADDRMAP10_Pos (1UL)                  /*!< PHYSADDRMAP10 (Bit 1)                                 */
28275 #define CRYPTO_MEMORYMAP10_PHYSADDRMAP10_Msk (0x7feUL)              /*!< PHYSADDRMAP10 (Bitfield-Mask: 0x3ff)                  */
28276 /* ======================================================  MEMORYMAP11  ====================================================== */
28277 #define CRYPTO_MEMORYMAP11_PHYSADDRMAP11_Pos (1UL)                  /*!< PHYSADDRMAP11 (Bit 1)                                 */
28278 #define CRYPTO_MEMORYMAP11_PHYSADDRMAP11_Msk (0x7feUL)              /*!< PHYSADDRMAP11 (Bitfield-Mask: 0x3ff)                  */
28279 /* ======================================================  MEMORYMAP12  ====================================================== */
28280 #define CRYPTO_MEMORYMAP12_PHYSADDRMAP12_Pos (1UL)                  /*!< PHYSADDRMAP12 (Bit 1)                                 */
28281 #define CRYPTO_MEMORYMAP12_PHYSADDRMAP12_Msk (0x7feUL)              /*!< PHYSADDRMAP12 (Bitfield-Mask: 0x3ff)                  */
28282 /* ======================================================  MEMORYMAP13  ====================================================== */
28283 #define CRYPTO_MEMORYMAP13_PHYSADDRMAP13_Pos (1UL)                  /*!< PHYSADDRMAP13 (Bit 1)                                 */
28284 #define CRYPTO_MEMORYMAP13_PHYSADDRMAP13_Msk (0x7feUL)              /*!< PHYSADDRMAP13 (Bitfield-Mask: 0x3ff)                  */
28285 /* ======================================================  MEMORYMAP14  ====================================================== */
28286 #define CRYPTO_MEMORYMAP14_PHYSADDRMAP14_Pos (1UL)                  /*!< PHYSADDRMAP14 (Bit 1)                                 */
28287 #define CRYPTO_MEMORYMAP14_PHYSADDRMAP14_Msk (0x7feUL)              /*!< PHYSADDRMAP14 (Bitfield-Mask: 0x3ff)                  */
28288 /* ======================================================  MEMORYMAP15  ====================================================== */
28289 #define CRYPTO_MEMORYMAP15_PHYSADDRMAP15_Pos (1UL)                  /*!< PHYSADDRMAP15 (Bit 1)                                 */
28290 #define CRYPTO_MEMORYMAP15_PHYSADDRMAP15_Msk (0x7feUL)              /*!< PHYSADDRMAP15 (Bitfield-Mask: 0x3ff)                  */
28291 /* ======================================================  MEMORYMAP16  ====================================================== */
28292 #define CRYPTO_MEMORYMAP16_PHYSADDRMAP16_Pos (1UL)                  /*!< PHYSADDRMAP16 (Bit 1)                                 */
28293 #define CRYPTO_MEMORYMAP16_PHYSADDRMAP16_Msk (0x7feUL)              /*!< PHYSADDRMAP16 (Bitfield-Mask: 0x3ff)                  */
28294 /* ======================================================  MEMORYMAP17  ====================================================== */
28295 #define CRYPTO_MEMORYMAP17_PHYSADDRMAP17_Pos (1UL)                  /*!< PHYSADDRMAP17 (Bit 1)                                 */
28296 #define CRYPTO_MEMORYMAP17_PHYSADDRMAP17_Msk (0x7feUL)              /*!< PHYSADDRMAP17 (Bitfield-Mask: 0x3ff)                  */
28297 /* ======================================================  MEMORYMAP18  ====================================================== */
28298 #define CRYPTO_MEMORYMAP18_PHYSADDRMAP18_Pos (1UL)                  /*!< PHYSADDRMAP18 (Bit 1)                                 */
28299 #define CRYPTO_MEMORYMAP18_PHYSADDRMAP18_Msk (0x7feUL)              /*!< PHYSADDRMAP18 (Bitfield-Mask: 0x3ff)                  */
28300 /* ======================================================  MEMORYMAP19  ====================================================== */
28301 #define CRYPTO_MEMORYMAP19_PHYSADDRMAP19_Pos (1UL)                  /*!< PHYSADDRMAP19 (Bit 1)                                 */
28302 #define CRYPTO_MEMORYMAP19_PHYSADDRMAP19_Msk (0x7feUL)              /*!< PHYSADDRMAP19 (Bitfield-Mask: 0x3ff)                  */
28303 /* ======================================================  MEMORYMAP20  ====================================================== */
28304 #define CRYPTO_MEMORYMAP20_PHYSADDRMAP20_Pos (1UL)                  /*!< PHYSADDRMAP20 (Bit 1)                                 */
28305 #define CRYPTO_MEMORYMAP20_PHYSADDRMAP20_Msk (0x7feUL)              /*!< PHYSADDRMAP20 (Bitfield-Mask: 0x3ff)                  */
28306 /* ======================================================  MEMORYMAP21  ====================================================== */
28307 #define CRYPTO_MEMORYMAP21_PHYSADDRMAP21_Pos (1UL)                  /*!< PHYSADDRMAP21 (Bit 1)                                 */
28308 #define CRYPTO_MEMORYMAP21_PHYSADDRMAP21_Msk (0x7feUL)              /*!< PHYSADDRMAP21 (Bitfield-Mask: 0x3ff)                  */
28309 /* ======================================================  MEMORYMAP22  ====================================================== */
28310 #define CRYPTO_MEMORYMAP22_PHYSADDRMAP22_Pos (1UL)                  /*!< PHYSADDRMAP22 (Bit 1)                                 */
28311 #define CRYPTO_MEMORYMAP22_PHYSADDRMAP22_Msk (0x7feUL)              /*!< PHYSADDRMAP22 (Bitfield-Mask: 0x3ff)                  */
28312 /* ======================================================  MEMORYMAP23  ====================================================== */
28313 #define CRYPTO_MEMORYMAP23_PHYSADDRMAP23_Pos (1UL)                  /*!< PHYSADDRMAP23 (Bit 1)                                 */
28314 #define CRYPTO_MEMORYMAP23_PHYSADDRMAP23_Msk (0x7feUL)              /*!< PHYSADDRMAP23 (Bitfield-Mask: 0x3ff)                  */
28315 /* ======================================================  MEMORYMAP24  ====================================================== */
28316 #define CRYPTO_MEMORYMAP24_PHYSADDRMAP24_Pos (1UL)                  /*!< PHYSADDRMAP24 (Bit 1)                                 */
28317 #define CRYPTO_MEMORYMAP24_PHYSADDRMAP24_Msk (0x7feUL)              /*!< PHYSADDRMAP24 (Bitfield-Mask: 0x3ff)                  */
28318 /* ======================================================  MEMORYMAP25  ====================================================== */
28319 #define CRYPTO_MEMORYMAP25_PHYSADDRMAP25_Pos (1UL)                  /*!< PHYSADDRMAP25 (Bit 1)                                 */
28320 #define CRYPTO_MEMORYMAP25_PHYSADDRMAP25_Msk (0x7feUL)              /*!< PHYSADDRMAP25 (Bitfield-Mask: 0x3ff)                  */
28321 /* ======================================================  MEMORYMAP26  ====================================================== */
28322 #define CRYPTO_MEMORYMAP26_PHYSADDRMAP26_Pos (1UL)                  /*!< PHYSADDRMAP26 (Bit 1)                                 */
28323 #define CRYPTO_MEMORYMAP26_PHYSADDRMAP26_Msk (0x7feUL)              /*!< PHYSADDRMAP26 (Bitfield-Mask: 0x3ff)                  */
28324 /* ======================================================  MEMORYMAP27  ====================================================== */
28325 #define CRYPTO_MEMORYMAP27_PHYSADDRMAP27_Pos (1UL)                  /*!< PHYSADDRMAP27 (Bit 1)                                 */
28326 #define CRYPTO_MEMORYMAP27_PHYSADDRMAP27_Msk (0x7feUL)              /*!< PHYSADDRMAP27 (Bitfield-Mask: 0x3ff)                  */
28327 /* ======================================================  MEMORYMAP28  ====================================================== */
28328 #define CRYPTO_MEMORYMAP28_PHYSADDRMAP28_Pos (1UL)                  /*!< PHYSADDRMAP28 (Bit 1)                                 */
28329 #define CRYPTO_MEMORYMAP28_PHYSADDRMAP28_Msk (0x7feUL)              /*!< PHYSADDRMAP28 (Bitfield-Mask: 0x3ff)                  */
28330 /* ======================================================  MEMORYMAP29  ====================================================== */
28331 #define CRYPTO_MEMORYMAP29_PHYSADDRMAP29_Pos (1UL)                  /*!< PHYSADDRMAP29 (Bit 1)                                 */
28332 #define CRYPTO_MEMORYMAP29_PHYSADDRMAP29_Msk (0x7feUL)              /*!< PHYSADDRMAP29 (Bitfield-Mask: 0x3ff)                  */
28333 /* ======================================================  MEMORYMAP30  ====================================================== */
28334 #define CRYPTO_MEMORYMAP30_PHYSADDRMAP30_Pos (1UL)                  /*!< PHYSADDRMAP30 (Bit 1)                                 */
28335 #define CRYPTO_MEMORYMAP30_PHYSADDRMAP30_Msk (0x7feUL)              /*!< PHYSADDRMAP30 (Bitfield-Mask: 0x3ff)                  */
28336 /* ======================================================  MEMORYMAP31  ====================================================== */
28337 #define CRYPTO_MEMORYMAP31_PHYSADDRMAP31_Pos (1UL)                  /*!< PHYSADDRMAP31 (Bit 1)                                 */
28338 #define CRYPTO_MEMORYMAP31_PHYSADDRMAP31_Msk (0x7feUL)              /*!< PHYSADDRMAP31 (Bitfield-Mask: 0x3ff)                  */
28339 /* ========================================================  OPCODE  ========================================================= */
28340 #define CRYPTO_OPCODE_OPCODE_Pos          (27UL)                    /*!< OPCODE (Bit 27)                                       */
28341 #define CRYPTO_OPCODE_OPCODE_Msk          (0xf8000000UL)            /*!< OPCODE (Bitfield-Mask: 0x1f)                          */
28342 #define CRYPTO_OPCODE_LEN_Pos             (24UL)                    /*!< LEN (Bit 24)                                          */
28343 #define CRYPTO_OPCODE_LEN_Msk             (0x7000000UL)             /*!< LEN (Bitfield-Mask: 0x07)                             */
28344 #define CRYPTO_OPCODE_REGA_Pos            (18UL)                    /*!< REGA (Bit 18)                                         */
28345 #define CRYPTO_OPCODE_REGA_Msk            (0xfc0000UL)              /*!< REGA (Bitfield-Mask: 0x3f)                            */
28346 #define CRYPTO_OPCODE_REGB_Pos            (12UL)                    /*!< REGB (Bit 12)                                         */
28347 #define CRYPTO_OPCODE_REGB_Msk            (0x3f000UL)               /*!< REGB (Bitfield-Mask: 0x3f)                            */
28348 #define CRYPTO_OPCODE_REGR_Pos            (6UL)                     /*!< REGR (Bit 6)                                          */
28349 #define CRYPTO_OPCODE_REGR_Msk            (0xfc0UL)                 /*!< REGR (Bitfield-Mask: 0x3f)                            */
28350 #define CRYPTO_OPCODE_TAG_Pos             (0UL)                     /*!< TAG (Bit 0)                                           */
28351 #define CRYPTO_OPCODE_TAG_Msk             (0x3fUL)                  /*!< TAG (Bitfield-Mask: 0x3f)                             */
28352 /* ======================================================  NNPT0T1ADDR  ====================================================== */
28353 #define CRYPTO_NNPT0T1ADDR_T1VIRTUALADDR_Pos (15UL)                 /*!< T1VIRTUALADDR (Bit 15)                                */
28354 #define CRYPTO_NNPT0T1ADDR_T1VIRTUALADDR_Msk (0xf8000UL)            /*!< T1VIRTUALADDR (Bitfield-Mask: 0x1f)                   */
28355 #define CRYPTO_NNPT0T1ADDR_T0VIRTUALADDR_Pos (10UL)                 /*!< T0VIRTUALADDR (Bit 10)                                */
28356 #define CRYPTO_NNPT0T1ADDR_T0VIRTUALADDR_Msk (0x7c00UL)             /*!< T0VIRTUALADDR (Bitfield-Mask: 0x1f)                   */
28357 #define CRYPTO_NNPT0T1ADDR_NPVIRTUALADDR_Pos (5UL)                  /*!< NPVIRTUALADDR (Bit 5)                                 */
28358 #define CRYPTO_NNPT0T1ADDR_NPVIRTUALADDR_Msk (0x3e0UL)              /*!< NPVIRTUALADDR (Bitfield-Mask: 0x1f)                   */
28359 #define CRYPTO_NNPT0T1ADDR_NVIRTUALADDR_Pos (0UL)                   /*!< NVIRTUALADDR (Bit 0)                                  */
28360 #define CRYPTO_NNPT0T1ADDR_NVIRTUALADDR_Msk (0x1fUL)                /*!< NVIRTUALADDR (Bitfield-Mask: 0x1f)                    */
28361 /* =======================================================  PKASTATUS  ======================================================= */
28362 #define CRYPTO_PKASTATUS_OPCODE_Pos       (16UL)                    /*!< OPCODE (Bit 16)                                       */
28363 #define CRYPTO_PKASTATUS_OPCODE_Msk       (0x1f0000UL)              /*!< OPCODE (Bitfield-Mask: 0x1f)                          */
28364 #define CRYPTO_PKASTATUS_MODINVOFZERO_Pos (15UL)                    /*!< MODINVOFZERO (Bit 15)                                 */
28365 #define CRYPTO_PKASTATUS_MODINVOFZERO_Msk (0x8000UL)                /*!< MODINVOFZERO (Bitfield-Mask: 0x01)                    */
28366 #define CRYPTO_PKASTATUS_DIVBYZERO_Pos    (14UL)                    /*!< DIVBYZERO (Bit 14)                                    */
28367 #define CRYPTO_PKASTATUS_DIVBYZERO_Msk    (0x4000UL)                /*!< DIVBYZERO (Bitfield-Mask: 0x01)                       */
28368 #define CRYPTO_PKASTATUS_ALUMODOVRFLW_Pos (13UL)                    /*!< ALUMODOVRFLW (Bit 13)                                 */
28369 #define CRYPTO_PKASTATUS_ALUMODOVRFLW_Msk (0x2000UL)                /*!< ALUMODOVRFLW (Bitfield-Mask: 0x01)                    */
28370 #define CRYPTO_PKASTATUS_ALUOUTZERO_Pos   (12UL)                    /*!< ALUOUTZERO (Bit 12)                                   */
28371 #define CRYPTO_PKASTATUS_ALUOUTZERO_Msk   (0x1000UL)                /*!< ALUOUTZERO (Bitfield-Mask: 0x01)                      */
28372 #define CRYPTO_PKASTATUS_ALUSUBISZERO_Pos (11UL)                    /*!< ALUSUBISZERO (Bit 11)                                 */
28373 #define CRYPTO_PKASTATUS_ALUSUBISZERO_Msk (0x800UL)                 /*!< ALUSUBISZERO (Bitfield-Mask: 0x01)                    */
28374 #define CRYPTO_PKASTATUS_ALUCARRYMOD_Pos  (10UL)                    /*!< ALUCARRYMOD (Bit 10)                                  */
28375 #define CRYPTO_PKASTATUS_ALUCARRYMOD_Msk  (0x400UL)                 /*!< ALUCARRYMOD (Bitfield-Mask: 0x01)                     */
28376 #define CRYPTO_PKASTATUS_ALUCARRY_Pos     (9UL)                     /*!< ALUCARRY (Bit 9)                                      */
28377 #define CRYPTO_PKASTATUS_ALUCARRY_Msk     (0x200UL)                 /*!< ALUCARRY (Bitfield-Mask: 0x01)                        */
28378 #define CRYPTO_PKASTATUS_ALUSIGNOUT_Pos   (8UL)                     /*!< ALUSIGNOUT (Bit 8)                                    */
28379 #define CRYPTO_PKASTATUS_ALUSIGNOUT_Msk   (0x100UL)                 /*!< ALUSIGNOUT (Bitfield-Mask: 0x01)                      */
28380 #define CRYPTO_PKASTATUS_ALULSB4BITS_Pos  (4UL)                     /*!< ALULSB4BITS (Bit 4)                                   */
28381 #define CRYPTO_PKASTATUS_ALULSB4BITS_Msk  (0xf0UL)                  /*!< ALULSB4BITS (Bitfield-Mask: 0x0f)                     */
28382 #define CRYPTO_PKASTATUS_ALUMSB4BITS_Pos  (0UL)                     /*!< ALUMSB4BITS (Bit 0)                                   */
28383 #define CRYPTO_PKASTATUS_ALUMSB4BITS_Msk  (0xfUL)                   /*!< ALUMSB4BITS (Bitfield-Mask: 0x0f)                     */
28384 /* ======================================================  PKASWRESET  ======================================================= */
28385 #define CRYPTO_PKASWRESET_PKASWRESET_Pos  (0UL)                     /*!< PKASWRESET (Bit 0)                                    */
28386 #define CRYPTO_PKASWRESET_PKASWRESET_Msk  (0x1UL)                   /*!< PKASWRESET (Bitfield-Mask: 0x01)                      */
28387 /* =========================================================  PKAL0  ========================================================= */
28388 #define CRYPTO_PKAL0_PKAL0_Pos            (0UL)                     /*!< PKAL0 (Bit 0)                                         */
28389 #define CRYPTO_PKAL0_PKAL0_Msk            (0x1fffUL)                /*!< PKAL0 (Bitfield-Mask: 0x1fff)                         */
28390 /* =========================================================  PKAL1  ========================================================= */
28391 #define CRYPTO_PKAL1_PKAL1_Pos            (0UL)                     /*!< PKAL1 (Bit 0)                                         */
28392 #define CRYPTO_PKAL1_PKAL1_Msk            (0x1fffUL)                /*!< PKAL1 (Bitfield-Mask: 0x1fff)                         */
28393 /* =========================================================  PKAL2  ========================================================= */
28394 #define CRYPTO_PKAL2_PKAL2_Pos            (0UL)                     /*!< PKAL2 (Bit 0)                                         */
28395 #define CRYPTO_PKAL2_PKAL2_Msk            (0x1fffUL)                /*!< PKAL2 (Bitfield-Mask: 0x1fff)                         */
28396 /* =========================================================  PKAL3  ========================================================= */
28397 #define CRYPTO_PKAL3_PKAL3_Pos            (0UL)                     /*!< PKAL3 (Bit 0)                                         */
28398 #define CRYPTO_PKAL3_PKAL3_Msk            (0x1fffUL)                /*!< PKAL3 (Bitfield-Mask: 0x1fff)                         */
28399 /* =========================================================  PKAL4  ========================================================= */
28400 #define CRYPTO_PKAL4_PKAL4_Pos            (0UL)                     /*!< PKAL4 (Bit 0)                                         */
28401 #define CRYPTO_PKAL4_PKAL4_Msk            (0x1fffUL)                /*!< PKAL4 (Bitfield-Mask: 0x1fff)                         */
28402 /* =========================================================  PKAL5  ========================================================= */
28403 #define CRYPTO_PKAL5_PKAL5_Pos            (0UL)                     /*!< PKAL5 (Bit 0)                                         */
28404 #define CRYPTO_PKAL5_PKAL5_Msk            (0x1fffUL)                /*!< PKAL5 (Bitfield-Mask: 0x1fff)                         */
28405 /* =========================================================  PKAL6  ========================================================= */
28406 #define CRYPTO_PKAL6_PKAL6_Pos            (0UL)                     /*!< PKAL6 (Bit 0)                                         */
28407 #define CRYPTO_PKAL6_PKAL6_Msk            (0x1fffUL)                /*!< PKAL6 (Bitfield-Mask: 0x1fff)                         */
28408 /* =========================================================  PKAL7  ========================================================= */
28409 #define CRYPTO_PKAL7_PKAL7_Pos            (0UL)                     /*!< PKAL7 (Bit 0)                                         */
28410 #define CRYPTO_PKAL7_PKAL7_Msk            (0x1fffUL)                /*!< PKAL7 (Bitfield-Mask: 0x1fff)                         */
28411 /* ======================================================  PKAPIPERDY  ======================================================= */
28412 #define CRYPTO_PKAPIPERDY_PKAPIPERDY_Pos  (0UL)                     /*!< PKAPIPERDY (Bit 0)                                    */
28413 #define CRYPTO_PKAPIPERDY_PKAPIPERDY_Msk  (0x1UL)                   /*!< PKAPIPERDY (Bitfield-Mask: 0x01)                      */
28414 /* ========================================================  PKADONE  ======================================================== */
28415 #define CRYPTO_PKADONE_PKADONE_Pos        (0UL)                     /*!< PKADONE (Bit 0)                                       */
28416 #define CRYPTO_PKADONE_PKADONE_Msk        (0x1UL)                   /*!< PKADONE (Bitfield-Mask: 0x01)                         */
28417 /* =====================================================  PKAMONSELECT  ====================================================== */
28418 #define CRYPTO_PKAMONSELECT_PKAMONSELECT_Pos (0UL)                  /*!< PKAMONSELECT (Bit 0)                                  */
28419 #define CRYPTO_PKAMONSELECT_PKAMONSELECT_Msk (0xfUL)                /*!< PKAMONSELECT (Bitfield-Mask: 0x0f)                    */
28420 /* ======================================================  PKAVERSION  ======================================================= */
28421 #define CRYPTO_PKAVERSION_PKAVERSION_Pos  (0UL)                     /*!< PKAVERSION (Bit 0)                                    */
28422 #define CRYPTO_PKAVERSION_PKAVERSION_Msk  (0xffffffffUL)            /*!< PKAVERSION (Bitfield-Mask: 0xffffffff)                */
28423 /* ======================================================  PKAMONREAD  ======================================================= */
28424 #define CRYPTO_PKAMONREAD_PKAMONREAD_Pos  (0UL)                     /*!< PKAMONREAD (Bit 0)                                    */
28425 #define CRYPTO_PKAMONREAD_PKAMONREAD_Msk  (0xffffffffUL)            /*!< PKAMONREAD (Bitfield-Mask: 0xffffffff)                */
28426 /* ======================================================  PKASRAMADDR  ====================================================== */
28427 #define CRYPTO_PKASRAMADDR_PKASRAMADDR_Pos (0UL)                    /*!< PKASRAMADDR (Bit 0)                                   */
28428 #define CRYPTO_PKASRAMADDR_PKASRAMADDR_Msk (0xffffffffUL)           /*!< PKASRAMADDR (Bitfield-Mask: 0xffffffff)               */
28429 /* =====================================================  PKASRAMWDATA  ====================================================== */
28430 #define CRYPTO_PKASRAMWDATA_PKASRAMWDATA_Pos (0UL)                  /*!< PKASRAMWDATA (Bit 0)                                  */
28431 #define CRYPTO_PKASRAMWDATA_PKASRAMWDATA_Msk (0xffffffffUL)         /*!< PKASRAMWDATA (Bitfield-Mask: 0xffffffff)              */
28432 /* =====================================================  PKASRAMRDATA  ====================================================== */
28433 #define CRYPTO_PKASRAMRDATA_PKASRAMRDATA_Pos (0UL)                  /*!< PKASRAMRDATA (Bit 0)                                  */
28434 #define CRYPTO_PKASRAMRDATA_PKASRAMRDATA_Msk (0xffffffffUL)         /*!< PKASRAMRDATA (Bitfield-Mask: 0xffffffff)              */
28435 /* =====================================================  PKASRAMWRCLR  ====================================================== */
28436 #define CRYPTO_PKASRAMWRCLR_PKASRAMWRCLR_Pos (0UL)                  /*!< PKASRAMWRCLR (Bit 0)                                  */
28437 #define CRYPTO_PKASRAMWRCLR_PKASRAMWRCLR_Msk (0xffffffffUL)         /*!< PKASRAMWRCLR (Bitfield-Mask: 0xffffffff)              */
28438 /* =====================================================  PKASRAMRADDR  ====================================================== */
28439 #define CRYPTO_PKASRAMRADDR_PKASRAMRADDR_Pos (0UL)                  /*!< PKASRAMRADDR (Bit 0)                                  */
28440 #define CRYPTO_PKASRAMRADDR_PKASRAMRADDR_Msk (0xffffffffUL)         /*!< PKASRAMRADDR (Bitfield-Mask: 0xffffffff)              */
28441 /* =====================================================  PKAWORDACCESS  ===================================================== */
28442 #define CRYPTO_PKAWORDACCESS_PKAWORDACCESS_Pos (0UL)                /*!< PKAWORDACCESS (Bit 0)                                 */
28443 #define CRYPTO_PKAWORDACCESS_PKAWORDACCESS_Msk (0xffffffffUL)       /*!< PKAWORDACCESS (Bitfield-Mask: 0xffffffff)             */
28444 /* ======================================================  PKABUFFADDR  ====================================================== */
28445 #define CRYPTO_PKABUFFADDR_PKABUFADDR_Pos (0UL)                     /*!< PKABUFADDR (Bit 0)                                    */
28446 #define CRYPTO_PKABUFFADDR_PKABUFADDR_Msk (0xfffUL)                 /*!< PKABUFADDR (Bitfield-Mask: 0xfff)                     */
28447 /* ========================================================  RNGIMR  ========================================================= */
28448 #define CRYPTO_RNGIMR_RNGDMADONEINT_Pos   (5UL)                     /*!< RNGDMADONEINT (Bit 5)                                 */
28449 #define CRYPTO_RNGIMR_RNGDMADONEINT_Msk   (0x20UL)                  /*!< RNGDMADONEINT (Bitfield-Mask: 0x01)                   */
28450 #define CRYPTO_RNGIMR_WATCHDOGINTMASK_Pos (4UL)                     /*!< WATCHDOGINTMASK (Bit 4)                               */
28451 #define CRYPTO_RNGIMR_WATCHDOGINTMASK_Msk (0x10UL)                  /*!< WATCHDOGINTMASK (Bitfield-Mask: 0x01)                 */
28452 #define CRYPTO_RNGIMR_VNERRINTMASK_Pos    (3UL)                     /*!< VNERRINTMASK (Bit 3)                                  */
28453 #define CRYPTO_RNGIMR_VNERRINTMASK_Msk    (0x8UL)                   /*!< VNERRINTMASK (Bitfield-Mask: 0x01)                    */
28454 #define CRYPTO_RNGIMR_CRNGTERRINTMASK_Pos (2UL)                     /*!< CRNGTERRINTMASK (Bit 2)                               */
28455 #define CRYPTO_RNGIMR_CRNGTERRINTMASK_Msk (0x4UL)                   /*!< CRNGTERRINTMASK (Bitfield-Mask: 0x01)                 */
28456 #define CRYPTO_RNGIMR_AUTOCORRERRINTMASK_Pos (1UL)                  /*!< AUTOCORRERRINTMASK (Bit 1)                            */
28457 #define CRYPTO_RNGIMR_AUTOCORRERRINTMASK_Msk (0x2UL)                /*!< AUTOCORRERRINTMASK (Bitfield-Mask: 0x01)              */
28458 #define CRYPTO_RNGIMR_EHRVALIDINTMASK_Pos (0UL)                     /*!< EHRVALIDINTMASK (Bit 0)                               */
28459 #define CRYPTO_RNGIMR_EHRVALIDINTMASK_Msk (0x1UL)                   /*!< EHRVALIDINTMASK (Bitfield-Mask: 0x01)                 */
28460 /* ========================================================  RNGISR  ========================================================= */
28461 #define CRYPTO_RNGISR_WHICHKATERR_Pos     (25UL)                    /*!< WHICHKATERR (Bit 25)                                  */
28462 #define CRYPTO_RNGISR_WHICHKATERR_Msk     (0x6000000UL)             /*!< WHICHKATERR (Bitfield-Mask: 0x03)                     */
28463 #define CRYPTO_RNGISR_KATERR_Pos          (24UL)                    /*!< KATERR (Bit 24)                                       */
28464 #define CRYPTO_RNGISR_KATERR_Msk          (0x1000000UL)             /*!< KATERR (Bitfield-Mask: 0x01)                          */
28465 #define CRYPTO_RNGISR_REQSIZE_Pos         (23UL)                    /*!< REQSIZE (Bit 23)                                      */
28466 #define CRYPTO_RNGISR_REQSIZE_Msk         (0x800000UL)              /*!< REQSIZE (Bitfield-Mask: 0x01)                         */
28467 #define CRYPTO_RNGISR_PRNGCRNGTERR_Pos    (22UL)                    /*!< PRNGCRNGTERR (Bit 22)                                 */
28468 #define CRYPTO_RNGISR_PRNGCRNGTERR_Msk    (0x400000UL)              /*!< PRNGCRNGTERR (Bitfield-Mask: 0x01)                    */
28469 #define CRYPTO_RNGISR_RESEEDCNTRTOP40_Pos (21UL)                    /*!< RESEEDCNTRTOP40 (Bit 21)                              */
28470 #define CRYPTO_RNGISR_RESEEDCNTRTOP40_Msk (0x200000UL)              /*!< RESEEDCNTRTOP40 (Bitfield-Mask: 0x01)                 */
28471 #define CRYPTO_RNGISR_RESEEDCNTRFULL_Pos  (20UL)                    /*!< RESEEDCNTRFULL (Bit 20)                               */
28472 #define CRYPTO_RNGISR_RESEEDCNTRFULL_Msk  (0x100000UL)              /*!< RESEEDCNTRFULL (Bitfield-Mask: 0x01)                  */
28473 #define CRYPTO_RNGISR_OUTPUTREADY_Pos     (19UL)                    /*!< OUTPUTREADY (Bit 19)                                  */
28474 #define CRYPTO_RNGISR_OUTPUTREADY_Msk     (0x80000UL)               /*!< OUTPUTREADY (Bitfield-Mask: 0x01)                     */
28475 #define CRYPTO_RNGISR_FINALUPDATEDONE_Pos (18UL)                    /*!< FINALUPDATEDONE (Bit 18)                              */
28476 #define CRYPTO_RNGISR_FINALUPDATEDONE_Msk (0x40000UL)               /*!< FINALUPDATEDONE (Bitfield-Mask: 0x01)                 */
28477 #define CRYPTO_RNGISR_INSTANTIATIONDONE_Pos (17UL)                  /*!< INSTANTIATIONDONE (Bit 17)                            */
28478 #define CRYPTO_RNGISR_INSTANTIATIONDONE_Msk (0x20000UL)             /*!< INSTANTIATIONDONE (Bitfield-Mask: 0x01)               */
28479 #define CRYPTO_RNGISR_RESEEDINGDONE_Pos   (16UL)                    /*!< RESEEDINGDONE (Bit 16)                                */
28480 #define CRYPTO_RNGISR_RESEEDINGDONE_Msk   (0x10000UL)               /*!< RESEEDINGDONE (Bitfield-Mask: 0x01)                   */
28481 #define CRYPTO_RNGISR_RNGDMADONE_Pos      (5UL)                     /*!< RNGDMADONE (Bit 5)                                    */
28482 #define CRYPTO_RNGISR_RNGDMADONE_Msk      (0x20UL)                  /*!< RNGDMADONE (Bitfield-Mask: 0x01)                      */
28483 #define CRYPTO_RNGISR_VNERR_Pos           (3UL)                     /*!< VNERR (Bit 3)                                         */
28484 #define CRYPTO_RNGISR_VNERR_Msk           (0x8UL)                   /*!< VNERR (Bitfield-Mask: 0x01)                           */
28485 #define CRYPTO_RNGISR_CRNGTERR_Pos        (2UL)                     /*!< CRNGTERR (Bit 2)                                      */
28486 #define CRYPTO_RNGISR_CRNGTERR_Msk        (0x4UL)                   /*!< CRNGTERR (Bitfield-Mask: 0x01)                        */
28487 #define CRYPTO_RNGISR_AUTOCORRERR_Pos     (1UL)                     /*!< AUTOCORRERR (Bit 1)                                   */
28488 #define CRYPTO_RNGISR_AUTOCORRERR_Msk     (0x2UL)                   /*!< AUTOCORRERR (Bitfield-Mask: 0x01)                     */
28489 #define CRYPTO_RNGISR_EHRVALID_Pos        (0UL)                     /*!< EHRVALID (Bit 0)                                      */
28490 #define CRYPTO_RNGISR_EHRVALID_Msk        (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
28491 /* ========================================================  RNGICR  ========================================================= */
28492 #define CRYPTO_RNGICR_WHICHKATERR_Pos     (25UL)                    /*!< WHICHKATERR (Bit 25)                                  */
28493 #define CRYPTO_RNGICR_WHICHKATERR_Msk     (0x6000000UL)             /*!< WHICHKATERR (Bitfield-Mask: 0x03)                     */
28494 #define CRYPTO_RNGICR_KATERR_Pos          (24UL)                    /*!< KATERR (Bit 24)                                       */
28495 #define CRYPTO_RNGICR_KATERR_Msk          (0x1000000UL)             /*!< KATERR (Bitfield-Mask: 0x01)                          */
28496 #define CRYPTO_RNGICR_REQSIZE_Pos         (23UL)                    /*!< REQSIZE (Bit 23)                                      */
28497 #define CRYPTO_RNGICR_REQSIZE_Msk         (0x800000UL)              /*!< REQSIZE (Bitfield-Mask: 0x01)                         */
28498 #define CRYPTO_RNGICR_PRNGCRNGTERR_Pos    (22UL)                    /*!< PRNGCRNGTERR (Bit 22)                                 */
28499 #define CRYPTO_RNGICR_PRNGCRNGTERR_Msk    (0x400000UL)              /*!< PRNGCRNGTERR (Bitfield-Mask: 0x01)                    */
28500 #define CRYPTO_RNGICR_RESEEDCNTRTOP40_Pos (21UL)                    /*!< RESEEDCNTRTOP40 (Bit 21)                              */
28501 #define CRYPTO_RNGICR_RESEEDCNTRTOP40_Msk (0x200000UL)              /*!< RESEEDCNTRTOP40 (Bitfield-Mask: 0x01)                 */
28502 #define CRYPTO_RNGICR_RESEEDCNTRFULL_Pos  (20UL)                    /*!< RESEEDCNTRFULL (Bit 20)                               */
28503 #define CRYPTO_RNGICR_RESEEDCNTRFULL_Msk  (0x100000UL)              /*!< RESEEDCNTRFULL (Bitfield-Mask: 0x01)                  */
28504 #define CRYPTO_RNGICR_OUTPUTREADY_Pos     (19UL)                    /*!< OUTPUTREADY (Bit 19)                                  */
28505 #define CRYPTO_RNGICR_OUTPUTREADY_Msk     (0x80000UL)               /*!< OUTPUTREADY (Bitfield-Mask: 0x01)                     */
28506 #define CRYPTO_RNGICR_FINALUPDATEDONE_Pos (18UL)                    /*!< FINALUPDATEDONE (Bit 18)                              */
28507 #define CRYPTO_RNGICR_FINALUPDATEDONE_Msk (0x40000UL)               /*!< FINALUPDATEDONE (Bitfield-Mask: 0x01)                 */
28508 #define CRYPTO_RNGICR_INSTANTIATIONDONE_Pos (17UL)                  /*!< INSTANTIATIONDONE (Bit 17)                            */
28509 #define CRYPTO_RNGICR_INSTANTIATIONDONE_Msk (0x20000UL)             /*!< INSTANTIATIONDONE (Bitfield-Mask: 0x01)               */
28510 #define CRYPTO_RNGICR_RESEEDINGDONE_Pos   (16UL)                    /*!< RESEEDINGDONE (Bit 16)                                */
28511 #define CRYPTO_RNGICR_RESEEDINGDONE_Msk   (0x10000UL)               /*!< RESEEDINGDONE (Bitfield-Mask: 0x01)                   */
28512 #define CRYPTO_RNGICR_RNGDMADONE_Pos      (5UL)                     /*!< RNGDMADONE (Bit 5)                                    */
28513 #define CRYPTO_RNGICR_RNGDMADONE_Msk      (0x20UL)                  /*!< RNGDMADONE (Bitfield-Mask: 0x01)                      */
28514 #define CRYPTO_RNGICR_RNGWATCHDOG_Pos     (4UL)                     /*!< RNGWATCHDOG (Bit 4)                                   */
28515 #define CRYPTO_RNGICR_RNGWATCHDOG_Msk     (0x10UL)                  /*!< RNGWATCHDOG (Bitfield-Mask: 0x01)                     */
28516 #define CRYPTO_RNGICR_VNERR_Pos           (3UL)                     /*!< VNERR (Bit 3)                                         */
28517 #define CRYPTO_RNGICR_VNERR_Msk           (0x8UL)                   /*!< VNERR (Bitfield-Mask: 0x01)                           */
28518 #define CRYPTO_RNGICR_CRNGTERR_Pos        (2UL)                     /*!< CRNGTERR (Bit 2)                                      */
28519 #define CRYPTO_RNGICR_CRNGTERR_Msk        (0x4UL)                   /*!< CRNGTERR (Bitfield-Mask: 0x01)                        */
28520 #define CRYPTO_RNGICR_AUTOCORRERR_Pos     (1UL)                     /*!< AUTOCORRERR (Bit 1)                                   */
28521 #define CRYPTO_RNGICR_AUTOCORRERR_Msk     (0x2UL)                   /*!< AUTOCORRERR (Bitfield-Mask: 0x01)                     */
28522 #define CRYPTO_RNGICR_EHRVALID_Pos        (0UL)                     /*!< EHRVALID (Bit 0)                                      */
28523 #define CRYPTO_RNGICR_EHRVALID_Msk        (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
28524 /* ======================================================  TRNGCONFIG  ======================================================= */
28525 #define CRYPTO_TRNGCONFIG_SOPSEL_Pos      (2UL)                     /*!< SOPSEL (Bit 2)                                        */
28526 #define CRYPTO_TRNGCONFIG_SOPSEL_Msk      (0x4UL)                   /*!< SOPSEL (Bitfield-Mask: 0x01)                          */
28527 #define CRYPTO_TRNGCONFIG_RNDSRCSEL_Pos   (0UL)                     /*!< RNDSRCSEL (Bit 0)                                     */
28528 #define CRYPTO_TRNGCONFIG_RNDSRCSEL_Msk   (0x3UL)                   /*!< RNDSRCSEL (Bitfield-Mask: 0x03)                       */
28529 /* =======================================================  TRNGVALID  ======================================================= */
28530 #define CRYPTO_TRNGVALID_EHRVALID_Pos     (0UL)                     /*!< EHRVALID (Bit 0)                                      */
28531 #define CRYPTO_TRNGVALID_EHRVALID_Msk     (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
28532 /* =======================================================  EHRDATA0  ======================================================== */
28533 #define CRYPTO_EHRDATA0_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
28534 #define CRYPTO_EHRDATA0_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
28535 /* =======================================================  EHRDATA1  ======================================================== */
28536 #define CRYPTO_EHRDATA1_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
28537 #define CRYPTO_EHRDATA1_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
28538 /* =======================================================  EHRDATA2  ======================================================== */
28539 #define CRYPTO_EHRDATA2_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
28540 #define CRYPTO_EHRDATA2_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
28541 /* =======================================================  EHRDATA3  ======================================================== */
28542 #define CRYPTO_EHRDATA3_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
28543 #define CRYPTO_EHRDATA3_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
28544 /* =======================================================  EHRDATA4  ======================================================== */
28545 #define CRYPTO_EHRDATA4_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
28546 #define CRYPTO_EHRDATA4_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
28547 /* =======================================================  EHRDATA5  ======================================================== */
28548 #define CRYPTO_EHRDATA5_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
28549 #define CRYPTO_EHRDATA5_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
28550 /* ====================================================  RNDSOURCEENABLE  ==================================================== */
28551 #define CRYPTO_RNDSOURCEENABLE_RNDSRCEN_Pos (0UL)                   /*!< RNDSRCEN (Bit 0)                                      */
28552 #define CRYPTO_RNDSOURCEENABLE_RNDSRCEN_Msk (0x1UL)                 /*!< RNDSRCEN (Bitfield-Mask: 0x01)                        */
28553 /* ======================================================  SAMPLECNT1  ======================================================= */
28554 #define CRYPTO_SAMPLECNT1_SAMPLECNTR1_Pos (0UL)                     /*!< SAMPLECNTR1 (Bit 0)                                   */
28555 #define CRYPTO_SAMPLECNT1_SAMPLECNTR1_Msk (0xffffffffUL)            /*!< SAMPLECNTR1 (Bitfield-Mask: 0xffffffff)               */
28556 /* ===================================================  AUTOCORRSTATISTIC  =================================================== */
28557 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRFAILS_Pos (14UL)           /*!< AUTOCORRFAILS (Bit 14)                                */
28558 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRFAILS_Msk (0x3fc000UL)     /*!< AUTOCORRFAILS (Bitfield-Mask: 0xff)                   */
28559 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRTRYS_Pos (0UL)             /*!< AUTOCORRTRYS (Bit 0)                                  */
28560 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRTRYS_Msk (0x3fffUL)        /*!< AUTOCORRTRYS (Bitfield-Mask: 0x3fff)                  */
28561 /* ===================================================  TRNGDEBUGCONTROL  ==================================================== */
28562 #define CRYPTO_TRNGDEBUGCONTROL_AUTOCORRELATEBYPASS_Pos (3UL)       /*!< AUTOCORRELATEBYPASS (Bit 3)                           */
28563 #define CRYPTO_TRNGDEBUGCONTROL_AUTOCORRELATEBYPASS_Msk (0x8UL)     /*!< AUTOCORRELATEBYPASS (Bitfield-Mask: 0x01)             */
28564 #define CRYPTO_TRNGDEBUGCONTROL_TRNGCRNGTBYPASS_Pos (2UL)           /*!< TRNGCRNGTBYPASS (Bit 2)                               */
28565 #define CRYPTO_TRNGDEBUGCONTROL_TRNGCRNGTBYPASS_Msk (0x4UL)         /*!< TRNGCRNGTBYPASS (Bitfield-Mask: 0x01)                 */
28566 #define CRYPTO_TRNGDEBUGCONTROL_VNCBYPASS_Pos (1UL)                 /*!< VNCBYPASS (Bit 1)                                     */
28567 #define CRYPTO_TRNGDEBUGCONTROL_VNCBYPASS_Msk (0x2UL)               /*!< VNCBYPASS (Bitfield-Mask: 0x01)                       */
28568 /* ======================================================  RNGSWRESET  ======================================================= */
28569 #define CRYPTO_RNGSWRESET_RNGSWRESET_Pos  (0UL)                     /*!< RNGSWRESET (Bit 0)                                    */
28570 #define CRYPTO_RNGSWRESET_RNGSWRESET_Msk  (0x1UL)                   /*!< RNGSWRESET (Bitfield-Mask: 0x01)                      */
28571 /* ====================================================  RNGDEBUGENINPUT  ==================================================== */
28572 #define CRYPTO_RNGDEBUGENINPUT_RNGDEBUGEN_Pos (0UL)                 /*!< RNGDEBUGEN (Bit 0)                                    */
28573 #define CRYPTO_RNGDEBUGENINPUT_RNGDEBUGEN_Msk (0x1UL)               /*!< RNGDEBUGEN (Bitfield-Mask: 0x01)                      */
28574 /* ========================================================  RNGBUSY  ======================================================== */
28575 #define CRYPTO_RNGBUSY_PRNGBUSY_Pos       (2UL)                     /*!< PRNGBUSY (Bit 2)                                      */
28576 #define CRYPTO_RNGBUSY_PRNGBUSY_Msk       (0x4UL)                   /*!< PRNGBUSY (Bitfield-Mask: 0x01)                        */
28577 #define CRYPTO_RNGBUSY_TRNGBUSY_Pos       (1UL)                     /*!< TRNGBUSY (Bit 1)                                      */
28578 #define CRYPTO_RNGBUSY_TRNGBUSY_Msk       (0x2UL)                   /*!< TRNGBUSY (Bitfield-Mask: 0x01)                        */
28579 #define CRYPTO_RNGBUSY_RNGBUSY_Pos        (0UL)                     /*!< RNGBUSY (Bit 0)                                       */
28580 #define CRYPTO_RNGBUSY_RNGBUSY_Msk        (0x1UL)                   /*!< RNGBUSY (Bitfield-Mask: 0x01)                         */
28581 /* ====================================================  RSTBITSCOUNTER  ===================================================== */
28582 #define CRYPTO_RSTBITSCOUNTER_RSTBITSCOUNTER_Pos (0UL)              /*!< RSTBITSCOUNTER (Bit 0)                                */
28583 #define CRYPTO_RSTBITSCOUNTER_RSTBITSCOUNTER_Msk (0x1UL)            /*!< RSTBITSCOUNTER (Bitfield-Mask: 0x01)                  */
28584 /* ======================================================  RNGVERSION  ======================================================= */
28585 #define CRYPTO_RNGVERSION_RNGUSE5SBOXES_Pos (7UL)                   /*!< RNGUSE5SBOXES (Bit 7)                                 */
28586 #define CRYPTO_RNGVERSION_RNGUSE5SBOXES_Msk (0x80UL)                /*!< RNGUSE5SBOXES (Bitfield-Mask: 0x01)                   */
28587 #define CRYPTO_RNGVERSION_RESEEDINGEXISTS_Pos (6UL)                 /*!< RESEEDINGEXISTS (Bit 6)                               */
28588 #define CRYPTO_RNGVERSION_RESEEDINGEXISTS_Msk (0x40UL)              /*!< RESEEDINGEXISTS (Bitfield-Mask: 0x01)                 */
28589 #define CRYPTO_RNGVERSION_KATEXISTS_Pos   (5UL)                     /*!< KATEXISTS (Bit 5)                                     */
28590 #define CRYPTO_RNGVERSION_KATEXISTS_Msk   (0x20UL)                  /*!< KATEXISTS (Bitfield-Mask: 0x01)                       */
28591 #define CRYPTO_RNGVERSION_PRNGEXISTS_Pos  (4UL)                     /*!< PRNGEXISTS (Bit 4)                                    */
28592 #define CRYPTO_RNGVERSION_PRNGEXISTS_Msk  (0x10UL)                  /*!< PRNGEXISTS (Bitfield-Mask: 0x01)                      */
28593 #define CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Pos (3UL)               /*!< TRNGTESTSBYPASSEN (Bit 3)                             */
28594 #define CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Msk (0x8UL)             /*!< TRNGTESTSBYPASSEN (Bitfield-Mask: 0x01)               */
28595 #define CRYPTO_RNGVERSION_AUTOCORREXISTS_Pos (2UL)                  /*!< AUTOCORREXISTS (Bit 2)                                */
28596 #define CRYPTO_RNGVERSION_AUTOCORREXISTS_Msk (0x4UL)                /*!< AUTOCORREXISTS (Bitfield-Mask: 0x01)                  */
28597 #define CRYPTO_RNGVERSION_CRNGTEXISTS_Pos (1UL)                     /*!< CRNGTEXISTS (Bit 1)                                   */
28598 #define CRYPTO_RNGVERSION_CRNGTEXISTS_Msk (0x2UL)                   /*!< CRNGTEXISTS (Bitfield-Mask: 0x01)                     */
28599 #define CRYPTO_RNGVERSION_EHRWIDTH192_Pos (0UL)                     /*!< EHRWIDTH192 (Bit 0)                                   */
28600 #define CRYPTO_RNGVERSION_EHRWIDTH192_Msk (0x1UL)                   /*!< EHRWIDTH192 (Bitfield-Mask: 0x01)                     */
28601 /* =====================================================  RNGCLKENABLE  ====================================================== */
28602 #define CRYPTO_RNGCLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
28603 #define CRYPTO_RNGCLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
28604 /* =====================================================  RNGDMAENABLE  ====================================================== */
28605 #define CRYPTO_RNGDMAENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
28606 #define CRYPTO_RNGDMAENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
28607 /* =====================================================  RNGDMASRCMASK  ===================================================== */
28608 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL3_Pos (3UL)                    /*!< ENSRCSEL3 (Bit 3)                                     */
28609 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL3_Msk (0x8UL)                  /*!< ENSRCSEL3 (Bitfield-Mask: 0x01)                       */
28610 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL2_Pos (2UL)                    /*!< ENSRCSEL2 (Bit 2)                                     */
28611 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL2_Msk (0x4UL)                  /*!< ENSRCSEL2 (Bitfield-Mask: 0x01)                       */
28612 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL1_Pos (1UL)                    /*!< ENSRCSEL1 (Bit 1)                                     */
28613 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL1_Msk (0x2UL)                  /*!< ENSRCSEL1 (Bitfield-Mask: 0x01)                       */
28614 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL0_Pos (0UL)                    /*!< ENSRCSEL0 (Bit 0)                                     */
28615 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL0_Msk (0x1UL)                  /*!< ENSRCSEL0 (Bitfield-Mask: 0x01)                       */
28616 /* ====================================================  RNGDMASRAMADDR  ===================================================== */
28617 #define CRYPTO_RNGDMASRAMADDR_RNGSRAMDMAADDR_Pos (0UL)              /*!< RNGSRAMDMAADDR (Bit 0)                                */
28618 #define CRYPTO_RNGDMASRAMADDR_RNGSRAMDMAADDR_Msk (0x7ffUL)          /*!< RNGSRAMDMAADDR (Bitfield-Mask: 0x7ff)                 */
28619 /* ====================================================  RNGWATCHDOGVAL  ===================================================== */
28620 #define CRYPTO_RNGWATCHDOGVAL_RNGWATCHDOGVAL_Pos (0UL)              /*!< RNGWATCHDOGVAL (Bit 0)                                */
28621 #define CRYPTO_RNGWATCHDOGVAL_RNGWATCHDOGVAL_Msk (0xffffffffUL)     /*!< RNGWATCHDOGVAL (Bitfield-Mask: 0xffffffff)            */
28622 /* =====================================================  RNGDMASTATUS  ====================================================== */
28623 #define CRYPTO_RNGDMASTATUS_NUMOFSAMPLES_Pos (3UL)                  /*!< NUMOFSAMPLES (Bit 3)                                  */
28624 #define CRYPTO_RNGDMASTATUS_NUMOFSAMPLES_Msk (0x7f8UL)              /*!< NUMOFSAMPLES (Bitfield-Mask: 0xff)                    */
28625 #define CRYPTO_RNGDMASTATUS_DMASRCSEL_Pos (1UL)                     /*!< DMASRCSEL (Bit 1)                                     */
28626 #define CRYPTO_RNGDMASTATUS_DMASRCSEL_Msk (0x6UL)                   /*!< DMASRCSEL (Bitfield-Mask: 0x03)                       */
28627 #define CRYPTO_RNGDMASTATUS_RNGDMABUSY_Pos (0UL)                    /*!< RNGDMABUSY (Bit 0)                                    */
28628 #define CRYPTO_RNGDMASTATUS_RNGDMABUSY_Msk (0x1UL)                  /*!< RNGDMABUSY (Bitfield-Mask: 0x01)                      */
28629 /* ===================================================  CHACHACONTROLREG  ==================================================== */
28630 #define CRYPTO_CHACHACONTROLREG_USEIV96BIT_Pos (10UL)               /*!< USEIV96BIT (Bit 10)                                   */
28631 #define CRYPTO_CHACHACONTROLREG_USEIV96BIT_Msk (0x400UL)            /*!< USEIV96BIT (Bitfield-Mask: 0x01)                      */
28632 #define CRYPTO_CHACHACONTROLREG_RESETBLOCKCNT_Pos (9UL)             /*!< RESETBLOCKCNT (Bit 9)                                 */
28633 #define CRYPTO_CHACHACONTROLREG_RESETBLOCKCNT_Msk (0x200UL)         /*!< RESETBLOCKCNT (Bitfield-Mask: 0x01)                   */
28634 #define CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Pos (4UL)               /*!< NUMOFROUNDS (Bit 4)                                   */
28635 #define CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Msk (0x30UL)            /*!< NUMOFROUNDS (Bitfield-Mask: 0x03)                     */
28636 #define CRYPTO_CHACHACONTROLREG_KEYLEN_Pos (3UL)                    /*!< KEYLEN (Bit 3)                                        */
28637 #define CRYPTO_CHACHACONTROLREG_KEYLEN_Msk (0x8UL)                  /*!< KEYLEN (Bitfield-Mask: 0x01)                          */
28638 #define CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Pos (2UL)        /*!< CALCKEYFORPOLY1305 (Bit 2)                            */
28639 #define CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Msk (0x4UL)      /*!< CALCKEYFORPOLY1305 (Bitfield-Mask: 0x01)              */
28640 #define CRYPTO_CHACHACONTROLREG_INITFROMHOST_Pos (1UL)              /*!< INITFROMHOST (Bit 1)                                  */
28641 #define CRYPTO_CHACHACONTROLREG_INITFROMHOST_Msk (0x2UL)            /*!< INITFROMHOST (Bitfield-Mask: 0x01)                    */
28642 #define CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Pos (0UL)             /*!< CHACHAORSALSA (Bit 0)                                 */
28643 #define CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Msk (0x1UL)           /*!< CHACHAORSALSA (Bitfield-Mask: 0x01)                   */
28644 /* =====================================================  CHACHAVERSION  ===================================================== */
28645 #define CRYPTO_CHACHAVERSION_CHACHAVERSION_Pos (0UL)                /*!< CHACHAVERSION (Bit 0)                                 */
28646 #define CRYPTO_CHACHAVERSION_CHACHAVERSION_Msk (0xffffffffUL)       /*!< CHACHAVERSION (Bitfield-Mask: 0xffffffff)             */
28647 /* ======================================================  CHACHAKEY0  ======================================================= */
28648 #define CRYPTO_CHACHAKEY0_CHACHAKEY0_Pos  (0UL)                     /*!< CHACHAKEY0 (Bit 0)                                    */
28649 #define CRYPTO_CHACHAKEY0_CHACHAKEY0_Msk  (0xffffffffUL)            /*!< CHACHAKEY0 (Bitfield-Mask: 0xffffffff)                */
28650 /* ======================================================  CHACHAKEY1  ======================================================= */
28651 #define CRYPTO_CHACHAKEY1_CHACHAKEY1_Pos  (0UL)                     /*!< CHACHAKEY1 (Bit 0)                                    */
28652 #define CRYPTO_CHACHAKEY1_CHACHAKEY1_Msk  (0xffffffffUL)            /*!< CHACHAKEY1 (Bitfield-Mask: 0xffffffff)                */
28653 /* ======================================================  CHACHAKEY2  ======================================================= */
28654 #define CRYPTO_CHACHAKEY2_CHACHAKEY2_Pos  (0UL)                     /*!< CHACHAKEY2 (Bit 0)                                    */
28655 #define CRYPTO_CHACHAKEY2_CHACHAKEY2_Msk  (0xffffffffUL)            /*!< CHACHAKEY2 (Bitfield-Mask: 0xffffffff)                */
28656 /* ======================================================  CHACHAKEY3  ======================================================= */
28657 #define CRYPTO_CHACHAKEY3_CHACHAKEY3_Pos  (0UL)                     /*!< CHACHAKEY3 (Bit 0)                                    */
28658 #define CRYPTO_CHACHAKEY3_CHACHAKEY3_Msk  (0xffffffffUL)            /*!< CHACHAKEY3 (Bitfield-Mask: 0xffffffff)                */
28659 /* ======================================================  CHACHAKEY4  ======================================================= */
28660 #define CRYPTO_CHACHAKEY4_CHACHAKEY4_Pos  (0UL)                     /*!< CHACHAKEY4 (Bit 0)                                    */
28661 #define CRYPTO_CHACHAKEY4_CHACHAKEY4_Msk  (0xffffffffUL)            /*!< CHACHAKEY4 (Bitfield-Mask: 0xffffffff)                */
28662 /* ======================================================  CHACHAKEY5  ======================================================= */
28663 #define CRYPTO_CHACHAKEY5_CHACHAKEY5_Pos  (0UL)                     /*!< CHACHAKEY5 (Bit 0)                                    */
28664 #define CRYPTO_CHACHAKEY5_CHACHAKEY5_Msk  (0xffffffffUL)            /*!< CHACHAKEY5 (Bitfield-Mask: 0xffffffff)                */
28665 /* ======================================================  CHACHAKEY6  ======================================================= */
28666 #define CRYPTO_CHACHAKEY6_CHACHAKEY6_Pos  (0UL)                     /*!< CHACHAKEY6 (Bit 0)                                    */
28667 #define CRYPTO_CHACHAKEY6_CHACHAKEY6_Msk  (0xffffffffUL)            /*!< CHACHAKEY6 (Bitfield-Mask: 0xffffffff)                */
28668 /* ======================================================  CHACHAKEY7  ======================================================= */
28669 #define CRYPTO_CHACHAKEY7_CHACHAKEY7_Pos  (0UL)                     /*!< CHACHAKEY7 (Bit 0)                                    */
28670 #define CRYPTO_CHACHAKEY7_CHACHAKEY7_Msk  (0xffffffffUL)            /*!< CHACHAKEY7 (Bitfield-Mask: 0xffffffff)                */
28671 /* =======================================================  CHACHAIV0  ======================================================= */
28672 #define CRYPTO_CHACHAIV0_CHACHAIV0_Pos    (0UL)                     /*!< CHACHAIV0 (Bit 0)                                     */
28673 #define CRYPTO_CHACHAIV0_CHACHAIV0_Msk    (0xffffffffUL)            /*!< CHACHAIV0 (Bitfield-Mask: 0xffffffff)                 */
28674 /* =======================================================  CHACHAIV1  ======================================================= */
28675 #define CRYPTO_CHACHAIV1_CHACHAIV1_Pos    (0UL)                     /*!< CHACHAIV1 (Bit 0)                                     */
28676 #define CRYPTO_CHACHAIV1_CHACHAIV1_Msk    (0xffffffffUL)            /*!< CHACHAIV1 (Bitfield-Mask: 0xffffffff)                 */
28677 /* ======================================================  CHACHABUSY  ======================================================= */
28678 #define CRYPTO_CHACHABUSY_CHACHABUSY_Pos  (0UL)                     /*!< CHACHABUSY (Bit 0)                                    */
28679 #define CRYPTO_CHACHABUSY_CHACHABUSY_Msk  (0x1UL)                   /*!< CHACHABUSY (Bitfield-Mask: 0x01)                      */
28680 /* =====================================================  CHACHAHWFLAGS  ===================================================== */
28681 #define CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Pos (2UL)                   /*!< FASTCHACHA (Bit 2)                                    */
28682 #define CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Msk (0x4UL)                 /*!< FASTCHACHA (Bitfield-Mask: 0x01)                      */
28683 #define CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Pos (1UL)                  /*!< SALSAEXISTS (Bit 1)                                   */
28684 #define CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Msk (0x2UL)                /*!< SALSAEXISTS (Bitfield-Mask: 0x01)                     */
28685 #define CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Pos (0UL)                 /*!< CHACHAEXISTS (Bit 0)                                  */
28686 #define CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Msk (0x1UL)               /*!< CHACHAEXISTS (Bitfield-Mask: 0x01)                    */
28687 /* ===================================================  CHACHABLOCKCNTLSB  =================================================== */
28688 #define CRYPTO_CHACHABLOCKCNTLSB_CHACHABLOCKCNTLSB_Pos (0UL)        /*!< CHACHABLOCKCNTLSB (Bit 0)                             */
28689 #define CRYPTO_CHACHABLOCKCNTLSB_CHACHABLOCKCNTLSB_Msk (0xffffffffUL) /*!< CHACHABLOCKCNTLSB (Bitfield-Mask: 0xffffffff)       */
28690 /* ===================================================  CHACHABLOCKCNTMSB  =================================================== */
28691 #define CRYPTO_CHACHABLOCKCNTMSB_CHACHABLOCKCNTMSB_Pos (0UL)        /*!< CHACHABLOCKCNTMSB (Bit 0)                             */
28692 #define CRYPTO_CHACHABLOCKCNTMSB_CHACHABLOCKCNTMSB_Msk (0xffffffffUL) /*!< CHACHABLOCKCNTMSB (Bitfield-Mask: 0xffffffff)       */
28693 /* =====================================================  CHACHASWRESET  ===================================================== */
28694 #define CRYPTO_CHACHASWRESET_CHACHSWRESET_Pos (0UL)                 /*!< CHACHSWRESET (Bit 0)                                  */
28695 #define CRYPTO_CHACHASWRESET_CHACHSWRESET_Msk (0x1UL)               /*!< CHACHSWRESET (Bitfield-Mask: 0x01)                    */
28696 /* ===================================================  CHACHAFORPOLYKEY0  =================================================== */
28697 #define CRYPTO_CHACHAFORPOLYKEY0_CHACHAFORPOLYKEY0_Pos (0UL)        /*!< CHACHAFORPOLYKEY0 (Bit 0)                             */
28698 #define CRYPTO_CHACHAFORPOLYKEY0_CHACHAFORPOLYKEY0_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY0 (Bitfield-Mask: 0xffffffff)       */
28699 /* ===================================================  CHACHAFORPOLYKEY1  =================================================== */
28700 #define CRYPTO_CHACHAFORPOLYKEY1_CHACHAFORPOLYKEY1_Pos (0UL)        /*!< CHACHAFORPOLYKEY1 (Bit 0)                             */
28701 #define CRYPTO_CHACHAFORPOLYKEY1_CHACHAFORPOLYKEY1_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY1 (Bitfield-Mask: 0xffffffff)       */
28702 /* ===================================================  CHACHAFORPOLYKEY2  =================================================== */
28703 #define CRYPTO_CHACHAFORPOLYKEY2_CHACHAFORPOLYKEY2_Pos (0UL)        /*!< CHACHAFORPOLYKEY2 (Bit 0)                             */
28704 #define CRYPTO_CHACHAFORPOLYKEY2_CHACHAFORPOLYKEY2_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY2 (Bitfield-Mask: 0xffffffff)       */
28705 /* ===================================================  CHACHAFORPOLYKEY3  =================================================== */
28706 #define CRYPTO_CHACHAFORPOLYKEY3_CHACHAFORPOLYKEY3_Pos (0UL)        /*!< CHACHAFORPOLYKEY3 (Bit 0)                             */
28707 #define CRYPTO_CHACHAFORPOLYKEY3_CHACHAFORPOLYKEY3_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY3 (Bitfield-Mask: 0xffffffff)       */
28708 /* ===================================================  CHACHAFORPOLYKEY4  =================================================== */
28709 #define CRYPTO_CHACHAFORPOLYKEY4_CHACHAFORPOLYKEY4_Pos (0UL)        /*!< CHACHAFORPOLYKEY4 (Bit 0)                             */
28710 #define CRYPTO_CHACHAFORPOLYKEY4_CHACHAFORPOLYKEY4_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY4 (Bitfield-Mask: 0xffffffff)       */
28711 /* ===================================================  CHACHAFORPOLYKEY5  =================================================== */
28712 #define CRYPTO_CHACHAFORPOLYKEY5_CHACHAFORPOLYKEY5_Pos (0UL)        /*!< CHACHAFORPOLYKEY5 (Bit 0)                             */
28713 #define CRYPTO_CHACHAFORPOLYKEY5_CHACHAFORPOLYKEY5_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY5 (Bitfield-Mask: 0xffffffff)       */
28714 /* ===================================================  CHACHAFORPOLYKEY6  =================================================== */
28715 #define CRYPTO_CHACHAFORPOLYKEY6_CHACHAFORPOLYKEY6_Pos (0UL)        /*!< CHACHAFORPOLYKEY6 (Bit 0)                             */
28716 #define CRYPTO_CHACHAFORPOLYKEY6_CHACHAFORPOLYKEY6_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY6 (Bitfield-Mask: 0xffffffff)       */
28717 /* ===================================================  CHACHAFORPOLYKEY7  =================================================== */
28718 #define CRYPTO_CHACHAFORPOLYKEY7_CHACHAFORPOLYKEY7_Pos (0UL)        /*!< CHACHAFORPOLYKEY7 (Bit 0)                             */
28719 #define CRYPTO_CHACHAFORPOLYKEY7_CHACHAFORPOLYKEY7_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY7 (Bitfield-Mask: 0xffffffff)       */
28720 /* ==============================================  CHACHABYTEWORDORDERCNTLREG  =============================================== */
28721 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Pos (4UL) /*!< CHACHADOUTBYTEORDER (Bit 4)                       */
28722 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Msk (0x10UL) /*!< CHACHADOUTBYTEORDER (Bitfield-Mask: 0x01)      */
28723 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Pos (3UL) /*!< CHACHADOUTWORDORDER (Bit 3)                       */
28724 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Msk (0x8UL) /*!< CHACHADOUTWORDORDER (Bitfield-Mask: 0x01)       */
28725 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Pos (2UL) /*!< CHACHACOREMATRIXLBEORDER (Bit 2)             */
28726 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Msk (0x4UL) /*!< CHACHACOREMATRIXLBEORDER (Bitfield-Mask: 0x01) */
28727 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Pos (1UL) /*!< CHACHADINBYTEORDER (Bit 1)                         */
28728 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Msk (0x2UL) /*!< CHACHADINBYTEORDER (Bitfield-Mask: 0x01)         */
28729 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Pos (0UL) /*!< CHACHADINWORDORDER (Bit 0)                         */
28730 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Msk (0x1UL) /*!< CHACHADINWORDORDER (Bitfield-Mask: 0x01)         */
28731 /* ====================================================  CHACHADEBUGREG  ===================================================== */
28732 #define CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Pos (0UL)         /*!< CHACHADEBUGFSMSTATE (Bit 0)                           */
28733 #define CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Msk (0x3UL)       /*!< CHACHADEBUGFSMSTATE (Bitfield-Mask: 0x03)             */
28734 /* =======================================================  AESKEY00  ======================================================== */
28735 #define CRYPTO_AESKEY00_AESKEY00_Pos      (0UL)                     /*!< AESKEY00 (Bit 0)                                      */
28736 #define CRYPTO_AESKEY00_AESKEY00_Msk      (0xffffffffUL)            /*!< AESKEY00 (Bitfield-Mask: 0xffffffff)                  */
28737 /* =======================================================  AESKEY01  ======================================================== */
28738 #define CRYPTO_AESKEY01_AESKEY01_Pos      (0UL)                     /*!< AESKEY01 (Bit 0)                                      */
28739 #define CRYPTO_AESKEY01_AESKEY01_Msk      (0xffffffffUL)            /*!< AESKEY01 (Bitfield-Mask: 0xffffffff)                  */
28740 /* =======================================================  AESKEY02  ======================================================== */
28741 #define CRYPTO_AESKEY02_AESKEY02_Pos      (0UL)                     /*!< AESKEY02 (Bit 0)                                      */
28742 #define CRYPTO_AESKEY02_AESKEY02_Msk      (0xffffffffUL)            /*!< AESKEY02 (Bitfield-Mask: 0xffffffff)                  */
28743 /* =======================================================  AESKEY03  ======================================================== */
28744 #define CRYPTO_AESKEY03_AESKEY03_Pos      (0UL)                     /*!< AESKEY03 (Bit 0)                                      */
28745 #define CRYPTO_AESKEY03_AESKEY03_Msk      (0xffffffffUL)            /*!< AESKEY03 (Bitfield-Mask: 0xffffffff)                  */
28746 /* =======================================================  AESKEY04  ======================================================== */
28747 #define CRYPTO_AESKEY04_AESKEY04_Pos      (0UL)                     /*!< AESKEY04 (Bit 0)                                      */
28748 #define CRYPTO_AESKEY04_AESKEY04_Msk      (0xffffffffUL)            /*!< AESKEY04 (Bitfield-Mask: 0xffffffff)                  */
28749 /* =======================================================  AESKEY05  ======================================================== */
28750 #define CRYPTO_AESKEY05_AESKEY05_Pos      (0UL)                     /*!< AESKEY05 (Bit 0)                                      */
28751 #define CRYPTO_AESKEY05_AESKEY05_Msk      (0xffffffffUL)            /*!< AESKEY05 (Bitfield-Mask: 0xffffffff)                  */
28752 /* =======================================================  AESKEY06  ======================================================== */
28753 #define CRYPTO_AESKEY06_AESKEY06_Pos      (0UL)                     /*!< AESKEY06 (Bit 0)                                      */
28754 #define CRYPTO_AESKEY06_AESKEY06_Msk      (0xffffffffUL)            /*!< AESKEY06 (Bitfield-Mask: 0xffffffff)                  */
28755 /* =======================================================  AESKEY07  ======================================================== */
28756 #define CRYPTO_AESKEY07_AESKEY07_Pos      (0UL)                     /*!< AESKEY07 (Bit 0)                                      */
28757 #define CRYPTO_AESKEY07_AESKEY07_Msk      (0xffffffffUL)            /*!< AESKEY07 (Bitfield-Mask: 0xffffffff)                  */
28758 /* =======================================================  AESKEY10  ======================================================== */
28759 #define CRYPTO_AESKEY10_AESKEY10_Pos      (0UL)                     /*!< AESKEY10 (Bit 0)                                      */
28760 #define CRYPTO_AESKEY10_AESKEY10_Msk      (0xffffffffUL)            /*!< AESKEY10 (Bitfield-Mask: 0xffffffff)                  */
28761 /* =======================================================  AESKEY11  ======================================================== */
28762 #define CRYPTO_AESKEY11_AESKEY11_Pos      (0UL)                     /*!< AESKEY11 (Bit 0)                                      */
28763 #define CRYPTO_AESKEY11_AESKEY11_Msk      (0xffffffffUL)            /*!< AESKEY11 (Bitfield-Mask: 0xffffffff)                  */
28764 /* =======================================================  AESKEY12  ======================================================== */
28765 #define CRYPTO_AESKEY12_AESKEY12_Pos      (0UL)                     /*!< AESKEY12 (Bit 0)                                      */
28766 #define CRYPTO_AESKEY12_AESKEY12_Msk      (0xffffffffUL)            /*!< AESKEY12 (Bitfield-Mask: 0xffffffff)                  */
28767 /* =======================================================  AESKEY13  ======================================================== */
28768 #define CRYPTO_AESKEY13_AESKEY13_Pos      (0UL)                     /*!< AESKEY13 (Bit 0)                                      */
28769 #define CRYPTO_AESKEY13_AESKEY13_Msk      (0xffffffffUL)            /*!< AESKEY13 (Bitfield-Mask: 0xffffffff)                  */
28770 /* =======================================================  AESKEY14  ======================================================== */
28771 #define CRYPTO_AESKEY14_AESKEY14_Pos      (0UL)                     /*!< AESKEY14 (Bit 0)                                      */
28772 #define CRYPTO_AESKEY14_AESKEY14_Msk      (0xffffffffUL)            /*!< AESKEY14 (Bitfield-Mask: 0xffffffff)                  */
28773 /* =======================================================  AESKEY15  ======================================================== */
28774 #define CRYPTO_AESKEY15_AESKEY15_Pos      (0UL)                     /*!< AESKEY15 (Bit 0)                                      */
28775 #define CRYPTO_AESKEY15_AESKEY15_Msk      (0xffffffffUL)            /*!< AESKEY15 (Bitfield-Mask: 0xffffffff)                  */
28776 /* =======================================================  AESKEY16  ======================================================== */
28777 #define CRYPTO_AESKEY16_AESKEY16_Pos      (0UL)                     /*!< AESKEY16 (Bit 0)                                      */
28778 #define CRYPTO_AESKEY16_AESKEY16_Msk      (0xffffffffUL)            /*!< AESKEY16 (Bitfield-Mask: 0xffffffff)                  */
28779 /* =======================================================  AESKEY17  ======================================================== */
28780 #define CRYPTO_AESKEY17_AESKEY17_Pos      (0UL)                     /*!< AESKEY17 (Bit 0)                                      */
28781 #define CRYPTO_AESKEY17_AESKEY17_Msk      (0xffffffffUL)            /*!< AESKEY17 (Bitfield-Mask: 0xffffffff)                  */
28782 /* ========================================================  AESIV00  ======================================================== */
28783 #define CRYPTO_AESIV00_AESIV00_Pos        (0UL)                     /*!< AESIV00 (Bit 0)                                       */
28784 #define CRYPTO_AESIV00_AESIV00_Msk        (0xffffffffUL)            /*!< AESIV00 (Bitfield-Mask: 0xffffffff)                   */
28785 /* ========================================================  AESIV01  ======================================================== */
28786 #define CRYPTO_AESIV01_AESIV01_Pos        (0UL)                     /*!< AESIV01 (Bit 0)                                       */
28787 #define CRYPTO_AESIV01_AESIV01_Msk        (0xffffffffUL)            /*!< AESIV01 (Bitfield-Mask: 0xffffffff)                   */
28788 /* ========================================================  AESIV02  ======================================================== */
28789 #define CRYPTO_AESIV02_AESIV02_Pos        (0UL)                     /*!< AESIV02 (Bit 0)                                       */
28790 #define CRYPTO_AESIV02_AESIV02_Msk        (0xffffffffUL)            /*!< AESIV02 (Bitfield-Mask: 0xffffffff)                   */
28791 /* ========================================================  AESIV03  ======================================================== */
28792 #define CRYPTO_AESIV03_AESIV03_Pos        (0UL)                     /*!< AESIV03 (Bit 0)                                       */
28793 #define CRYPTO_AESIV03_AESIV03_Msk        (0xffffffffUL)            /*!< AESIV03 (Bitfield-Mask: 0xffffffff)                   */
28794 /* ========================================================  AESIV10  ======================================================== */
28795 #define CRYPTO_AESIV10_AESIV10_Pos        (0UL)                     /*!< AESIV10 (Bit 0)                                       */
28796 #define CRYPTO_AESIV10_AESIV10_Msk        (0xffffffffUL)            /*!< AESIV10 (Bitfield-Mask: 0xffffffff)                   */
28797 /* ========================================================  AESIV11  ======================================================== */
28798 #define CRYPTO_AESIV11_AESIV11_Pos        (0UL)                     /*!< AESIV11 (Bit 0)                                       */
28799 #define CRYPTO_AESIV11_AESIV11_Msk        (0xffffffffUL)            /*!< AESIV11 (Bitfield-Mask: 0xffffffff)                   */
28800 /* ========================================================  AESIV12  ======================================================== */
28801 #define CRYPTO_AESIV12_AESIV12_Pos        (0UL)                     /*!< AESIV12 (Bit 0)                                       */
28802 #define CRYPTO_AESIV12_AESIV12_Msk        (0xffffffffUL)            /*!< AESIV12 (Bitfield-Mask: 0xffffffff)                   */
28803 /* ========================================================  AESIV13  ======================================================== */
28804 #define CRYPTO_AESIV13_AESIV13_Pos        (0UL)                     /*!< AESIV13 (Bit 0)                                       */
28805 #define CRYPTO_AESIV13_AESIV13_Msk        (0xffffffffUL)            /*!< AESIV13 (Bitfield-Mask: 0xffffffff)                   */
28806 /* =======================================================  AESCTR00  ======================================================== */
28807 #define CRYPTO_AESCTR00_AESCTR00_Pos      (0UL)                     /*!< AESCTR00 (Bit 0)                                      */
28808 #define CRYPTO_AESCTR00_AESCTR00_Msk      (0xffffffffUL)            /*!< AESCTR00 (Bitfield-Mask: 0xffffffff)                  */
28809 /* =======================================================  AESCTR01  ======================================================== */
28810 #define CRYPTO_AESCTR01_AESCTR01_Pos      (0UL)                     /*!< AESCTR01 (Bit 0)                                      */
28811 #define CRYPTO_AESCTR01_AESCTR01_Msk      (0xffffffffUL)            /*!< AESCTR01 (Bitfield-Mask: 0xffffffff)                  */
28812 /* =======================================================  AESCTR02  ======================================================== */
28813 #define CRYPTO_AESCTR02_AESCTR02_Pos      (0UL)                     /*!< AESCTR02 (Bit 0)                                      */
28814 #define CRYPTO_AESCTR02_AESCTR02_Msk      (0xffffffffUL)            /*!< AESCTR02 (Bitfield-Mask: 0xffffffff)                  */
28815 /* =======================================================  AESCTR03  ======================================================== */
28816 #define CRYPTO_AESCTR03_AESCTR03_Pos      (0UL)                     /*!< AESCTR03 (Bit 0)                                      */
28817 #define CRYPTO_AESCTR03_AESCTR03_Msk      (0xffffffffUL)            /*!< AESCTR03 (Bitfield-Mask: 0xffffffff)                  */
28818 /* ========================================================  AESBUSY  ======================================================== */
28819 #define CRYPTO_AESBUSY_AESBUSY_Pos        (0UL)                     /*!< AESBUSY (Bit 0)                                       */
28820 #define CRYPTO_AESBUSY_AESBUSY_Msk        (0x1UL)                   /*!< AESBUSY (Bitfield-Mask: 0x01)                         */
28821 /* =========================================================  AESSK  ========================================================= */
28822 #define CRYPTO_AESSK_AESSK_Pos            (0UL)                     /*!< AESSK (Bit 0)                                         */
28823 #define CRYPTO_AESSK_AESSK_Msk            (0x1UL)                   /*!< AESSK (Bitfield-Mask: 0x01)                           */
28824 /* ======================================================  AESCMACINIT  ====================================================== */
28825 #define CRYPTO_AESCMACINIT_AESCMACINIT_Pos (0UL)                    /*!< AESCMACINIT (Bit 0)                                   */
28826 #define CRYPTO_AESCMACINIT_AESCMACINIT_Msk (0x1UL)                  /*!< AESCMACINIT (Bitfield-Mask: 0x01)                     */
28827 /* ========================================================  AESSK1  ========================================================= */
28828 #define CRYPTO_AESSK1_AESSK1_Pos          (0UL)                     /*!< AESSK1 (Bit 0)                                        */
28829 #define CRYPTO_AESSK1_AESSK1_Msk          (0x1UL)                   /*!< AESSK1 (Bitfield-Mask: 0x01)                          */
28830 /* ===================================================  AESREMAININGBYTES  =================================================== */
28831 #define CRYPTO_AESREMAININGBYTES_AESREMAININGBYTES_Pos (0UL)        /*!< AESREMAININGBYTES (Bit 0)                             */
28832 #define CRYPTO_AESREMAININGBYTES_AESREMAININGBYTES_Msk (0xffffffffUL) /*!< AESREMAININGBYTES (Bitfield-Mask: 0xffffffff)       */
28833 /* ======================================================  AESCONTROL  ======================================================= */
28834 #define CRYPTO_AESCONTROL_DIRECTACCESS_Pos (31UL)                   /*!< DIRECTACCESS (Bit 31)                                 */
28835 #define CRYPTO_AESCONTROL_DIRECTACCESS_Msk (0x80000000UL)           /*!< DIRECTACCESS (Bitfield-Mask: 0x01)                    */
28836 #define CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Pos (29UL)                /*!< AESXORCRYPTOKEY (Bit 29)                              */
28837 #define CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Msk (0x20000000UL)        /*!< AESXORCRYPTOKEY (Bitfield-Mask: 0x01)                 */
28838 #define CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Pos (28UL)             /*!< AESOUTMIDTUNTOHASH (Bit 28)                           */
28839 #define CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Msk (0x10000000UL)     /*!< AESOUTMIDTUNTOHASH (Bitfield-Mask: 0x01)              */
28840 #define CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Pos (26UL)               /*!< AESTUNNELB1PADEN (Bit 26)                             */
28841 #define CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Msk (0x4000000UL)        /*!< AESTUNNELB1PADEN (Bitfield-Mask: 0x01)                */
28842 #define CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Pos (25UL)         /*!< AESOUTPUTMIDTUNNELDATA (Bit 25)                       */
28843 #define CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Msk (0x2000000UL)  /*!< AESOUTPUTMIDTUNNELDATA (Bitfield-Mask: 0x01)          */
28844 #define CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Pos (24UL)              /*!< AESTUNNEL0ENCRYPT (Bit 24)                            */
28845 #define CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Msk (0x1000000UL)       /*!< AESTUNNEL0ENCRYPT (Bitfield-Mask: 0x01)               */
28846 #define CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Pos (23UL)       /*!< AESTUNB1USESPADDEDDATAIN (Bit 23)                     */
28847 #define CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Msk (0x800000UL) /*!< AESTUNB1USESPADDEDDATAIN (Bitfield-Mask: 0x01)        */
28848 #define CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Pos (22UL)              /*!< AESTUNNEL1DECRYPT (Bit 22)                            */
28849 #define CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Msk (0x400000UL)        /*!< AESTUNNEL1DECRYPT (Bitfield-Mask: 0x01)               */
28850 #define CRYPTO_AESCONTROL_NKKEY1_Pos      (14UL)                    /*!< NKKEY1 (Bit 14)                                       */
28851 #define CRYPTO_AESCONTROL_NKKEY1_Msk      (0xc000UL)                /*!< NKKEY1 (Bitfield-Mask: 0x03)                          */
28852 #define CRYPTO_AESCONTROL_NKKEY0_Pos      (12UL)                    /*!< NKKEY0 (Bit 12)                                       */
28853 #define CRYPTO_AESCONTROL_NKKEY0_Msk      (0x3000UL)                /*!< NKKEY0 (Bitfield-Mask: 0x03)                          */
28854 #define CRYPTO_AESCONTROL_CBCISBITLOCKER_Pos (11UL)                 /*!< CBCISBITLOCKER (Bit 11)                               */
28855 #define CRYPTO_AESCONTROL_CBCISBITLOCKER_Msk (0x800UL)              /*!< CBCISBITLOCKER (Bitfield-Mask: 0x01)                  */
28856 #define CRYPTO_AESCONTROL_AESTUNNELISON_Pos (10UL)                  /*!< AESTUNNELISON (Bit 10)                                */
28857 #define CRYPTO_AESCONTROL_AESTUNNELISON_Msk (0x400UL)               /*!< AESTUNNELISON (Bitfield-Mask: 0x01)                   */
28858 #define CRYPTO_AESCONTROL_CBCISESSIV_Pos  (8UL)                     /*!< CBCISESSIV (Bit 8)                                    */
28859 #define CRYPTO_AESCONTROL_CBCISESSIV_Msk  (0x100UL)                 /*!< CBCISESSIV (Bitfield-Mask: 0x01)                      */
28860 #define CRYPTO_AESCONTROL_MODEKEY1_Pos    (5UL)                     /*!< MODEKEY1 (Bit 5)                                      */
28861 #define CRYPTO_AESCONTROL_MODEKEY1_Msk    (0xe0UL)                  /*!< MODEKEY1 (Bitfield-Mask: 0x07)                        */
28862 #define CRYPTO_AESCONTROL_MODEKEY0_Pos    (2UL)                     /*!< MODEKEY0 (Bit 2)                                      */
28863 #define CRYPTO_AESCONTROL_MODEKEY0_Msk    (0x1cUL)                  /*!< MODEKEY0 (Bitfield-Mask: 0x07)                        */
28864 #define CRYPTO_AESCONTROL_MODE0ISCBCCTS_Pos (1UL)                   /*!< MODE0ISCBCCTS (Bit 1)                                 */
28865 #define CRYPTO_AESCONTROL_MODE0ISCBCCTS_Msk (0x2UL)                 /*!< MODE0ISCBCCTS (Bitfield-Mask: 0x01)                   */
28866 #define CRYPTO_AESCONTROL_DECKEY0_Pos     (0UL)                     /*!< DECKEY0 (Bit 0)                                       */
28867 #define CRYPTO_AESCONTROL_DECKEY0_Msk     (0x1UL)                   /*!< DECKEY0 (Bitfield-Mask: 0x01)                         */
28868 /* ======================================================  AESHWFLAGS  ======================================================= */
28869 #define CRYPTO_AESHWFLAGS_DFACNTRMSREXIST_Pos (12UL)                /*!< DFACNTRMSREXIST (Bit 12)                              */
28870 #define CRYPTO_AESHWFLAGS_DFACNTRMSREXIST_Msk (0x1000UL)            /*!< DFACNTRMSREXIST (Bitfield-Mask: 0x01)                 */
28871 #define CRYPTO_AESHWFLAGS_SECONDREGSSETEXIST_Pos (11UL)             /*!< SECONDREGSSETEXIST (Bit 11)                           */
28872 #define CRYPTO_AESHWFLAGS_SECONDREGSSETEXIST_Msk (0x800UL)          /*!< SECONDREGSSETEXIST (Bitfield-Mask: 0x01)              */
28873 #define CRYPTO_AESHWFLAGS_aestunnelexists_Pos (10UL)                /*!< aestunnelexists (Bit 10)                              */
28874 #define CRYPTO_AESHWFLAGS_aestunnelexists_Msk (0x400UL)             /*!< aestunnelexists (Bitfield-Mask: 0x01)                 */
28875 #define CRYPTO_AESHWFLAGS_AESSUPPORTPREVIV_Pos (9UL)                /*!< AESSUPPORTPREVIV (Bit 9)                              */
28876 #define CRYPTO_AESHWFLAGS_AESSUPPORTPREVIV_Msk (0x200UL)            /*!< AESSUPPORTPREVIV (Bitfield-Mask: 0x01)                */
28877 #define CRYPTO_AESHWFLAGS_USE5SBOXES_Pos  (8UL)                     /*!< USE5SBOXES (Bit 8)                                    */
28878 #define CRYPTO_AESHWFLAGS_USE5SBOXES_Msk  (0x100UL)                 /*!< USE5SBOXES (Bitfield-Mask: 0x01)                      */
28879 #define CRYPTO_AESHWFLAGS_USESBOXTABLE_Pos (5UL)                    /*!< USESBOXTABLE (Bit 5)                                  */
28880 #define CRYPTO_AESHWFLAGS_USESBOXTABLE_Msk (0x20UL)                 /*!< USESBOXTABLE (Bitfield-Mask: 0x01)                    */
28881 #define CRYPTO_AESHWFLAGS_ONLYENCRYPT_Pos (4UL)                     /*!< ONLYENCRYPT (Bit 4)                                   */
28882 #define CRYPTO_AESHWFLAGS_ONLYENCRYPT_Msk (0x10UL)                  /*!< ONLYENCRYPT (Bitfield-Mask: 0x01)                     */
28883 #define CRYPTO_AESHWFLAGS_CTREXIST_Pos    (3UL)                     /*!< CTREXIST (Bit 3)                                      */
28884 #define CRYPTO_AESHWFLAGS_CTREXIST_Msk    (0x8UL)                   /*!< CTREXIST (Bitfield-Mask: 0x01)                        */
28885 #define CRYPTO_AESHWFLAGS_DPACNTRMSREXIST_Pos (2UL)                 /*!< DPACNTRMSREXIST (Bit 2)                               */
28886 #define CRYPTO_AESHWFLAGS_DPACNTRMSREXIST_Msk (0x4UL)               /*!< DPACNTRMSREXIST (Bitfield-Mask: 0x01)                 */
28887 #define CRYPTO_AESHWFLAGS_AESLARGERKEK_Pos (1UL)                    /*!< AESLARGERKEK (Bit 1)                                  */
28888 #define CRYPTO_AESHWFLAGS_AESLARGERKEK_Msk (0x2UL)                  /*!< AESLARGERKEK (Bitfield-Mask: 0x01)                    */
28889 #define CRYPTO_AESHWFLAGS_SUPPORT256192KEY_Pos (0UL)                /*!< SUPPORT256192KEY (Bit 0)                              */
28890 #define CRYPTO_AESHWFLAGS_SUPPORT256192KEY_Msk (0x1UL)              /*!< SUPPORT256192KEY (Bitfield-Mask: 0x01)                */
28891 /* ===================================================  AESCTRNOINCREMENT  =================================================== */
28892 #define CRYPTO_AESCTRNOINCREMENT_AESCTRNOINCREMENT_Pos (0UL)        /*!< AESCTRNOINCREMENT (Bit 0)                             */
28893 #define CRYPTO_AESCTRNOINCREMENT_AESCTRNOINCREMENT_Msk (0x1UL)      /*!< AESCTRNOINCREMENT (Bitfield-Mask: 0x01)               */
28894 /* ======================================================  AESDFAISON  ======================================================= */
28895 #define CRYPTO_AESDFAISON_AESDFAISON_Pos  (0UL)                     /*!< AESDFAISON (Bit 0)                                    */
28896 #define CRYPTO_AESDFAISON_AESDFAISON_Msk  (0x1UL)                   /*!< AESDFAISON (Bitfield-Mask: 0x01)                      */
28897 /* ====================================================  AESDFAERRSTATUS  ==================================================== */
28898 #define CRYPTO_AESDFAERRSTATUS_AESDFAERRSTATUS_Pos (0UL)            /*!< AESDFAERRSTATUS (Bit 0)                               */
28899 #define CRYPTO_AESDFAERRSTATUS_AESDFAERRSTATUS_Msk (0x1UL)          /*!< AESDFAERRSTATUS (Bitfield-Mask: 0x01)                 */
28900 /* ===================================================  AESCMACSIZE0KICK  ==================================================== */
28901 #define CRYPTO_AESCMACSIZE0KICK_AESCMACSIZE0KICK_Pos (0UL)          /*!< AESCMACSIZE0KICK (Bit 0)                              */
28902 #define CRYPTO_AESCMACSIZE0KICK_AESCMACSIZE0KICK_Msk (0x1UL)        /*!< AESCMACSIZE0KICK (Bitfield-Mask: 0x01)                */
28903 /* ========================================================  HASHH0  ========================================================= */
28904 #define CRYPTO_HASHH0_HASHH0_Pos          (0UL)                     /*!< HASHH0 (Bit 0)                                        */
28905 #define CRYPTO_HASHH0_HASHH0_Msk          (0xffffffffUL)            /*!< HASHH0 (Bitfield-Mask: 0xffffffff)                    */
28906 /* ========================================================  HASHH1  ========================================================= */
28907 #define CRYPTO_HASHH1_HASHH1_Pos          (0UL)                     /*!< HASHH1 (Bit 0)                                        */
28908 #define CRYPTO_HASHH1_HASHH1_Msk          (0xffffffffUL)            /*!< HASHH1 (Bitfield-Mask: 0xffffffff)                    */
28909 /* ========================================================  HASHH2  ========================================================= */
28910 #define CRYPTO_HASHH2_HASHH2_Pos          (0UL)                     /*!< HASHH2 (Bit 0)                                        */
28911 #define CRYPTO_HASHH2_HASHH2_Msk          (0xffffffffUL)            /*!< HASHH2 (Bitfield-Mask: 0xffffffff)                    */
28912 /* ========================================================  HASHH3  ========================================================= */
28913 #define CRYPTO_HASHH3_HASHH3_Pos          (0UL)                     /*!< HASHH3 (Bit 0)                                        */
28914 #define CRYPTO_HASHH3_HASHH3_Msk          (0xffffffffUL)            /*!< HASHH3 (Bitfield-Mask: 0xffffffff)                    */
28915 /* ========================================================  HASHH4  ========================================================= */
28916 #define CRYPTO_HASHH4_HASHH4_Pos          (0UL)                     /*!< HASHH4 (Bit 0)                                        */
28917 #define CRYPTO_HASHH4_HASHH4_Msk          (0xffffffffUL)            /*!< HASHH4 (Bitfield-Mask: 0xffffffff)                    */
28918 /* ========================================================  HASHH5  ========================================================= */
28919 #define CRYPTO_HASHH5_HASHH5_Pos          (0UL)                     /*!< HASHH5 (Bit 0)                                        */
28920 #define CRYPTO_HASHH5_HASHH5_Msk          (0xffffffffUL)            /*!< HASHH5 (Bitfield-Mask: 0xffffffff)                    */
28921 /* ========================================================  HASHH6  ========================================================= */
28922 #define CRYPTO_HASHH6_HASHH6_Pos          (0UL)                     /*!< HASHH6 (Bit 0)                                        */
28923 #define CRYPTO_HASHH6_HASHH6_Msk          (0xffffffffUL)            /*!< HASHH6 (Bitfield-Mask: 0xffffffff)                    */
28924 /* ========================================================  HASHH7  ========================================================= */
28925 #define CRYPTO_HASHH7_HASHH7_Pos          (0UL)                     /*!< HASHH7 (Bit 0)                                        */
28926 #define CRYPTO_HASHH7_HASHH7_Msk          (0xffffffffUL)            /*!< HASHH7 (Bitfield-Mask: 0xffffffff)                    */
28927 /* ========================================================  HASHH8  ========================================================= */
28928 #define CRYPTO_HASHH8_HASHH8_Pos          (0UL)                     /*!< HASHH8 (Bit 0)                                        */
28929 #define CRYPTO_HASHH8_HASHH8_Msk          (0xffffffffUL)            /*!< HASHH8 (Bitfield-Mask: 0xffffffff)                    */
28930 /* =====================================================  AUTOHWPADDING  ===================================================== */
28931 #define CRYPTO_AUTOHWPADDING_EN_Pos       (0UL)                     /*!< EN (Bit 0)                                            */
28932 #define CRYPTO_AUTOHWPADDING_EN_Msk       (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
28933 /* ======================================================  HASHXORDIN  ======================================================= */
28934 #define CRYPTO_HASHXORDIN_HASHXORDATA_Pos (0UL)                     /*!< HASHXORDATA (Bit 0)                                   */
28935 #define CRYPTO_HASHXORDIN_HASHXORDATA_Msk (0xffffffffUL)            /*!< HASHXORDATA (Bitfield-Mask: 0xffffffff)               */
28936 /* =====================================================  LOADINITSTATE  ===================================================== */
28937 #define CRYPTO_LOADINITSTATE_LOAD_Pos     (0UL)                     /*!< LOAD (Bit 0)                                          */
28938 #define CRYPTO_LOADINITSTATE_LOAD_Msk     (0x1UL)                   /*!< LOAD (Bitfield-Mask: 0x01)                            */
28939 /* =====================================================  HASHSELAESMAC  ===================================================== */
28940 #define CRYPTO_HASHSELAESMAC_GHASHSEL_Pos (1UL)                     /*!< GHASHSEL (Bit 1)                                      */
28941 #define CRYPTO_HASHSELAESMAC_GHASHSEL_Msk (0x2UL)                   /*!< GHASHSEL (Bitfield-Mask: 0x01)                        */
28942 #define CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Pos (0UL)                /*!< HASHSELAESMAC (Bit 0)                                 */
28943 #define CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Msk (0x1UL)              /*!< HASHSELAESMAC (Bitfield-Mask: 0x01)                   */
28944 /* ======================================================  HASHVERSION  ====================================================== */
28945 #define CRYPTO_HASHVERSION_MAJORVERSIONNUMBER_Pos (12UL)            /*!< MAJORVERSIONNUMBER (Bit 12)                           */
28946 #define CRYPTO_HASHVERSION_MAJORVERSIONNUMBER_Msk (0xf000UL)        /*!< MAJORVERSIONNUMBER (Bitfield-Mask: 0x0f)              */
28947 #define CRYPTO_HASHVERSION_MINORVERSIONNUMBER_Pos (8UL)             /*!< MINORVERSIONNUMBER (Bit 8)                            */
28948 #define CRYPTO_HASHVERSION_MINORVERSIONNUMBER_Msk (0xf00UL)         /*!< MINORVERSIONNUMBER (Bitfield-Mask: 0x0f)              */
28949 #define CRYPTO_HASHVERSION_FIXES_Pos      (0UL)                     /*!< FIXES (Bit 0)                                         */
28950 #define CRYPTO_HASHVERSION_FIXES_Msk      (0xffUL)                  /*!< FIXES (Bitfield-Mask: 0xff)                           */
28951 /* ======================================================  HASHCONTROL  ====================================================== */
28952 #define CRYPTO_HASHCONTROL_MODE3_Pos      (3UL)                     /*!< MODE3 (Bit 3)                                         */
28953 #define CRYPTO_HASHCONTROL_MODE3_Msk      (0x8UL)                   /*!< MODE3 (Bitfield-Mask: 0x01)                           */
28954 #define CRYPTO_HASHCONTROL_MODE01_Pos     (0UL)                     /*!< MODE01 (Bit 0)                                        */
28955 #define CRYPTO_HASHCONTROL_MODE01_Msk     (0x3UL)                   /*!< MODE01 (Bitfield-Mask: 0x03)                          */
28956 /* =======================================================  HASHPADEN  ======================================================= */
28957 #define CRYPTO_HASHPADEN_EN_Pos           (0UL)                     /*!< EN (Bit 0)                                            */
28958 #define CRYPTO_HASHPADEN_EN_Msk           (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
28959 /* ======================================================  HASHPADCFG  ======================================================= */
28960 #define CRYPTO_HASHPADCFG_DOPAD_Pos       (2UL)                     /*!< DOPAD (Bit 2)                                         */
28961 #define CRYPTO_HASHPADCFG_DOPAD_Msk       (0x4UL)                   /*!< DOPAD (Bitfield-Mask: 0x01)                           */
28962 /* ======================================================  HASHCURLEN0  ====================================================== */
28963 #define CRYPTO_HASHCURLEN0_Length_Pos     (0UL)                     /*!< Length (Bit 0)                                        */
28964 #define CRYPTO_HASHCURLEN0_Length_Msk     (0xffffffffUL)            /*!< Length (Bitfield-Mask: 0xffffffff)                    */
28965 /* ======================================================  HASHCURLEN1  ====================================================== */
28966 #define CRYPTO_HASHCURLEN1_Length_Pos     (0UL)                     /*!< Length (Bit 0)                                        */
28967 #define CRYPTO_HASHCURLEN1_Length_Msk     (0xffffffffUL)            /*!< Length (Bitfield-Mask: 0xffffffff)                    */
28968 /* =======================================================  HASHPARAM  ======================================================= */
28969 #define CRYPTO_HASHPARAM_DUMPHASHTODOUTEXISTS_Pos (18UL)            /*!< DUMPHASHTODOUTEXISTS (Bit 18)                         */
28970 #define CRYPTO_HASHPARAM_DUMPHASHTODOUTEXISTS_Msk (0x40000UL)       /*!< DUMPHASHTODOUTEXISTS (Bitfield-Mask: 0x01)            */
28971 #define CRYPTO_HASHPARAM_HASHCOMPAREEXISTS_Pos (17UL)               /*!< HASHCOMPAREEXISTS (Bit 17)                            */
28972 #define CRYPTO_HASHPARAM_HASHCOMPAREEXISTS_Msk (0x20000UL)          /*!< HASHCOMPAREEXISTS (Bitfield-Mask: 0x01)               */
28973 #define CRYPTO_HASHPARAM_SHA256EXISTS_Pos (16UL)                    /*!< SHA256EXISTS (Bit 16)                                 */
28974 #define CRYPTO_HASHPARAM_SHA256EXISTS_Msk (0x10000UL)               /*!< SHA256EXISTS (Bitfield-Mask: 0x01)                    */
28975 #define CRYPTO_HASHPARAM_HMACEXISTS_Pos   (15UL)                    /*!< HMACEXISTS (Bit 15)                                   */
28976 #define CRYPTO_HASHPARAM_HMACEXISTS_Msk   (0x8000UL)                /*!< HMACEXISTS (Bitfield-Mask: 0x01)                      */
28977 #define CRYPTO_HASHPARAM_MD5EXISTS_Pos    (14UL)                    /*!< MD5EXISTS (Bit 14)                                    */
28978 #define CRYPTO_HASHPARAM_MD5EXISTS_Msk    (0x4000UL)                /*!< MD5EXISTS (Bitfield-Mask: 0x01)                       */
28979 #define CRYPTO_HASHPARAM_PADEXISTS_Pos    (13UL)                    /*!< PADEXISTS (Bit 13)                                    */
28980 #define CRYPTO_HASHPARAM_PADEXISTS_Msk    (0x2000UL)                /*!< PADEXISTS (Bitfield-Mask: 0x01)                       */
28981 #define CRYPTO_HASHPARAM_SHA512EXISTS_Pos (12UL)                    /*!< SHA512EXISTS (Bit 12)                                 */
28982 #define CRYPTO_HASHPARAM_SHA512EXISTS_Msk (0x1000UL)                /*!< SHA512EXISTS (Bitfield-Mask: 0x01)                    */
28983 #define CRYPTO_HASHPARAM_DW_Pos           (8UL)                     /*!< DW (Bit 8)                                            */
28984 #define CRYPTO_HASHPARAM_DW_Msk           (0xf00UL)                 /*!< DW (Bitfield-Mask: 0x0f)                              */
28985 #define CRYPTO_HASHPARAM_CH_Pos           (4UL)                     /*!< CH (Bit 4)                                            */
28986 #define CRYPTO_HASHPARAM_CH_Msk           (0xf0UL)                  /*!< CH (Bitfield-Mask: 0x0f)                              */
28987 #define CRYPTO_HASHPARAM_CW_Pos           (0UL)                     /*!< CW (Bit 0)                                            */
28988 #define CRYPTO_HASHPARAM_CW_Msk           (0xfUL)                   /*!< CW (Bitfield-Mask: 0x0f)                              */
28989 /* ====================================================  HASHAESSWRESET  ===================================================== */
28990 #define CRYPTO_HASHAESSWRESET_HASHAESSWRESET_Pos (0UL)              /*!< HASHAESSWRESET (Bit 0)                                */
28991 #define CRYPTO_HASHAESSWRESET_HASHAESSWRESET_Msk (0x1UL)            /*!< HASHAESSWRESET (Bitfield-Mask: 0x01)                  */
28992 /* =====================================================  HASHENDIANESS  ===================================================== */
28993 #define CRYPTO_HASHENDIANESS_ENDIAN_Pos   (0UL)                     /*!< ENDIAN (Bit 0)                                        */
28994 #define CRYPTO_HASHENDIANESS_ENDIAN_Msk   (0x1UL)                   /*!< ENDIAN (Bitfield-Mask: 0x01)                          */
28995 /* =====================================================  AESCLKENABLE  ====================================================== */
28996 #define CRYPTO_AESCLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
28997 #define CRYPTO_AESCLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
28998 /* =====================================================  HASHCLKENABLE  ===================================================== */
28999 #define CRYPTO_HASHCLKENABLE_EN_Pos       (0UL)                     /*!< EN (Bit 0)                                            */
29000 #define CRYPTO_HASHCLKENABLE_EN_Msk       (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29001 /* =====================================================  PKACLKENABLE  ====================================================== */
29002 #define CRYPTO_PKACLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
29003 #define CRYPTO_PKACLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29004 /* =====================================================  DMACLKENABLE  ====================================================== */
29005 #define CRYPTO_DMACLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
29006 #define CRYPTO_DMACLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29007 /* =======================================================  CLKSTATUS  ======================================================= */
29008 #define CRYPTO_CLKSTATUS_DMACLKSTATUS_Pos (8UL)                     /*!< DMACLKSTATUS (Bit 8)                                  */
29009 #define CRYPTO_CLKSTATUS_DMACLKSTATUS_Msk (0x100UL)                 /*!< DMACLKSTATUS (Bitfield-Mask: 0x01)                    */
29010 #define CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Pos (7UL)                  /*!< CHACHACLKSTATUS (Bit 7)                               */
29011 #define CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Msk (0x80UL)               /*!< CHACHACLKSTATUS (Bitfield-Mask: 0x01)                 */
29012 #define CRYPTO_CLKSTATUS_PKACLKSTATUS_Pos (3UL)                     /*!< PKACLKSTATUS (Bit 3)                                  */
29013 #define CRYPTO_CLKSTATUS_PKACLKSTATUS_Msk (0x8UL)                   /*!< PKACLKSTATUS (Bitfield-Mask: 0x01)                    */
29014 #define CRYPTO_CLKSTATUS_HASHCLKSTATUS_Pos (2UL)                    /*!< HASHCLKSTATUS (Bit 2)                                 */
29015 #define CRYPTO_CLKSTATUS_HASHCLKSTATUS_Msk (0x4UL)                  /*!< HASHCLKSTATUS (Bitfield-Mask: 0x01)                   */
29016 #define CRYPTO_CLKSTATUS_AESCLKSTATUS_Pos (0UL)                     /*!< AESCLKSTATUS (Bit 0)                                  */
29017 #define CRYPTO_CLKSTATUS_AESCLKSTATUS_Msk (0x1UL)                   /*!< AESCLKSTATUS (Bitfield-Mask: 0x01)                    */
29018 /* ====================================================  CHACHACLKENABLE  ==================================================== */
29019 #define CRYPTO_CHACHACLKENABLE_EN_Pos     (0UL)                     /*!< EN (Bit 0)                                            */
29020 #define CRYPTO_CHACHACLKENABLE_EN_Msk     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29021 /* =======================================================  CRYPTOCTL  ======================================================= */
29022 #define CRYPTO_CRYPTOCTL_MODE_Pos         (0UL)                     /*!< MODE (Bit 0)                                          */
29023 #define CRYPTO_CRYPTOCTL_MODE_Msk         (0x1fUL)                  /*!< MODE (Bitfield-Mask: 0x1f)                            */
29024 /* ======================================================  CRYPTOBUSY  ======================================================= */
29025 #define CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Pos  (0UL)                     /*!< CRYPTOBUSY (Bit 0)                                    */
29026 #define CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Msk  (0x1UL)                   /*!< CRYPTOBUSY (Bitfield-Mask: 0x01)                      */
29027 /* =======================================================  HASHBUSY  ======================================================== */
29028 #define CRYPTO_HASHBUSY_HASHBUSY_Pos      (0UL)                     /*!< HASHBUSY (Bit 0)                                      */
29029 #define CRYPTO_HASHBUSY_HASHBUSY_Msk      (0x1UL)                   /*!< HASHBUSY (Bitfield-Mask: 0x01)                        */
29030 /* =======================================================  CONTEXTID  ======================================================= */
29031 #define CRYPTO_CONTEXTID_CONTEXTID_Pos    (0UL)                     /*!< CONTEXTID (Bit 0)                                     */
29032 #define CRYPTO_CONTEXTID_CONTEXTID_Msk    (0xffUL)                  /*!< CONTEXTID (Bitfield-Mask: 0xff)                       */
29033 /* =====================================================  GHASHSUBKEY00  ===================================================== */
29034 #define CRYPTO_GHASHSUBKEY00_GHASHSUBKEY00_Pos (0UL)                /*!< GHASHSUBKEY00 (Bit 0)                                 */
29035 #define CRYPTO_GHASHSUBKEY00_GHASHSUBKEY00_Msk (0xffffffffUL)       /*!< GHASHSUBKEY00 (Bitfield-Mask: 0xffffffff)             */
29036 /* =====================================================  GHASHSUBKEY01  ===================================================== */
29037 #define CRYPTO_GHASHSUBKEY01_GHASHSUBKEY01_Pos (0UL)                /*!< GHASHSUBKEY01 (Bit 0)                                 */
29038 #define CRYPTO_GHASHSUBKEY01_GHASHSUBKEY01_Msk (0xffffffffUL)       /*!< GHASHSUBKEY01 (Bitfield-Mask: 0xffffffff)             */
29039 /* =====================================================  GHASHSUBKEY02  ===================================================== */
29040 #define CRYPTO_GHASHSUBKEY02_GHASHSUBKEY02_Pos (0UL)                /*!< GHASHSUBKEY02 (Bit 0)                                 */
29041 #define CRYPTO_GHASHSUBKEY02_GHASHSUBKEY02_Msk (0xffffffffUL)       /*!< GHASHSUBKEY02 (Bitfield-Mask: 0xffffffff)             */
29042 /* =====================================================  GHASHSUBKEY03  ===================================================== */
29043 #define CRYPTO_GHASHSUBKEY03_GHASHSUBKEY03_Pos (0UL)                /*!< GHASHSUBKEY03 (Bit 0)                                 */
29044 #define CRYPTO_GHASHSUBKEY03_GHASHSUBKEY03_Msk (0xffffffffUL)       /*!< GHASHSUBKEY03 (Bitfield-Mask: 0xffffffff)             */
29045 /* =======================================================  GHASHIV00  ======================================================= */
29046 #define CRYPTO_GHASHIV00_GHASHIV00_Pos    (0UL)                     /*!< GHASHIV00 (Bit 0)                                     */
29047 #define CRYPTO_GHASHIV00_GHASHIV00_Msk    (0xffffffffUL)            /*!< GHASHIV00 (Bitfield-Mask: 0xffffffff)                 */
29048 /* =======================================================  GHASHIV01  ======================================================= */
29049 #define CRYPTO_GHASHIV01_GHASHIV01_Pos    (0UL)                     /*!< GHASHIV01 (Bit 0)                                     */
29050 #define CRYPTO_GHASHIV01_GHASHIV01_Msk    (0xffffffffUL)            /*!< GHASHIV01 (Bitfield-Mask: 0xffffffff)                 */
29051 /* =======================================================  GHASHIV02  ======================================================= */
29052 #define CRYPTO_GHASHIV02_GHASHIV02_Pos    (0UL)                     /*!< GHASHIV02 (Bit 0)                                     */
29053 #define CRYPTO_GHASHIV02_GHASHIV02_Msk    (0xffffffffUL)            /*!< GHASHIV02 (Bitfield-Mask: 0xffffffff)                 */
29054 /* =======================================================  GHASHIV03  ======================================================= */
29055 #define CRYPTO_GHASHIV03_GHASHIV03_Pos    (0UL)                     /*!< GHASHIV03 (Bit 0)                                     */
29056 #define CRYPTO_GHASHIV03_GHASHIV03_Msk    (0xffffffffUL)            /*!< GHASHIV03 (Bitfield-Mask: 0xffffffff)                 */
29057 /* =======================================================  GHASHBUSY  ======================================================= */
29058 #define CRYPTO_GHASHBUSY_GHASHBUSY_Pos    (0UL)                     /*!< GHASHBUSY (Bit 0)                                     */
29059 #define CRYPTO_GHASHBUSY_GHASHBUSY_Msk    (0x1UL)                   /*!< GHASHBUSY (Bitfield-Mask: 0x01)                       */
29060 /* =======================================================  GHASHINIT  ======================================================= */
29061 #define CRYPTO_GHASHINIT_GHASHINIT_Pos    (0UL)                     /*!< GHASHINIT (Bit 0)                                     */
29062 #define CRYPTO_GHASHINIT_GHASHINIT_Msk    (0x1UL)                   /*!< GHASHINIT (Bitfield-Mask: 0x01)                       */
29063 /* ======================================================  HOSTRGFIRR  ======================================================= */
29064 #define CRYPTO_HOSTRGFIRR_SYMDMACOMPLETED_Pos (11UL)                /*!< SYMDMACOMPLETED (Bit 11)                              */
29065 #define CRYPTO_HOSTRGFIRR_SYMDMACOMPLETED_Msk (0x800UL)             /*!< SYMDMACOMPLETED (Bitfield-Mask: 0x01)                 */
29066 #define CRYPTO_HOSTRGFIRR_RNGINT_Pos      (10UL)                    /*!< RNGINT (Bit 10)                                       */
29067 #define CRYPTO_HOSTRGFIRR_RNGINT_Msk      (0x400UL)                 /*!< RNGINT (Bitfield-Mask: 0x01)                          */
29068 #define CRYPTO_HOSTRGFIRR_PKAEXPINT_Pos   (9UL)                     /*!< PKAEXPINT (Bit 9)                                     */
29069 #define CRYPTO_HOSTRGFIRR_PKAEXPINT_Msk   (0x200UL)                 /*!< PKAEXPINT (Bitfield-Mask: 0x01)                       */
29070 #define CRYPTO_HOSTRGFIRR_AHBERRINT_Pos   (8UL)                     /*!< AHBERRINT (Bit 8)                                     */
29071 #define CRYPTO_HOSTRGFIRR_AHBERRINT_Msk   (0x100UL)                 /*!< AHBERRINT (Bitfield-Mask: 0x01)                       */
29072 #define CRYPTO_HOSTRGFIRR_DOUTTOMEMINT_Pos (7UL)                    /*!< DOUTTOMEMINT (Bit 7)                                  */
29073 #define CRYPTO_HOSTRGFIRR_DOUTTOMEMINT_Msk (0x80UL)                 /*!< DOUTTOMEMINT (Bitfield-Mask: 0x01)                    */
29074 #define CRYPTO_HOSTRGFIRR_MEMTODININT_Pos (6UL)                     /*!< MEMTODININT (Bit 6)                                   */
29075 #define CRYPTO_HOSTRGFIRR_MEMTODININT_Msk (0x40UL)                  /*!< MEMTODININT (Bitfield-Mask: 0x01)                     */
29076 #define CRYPTO_HOSTRGFIRR_DOUTTOSRAMINT_Pos (5UL)                   /*!< DOUTTOSRAMINT (Bit 5)                                 */
29077 #define CRYPTO_HOSTRGFIRR_DOUTTOSRAMINT_Msk (0x20UL)                /*!< DOUTTOSRAMINT (Bitfield-Mask: 0x01)                   */
29078 #define CRYPTO_HOSTRGFIRR_SRAMTODININT_Pos (4UL)                    /*!< SRAMTODININT (Bit 4)                                  */
29079 #define CRYPTO_HOSTRGFIRR_SRAMTODININT_Msk (0x10UL)                 /*!< SRAMTODININT (Bitfield-Mask: 0x01)                    */
29080 /* ======================================================  HOSTRGFIMR  ======================================================= */
29081 #define CRYPTO_HOSTRGFIMR_SYMDMACOMPLETEDMASK_Pos (11UL)            /*!< SYMDMACOMPLETEDMASK (Bit 11)                          */
29082 #define CRYPTO_HOSTRGFIMR_SYMDMACOMPLETEDMASK_Msk (0x800UL)         /*!< SYMDMACOMPLETEDMASK (Bitfield-Mask: 0x01)             */
29083 #define CRYPTO_HOSTRGFIMR_RNGINTMASK_Pos  (10UL)                    /*!< RNGINTMASK (Bit 10)                                   */
29084 #define CRYPTO_HOSTRGFIMR_RNGINTMASK_Msk  (0x400UL)                 /*!< RNGINTMASK (Bitfield-Mask: 0x01)                      */
29085 #define CRYPTO_HOSTRGFIMR_PKAEXPMASK_Pos  (9UL)                     /*!< PKAEXPMASK (Bit 9)                                    */
29086 #define CRYPTO_HOSTRGFIMR_PKAEXPMASK_Msk  (0x200UL)                 /*!< PKAEXPMASK (Bitfield-Mask: 0x01)                      */
29087 #define CRYPTO_HOSTRGFIMR_AXIERRMASK_Pos  (8UL)                     /*!< AXIERRMASK (Bit 8)                                    */
29088 #define CRYPTO_HOSTRGFIMR_AXIERRMASK_Msk  (0x100UL)                 /*!< AXIERRMASK (Bitfield-Mask: 0x01)                      */
29089 #define CRYPTO_HOSTRGFIMR_DOUTTOMEMMASK_Pos (7UL)                   /*!< DOUTTOMEMMASK (Bit 7)                                 */
29090 #define CRYPTO_HOSTRGFIMR_DOUTTOMEMMASK_Msk (0x80UL)                /*!< DOUTTOMEMMASK (Bitfield-Mask: 0x01)                   */
29091 #define CRYPTO_HOSTRGFIMR_MEMTODINMASK_Pos (6UL)                    /*!< MEMTODINMASK (Bit 6)                                  */
29092 #define CRYPTO_HOSTRGFIMR_MEMTODINMASK_Msk (0x40UL)                 /*!< MEMTODINMASK (Bitfield-Mask: 0x01)                    */
29093 #define CRYPTO_HOSTRGFIMR_DOUTTOSRAMMASK_Pos (5UL)                  /*!< DOUTTOSRAMMASK (Bit 5)                                */
29094 #define CRYPTO_HOSTRGFIMR_DOUTTOSRAMMASK_Msk (0x20UL)               /*!< DOUTTOSRAMMASK (Bitfield-Mask: 0x01)                  */
29095 #define CRYPTO_HOSTRGFIMR_SRAMTODINMASK_Pos (4UL)                   /*!< SRAMTODINMASK (Bit 4)                                 */
29096 #define CRYPTO_HOSTRGFIMR_SRAMTODINMASK_Msk (0x10UL)                /*!< SRAMTODINMASK (Bitfield-Mask: 0x01)                   */
29097 /* ======================================================  HOSTRGFICR  ======================================================= */
29098 #define CRYPTO_HOSTRGFICR_SYMDMACOMPLETEDCLEAR_Pos (11UL)           /*!< SYMDMACOMPLETEDCLEAR (Bit 11)                         */
29099 #define CRYPTO_HOSTRGFICR_SYMDMACOMPLETEDCLEAR_Msk (0x800UL)        /*!< SYMDMACOMPLETEDCLEAR (Bitfield-Mask: 0x01)            */
29100 #define CRYPTO_HOSTRGFICR_RNGINTCLEAR_Pos (10UL)                    /*!< RNGINTCLEAR (Bit 10)                                  */
29101 #define CRYPTO_HOSTRGFICR_RNGINTCLEAR_Msk (0x400UL)                 /*!< RNGINTCLEAR (Bitfield-Mask: 0x01)                     */
29102 #define CRYPTO_HOSTRGFICR_PKAEXPCLEAR_Pos (9UL)                     /*!< PKAEXPCLEAR (Bit 9)                                   */
29103 #define CRYPTO_HOSTRGFICR_PKAEXPCLEAR_Msk (0x200UL)                 /*!< PKAEXPCLEAR (Bitfield-Mask: 0x01)                     */
29104 #define CRYPTO_HOSTRGFICR_AXIERRCLEAR_Pos (8UL)                     /*!< AXIERRCLEAR (Bit 8)                                   */
29105 #define CRYPTO_HOSTRGFICR_AXIERRCLEAR_Msk (0x100UL)                 /*!< AXIERRCLEAR (Bitfield-Mask: 0x01)                     */
29106 #define CRYPTO_HOSTRGFICR_DOUTTOMEMCLEAR_Pos (7UL)                  /*!< DOUTTOMEMCLEAR (Bit 7)                                */
29107 #define CRYPTO_HOSTRGFICR_DOUTTOMEMCLEAR_Msk (0x80UL)               /*!< DOUTTOMEMCLEAR (Bitfield-Mask: 0x01)                  */
29108 #define CRYPTO_HOSTRGFICR_MEMTODINCLEAR_Pos (6UL)                   /*!< MEMTODINCLEAR (Bit 6)                                 */
29109 #define CRYPTO_HOSTRGFICR_MEMTODINCLEAR_Msk (0x40UL)                /*!< MEMTODINCLEAR (Bitfield-Mask: 0x01)                   */
29110 #define CRYPTO_HOSTRGFICR_DOUTTOSRAMCLEAR_Pos (5UL)                 /*!< DOUTTOSRAMCLEAR (Bit 5)                               */
29111 #define CRYPTO_HOSTRGFICR_DOUTTOSRAMCLEAR_Msk (0x20UL)              /*!< DOUTTOSRAMCLEAR (Bitfield-Mask: 0x01)                 */
29112 #define CRYPTO_HOSTRGFICR_SRAMTODINCLEAR_Pos (4UL)                  /*!< SRAMTODINCLEAR (Bit 4)                                */
29113 #define CRYPTO_HOSTRGFICR_SRAMTODINCLEAR_Msk (0x10UL)               /*!< SRAMTODINCLEAR (Bitfield-Mask: 0x01)                  */
29114 /* =====================================================  HOSTRGFENDIAN  ===================================================== */
29115 #define CRYPTO_HOSTRGFENDIAN_DINRDWBG_Pos (15UL)                    /*!< DINRDWBG (Bit 15)                                     */
29116 #define CRYPTO_HOSTRGFENDIAN_DINRDWBG_Msk (0x8000UL)                /*!< DINRDWBG (Bitfield-Mask: 0x01)                        */
29117 #define CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Pos (11UL)                   /*!< DOUTWRWBG (Bit 11)                                    */
29118 #define CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Msk (0x800UL)                /*!< DOUTWRWBG (Bitfield-Mask: 0x01)                       */
29119 #define CRYPTO_HOSTRGFENDIAN_DINRDBG_Pos  (7UL)                     /*!< DINRDBG (Bit 7)                                       */
29120 #define CRYPTO_HOSTRGFENDIAN_DINRDBG_Msk  (0x80UL)                  /*!< DINRDBG (Bitfield-Mask: 0x01)                         */
29121 #define CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Pos (3UL)                     /*!< DOUTWRBG (Bit 3)                                      */
29122 #define CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Msk (0x8UL)                   /*!< DOUTWRBG (Bitfield-Mask: 0x01)                        */
29123 /* ===================================================  HOSTRGFSIGNATURE  ==================================================== */
29124 #define CRYPTO_HOSTRGFSIGNATURE_HOSTSIGNATURE_Pos (0UL)             /*!< HOSTSIGNATURE (Bit 0)                                 */
29125 #define CRYPTO_HOSTRGFSIGNATURE_HOSTSIGNATURE_Msk (0xffffffffUL)    /*!< HOSTSIGNATURE (Bitfield-Mask: 0xffffffff)             */
29126 /* =======================================================  HOSTBOOT  ======================================================== */
29127 #define CRYPTO_HOSTBOOT_AESEXISTSLOCAL_Pos (30UL)                   /*!< AESEXISTSLOCAL (Bit 30)                               */
29128 #define CRYPTO_HOSTBOOT_AESEXISTSLOCAL_Msk (0x40000000UL)           /*!< AESEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29129 #define CRYPTO_HOSTBOOT_ONLYENCRYPTLOCAL_Pos (29UL)                 /*!< ONLYENCRYPTLOCAL (Bit 29)                             */
29130 #define CRYPTO_HOSTBOOT_ONLYENCRYPTLOCAL_Msk (0x20000000UL)         /*!< ONLYENCRYPTLOCAL (Bitfield-Mask: 0x01)                */
29131 #define CRYPTO_HOSTBOOT_SUPPORT256192KEYLOCAL_Pos (28UL)            /*!< SUPPORT256192KEYLOCAL (Bit 28)                        */
29132 #define CRYPTO_HOSTBOOT_SUPPORT256192KEYLOCAL_Msk (0x10000000UL)    /*!< SUPPORT256192KEYLOCAL (Bitfield-Mask: 0x01)           */
29133 #define CRYPTO_HOSTBOOT_TUNNELINGENBLOCAL_Pos (27UL)                /*!< TUNNELINGENBLOCAL (Bit 27)                            */
29134 #define CRYPTO_HOSTBOOT_TUNNELINGENBLOCAL_Msk (0x8000000UL)         /*!< TUNNELINGENBLOCAL (Bitfield-Mask: 0x01)               */
29135 #define CRYPTO_HOSTBOOT_AESDINBYTERESOLUTIONLOCAL_Pos (26UL)        /*!< AESDINBYTERESOLUTIONLOCAL (Bit 26)                    */
29136 #define CRYPTO_HOSTBOOT_AESDINBYTERESOLUTIONLOCAL_Msk (0x4000000UL) /*!< AESDINBYTERESOLUTIONLOCAL (Bitfield-Mask: 0x01)       */
29137 #define CRYPTO_HOSTBOOT_CTREXISTSLOCAL_Pos (25UL)                   /*!< CTREXISTSLOCAL (Bit 25)                               */
29138 #define CRYPTO_HOSTBOOT_CTREXISTSLOCAL_Msk (0x2000000UL)            /*!< CTREXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29139 #define CRYPTO_HOSTBOOT_AESXEXEXISTSLOCAL_Pos (24UL)                /*!< AESXEXEXISTSLOCAL (Bit 24)                            */
29140 #define CRYPTO_HOSTBOOT_AESXEXEXISTSLOCAL_Msk (0x1000000UL)         /*!< AESXEXEXISTSLOCAL (Bitfield-Mask: 0x01)               */
29141 #define CRYPTO_HOSTBOOT_AESXEXHWTCALCLOCAL_Pos (23UL)               /*!< AESXEXHWTCALCLOCAL (Bit 23)                           */
29142 #define CRYPTO_HOSTBOOT_AESXEXHWTCALCLOCAL_Msk (0x800000UL)         /*!< AESXEXHWTCALCLOCAL (Bitfield-Mask: 0x01)              */
29143 #define CRYPTO_HOSTBOOT_AESCCMEXISTSLOCAL_Pos (22UL)                /*!< AESCCMEXISTSLOCAL (Bit 22)                            */
29144 #define CRYPTO_HOSTBOOT_AESCCMEXISTSLOCAL_Msk (0x400000UL)          /*!< AESCCMEXISTSLOCAL (Bitfield-Mask: 0x01)               */
29145 #define CRYPTO_HOSTBOOT_AESCMACEXISTSLOCAL_Pos (21UL)               /*!< AESCMACEXISTSLOCAL (Bit 21)                           */
29146 #define CRYPTO_HOSTBOOT_AESCMACEXISTSLOCAL_Msk (0x200000UL)         /*!< AESCMACEXISTSLOCAL (Bitfield-Mask: 0x01)              */
29147 #define CRYPTO_HOSTBOOT_AESXCBCMACEXISTSLOCAL_Pos (20UL)            /*!< AESXCBCMACEXISTSLOCAL (Bit 20)                        */
29148 #define CRYPTO_HOSTBOOT_AESXCBCMACEXISTSLOCAL_Msk (0x100000UL)      /*!< AESXCBCMACEXISTSLOCAL (Bitfield-Mask: 0x01)           */
29149 #define CRYPTO_HOSTBOOT_DESEXISTSLOCAL_Pos (19UL)                   /*!< DESEXISTSLOCAL (Bit 19)                               */
29150 #define CRYPTO_HOSTBOOT_DESEXISTSLOCAL_Msk (0x80000UL)              /*!< DESEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29151 #define CRYPTO_HOSTBOOT_C2EXISTSLOCAL_Pos (18UL)                    /*!< C2EXISTSLOCAL (Bit 18)                                */
29152 #define CRYPTO_HOSTBOOT_C2EXISTSLOCAL_Msk (0x40000UL)               /*!< C2EXISTSLOCAL (Bitfield-Mask: 0x01)                   */
29153 #define CRYPTO_HOSTBOOT_HASHEXISTSLOCAL_Pos (17UL)                  /*!< HASHEXISTSLOCAL (Bit 17)                              */
29154 #define CRYPTO_HOSTBOOT_HASHEXISTSLOCAL_Msk (0x20000UL)             /*!< HASHEXISTSLOCAL (Bitfield-Mask: 0x01)                 */
29155 #define CRYPTO_HOSTBOOT_MD5PRSNTLOCAL_Pos (16UL)                    /*!< MD5PRSNTLOCAL (Bit 16)                                */
29156 #define CRYPTO_HOSTBOOT_MD5PRSNTLOCAL_Msk (0x10000UL)               /*!< MD5PRSNTLOCAL (Bitfield-Mask: 0x01)                   */
29157 #define CRYPTO_HOSTBOOT_SHA256PRSNTLOCAL_Pos (15UL)                 /*!< SHA256PRSNTLOCAL (Bit 15)                             */
29158 #define CRYPTO_HOSTBOOT_SHA256PRSNTLOCAL_Msk (0x8000UL)             /*!< SHA256PRSNTLOCAL (Bitfield-Mask: 0x01)                */
29159 #define CRYPTO_HOSTBOOT_SHA512PRSNTLOCAL_Pos (14UL)                 /*!< SHA512PRSNTLOCAL (Bit 14)                             */
29160 #define CRYPTO_HOSTBOOT_SHA512PRSNTLOCAL_Msk (0x4000UL)             /*!< SHA512PRSNTLOCAL (Bitfield-Mask: 0x01)                */
29161 #define CRYPTO_HOSTBOOT_RC4EXISTSLOCAL_Pos (13UL)                   /*!< RC4EXISTSLOCAL (Bit 13)                               */
29162 #define CRYPTO_HOSTBOOT_RC4EXISTSLOCAL_Msk (0x2000UL)               /*!< RC4EXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29163 #define CRYPTO_HOSTBOOT_PKAEXISTSLOCAL_Pos (12UL)                   /*!< PKAEXISTSLOCAL (Bit 12)                               */
29164 #define CRYPTO_HOSTBOOT_PKAEXISTSLOCAL_Msk (0x1000UL)               /*!< PKAEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29165 #define CRYPTO_HOSTBOOT_RNGEXISTSLOCAL_Pos (11UL)                   /*!< RNGEXISTSLOCAL (Bit 11)                               */
29166 #define CRYPTO_HOSTBOOT_RNGEXISTSLOCAL_Msk (0x800UL)                /*!< RNGEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29167 #define CRYPTO_HOSTBOOT_PAUEXISTSLOCAL_Pos (10UL)                   /*!< PAUEXISTSLOCAL (Bit 10)                               */
29168 #define CRYPTO_HOSTBOOT_PAUEXISTSLOCAL_Msk (0x400UL)                /*!< PAUEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29169 #define CRYPTO_HOSTBOOT_DSCRPTREXISTSLOCAL_Pos (9UL)                /*!< DSCRPTREXISTSLOCAL (Bit 9)                            */
29170 #define CRYPTO_HOSTBOOT_DSCRPTREXISTSLOCAL_Msk (0x200UL)            /*!< DSCRPTREXISTSLOCAL (Bitfield-Mask: 0x01)              */
29171 #define CRYPTO_HOSTBOOT_SRAMSIZELOCAL_Pos (6UL)                     /*!< SRAMSIZELOCAL (Bit 6)                                 */
29172 #define CRYPTO_HOSTBOOT_SRAMSIZELOCAL_Msk (0x1c0UL)                 /*!< SRAMSIZELOCAL (Bitfield-Mask: 0x07)                   */
29173 #define CRYPTO_HOSTBOOT_RKEKECCEXISTSLOCALN_Pos (5UL)               /*!< RKEKECCEXISTSLOCALN (Bit 5)                           */
29174 #define CRYPTO_HOSTBOOT_RKEKECCEXISTSLOCALN_Msk (0x20UL)            /*!< RKEKECCEXISTSLOCALN (Bitfield-Mask: 0x01)             */
29175 #define CRYPTO_HOSTBOOT_EXTMEMSECUREDLOCAL_Pos (3UL)                /*!< EXTMEMSECUREDLOCAL (Bit 3)                            */
29176 #define CRYPTO_HOSTBOOT_EXTMEMSECUREDLOCAL_Msk (0x8UL)              /*!< EXTMEMSECUREDLOCAL (Bitfield-Mask: 0x01)              */
29177 #define CRYPTO_HOSTBOOT_HASHINFUSESLOCAL_Pos (2UL)                  /*!< HASHINFUSESLOCAL (Bit 2)                              */
29178 #define CRYPTO_HOSTBOOT_HASHINFUSESLOCAL_Msk (0x4UL)                /*!< HASHINFUSESLOCAL (Bitfield-Mask: 0x01)                */
29179 #define CRYPTO_HOSTBOOT_LARGERKEKLOCAL_Pos (1UL)                    /*!< LARGERKEKLOCAL (Bit 1)                                */
29180 #define CRYPTO_HOSTBOOT_LARGERKEKLOCAL_Msk (0x2UL)                  /*!< LARGERKEKLOCAL (Bitfield-Mask: 0x01)                  */
29181 #define CRYPTO_HOSTBOOT_SYNTHESISCONFIG_Pos (0UL)                   /*!< SYNTHESISCONFIG (Bit 0)                               */
29182 #define CRYPTO_HOSTBOOT_SYNTHESISCONFIG_Msk (0x1UL)                 /*!< SYNTHESISCONFIG (Bitfield-Mask: 0x01)                 */
29183 /* ===================================================  HOSTCRYPTOKEYSEL  ==================================================== */
29184 #define CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Pos (0UL)              /*!< SELCRYPTOKEY (Bit 0)                                  */
29185 #define CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Msk (0x7UL)            /*!< SELCRYPTOKEY (Bitfield-Mask: 0x07)                    */
29186 /* ================================================  HOSTCORECLKGATINGENABLE  ================================================ */
29187 #define CRYPTO_HOSTCORECLKGATINGENABLE_HOSTCORECLKGATINGENABLE_Pos (0UL) /*!< HOSTCORECLKGATINGENABLE (Bit 0)                  */
29188 #define CRYPTO_HOSTCORECLKGATINGENABLE_HOSTCORECLKGATINGENABLE_Msk (0x1UL) /*!< HOSTCORECLKGATINGENABLE (Bitfield-Mask: 0x01)  */
29189 /* =====================================================  HOSTCCISIDLE  ====================================================== */
29190 #define CRYPTO_HOSTCCISIDLE_CRYPTOISIDLE_Pos (9UL)                  /*!< CRYPTOISIDLE (Bit 9)                                  */
29191 #define CRYPTO_HOSTCCISIDLE_CRYPTOISIDLE_Msk (0x200UL)              /*!< CRYPTOISIDLE (Bitfield-Mask: 0x01)                    */
29192 #define CRYPTO_HOSTCCISIDLE_PKAISIDLE_Pos (8UL)                     /*!< PKAISIDLE (Bit 8)                                     */
29193 #define CRYPTO_HOSTCCISIDLE_PKAISIDLE_Msk (0x100UL)                 /*!< PKAISIDLE (Bitfield-Mask: 0x01)                       */
29194 #define CRYPTO_HOSTCCISIDLE_RNGISIDLE_Pos (7UL)                     /*!< RNGISIDLE (Bit 7)                                     */
29195 #define CRYPTO_HOSTCCISIDLE_RNGISIDLE_Msk (0x80UL)                  /*!< RNGISIDLE (Bitfield-Mask: 0x01)                       */
29196 #define CRYPTO_HOSTCCISIDLE_FATALWR_Pos   (6UL)                     /*!< FATALWR (Bit 6)                                       */
29197 #define CRYPTO_HOSTCCISIDLE_FATALWR_Msk   (0x40UL)                  /*!< FATALWR (Bitfield-Mask: 0x01)                         */
29198 #define CRYPTO_HOSTCCISIDLE_NVMISIDLE_Pos (5UL)                     /*!< NVMISIDLE (Bit 5)                                     */
29199 #define CRYPTO_HOSTCCISIDLE_NVMISIDLE_Msk (0x20UL)                  /*!< NVMISIDLE (Bitfield-Mask: 0x01)                       */
29200 #define CRYPTO_HOSTCCISIDLE_NVMARBISIDLE_Pos (4UL)                  /*!< NVMARBISIDLE (Bit 4)                                  */
29201 #define CRYPTO_HOSTCCISIDLE_NVMARBISIDLE_Msk (0x10UL)               /*!< NVMARBISIDLE (Bitfield-Mask: 0x01)                    */
29202 #define CRYPTO_HOSTCCISIDLE_AHBISIDLE_Pos (3UL)                     /*!< AHBISIDLE (Bit 3)                                     */
29203 #define CRYPTO_HOSTCCISIDLE_AHBISIDLE_Msk (0x8UL)                   /*!< AHBISIDLE (Bitfield-Mask: 0x01)                       */
29204 #define CRYPTO_HOSTCCISIDLE_SYMISBUSY_Pos (2UL)                     /*!< SYMISBUSY (Bit 2)                                     */
29205 #define CRYPTO_HOSTCCISIDLE_SYMISBUSY_Msk (0x4UL)                   /*!< SYMISBUSY (Bitfield-Mask: 0x01)                       */
29206 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLEEVENT_Pos (1UL)             /*!< HOSTCCISIDLEEVENT (Bit 1)                             */
29207 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLEEVENT_Msk (0x2UL)           /*!< HOSTCCISIDLEEVENT (Bitfield-Mask: 0x01)               */
29208 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLE_Pos (0UL)                  /*!< HOSTCCISIDLE (Bit 0)                                  */
29209 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLE_Msk (0x1UL)                /*!< HOSTCCISIDLE (Bitfield-Mask: 0x01)                    */
29210 /* =====================================================  HOSTPOWERDOWN  ===================================================== */
29211 #define CRYPTO_HOSTPOWERDOWN_HOSTPOWERDOWN_Pos (0UL)                /*!< HOSTPOWERDOWN (Bit 0)                                 */
29212 #define CRYPTO_HOSTPOWERDOWN_HOSTPOWERDOWN_Msk (0x1UL)              /*!< HOSTPOWERDOWN (Bitfield-Mask: 0x01)                   */
29213 /* =================================================  HOSTREMOVEGHASHENGINE  ================================================= */
29214 #define CRYPTO_HOSTREMOVEGHASHENGINE_HOSTREMOVEGHASHENGINE_Pos (0UL) /*!< HOSTREMOVEGHASHENGINE (Bit 0)                        */
29215 #define CRYPTO_HOSTREMOVEGHASHENGINE_HOSTREMOVEGHASHENGINE_Msk (0x1UL) /*!< HOSTREMOVEGHASHENGINE (Bitfield-Mask: 0x01)        */
29216 /* ================================================  HOSTREMOVECHACHAENGINE  ================================================= */
29217 #define CRYPTO_HOSTREMOVECHACHAENGINE_HOSTREMOVECHACHAENGINE_Pos (0UL) /*!< HOSTREMOVECHACHAENGINE (Bit 0)                     */
29218 #define CRYPTO_HOSTREMOVECHACHAENGINE_HOSTREMOVECHACHAENGINE_Msk (0x1UL) /*!< HOSTREMOVECHACHAENGINE (Bitfield-Mask: 0x01)     */
29219 /* ======================================================  AHBMSINGLES  ====================================================== */
29220 #define CRYPTO_AHBMSINGLES_AHBSINGLES_Pos (0UL)                     /*!< AHBSINGLES (Bit 0)                                    */
29221 #define CRYPTO_AHBMSINGLES_AHBSINGLES_Msk (0x1UL)                   /*!< AHBSINGLES (Bitfield-Mask: 0x01)                      */
29222 /* =======================================================  AHBMHPROT  ======================================================= */
29223 #define CRYPTO_AHBMHPROT_AHBPROT_Pos      (0UL)                     /*!< AHBPROT (Bit 0)                                       */
29224 #define CRYPTO_AHBMHPROT_AHBPROT_Msk      (0xfUL)                   /*!< AHBPROT (Bitfield-Mask: 0x0f)                         */
29225 /* =====================================================  AHBMHMASTLOCK  ===================================================== */
29226 #define CRYPTO_AHBMHMASTLOCK_AHBHMASTLOCK_Pos (0UL)                 /*!< AHBHMASTLOCK (Bit 0)                                  */
29227 #define CRYPTO_AHBMHMASTLOCK_AHBHMASTLOCK_Msk (0x1UL)               /*!< AHBHMASTLOCK (Bitfield-Mask: 0x01)                    */
29228 /* ======================================================  AHBMHNONSEC  ====================================================== */
29229 #define CRYPTO_AHBMHNONSEC_AHBREADHNONSEC_Pos (1UL)                 /*!< AHBREADHNONSEC (Bit 1)                                */
29230 #define CRYPTO_AHBMHNONSEC_AHBREADHNONSEC_Msk (0x2UL)               /*!< AHBREADHNONSEC (Bitfield-Mask: 0x01)                  */
29231 #define CRYPTO_AHBMHNONSEC_AHBWRITEHNONSEC_Pos (0UL)                /*!< AHBWRITEHNONSEC (Bit 0)                               */
29232 #define CRYPTO_AHBMHNONSEC_AHBWRITEHNONSEC_Msk (0x1UL)              /*!< AHBWRITEHNONSEC (Bitfield-Mask: 0x01)                 */
29233 /* =======================================================  DINBUFFER  ======================================================= */
29234 #define CRYPTO_DINBUFFER_DINBUFFERDATA_Pos (0UL)                    /*!< DINBUFFERDATA (Bit 0)                                 */
29235 #define CRYPTO_DINBUFFER_DINBUFFERDATA_Msk (0xffffffffUL)           /*!< DINBUFFERDATA (Bitfield-Mask: 0xffffffff)             */
29236 /* =====================================================  DINMEMDMABUSY  ===================================================== */
29237 #define CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Pos (0UL)                /*!< DINMEMDMABUSY (Bit 0)                                 */
29238 #define CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Msk (0x1UL)              /*!< DINMEMDMABUSY (Bitfield-Mask: 0x01)                   */
29239 /* ======================================================  SRCLLIWORD0  ====================================================== */
29240 #define CRYPTO_SRCLLIWORD0_SRCLLIWORD0_Pos (0UL)                    /*!< SRCLLIWORD0 (Bit 0)                                   */
29241 #define CRYPTO_SRCLLIWORD0_SRCLLIWORD0_Msk (0xffffffffUL)           /*!< SRCLLIWORD0 (Bitfield-Mask: 0xffffffff)               */
29242 /* ======================================================  SRCLLIWORD1  ====================================================== */
29243 #define CRYPTO_SRCLLIWORD1_LAST_Pos       (31UL)                    /*!< LAST (Bit 31)                                         */
29244 #define CRYPTO_SRCLLIWORD1_LAST_Msk       (0x80000000UL)            /*!< LAST (Bitfield-Mask: 0x01)                            */
29245 #define CRYPTO_SRCLLIWORD1_FIRST_Pos      (30UL)                    /*!< FIRST (Bit 30)                                        */
29246 #define CRYPTO_SRCLLIWORD1_FIRST_Msk      (0x40000000UL)            /*!< FIRST (Bitfield-Mask: 0x01)                           */
29247 #define CRYPTO_SRCLLIWORD1_BYTESNUM_Pos   (0UL)                     /*!< BYTESNUM (Bit 0)                                      */
29248 #define CRYPTO_SRCLLIWORD1_BYTESNUM_Msk   (0x3fffffffUL)            /*!< BYTESNUM (Bitfield-Mask: 0x3fffffff)                  */
29249 /* ======================================================  SRAMSRCADDR  ====================================================== */
29250 #define CRYPTO_SRAMSRCADDR_SRAMSOURCE_Pos (0UL)                     /*!< SRAMSOURCE (Bit 0)                                    */
29251 #define CRYPTO_SRAMSRCADDR_SRAMSOURCE_Msk (0xffffffffUL)            /*!< SRAMSOURCE (Bitfield-Mask: 0xffffffff)                */
29252 /* ====================================================  DINSRAMBYTESLEN  ==================================================== */
29253 #define CRYPTO_DINSRAMBYTESLEN_BYTESLEN_Pos (0UL)                   /*!< BYTESLEN (Bit 0)                                      */
29254 #define CRYPTO_DINSRAMBYTESLEN_BYTESLEN_Msk (0xffffffffUL)          /*!< BYTESLEN (Bitfield-Mask: 0xffffffff)                  */
29255 /* ====================================================  DINSRAMDMABUSY  ===================================================== */
29256 #define CRYPTO_DINSRAMDMABUSY_BUSY_Pos    (0UL)                     /*!< BUSY (Bit 0)                                          */
29257 #define CRYPTO_DINSRAMDMABUSY_BUSY_Msk    (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
29258 /* ===================================================  DINSRAMENDIANNESS  =================================================== */
29259 #define CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Pos (0UL)        /*!< SRAMDINENDIANNESS (Bit 0)                             */
29260 #define CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Msk (0x1UL)      /*!< SRAMDINENDIANNESS (Bitfield-Mask: 0x01)               */
29261 /* ====================================================  DINCPUDATASIZE  ===================================================== */
29262 #define CRYPTO_DINCPUDATASIZE_CPUDINSIZE_Pos (0UL)                  /*!< CPUDINSIZE (Bit 0)                                    */
29263 #define CRYPTO_DINCPUDATASIZE_CPUDINSIZE_Msk (0xffffUL)             /*!< CPUDINSIZE (Bitfield-Mask: 0xffff)                    */
29264 /* ======================================================  FIFOINEMPTY  ====================================================== */
29265 #define CRYPTO_FIFOINEMPTY_EMPTY_Pos      (0UL)                     /*!< EMPTY (Bit 0)                                         */
29266 #define CRYPTO_FIFOINEMPTY_EMPTY_Msk      (0x1UL)                   /*!< EMPTY (Bitfield-Mask: 0x01)                           */
29267 /* ====================================================  DINFIFORSTPNTR  ===================================================== */
29268 #define CRYPTO_DINFIFORSTPNTR_RST_Pos     (0UL)                     /*!< RST (Bit 0)                                           */
29269 #define CRYPTO_DINFIFORSTPNTR_RST_Msk     (0x1UL)                   /*!< RST (Bitfield-Mask: 0x01)                             */
29270 /* ======================================================  DOUTBUFFER  ======================================================= */
29271 #define CRYPTO_DOUTBUFFER_DATA_Pos        (0UL)                     /*!< DATA (Bit 0)                                          */
29272 #define CRYPTO_DOUTBUFFER_DATA_Msk        (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
29273 /* ====================================================  DOUTMEMDMABUSY  ===================================================== */
29274 #define CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Pos (0UL)              /*!< DOUTMEMDMABUSY (Bit 0)                                */
29275 #define CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Msk (0x1UL)            /*!< DOUTMEMDMABUSY (Bitfield-Mask: 0x01)                  */
29276 /* ======================================================  DSTLLIWORD0  ====================================================== */
29277 #define CRYPTO_DSTLLIWORD0_DSTLLIWORD0_Pos (0UL)                    /*!< DSTLLIWORD0 (Bit 0)                                   */
29278 #define CRYPTO_DSTLLIWORD0_DSTLLIWORD0_Msk (0xffffffffUL)           /*!< DSTLLIWORD0 (Bitfield-Mask: 0xffffffff)               */
29279 /* ======================================================  DSTLLIWORD1  ====================================================== */
29280 #define CRYPTO_DSTLLIWORD1_LAST_Pos       (31UL)                    /*!< LAST (Bit 31)                                         */
29281 #define CRYPTO_DSTLLIWORD1_LAST_Msk       (0x80000000UL)            /*!< LAST (Bitfield-Mask: 0x01)                            */
29282 #define CRYPTO_DSTLLIWORD1_FIRST_Pos      (30UL)                    /*!< FIRST (Bit 30)                                        */
29283 #define CRYPTO_DSTLLIWORD1_FIRST_Msk      (0x40000000UL)            /*!< FIRST (Bitfield-Mask: 0x01)                           */
29284 #define CRYPTO_DSTLLIWORD1_BYTESNUM_Pos   (0UL)                     /*!< BYTESNUM (Bit 0)                                      */
29285 #define CRYPTO_DSTLLIWORD1_BYTESNUM_Msk   (0x3fffffffUL)            /*!< BYTESNUM (Bitfield-Mask: 0x3fffffff)                  */
29286 /* =====================================================  SRAMDESTADDR  ====================================================== */
29287 #define CRYPTO_SRAMDESTADDR_SRAMDEST_Pos  (0UL)                     /*!< SRAMDEST (Bit 0)                                      */
29288 #define CRYPTO_SRAMDESTADDR_SRAMDEST_Msk  (0xffffffffUL)            /*!< SRAMDEST (Bitfield-Mask: 0xffffffff)                  */
29289 /* ===================================================  DOUTSRAMBYTESLEN  ==================================================== */
29290 #define CRYPTO_DOUTSRAMBYTESLEN_BYTESLEN_Pos (0UL)                  /*!< BYTESLEN (Bit 0)                                      */
29291 #define CRYPTO_DOUTSRAMBYTESLEN_BYTESLEN_Msk (0xffffffffUL)         /*!< BYTESLEN (Bitfield-Mask: 0xffffffff)                  */
29292 /* ====================================================  DOUTSRAMDMABUSY  ==================================================== */
29293 #define CRYPTO_DOUTSRAMDMABUSY_BUSY_Pos   (0UL)                     /*!< BUSY (Bit 0)                                          */
29294 #define CRYPTO_DOUTSRAMDMABUSY_BUSY_Msk   (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
29295 /* ==================================================  DOUTSRAMENDIANNESS  =================================================== */
29296 #define CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Pos (0UL)      /*!< DOUTSRAMENDIANNESS (Bit 0)                            */
29297 #define CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Msk (0x1UL)    /*!< DOUTSRAMENDIANNESS (Bitfield-Mask: 0x01)              */
29298 /* =====================================================  READALIGNLAST  ===================================================== */
29299 #define CRYPTO_READALIGNLAST_LAST_Pos     (0UL)                     /*!< LAST (Bit 0)                                          */
29300 #define CRYPTO_READALIGNLAST_LAST_Msk     (0x1UL)                   /*!< LAST (Bitfield-Mask: 0x01)                            */
29301 /* =====================================================  DOUTFIFOEMPTY  ===================================================== */
29302 #define CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Pos (0UL)                /*!< DOUTFIFOEMPTY (Bit 0)                                 */
29303 #define CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Msk (0x1UL)              /*!< DOUTFIFOEMPTY (Bitfield-Mask: 0x01)                   */
29304 /* =======================================================  SRAMDATA  ======================================================== */
29305 #define CRYPTO_SRAMDATA_SRAMDATA_Pos      (0UL)                     /*!< SRAMDATA (Bit 0)                                      */
29306 #define CRYPTO_SRAMDATA_SRAMDATA_Msk      (0xffffffffUL)            /*!< SRAMDATA (Bitfield-Mask: 0xffffffff)                  */
29307 /* =======================================================  SRAMADDR  ======================================================== */
29308 #define CRYPTO_SRAMADDR_SRAMADDR_Pos      (0UL)                     /*!< SRAMADDR (Bit 0)                                      */
29309 #define CRYPTO_SRAMADDR_SRAMADDR_Msk      (0x7fffUL)                /*!< SRAMADDR (Bitfield-Mask: 0x7fff)                      */
29310 /* =====================================================  SRAMDATAREADY  ===================================================== */
29311 #define CRYPTO_SRAMDATAREADY_SRAMREADY_Pos (0UL)                    /*!< SRAMREADY (Bit 0)                                     */
29312 #define CRYPTO_SRAMDATAREADY_SRAMREADY_Msk (0x1UL)                  /*!< SRAMREADY (Bitfield-Mask: 0x01)                       */
29313 /* =====================================================  PERIPHERALID4  ===================================================== */
29314 #define CRYPTO_PERIPHERALID4_DES2JEP106_Pos (0UL)                   /*!< DES2JEP106 (Bit 0)                                    */
29315 #define CRYPTO_PERIPHERALID4_DES2JEP106_Msk (0xfUL)                 /*!< DES2JEP106 (Bitfield-Mask: 0x0f)                      */
29316 /* =====================================================  PERIPHERALID0  ===================================================== */
29317 #define CRYPTO_PERIPHERALID0_PART0_Pos    (0UL)                     /*!< PART0 (Bit 0)                                         */
29318 #define CRYPTO_PERIPHERALID0_PART0_Msk    (0xffUL)                  /*!< PART0 (Bitfield-Mask: 0xff)                           */
29319 /* =====================================================  PERIPHERALID1  ===================================================== */
29320 #define CRYPTO_PERIPHERALID1_DES0JEP106_Pos (4UL)                   /*!< DES0JEP106 (Bit 4)                                    */
29321 #define CRYPTO_PERIPHERALID1_DES0JEP106_Msk (0xf0UL)                /*!< DES0JEP106 (Bitfield-Mask: 0x0f)                      */
29322 #define CRYPTO_PERIPHERALID1_PART1_Pos    (0UL)                     /*!< PART1 (Bit 0)                                         */
29323 #define CRYPTO_PERIPHERALID1_PART1_Msk    (0xfUL)                   /*!< PART1 (Bitfield-Mask: 0x0f)                           */
29324 /* =====================================================  PERIPHERALID2  ===================================================== */
29325 #define CRYPTO_PERIPHERALID2_REVISION_Pos (4UL)                     /*!< REVISION (Bit 4)                                      */
29326 #define CRYPTO_PERIPHERALID2_REVISION_Msk (0xf0UL)                  /*!< REVISION (Bitfield-Mask: 0x0f)                        */
29327 #define CRYPTO_PERIPHERALID2_JEDEC_Pos    (3UL)                     /*!< JEDEC (Bit 3)                                         */
29328 #define CRYPTO_PERIPHERALID2_JEDEC_Msk    (0x8UL)                   /*!< JEDEC (Bitfield-Mask: 0x01)                           */
29329 #define CRYPTO_PERIPHERALID2_DES1JEP106_Pos (0UL)                   /*!< DES1JEP106 (Bit 0)                                    */
29330 #define CRYPTO_PERIPHERALID2_DES1JEP106_Msk (0x7UL)                 /*!< DES1JEP106 (Bitfield-Mask: 0x07)                      */
29331 /* =====================================================  PERIPHERALID3  ===================================================== */
29332 #define CRYPTO_PERIPHERALID3_REVAND_Pos   (4UL)                     /*!< REVAND (Bit 4)                                        */
29333 #define CRYPTO_PERIPHERALID3_REVAND_Msk   (0xf0UL)                  /*!< REVAND (Bitfield-Mask: 0x0f)                          */
29334 #define CRYPTO_PERIPHERALID3_CMOD_Pos     (0UL)                     /*!< CMOD (Bit 0)                                          */
29335 #define CRYPTO_PERIPHERALID3_CMOD_Msk     (0xfUL)                   /*!< CMOD (Bitfield-Mask: 0x0f)                            */
29336 /* =====================================================  COMPONENTID0  ====================================================== */
29337 #define CRYPTO_COMPONENTID0_PRMBL0_Pos    (0UL)                     /*!< PRMBL0 (Bit 0)                                        */
29338 #define CRYPTO_COMPONENTID0_PRMBL0_Msk    (0xffUL)                  /*!< PRMBL0 (Bitfield-Mask: 0xff)                          */
29339 /* =====================================================  COMPONENTID1  ====================================================== */
29340 #define CRYPTO_COMPONENTID1_CLASS_Pos     (4UL)                     /*!< CLASS (Bit 4)                                         */
29341 #define CRYPTO_COMPONENTID1_CLASS_Msk     (0xf0UL)                  /*!< CLASS (Bitfield-Mask: 0x0f)                           */
29342 #define CRYPTO_COMPONENTID1_PRMBL1_Pos    (0UL)                     /*!< PRMBL1 (Bit 0)                                        */
29343 #define CRYPTO_COMPONENTID1_PRMBL1_Msk    (0xfUL)                   /*!< PRMBL1 (Bitfield-Mask: 0x0f)                          */
29344 /* =====================================================  COMPONENTID2  ====================================================== */
29345 #define CRYPTO_COMPONENTID2_PRMBL2_Pos    (0UL)                     /*!< PRMBL2 (Bit 0)                                        */
29346 #define CRYPTO_COMPONENTID2_PRMBL2_Msk    (0xffUL)                  /*!< PRMBL2 (Bitfield-Mask: 0xff)                          */
29347 /* =====================================================  COMPONENTID3  ====================================================== */
29348 #define CRYPTO_COMPONENTID3_PRMBL3_Pos    (0UL)                     /*!< PRMBL3 (Bit 0)                                        */
29349 #define CRYPTO_COMPONENTID3_PRMBL3_Msk    (0xffUL)                  /*!< PRMBL3 (Bitfield-Mask: 0xff)                          */
29350 /* ======================================================  HOSTDCUEN0  ======================================================= */
29351 #define CRYPTO_HOSTDCUEN0_HOSTDCUEN0_Pos  (0UL)                     /*!< HOSTDCUEN0 (Bit 0)                                    */
29352 #define CRYPTO_HOSTDCUEN0_HOSTDCUEN0_Msk  (0xffffffffUL)            /*!< HOSTDCUEN0 (Bitfield-Mask: 0xffffffff)                */
29353 /* ======================================================  HOSTDCUEN1  ======================================================= */
29354 #define CRYPTO_HOSTDCUEN1_HOSTDCUEN1_Pos  (0UL)                     /*!< HOSTDCUEN1 (Bit 0)                                    */
29355 #define CRYPTO_HOSTDCUEN1_HOSTDCUEN1_Msk  (0xffffffffUL)            /*!< HOSTDCUEN1 (Bitfield-Mask: 0xffffffff)                */
29356 /* ======================================================  HOSTDCUEN2  ======================================================= */
29357 #define CRYPTO_HOSTDCUEN2_HOSTDCUEN2_Pos  (0UL)                     /*!< HOSTDCUEN2 (Bit 0)                                    */
29358 #define CRYPTO_HOSTDCUEN2_HOSTDCUEN2_Msk  (0xffffffffUL)            /*!< HOSTDCUEN2 (Bitfield-Mask: 0xffffffff)                */
29359 /* ======================================================  HOSTDCUEN3  ======================================================= */
29360 #define CRYPTO_HOSTDCUEN3_HOSTDCUEN3_Pos  (0UL)                     /*!< HOSTDCUEN3 (Bit 0)                                    */
29361 #define CRYPTO_HOSTDCUEN3_HOSTDCUEN3_Msk  (0xffffffffUL)            /*!< HOSTDCUEN3 (Bitfield-Mask: 0xffffffff)                */
29362 /* =====================================================  HOSTDCULOCK0  ====================================================== */
29363 #define CRYPTO_HOSTDCULOCK0_HOSTDCULOCK0_Pos (0UL)                  /*!< HOSTDCULOCK0 (Bit 0)                                  */
29364 #define CRYPTO_HOSTDCULOCK0_HOSTDCULOCK0_Msk (0xffffffffUL)         /*!< HOSTDCULOCK0 (Bitfield-Mask: 0xffffffff)              */
29365 /* =====================================================  HOSTDCULOCK1  ====================================================== */
29366 #define CRYPTO_HOSTDCULOCK1_HOSTDCULOCK1_Pos (0UL)                  /*!< HOSTDCULOCK1 (Bit 0)                                  */
29367 #define CRYPTO_HOSTDCULOCK1_HOSTDCULOCK1_Msk (0xffffffffUL)         /*!< HOSTDCULOCK1 (Bitfield-Mask: 0xffffffff)              */
29368 /* =====================================================  HOSTDCULOCK2  ====================================================== */
29369 #define CRYPTO_HOSTDCULOCK2_HOSTDCULOCK2_Pos (0UL)                  /*!< HOSTDCULOCK2 (Bit 0)                                  */
29370 #define CRYPTO_HOSTDCULOCK2_HOSTDCULOCK2_Msk (0xffffffffUL)         /*!< HOSTDCULOCK2 (Bitfield-Mask: 0xffffffff)              */
29371 /* =====================================================  HOSTDCULOCK3  ====================================================== */
29372 #define CRYPTO_HOSTDCULOCK3_HOSTDCULOCK3_Pos (0UL)                  /*!< HOSTDCULOCK3 (Bit 0)                                  */
29373 #define CRYPTO_HOSTDCULOCK3_HOSTDCULOCK3_Msk (0xffffffffUL)         /*!< HOSTDCULOCK3 (Bitfield-Mask: 0xffffffff)              */
29374 /* ===============================================  AOICVDCURESTRICTIONMASK0  ================================================ */
29375 #define CRYPTO_AOICVDCURESTRICTIONMASK0_AOICVDCURESTRICTIONMASK0_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK0 (Bit 0)               */
29376 #define CRYPTO_AOICVDCURESTRICTIONMASK0_AOICVDCURESTRICTIONMASK0_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK0 (Bitfield-Mask: 0xffffffff) */
29377 /* ===============================================  AOICVDCURESTRICTIONMASK1  ================================================ */
29378 #define CRYPTO_AOICVDCURESTRICTIONMASK1_AOICVDCURESTRICTIONMASK1_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK1 (Bit 0)               */
29379 #define CRYPTO_AOICVDCURESTRICTIONMASK1_AOICVDCURESTRICTIONMASK1_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK1 (Bitfield-Mask: 0xffffffff) */
29380 /* ===============================================  AOICVDCURESTRICTIONMASK2  ================================================ */
29381 #define CRYPTO_AOICVDCURESTRICTIONMASK2_AOICVDCURESTRICTIONMASK2_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK2 (Bit 0)               */
29382 #define CRYPTO_AOICVDCURESTRICTIONMASK2_AOICVDCURESTRICTIONMASK2_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK2 (Bitfield-Mask: 0xffffffff) */
29383 /* ===============================================  AOICVDCURESTRICTIONMASK3  ================================================ */
29384 #define CRYPTO_AOICVDCURESTRICTIONMASK3_AOICVDCURESTRICTIONMASK3_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK3 (Bit 0)               */
29385 #define CRYPTO_AOICVDCURESTRICTIONMASK3_AOICVDCURESTRICTIONMASK3_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK3 (Bitfield-Mask: 0xffffffff) */
29386 /* ===================================================  AOCCSECDEBUGRESET  =================================================== */
29387 #define CRYPTO_AOCCSECDEBUGRESET_AOCCSECDEBUGRESET_Pos (0UL)        /*!< AOCCSECDEBUGRESET (Bit 0)                             */
29388 #define CRYPTO_AOCCSECDEBUGRESET_AOCCSECDEBUGRESET_Msk (0x1UL)      /*!< AOCCSECDEBUGRESET (Bitfield-Mask: 0x01)               */
29389 /* ====================================================  HOSTAOLOCKBITS  ===================================================== */
29390 #define CRYPTO_HOSTAOLOCKBITS_HOSTDFAENABLELOCK_Pos (8UL)           /*!< HOSTDFAENABLELOCK (Bit 8)                             */
29391 #define CRYPTO_HOSTAOLOCKBITS_HOSTDFAENABLELOCK_Msk (0x100UL)       /*!< HOSTDFAENABLELOCK (Bitfield-Mask: 0x01)               */
29392 #define CRYPTO_HOSTAOLOCKBITS_HOSTFORCEDFAENABLE_Pos (7UL)          /*!< HOSTFORCEDFAENABLE (Bit 7)                            */
29393 #define CRYPTO_HOSTAOLOCKBITS_HOSTFORCEDFAENABLE_Msk (0x80UL)       /*!< HOSTFORCEDFAENABLE (Bitfield-Mask: 0x01)              */
29394 #define CRYPTO_HOSTAOLOCKBITS_RESETUPONDEBUGDISABLE_Pos (6UL)       /*!< RESETUPONDEBUGDISABLE (Bit 6)                         */
29395 #define CRYPTO_HOSTAOLOCKBITS_RESETUPONDEBUGDISABLE_Msk (0x40UL)    /*!< RESETUPONDEBUGDISABLE (Bitfield-Mask: 0x01)           */
29396 #define CRYPTO_HOSTAOLOCKBITS_HOSTICVRMALOCK_Pos (5UL)              /*!< HOSTICVRMALOCK (Bit 5)                                */
29397 #define CRYPTO_HOSTAOLOCKBITS_HOSTICVRMALOCK_Msk (0x20UL)           /*!< HOSTICVRMALOCK (Bitfield-Mask: 0x01)                  */
29398 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCELOCK_Pos (4UL)                 /*!< HOSTKCELOCK (Bit 4)                                   */
29399 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCELOCK_Msk (0x10UL)              /*!< HOSTKCELOCK (Bitfield-Mask: 0x01)                     */
29400 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCPLOCK_Pos (3UL)                 /*!< HOSTKCPLOCK (Bit 3)                                   */
29401 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCPLOCK_Msk (0x8UL)               /*!< HOSTKCPLOCK (Bitfield-Mask: 0x01)                     */
29402 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCEICVLOCK_Pos (2UL)              /*!< HOSTKCEICVLOCK (Bit 2)                                */
29403 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCEICVLOCK_Msk (0x4UL)            /*!< HOSTKCEICVLOCK (Bitfield-Mask: 0x01)                  */
29404 #define CRYPTO_HOSTAOLOCKBITS_HOSTKPICVLOCK_Pos (1UL)               /*!< HOSTKPICVLOCK (Bit 1)                                 */
29405 #define CRYPTO_HOSTAOLOCKBITS_HOSTKPICVLOCK_Msk (0x2UL)             /*!< HOSTKPICVLOCK (Bitfield-Mask: 0x01)                   */
29406 #define CRYPTO_HOSTAOLOCKBITS_HOSTFATALERR_Pos (0UL)                /*!< HOSTFATALERR (Bit 0)                                  */
29407 #define CRYPTO_HOSTAOLOCKBITS_HOSTFATALERR_Msk (0x1UL)              /*!< HOSTFATALERR (Bitfield-Mask: 0x01)                    */
29408 /* ====================================================  AOAPBFILTERING  ===================================================== */
29409 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOWLOCK_Pos (9UL) /*!< APBCONLYINSTACCESSALLOWLOCK (Bit 9)                   */
29410 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOWLOCK_Msk (0x200UL) /*!< APBCONLYINSTACCESSALLOWLOCK (Bitfield-Mask: 0x01) */
29411 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOW_Pos (8UL)     /*!< APBCONLYINSTACCESSALLOW (Bit 8)                       */
29412 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOW_Msk (0x100UL) /*!< APBCONLYINSTACCESSALLOW (Bitfield-Mask: 0x01)         */
29413 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOWLOCK_Pos (7UL) /*!< APBCONLYPRIVACCESSALLOWLOCK (Bit 7)                   */
29414 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOWLOCK_Msk (0x80UL) /*!< APBCONLYPRIVACCESSALLOWLOCK (Bitfield-Mask: 0x01)  */
29415 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOW_Pos (6UL)     /*!< APBCONLYPRIVACCESSALLOW (Bit 6)                       */
29416 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOW_Msk (0x40UL)  /*!< APBCONLYPRIVACCESSALLOW (Bitfield-Mask: 0x01)         */
29417 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOWLOCK_Pos (5UL)  /*!< APBCONLYSECACCESSALLOWLOCK (Bit 5)                    */
29418 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOWLOCK_Msk (0x20UL) /*!< APBCONLYSECACCESSALLOWLOCK (Bitfield-Mask: 0x01)    */
29419 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOW_Pos (4UL)      /*!< APBCONLYSECACCESSALLOW (Bit 4)                        */
29420 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOW_Msk (0x10UL)   /*!< APBCONLYSECACCESSALLOW (Bitfield-Mask: 0x01)          */
29421 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOWLOCK_Pos (3UL)     /*!< ONLYPRIVACCESSALLOWLOCK (Bit 3)                       */
29422 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOWLOCK_Msk (0x8UL)   /*!< ONLYPRIVACCESSALLOWLOCK (Bitfield-Mask: 0x01)         */
29423 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOW_Pos (2UL)         /*!< ONLYPRIVACCESSALLOW (Bit 2)                           */
29424 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOW_Msk (0x4UL)       /*!< ONLYPRIVACCESSALLOW (Bitfield-Mask: 0x01)             */
29425 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOWLOCK_Pos (1UL)      /*!< ONLYSECACCESSALLOWLOCK (Bit 1)                        */
29426 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOWLOCK_Msk (0x2UL)    /*!< ONLYSECACCESSALLOWLOCK (Bitfield-Mask: 0x01)          */
29427 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOW_Pos (0UL)          /*!< ONLYSECACCESSALLOW (Bit 0)                            */
29428 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOW_Msk (0x1UL)        /*!< ONLYSECACCESSALLOW (Bitfield-Mask: 0x01)              */
29429 /* =======================================================  AOCCGPPC  ======================================================== */
29430 #define CRYPTO_AOCCGPPC_AOCCGPPC_Pos      (0UL)                     /*!< AOCCGPPC (Bit 0)                                      */
29431 #define CRYPTO_AOCCGPPC_AOCCGPPC_Msk      (0xffUL)                  /*!< AOCCGPPC (Bitfield-Mask: 0xff)                        */
29432 /* ====================================================  HOSTRGFCCSWRST  ===================================================== */
29433 #define CRYPTO_HOSTRGFCCSWRST_HOSTRGFCCSWRST_Pos (0UL)              /*!< HOSTRGFCCSWRST (Bit 0)                                */
29434 #define CRYPTO_HOSTRGFCCSWRST_HOSTRGFCCSWRST_Msk (0x1UL)            /*!< HOSTRGFCCSWRST (Bitfield-Mask: 0x01)                  */
29435 /* =================================================  AIBFUSEPROGCOMPLETED  ================================================== */
29436 #define CRYPTO_AIBFUSEPROGCOMPLETED_AIBFUSEPROGCOMPLETED_Pos (0UL)  /*!< AIBFUSEPROGCOMPLETED (Bit 0)                          */
29437 #define CRYPTO_AIBFUSEPROGCOMPLETED_AIBFUSEPROGCOMPLETED_Msk (0x1UL) /*!< AIBFUSEPROGCOMPLETED (Bitfield-Mask: 0x01)           */
29438 /* ====================================================  NVMDEBUGSTATUS  ===================================================== */
29439 #define CRYPTO_NVMDEBUGSTATUS_NVMSM_Pos   (1UL)                     /*!< NVMSM (Bit 1)                                         */
29440 #define CRYPTO_NVMDEBUGSTATUS_NVMSM_Msk   (0xeUL)                   /*!< NVMSM (Bitfield-Mask: 0x07)                           */
29441 /* ======================================================  LCSISVALID  ======================================================= */
29442 #define CRYPTO_LCSISVALID_LCSISVALIDREG_Pos (0UL)                   /*!< LCSISVALIDREG (Bit 0)                                 */
29443 #define CRYPTO_LCSISVALID_LCSISVALIDREG_Msk (0x1UL)                 /*!< LCSISVALIDREG (Bitfield-Mask: 0x01)                   */
29444 /* =======================================================  NVMISIDLE  ======================================================= */
29445 #define CRYPTO_NVMISIDLE_NVMISIDLEREG_Pos (0UL)                     /*!< NVMISIDLEREG (Bit 0)                                  */
29446 #define CRYPTO_NVMISIDLE_NVMISIDLEREG_Msk (0x1UL)                   /*!< NVMISIDLEREG (Bitfield-Mask: 0x01)                    */
29447 /* ========================================================  LCSREG  ========================================================= */
29448 #define CRYPTO_LCSREG_ERRORKCEICVZEROCNT_Pos (12UL)                 /*!< ERRORKCEICVZEROCNT (Bit 12)                           */
29449 #define CRYPTO_LCSREG_ERRORKCEICVZEROCNT_Msk (0x1000UL)             /*!< ERRORKCEICVZEROCNT (Bitfield-Mask: 0x01)              */
29450 #define CRYPTO_LCSREG_ERRORKPICVZEROCNT_Pos (11UL)                  /*!< ERRORKPICVZEROCNT (Bit 11)                            */
29451 #define CRYPTO_LCSREG_ERRORKPICVZEROCNT_Msk (0x800UL)               /*!< ERRORKPICVZEROCNT (Bitfield-Mask: 0x01)               */
29452 #define CRYPTO_LCSREG_ERRORKCEZEROCNT_Pos (10UL)                    /*!< ERRORKCEZEROCNT (Bit 10)                              */
29453 #define CRYPTO_LCSREG_ERRORKCEZEROCNT_Msk (0x400UL)                 /*!< ERRORKCEZEROCNT (Bitfield-Mask: 0x01)                 */
29454 #define CRYPTO_LCSREG_ERRORPROVZEROCNT_Pos (9UL)                    /*!< ERRORPROVZEROCNT (Bit 9)                              */
29455 #define CRYPTO_LCSREG_ERRORPROVZEROCNT_Msk (0x200UL)                /*!< ERRORPROVZEROCNT (Bitfield-Mask: 0x01)                */
29456 #define CRYPTO_LCSREG_ERRORKDRZEROCNT_Pos (8UL)                     /*!< ERRORKDRZEROCNT (Bit 8)                               */
29457 #define CRYPTO_LCSREG_ERRORKDRZEROCNT_Msk (0x100UL)                 /*!< ERRORKDRZEROCNT (Bitfield-Mask: 0x01)                 */
29458 #define CRYPTO_LCSREG_LCSREG_Pos          (0UL)                     /*!< LCSREG (Bit 0)                                        */
29459 #define CRYPTO_LCSREG_LCSREG_Msk          (0x7UL)                   /*!< LCSREG (Bitfield-Mask: 0x07)                          */
29460 /* ===================================================  HOSTSHADOWKDRREG  ==================================================== */
29461 #define CRYPTO_HOSTSHADOWKDRREG_HOSTSHADOWKDRREG_Pos (0UL)          /*!< HOSTSHADOWKDRREG (Bit 0)                              */
29462 #define CRYPTO_HOSTSHADOWKDRREG_HOSTSHADOWKDRREG_Msk (0x1UL)        /*!< HOSTSHADOWKDRREG (Bitfield-Mask: 0x01)                */
29463 /* ===================================================  HOSTSHADOWKCPREG  ==================================================== */
29464 #define CRYPTO_HOSTSHADOWKCPREG_HOSTSHADOWKCPREG_Pos (0UL)          /*!< HOSTSHADOWKCPREG (Bit 0)                              */
29465 #define CRYPTO_HOSTSHADOWKCPREG_HOSTSHADOWKCPREG_Msk (0x1UL)        /*!< HOSTSHADOWKCPREG (Bitfield-Mask: 0x01)                */
29466 /* ===================================================  HOSTSHADOWKCEREG  ==================================================== */
29467 #define CRYPTO_HOSTSHADOWKCEREG_HOSTSHADOWKCEREG_Pos (0UL)          /*!< HOSTSHADOWKCEREG (Bit 0)                              */
29468 #define CRYPTO_HOSTSHADOWKCEREG_HOSTSHADOWKCEREG_Msk (0x1UL)        /*!< HOSTSHADOWKCEREG (Bitfield-Mask: 0x01)                */
29469 /* ==================================================  HOSTSHADOWKPICVREG  =================================================== */
29470 #define CRYPTO_HOSTSHADOWKPICVREG_HOSTSHADOWKPICVREG_Pos (0UL)      /*!< HOSTSHADOWKPICVREG (Bit 0)                            */
29471 #define CRYPTO_HOSTSHADOWKPICVREG_HOSTSHADOWKPICVREG_Msk (0x1UL)    /*!< HOSTSHADOWKPICVREG (Bitfield-Mask: 0x01)              */
29472 /* ==================================================  HOSTSHADOWKCEICVREG  ================================================== */
29473 #define CRYPTO_HOSTSHADOWKCEICVREG_HOSTSHADOWKCEICVREG_Pos (0UL)    /*!< HOSTSHADOWKCEICVREG (Bit 0)                           */
29474 #define CRYPTO_HOSTSHADOWKCEICVREG_HOSTSHADOWKCEICVREG_Msk (0x1UL)  /*!< HOSTSHADOWKCEICVREG (Bitfield-Mask: 0x01)             */
29475 /* ====================================================  OTPADDRWIDTHDEF  ==================================================== */
29476 #define CRYPTO_OTPADDRWIDTHDEF_OTPADDRWIDTHDEF_Pos (0UL)            /*!< OTPADDRWIDTHDEF (Bit 0)                               */
29477 #define CRYPTO_OTPADDRWIDTHDEF_OTPADDRWIDTHDEF_Msk (0xfUL)          /*!< OTPADDRWIDTHDEF (Bitfield-Mask: 0x0f)                 */
29478 
29479 
29480 /* =========================================================================================================================== */
29481 /* ================                                            DC                                             ================ */
29482 /* =========================================================================================================================== */
29483 
29484 /* =========================================================  MODE  ========================================================== */
29485 #define DC_MODE_DC400ACT_Pos              (31UL)                    /*!< DC400ACT (Bit 31)                                     */
29486 #define DC_MODE_DC400ACT_Msk              (0x80000000UL)            /*!< DC400ACT (Bitfield-Mask: 0x01)                        */
29487 #define DC_MODE_CUSOREN_Pos               (30UL)                    /*!< CUSOREN (Bit 30)                                      */
29488 #define DC_MODE_CUSOREN_Msk               (0x40000000UL)            /*!< CUSOREN (Bitfield-Mask: 0x01)                         */
29489 #define DC_MODE_RSVD4_Pos                 (29UL)                    /*!< RSVD4 (Bit 29)                                        */
29490 #define DC_MODE_RSVD4_Msk                 (0x20000000UL)            /*!< RSVD4 (Bitfield-Mask: 0x01)                           */
29491 #define DC_MODE_VSYNCPOL_Pos              (28UL)                    /*!< VSYNCPOL (Bit 28)                                     */
29492 #define DC_MODE_VSYNCPOL_Msk              (0x10000000UL)            /*!< VSYNCPOL (Bitfield-Mask: 0x01)                        */
29493 #define DC_MODE_HSYNCPOL_Pos              (27UL)                    /*!< HSYNCPOL (Bit 27)                                     */
29494 #define DC_MODE_HSYNCPOL_Msk              (0x8000000UL)             /*!< HSYNCPOL (Bitfield-Mask: 0x01)                        */
29495 #define DC_MODE_DEPOL_Pos                 (26UL)                    /*!< DEPOL (Bit 26)                                        */
29496 #define DC_MODE_DEPOL_Msk                 (0x4000000UL)             /*!< DEPOL (Bitfield-Mask: 0x01)                           */
29497 #define DC_MODE_RSVD3_Pos                 (25UL)                    /*!< RSVD3 (Bit 25)                                        */
29498 #define DC_MODE_RSVD3_Msk                 (0x2000000UL)             /*!< RSVD3 (Bitfield-Mask: 0x01)                           */
29499 #define DC_MODE_DITHEREN_Pos              (24UL)                    /*!< DITHEREN (Bit 24)                                     */
29500 #define DC_MODE_DITHEREN_Msk              (0x1000000UL)             /*!< DITHEREN (Bitfield-Mask: 0x01)                        */
29501 #define DC_MODE_VSYNCEN_Pos               (23UL)                    /*!< VSYNCEN (Bit 23)                                      */
29502 #define DC_MODE_VSYNCEN_Msk               (0x800000UL)              /*!< VSYNCEN (Bitfield-Mask: 0x01)                         */
29503 #define DC_MODE_PIXCLKPOL_Pos             (22UL)                    /*!< PIXCLKPOL (Bit 22)                                    */
29504 #define DC_MODE_PIXCLKPOL_Msk             (0x400000UL)              /*!< PIXCLKPOL (Bitfield-Mask: 0x01)                       */
29505 #define DC_MODE_RSVD2_Pos                 (21UL)                    /*!< RSVD2 (Bit 21)                                        */
29506 #define DC_MODE_RSVD2_Msk                 (0x200000UL)              /*!< RSVD2 (Bitfield-Mask: 0x01)                           */
29507 #define DC_MODE_GAMARAMPEN_Pos            (20UL)                    /*!< GAMARAMPEN (Bit 20)                                   */
29508 #define DC_MODE_GAMARAMPEN_Msk            (0x100000UL)              /*!< GAMARAMPEN (Bitfield-Mask: 0x01)                      */
29509 #define DC_MODE_BLANKFRC_Pos              (19UL)                    /*!< BLANKFRC (Bit 19)                                     */
29510 #define DC_MODE_BLANKFRC_Msk              (0x80000UL)               /*!< BLANKFRC (Bitfield-Mask: 0x01)                        */
29511 #define DC_MODE_RSVD1_Pos                 (18UL)                    /*!< RSVD1 (Bit 18)                                        */
29512 #define DC_MODE_RSVD1_Msk                 (0x40000UL)               /*!< RSVD1 (Bitfield-Mask: 0x01)                           */
29513 #define DC_MODE_FRAMEUPDTEN_Pos           (17UL)                    /*!< FRAMEUPDTEN (Bit 17)                                  */
29514 #define DC_MODE_FRAMEUPDTEN_Msk           (0x20000UL)               /*!< FRAMEUPDTEN (Bitfield-Mask: 0x01)                     */
29515 #define DC_MODE_RSVD0_Pos                 (12UL)                    /*!< RSVD0 (Bit 12)                                        */
29516 #define DC_MODE_RSVD0_Msk                 (0x1f000UL)               /*!< RSVD0 (Bitfield-Mask: 0x1f)                           */
29517 #define DC_MODE_PLLCLKNDIV_Pos            (11UL)                    /*!< PLLCLKNDIV (Bit 11)                                   */
29518 #define DC_MODE_PLLCLKNDIV_Msk            (0x800UL)                 /*!< PLLCLKNDIV (Bitfield-Mask: 0x01)                      */
29519 #define DC_MODE_LVDSPADSEN_Pos            (10UL)                    /*!< LVDSPADSEN (Bit 10)                                   */
29520 #define DC_MODE_LVDSPADSEN_Msk            (0x400UL)                 /*!< LVDSPADSEN (Bitfield-Mask: 0x01)                      */
29521 #define DC_MODE_COLFMT_Pos                (9UL)                     /*!< COLFMT (Bit 9)                                        */
29522 #define DC_MODE_COLFMT_Msk                (0x200UL)                 /*!< COLFMT (Bitfield-Mask: 0x01)                          */
29523 #define DC_MODE_DISPFMT_Pos               (5UL)                     /*!< DISPFMT (Bit 5)                                       */
29524 #define DC_MODE_DISPFMT_Msk               (0x1e0UL)                 /*!< DISPFMT (Bitfield-Mask: 0x0f)                         */
29525 #define DC_MODE_DBITYPEBEN_Pos            (4UL)                     /*!< DBITYPEBEN (Bit 4)                                    */
29526 #define DC_MODE_DBITYPEBEN_Msk            (0x10UL)                  /*!< DBITYPEBEN (Bitfield-Mask: 0x01)                      */
29527 #define DC_MODE_YUYVEN_Pos                (3UL)                     /*!< YUYVEN (Bit 3)                                        */
29528 #define DC_MODE_YUYVEN_Msk                (0x8UL)                   /*!< YUYVEN (Bitfield-Mask: 0x01)                          */
29529 #define DC_MODE_LVDSINTEN_Pos             (2UL)                     /*!< LVDSINTEN (Bit 2)                                     */
29530 #define DC_MODE_LVDSINTEN_Msk             (0x4UL)                   /*!< LVDSINTEN (Bitfield-Mask: 0x01)                       */
29531 #define DC_MODE_DBLHORSCANEN_Pos          (1UL)                     /*!< DBLHORSCANEN (Bit 1)                                  */
29532 #define DC_MODE_DBLHORSCANEN_Msk          (0x2UL)                   /*!< DBLHORSCANEN (Bitfield-Mask: 0x01)                    */
29533 #define DC_MODE_TSTMODEN_Pos              (0UL)                     /*!< TSTMODEN (Bit 0)                                      */
29534 #define DC_MODE_TSTMODEN_Msk              (0x1UL)                   /*!< TSTMODEN (Bitfield-Mask: 0x01)                        */
29535 /* ========================================================  CLKCTRL  ======================================================== */
29536 #define DC_CLKCTRL_SECCLKDIV_Pos          (27UL)                    /*!< SECCLKDIV (Bit 27)                                    */
29537 #define DC_CLKCTRL_SECCLKDIV_Msk          (0xf8000000UL)            /*!< SECCLKDIV (Bitfield-Mask: 0x1f)                       */
29538 #define DC_CLKCTRL_LVDS_Pos               (24UL)                    /*!< LVDS (Bit 24)                                         */
29539 #define DC_CLKCTRL_LVDS_Msk               (0x7000000UL)             /*!< LVDS (Bitfield-Mask: 0x07)                            */
29540 #define DC_CLKCTRL_PLL_Pos                (16UL)                    /*!< PLL (Bit 16)                                          */
29541 #define DC_CLKCTRL_PLL_Msk                (0xff0000UL)              /*!< PLL (Bitfield-Mask: 0xff)                             */
29542 #define DC_CLKCTRL_RSVD1_Pos              (14UL)                    /*!< RSVD1 (Bit 14)                                        */
29543 #define DC_CLKCTRL_RSVD1_Msk              (0xc000UL)                /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
29544 #define DC_CLKCTRL_LINENUM_Pos            (8UL)                     /*!< LINENUM (Bit 8)                                       */
29545 #define DC_CLKCTRL_LINENUM_Msk            (0x3f00UL)                /*!< LINENUM (Bitfield-Mask: 0x3f)                         */
29546 #define DC_CLKCTRL_RSVD0_Pos              (6UL)                     /*!< RSVD0 (Bit 6)                                         */
29547 #define DC_CLKCTRL_RSVD0_Msk              (0xc0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x03)                           */
29548 #define DC_CLKCTRL_DIVIDEVALUE_Pos        (0UL)                     /*!< DIVIDEVALUE (Bit 0)                                   */
29549 #define DC_CLKCTRL_DIVIDEVALUE_Msk        (0x3fUL)                  /*!< DIVIDEVALUE (Bitfield-Mask: 0x3f)                     */
29550 /* ========================================================  BGCOLOR  ======================================================== */
29551 #define DC_BGCOLOR_REDCOLOR_Pos           (24UL)                    /*!< REDCOLOR (Bit 24)                                     */
29552 #define DC_BGCOLOR_REDCOLOR_Msk           (0xff000000UL)            /*!< REDCOLOR (Bitfield-Mask: 0xff)                        */
29553 #define DC_BGCOLOR_GREENCOLOR_Pos         (16UL)                    /*!< GREENCOLOR (Bit 16)                                   */
29554 #define DC_BGCOLOR_GREENCOLOR_Msk         (0xff0000UL)              /*!< GREENCOLOR (Bitfield-Mask: 0xff)                      */
29555 #define DC_BGCOLOR_BLUECOLOR_Pos          (8UL)                     /*!< BLUECOLOR (Bit 8)                                     */
29556 #define DC_BGCOLOR_BLUECOLOR_Msk          (0xff00UL)                /*!< BLUECOLOR (Bitfield-Mask: 0xff)                       */
29557 #define DC_BGCOLOR_ALPHACOLOR_Pos         (0UL)                     /*!< ALPHACOLOR (Bit 0)                                    */
29558 #define DC_BGCOLOR_ALPHACOLOR_Msk         (0xffUL)                  /*!< ALPHACOLOR (Bitfield-Mask: 0xff)                      */
29559 /* =========================================================  RESXY  ========================================================= */
29560 #define DC_RESXY_XRES_Pos                 (16UL)                    /*!< XRES (Bit 16)                                         */
29561 #define DC_RESXY_XRES_Msk                 (0xffff0000UL)            /*!< XRES (Bitfield-Mask: 0xffff)                          */
29562 #define DC_RESXY_YRES_Pos                 (0UL)                     /*!< YRES (Bit 0)                                          */
29563 #define DC_RESXY_YRES_Msk                 (0xffffUL)                /*!< YRES (Bitfield-Mask: 0xffff)                          */
29564 /* =====================================================  FRONTPORCHXY  ====================================================== */
29565 #define DC_FRONTPORCHXY_FPCLKCYCLES_Pos   (16UL)                    /*!< FPCLKCYCLES (Bit 16)                                  */
29566 #define DC_FRONTPORCHXY_FPCLKCYCLES_Msk   (0xffff0000UL)            /*!< FPCLKCYCLES (Bitfield-Mask: 0xffff)                   */
29567 #define DC_FRONTPORCHXY_FLINES_Pos        (0UL)                     /*!< FLINES (Bit 0)                                        */
29568 #define DC_FRONTPORCHXY_FLINES_Msk        (0xffffUL)                /*!< FLINES (Bitfield-Mask: 0xffff)                        */
29569 /* ======================================================  BLANKINGXY  ======================================================= */
29570 #define DC_BLANKINGXY_HSYNCPULSE_Pos      (16UL)                    /*!< HSYNCPULSE (Bit 16)                                   */
29571 #define DC_BLANKINGXY_HSYNCPULSE_Msk      (0xffff0000UL)            /*!< HSYNCPULSE (Bitfield-Mask: 0xffff)                    */
29572 #define DC_BLANKINGXY_VSYNCLINES_Pos      (0UL)                     /*!< VSYNCLINES (Bit 0)                                    */
29573 #define DC_BLANKINGXY_VSYNCLINES_Msk      (0xffffUL)                /*!< VSYNCLINES (Bitfield-Mask: 0xffff)                    */
29574 /* ======================================================  BACKPORCHXY  ====================================================== */
29575 #define DC_BACKPORCHXY_BPCLKCYCLES_Pos    (16UL)                    /*!< BPCLKCYCLES (Bit 16)                                  */
29576 #define DC_BACKPORCHXY_BPCLKCYCLES_Msk    (0xffff0000UL)            /*!< BPCLKCYCLES (Bitfield-Mask: 0xffff)                   */
29577 #define DC_BACKPORCHXY_BLINES_Pos         (0UL)                     /*!< BLINES (Bit 0)                                        */
29578 #define DC_BACKPORCHXY_BLINES_Msk         (0xffffUL)                /*!< BLINES (Bitfield-Mask: 0xffff)                        */
29579 /* =======================================================  CURSORXY  ======================================================== */
29580 #define DC_CURSORXY_CURSORX_Pos           (16UL)                    /*!< CURSORX (Bit 16)                                      */
29581 #define DC_CURSORXY_CURSORX_Msk           (0xffff0000UL)            /*!< CURSORX (Bitfield-Mask: 0xffff)                       */
29582 #define DC_CURSORXY_CURSORY_Pos           (0UL)                     /*!< CURSORY (Bit 0)                                       */
29583 #define DC_CURSORXY_CURSORY_Msk           (0xffffUL)                /*!< CURSORY (Bitfield-Mask: 0xffff)                       */
29584 /* ========================================================  DBICFG  ========================================================= */
29585 #define DC_DBICFG_DBIINTACT_Pos           (31UL)                    /*!< DBIINTACT (Bit 31)                                    */
29586 #define DC_DBICFG_DBIINTACT_Msk           (0x80000000UL)            /*!< DBIINTACT (Bitfield-Mask: 0x01)                       */
29587 #define DC_DBICFG_CSXCFG_Pos              (30UL)                    /*!< CSXCFG (Bit 30)                                       */
29588 #define DC_DBICFG_CSXCFG_Msk              (0x40000000UL)            /*!< CSXCFG (Bitfield-Mask: 0x01)                          */
29589 #define DC_DBICFG_CSXSET_Pos              (29UL)                    /*!< CSXSET (Bit 29)                                       */
29590 #define DC_DBICFG_CSXSET_Msk              (0x20000000UL)            /*!< CSXSET (Bitfield-Mask: 0x01)                          */
29591 #define DC_DBICFG_DBIBTEDIS_Pos           (28UL)                    /*!< DBIBTEDIS (Bit 28)                                    */
29592 #define DC_DBICFG_DBIBTEDIS_Msk           (0x10000000UL)            /*!< DBIBTEDIS (Bitfield-Mask: 0x01)                       */
29593 #define DC_DBICFG_RSVD4_Pos               (26UL)                    /*!< RSVD4 (Bit 26)                                        */
29594 #define DC_DBICFG_RSVD4_Msk               (0xc000000UL)             /*!< RSVD4 (Bitfield-Mask: 0x03)                           */
29595 #define DC_DBICFG_RESXLOW_Pos             (25UL)                    /*!< RESXLOW (Bit 25)                                      */
29596 #define DC_DBICFG_RESXLOW_Msk             (0x2000000UL)             /*!< RESXLOW (Bitfield-Mask: 0x01)                         */
29597 #define DC_DBICFG_RSVD3_Pos               (24UL)                    /*!< RSVD3 (Bit 24)                                        */
29598 #define DC_DBICFG_RSVD3_Msk               (0x1000000UL)             /*!< RSVD3 (Bitfield-Mask: 0x01)                           */
29599 #define DC_DBICFG_SPI3_Pos                (23UL)                    /*!< SPI3 (Bit 23)                                         */
29600 #define DC_DBICFG_SPI3_Msk                (0x800000UL)              /*!< SPI3 (Bitfield-Mask: 0x01)                            */
29601 #define DC_DBICFG_SPI4_Pos                (22UL)                    /*!< SPI4 (Bit 22)                                         */
29602 #define DC_DBICFG_SPI4_Msk                (0x400000UL)              /*!< SPI4 (Bitfield-Mask: 0x01)                            */
29603 #define DC_DBICFG_RSVD2_Pos               (18UL)                    /*!< RSVD2 (Bit 18)                                        */
29604 #define DC_DBICFG_RSVD2_Msk               (0x3c0000UL)              /*!< RSVD2 (Bitfield-Mask: 0x0f)                           */
29605 #define DC_DBICFG_BINDCMDS_Pos            (17UL)                    /*!< BINDCMDS (Bit 17)                                     */
29606 #define DC_DBICFG_BINDCMDS_Msk            (0x20000UL)               /*!< BINDCMDS (Bitfield-Mask: 0x01)                        */
29607 #define DC_DBICFG_INVHRZLINE_Pos          (16UL)                    /*!< INVHRZLINE (Bit 16)                                   */
29608 #define DC_DBICFG_INVHRZLINE_Msk          (0x10000UL)               /*!< INVHRZLINE (Bitfield-Mask: 0x01)                      */
29609 #define DC_DBICFG_RSVD1_Pos               (12UL)                    /*!< RSVD1 (Bit 12)                                        */
29610 #define DC_DBICFG_RSVD1_Msk               (0xf000UL)                /*!< RSVD1 (Bitfield-Mask: 0x0f)                           */
29611 #define DC_DBICFG_BACKPRESSUREEN_Pos      (11UL)                    /*!< BACKPRESSUREEN (Bit 11)                               */
29612 #define DC_DBICFG_BACKPRESSUREEN_Msk      (0x800UL)                 /*!< BACKPRESSUREEN (Bitfield-Mask: 0x01)                  */
29613 #define DC_DBICFG_RSVD0_Pos               (8UL)                     /*!< RSVD0 (Bit 8)                                         */
29614 #define DC_DBICFG_RSVD0_Msk               (0x700UL)                 /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
29615 #define DC_DBICFG_TYPEBWIDTH_Pos          (6UL)                     /*!< TYPEBWIDTH (Bit 6)                                    */
29616 #define DC_DBICFG_TYPEBWIDTH_Msk          (0xc0UL)                  /*!< TYPEBWIDTH (Bitfield-Mask: 0x03)                      */
29617 #define DC_DBICFG_DATAWDORDER_Pos         (3UL)                     /*!< DATAWDORDER (Bit 3)                                   */
29618 #define DC_DBICFG_DATAWDORDER_Msk         (0x38UL)                  /*!< DATAWDORDER (Bitfield-Mask: 0x07)                     */
29619 #define DC_DBICFG_DBICOLORFMT_Pos         (0UL)                     /*!< DBICOLORFMT (Bit 0)                                   */
29620 #define DC_DBICFG_DBICOLORFMT_Msk         (0x7UL)                   /*!< DBICOLORFMT (Bitfield-Mask: 0x07)                     */
29621 /* ========================================================  DCGPIO  ========================================================= */
29622 #define DC_DCGPIO_CGBYPASS_Pos            (22UL)                    /*!< CGBYPASS (Bit 22)                                     */
29623 #define DC_DCGPIO_CGBYPASS_Msk            (0xffc00000UL)            /*!< CGBYPASS (Bitfield-Mask: 0x3ff)                       */
29624 #define DC_DCGPIO_RSVD1_Pos               (9UL)                     /*!< RSVD1 (Bit 9)                                         */
29625 #define DC_DCGPIO_RSVD1_Msk               (0x3ffe00UL)              /*!< RSVD1 (Bitfield-Mask: 0x1fff)                         */
29626 #define DC_DCGPIO_ADVANCEANYWAY_Pos       (7UL)                     /*!< ADVANCEANYWAY (Bit 7)                                 */
29627 #define DC_DCGPIO_ADVANCEANYWAY_Msk       (0x180UL)                 /*!< ADVANCEANYWAY (Bitfield-Mask: 0x03)                   */
29628 #define DC_DCGPIO_RSVD0_Pos               (2UL)                     /*!< RSVD0 (Bit 2)                                         */
29629 #define DC_DCGPIO_RSVD0_Msk               (0x7cUL)                  /*!< RSVD0 (Bitfield-Mask: 0x1f)                           */
29630 #define DC_DCGPIO_RWPINS_Pos              (0UL)                     /*!< RWPINS (Bit 0)                                        */
29631 #define DC_DCGPIO_RWPINS_Msk              (0x3UL)                   /*!< RWPINS (Bitfield-Mask: 0x03)                          */
29632 /* ======================================================  LAYER0MODE  ======================================================= */
29633 #define DC_LAYER0MODE_LAYER0EN_Pos        (31UL)                    /*!< LAYER0EN (Bit 31)                                     */
29634 #define DC_LAYER0MODE_LAYER0EN_Msk        (0x80000000UL)            /*!< LAYER0EN (Bitfield-Mask: 0x01)                        */
29635 #define DC_LAYER0MODE_LAYER0FORCE_Pos     (30UL)                    /*!< LAYER0FORCE (Bit 30)                                  */
29636 #define DC_LAYER0MODE_LAYER0FORCE_Msk     (0x40000000UL)            /*!< LAYER0FORCE (Bitfield-Mask: 0x01)                     */
29637 #define DC_LAYER0MODE_LAYER0BFILTER_Pos   (29UL)                    /*!< LAYER0BFILTER (Bit 29)                                */
29638 #define DC_LAYER0MODE_LAYER0BFILTER_Msk   (0x20000000UL)            /*!< LAYER0BFILTER (Bitfield-Mask: 0x01)                   */
29639 #define DC_LAYER0MODE_LAYER0PREMULT_Pos   (28UL)                    /*!< LAYER0PREMULT (Bit 28)                                */
29640 #define DC_LAYER0MODE_LAYER0PREMULT_Msk   (0x10000000UL)            /*!< LAYER0PREMULT (Bitfield-Mask: 0x01)                   */
29641 #define DC_LAYER0MODE_LAYER0HLOCK_Pos     (27UL)                    /*!< LAYER0HLOCK (Bit 27)                                  */
29642 #define DC_LAYER0MODE_LAYER0HLOCK_Msk     (0x8000000UL)             /*!< LAYER0HLOCK (Bitfield-Mask: 0x01)                     */
29643 #define DC_LAYER0MODE_LAYER0GAMMA_Pos     (26UL)                    /*!< LAYER0GAMMA (Bit 26)                                  */
29644 #define DC_LAYER0MODE_LAYER0GAMMA_Msk     (0x4000000UL)             /*!< LAYER0GAMMA (Bitfield-Mask: 0x01)                     */
29645 #define DC_LAYER0MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
29646 #define DC_LAYER0MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
29647 #define DC_LAYER0MODE_LAYER0ALPHA_Pos     (16UL)                    /*!< LAYER0ALPHA (Bit 16)                                  */
29648 #define DC_LAYER0MODE_LAYER0ALPHA_Msk     (0xff0000UL)              /*!< LAYER0ALPHA (Bitfield-Mask: 0xff)                     */
29649 #define DC_LAYER0MODE_LAYER0DBLEND_Pos    (12UL)                    /*!< LAYER0DBLEND (Bit 12)                                 */
29650 #define DC_LAYER0MODE_LAYER0DBLEND_Msk    (0xf000UL)                /*!< LAYER0DBLEND (Bitfield-Mask: 0x0f)                    */
29651 #define DC_LAYER0MODE_LAYER0SBLEND_Pos    (8UL)                     /*!< LAYER0SBLEND (Bit 8)                                  */
29652 #define DC_LAYER0MODE_LAYER0SBLEND_Msk    (0xf00UL)                 /*!< LAYER0SBLEND (Bitfield-Mask: 0x0f)                    */
29653 #define DC_LAYER0MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
29654 #define DC_LAYER0MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
29655 #define DC_LAYER0MODE_LAYER0COLMODE_Pos   (0UL)                     /*!< LAYER0COLMODE (Bit 0)                                 */
29656 #define DC_LAYER0MODE_LAYER0COLMODE_Msk   (0x1fUL)                  /*!< LAYER0COLMODE (Bitfield-Mask: 0x1f)                   */
29657 /* =====================================================  LAYER0STARTXY  ===================================================== */
29658 #define DC_LAYER0STARTXY_LAYER0XOFF_Pos   (16UL)                    /*!< LAYER0XOFF (Bit 16)                                   */
29659 #define DC_LAYER0STARTXY_LAYER0XOFF_Msk   (0xffff0000UL)            /*!< LAYER0XOFF (Bitfield-Mask: 0xffff)                    */
29660 #define DC_LAYER0STARTXY_LAYER0YOFF_Pos   (0UL)                     /*!< LAYER0YOFF (Bit 0)                                    */
29661 #define DC_LAYER0STARTXY_LAYER0YOFF_Msk   (0xffffUL)                /*!< LAYER0YOFF (Bitfield-Mask: 0xffff)                    */
29662 /* =====================================================  LAYER0SIZEXY  ====================================================== */
29663 #define DC_LAYER0SIZEXY_LAYER0PIXSZEX_Pos (16UL)                    /*!< LAYER0PIXSZEX (Bit 16)                                */
29664 #define DC_LAYER0SIZEXY_LAYER0PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER0PIXSZEX (Bitfield-Mask: 0xffff)                 */
29665 #define DC_LAYER0SIZEXY_LAYER0PIXSZEY_Pos (0UL)                     /*!< LAYER0PIXSZEY (Bit 0)                                 */
29666 #define DC_LAYER0SIZEXY_LAYER0PIXSZEY_Msk (0xffffUL)                /*!< LAYER0PIXSZEY (Bitfield-Mask: 0xffff)                 */
29667 /* ======================================================  LAYER0ADDR  ======================================================= */
29668 #define DC_LAYER0ADDR_LAYER0STARTADDRFBUF_Pos (0UL)                 /*!< LAYER0STARTADDRFBUF (Bit 0)                           */
29669 #define DC_LAYER0ADDR_LAYER0STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER0STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
29670 /* =====================================================  LAYER0STRIDE  ====================================================== */
29671 #define DC_LAYER0STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
29672 #define DC_LAYER0STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
29673 #define DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_Pos (19UL)                /*!< LAYER0AXIFIFOTHLD (Bit 19)                            */
29674 #define DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER0AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
29675 #define DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_Pos (16UL)               /*!< LAYER0AXIBURSTBITS (Bit 16)                           */
29676 #define DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER0AXIBURSTBITS (Bitfield-Mask: 0x07)              */
29677 #define DC_LAYER0STRIDE_LAYER0STRIDEDIST_Pos (0UL)                  /*!< LAYER0STRIDEDIST (Bit 0)                              */
29678 #define DC_LAYER0STRIDE_LAYER0STRIDEDIST_Msk (0xffffUL)             /*!< LAYER0STRIDEDIST (Bitfield-Mask: 0xffff)              */
29679 /* ======================================================  LAYER0RESXY  ====================================================== */
29680 #define DC_LAYER0RESXY_LAYER0PIXRESX_Pos  (16UL)                    /*!< LAYER0PIXRESX (Bit 16)                                */
29681 #define DC_LAYER0RESXY_LAYER0PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER0PIXRESX (Bitfield-Mask: 0xffff)                 */
29682 #define DC_LAYER0RESXY_LAYER0PIXRESY_Pos  (0UL)                     /*!< LAYER0PIXRESY (Bit 0)                                 */
29683 #define DC_LAYER0RESXY_LAYER0PIXRESY_Msk  (0xffffUL)                /*!< LAYER0PIXRESY (Bitfield-Mask: 0xffff)                 */
29684 /* =====================================================  LAYER0SCALEX  ====================================================== */
29685 #define DC_LAYER0SCALEX_LAYER0XFACTOR_Pos (0UL)                     /*!< LAYER0XFACTOR (Bit 0)                                 */
29686 #define DC_LAYER0SCALEX_LAYER0XFACTOR_Msk (0xffffffffUL)            /*!< LAYER0XFACTOR (Bitfield-Mask: 0xffffffff)             */
29687 /* =====================================================  LAYER0SCALEY  ====================================================== */
29688 #define DC_LAYER0SCALEY_LAYER0YFACTOR_Pos (0UL)                     /*!< LAYER0YFACTOR (Bit 0)                                 */
29689 #define DC_LAYER0SCALEY_LAYER0YFACTOR_Msk (0xffffffffUL)            /*!< LAYER0YFACTOR (Bitfield-Mask: 0xffffffff)             */
29690 /* ======================================================  LAYER1MODE  ======================================================= */
29691 #define DC_LAYER1MODE_LAYER1EN_Pos        (31UL)                    /*!< LAYER1EN (Bit 31)                                     */
29692 #define DC_LAYER1MODE_LAYER1EN_Msk        (0x80000000UL)            /*!< LAYER1EN (Bitfield-Mask: 0x01)                        */
29693 #define DC_LAYER1MODE_LAYER1FORCE_Pos     (30UL)                    /*!< LAYER1FORCE (Bit 30)                                  */
29694 #define DC_LAYER1MODE_LAYER1FORCE_Msk     (0x40000000UL)            /*!< LAYER1FORCE (Bitfield-Mask: 0x01)                     */
29695 #define DC_LAYER1MODE_LAYER1BFILTER_Pos   (29UL)                    /*!< LAYER1BFILTER (Bit 29)                                */
29696 #define DC_LAYER1MODE_LAYER1BFILTER_Msk   (0x20000000UL)            /*!< LAYER1BFILTER (Bitfield-Mask: 0x01)                   */
29697 #define DC_LAYER1MODE_LAYER1PREMULT_Pos   (28UL)                    /*!< LAYER1PREMULT (Bit 28)                                */
29698 #define DC_LAYER1MODE_LAYER1PREMULT_Msk   (0x10000000UL)            /*!< LAYER1PREMULT (Bitfield-Mask: 0x01)                   */
29699 #define DC_LAYER1MODE_LAYER1HLOCK_Pos     (27UL)                    /*!< LAYER1HLOCK (Bit 27)                                  */
29700 #define DC_LAYER1MODE_LAYER1HLOCK_Msk     (0x8000000UL)             /*!< LAYER1HLOCK (Bitfield-Mask: 0x01)                     */
29701 #define DC_LAYER1MODE_LAYER1GAMMA_Pos     (26UL)                    /*!< LAYER1GAMMA (Bit 26)                                  */
29702 #define DC_LAYER1MODE_LAYER1GAMMA_Msk     (0x4000000UL)             /*!< LAYER1GAMMA (Bitfield-Mask: 0x01)                     */
29703 #define DC_LAYER1MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
29704 #define DC_LAYER1MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
29705 #define DC_LAYER1MODE_LAYER1ALPHA_Pos     (16UL)                    /*!< LAYER1ALPHA (Bit 16)                                  */
29706 #define DC_LAYER1MODE_LAYER1ALPHA_Msk     (0xff0000UL)              /*!< LAYER1ALPHA (Bitfield-Mask: 0xff)                     */
29707 #define DC_LAYER1MODE_LAYER1DBLEND_Pos    (12UL)                    /*!< LAYER1DBLEND (Bit 12)                                 */
29708 #define DC_LAYER1MODE_LAYER1DBLEND_Msk    (0xf000UL)                /*!< LAYER1DBLEND (Bitfield-Mask: 0x0f)                    */
29709 #define DC_LAYER1MODE_LAYER1SBLEND_Pos    (8UL)                     /*!< LAYER1SBLEND (Bit 8)                                  */
29710 #define DC_LAYER1MODE_LAYER1SBLEND_Msk    (0xf00UL)                 /*!< LAYER1SBLEND (Bitfield-Mask: 0x0f)                    */
29711 #define DC_LAYER1MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
29712 #define DC_LAYER1MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
29713 #define DC_LAYER1MODE_LAYER1COLORMODE_Pos (0UL)                     /*!< LAYER1COLORMODE (Bit 0)                               */
29714 #define DC_LAYER1MODE_LAYER1COLORMODE_Msk (0x1fUL)                  /*!< LAYER1COLORMODE (Bitfield-Mask: 0x1f)                 */
29715 /* =====================================================  LAYER1STARTXY  ===================================================== */
29716 #define DC_LAYER1STARTXY_LAYER1XOFF_Pos   (16UL)                    /*!< LAYER1XOFF (Bit 16)                                   */
29717 #define DC_LAYER1STARTXY_LAYER1XOFF_Msk   (0xffff0000UL)            /*!< LAYER1XOFF (Bitfield-Mask: 0xffff)                    */
29718 #define DC_LAYER1STARTXY_LAYER1YOFF_Pos   (0UL)                     /*!< LAYER1YOFF (Bit 0)                                    */
29719 #define DC_LAYER1STARTXY_LAYER1YOFF_Msk   (0xffffUL)                /*!< LAYER1YOFF (Bitfield-Mask: 0xffff)                    */
29720 /* =====================================================  LAYER1SIZEXY  ====================================================== */
29721 #define DC_LAYER1SIZEXY_LAYER1PIXSZEX_Pos (16UL)                    /*!< LAYER1PIXSZEX (Bit 16)                                */
29722 #define DC_LAYER1SIZEXY_LAYER1PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER1PIXSZEX (Bitfield-Mask: 0xffff)                 */
29723 #define DC_LAYER1SIZEXY_LAYER1PIXSZEY_Pos (0UL)                     /*!< LAYER1PIXSZEY (Bit 0)                                 */
29724 #define DC_LAYER1SIZEXY_LAYER1PIXSZEY_Msk (0xffffUL)                /*!< LAYER1PIXSZEY (Bitfield-Mask: 0xffff)                 */
29725 /* ======================================================  LAYER1ADDR  ======================================================= */
29726 #define DC_LAYER1ADDR_LAYER1STARTADDRFBUF_Pos (0UL)                 /*!< LAYER1STARTADDRFBUF (Bit 0)                           */
29727 #define DC_LAYER1ADDR_LAYER1STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER1STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
29728 /* =====================================================  LAYER1STRIDE  ====================================================== */
29729 #define DC_LAYER1STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
29730 #define DC_LAYER1STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
29731 #define DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_Pos (19UL)                /*!< LAYER1AXIFIFOTHLD (Bit 19)                            */
29732 #define DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER1AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
29733 #define DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_Pos (16UL)               /*!< LAYER1AXIBURSTBITS (Bit 16)                           */
29734 #define DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER1AXIBURSTBITS (Bitfield-Mask: 0x07)              */
29735 #define DC_LAYER1STRIDE_LAYER1STRIDEDIST_Pos (0UL)                  /*!< LAYER1STRIDEDIST (Bit 0)                              */
29736 #define DC_LAYER1STRIDE_LAYER1STRIDEDIST_Msk (0xffffUL)             /*!< LAYER1STRIDEDIST (Bitfield-Mask: 0xffff)              */
29737 /* ======================================================  LAYER1RESXY  ====================================================== */
29738 #define DC_LAYER1RESXY_LAYER1PIXRESX_Pos  (16UL)                    /*!< LAYER1PIXRESX (Bit 16)                                */
29739 #define DC_LAYER1RESXY_LAYER1PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER1PIXRESX (Bitfield-Mask: 0xffff)                 */
29740 #define DC_LAYER1RESXY_LAYER1PIXRESY_Pos  (0UL)                     /*!< LAYER1PIXRESY (Bit 0)                                 */
29741 #define DC_LAYER1RESXY_LAYER1PIXRESY_Msk  (0xffffUL)                /*!< LAYER1PIXRESY (Bitfield-Mask: 0xffff)                 */
29742 /* =====================================================  LAYER1SCALEX  ====================================================== */
29743 #define DC_LAYER1SCALEX_LAYER1XFACTOR_Pos (0UL)                     /*!< LAYER1XFACTOR (Bit 0)                                 */
29744 #define DC_LAYER1SCALEX_LAYER1XFACTOR_Msk (0xffffffffUL)            /*!< LAYER1XFACTOR (Bitfield-Mask: 0xffffffff)             */
29745 /* =====================================================  LAYER1SCALEY  ====================================================== */
29746 #define DC_LAYER1SCALEY_LAYER1YFACTOR_Pos (0UL)                     /*!< LAYER1YFACTOR (Bit 0)                                 */
29747 #define DC_LAYER1SCALEY_LAYER1YFACTOR_Msk (0xffffffffUL)            /*!< LAYER1YFACTOR (Bitfield-Mask: 0xffffffff)             */
29748 /* ======================================================  LAYER2MODE  ======================================================= */
29749 #define DC_LAYER2MODE_LAYER2EN_Pos        (31UL)                    /*!< LAYER2EN (Bit 31)                                     */
29750 #define DC_LAYER2MODE_LAYER2EN_Msk        (0x80000000UL)            /*!< LAYER2EN (Bitfield-Mask: 0x01)                        */
29751 #define DC_LAYER2MODE_LAYER2FORCE_Pos     (30UL)                    /*!< LAYER2FORCE (Bit 30)                                  */
29752 #define DC_LAYER2MODE_LAYER2FORCE_Msk     (0x40000000UL)            /*!< LAYER2FORCE (Bitfield-Mask: 0x01)                     */
29753 #define DC_LAYER2MODE_LAYER2BFILTER_Pos   (29UL)                    /*!< LAYER2BFILTER (Bit 29)                                */
29754 #define DC_LAYER2MODE_LAYER2BFILTER_Msk   (0x20000000UL)            /*!< LAYER2BFILTER (Bitfield-Mask: 0x01)                   */
29755 #define DC_LAYER2MODE_LAYER2PREMULT_Pos   (28UL)                    /*!< LAYER2PREMULT (Bit 28)                                */
29756 #define DC_LAYER2MODE_LAYER2PREMULT_Msk   (0x10000000UL)            /*!< LAYER2PREMULT (Bitfield-Mask: 0x01)                   */
29757 #define DC_LAYER2MODE_LAYER2HLOCK_Pos     (27UL)                    /*!< LAYER2HLOCK (Bit 27)                                  */
29758 #define DC_LAYER2MODE_LAYER2HLOCK_Msk     (0x8000000UL)             /*!< LAYER2HLOCK (Bitfield-Mask: 0x01)                     */
29759 #define DC_LAYER2MODE_LAYER2GAMMA_Pos     (26UL)                    /*!< LAYER2GAMMA (Bit 26)                                  */
29760 #define DC_LAYER2MODE_LAYER2GAMMA_Msk     (0x4000000UL)             /*!< LAYER2GAMMA (Bitfield-Mask: 0x01)                     */
29761 #define DC_LAYER2MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
29762 #define DC_LAYER2MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
29763 #define DC_LAYER2MODE_LAYER2ALPHA_Pos     (16UL)                    /*!< LAYER2ALPHA (Bit 16)                                  */
29764 #define DC_LAYER2MODE_LAYER2ALPHA_Msk     (0xff0000UL)              /*!< LAYER2ALPHA (Bitfield-Mask: 0xff)                     */
29765 #define DC_LAYER2MODE_LAYER2DBLEND_Pos    (12UL)                    /*!< LAYER2DBLEND (Bit 12)                                 */
29766 #define DC_LAYER2MODE_LAYER2DBLEND_Msk    (0xf000UL)                /*!< LAYER2DBLEND (Bitfield-Mask: 0x0f)                    */
29767 #define DC_LAYER2MODE_LAYER2SBLEND_Pos    (8UL)                     /*!< LAYER2SBLEND (Bit 8)                                  */
29768 #define DC_LAYER2MODE_LAYER2SBLEND_Msk    (0xf00UL)                 /*!< LAYER2SBLEND (Bitfield-Mask: 0x0f)                    */
29769 #define DC_LAYER2MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
29770 #define DC_LAYER2MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
29771 #define DC_LAYER2MODE_LAYER2COLORMODE_Pos (0UL)                     /*!< LAYER2COLORMODE (Bit 0)                               */
29772 #define DC_LAYER2MODE_LAYER2COLORMODE_Msk (0x1fUL)                  /*!< LAYER2COLORMODE (Bitfield-Mask: 0x1f)                 */
29773 /* =====================================================  LAYER2STARTXY  ===================================================== */
29774 #define DC_LAYER2STARTXY_LAYER2XOFF_Pos   (16UL)                    /*!< LAYER2XOFF (Bit 16)                                   */
29775 #define DC_LAYER2STARTXY_LAYER2XOFF_Msk   (0xffff0000UL)            /*!< LAYER2XOFF (Bitfield-Mask: 0xffff)                    */
29776 #define DC_LAYER2STARTXY_LAYER2YOFF_Pos   (0UL)                     /*!< LAYER2YOFF (Bit 0)                                    */
29777 #define DC_LAYER2STARTXY_LAYER2YOFF_Msk   (0xffffUL)                /*!< LAYER2YOFF (Bitfield-Mask: 0xffff)                    */
29778 /* =====================================================  LAYER2SIZEXY  ====================================================== */
29779 #define DC_LAYER2SIZEXY_LAYER2PIXSZEX_Pos (16UL)                    /*!< LAYER2PIXSZEX (Bit 16)                                */
29780 #define DC_LAYER2SIZEXY_LAYER2PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER2PIXSZEX (Bitfield-Mask: 0xffff)                 */
29781 #define DC_LAYER2SIZEXY_LAYER2PIXSZEY_Pos (0UL)                     /*!< LAYER2PIXSZEY (Bit 0)                                 */
29782 #define DC_LAYER2SIZEXY_LAYER2PIXSZEY_Msk (0xffffUL)                /*!< LAYER2PIXSZEY (Bitfield-Mask: 0xffff)                 */
29783 /* ======================================================  LAYER2ADDR  ======================================================= */
29784 #define DC_LAYER2ADDR_LAYER2STARTADDRFBUF_Pos (0UL)                 /*!< LAYER2STARTADDRFBUF (Bit 0)                           */
29785 #define DC_LAYER2ADDR_LAYER2STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER2STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
29786 /* =====================================================  LAYER2STRIDE  ====================================================== */
29787 #define DC_LAYER2STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
29788 #define DC_LAYER2STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
29789 #define DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_Pos (19UL)                /*!< LAYER2AXIFIFOTHLD (Bit 19)                            */
29790 #define DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER2AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
29791 #define DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_Pos (16UL)               /*!< LAYER2AXIBURSTBITS (Bit 16)                           */
29792 #define DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER2AXIBURSTBITS (Bitfield-Mask: 0x07)              */
29793 #define DC_LAYER2STRIDE_LAYER2STRIDEDIST_Pos (0UL)                  /*!< LAYER2STRIDEDIST (Bit 0)                              */
29794 #define DC_LAYER2STRIDE_LAYER2STRIDEDIST_Msk (0xffffUL)             /*!< LAYER2STRIDEDIST (Bitfield-Mask: 0xffff)              */
29795 /* ======================================================  LAYER2RESXY  ====================================================== */
29796 #define DC_LAYER2RESXY_LAYER2PIXRESX_Pos  (16UL)                    /*!< LAYER2PIXRESX (Bit 16)                                */
29797 #define DC_LAYER2RESXY_LAYER2PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER2PIXRESX (Bitfield-Mask: 0xffff)                 */
29798 #define DC_LAYER2RESXY_LAYER2PIXRESY_Pos  (0UL)                     /*!< LAYER2PIXRESY (Bit 0)                                 */
29799 #define DC_LAYER2RESXY_LAYER2PIXRESY_Msk  (0xffffUL)                /*!< LAYER2PIXRESY (Bitfield-Mask: 0xffff)                 */
29800 /* =====================================================  LAYER2SCALEX  ====================================================== */
29801 #define DC_LAYER2SCALEX_LAYER2XFACTOR_Pos (0UL)                     /*!< LAYER2XFACTOR (Bit 0)                                 */
29802 #define DC_LAYER2SCALEX_LAYER2XFACTOR_Msk (0xffffffffUL)            /*!< LAYER2XFACTOR (Bitfield-Mask: 0xffffffff)             */
29803 /* =====================================================  LAYER2SCALEY  ====================================================== */
29804 #define DC_LAYER2SCALEY_LAYER2YFACTOR_Pos (0UL)                     /*!< LAYER2YFACTOR (Bit 0)                                 */
29805 #define DC_LAYER2SCALEY_LAYER2YFACTOR_Msk (0xffffffffUL)            /*!< LAYER2YFACTOR (Bitfield-Mask: 0xffffffff)             */
29806 /* ======================================================  LAYER3MODE  ======================================================= */
29807 #define DC_LAYER3MODE_LAYER3EN_Pos        (31UL)                    /*!< LAYER3EN (Bit 31)                                     */
29808 #define DC_LAYER3MODE_LAYER3EN_Msk        (0x80000000UL)            /*!< LAYER3EN (Bitfield-Mask: 0x01)                        */
29809 #define DC_LAYER3MODE_LAYER3FORCE_Pos     (30UL)                    /*!< LAYER3FORCE (Bit 30)                                  */
29810 #define DC_LAYER3MODE_LAYER3FORCE_Msk     (0x40000000UL)            /*!< LAYER3FORCE (Bitfield-Mask: 0x01)                     */
29811 #define DC_LAYER3MODE_LAYER3BFILTER_Pos   (29UL)                    /*!< LAYER3BFILTER (Bit 29)                                */
29812 #define DC_LAYER3MODE_LAYER3BFILTER_Msk   (0x20000000UL)            /*!< LAYER3BFILTER (Bitfield-Mask: 0x01)                   */
29813 #define DC_LAYER3MODE_LAYER3PREMULT_Pos   (28UL)                    /*!< LAYER3PREMULT (Bit 28)                                */
29814 #define DC_LAYER3MODE_LAYER3PREMULT_Msk   (0x10000000UL)            /*!< LAYER3PREMULT (Bitfield-Mask: 0x01)                   */
29815 #define DC_LAYER3MODE_LAYER3HLOCK_Pos     (27UL)                    /*!< LAYER3HLOCK (Bit 27)                                  */
29816 #define DC_LAYER3MODE_LAYER3HLOCK_Msk     (0x8000000UL)             /*!< LAYER3HLOCK (Bitfield-Mask: 0x01)                     */
29817 #define DC_LAYER3MODE_LAYER3GAMMA_Pos     (26UL)                    /*!< LAYER3GAMMA (Bit 26)                                  */
29818 #define DC_LAYER3MODE_LAYER3GAMMA_Msk     (0x4000000UL)             /*!< LAYER3GAMMA (Bitfield-Mask: 0x01)                     */
29819 #define DC_LAYER3MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
29820 #define DC_LAYER3MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
29821 #define DC_LAYER3MODE_LAYER3ALPHA_Pos     (16UL)                    /*!< LAYER3ALPHA (Bit 16)                                  */
29822 #define DC_LAYER3MODE_LAYER3ALPHA_Msk     (0xff0000UL)              /*!< LAYER3ALPHA (Bitfield-Mask: 0xff)                     */
29823 #define DC_LAYER3MODE_LAYER3DBLEND_Pos    (12UL)                    /*!< LAYER3DBLEND (Bit 12)                                 */
29824 #define DC_LAYER3MODE_LAYER3DBLEND_Msk    (0xf000UL)                /*!< LAYER3DBLEND (Bitfield-Mask: 0x0f)                    */
29825 #define DC_LAYER3MODE_LAYER3SBLEND_Pos    (8UL)                     /*!< LAYER3SBLEND (Bit 8)                                  */
29826 #define DC_LAYER3MODE_LAYER3SBLEND_Msk    (0xf00UL)                 /*!< LAYER3SBLEND (Bitfield-Mask: 0x0f)                    */
29827 #define DC_LAYER3MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
29828 #define DC_LAYER3MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
29829 #define DC_LAYER3MODE_LAYER3COLORMODE_Pos (0UL)                     /*!< LAYER3COLORMODE (Bit 0)                               */
29830 #define DC_LAYER3MODE_LAYER3COLORMODE_Msk (0x1fUL)                  /*!< LAYER3COLORMODE (Bitfield-Mask: 0x1f)                 */
29831 /* =====================================================  LAYER3STARTXY  ===================================================== */
29832 #define DC_LAYER3STARTXY_LAYER3XOFF_Pos   (16UL)                    /*!< LAYER3XOFF (Bit 16)                                   */
29833 #define DC_LAYER3STARTXY_LAYER3XOFF_Msk   (0xffff0000UL)            /*!< LAYER3XOFF (Bitfield-Mask: 0xffff)                    */
29834 #define DC_LAYER3STARTXY_LAYER3YOFF_Pos   (0UL)                     /*!< LAYER3YOFF (Bit 0)                                    */
29835 #define DC_LAYER3STARTXY_LAYER3YOFF_Msk   (0xffffUL)                /*!< LAYER3YOFF (Bitfield-Mask: 0xffff)                    */
29836 /* =====================================================  LAYER3SIZEXY  ====================================================== */
29837 #define DC_LAYER3SIZEXY_LAYER3PIXSZEX_Pos (16UL)                    /*!< LAYER3PIXSZEX (Bit 16)                                */
29838 #define DC_LAYER3SIZEXY_LAYER3PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER3PIXSZEX (Bitfield-Mask: 0xffff)                 */
29839 #define DC_LAYER3SIZEXY_LAYER3PIXSZEY_Pos (0UL)                     /*!< LAYER3PIXSZEY (Bit 0)                                 */
29840 #define DC_LAYER3SIZEXY_LAYER3PIXSZEY_Msk (0xffffUL)                /*!< LAYER3PIXSZEY (Bitfield-Mask: 0xffff)                 */
29841 /* ======================================================  LAYER3ADDR  ======================================================= */
29842 #define DC_LAYER3ADDR_LAYER3STARTADDRFBUF_Pos (0UL)                 /*!< LAYER3STARTADDRFBUF (Bit 0)                           */
29843 #define DC_LAYER3ADDR_LAYER3STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER3STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
29844 /* =====================================================  LAYER3STRIDE  ====================================================== */
29845 #define DC_LAYER3STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
29846 #define DC_LAYER3STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
29847 #define DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_Pos (19UL)                /*!< LAYER3AXIFIFOTHLD (Bit 19)                            */
29848 #define DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER3AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
29849 #define DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_Pos (16UL)               /*!< LAYER3AXIBURSTBITS (Bit 16)                           */
29850 #define DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER3AXIBURSTBITS (Bitfield-Mask: 0x07)              */
29851 #define DC_LAYER3STRIDE_LAYER3STRIDEDIST_Pos (0UL)                  /*!< LAYER3STRIDEDIST (Bit 0)                              */
29852 #define DC_LAYER3STRIDE_LAYER3STRIDEDIST_Msk (0xffffUL)             /*!< LAYER3STRIDEDIST (Bitfield-Mask: 0xffff)              */
29853 /* ======================================================  LAYER3RESXY  ====================================================== */
29854 #define DC_LAYER3RESXY_LAYER3PIXRESX_Pos  (16UL)                    /*!< LAYER3PIXRESX (Bit 16)                                */
29855 #define DC_LAYER3RESXY_LAYER3PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER3PIXRESX (Bitfield-Mask: 0xffff)                 */
29856 #define DC_LAYER3RESXY_LAYER3PIXRESY_Pos  (0UL)                     /*!< LAYER3PIXRESY (Bit 0)                                 */
29857 #define DC_LAYER3RESXY_LAYER3PIXRESY_Msk  (0xffffUL)                /*!< LAYER3PIXRESY (Bitfield-Mask: 0xffff)                 */
29858 /* =====================================================  LAYER3SCALEX  ====================================================== */
29859 #define DC_LAYER3SCALEX_LAYER3XFACTOR_Pos (0UL)                     /*!< LAYER3XFACTOR (Bit 0)                                 */
29860 #define DC_LAYER3SCALEX_LAYER3XFACTOR_Msk (0xffffffffUL)            /*!< LAYER3XFACTOR (Bitfield-Mask: 0xffffffff)             */
29861 /* =====================================================  LAYER3SCALEY  ====================================================== */
29862 #define DC_LAYER3SCALEY_LAYER3YFACTOR_Pos (0UL)                     /*!< LAYER3YFACTOR (Bit 0)                                 */
29863 #define DC_LAYER3SCALEY_LAYER3YFACTOR_Msk (0xffffffffUL)            /*!< LAYER3YFACTOR (Bitfield-Mask: 0xffffffff)             */
29864 /* ========================================================  DBICMD  ========================================================= */
29865 #define DC_DBICMD_RSVD2_Pos               (31UL)                    /*!< RSVD2 (Bit 31)                                        */
29866 #define DC_DBICMD_RSVD2_Msk               (0x80000000UL)            /*!< RSVD2 (Bitfield-Mask: 0x01)                           */
29867 #define DC_DBICMD_DIRECTDATA_Pos          (30UL)                    /*!< DIRECTDATA (Bit 30)                                   */
29868 #define DC_DBICMD_DIRECTDATA_Msk          (0x40000000UL)            /*!< DIRECTDATA (Bitfield-Mask: 0x01)                      */
29869 #define DC_DBICMD_RSVD1_Pos               (29UL)                    /*!< RSVD1 (Bit 29)                                        */
29870 #define DC_DBICMD_RSVD1_Msk               (0x20000000UL)            /*!< RSVD1 (Bitfield-Mask: 0x01)                           */
29871 #define DC_DBICMD_READDBI_Pos             (28UL)                    /*!< READDBI (Bit 28)                                      */
29872 #define DC_DBICMD_READDBI_Msk             (0x10000000UL)            /*!< READDBI (Bitfield-Mask: 0x01)                         */
29873 #define DC_DBICMD_LOCALSTORE_Pos          (27UL)                    /*!< LOCALSTORE (Bit 27)                                   */
29874 #define DC_DBICMD_LOCALSTORE_Msk          (0x8000000UL)             /*!< LOCALSTORE (Bitfield-Mask: 0x01)                      */
29875 #define DC_DBICMD_RSVD0_Pos               (16UL)                    /*!< RSVD0 (Bit 16)                                        */
29876 #define DC_DBICMD_RSVD0_Msk               (0x7ff0000UL)             /*!< RSVD0 (Bitfield-Mask: 0x7ff)                          */
29877 #define DC_DBICMD_DATA2DBI_Pos            (0UL)                     /*!< DATA2DBI (Bit 0)                                      */
29878 #define DC_DBICMD_DATA2DBI_Msk            (0xffffUL)                /*!< DATA2DBI (Bitfield-Mask: 0xffff)                      */
29879 /* ========================================================  DBIRDAT  ======================================================== */
29880 #define DC_DBIRDAT_READTYPEB_Pos          (0UL)                     /*!< READTYPEB (Bit 0)                                     */
29881 #define DC_DBIRDAT_READTYPEB_Msk          (0xffffffffUL)            /*!< READTYPEB (Bitfield-Mask: 0xffffffff)                 */
29882 /* =========================================================  CONFG  ========================================================= */
29883 #define DC_CONFG_RSVD_Pos                 (24UL)                    /*!< RSVD (Bit 24)                                         */
29884 #define DC_CONFG_RSVD_Msk                 (0xff000000UL)            /*!< RSVD (Bitfield-Mask: 0xff)                            */
29885 #define DC_CONFG_CFGLAYER3GAMMALUT_Pos    (23UL)                    /*!< CFGLAYER3GAMMALUT (Bit 23)                            */
29886 #define DC_CONFG_CFGLAYER3GAMMALUT_Msk    (0x800000UL)              /*!< CFGLAYER3GAMMALUT (Bitfield-Mask: 0x01)               */
29887 #define DC_CONFG_CFGLAYER3SCALAR_Pos      (22UL)                    /*!< CFGLAYER3SCALAR (Bit 22)                              */
29888 #define DC_CONFG_CFGLAYER3SCALAR_Msk      (0x400000UL)              /*!< CFGLAYER3SCALAR (Bitfield-Mask: 0x01)                 */
29889 #define DC_CONFG_CFGLAYER3BLENDER_Pos     (21UL)                    /*!< CFGLAYER3BLENDER (Bit 21)                             */
29890 #define DC_CONFG_CFGLAYER3BLENDER_Msk     (0x200000UL)              /*!< CFGLAYER3BLENDER (Bitfield-Mask: 0x01)                */
29891 #define DC_CONFG_CFGLAYER3EN_Pos          (20UL)                    /*!< CFGLAYER3EN (Bit 20)                                  */
29892 #define DC_CONFG_CFGLAYER3EN_Msk          (0x100000UL)              /*!< CFGLAYER3EN (Bitfield-Mask: 0x01)                     */
29893 #define DC_CONFG_CFGLAYER2GAMMALUT_Pos    (19UL)                    /*!< CFGLAYER2GAMMALUT (Bit 19)                            */
29894 #define DC_CONFG_CFGLAYER2GAMMALUT_Msk    (0x80000UL)               /*!< CFGLAYER2GAMMALUT (Bitfield-Mask: 0x01)               */
29895 #define DC_CONFG_CFGLAYER2SCALAR_Pos      (18UL)                    /*!< CFGLAYER2SCALAR (Bit 18)                              */
29896 #define DC_CONFG_CFGLAYER2SCALAR_Msk      (0x40000UL)               /*!< CFGLAYER2SCALAR (Bitfield-Mask: 0x01)                 */
29897 #define DC_CONFG_CFGLAYER2BLENDER_Pos     (17UL)                    /*!< CFGLAYER2BLENDER (Bit 17)                             */
29898 #define DC_CONFG_CFGLAYER2BLENDER_Msk     (0x20000UL)               /*!< CFGLAYER2BLENDER (Bitfield-Mask: 0x01)                */
29899 #define DC_CONFG_CFGLAYER2EN_Pos          (16UL)                    /*!< CFGLAYER2EN (Bit 16)                                  */
29900 #define DC_CONFG_CFGLAYER2EN_Msk          (0x10000UL)               /*!< CFGLAYER2EN (Bitfield-Mask: 0x01)                     */
29901 #define DC_CONFG_CFGLAYER1GAMMALUT_Pos    (15UL)                    /*!< CFGLAYER1GAMMALUT (Bit 15)                            */
29902 #define DC_CONFG_CFGLAYER1GAMMALUT_Msk    (0x8000UL)                /*!< CFGLAYER1GAMMALUT (Bitfield-Mask: 0x01)               */
29903 #define DC_CONFG_CFGLAYER1SCALAR_Pos      (14UL)                    /*!< CFGLAYER1SCALAR (Bit 14)                              */
29904 #define DC_CONFG_CFGLAYER1SCALAR_Msk      (0x4000UL)                /*!< CFGLAYER1SCALAR (Bitfield-Mask: 0x01)                 */
29905 #define DC_CONFG_CFGLAYER1BLENDER_Pos     (13UL)                    /*!< CFGLAYER1BLENDER (Bit 13)                             */
29906 #define DC_CONFG_CFGLAYER1BLENDER_Msk     (0x2000UL)                /*!< CFGLAYER1BLENDER (Bitfield-Mask: 0x01)                */
29907 #define DC_CONFG_CFGLAYER1EN_Pos          (12UL)                    /*!< CFGLAYER1EN (Bit 12)                                  */
29908 #define DC_CONFG_CFGLAYER1EN_Msk          (0x1000UL)                /*!< CFGLAYER1EN (Bitfield-Mask: 0x01)                     */
29909 #define DC_CONFG_CFGLAYER0GAMMALUT_Pos    (11UL)                    /*!< CFGLAYER0GAMMALUT (Bit 11)                            */
29910 #define DC_CONFG_CFGLAYER0GAMMALUT_Msk    (0x800UL)                 /*!< CFGLAYER0GAMMALUT (Bitfield-Mask: 0x01)               */
29911 #define DC_CONFG_CFGLAYER0SCALAR_Pos      (10UL)                    /*!< CFGLAYER0SCALAR (Bit 10)                              */
29912 #define DC_CONFG_CFGLAYER0SCALAR_Msk      (0x400UL)                 /*!< CFGLAYER0SCALAR (Bitfield-Mask: 0x01)                 */
29913 #define DC_CONFG_CFGLAYER0BLENDER_Pos     (9UL)                     /*!< CFGLAYER0BLENDER (Bit 9)                              */
29914 #define DC_CONFG_CFGLAYER0BLENDER_Msk     (0x200UL)                 /*!< CFGLAYER0BLENDER (Bitfield-Mask: 0x01)                */
29915 #define DC_CONFG_CFGLAYER0EN_Pos          (8UL)                     /*!< CFGLAYER0EN (Bit 8)                                   */
29916 #define DC_CONFG_CFGLAYER0EN_Msk          (0x100UL)                 /*!< CFGLAYER0EN (Bitfield-Mask: 0x01)                     */
29917 #define DC_CONFG_CFGRGB2YUVEN_Pos         (7UL)                     /*!< CFGRGB2YUVEN (Bit 7)                                  */
29918 #define DC_CONFG_CFGRGB2YUVEN_Msk         (0x80UL)                  /*!< CFGRGB2YUVEN (Bitfield-Mask: 0x01)                    */
29919 #define DC_CONFG_CFGDBITYPEBEN_Pos        (6UL)                     /*!< CFGDBITYPEBEN (Bit 6)                                 */
29920 #define DC_CONFG_CFGDBITYPEBEN_Msk        (0x40UL)                  /*!< CFGDBITYPEBEN (Bitfield-Mask: 0x01)                   */
29921 #define DC_CONFG_CFGYUVCNVTEN_Pos         (5UL)                     /*!< CFGYUVCNVTEN (Bit 5)                                  */
29922 #define DC_CONFG_CFGYUVCNVTEN_Msk         (0x20UL)                  /*!< CFGYUVCNVTEN (Bitfield-Mask: 0x01)                    */
29923 #define DC_CONFG_CFGFORMATTEN_Pos         (4UL)                     /*!< CFGFORMATTEN (Bit 4)                                  */
29924 #define DC_CONFG_CFGFORMATTEN_Msk         (0x10UL)                  /*!< CFGFORMATTEN (Bitfield-Mask: 0x01)                    */
29925 #define DC_CONFG_CFGDITHEREN_Pos          (3UL)                     /*!< CFGDITHEREN (Bit 3)                                   */
29926 #define DC_CONFG_CFGDITHEREN_Msk          (0x8UL)                   /*!< CFGDITHEREN (Bitfield-Mask: 0x01)                     */
29927 #define DC_CONFG_CFGPCURSOREN_Pos         (2UL)                     /*!< CFGPCURSOREN (Bit 2)                                  */
29928 #define DC_CONFG_CFGPCURSOREN_Msk         (0x4UL)                   /*!< CFGPCURSOREN (Bitfield-Mask: 0x01)                    */
29929 #define DC_CONFG_CFGFCURSOREN_Pos         (1UL)                     /*!< CFGFCURSOREN (Bit 1)                                  */
29930 #define DC_CONFG_CFGFCURSOREN_Msk         (0x2UL)                   /*!< CFGFCURSOREN (Bitfield-Mask: 0x01)                    */
29931 #define DC_CONFG_CFGGLBGAMMAEN_Pos        (0UL)                     /*!< CFGGLBGAMMAEN (Bit 0)                                 */
29932 #define DC_CONFG_CFGGLBGAMMAEN_Msk        (0x1UL)                   /*!< CFGGLBGAMMAEN (Bitfield-Mask: 0x01)                   */
29933 /* =========================================================  IDREG  ========================================================= */
29934 #define DC_IDREG_DCID_Pos                 (0UL)                     /*!< DCID (Bit 0)                                          */
29935 #define DC_IDREG_DCID_Msk                 (0xffffffffUL)            /*!< DCID (Bitfield-Mask: 0xffffffff)                      */
29936 /* =======================================================  INTERRUPT  ======================================================= */
29937 #define DC_INTERRUPT_INTTRIGGER_Pos       (31UL)                    /*!< INTTRIGGER (Bit 31)                                   */
29938 #define DC_INTERRUPT_INTTRIGGER_Msk       (0x80000000UL)            /*!< INTTRIGGER (Bitfield-Mask: 0x01)                      */
29939 #define DC_INTERRUPT_INTTEEN_Pos          (3UL)                     /*!< INTTEEN (Bit 3)                                       */
29940 #define DC_INTERRUPT_INTTEEN_Msk          (0x8UL)                   /*!< INTTEEN (Bitfield-Mask: 0x01)                         */
29941 #define DC_INTERRUPT_INTMMUERR_Pos        (2UL)                     /*!< INTMMUERR (Bit 2)                                     */
29942 #define DC_INTERRUPT_INTMMUERR_Msk        (0x4UL)                   /*!< INTMMUERR (Bitfield-Mask: 0x01)                       */
29943 #define DC_INTERRUPT_INTHSYNCEN_Pos       (1UL)                     /*!< INTHSYNCEN (Bit 1)                                    */
29944 #define DC_INTERRUPT_INTHSYNCEN_Msk       (0x2UL)                   /*!< INTHSYNCEN (Bitfield-Mask: 0x01)                      */
29945 #define DC_INTERRUPT_INTVSYNCEN_Pos       (0UL)                     /*!< INTVSYNCEN (Bit 0)                                    */
29946 #define DC_INTERRUPT_INTVSYNCEN_Msk       (0x1UL)                   /*!< INTVSYNCEN (Bitfield-Mask: 0x01)                      */
29947 /* ========================================================  STATUS  ========================================================= */
29948 #define DC_STATUS_STATDBIPENDTRANS_Pos    (12UL)                    /*!< STATDBIPENDTRANS (Bit 12)                             */
29949 #define DC_STATUS_STATDBIPENDTRANS_Msk    (0x1000UL)                /*!< STATDBIPENDTRANS (Bitfield-Mask: 0x01)                */
29950 #define DC_STATUS_STATDBIPENDCOM_Pos      (11UL)                    /*!< STATDBIPENDCOM (Bit 11)                               */
29951 #define DC_STATUS_STATDBIPENDCOM_Msk      (0x800UL)                 /*!< STATDBIPENDCOM (Bitfield-Mask: 0x01)                  */
29952 #define DC_STATUS_STATDBIRGB_Pos          (10UL)                    /*!< STATDBIRGB (Bit 10)                                   */
29953 #define DC_STATUS_STATDBIRGB_Msk          (0x400UL)                 /*!< STATDBIRGB (Bitfield-Mask: 0x01)                      */
29954 #define DC_STATUS_STATTEAR_Pos            (8UL)                     /*!< STATTEAR (Bit 8)                                      */
29955 #define DC_STATUS_STATTEAR_Msk            (0x100UL)                 /*!< STATTEAR (Bitfield-Mask: 0x01)                        */
29956 #define DC_STATUS_STATSTICKY_Pos          (7UL)                     /*!< STATSTICKY (Bit 7)                                    */
29957 #define DC_STATUS_STATSTICKY_Msk          (0x80UL)                  /*!< STATSTICKY (Bitfield-Mask: 0x01)                      */
29958 #define DC_STATUS_STATUF_Pos              (6UL)                     /*!< STATUF (Bit 6)                                        */
29959 #define DC_STATUS_STATUF_Msk              (0x40UL)                  /*!< STATUF (Bitfield-Mask: 0x01)                          */
29960 #define DC_STATUS_STATLAST_Pos            (5UL)                     /*!< STATLAST (Bit 5)                                      */
29961 #define DC_STATUS_STATLAST_Msk            (0x20UL)                  /*!< STATLAST (Bitfield-Mask: 0x01)                        */
29962 #define DC_STATUS_STATCSYNC_Pos           (4UL)                     /*!< STATCSYNC (Bit 4)                                     */
29963 #define DC_STATUS_STATCSYNC_Msk           (0x10UL)                  /*!< STATCSYNC (Bitfield-Mask: 0x01)                       */
29964 #define DC_STATUS_STATVSYNC_Pos           (3UL)                     /*!< STATVSYNC (Bit 3)                                     */
29965 #define DC_STATUS_STATVSYNC_Msk           (0x8UL)                   /*!< STATVSYNC (Bitfield-Mask: 0x01)                       */
29966 #define DC_STATUS_STATHSYNC_Pos           (2UL)                     /*!< STATHSYNC (Bit 2)                                     */
29967 #define DC_STATUS_STATHSYNC_Msk           (0x4UL)                   /*!< STATHSYNC (Bitfield-Mask: 0x01)                       */
29968 #define DC_STATUS_STATDE_Pos              (1UL)                     /*!< STATDE (Bit 1)                                        */
29969 #define DC_STATUS_STATDE_Msk              (0x2UL)                   /*!< STATDE (Bitfield-Mask: 0x01)                          */
29970 #define DC_STATUS_STATNOTBLANK_Pos        (0UL)                     /*!< STATNOTBLANK (Bit 0)                                  */
29971 #define DC_STATUS_STATNOTBLANK_Msk        (0x1UL)                   /*!< STATNOTBLANK (Bitfield-Mask: 0x01)                    */
29972 /* ========================================================  COLMOD  ========================================================= */
29973 #define DC_COLMOD_CLMDBKPRESSURE_Pos      (31UL)                    /*!< CLMDBKPRESSURE (Bit 31)                               */
29974 #define DC_COLMOD_CLMDBKPRESSURE_Msk      (0x80000000UL)            /*!< CLMDBKPRESSURE (Bitfield-Mask: 0x01)                  */
29975 #define DC_COLMOD_CLMDLUT8_Pos            (16UL)                    /*!< CLMDLUT8 (Bit 16)                                     */
29976 #define DC_COLMOD_CLMDLUT8_Msk            (0x10000UL)               /*!< CLMDLUT8 (Bitfield-Mask: 0x01)                        */
29977 #define DC_COLMOD_CLMDRGBA5551_Pos        (15UL)                    /*!< CLMDRGBA5551 (Bit 15)                                 */
29978 #define DC_COLMOD_CLMDRGBA5551_Msk        (0x8000UL)                /*!< CLMDRGBA5551 (Bitfield-Mask: 0x01)                    */
29979 #define DC_COLMOD_CLMDRGBA8888_Pos        (14UL)                    /*!< CLMDRGBA8888 (Bit 14)                                 */
29980 #define DC_COLMOD_CLMDRGBA8888_Msk        (0x4000UL)                /*!< CLMDRGBA8888 (Bitfield-Mask: 0x01)                    */
29981 #define DC_COLMOD_CLMDRGB332_Pos          (13UL)                    /*!< CLMDRGB332 (Bit 13)                                   */
29982 #define DC_COLMOD_CLMDRGB332_Msk          (0x2000UL)                /*!< CLMDRGB332 (Bitfield-Mask: 0x01)                      */
29983 #define DC_COLMOD_CLMDRGB565_Pos          (12UL)                    /*!< CLMDRGB565 (Bit 12)                                   */
29984 #define DC_COLMOD_CLMDRGB565_Msk          (0x1000UL)                /*!< CLMDRGB565 (Bitfield-Mask: 0x01)                      */
29985 #define DC_COLMOD_CLMDARGB8888_Pos        (11UL)                    /*!< CLMDARGB8888 (Bit 11)                                 */
29986 #define DC_COLMOD_CLMDARGB8888_Msk        (0x800UL)                 /*!< CLMDARGB8888 (Bitfield-Mask: 0x01)                    */
29987 #define DC_COLMOD_CLMDL8_Pos              (10UL)                    /*!< CLMDL8 (Bit 10)                                       */
29988 #define DC_COLMOD_CLMDL8_Msk              (0x400UL)                 /*!< CLMDL8 (Bitfield-Mask: 0x01)                          */
29989 #define DC_COLMOD_CLMDL1_Pos              (9UL)                     /*!< CLMDL1 (Bit 9)                                        */
29990 #define DC_COLMOD_CLMDL1_Msk              (0x200UL)                 /*!< CLMDL1 (Bitfield-Mask: 0x01)                          */
29991 #define DC_COLMOD_CLMDL4_Pos              (8UL)                     /*!< CLMDL4 (Bit 8)                                        */
29992 #define DC_COLMOD_CLMDL4_Msk              (0x100UL)                 /*!< CLMDL4 (Bitfield-Mask: 0x01)                          */
29993 #define DC_COLMOD_CLMDYUYV_Pos            (7UL)                     /*!< CLMDYUYV (Bit 7)                                      */
29994 #define DC_COLMOD_CLMDYUYV_Msk            (0x80UL)                  /*!< CLMDYUYV (Bitfield-Mask: 0x01)                        */
29995 #define DC_COLMOD_CLMDRGB888_Pos          (6UL)                     /*!< CLMDRGB888 (Bit 6)                                    */
29996 #define DC_COLMOD_CLMDRGB888_Msk          (0x40UL)                  /*!< CLMDRGB888 (Bitfield-Mask: 0x01)                      */
29997 #define DC_COLMOD_CLMDYUY2_Pos            (5UL)                     /*!< CLMDYUY2 (Bit 5)                                      */
29998 #define DC_COLMOD_CLMDYUY2_Msk            (0x20UL)                  /*!< CLMDYUY2 (Bitfield-Mask: 0x01)                        */
29999 #define DC_COLMOD_CLMDABGR8888_Pos        (4UL)                     /*!< CLMDABGR8888 (Bit 4)                                  */
30000 #define DC_COLMOD_CLMDABGR8888_Msk        (0x10UL)                  /*!< CLMDABGR8888 (Bitfield-Mask: 0x01)                    */
30001 #define DC_COLMOD_CLMDBGRA8888_Pos        (3UL)                     /*!< CLMDBGRA8888 (Bit 3)                                  */
30002 #define DC_COLMOD_CLMDBGRA8888_Msk        (0x8UL)                   /*!< CLMDBGRA8888 (Bitfield-Mask: 0x01)                    */
30003 #define DC_COLMOD_CLMDVYUV420_Pos         (2UL)                     /*!< CLMDVYUV420 (Bit 2)                                   */
30004 #define DC_COLMOD_CLMDVYUV420_Msk         (0x4UL)                   /*!< CLMDVYUV420 (Bitfield-Mask: 0x01)                     */
30005 #define DC_COLMOD_CLMDTLYUV420_Pos        (1UL)                     /*!< CLMDTLYUV420 (Bit 1)                                  */
30006 #define DC_COLMOD_CLMDTLYUV420_Msk        (0x2UL)                   /*!< CLMDTLYUV420 (Bitfield-Mask: 0x01)                    */
30007 #define DC_COLMOD_CLMDTSC4TSC6_Pos        (0UL)                     /*!< CLMDTSC4TSC6 (Bit 0)                                  */
30008 #define DC_COLMOD_CLMDTSC4TSC6_Msk        (0x1UL)                   /*!< CLMDTSC4TSC6 (Bitfield-Mask: 0x01)                    */
30009 /* ==========================================================  CRC  ========================================================== */
30010 #define DC_CRC_CRCREG_Pos                 (0UL)                     /*!< CRCREG (Bit 0)                                        */
30011 #define DC_CRC_CRCREG_Msk                 (0xffffffffUL)            /*!< CRCREG (Bitfield-Mask: 0xffffffff)                    */
30012 /* =========================================================  GLLUT  ========================================================= */
30013 #define DC_GLLUT_GLLUT0GAMRAMPR_Pos       (16UL)                    /*!< GLLUT0GAMRAMPR (Bit 16)                               */
30014 #define DC_GLLUT_GLLUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< GLLUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30015 #define DC_GLLUT_GLLUT0GAMRAMPG_Pos       (8UL)                     /*!< GLLUT0GAMRAMPG (Bit 8)                                */
30016 #define DC_GLLUT_GLLUT0GAMRAMPG_Msk       (0xff00UL)                /*!< GLLUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30017 #define DC_GLLUT_GLLUT0GAMRAMPB_Pos       (0UL)                     /*!< GLLUT0GAMRAMPB (Bit 0)                                */
30018 #define DC_GLLUT_GLLUT0GAMRAMPB_Msk       (0xffUL)                  /*!< GLLUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30019 /* ======================================================  CURSORDATA  ======================================================= */
30020 #define DC_CURSORDATA_CURDATA3112_Pos     (12UL)                    /*!< CURDATA3112 (Bit 12)                                  */
30021 #define DC_CURSORDATA_CURDATA3112_Msk     (0xfffff000UL)            /*!< CURDATA3112 (Bitfield-Mask: 0xfffff)                  */
30022 #define DC_CURSORDATA_CURDATA70_Pos       (0UL)                     /*!< CURDATA70 (Bit 0)                                     */
30023 #define DC_CURSORDATA_CURDATA70_Msk       (0xffUL)                  /*!< CURDATA70 (Bitfield-Mask: 0xff)                       */
30024 /* =======================================================  CURSORLUT  ======================================================= */
30025 #define DC_CURSORLUT_CURLUT0R_Pos         (16UL)                    /*!< CURLUT0R (Bit 16)                                     */
30026 #define DC_CURSORLUT_CURLUT0R_Msk         (0xff0000UL)              /*!< CURLUT0R (Bitfield-Mask: 0xff)                        */
30027 #define DC_CURSORLUT_CURLUT0G_Pos         (8UL)                     /*!< CURLUT0G (Bit 8)                                      */
30028 #define DC_CURSORLUT_CURLUT0G_Msk         (0xff00UL)                /*!< CURLUT0G (Bitfield-Mask: 0xff)                        */
30029 #define DC_CURSORLUT_CURLUT0B_Pos         (0UL)                     /*!< CURLUT0B (Bit 0)                                      */
30030 #define DC_CURSORLUT_CURLUT0B_Msk         (0xffUL)                  /*!< CURLUT0B (Bitfield-Mask: 0xff)                        */
30031 /* =========================================================  L0LUT  ========================================================= */
30032 #define DC_L0LUT_L0LUT0GAMRAMPA_Pos       (24UL)                    /*!< L0LUT0GAMRAMPA (Bit 24)                               */
30033 #define DC_L0LUT_L0LUT0GAMRAMPA_Msk       (0xff000000UL)            /*!< L0LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30034 #define DC_L0LUT_L0LUT0GAMRAMPR_Pos       (16UL)                    /*!< L0LUT0GAMRAMPR (Bit 16)                               */
30035 #define DC_L0LUT_L0LUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< L0LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30036 #define DC_L0LUT_L0LUT0GAMRAMPG_Pos       (8UL)                     /*!< L0LUT0GAMRAMPG (Bit 8)                                */
30037 #define DC_L0LUT_L0LUT0GAMRAMPG_Msk       (0xff00UL)                /*!< L0LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30038 #define DC_L0LUT_L0LUT0GAMRAMPB_Pos       (0UL)                     /*!< L0LUT0GAMRAMPB (Bit 0)                                */
30039 #define DC_L0LUT_L0LUT0GAMRAMPB_Msk       (0xffUL)                  /*!< L0LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30040 /* =========================================================  L1LUT  ========================================================= */
30041 #define DC_L1LUT_L1LUT0GAMRAMPA_Pos       (24UL)                    /*!< L1LUT0GAMRAMPA (Bit 24)                               */
30042 #define DC_L1LUT_L1LUT0GAMRAMPA_Msk       (0xff000000UL)            /*!< L1LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30043 #define DC_L1LUT_L1LUT0GAMRAMPR_Pos       (16UL)                    /*!< L1LUT0GAMRAMPR (Bit 16)                               */
30044 #define DC_L1LUT_L1LUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< L1LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30045 #define DC_L1LUT_L1LUT0GAMRAMPG_Pos       (8UL)                     /*!< L1LUT0GAMRAMPG (Bit 8)                                */
30046 #define DC_L1LUT_L1LUT0GAMRAMPG_Msk       (0xff00UL)                /*!< L1LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30047 #define DC_L1LUT_L1LUT0GAMRAMPB_Pos       (0UL)                     /*!< L1LUT0GAMRAMPB (Bit 0)                                */
30048 #define DC_L1LUT_L1LUT0GAMRAMPB_Msk       (0xffUL)                  /*!< L1LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30049 /* ========================================================  L2LUT0  ========================================================= */
30050 #define DC_L2LUT0_L2LUT0GAMRAMPA_Pos      (24UL)                    /*!< L2LUT0GAMRAMPA (Bit 24)                               */
30051 #define DC_L2LUT0_L2LUT0GAMRAMPA_Msk      (0xff000000UL)            /*!< L2LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30052 #define DC_L2LUT0_L2LUT0GAMRAMPR_Pos      (16UL)                    /*!< L2LUT0GAMRAMPR (Bit 16)                               */
30053 #define DC_L2LUT0_L2LUT0GAMRAMPR_Msk      (0xff0000UL)              /*!< L2LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30054 #define DC_L2LUT0_L2LUT0GAMRAMPG_Pos      (8UL)                     /*!< L2LUT0GAMRAMPG (Bit 8)                                */
30055 #define DC_L2LUT0_L2LUT0GAMRAMPG_Msk      (0xff00UL)                /*!< L2LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30056 #define DC_L2LUT0_L2LUT0GAMRAMPB_Pos      (0UL)                     /*!< L2LUT0GAMRAMPB (Bit 0)                                */
30057 #define DC_L2LUT0_L2LUT0GAMRAMPB_Msk      (0xffUL)                  /*!< L2LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30058 /* =========================================================  L3LUT  ========================================================= */
30059 #define DC_L3LUT_L3LUT0GAMRAMPA_Pos       (24UL)                    /*!< L3LUT0GAMRAMPA (Bit 24)                               */
30060 #define DC_L3LUT_L3LUT0GAMRAMPA_Msk       (0xff000000UL)            /*!< L3LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30061 #define DC_L3LUT_L3LUT0GAMRAMPR_Pos       (16UL)                    /*!< L3LUT0GAMRAMPR (Bit 16)                               */
30062 #define DC_L3LUT_L3LUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< L3LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30063 #define DC_L3LUT_L3LUT0GAMRAMPG_Pos       (8UL)                     /*!< L3LUT0GAMRAMPG (Bit 8)                                */
30064 #define DC_L3LUT_L3LUT0GAMRAMPG_Msk       (0xff00UL)                /*!< L3LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30065 #define DC_L3LUT_L3LUT0GAMRAMPB_Pos       (0UL)                     /*!< L3LUT0GAMRAMPB (Bit 0)                                */
30066 #define DC_L3LUT_L3LUT0GAMRAMPB_Msk       (0xffUL)                  /*!< L3LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30067 
30068 
30069 /* =========================================================================================================================== */
30070 /* ================                                            DSI                                            ================ */
30071 /* =========================================================================================================================== */
30072 
30073 /* ======================================================  DEVICEREADY  ====================================================== */
30074 #define DSI_DEVICEREADY_DISPLAYBUSPOSSESSEN_Pos (3UL)               /*!< DISPLAYBUSPOSSESSEN (Bit 3)                           */
30075 #define DSI_DEVICEREADY_DISPLAYBUSPOSSESSEN_Msk (0x8UL)             /*!< DISPLAYBUSPOSSESSEN (Bitfield-Mask: 0x01)             */
30076 #define DSI_DEVICEREADY_ULPS_Pos          (1UL)                     /*!< ULPS (Bit 1)                                          */
30077 #define DSI_DEVICEREADY_ULPS_Msk          (0x6UL)                   /*!< ULPS (Bitfield-Mask: 0x03)                            */
30078 #define DSI_DEVICEREADY_READY_Pos         (0UL)                     /*!< READY (Bit 0)                                         */
30079 #define DSI_DEVICEREADY_READY_Msk         (0x1UL)                   /*!< READY (Bitfield-Mask: 0x01)                           */
30080 /* =======================================================  INTRSTAT  ======================================================== */
30081 #define DSI_INTRSTAT_DPIPRGERR_Pos        (31UL)                    /*!< DPIPRGERR (Bit 31)                                    */
30082 #define DSI_INTRSTAT_DPIPRGERR_Msk        (0x80000000UL)            /*!< DPIPRGERR (Bitfield-Mask: 0x01)                       */
30083 #define DSI_INTRSTAT_DPILINETO_Pos        (30UL)                    /*!< DPILINETO (Bit 30)                                    */
30084 #define DSI_INTRSTAT_DPILINETO_Msk        (0x40000000UL)            /*!< DPILINETO (Bitfield-Mask: 0x01)                       */
30085 #define DSI_INTRSTAT_RXCNT_Pos            (29UL)                    /*!< RXCNT (Bit 29)                                        */
30086 #define DSI_INTRSTAT_RXCNT_Msk            (0x20000000UL)            /*!< RXCNT (Bitfield-Mask: 0x01)                           */
30087 #define DSI_INTRSTAT_INITDONE_Pos         (28UL)                    /*!< INITDONE (Bit 28)                                     */
30088 #define DSI_INTRSTAT_INITDONE_Msk         (0x10000000UL)            /*!< INITDONE (Bitfield-Mask: 0x01)                        */
30089 #define DSI_INTRSTAT_SPECIALPACK_Pos      (27UL)                    /*!< SPECIALPACK (Bit 27)                                  */
30090 #define DSI_INTRSTAT_SPECIALPACK_Msk      (0x8000000UL)             /*!< SPECIALPACK (Bitfield-Mask: 0x01)                     */
30091 #define DSI_INTRSTAT_RXDSIPROT_Pos        (26UL)                    /*!< RXDSIPROT (Bit 26)                                    */
30092 #define DSI_INTRSTAT_RXDSIPROT_Msk        (0x4000000UL)             /*!< RXDSIPROT (Bitfield-Mask: 0x01)                       */
30093 #define DSI_INTRSTAT_RXINVALID_Pos        (25UL)                    /*!< RXINVALID (Bit 25)                                    */
30094 #define DSI_INTRSTAT_RXINVALID_Msk        (0x2000000UL)             /*!< RXINVALID (Bitfield-Mask: 0x01)                       */
30095 #define DSI_INTRSTAT_ACKWNOERR_Pos        (24UL)                    /*!< ACKWNOERR (Bit 24)                                    */
30096 #define DSI_INTRSTAT_ACKWNOERR_Msk        (0x1000000UL)             /*!< ACKWNOERR (Bitfield-Mask: 0x01)                       */
30097 #define DSI_INTRSTAT_TURNARNDACK_Pos      (23UL)                    /*!< TURNARNDACK (Bit 23)                                  */
30098 #define DSI_INTRSTAT_TURNARNDACK_Msk      (0x800000UL)              /*!< TURNARNDACK (Bitfield-Mask: 0x01)                     */
30099 #define DSI_INTRSTAT_LPRXTIMEOUT_Pos      (22UL)                    /*!< LPRXTIMEOUT (Bit 22)                                  */
30100 #define DSI_INTRSTAT_LPRXTIMEOUT_Msk      (0x400000UL)              /*!< LPRXTIMEOUT (Bitfield-Mask: 0x01)                     */
30101 #define DSI_INTRSTAT_HSTXTIMEOUT_Pos      (21UL)                    /*!< HSTXTIMEOUT (Bit 21)                                  */
30102 #define DSI_INTRSTAT_HSTXTIMEOUT_Msk      (0x200000UL)              /*!< HSTXTIMEOUT (Bitfield-Mask: 0x01)                     */
30103 #define DSI_INTRSTAT_FIFOEMPTY_Pos        (20UL)                    /*!< FIFOEMPTY (Bit 20)                                    */
30104 #define DSI_INTRSTAT_FIFOEMPTY_Msk        (0x100000UL)              /*!< FIFOEMPTY (Bitfield-Mask: 0x01)                       */
30105 #define DSI_INTRSTAT_LOWC_Pos             (19UL)                    /*!< LOWC (Bit 19)                                         */
30106 #define DSI_INTRSTAT_LOWC_Msk             (0x80000UL)               /*!< LOWC (Bitfield-Mask: 0x01)                            */
30107 #define DSI_INTRSTAT_HIGHC_Pos            (18UL)                    /*!< HIGHC (Bit 18)                                        */
30108 #define DSI_INTRSTAT_HIGHC_Msk            (0x40000UL)               /*!< HIGHC (Bitfield-Mask: 0x01)                           */
30109 #define DSI_INTRSTAT_TxDSII_Pos           (17UL)                    /*!< TxDSII (Bit 17)                                       */
30110 #define DSI_INTRSTAT_TxDSII_Msk           (0x20000UL)               /*!< TxDSII (Bitfield-Mask: 0x01)                          */
30111 #define DSI_INTRSTAT_TxDSIN_Pos           (16UL)                    /*!< TxDSIN (Bit 16)                                       */
30112 #define DSI_INTRSTAT_TxDSIN_Msk           (0x10000UL)               /*!< TxDSIN (Bitfield-Mask: 0x01)                          */
30113 #define DSI_INTRSTAT_TXCHECKSUM_Pos       (15UL)                    /*!< TXCHECKSUM (Bit 15)                                   */
30114 #define DSI_INTRSTAT_TXCHECKSUM_Msk       (0x8000UL)                /*!< TXCHECKSUM (Bitfield-Mask: 0x01)                      */
30115 #define DSI_INTRSTAT_TXECCM_Pos           (14UL)                    /*!< TXECCM (Bit 14)                                       */
30116 #define DSI_INTRSTAT_TXECCM_Msk           (0x4000UL)                /*!< TXECCM (Bitfield-Mask: 0x01)                          */
30117 #define DSI_INTRSTAT_TXECCS_Pos           (13UL)                    /*!< TXECCS (Bit 13)                                       */
30118 #define DSI_INTRSTAT_TXECCS_Msk           (0x2000UL)                /*!< TXECCS (Bitfield-Mask: 0x01)                          */
30119 #define DSI_INTRSTAT_TXFALSECNTRL_Pos     (12UL)                    /*!< TXFALSECNTRL (Bit 12)                                 */
30120 #define DSI_INTRSTAT_TXFALSECNTRL_Msk     (0x1000UL)                /*!< TXFALSECNTRL (Bitfield-Mask: 0x01)                    */
30121 #define DSI_INTRSTAT_RxDSIDI_Pos          (11UL)                    /*!< RxDSIDI (Bit 11)                                      */
30122 #define DSI_INTRSTAT_RxDSIDI_Msk          (0x800UL)                 /*!< RxDSIDI (Bitfield-Mask: 0x01)                         */
30123 #define DSI_INTRSTAT_RxDSINR_Pos          (10UL)                    /*!< RxDSINR (Bit 10)                                      */
30124 #define DSI_INTRSTAT_RxDSINR_Msk          (0x400UL)                 /*!< RxDSINR (Bitfield-Mask: 0x01)                         */
30125 #define DSI_INTRSTAT_RXCHECKSUM_Pos       (9UL)                     /*!< RXCHECKSUM (Bit 9)                                    */
30126 #define DSI_INTRSTAT_RXCHECKSUM_Msk       (0x200UL)                 /*!< RXCHECKSUM (Bitfield-Mask: 0x01)                      */
30127 #define DSI_INTRSTAT_RxECCM_Pos           (8UL)                     /*!< RxECCM (Bit 8)                                        */
30128 #define DSI_INTRSTAT_RxECCM_Msk           (0x100UL)                 /*!< RxECCM (Bitfield-Mask: 0x01)                          */
30129 #define DSI_INTRSTAT_RxECCS_Pos           (7UL)                     /*!< RxECCS (Bit 7)                                        */
30130 #define DSI_INTRSTAT_RxECCS_Msk           (0x80UL)                  /*!< RxECCS (Bitfield-Mask: 0x01)                          */
30131 #define DSI_INTRSTAT_RXFALSECNTRL_Pos     (6UL)                     /*!< RXFALSECNTRL (Bit 6)                                  */
30132 #define DSI_INTRSTAT_RXFALSECNTRL_Msk     (0x40UL)                  /*!< RXFALSECNTRL (Bitfield-Mask: 0x01)                    */
30133 #define DSI_INTRSTAT_RXPERIPHERAL_Pos     (5UL)                     /*!< RXPERIPHERAL (Bit 5)                                  */
30134 #define DSI_INTRSTAT_RXPERIPHERAL_Msk     (0x20UL)                  /*!< RXPERIPHERAL (Bitfield-Mask: 0x01)                    */
30135 #define DSI_INTRSTAT_RXLPTXSYNCERR_Pos    (4UL)                     /*!< RXLPTXSYNCERR (Bit 4)                                 */
30136 #define DSI_INTRSTAT_RXLPTXSYNCERR_Msk    (0x10UL)                  /*!< RXLPTXSYNCERR (Bitfield-Mask: 0x01)                   */
30137 #define DSI_INTRSTAT_RXESCAPEMODE_Pos     (3UL)                     /*!< RXESCAPEMODE (Bit 3)                                  */
30138 #define DSI_INTRSTAT_RXESCAPEMODE_Msk     (0x8UL)                   /*!< RXESCAPEMODE (Bitfield-Mask: 0x01)                    */
30139 #define DSI_INTRSTAT_RXEOTSYNCERROR_Pos   (2UL)                     /*!< RXEOTSYNCERROR (Bit 2)                                */
30140 #define DSI_INTRSTAT_RXEOTSYNCERROR_Msk   (0x4UL)                   /*!< RXEOTSYNCERROR (Bitfield-Mask: 0x01)                  */
30141 #define DSI_INTRSTAT_RXSOTSYNCERROR_Pos   (1UL)                     /*!< RXSOTSYNCERROR (Bit 1)                                */
30142 #define DSI_INTRSTAT_RXSOTSYNCERROR_Msk   (0x2UL)                   /*!< RXSOTSYNCERROR (Bitfield-Mask: 0x01)                  */
30143 #define DSI_INTRSTAT_RXSOTERROR_Pos       (0UL)                     /*!< RXSOTERROR (Bit 0)                                    */
30144 #define DSI_INTRSTAT_RXSOTERROR_Msk       (0x1UL)                   /*!< RXSOTERROR (Bitfield-Mask: 0x01)                      */
30145 /* ========================================================  INTREN  ========================================================= */
30146 #define DSI_INTREN_DPI_Pos                (31UL)                    /*!< DPI (Bit 31)                                          */
30147 #define DSI_INTREN_DPI_Msk                (0x80000000UL)            /*!< DPI (Bitfield-Mask: 0x01)                             */
30148 #define DSI_INTREN_DPILINETO_Pos          (30UL)                    /*!< DPILINETO (Bit 30)                                    */
30149 #define DSI_INTREN_DPILINETO_Msk          (0x40000000UL)            /*!< DPILINETO (Bitfield-Mask: 0x01)                       */
30150 #define DSI_INTREN_RXCONTENT_Pos          (29UL)                    /*!< RXCONTENT (Bit 29)                                    */
30151 #define DSI_INTREN_RXCONTENT_Msk          (0x20000000UL)            /*!< RXCONTENT (Bitfield-Mask: 0x01)                       */
30152 #define DSI_INTREN_INITDONE_Pos           (28UL)                    /*!< INITDONE (Bit 28)                                     */
30153 #define DSI_INTREN_INITDONE_Msk           (0x10000000UL)            /*!< INITDONE (Bitfield-Mask: 0x01)                        */
30154 #define DSI_INTREN_SPECIALPACK_Pos        (27UL)                    /*!< SPECIALPACK (Bit 27)                                  */
30155 #define DSI_INTREN_SPECIALPACK_Msk        (0x8000000UL)             /*!< SPECIALPACK (Bitfield-Mask: 0x01)                     */
30156 #define DSI_INTREN_RXDSI_Pos              (26UL)                    /*!< RXDSI (Bit 26)                                        */
30157 #define DSI_INTREN_RXDSI_Msk              (0x4000000UL)             /*!< RXDSI (Bitfield-Mask: 0x01)                           */
30158 #define DSI_INTREN_RXINV_Pos              (25UL)                    /*!< RXINV (Bit 25)                                        */
30159 #define DSI_INTREN_RXINV_Msk              (0x2000000UL)             /*!< RXINV (Bitfield-Mask: 0x01)                           */
30160 #define DSI_INTREN_ACKWITHNOERR_Pos       (24UL)                    /*!< ACKWITHNOERR (Bit 24)                                 */
30161 #define DSI_INTREN_ACKWITHNOERR_Msk       (0x1000000UL)             /*!< ACKWITHNOERR (Bitfield-Mask: 0x01)                    */
30162 #define DSI_INTREN_TURNARNDACK_Pos        (23UL)                    /*!< TURNARNDACK (Bit 23)                                  */
30163 #define DSI_INTREN_TURNARNDACK_Msk        (0x800000UL)              /*!< TURNARNDACK (Bitfield-Mask: 0x01)                     */
30164 #define DSI_INTREN_LPRXTIMEOUT_Pos        (22UL)                    /*!< LPRXTIMEOUT (Bit 22)                                  */
30165 #define DSI_INTREN_LPRXTIMEOUT_Msk        (0x400000UL)              /*!< LPRXTIMEOUT (Bitfield-Mask: 0x01)                     */
30166 #define DSI_INTREN_HSTXTIMEOUT_Pos        (21UL)                    /*!< HSTXTIMEOUT (Bit 21)                                  */
30167 #define DSI_INTREN_HSTXTIMEOUT_Msk        (0x200000UL)              /*!< HSTXTIMEOUT (Bitfield-Mask: 0x01)                     */
30168 #define DSI_INTREN_FIFOEMPTY_Pos          (20UL)                    /*!< FIFOEMPTY (Bit 20)                                    */
30169 #define DSI_INTREN_FIFOEMPTY_Msk          (0x100000UL)              /*!< FIFOEMPTY (Bitfield-Mask: 0x01)                       */
30170 #define DSI_INTREN_LOWC_Pos               (19UL)                    /*!< LOWC (Bit 19)                                         */
30171 #define DSI_INTREN_LOWC_Msk               (0x80000UL)               /*!< LOWC (Bitfield-Mask: 0x01)                            */
30172 #define DSI_INTREN_HIGHC_Pos              (18UL)                    /*!< HIGHC (Bit 18)                                        */
30173 #define DSI_INTREN_HIGHC_Msk              (0x40000UL)               /*!< HIGHC (Bitfield-Mask: 0x01)                           */
30174 #define DSI_INTREN_TxDSIV_Pos             (17UL)                    /*!< TxDSIV (Bit 17)                                       */
30175 #define DSI_INTREN_TxDSIV_Msk             (0x20000UL)               /*!< TxDSIV (Bitfield-Mask: 0x01)                          */
30176 #define DSI_INTREN_TxDSID_Pos             (16UL)                    /*!< TxDSID (Bit 16)                                       */
30177 #define DSI_INTREN_TxDSID_Msk             (0x10000UL)               /*!< TxDSID (Bitfield-Mask: 0x01)                          */
30178 #define DSI_INTREN_TXCHCKSUM_Pos          (15UL)                    /*!< TXCHCKSUM (Bit 15)                                    */
30179 #define DSI_INTREN_TXCHCKSUM_Msk          (0x8000UL)                /*!< TXCHCKSUM (Bitfield-Mask: 0x01)                       */
30180 #define DSI_INTREN_TxECCM_Pos             (14UL)                    /*!< TxECCM (Bit 14)                                       */
30181 #define DSI_INTREN_TxECCM_Msk             (0x4000UL)                /*!< TxECCM (Bitfield-Mask: 0x01)                          */
30182 #define DSI_INTREN_TxECCS_Pos             (13UL)                    /*!< TxECCS (Bit 13)                                       */
30183 #define DSI_INTREN_TxECCS_Msk             (0x2000UL)                /*!< TxECCS (Bitfield-Mask: 0x01)                          */
30184 #define DSI_INTREN_TxFalseCntrl_Pos       (12UL)                    /*!< TxFalseCntrl (Bit 12)                                 */
30185 #define DSI_INTREN_TxFalseCntrl_Msk       (0x1000UL)                /*!< TxFalseCntrl (Bitfield-Mask: 0x01)                    */
30186 #define DSI_INTREN_RxDSIV_Pos             (11UL)                    /*!< RxDSIV (Bit 11)                                       */
30187 #define DSI_INTREN_RxDSIV_Msk             (0x800UL)                 /*!< RxDSIV (Bitfield-Mask: 0x01)                          */
30188 #define DSI_INTREN_RxDSIData_Pos          (10UL)                    /*!< RxDSIData (Bit 10)                                    */
30189 #define DSI_INTREN_RxDSIData_Msk          (0x400UL)                 /*!< RxDSIData (Bitfield-Mask: 0x01)                       */
30190 #define DSI_INTREN_RXCHECKSUM_Pos         (9UL)                     /*!< RXCHECKSUM (Bit 9)                                    */
30191 #define DSI_INTREN_RXCHECKSUM_Msk         (0x200UL)                 /*!< RXCHECKSUM (Bitfield-Mask: 0x01)                      */
30192 #define DSI_INTREN_RXECCM_Pos             (8UL)                     /*!< RXECCM (Bit 8)                                        */
30193 #define DSI_INTREN_RXECCM_Msk             (0x100UL)                 /*!< RXECCM (Bitfield-Mask: 0x01)                          */
30194 #define DSI_INTREN_RXECCS_Pos             (7UL)                     /*!< RXECCS (Bit 7)                                        */
30195 #define DSI_INTREN_RXECCS_Msk             (0x80UL)                  /*!< RXECCS (Bitfield-Mask: 0x01)                          */
30196 #define DSI_INTREN_RXFALSE_Pos            (6UL)                     /*!< RXFALSE (Bit 6)                                       */
30197 #define DSI_INTREN_RXFALSE_Msk            (0x40UL)                  /*!< RXFALSE (Bitfield-Mask: 0x01)                         */
30198 #define DSI_INTREN_RXPERIPHRCVTOE_Pos     (5UL)                     /*!< RXPERIPHRCVTOE (Bit 5)                                */
30199 #define DSI_INTREN_RXPERIPHRCVTOE_Msk     (0x20UL)                  /*!< RXPERIPHRCVTOE (Bitfield-Mask: 0x01)                  */
30200 #define DSI_INTREN_RXLPTXSYNCERR_Pos      (4UL)                     /*!< RXLPTXSYNCERR (Bit 4)                                 */
30201 #define DSI_INTREN_RXLPTXSYNCERR_Msk      (0x10UL)                  /*!< RXLPTXSYNCERR (Bitfield-Mask: 0x01)                   */
30202 #define DSI_INTREN_RXESCPMDETRYERR_Pos    (3UL)                     /*!< RXESCPMDETRYERR (Bit 3)                               */
30203 #define DSI_INTREN_RXESCPMDETRYERR_Msk    (0x8UL)                   /*!< RXESCPMDETRYERR (Bitfield-Mask: 0x01)                 */
30204 #define DSI_INTREN_RXEOTSYNCRR_Pos        (2UL)                     /*!< RXEOTSYNCRR (Bit 2)                                   */
30205 #define DSI_INTREN_RXEOTSYNCRR_Msk        (0x4UL)                   /*!< RXEOTSYNCRR (Bitfield-Mask: 0x01)                     */
30206 #define DSI_INTREN_RXSOTSYNCERROR_Pos     (1UL)                     /*!< RXSOTSYNCERROR (Bit 1)                                */
30207 #define DSI_INTREN_RXSOTSYNCERROR_Msk     (0x2UL)                   /*!< RXSOTSYNCERROR (Bitfield-Mask: 0x01)                  */
30208 #define DSI_INTREN_RXSOTERROR_Pos         (0UL)                     /*!< RXSOTERROR (Bit 0)                                    */
30209 #define DSI_INTREN_RXSOTERROR_Msk         (0x1UL)                   /*!< RXSOTERROR (Bitfield-Mask: 0x01)                      */
30210 /* ======================================================  DSIFUNCPRG  ======================================================= */
30211 #define DSI_DSIFUNCPRG_REGNAME_Pos        (13UL)                    /*!< REGNAME (Bit 13)                                      */
30212 #define DSI_DSIFUNCPRG_REGNAME_Msk        (0xe000UL)                /*!< REGNAME (Bitfield-Mask: 0x07)                         */
30213 #define DSI_DSIFUNCPRG_SUPCOLVIDMODE_Pos  (7UL)                     /*!< SUPCOLVIDMODE (Bit 7)                                 */
30214 #define DSI_DSIFUNCPRG_SUPCOLVIDMODE_Msk  (0x380UL)                 /*!< SUPCOLVIDMODE (Bitfield-Mask: 0x07)                   */
30215 #define DSI_DSIFUNCPRG_CHNUMCMODE_Pos     (5UL)                     /*!< CHNUMCMODE (Bit 5)                                    */
30216 #define DSI_DSIFUNCPRG_CHNUMCMODE_Msk     (0x60UL)                  /*!< CHNUMCMODE (Bitfield-Mask: 0x03)                      */
30217 #define DSI_DSIFUNCPRG_CHNUMVM_Pos        (3UL)                     /*!< CHNUMVM (Bit 3)                                       */
30218 #define DSI_DSIFUNCPRG_CHNUMVM_Msk        (0x18UL)                  /*!< CHNUMVM (Bitfield-Mask: 0x03)                         */
30219 #define DSI_DSIFUNCPRG_DATALANES_Pos      (0UL)                     /*!< DATALANES (Bit 0)                                     */
30220 #define DSI_DSIFUNCPRG_DATALANES_Msk      (0x7UL)                   /*!< DATALANES (Bitfield-Mask: 0x07)                       */
30221 /* ======================================================  HSTXTIMEOUT  ====================================================== */
30222 #define DSI_HSTXTIMEOUT_MAXDURTOCNT_Pos   (0UL)                     /*!< MAXDURTOCNT (Bit 0)                                   */
30223 #define DSI_HSTXTIMEOUT_MAXDURTOCNT_Msk   (0xffffffUL)              /*!< MAXDURTOCNT (Bitfield-Mask: 0xffffff)                 */
30224 /* ========================================================  LPRXTO  ========================================================= */
30225 #define DSI_LPRXTO_TOCHKRVS_Pos           (0UL)                     /*!< TOCHKRVS (Bit 0)                                      */
30226 #define DSI_LPRXTO_TOCHKRVS_Msk           (0xffffffUL)              /*!< TOCHKRVS (Bitfield-Mask: 0xffffff)                    */
30227 /* ======================================================  TURNARNDTO  ======================================================= */
30228 #define DSI_TURNARNDTO_TIMOUT_Pos         (0UL)                     /*!< TIMOUT (Bit 0)                                        */
30229 #define DSI_TURNARNDTO_TIMOUT_Msk         (0x3fUL)                  /*!< TIMOUT (Bitfield-Mask: 0x3f)                          */
30230 /* ===================================================  DEVICERESETTIMER  ==================================================== */
30231 #define DSI_DEVICERESETTIMER_TIMOUT_Pos   (0UL)                     /*!< TIMOUT (Bit 0)                                        */
30232 #define DSI_DEVICERESETTIMER_TIMOUT_Msk   (0xffffUL)                /*!< TIMOUT (Bitfield-Mask: 0xffff)                        */
30233 /* =====================================================  DPIRESOLUTION  ===================================================== */
30234 #define DSI_DPIRESOLUTION_DPIRESOLUTION_Pos (0UL)                   /*!< DPIRESOLUTION (Bit 0)                                 */
30235 #define DSI_DPIRESOLUTION_DPIRESOLUTION_Msk (0xffffffffUL)          /*!< DPIRESOLUTION (Bitfield-Mask: 0xffffffff)             */
30236 /* =======================================================  HSYNCCNT  ======================================================== */
30237 #define DSI_HSYNCCNT_HORZCNT_Pos          (0UL)                     /*!< HORZCNT (Bit 0)                                       */
30238 #define DSI_HSYNCCNT_HORZCNT_Msk          (0xffffUL)                /*!< HORZCNT (Bitfield-Mask: 0xffff)                       */
30239 /* ====================================================  HORIZBKPORCHCNT  ==================================================== */
30240 #define DSI_HORIZBKPORCHCNT_HORZBKPCNT_Pos (0UL)                    /*!< HORZBKPCNT (Bit 0)                                    */
30241 #define DSI_HORIZBKPORCHCNT_HORZBKPCNT_Msk (0xffffUL)               /*!< HORZBKPCNT (Bitfield-Mask: 0xffff)                    */
30242 /* ====================================================  HORIZFPORCHCNT  ===================================================== */
30243 #define DSI_HORIZFPORCHCNT_HORZFTPCNT_Pos (0UL)                     /*!< HORZFTPCNT (Bit 0)                                    */
30244 #define DSI_HORIZFPORCHCNT_HORZFTPCNT_Msk (0xffffUL)                /*!< HORZFTPCNT (Bitfield-Mask: 0xffff)                    */
30245 /* ===================================================  HORZACTIVEAREACNT  =================================================== */
30246 #define DSI_HORZACTIVEAREACNT_HORACTCNT_Pos (0UL)                   /*!< HORACTCNT (Bit 0)                                     */
30247 #define DSI_HORZACTIVEAREACNT_HORACTCNT_Msk (0xffffUL)              /*!< HORACTCNT (Bitfield-Mask: 0xffff)                     */
30248 /* =======================================================  VSYNCCNT  ======================================================== */
30249 #define DSI_VSYNCCNT_VSC_Pos              (0UL)                     /*!< VSC (Bit 0)                                           */
30250 #define DSI_VSYNCCNT_VSC_Msk              (0xffffUL)                /*!< VSC (Bitfield-Mask: 0xffff)                           */
30251 /* ====================================================  VERTBKPORCHCNT  ===================================================== */
30252 #define DSI_VERTBKPORCHCNT_VBPSC_Pos      (0UL)                     /*!< VBPSC (Bit 0)                                         */
30253 #define DSI_VERTBKPORCHCNT_VBPSC_Msk      (0xffffUL)                /*!< VBPSC (Bitfield-Mask: 0xffff)                         */
30254 /* =====================================================  VERTFPORCHCNT  ===================================================== */
30255 #define DSI_VERTFPORCHCNT_VFPSC_Pos       (0UL)                     /*!< VFPSC (Bit 0)                                         */
30256 #define DSI_VERTFPORCHCNT_VFPSC_Msk       (0xffffUL)                /*!< VFPSC (Bitfield-Mask: 0xffff)                         */
30257 /* ===================================================  DATALANEHILOSWCNT  =================================================== */
30258 #define DSI_DATALANEHILOSWCNT_DATALHLSWCNT_Pos (0UL)                /*!< DATALHLSWCNT (Bit 0)                                  */
30259 #define DSI_DATALANEHILOSWCNT_DATALHLSWCNT_Msk (0xffffUL)           /*!< DATALHLSWCNT (Bitfield-Mask: 0xffff)                  */
30260 /* ==========================================================  DPI  ========================================================== */
30261 #define DSI_DPI_COLORMODEOFF_Pos          (3UL)                     /*!< COLORMODEOFF (Bit 3)                                  */
30262 #define DSI_DPI_COLORMODEOFF_Msk          (0x8UL)                   /*!< COLORMODEOFF (Bitfield-Mask: 0x01)                    */
30263 #define DSI_DPI_COLOR_Pos                 (2UL)                     /*!< COLOR (Bit 2)                                         */
30264 #define DSI_DPI_COLOR_Msk                 (0x4UL)                   /*!< COLOR (Bitfield-Mask: 0x01)                           */
30265 #define DSI_DPI_TURNON1_Pos               (1UL)                     /*!< TURNON1 (Bit 1)                                       */
30266 #define DSI_DPI_TURNON1_Msk               (0x2UL)                   /*!< TURNON1 (Bitfield-Mask: 0x01)                         */
30267 #define DSI_DPI_SHUTDOWN_Pos              (0UL)                     /*!< SHUTDOWN (Bit 0)                                      */
30268 #define DSI_DPI_SHUTDOWN_Msk              (0x1UL)                   /*!< SHUTDOWN (Bitfield-Mask: 0x01)                        */
30269 /* ======================================================  PLLLOCKCNT  ======================================================= */
30270 #define DSI_PLLLOCKCNT_PLLCNTVAL_Pos      (0UL)                     /*!< PLLCNTVAL (Bit 0)                                     */
30271 #define DSI_PLLLOCKCNT_PLLCNTVAL_Msk      (0xffffUL)                /*!< PLLCNTVAL (Bitfield-Mask: 0xffff)                     */
30272 /* ========================================================  INITCNT  ======================================================== */
30273 #define DSI_INITCNT_MSTR_Pos              (0UL)                     /*!< MSTR (Bit 0)                                          */
30274 #define DSI_INITCNT_MSTR_Msk              (0xffffUL)                /*!< MSTR (Bitfield-Mask: 0xffff)                          */
30275 /* =====================================================  MAXRETPACSZE  ====================================================== */
30276 #define DSI_MAXRETPACSZE_HSLP_Pos         (15UL)                    /*!< HSLP (Bit 15)                                         */
30277 #define DSI_MAXRETPACSZE_HSLP_Msk         (0x8000UL)                /*!< HSLP (Bitfield-Mask: 0x01)                            */
30278 #define DSI_MAXRETPACSZE_COUNTVAL_Pos     (0UL)                     /*!< COUNTVAL (Bit 0)                                      */
30279 #define DSI_MAXRETPACSZE_COUNTVAL_Msk     (0x7ffUL)                 /*!< COUNTVAL (Bitfield-Mask: 0x7ff)                       */
30280 /* =====================================================  VIDEOMODEFMT  ====================================================== */
30281 #define DSI_VIDEOMODEFMT_VIDEMDFMT_Pos    (0UL)                     /*!< VIDEMDFMT (Bit 0)                                     */
30282 #define DSI_VIDEOMODEFMT_VIDEMDFMT_Msk    (0x3UL)                   /*!< VIDEMDFMT (Bitfield-Mask: 0x03)                       */
30283 /* ========================================================  CLKEOT  ========================================================= */
30284 #define DSI_CLKEOT_BTA_Pos                (2UL)                     /*!< BTA (Bit 2)                                           */
30285 #define DSI_CLKEOT_BTA_Msk                (0x4UL)                   /*!< BTA (Bitfield-Mask: 0x01)                             */
30286 #define DSI_CLKEOT_CLOCK_Pos              (1UL)                     /*!< CLOCK (Bit 1)                                         */
30287 #define DSI_CLKEOT_CLOCK_Msk              (0x2UL)                   /*!< CLOCK (Bitfield-Mask: 0x01)                           */
30288 #define DSI_CLKEOT_EOT_Pos                (0UL)                     /*!< EOT (Bit 0)                                           */
30289 #define DSI_CLKEOT_EOT_Msk                (0x1UL)                   /*!< EOT (Bitfield-Mask: 0x01)                             */
30290 /* =======================================================  POLARITY  ======================================================== */
30291 #define DSI_POLARITY_PBITS_Pos            (0UL)                     /*!< PBITS (Bit 0)                                         */
30292 #define DSI_POLARITY_PBITS_Msk            (0xfUL)                   /*!< PBITS (Bitfield-Mask: 0x0f)                           */
30293 /* ======================================================  CLKLANESWT  ======================================================= */
30294 #define DSI_CLKLANESWT_LOWPWR2HI_Pos      (16UL)                    /*!< LOWPWR2HI (Bit 16)                                    */
30295 #define DSI_CLKLANESWT_LOWPWR2HI_Msk      (0xffff0000UL)            /*!< LOWPWR2HI (Bitfield-Mask: 0xffff)                     */
30296 #define DSI_CLKLANESWT_HISPLPSW_Pos       (0UL)                     /*!< HISPLPSW (Bit 0)                                      */
30297 #define DSI_CLKLANESWT_HISPLPSW_Msk       (0xffffUL)                /*!< HISPLPSW (Bitfield-Mask: 0xffff)                      */
30298 /* =======================================================  LPBYTECLK  ======================================================= */
30299 #define DSI_LPBYTECLK_VALBYTECLK_Pos      (0UL)                     /*!< VALBYTECLK (Bit 0)                                    */
30300 #define DSI_LPBYTECLK_VALBYTECLK_Msk      (0xffffUL)                /*!< VALBYTECLK (Bitfield-Mask: 0xffff)                    */
30301 /* =======================================================  DPHYPARAM  ======================================================= */
30302 #define DSI_DPHYPARAM_HSEXIT_Pos          (24UL)                    /*!< HSEXIT (Bit 24)                                       */
30303 #define DSI_DPHYPARAM_HSEXIT_Msk          (0xff000000UL)            /*!< HSEXIT (Bitfield-Mask: 0xff)                          */
30304 #define DSI_DPHYPARAM_HSTRAIL_Pos         (16UL)                    /*!< HSTRAIL (Bit 16)                                      */
30305 #define DSI_DPHYPARAM_HSTRAIL_Msk         (0xff0000UL)              /*!< HSTRAIL (Bitfield-Mask: 0xff)                         */
30306 #define DSI_DPHYPARAM_HSZERO_Pos          (8UL)                     /*!< HSZERO (Bit 8)                                        */
30307 #define DSI_DPHYPARAM_HSZERO_Msk          (0xff00UL)                /*!< HSZERO (Bitfield-Mask: 0xff)                          */
30308 #define DSI_DPHYPARAM_HSPREP_Pos          (0UL)                     /*!< HSPREP (Bit 0)                                        */
30309 #define DSI_DPHYPARAM_HSPREP_Msk          (0xffUL)                  /*!< HSPREP (Bitfield-Mask: 0xff)                          */
30310 /* ====================================================  CLKLANETIMPARM  ===================================================== */
30311 #define DSI_CLKLANETIMPARM_HSEXIT_Pos     (24UL)                    /*!< HSEXIT (Bit 24)                                       */
30312 #define DSI_CLKLANETIMPARM_HSEXIT_Msk     (0xff000000UL)            /*!< HSEXIT (Bitfield-Mask: 0xff)                          */
30313 #define DSI_CLKLANETIMPARM_HSTRAIL_Pos    (16UL)                    /*!< HSTRAIL (Bit 16)                                      */
30314 #define DSI_CLKLANETIMPARM_HSTRAIL_Msk    (0xff0000UL)              /*!< HSTRAIL (Bitfield-Mask: 0xff)                         */
30315 #define DSI_CLKLANETIMPARM_HSZERO_Pos     (8UL)                     /*!< HSZERO (Bit 8)                                        */
30316 #define DSI_CLKLANETIMPARM_HSZERO_Msk     (0xff00UL)                /*!< HSZERO (Bitfield-Mask: 0xff)                          */
30317 #define DSI_CLKLANETIMPARM_HSPREP_Pos     (0UL)                     /*!< HSPREP (Bit 0)                                        */
30318 #define DSI_CLKLANETIMPARM_HSPREP_Msk     (0xffUL)                  /*!< HSPREP (Bitfield-Mask: 0xff)                          */
30319 /* =======================================================  RSTENBDFE  ======================================================= */
30320 #define DSI_RSTENBDFE_ENABLE_Pos          (0UL)                     /*!< ENABLE (Bit 0)                                        */
30321 #define DSI_RSTENBDFE_ENABLE_Msk          (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
30322 /* =======================================================  AFETRIM0  ======================================================== */
30323 #define DSI_AFETRIM0_AFETRIM0_Pos         (0UL)                     /*!< AFETRIM0 (Bit 0)                                      */
30324 #define DSI_AFETRIM0_AFETRIM0_Msk         (0xffffffffUL)            /*!< AFETRIM0 (Bitfield-Mask: 0xffffffff)                  */
30325 /* =======================================================  AFETRIM1  ======================================================== */
30326 #define DSI_AFETRIM1_AFETRIM1_Pos         (0UL)                     /*!< AFETRIM1 (Bit 0)                                      */
30327 #define DSI_AFETRIM1_AFETRIM1_Msk         (0xffffffffUL)            /*!< AFETRIM1 (Bitfield-Mask: 0xffffffff)                  */
30328 /* =======================================================  AFETRIM2  ======================================================== */
30329 #define DSI_AFETRIM2_AFETRIM2_Pos         (0UL)                     /*!< AFETRIM2 (Bit 0)                                      */
30330 #define DSI_AFETRIM2_AFETRIM2_Msk         (0xffffffffUL)            /*!< AFETRIM2 (Bitfield-Mask: 0xffffffff)                  */
30331 /* =======================================================  AFETRIM3  ======================================================== */
30332 #define DSI_AFETRIM3_AFETRIM3_Pos         (0UL)                     /*!< AFETRIM3 (Bit 0)                                      */
30333 #define DSI_AFETRIM3_AFETRIM3_Msk         (0xffffffffUL)            /*!< AFETRIM3 (Bitfield-Mask: 0xffffffff)                  */
30334 /* =====================================================  ERRORAUTORCOV  ===================================================== */
30335 #define DSI_ERRORAUTORCOV_LPRXTIMEOUTCLR_Pos (5UL)                  /*!< LPRXTIMEOUTCLR (Bit 5)                                */
30336 #define DSI_ERRORAUTORCOV_LPRXTIMEOUTCLR_Msk (0x20UL)               /*!< LPRXTIMEOUTCLR (Bitfield-Mask: 0x01)                  */
30337 #define DSI_ERRORAUTORCOV_HSRXTIMEOUTCLR_Pos (4UL)                  /*!< HSRXTIMEOUTCLR (Bit 4)                                */
30338 #define DSI_ERRORAUTORCOV_HSRXTIMEOUTCLR_Msk (0x10UL)               /*!< HSRXTIMEOUTCLR (Bitfield-Mask: 0x01)                  */
30339 #define DSI_ERRORAUTORCOV_LOCONTCLR_Pos   (3UL)                     /*!< LOCONTCLR (Bit 3)                                     */
30340 #define DSI_ERRORAUTORCOV_LOCONTCLR_Msk   (0x8UL)                   /*!< LOCONTCLR (Bitfield-Mask: 0x01)                       */
30341 #define DSI_ERRORAUTORCOV_HICONTCLR_Pos   (2UL)                     /*!< HICONTCLR (Bit 2)                                     */
30342 #define DSI_ERRORAUTORCOV_HICONTCLR_Msk   (0x4UL)                   /*!< HICONTCLR (Bitfield-Mask: 0x01)                       */
30343 #define DSI_ERRORAUTORCOV_INVLDDTCLR_Pos  (1UL)                     /*!< INVLDDTCLR (Bit 1)                                    */
30344 #define DSI_ERRORAUTORCOV_INVLDDTCLR_Msk  (0x2UL)                   /*!< INVLDDTCLR (Bitfield-Mask: 0x01)                      */
30345 #define DSI_ERRORAUTORCOV_ECCMULERRCLR_Pos (0UL)                    /*!< ECCMULERRCLR (Bit 0)                                  */
30346 #define DSI_ERRORAUTORCOV_ECCMULERRCLR_Msk (0x1UL)                  /*!< ECCMULERRCLR (Bitfield-Mask: 0x01)                    */
30347 /* ====================================================  MIPIDIRDPIDIFF  ===================================================== */
30348 #define DSI_MIPIDIRDPIDIFF_DPIDIFF_Pos    (16UL)                    /*!< DPIDIFF (Bit 16)                                      */
30349 #define DSI_MIPIDIRDPIDIFF_DPIDIFF_Msk    (0xffff0000UL)            /*!< DPIDIFF (Bitfield-Mask: 0xffff)                       */
30350 #define DSI_MIPIDIRDPIDIFF_DPIHIGH_Pos    (15UL)                    /*!< DPIHIGH (Bit 15)                                      */
30351 #define DSI_MIPIDIRDPIDIFF_DPIHIGH_Msk    (0x8000UL)                /*!< DPIHIGH (Bitfield-Mask: 0x01)                         */
30352 #define DSI_MIPIDIRDPIDIFF_MIPIDIR_Pos    (0UL)                     /*!< MIPIDIR (Bit 0)                                       */
30353 #define DSI_MIPIDIRDPIDIFF_MIPIDIR_Msk    (0x1UL)                   /*!< MIPIDIR (Bitfield-Mask: 0x01)                         */
30354 /* ====================================================  DATALANEPOLSWAP  ==================================================== */
30355 #define DSI_DATALANEPOLSWAP_DATALNPOLSWAP_Pos (0UL)                 /*!< DATALNPOLSWAP (Bit 0)                                 */
30356 #define DSI_DATALANEPOLSWAP_DATALNPOLSWAP_Msk (0xfUL)               /*!< DATALNPOLSWAP (Bitfield-Mask: 0x0f)                   */
30357 
30358 
30359 /* =========================================================================================================================== */
30360 /* ================                                            DSP                                            ================ */
30361 /* =========================================================================================================================== */
30362 
30363 /* ========================================================  MUTEX0  ========================================================= */
30364 #define DSP_MUTEX0_MUTEX0_Pos             (0UL)                     /*!< MUTEX0 (Bit 0)                                        */
30365 #define DSP_MUTEX0_MUTEX0_Msk             (0x7UL)                   /*!< MUTEX0 (Bitfield-Mask: 0x07)                          */
30366 /* ========================================================  MUTEX1  ========================================================= */
30367 #define DSP_MUTEX1_MUTEX1_Pos             (0UL)                     /*!< MUTEX1 (Bit 0)                                        */
30368 #define DSP_MUTEX1_MUTEX1_Msk             (0x7UL)                   /*!< MUTEX1 (Bitfield-Mask: 0x07)                          */
30369 /* ========================================================  MUTEX2  ========================================================= */
30370 #define DSP_MUTEX2_MUTEX2_Pos             (0UL)                     /*!< MUTEX2 (Bit 0)                                        */
30371 #define DSP_MUTEX2_MUTEX2_Msk             (0x7UL)                   /*!< MUTEX2 (Bitfield-Mask: 0x07)                          */
30372 /* ========================================================  MUTEX3  ========================================================= */
30373 #define DSP_MUTEX3_MUTEX3_Pos             (0UL)                     /*!< MUTEX3 (Bit 0)                                        */
30374 #define DSP_MUTEX3_MUTEX3_Msk             (0x7UL)                   /*!< MUTEX3 (Bitfield-Mask: 0x07)                          */
30375 /* ========================================================  MUTEX4  ========================================================= */
30376 #define DSP_MUTEX4_MUTEX4_Pos             (0UL)                     /*!< MUTEX4 (Bit 0)                                        */
30377 #define DSP_MUTEX4_MUTEX4_Msk             (0x7UL)                   /*!< MUTEX4 (Bitfield-Mask: 0x07)                          */
30378 /* ========================================================  MUTEX5  ========================================================= */
30379 #define DSP_MUTEX5_MUTEX5_Pos             (0UL)                     /*!< MUTEX5 (Bit 0)                                        */
30380 #define DSP_MUTEX5_MUTEX5_Msk             (0x7UL)                   /*!< MUTEX5 (Bitfield-Mask: 0x07)                          */
30381 /* ========================================================  MUTEX6  ========================================================= */
30382 #define DSP_MUTEX6_MUTEX6_Pos             (0UL)                     /*!< MUTEX6 (Bit 0)                                        */
30383 #define DSP_MUTEX6_MUTEX6_Msk             (0x7UL)                   /*!< MUTEX6 (Bitfield-Mask: 0x07)                          */
30384 /* ========================================================  MUTEX7  ========================================================= */
30385 #define DSP_MUTEX7_MUTEX7_Pos             (0UL)                     /*!< MUTEX7 (Bit 0)                                        */
30386 #define DSP_MUTEX7_MUTEX7_Msk             (0x7UL)                   /*!< MUTEX7 (Bitfield-Mask: 0x07)                          */
30387 /* ======================================================  CPUMBINTSET  ====================================================== */
30388 #define DSP_CPUMBINTSET_CPUMBINTSET_Pos   (0UL)                     /*!< CPUMBINTSET (Bit 0)                                   */
30389 #define DSP_CPUMBINTSET_CPUMBINTSET_Msk   (0xffffffffUL)            /*!< CPUMBINTSET (Bitfield-Mask: 0xffffffff)               */
30390 /* ======================================================  CPUMBINTCLR  ====================================================== */
30391 #define DSP_CPUMBINTCLR_CPUMBINTCLR_Pos   (0UL)                     /*!< CPUMBINTCLR (Bit 0)                                   */
30392 #define DSP_CPUMBINTCLR_CPUMBINTCLR_Msk   (0xffffffffUL)            /*!< CPUMBINTCLR (Bitfield-Mask: 0xffffffff)               */
30393 /* =====================================================  CPUMBINTSTAT  ====================================================== */
30394 #define DSP_CPUMBINTSTAT_CPUMBINTSTAT_Pos (0UL)                     /*!< CPUMBINTSTAT (Bit 0)                                  */
30395 #define DSP_CPUMBINTSTAT_CPUMBINTSTAT_Msk (0xffffffffUL)            /*!< CPUMBINTSTAT (Bitfield-Mask: 0xffffffff)              */
30396 /* =====================================================  CPUCPUMBDATA  ====================================================== */
30397 #define DSP_CPUCPUMBDATA_CPUCPUMBDATA_Pos (0UL)                     /*!< CPUCPUMBDATA (Bit 0)                                  */
30398 #define DSP_CPUCPUMBDATA_CPUCPUMBDATA_Msk (0xffffffffUL)            /*!< CPUCPUMBDATA (Bitfield-Mask: 0xffffffff)              */
30399 /* =====================================================  DSP0CPUMBDATA  ===================================================== */
30400 #define DSP_DSP0CPUMBDATA_DSP0CPUMBDATA_Pos (0UL)                   /*!< DSP0CPUMBDATA (Bit 0)                                 */
30401 #define DSP_DSP0CPUMBDATA_DSP0CPUMBDATA_Msk (0xffffffffUL)          /*!< DSP0CPUMBDATA (Bitfield-Mask: 0xffffffff)             */
30402 /* =====================================================  DSP1CPUMBDATA  ===================================================== */
30403 #define DSP_DSP1CPUMBDATA_DSP1CPUMBDATA_Pos (0UL)                   /*!< DSP1CPUMBDATA (Bit 0)                                 */
30404 #define DSP_DSP1CPUMBDATA_DSP1CPUMBDATA_Msk (0xffffffffUL)          /*!< DSP1CPUMBDATA (Bitfield-Mask: 0xffffffff)             */
30405 /* =====================================================  DSP0MBINTSET  ====================================================== */
30406 #define DSP_DSP0MBINTSET_DSP0MBINTSET_Pos (0UL)                     /*!< DSP0MBINTSET (Bit 0)                                  */
30407 #define DSP_DSP0MBINTSET_DSP0MBINTSET_Msk (0xffffffffUL)            /*!< DSP0MBINTSET (Bitfield-Mask: 0xffffffff)              */
30408 /* =====================================================  DSP0MBINTCLR  ====================================================== */
30409 #define DSP_DSP0MBINTCLR_DSP0MBINTCLR_Pos (0UL)                     /*!< DSP0MBINTCLR (Bit 0)                                  */
30410 #define DSP_DSP0MBINTCLR_DSP0MBINTCLR_Msk (0xffffffffUL)            /*!< DSP0MBINTCLR (Bitfield-Mask: 0xffffffff)              */
30411 /* =====================================================  DSP0MBINTSTAT  ===================================================== */
30412 #define DSP_DSP0MBINTSTAT_DSP0MBINTSTAT_Pos (0UL)                   /*!< DSP0MBINTSTAT (Bit 0)                                 */
30413 #define DSP_DSP0MBINTSTAT_DSP0MBINTSTAT_Msk (0xffffffffUL)          /*!< DSP0MBINTSTAT (Bitfield-Mask: 0xffffffff)             */
30414 /* =====================================================  CPUDSP0MBDATA  ===================================================== */
30415 #define DSP_CPUDSP0MBDATA_CPUDSP0MBDATA_Pos (0UL)                   /*!< CPUDSP0MBDATA (Bit 0)                                 */
30416 #define DSP_CPUDSP0MBDATA_CPUDSP0MBDATA_Msk (0xffffffffUL)          /*!< CPUDSP0MBDATA (Bitfield-Mask: 0xffffffff)             */
30417 /* ====================================================  DSP0DSP0MBDATA  ===================================================== */
30418 #define DSP_DSP0DSP0MBDATA_DSP0DSP0MBDATA_Pos (0UL)                 /*!< DSP0DSP0MBDATA (Bit 0)                                */
30419 #define DSP_DSP0DSP0MBDATA_DSP0DSP0MBDATA_Msk (0xffffffffUL)        /*!< DSP0DSP0MBDATA (Bitfield-Mask: 0xffffffff)            */
30420 /* ====================================================  DSP1DSP0MBDATA  ===================================================== */
30421 #define DSP_DSP1DSP0MBDATA_DSP1DSP0MBDATA_Pos (0UL)                 /*!< DSP1DSP0MBDATA (Bit 0)                                */
30422 #define DSP_DSP1DSP0MBDATA_DSP1DSP0MBDATA_Msk (0xffffffffUL)        /*!< DSP1DSP0MBDATA (Bitfield-Mask: 0xffffffff)            */
30423 /* =====================================================  DSP1MBINTSET  ====================================================== */
30424 #define DSP_DSP1MBINTSET_DSP1MBINTSET_Pos (0UL)                     /*!< DSP1MBINTSET (Bit 0)                                  */
30425 #define DSP_DSP1MBINTSET_DSP1MBINTSET_Msk (0xffffffffUL)            /*!< DSP1MBINTSET (Bitfield-Mask: 0xffffffff)              */
30426 /* =====================================================  DSP1MBINTCLR  ====================================================== */
30427 #define DSP_DSP1MBINTCLR_DSP1MBINTCLR_Pos (0UL)                     /*!< DSP1MBINTCLR (Bit 0)                                  */
30428 #define DSP_DSP1MBINTCLR_DSP1MBINTCLR_Msk (0xffffffffUL)            /*!< DSP1MBINTCLR (Bitfield-Mask: 0xffffffff)              */
30429 /* =====================================================  DSP1MBINTSTAT  ===================================================== */
30430 #define DSP_DSP1MBINTSTAT_DSP1MBINTSTAT_Pos (0UL)                   /*!< DSP1MBINTSTAT (Bit 0)                                 */
30431 #define DSP_DSP1MBINTSTAT_DSP1MBINTSTAT_Msk (0xffffffffUL)          /*!< DSP1MBINTSTAT (Bitfield-Mask: 0xffffffff)             */
30432 /* =====================================================  CPUDSP1MBDATA  ===================================================== */
30433 #define DSP_CPUDSP1MBDATA_CPUDSP1MBDATA_Pos (0UL)                   /*!< CPUDSP1MBDATA (Bit 0)                                 */
30434 #define DSP_CPUDSP1MBDATA_CPUDSP1MBDATA_Msk (0xffffffffUL)          /*!< CPUDSP1MBDATA (Bitfield-Mask: 0xffffffff)             */
30435 /* ====================================================  DSP0DSP1MBDATA  ===================================================== */
30436 #define DSP_DSP0DSP1MBDATA_DSP0DSP1MBDATA_Pos (0UL)                 /*!< DSP0DSP1MBDATA (Bit 0)                                */
30437 #define DSP_DSP0DSP1MBDATA_DSP0DSP1MBDATA_Msk (0xffffffffUL)        /*!< DSP0DSP1MBDATA (Bitfield-Mask: 0xffffffff)            */
30438 /* ====================================================  DSP1DSP1MBDATA  ===================================================== */
30439 #define DSP_DSP1DSP1MBDATA_DSP1DSP1MBDATA_Pos (0UL)                 /*!< DSP1DSP1MBDATA (Bit 0)                                */
30440 #define DSP_DSP1DSP1MBDATA_DSP1DSP1MBDATA_Msk (0xffffffffUL)        /*!< DSP1DSP1MBDATA (Bitfield-Mask: 0xffffffff)            */
30441 /* ======================================================  DSP0CONTROL  ====================================================== */
30442 #define DSP_DSP0CONTROL_DSP0IDMAXTRIGSRC_Pos (8UL)                  /*!< DSP0IDMAXTRIGSRC (Bit 8)                              */
30443 #define DSP_DSP0CONTROL_DSP0IDMAXTRIGSRC_Msk (0x7fffff00UL)         /*!< DSP0IDMAXTRIGSRC (Bitfield-Mask: 0x7fffff)            */
30444 #define DSP_DSP0CONTROL_DSP0IDMATRIG_Pos  (4UL)                     /*!< DSP0IDMATRIG (Bit 4)                                  */
30445 #define DSP_DSP0CONTROL_DSP0IDMATRIG_Msk  (0x30UL)                  /*!< DSP0IDMATRIG (Bitfield-Mask: 0x03)                    */
30446 #define DSP_DSP0CONTROL_DSP0RUNSTALL_Pos  (3UL)                     /*!< DSP0RUNSTALL (Bit 3)                                  */
30447 #define DSP_DSP0CONTROL_DSP0RUNSTALL_Msk  (0x8UL)                   /*!< DSP0RUNSTALL (Bitfield-Mask: 0x01)                    */
30448 #define DSP_DSP0CONTROL_DSP0DRESET_Pos    (2UL)                     /*!< DSP0DRESET (Bit 2)                                    */
30449 #define DSP_DSP0CONTROL_DSP0DRESET_Msk    (0x4UL)                   /*!< DSP0DRESET (Bitfield-Mask: 0x01)                      */
30450 #define DSP_DSP0CONTROL_DSP0BRESET_Pos    (1UL)                     /*!< DSP0BRESET (Bit 1)                                    */
30451 #define DSP_DSP0CONTROL_DSP0BRESET_Msk    (0x2UL)                   /*!< DSP0BRESET (Bitfield-Mask: 0x01)                      */
30452 #define DSP_DSP0CONTROL_DSP0STATVECSEL_Pos (0UL)                    /*!< DSP0STATVECSEL (Bit 0)                                */
30453 #define DSP_DSP0CONTROL_DSP0STATVECSEL_Msk (0x1UL)                  /*!< DSP0STATVECSEL (Bitfield-Mask: 0x01)                  */
30454 /* =====================================================  DSP0RESETVEC  ====================================================== */
30455 #define DSP_DSP0RESETVEC_DSP0RESETVEC_Pos (0UL)                     /*!< DSP0RESETVEC (Bit 0)                                  */
30456 #define DSP_DSP0RESETVEC_DSP0RESETVEC_Msk (0xffffffffUL)            /*!< DSP0RESETVEC (Bitfield-Mask: 0xffffffff)              */
30457 /* ======================================================  DSP0IRQMASK  ====================================================== */
30458 #define DSP_DSP0IRQMASK_DSP0IRQMASK_Pos   (0UL)                     /*!< DSP0IRQMASK (Bit 0)                                   */
30459 #define DSP_DSP0IRQMASK_DSP0IRQMASK_Msk   (0x7fffffUL)              /*!< DSP0IRQMASK (Bitfield-Mask: 0x7fffff)                 */
30460 /* =====================================================  DSP0WAKEMASK  ====================================================== */
30461 #define DSP_DSP0WAKEMASK_DSP0WAKEMASK_Pos (0UL)                     /*!< DSP0WAKEMASK (Bit 0)                                  */
30462 #define DSP_DSP0WAKEMASK_DSP0WAKEMASK_Msk (0x7fffffUL)              /*!< DSP0WAKEMASK (Bitfield-Mask: 0x7fffff)                */
30463 /* ==================================================  DSP0RAWIRQSTAT31to0  ================================================== */
30464 #define DSP_DSP0RAWIRQSTAT31to0_DSP0RAWIRQSTAT31to0_Pos (0UL)       /*!< DSP0RAWIRQSTAT31to0 (Bit 0)                           */
30465 #define DSP_DSP0RAWIRQSTAT31to0_DSP0RAWIRQSTAT31to0_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT31to0 (Bitfield-Mask: 0xffffffff)    */
30466 /* =================================================  DSP0RAWIRQSTAT63to32  ================================================== */
30467 #define DSP_DSP0RAWIRQSTAT63to32_DSP0RAWIRQSTAT63to32_Pos (0UL)     /*!< DSP0RAWIRQSTAT63to32 (Bit 0)                          */
30468 #define DSP_DSP0RAWIRQSTAT63to32_DSP0RAWIRQSTAT63to32_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT63to32 (Bitfield-Mask: 0xffffffff) */
30469 /* =================================================  DSP0RAWIRQSTAT95to64  ================================================== */
30470 #define DSP_DSP0RAWIRQSTAT95to64_DSP0RAWIRQSTAT95to64_Pos (0UL)     /*!< DSP0RAWIRQSTAT95to64 (Bit 0)                          */
30471 #define DSP_DSP0RAWIRQSTAT95to64_DSP0RAWIRQSTAT95to64_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT95to64 (Bitfield-Mask: 0xffffffff) */
30472 /* =====================================================  DSP0L2LVLINT  ====================================================== */
30473 #define DSP_DSP0L2LVLINT_DSP0L2LVLINT_Pos (0UL)                     /*!< DSP0L2LVLINT (Bit 0)                                  */
30474 #define DSP_DSP0L2LVLINT_DSP0L2LVLINT_Msk (0x7ffffUL)               /*!< DSP0L2LVLINT (Bitfield-Mask: 0x7ffff)                 */
30475 /* =====================================================  DSP0L3LVLINT  ====================================================== */
30476 #define DSP_DSP0L3LVLINT_DSP0L3LVLINT_Pos (0UL)                     /*!< DSP0L3LVLINT (Bit 0)                                  */
30477 #define DSP_DSP0L3LVLINT_DSP0L3LVLINT_Msk (0x7ffffUL)               /*!< DSP0L3LVLINT (Bitfield-Mask: 0x7ffff)                 */
30478 /* =====================================================  DSP0L4LVLINT  ====================================================== */
30479 #define DSP_DSP0L4LVLINT_DSP0L4LVLINT_Pos (0UL)                     /*!< DSP0L4LVLINT (Bit 0)                                  */
30480 #define DSP_DSP0L4LVLINT_DSP0L4LVLINT_Msk (0x7ffffUL)               /*!< DSP0L4LVLINT (Bitfield-Mask: 0x7ffff)                 */
30481 /* =====================================================  DSP0L5LVLINT  ====================================================== */
30482 #define DSP_DSP0L5LVLINT_DSP0L5LVLINT_Pos (0UL)                     /*!< DSP0L5LVLINT (Bit 0)                                  */
30483 #define DSP_DSP0L5LVLINT_DSP0L5LVLINT_Msk (0x7ffffUL)               /*!< DSP0L5LVLINT (Bitfield-Mask: 0x7ffff)                 */
30484 /* ====================================================  DSP0IDMATRIGCTL  ==================================================== */
30485 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGPULSE_Pos (4UL)             /*!< DSP0IDMATRIGPULSE (Bit 4)                             */
30486 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGPULSE_Msk (0x10UL)          /*!< DSP0IDMATRIGPULSE (Bitfield-Mask: 0x01)               */
30487 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGSTAT_Pos (0UL)              /*!< DSP0IDMATRIGSTAT (Bit 0)                              */
30488 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGSTAT_Msk (0x1UL)            /*!< DSP0IDMATRIGSTAT (Bitfield-Mask: 0x01)                */
30489 /* ==================================================  DSP0INTORMASK31TO0A  ================================================== */
30490 #define DSP_DSP0INTORMASK31TO0A_DSP0INTMCUIOORMASKA_Pos (0UL)       /*!< DSP0INTMCUIOORMASKA (Bit 0)                           */
30491 #define DSP_DSP0INTORMASK31TO0A_DSP0INTMCUIOORMASKA_Msk (0xffffffffUL) /*!< DSP0INTMCUIOORMASKA (Bitfield-Mask: 0xffffffff)    */
30492 /* =================================================  DSP0INTORMASK63TO32A  ================================================== */
30493 #define DSP_DSP0INTORMASK63TO32A_DSP0GPIOORMASKA_Pos (24UL)         /*!< DSP0GPIOORMASKA (Bit 24)                              */
30494 #define DSP_DSP0INTORMASK63TO32A_DSP0GPIOORMASKA_Msk (0x3f000000UL) /*!< DSP0GPIOORMASKA (Bitfield-Mask: 0x3f)                 */
30495 #define DSP_DSP0INTORMASK63TO32A_DSP0PDMORMASKA_Pos (16UL)          /*!< DSP0PDMORMASKA (Bit 16)                               */
30496 #define DSP_DSP0INTORMASK63TO32A_DSP0PDMORMASKA_Msk (0xf0000UL)     /*!< DSP0PDMORMASKA (Bitfield-Mask: 0x0f)                  */
30497 #define DSP_DSP0INTORMASK63TO32A_DSP0I2SORMASKA_Pos (12UL)          /*!< DSP0I2SORMASKA (Bit 12)                               */
30498 #define DSP_DSP0INTORMASK63TO32A_DSP0I2SORMASKA_Msk (0xf000UL)      /*!< DSP0I2SORMASKA (Bitfield-Mask: 0x0f)                  */
30499 #define DSP_DSP0INTORMASK63TO32A_DSP0TMRORMASKA_Pos (0UL)           /*!< DSP0TMRORMASKA (Bit 0)                                */
30500 #define DSP_DSP0INTORMASK63TO32A_DSP0TMRORMASKA_Msk (0x3ffUL)       /*!< DSP0TMRORMASKA (Bitfield-Mask: 0x3ff)                 */
30501 /* =================================================  DSP0INTORMASK95TO64A  ================================================== */
30502 #define DSP_DSP0INTORMASK95TO64A_DSP0MBINTORMASKA_Pos (0UL)         /*!< DSP0MBINTORMASKA (Bit 0)                              */
30503 #define DSP_DSP0INTORMASK95TO64A_DSP0MBINTORMASKA_Msk (0xffffffffUL) /*!< DSP0MBINTORMASKA (Bitfield-Mask: 0xffffffff)         */
30504 /* ==================================================  DSP0INTORMASK31to0B  ================================================== */
30505 #define DSP_DSP0INTORMASK31to0B_DSP0INTMCUIOORMASKB_Pos (0UL)       /*!< DSP0INTMCUIOORMASKB (Bit 0)                           */
30506 #define DSP_DSP0INTORMASK31to0B_DSP0INTMCUIOORMASKB_Msk (0xffffffffUL) /*!< DSP0INTMCUIOORMASKB (Bitfield-Mask: 0xffffffff)    */
30507 /* =================================================  DSP0INTORMASK63TO32B  ================================================== */
30508 #define DSP_DSP0INTORMASK63TO32B_DSP0GPIOORMASKB_Pos (24UL)         /*!< DSP0GPIOORMASKB (Bit 24)                              */
30509 #define DSP_DSP0INTORMASK63TO32B_DSP0GPIOORMASKB_Msk (0x3f000000UL) /*!< DSP0GPIOORMASKB (Bitfield-Mask: 0x3f)                 */
30510 #define DSP_DSP0INTORMASK63TO32B_DSP0PDMORMASKB_Pos (16UL)          /*!< DSP0PDMORMASKB (Bit 16)                               */
30511 #define DSP_DSP0INTORMASK63TO32B_DSP0PDMORMASKB_Msk (0xf0000UL)     /*!< DSP0PDMORMASKB (Bitfield-Mask: 0x0f)                  */
30512 #define DSP_DSP0INTORMASK63TO32B_DSP0I2SORMASKB_Pos (12UL)          /*!< DSP0I2SORMASKB (Bit 12)                               */
30513 #define DSP_DSP0INTORMASK63TO32B_DSP0I2SORMASKB_Msk (0xf000UL)      /*!< DSP0I2SORMASKB (Bitfield-Mask: 0x0f)                  */
30514 #define DSP_DSP0INTORMASK63TO32B_DSP0TMRORMASKB_Pos (0UL)           /*!< DSP0TMRORMASKB (Bit 0)                                */
30515 #define DSP_DSP0INTORMASK63TO32B_DSP0TMRORMASKB_Msk (0x3ffUL)       /*!< DSP0TMRORMASKB (Bitfield-Mask: 0x3ff)                 */
30516 /* =================================================  DSP0INTORMASK95TO64B  ================================================== */
30517 #define DSP_DSP0INTORMASK95TO64B_DSP0MBINTORMASKB_Pos (0UL)         /*!< DSP0MBINTORMASKB (Bit 0)                              */
30518 #define DSP_DSP0INTORMASK95TO64B_DSP0MBINTORMASKB_Msk (0xffffffffUL) /*!< DSP0MBINTORMASKB (Bitfield-Mask: 0xffffffff)         */
30519 /* ===================================================  DSP0INTENIRQ31TO0  =================================================== */
30520 #define DSP_DSP0INTENIRQ31TO0_DSP0INTENIRQ31TO0_Pos (0UL)           /*!< DSP0INTENIRQ31TO0 (Bit 0)                             */
30521 #define DSP_DSP0INTENIRQ31TO0_DSP0INTENIRQ31TO0_Msk (0xffffffffUL)  /*!< DSP0INTENIRQ31TO0 (Bitfield-Mask: 0xffffffff)         */
30522 /* ==================================================  DSP0INTENIRQ63TO32  =================================================== */
30523 #define DSP_DSP0INTENIRQ63TO32_DSP0INTENIRQ63TO32_Pos (0UL)         /*!< DSP0INTENIRQ63TO32 (Bit 0)                            */
30524 #define DSP_DSP0INTENIRQ63TO32_DSP0INTENIRQ63TO32_Msk (0xffffffffUL) /*!< DSP0INTENIRQ63TO32 (Bitfield-Mask: 0xffffffff)       */
30525 /* ==================================================  DSP0INTENIRQ95TO64  =================================================== */
30526 #define DSP_DSP0INTENIRQ95TO64_DSP0INTENIRQ95TO64_Pos (0UL)         /*!< DSP0INTENIRQ95TO64 (Bit 0)                            */
30527 #define DSP_DSP0INTENIRQ95TO64_DSP0INTENIRQ95TO64_Msk (0xffffffffUL) /*!< DSP0INTENIRQ95TO64 (Bitfield-Mask: 0xffffffff)       */
30528 /* ======================================================  DSP1CONTROL  ====================================================== */
30529 #define DSP_DSP1CONTROL_DSP1IDMAXTRIGSRC_Pos (8UL)                  /*!< DSP1IDMAXTRIGSRC (Bit 8)                              */
30530 #define DSP_DSP1CONTROL_DSP1IDMAXTRIGSRC_Msk (0x7fffff00UL)         /*!< DSP1IDMAXTRIGSRC (Bitfield-Mask: 0x7fffff)            */
30531 #define DSP_DSP1CONTROL_DSP1IDMATRIG_Pos  (4UL)                     /*!< DSP1IDMATRIG (Bit 4)                                  */
30532 #define DSP_DSP1CONTROL_DSP1IDMATRIG_Msk  (0x30UL)                  /*!< DSP1IDMATRIG (Bitfield-Mask: 0x03)                    */
30533 #define DSP_DSP1CONTROL_DSP1RUNSTALL_Pos  (3UL)                     /*!< DSP1RUNSTALL (Bit 3)                                  */
30534 #define DSP_DSP1CONTROL_DSP1RUNSTALL_Msk  (0x8UL)                   /*!< DSP1RUNSTALL (Bitfield-Mask: 0x01)                    */
30535 #define DSP_DSP1CONTROL_DSP1DRESET_Pos    (2UL)                     /*!< DSP1DRESET (Bit 2)                                    */
30536 #define DSP_DSP1CONTROL_DSP1DRESET_Msk    (0x4UL)                   /*!< DSP1DRESET (Bitfield-Mask: 0x01)                      */
30537 #define DSP_DSP1CONTROL_DSP1BRESET_Pos    (1UL)                     /*!< DSP1BRESET (Bit 1)                                    */
30538 #define DSP_DSP1CONTROL_DSP1BRESET_Msk    (0x2UL)                   /*!< DSP1BRESET (Bitfield-Mask: 0x01)                      */
30539 #define DSP_DSP1CONTROL_DSP1STATVECSEL_Pos (0UL)                    /*!< DSP1STATVECSEL (Bit 0)                                */
30540 #define DSP_DSP1CONTROL_DSP1STATVECSEL_Msk (0x1UL)                  /*!< DSP1STATVECSEL (Bitfield-Mask: 0x01)                  */
30541 /* =====================================================  DSP1RESETVEC  ====================================================== */
30542 #define DSP_DSP1RESETVEC_DSP1RESETVEC_Pos (0UL)                     /*!< DSP1RESETVEC (Bit 0)                                  */
30543 #define DSP_DSP1RESETVEC_DSP1RESETVEC_Msk (0xffffffffUL)            /*!< DSP1RESETVEC (Bitfield-Mask: 0xffffffff)              */
30544 /* ======================================================  DSP1IRQMASK  ====================================================== */
30545 #define DSP_DSP1IRQMASK_DSP1IRQMASK_Pos   (0UL)                     /*!< DSP1IRQMASK (Bit 0)                                   */
30546 #define DSP_DSP1IRQMASK_DSP1IRQMASK_Msk   (0x7fffffUL)              /*!< DSP1IRQMASK (Bitfield-Mask: 0x7fffff)                 */
30547 /* =====================================================  DSP1WAKEMASK  ====================================================== */
30548 #define DSP_DSP1WAKEMASK_DSP1WAKEMASK_Pos (0UL)                     /*!< DSP1WAKEMASK (Bit 0)                                  */
30549 #define DSP_DSP1WAKEMASK_DSP1WAKEMASK_Msk (0x7fffffUL)              /*!< DSP1WAKEMASK (Bitfield-Mask: 0x7fffff)                */
30550 /* ==================================================  DSP1RAWIRQSTAT31to0  ================================================== */
30551 #define DSP_DSP1RAWIRQSTAT31to0_DSP1RAWIRQSTAT31to0_Pos (0UL)       /*!< DSP1RAWIRQSTAT31to0 (Bit 0)                           */
30552 #define DSP_DSP1RAWIRQSTAT31to0_DSP1RAWIRQSTAT31to0_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT31to0 (Bitfield-Mask: 0xffffffff)    */
30553 /* =================================================  DSP1RAWIRQSTAT63to32  ================================================== */
30554 #define DSP_DSP1RAWIRQSTAT63to32_DSP1RAWIRQSTAT63to32_Pos (0UL)     /*!< DSP1RAWIRQSTAT63to32 (Bit 0)                          */
30555 #define DSP_DSP1RAWIRQSTAT63to32_DSP1RAWIRQSTAT63to32_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT63to32 (Bitfield-Mask: 0xffffffff) */
30556 /* =================================================  DSP1RAWIRQSTAT95to64  ================================================== */
30557 #define DSP_DSP1RAWIRQSTAT95to64_DSP1RAWIRQSTAT95to64_Pos (0UL)     /*!< DSP1RAWIRQSTAT95to64 (Bit 0)                          */
30558 #define DSP_DSP1RAWIRQSTAT95to64_DSP1RAWIRQSTAT95to64_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT95to64 (Bitfield-Mask: 0xffffffff) */
30559 /* =====================================================  DSP1L2LVLINT  ====================================================== */
30560 #define DSP_DSP1L2LVLINT_DSP1L2LVLINT_Pos (0UL)                     /*!< DSP1L2LVLINT (Bit 0)                                  */
30561 #define DSP_DSP1L2LVLINT_DSP1L2LVLINT_Msk (0x7ffffUL)               /*!< DSP1L2LVLINT (Bitfield-Mask: 0x7ffff)                 */
30562 /* =====================================================  DSP1L3LVLINT  ====================================================== */
30563 #define DSP_DSP1L3LVLINT_DSP1L3LVLINT_Pos (0UL)                     /*!< DSP1L3LVLINT (Bit 0)                                  */
30564 #define DSP_DSP1L3LVLINT_DSP1L3LVLINT_Msk (0x7ffffUL)               /*!< DSP1L3LVLINT (Bitfield-Mask: 0x7ffff)                 */
30565 /* =====================================================  DSP1L4LVLINT  ====================================================== */
30566 #define DSP_DSP1L4LVLINT_DSP1L4LVLINT_Pos (0UL)                     /*!< DSP1L4LVLINT (Bit 0)                                  */
30567 #define DSP_DSP1L4LVLINT_DSP1L4LVLINT_Msk (0x7ffffUL)               /*!< DSP1L4LVLINT (Bitfield-Mask: 0x7ffff)                 */
30568 /* =====================================================  DSP1L5LVLINT  ====================================================== */
30569 #define DSP_DSP1L5LVLINT_DSP1L5LVLINT_Pos (0UL)                     /*!< DSP1L5LVLINT (Bit 0)                                  */
30570 #define DSP_DSP1L5LVLINT_DSP1L5LVLINT_Msk (0x7ffffUL)               /*!< DSP1L5LVLINT (Bitfield-Mask: 0x7ffff)                 */
30571 /* ====================================================  DSP1IDMATRIGCTL  ==================================================== */
30572 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGPULSE_Pos (4UL)             /*!< DSP1IDMATRIGPULSE (Bit 4)                             */
30573 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGPULSE_Msk (0x10UL)          /*!< DSP1IDMATRIGPULSE (Bitfield-Mask: 0x01)               */
30574 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGSTAT_Pos (0UL)              /*!< DSP1IDMATRIGSTAT (Bit 0)                              */
30575 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGSTAT_Msk (0x1UL)            /*!< DSP1IDMATRIGSTAT (Bitfield-Mask: 0x01)                */
30576 /* ==================================================  DSP1INTORMASK31TO0A  ================================================== */
30577 #define DSP_DSP1INTORMASK31TO0A_DSP1INTMCUIOORMASKA_Pos (0UL)       /*!< DSP1INTMCUIOORMASKA (Bit 0)                           */
30578 #define DSP_DSP1INTORMASK31TO0A_DSP1INTMCUIOORMASKA_Msk (0xffffffffUL) /*!< DSP1INTMCUIOORMASKA (Bitfield-Mask: 0xffffffff)    */
30579 /* =================================================  DSP1INTORMASK63TO32A  ================================================== */
30580 #define DSP_DSP1INTORMASK63TO32A_DSP1GPIOORMASKA_Pos (24UL)         /*!< DSP1GPIOORMASKA (Bit 24)                              */
30581 #define DSP_DSP1INTORMASK63TO32A_DSP1GPIOORMASKA_Msk (0x3f000000UL) /*!< DSP1GPIOORMASKA (Bitfield-Mask: 0x3f)                 */
30582 #define DSP_DSP1INTORMASK63TO32A_DSP1PDMORMASKA_Pos (16UL)          /*!< DSP1PDMORMASKA (Bit 16)                               */
30583 #define DSP_DSP1INTORMASK63TO32A_DSP1PDMORMASKA_Msk (0xf0000UL)     /*!< DSP1PDMORMASKA (Bitfield-Mask: 0x0f)                  */
30584 #define DSP_DSP1INTORMASK63TO32A_DSP1I2SORMASKA_Pos (12UL)          /*!< DSP1I2SORMASKA (Bit 12)                               */
30585 #define DSP_DSP1INTORMASK63TO32A_DSP1I2SORMASKA_Msk (0xf000UL)      /*!< DSP1I2SORMASKA (Bitfield-Mask: 0x0f)                  */
30586 #define DSP_DSP1INTORMASK63TO32A_DSP1TMRORMASKA_Pos (0UL)           /*!< DSP1TMRORMASKA (Bit 0)                                */
30587 #define DSP_DSP1INTORMASK63TO32A_DSP1TMRORMASKA_Msk (0x3ffUL)       /*!< DSP1TMRORMASKA (Bitfield-Mask: 0x3ff)                 */
30588 /* =================================================  DSP1INTORMASK95TO64A  ================================================== */
30589 #define DSP_DSP1INTORMASK95TO64A_DSP1MBINTORMASKA_Pos (0UL)         /*!< DSP1MBINTORMASKA (Bit 0)                              */
30590 #define DSP_DSP1INTORMASK95TO64A_DSP1MBINTORMASKA_Msk (0xffffffffUL) /*!< DSP1MBINTORMASKA (Bitfield-Mask: 0xffffffff)         */
30591 /* ==================================================  DSP1INTORMASK31to0B  ================================================== */
30592 #define DSP_DSP1INTORMASK31to0B_DSP1INTMCUIOORMASKB_Pos (0UL)       /*!< DSP1INTMCUIOORMASKB (Bit 0)                           */
30593 #define DSP_DSP1INTORMASK31to0B_DSP1INTMCUIOORMASKB_Msk (0xffffffffUL) /*!< DSP1INTMCUIOORMASKB (Bitfield-Mask: 0xffffffff)    */
30594 /* =================================================  DSP1INTORMASK63TO32B  ================================================== */
30595 #define DSP_DSP1INTORMASK63TO32B_DSP1GPIOORMASKB_Pos (24UL)         /*!< DSP1GPIOORMASKB (Bit 24)                              */
30596 #define DSP_DSP1INTORMASK63TO32B_DSP1GPIOORMASKB_Msk (0x3f000000UL) /*!< DSP1GPIOORMASKB (Bitfield-Mask: 0x3f)                 */
30597 #define DSP_DSP1INTORMASK63TO32B_DSP1PDMORMASKB_Pos (16UL)          /*!< DSP1PDMORMASKB (Bit 16)                               */
30598 #define DSP_DSP1INTORMASK63TO32B_DSP1PDMORMASKB_Msk (0xf0000UL)     /*!< DSP1PDMORMASKB (Bitfield-Mask: 0x0f)                  */
30599 #define DSP_DSP1INTORMASK63TO32B_DSP1I2SORMASKB_Pos (12UL)          /*!< DSP1I2SORMASKB (Bit 12)                               */
30600 #define DSP_DSP1INTORMASK63TO32B_DSP1I2SORMASKB_Msk (0xf000UL)      /*!< DSP1I2SORMASKB (Bitfield-Mask: 0x0f)                  */
30601 #define DSP_DSP1INTORMASK63TO32B_DSP1TMRORMASKB_Pos (0UL)           /*!< DSP1TMRORMASKB (Bit 0)                                */
30602 #define DSP_DSP1INTORMASK63TO32B_DSP1TMRORMASKB_Msk (0x3ffUL)       /*!< DSP1TMRORMASKB (Bitfield-Mask: 0x3ff)                 */
30603 /* =================================================  DSP1INTORMASK95TO64B  ================================================== */
30604 #define DSP_DSP1INTORMASK95TO64B_DSP1MBINTORMASKB_Pos (0UL)         /*!< DSP1MBINTORMASKB (Bit 0)                              */
30605 #define DSP_DSP1INTORMASK95TO64B_DSP1MBINTORMASKB_Msk (0xffffffffUL) /*!< DSP1MBINTORMASKB (Bitfield-Mask: 0xffffffff)         */
30606 /* ===================================================  DSP1INTENIRQ31TO0  =================================================== */
30607 #define DSP_DSP1INTENIRQ31TO0_DSP1INTENIRQ31TO0_Pos (0UL)           /*!< DSP1INTENIRQ31TO0 (Bit 0)                             */
30608 #define DSP_DSP1INTENIRQ31TO0_DSP1INTENIRQ31TO0_Msk (0xffffffffUL)  /*!< DSP1INTENIRQ31TO0 (Bitfield-Mask: 0xffffffff)         */
30609 /* ==================================================  DSP1INTENIRQ63TO32  =================================================== */
30610 #define DSP_DSP1INTENIRQ63TO32_DSP1INTENIRQ63TO32_Pos (0UL)         /*!< DSP1INTENIRQ63TO32 (Bit 0)                            */
30611 #define DSP_DSP1INTENIRQ63TO32_DSP1INTENIRQ63TO32_Msk (0xffffffffUL) /*!< DSP1INTENIRQ63TO32 (Bitfield-Mask: 0xffffffff)       */
30612 /* ==================================================  DSP1INTENIRQ95TO64  =================================================== */
30613 #define DSP_DSP1INTENIRQ95TO64_DSP1INTENIRQ95TO64_Pos (0UL)         /*!< DSP1INTENIRQ95TO64 (Bit 0)                            */
30614 #define DSP_DSP1INTENIRQ95TO64_DSP1INTENIRQ95TO64_Msk (0xffffffffUL) /*!< DSP1INTENIRQ95TO64 (Bitfield-Mask: 0xffffffff)       */
30615 
30616 
30617 /* =========================================================================================================================== */
30618 /* ================                                           FPIO                                            ================ */
30619 /* =========================================================================================================================== */
30620 
30621 /* ==========================================================  RD0  ========================================================== */
30622 #define FPIO_RD0_RD0_Pos                  (0UL)                     /*!< RD0 (Bit 0)                                           */
30623 #define FPIO_RD0_RD0_Msk                  (0xffffffffUL)            /*!< RD0 (Bitfield-Mask: 0xffffffff)                       */
30624 /* ==========================================================  RD1  ========================================================== */
30625 #define FPIO_RD1_RD1_Pos                  (0UL)                     /*!< RD1 (Bit 0)                                           */
30626 #define FPIO_RD1_RD1_Msk                  (0xffffffffUL)            /*!< RD1 (Bitfield-Mask: 0xffffffff)                       */
30627 /* ==========================================================  RD2  ========================================================== */
30628 #define FPIO_RD2_RD2_Pos                  (0UL)                     /*!< RD2 (Bit 0)                                           */
30629 #define FPIO_RD2_RD2_Msk                  (0xffffffffUL)            /*!< RD2 (Bitfield-Mask: 0xffffffff)                       */
30630 /* ==========================================================  RD3  ========================================================== */
30631 #define FPIO_RD3_RD3_Pos                  (0UL)                     /*!< RD3 (Bit 0)                                           */
30632 #define FPIO_RD3_RD3_Msk                  (0xffffffffUL)            /*!< RD3 (Bitfield-Mask: 0xffffffff)                       */
30633 /* ==========================================================  WT0  ========================================================== */
30634 #define FPIO_WT0_WT0_Pos                  (0UL)                     /*!< WT0 (Bit 0)                                           */
30635 #define FPIO_WT0_WT0_Msk                  (0xffffffffUL)            /*!< WT0 (Bitfield-Mask: 0xffffffff)                       */
30636 /* ==========================================================  WT1  ========================================================== */
30637 #define FPIO_WT1_WT1_Pos                  (0UL)                     /*!< WT1 (Bit 0)                                           */
30638 #define FPIO_WT1_WT1_Msk                  (0xffffffffUL)            /*!< WT1 (Bitfield-Mask: 0xffffffff)                       */
30639 /* ==========================================================  WT2  ========================================================== */
30640 #define FPIO_WT2_WT2_Pos                  (0UL)                     /*!< WT2 (Bit 0)                                           */
30641 #define FPIO_WT2_WT2_Msk                  (0xffffffffUL)            /*!< WT2 (Bitfield-Mask: 0xffffffff)                       */
30642 /* ==========================================================  WT3  ========================================================== */
30643 #define FPIO_WT3_WT3_Pos                  (0UL)                     /*!< WT3 (Bit 0)                                           */
30644 #define FPIO_WT3_WT3_Msk                  (0xffffffffUL)            /*!< WT3 (Bitfield-Mask: 0xffffffff)                       */
30645 /* =========================================================  WTS0  ========================================================== */
30646 #define FPIO_WTS0_WTS0_Pos                (0UL)                     /*!< WTS0 (Bit 0)                                          */
30647 #define FPIO_WTS0_WTS0_Msk                (0xffffffffUL)            /*!< WTS0 (Bitfield-Mask: 0xffffffff)                      */
30648 /* =========================================================  WTS1  ========================================================== */
30649 #define FPIO_WTS1_WTS1_Pos                (0UL)                     /*!< WTS1 (Bit 0)                                          */
30650 #define FPIO_WTS1_WTS1_Msk                (0xffffffffUL)            /*!< WTS1 (Bitfield-Mask: 0xffffffff)                      */
30651 /* =========================================================  WTS2  ========================================================== */
30652 #define FPIO_WTS2_WTS2_Pos                (0UL)                     /*!< WTS2 (Bit 0)                                          */
30653 #define FPIO_WTS2_WTS2_Msk                (0xffffffffUL)            /*!< WTS2 (Bitfield-Mask: 0xffffffff)                      */
30654 /* =========================================================  WTS3  ========================================================== */
30655 #define FPIO_WTS3_WTS3_Pos                (0UL)                     /*!< WTS3 (Bit 0)                                          */
30656 #define FPIO_WTS3_WTS3_Msk                (0xffffffffUL)            /*!< WTS3 (Bitfield-Mask: 0xffffffff)                      */
30657 /* =========================================================  WTC0  ========================================================== */
30658 #define FPIO_WTC0_WTC0_Pos                (0UL)                     /*!< WTC0 (Bit 0)                                          */
30659 #define FPIO_WTC0_WTC0_Msk                (0xffffffffUL)            /*!< WTC0 (Bitfield-Mask: 0xffffffff)                      */
30660 /* =========================================================  WTC1  ========================================================== */
30661 #define FPIO_WTC1_WTC1_Pos                (0UL)                     /*!< WTC1 (Bit 0)                                          */
30662 #define FPIO_WTC1_WTC1_Msk                (0xffffffffUL)            /*!< WTC1 (Bitfield-Mask: 0xffffffff)                      */
30663 /* =========================================================  WTC2  ========================================================== */
30664 #define FPIO_WTC2_WTC2_Pos                (0UL)                     /*!< WTC2 (Bit 0)                                          */
30665 #define FPIO_WTC2_WTC2_Msk                (0xffffffffUL)            /*!< WTC2 (Bitfield-Mask: 0xffffffff)                      */
30666 /* =========================================================  WTC3  ========================================================== */
30667 #define FPIO_WTC3_WTC3_Pos                (0UL)                     /*!< WTC3 (Bit 0)                                          */
30668 #define FPIO_WTC3_WTC3_Msk                (0xffffffffUL)            /*!< WTC3 (Bitfield-Mask: 0xffffffff)                      */
30669 /* ==========================================================  EN0  ========================================================== */
30670 #define FPIO_EN0_EN0_Pos                  (0UL)                     /*!< EN0 (Bit 0)                                           */
30671 #define FPIO_EN0_EN0_Msk                  (0xffffffffUL)            /*!< EN0 (Bitfield-Mask: 0xffffffff)                       */
30672 /* ==========================================================  EN1  ========================================================== */
30673 #define FPIO_EN1_EN1_Pos                  (0UL)                     /*!< EN1 (Bit 0)                                           */
30674 #define FPIO_EN1_EN1_Msk                  (0xffffffffUL)            /*!< EN1 (Bitfield-Mask: 0xffffffff)                       */
30675 /* ==========================================================  EN2  ========================================================== */
30676 #define FPIO_EN2_EN2_Pos                  (0UL)                     /*!< EN2 (Bit 0)                                           */
30677 #define FPIO_EN2_EN2_Msk                  (0xffffffffUL)            /*!< EN2 (Bitfield-Mask: 0xffffffff)                       */
30678 /* ==========================================================  EN3  ========================================================== */
30679 #define FPIO_EN3_EN3_Pos                  (0UL)                     /*!< EN3 (Bit 0)                                           */
30680 #define FPIO_EN3_EN3_Msk                  (0xffffffffUL)            /*!< EN3 (Bitfield-Mask: 0xffffffff)                       */
30681 /* =========================================================  ENS0  ========================================================== */
30682 #define FPIO_ENS0_ENS0_Pos                (0UL)                     /*!< ENS0 (Bit 0)                                          */
30683 #define FPIO_ENS0_ENS0_Msk                (0xffffffffUL)            /*!< ENS0 (Bitfield-Mask: 0xffffffff)                      */
30684 /* =========================================================  ENS1  ========================================================== */
30685 #define FPIO_ENS1_ENS1_Pos                (0UL)                     /*!< ENS1 (Bit 0)                                          */
30686 #define FPIO_ENS1_ENS1_Msk                (0xffffffffUL)            /*!< ENS1 (Bitfield-Mask: 0xffffffff)                      */
30687 /* =========================================================  ENS2  ========================================================== */
30688 #define FPIO_ENS2_ENS2_Pos                (0UL)                     /*!< ENS2 (Bit 0)                                          */
30689 #define FPIO_ENS2_ENS2_Msk                (0xffffffffUL)            /*!< ENS2 (Bitfield-Mask: 0xffffffff)                      */
30690 /* =========================================================  ENS3  ========================================================== */
30691 #define FPIO_ENS3_ENS3_Pos                (0UL)                     /*!< ENS3 (Bit 0)                                          */
30692 #define FPIO_ENS3_ENS3_Msk                (0xffffffffUL)            /*!< ENS3 (Bitfield-Mask: 0xffffffff)                      */
30693 /* =========================================================  ENC0  ========================================================== */
30694 #define FPIO_ENC0_ENC0_Pos                (0UL)                     /*!< ENC0 (Bit 0)                                          */
30695 #define FPIO_ENC0_ENC0_Msk                (0xffffffffUL)            /*!< ENC0 (Bitfield-Mask: 0xffffffff)                      */
30696 /* =========================================================  ENC1  ========================================================== */
30697 #define FPIO_ENC1_ENC1_Pos                (0UL)                     /*!< ENC1 (Bit 0)                                          */
30698 #define FPIO_ENC1_ENC1_Msk                (0xffffffffUL)            /*!< ENC1 (Bitfield-Mask: 0xffffffff)                      */
30699 /* =========================================================  ENC2  ========================================================== */
30700 #define FPIO_ENC2_ENC2_Pos                (0UL)                     /*!< ENC2 (Bit 0)                                          */
30701 #define FPIO_ENC2_ENC2_Msk                (0xffffffffUL)            /*!< ENC2 (Bitfield-Mask: 0xffffffff)                      */
30702 /* =========================================================  ENC3  ========================================================== */
30703 #define FPIO_ENC3_ENC3_Pos                (0UL)                     /*!< ENC3 (Bit 0)                                          */
30704 #define FPIO_ENC3_ENC3_Msk                (0xffffffffUL)            /*!< ENC3 (Bitfield-Mask: 0xffffffff)                      */
30705 
30706 
30707 /* =========================================================================================================================== */
30708 /* ================                                           GPIO                                            ================ */
30709 /* =========================================================================================================================== */
30710 
30711 /* ========================================================  PINCFG0  ======================================================== */
30712 #define GPIO_PINCFG0_FOEN0_Pos            (27UL)                    /*!< FOEN0 (Bit 27)                                        */
30713 #define GPIO_PINCFG0_FOEN0_Msk            (0x8000000UL)             /*!< FOEN0 (Bitfield-Mask: 0x01)                           */
30714 #define GPIO_PINCFG0_FIEN0_Pos            (26UL)                    /*!< FIEN0 (Bit 26)                                        */
30715 #define GPIO_PINCFG0_FIEN0_Msk            (0x4000000UL)             /*!< FIEN0 (Bitfield-Mask: 0x01)                           */
30716 #define GPIO_PINCFG0_NCEPOL0_Pos          (22UL)                    /*!< NCEPOL0 (Bit 22)                                      */
30717 #define GPIO_PINCFG0_NCEPOL0_Msk          (0x400000UL)              /*!< NCEPOL0 (Bitfield-Mask: 0x01)                         */
30718 #define GPIO_PINCFG0_NCESRC0_Pos          (16UL)                    /*!< NCESRC0 (Bit 16)                                      */
30719 #define GPIO_PINCFG0_NCESRC0_Msk          (0x3f0000UL)              /*!< NCESRC0 (Bitfield-Mask: 0x3f)                         */
30720 #define GPIO_PINCFG0_PULLCFG0_Pos         (13UL)                    /*!< PULLCFG0 (Bit 13)                                     */
30721 #define GPIO_PINCFG0_PULLCFG0_Msk         (0xe000UL)                /*!< PULLCFG0 (Bitfield-Mask: 0x07)                        */
30722 #define GPIO_PINCFG0_SR0_Pos              (12UL)                    /*!< SR0 (Bit 12)                                          */
30723 #define GPIO_PINCFG0_SR0_Msk              (0x1000UL)                /*!< SR0 (Bitfield-Mask: 0x01)                             */
30724 #define GPIO_PINCFG0_DS0_Pos              (10UL)                    /*!< DS0 (Bit 10)                                          */
30725 #define GPIO_PINCFG0_DS0_Msk              (0xc00UL)                 /*!< DS0 (Bitfield-Mask: 0x03)                             */
30726 #define GPIO_PINCFG0_OUTCFG0_Pos          (8UL)                     /*!< OUTCFG0 (Bit 8)                                       */
30727 #define GPIO_PINCFG0_OUTCFG0_Msk          (0x300UL)                 /*!< OUTCFG0 (Bitfield-Mask: 0x03)                         */
30728 #define GPIO_PINCFG0_IRPTEN0_Pos          (6UL)                     /*!< IRPTEN0 (Bit 6)                                       */
30729 #define GPIO_PINCFG0_IRPTEN0_Msk          (0xc0UL)                  /*!< IRPTEN0 (Bitfield-Mask: 0x03)                         */
30730 #define GPIO_PINCFG0_RDZERO0_Pos          (5UL)                     /*!< RDZERO0 (Bit 5)                                       */
30731 #define GPIO_PINCFG0_RDZERO0_Msk          (0x20UL)                  /*!< RDZERO0 (Bitfield-Mask: 0x01)                         */
30732 #define GPIO_PINCFG0_INPEN0_Pos           (4UL)                     /*!< INPEN0 (Bit 4)                                        */
30733 #define GPIO_PINCFG0_INPEN0_Msk           (0x10UL)                  /*!< INPEN0 (Bitfield-Mask: 0x01)                          */
30734 #define GPIO_PINCFG0_FNCSEL0_Pos          (0UL)                     /*!< FNCSEL0 (Bit 0)                                       */
30735 #define GPIO_PINCFG0_FNCSEL0_Msk          (0xfUL)                   /*!< FNCSEL0 (Bitfield-Mask: 0x0f)                         */
30736 /* ========================================================  PINCFG1  ======================================================== */
30737 #define GPIO_PINCFG1_FOEN1_Pos            (27UL)                    /*!< FOEN1 (Bit 27)                                        */
30738 #define GPIO_PINCFG1_FOEN1_Msk            (0x8000000UL)             /*!< FOEN1 (Bitfield-Mask: 0x01)                           */
30739 #define GPIO_PINCFG1_FIEN1_Pos            (26UL)                    /*!< FIEN1 (Bit 26)                                        */
30740 #define GPIO_PINCFG1_FIEN1_Msk            (0x4000000UL)             /*!< FIEN1 (Bitfield-Mask: 0x01)                           */
30741 #define GPIO_PINCFG1_NCEPOL1_Pos          (22UL)                    /*!< NCEPOL1 (Bit 22)                                      */
30742 #define GPIO_PINCFG1_NCEPOL1_Msk          (0x400000UL)              /*!< NCEPOL1 (Bitfield-Mask: 0x01)                         */
30743 #define GPIO_PINCFG1_NCESRC1_Pos          (16UL)                    /*!< NCESRC1 (Bit 16)                                      */
30744 #define GPIO_PINCFG1_NCESRC1_Msk          (0x3f0000UL)              /*!< NCESRC1 (Bitfield-Mask: 0x3f)                         */
30745 #define GPIO_PINCFG1_PULLCFG1_Pos         (13UL)                    /*!< PULLCFG1 (Bit 13)                                     */
30746 #define GPIO_PINCFG1_PULLCFG1_Msk         (0xe000UL)                /*!< PULLCFG1 (Bitfield-Mask: 0x07)                        */
30747 #define GPIO_PINCFG1_SR1_Pos              (12UL)                    /*!< SR1 (Bit 12)                                          */
30748 #define GPIO_PINCFG1_SR1_Msk              (0x1000UL)                /*!< SR1 (Bitfield-Mask: 0x01)                             */
30749 #define GPIO_PINCFG1_DS1_Pos              (10UL)                    /*!< DS1 (Bit 10)                                          */
30750 #define GPIO_PINCFG1_DS1_Msk              (0xc00UL)                 /*!< DS1 (Bitfield-Mask: 0x03)                             */
30751 #define GPIO_PINCFG1_OUTCFG1_Pos          (8UL)                     /*!< OUTCFG1 (Bit 8)                                       */
30752 #define GPIO_PINCFG1_OUTCFG1_Msk          (0x300UL)                 /*!< OUTCFG1 (Bitfield-Mask: 0x03)                         */
30753 #define GPIO_PINCFG1_IRPTEN1_Pos          (6UL)                     /*!< IRPTEN1 (Bit 6)                                       */
30754 #define GPIO_PINCFG1_IRPTEN1_Msk          (0xc0UL)                  /*!< IRPTEN1 (Bitfield-Mask: 0x03)                         */
30755 #define GPIO_PINCFG1_RDZERO1_Pos          (5UL)                     /*!< RDZERO1 (Bit 5)                                       */
30756 #define GPIO_PINCFG1_RDZERO1_Msk          (0x20UL)                  /*!< RDZERO1 (Bitfield-Mask: 0x01)                         */
30757 #define GPIO_PINCFG1_INPEN1_Pos           (4UL)                     /*!< INPEN1 (Bit 4)                                        */
30758 #define GPIO_PINCFG1_INPEN1_Msk           (0x10UL)                  /*!< INPEN1 (Bitfield-Mask: 0x01)                          */
30759 #define GPIO_PINCFG1_FNCSEL1_Pos          (0UL)                     /*!< FNCSEL1 (Bit 0)                                       */
30760 #define GPIO_PINCFG1_FNCSEL1_Msk          (0xfUL)                   /*!< FNCSEL1 (Bitfield-Mask: 0x0f)                         */
30761 /* ========================================================  PINCFG2  ======================================================== */
30762 #define GPIO_PINCFG2_FOEN2_Pos            (27UL)                    /*!< FOEN2 (Bit 27)                                        */
30763 #define GPIO_PINCFG2_FOEN2_Msk            (0x8000000UL)             /*!< FOEN2 (Bitfield-Mask: 0x01)                           */
30764 #define GPIO_PINCFG2_FIEN2_Pos            (26UL)                    /*!< FIEN2 (Bit 26)                                        */
30765 #define GPIO_PINCFG2_FIEN2_Msk            (0x4000000UL)             /*!< FIEN2 (Bitfield-Mask: 0x01)                           */
30766 #define GPIO_PINCFG2_NCEPOL2_Pos          (22UL)                    /*!< NCEPOL2 (Bit 22)                                      */
30767 #define GPIO_PINCFG2_NCEPOL2_Msk          (0x400000UL)              /*!< NCEPOL2 (Bitfield-Mask: 0x01)                         */
30768 #define GPIO_PINCFG2_NCESRC2_Pos          (16UL)                    /*!< NCESRC2 (Bit 16)                                      */
30769 #define GPIO_PINCFG2_NCESRC2_Msk          (0x3f0000UL)              /*!< NCESRC2 (Bitfield-Mask: 0x3f)                         */
30770 #define GPIO_PINCFG2_PULLCFG2_Pos         (13UL)                    /*!< PULLCFG2 (Bit 13)                                     */
30771 #define GPIO_PINCFG2_PULLCFG2_Msk         (0xe000UL)                /*!< PULLCFG2 (Bitfield-Mask: 0x07)                        */
30772 #define GPIO_PINCFG2_SR2_Pos              (12UL)                    /*!< SR2 (Bit 12)                                          */
30773 #define GPIO_PINCFG2_SR2_Msk              (0x1000UL)                /*!< SR2 (Bitfield-Mask: 0x01)                             */
30774 #define GPIO_PINCFG2_DS2_Pos              (10UL)                    /*!< DS2 (Bit 10)                                          */
30775 #define GPIO_PINCFG2_DS2_Msk              (0xc00UL)                 /*!< DS2 (Bitfield-Mask: 0x03)                             */
30776 #define GPIO_PINCFG2_OUTCFG2_Pos          (8UL)                     /*!< OUTCFG2 (Bit 8)                                       */
30777 #define GPIO_PINCFG2_OUTCFG2_Msk          (0x300UL)                 /*!< OUTCFG2 (Bitfield-Mask: 0x03)                         */
30778 #define GPIO_PINCFG2_IRPTEN2_Pos          (6UL)                     /*!< IRPTEN2 (Bit 6)                                       */
30779 #define GPIO_PINCFG2_IRPTEN2_Msk          (0xc0UL)                  /*!< IRPTEN2 (Bitfield-Mask: 0x03)                         */
30780 #define GPIO_PINCFG2_RDZERO2_Pos          (5UL)                     /*!< RDZERO2 (Bit 5)                                       */
30781 #define GPIO_PINCFG2_RDZERO2_Msk          (0x20UL)                  /*!< RDZERO2 (Bitfield-Mask: 0x01)                         */
30782 #define GPIO_PINCFG2_INPEN2_Pos           (4UL)                     /*!< INPEN2 (Bit 4)                                        */
30783 #define GPIO_PINCFG2_INPEN2_Msk           (0x10UL)                  /*!< INPEN2 (Bitfield-Mask: 0x01)                          */
30784 #define GPIO_PINCFG2_FNCSEL2_Pos          (0UL)                     /*!< FNCSEL2 (Bit 0)                                       */
30785 #define GPIO_PINCFG2_FNCSEL2_Msk          (0xfUL)                   /*!< FNCSEL2 (Bitfield-Mask: 0x0f)                         */
30786 /* ========================================================  PINCFG3  ======================================================== */
30787 #define GPIO_PINCFG3_FOEN3_Pos            (27UL)                    /*!< FOEN3 (Bit 27)                                        */
30788 #define GPIO_PINCFG3_FOEN3_Msk            (0x8000000UL)             /*!< FOEN3 (Bitfield-Mask: 0x01)                           */
30789 #define GPIO_PINCFG3_FIEN3_Pos            (26UL)                    /*!< FIEN3 (Bit 26)                                        */
30790 #define GPIO_PINCFG3_FIEN3_Msk            (0x4000000UL)             /*!< FIEN3 (Bitfield-Mask: 0x01)                           */
30791 #define GPIO_PINCFG3_NCEPOL3_Pos          (22UL)                    /*!< NCEPOL3 (Bit 22)                                      */
30792 #define GPIO_PINCFG3_NCEPOL3_Msk          (0x400000UL)              /*!< NCEPOL3 (Bitfield-Mask: 0x01)                         */
30793 #define GPIO_PINCFG3_NCESRC3_Pos          (16UL)                    /*!< NCESRC3 (Bit 16)                                      */
30794 #define GPIO_PINCFG3_NCESRC3_Msk          (0x3f0000UL)              /*!< NCESRC3 (Bitfield-Mask: 0x3f)                         */
30795 #define GPIO_PINCFG3_PULLCFG3_Pos         (13UL)                    /*!< PULLCFG3 (Bit 13)                                     */
30796 #define GPIO_PINCFG3_PULLCFG3_Msk         (0xe000UL)                /*!< PULLCFG3 (Bitfield-Mask: 0x07)                        */
30797 #define GPIO_PINCFG3_SR3_Pos              (12UL)                    /*!< SR3 (Bit 12)                                          */
30798 #define GPIO_PINCFG3_SR3_Msk              (0x1000UL)                /*!< SR3 (Bitfield-Mask: 0x01)                             */
30799 #define GPIO_PINCFG3_DS3_Pos              (10UL)                    /*!< DS3 (Bit 10)                                          */
30800 #define GPIO_PINCFG3_DS3_Msk              (0xc00UL)                 /*!< DS3 (Bitfield-Mask: 0x03)                             */
30801 #define GPIO_PINCFG3_OUTCFG3_Pos          (8UL)                     /*!< OUTCFG3 (Bit 8)                                       */
30802 #define GPIO_PINCFG3_OUTCFG3_Msk          (0x300UL)                 /*!< OUTCFG3 (Bitfield-Mask: 0x03)                         */
30803 #define GPIO_PINCFG3_IRPTEN3_Pos          (6UL)                     /*!< IRPTEN3 (Bit 6)                                       */
30804 #define GPIO_PINCFG3_IRPTEN3_Msk          (0xc0UL)                  /*!< IRPTEN3 (Bitfield-Mask: 0x03)                         */
30805 #define GPIO_PINCFG3_RDZERO3_Pos          (5UL)                     /*!< RDZERO3 (Bit 5)                                       */
30806 #define GPIO_PINCFG3_RDZERO3_Msk          (0x20UL)                  /*!< RDZERO3 (Bitfield-Mask: 0x01)                         */
30807 #define GPIO_PINCFG3_INPEN3_Pos           (4UL)                     /*!< INPEN3 (Bit 4)                                        */
30808 #define GPIO_PINCFG3_INPEN3_Msk           (0x10UL)                  /*!< INPEN3 (Bitfield-Mask: 0x01)                          */
30809 #define GPIO_PINCFG3_FNCSEL3_Pos          (0UL)                     /*!< FNCSEL3 (Bit 0)                                       */
30810 #define GPIO_PINCFG3_FNCSEL3_Msk          (0xfUL)                   /*!< FNCSEL3 (Bitfield-Mask: 0x0f)                         */
30811 /* ========================================================  PINCFG4  ======================================================== */
30812 #define GPIO_PINCFG4_FOEN4_Pos            (27UL)                    /*!< FOEN4 (Bit 27)                                        */
30813 #define GPIO_PINCFG4_FOEN4_Msk            (0x8000000UL)             /*!< FOEN4 (Bitfield-Mask: 0x01)                           */
30814 #define GPIO_PINCFG4_FIEN4_Pos            (26UL)                    /*!< FIEN4 (Bit 26)                                        */
30815 #define GPIO_PINCFG4_FIEN4_Msk            (0x4000000UL)             /*!< FIEN4 (Bitfield-Mask: 0x01)                           */
30816 #define GPIO_PINCFG4_NCEPOL4_Pos          (22UL)                    /*!< NCEPOL4 (Bit 22)                                      */
30817 #define GPIO_PINCFG4_NCEPOL4_Msk          (0x400000UL)              /*!< NCEPOL4 (Bitfield-Mask: 0x01)                         */
30818 #define GPIO_PINCFG4_NCESRC4_Pos          (16UL)                    /*!< NCESRC4 (Bit 16)                                      */
30819 #define GPIO_PINCFG4_NCESRC4_Msk          (0x3f0000UL)              /*!< NCESRC4 (Bitfield-Mask: 0x3f)                         */
30820 #define GPIO_PINCFG4_PULLCFG4_Pos         (13UL)                    /*!< PULLCFG4 (Bit 13)                                     */
30821 #define GPIO_PINCFG4_PULLCFG4_Msk         (0xe000UL)                /*!< PULLCFG4 (Bitfield-Mask: 0x07)                        */
30822 #define GPIO_PINCFG4_SR4_Pos              (12UL)                    /*!< SR4 (Bit 12)                                          */
30823 #define GPIO_PINCFG4_SR4_Msk              (0x1000UL)                /*!< SR4 (Bitfield-Mask: 0x01)                             */
30824 #define GPIO_PINCFG4_DS4_Pos              (10UL)                    /*!< DS4 (Bit 10)                                          */
30825 #define GPIO_PINCFG4_DS4_Msk              (0xc00UL)                 /*!< DS4 (Bitfield-Mask: 0x03)                             */
30826 #define GPIO_PINCFG4_OUTCFG4_Pos          (8UL)                     /*!< OUTCFG4 (Bit 8)                                       */
30827 #define GPIO_PINCFG4_OUTCFG4_Msk          (0x300UL)                 /*!< OUTCFG4 (Bitfield-Mask: 0x03)                         */
30828 #define GPIO_PINCFG4_IRPTEN4_Pos          (6UL)                     /*!< IRPTEN4 (Bit 6)                                       */
30829 #define GPIO_PINCFG4_IRPTEN4_Msk          (0xc0UL)                  /*!< IRPTEN4 (Bitfield-Mask: 0x03)                         */
30830 #define GPIO_PINCFG4_RDZERO4_Pos          (5UL)                     /*!< RDZERO4 (Bit 5)                                       */
30831 #define GPIO_PINCFG4_RDZERO4_Msk          (0x20UL)                  /*!< RDZERO4 (Bitfield-Mask: 0x01)                         */
30832 #define GPIO_PINCFG4_INPEN4_Pos           (4UL)                     /*!< INPEN4 (Bit 4)                                        */
30833 #define GPIO_PINCFG4_INPEN4_Msk           (0x10UL)                  /*!< INPEN4 (Bitfield-Mask: 0x01)                          */
30834 #define GPIO_PINCFG4_FNCSEL4_Pos          (0UL)                     /*!< FNCSEL4 (Bit 0)                                       */
30835 #define GPIO_PINCFG4_FNCSEL4_Msk          (0xfUL)                   /*!< FNCSEL4 (Bitfield-Mask: 0x0f)                         */
30836 /* ========================================================  PINCFG5  ======================================================== */
30837 #define GPIO_PINCFG5_FOEN5_Pos            (27UL)                    /*!< FOEN5 (Bit 27)                                        */
30838 #define GPIO_PINCFG5_FOEN5_Msk            (0x8000000UL)             /*!< FOEN5 (Bitfield-Mask: 0x01)                           */
30839 #define GPIO_PINCFG5_FIEN5_Pos            (26UL)                    /*!< FIEN5 (Bit 26)                                        */
30840 #define GPIO_PINCFG5_FIEN5_Msk            (0x4000000UL)             /*!< FIEN5 (Bitfield-Mask: 0x01)                           */
30841 #define GPIO_PINCFG5_NCEPOL5_Pos          (22UL)                    /*!< NCEPOL5 (Bit 22)                                      */
30842 #define GPIO_PINCFG5_NCEPOL5_Msk          (0x400000UL)              /*!< NCEPOL5 (Bitfield-Mask: 0x01)                         */
30843 #define GPIO_PINCFG5_NCESRC5_Pos          (16UL)                    /*!< NCESRC5 (Bit 16)                                      */
30844 #define GPIO_PINCFG5_NCESRC5_Msk          (0x3f0000UL)              /*!< NCESRC5 (Bitfield-Mask: 0x3f)                         */
30845 #define GPIO_PINCFG5_PULLCFG5_Pos         (13UL)                    /*!< PULLCFG5 (Bit 13)                                     */
30846 #define GPIO_PINCFG5_PULLCFG5_Msk         (0xe000UL)                /*!< PULLCFG5 (Bitfield-Mask: 0x07)                        */
30847 #define GPIO_PINCFG5_SR5_Pos              (12UL)                    /*!< SR5 (Bit 12)                                          */
30848 #define GPIO_PINCFG5_SR5_Msk              (0x1000UL)                /*!< SR5 (Bitfield-Mask: 0x01)                             */
30849 #define GPIO_PINCFG5_DS5_Pos              (10UL)                    /*!< DS5 (Bit 10)                                          */
30850 #define GPIO_PINCFG5_DS5_Msk              (0xc00UL)                 /*!< DS5 (Bitfield-Mask: 0x03)                             */
30851 #define GPIO_PINCFG5_OUTCFG5_Pos          (8UL)                     /*!< OUTCFG5 (Bit 8)                                       */
30852 #define GPIO_PINCFG5_OUTCFG5_Msk          (0x300UL)                 /*!< OUTCFG5 (Bitfield-Mask: 0x03)                         */
30853 #define GPIO_PINCFG5_IRPTEN5_Pos          (6UL)                     /*!< IRPTEN5 (Bit 6)                                       */
30854 #define GPIO_PINCFG5_IRPTEN5_Msk          (0xc0UL)                  /*!< IRPTEN5 (Bitfield-Mask: 0x03)                         */
30855 #define GPIO_PINCFG5_RDZERO5_Pos          (5UL)                     /*!< RDZERO5 (Bit 5)                                       */
30856 #define GPIO_PINCFG5_RDZERO5_Msk          (0x20UL)                  /*!< RDZERO5 (Bitfield-Mask: 0x01)                         */
30857 #define GPIO_PINCFG5_INPEN5_Pos           (4UL)                     /*!< INPEN5 (Bit 4)                                        */
30858 #define GPIO_PINCFG5_INPEN5_Msk           (0x10UL)                  /*!< INPEN5 (Bitfield-Mask: 0x01)                          */
30859 #define GPIO_PINCFG5_FNCSEL5_Pos          (0UL)                     /*!< FNCSEL5 (Bit 0)                                       */
30860 #define GPIO_PINCFG5_FNCSEL5_Msk          (0xfUL)                   /*!< FNCSEL5 (Bitfield-Mask: 0x0f)                         */
30861 /* ========================================================  PINCFG6  ======================================================== */
30862 #define GPIO_PINCFG6_FOEN6_Pos            (27UL)                    /*!< FOEN6 (Bit 27)                                        */
30863 #define GPIO_PINCFG6_FOEN6_Msk            (0x8000000UL)             /*!< FOEN6 (Bitfield-Mask: 0x01)                           */
30864 #define GPIO_PINCFG6_FIEN6_Pos            (26UL)                    /*!< FIEN6 (Bit 26)                                        */
30865 #define GPIO_PINCFG6_FIEN6_Msk            (0x4000000UL)             /*!< FIEN6 (Bitfield-Mask: 0x01)                           */
30866 #define GPIO_PINCFG6_NCEPOL6_Pos          (22UL)                    /*!< NCEPOL6 (Bit 22)                                      */
30867 #define GPIO_PINCFG6_NCEPOL6_Msk          (0x400000UL)              /*!< NCEPOL6 (Bitfield-Mask: 0x01)                         */
30868 #define GPIO_PINCFG6_NCESRC6_Pos          (16UL)                    /*!< NCESRC6 (Bit 16)                                      */
30869 #define GPIO_PINCFG6_NCESRC6_Msk          (0x3f0000UL)              /*!< NCESRC6 (Bitfield-Mask: 0x3f)                         */
30870 #define GPIO_PINCFG6_PULLCFG6_Pos         (13UL)                    /*!< PULLCFG6 (Bit 13)                                     */
30871 #define GPIO_PINCFG6_PULLCFG6_Msk         (0xe000UL)                /*!< PULLCFG6 (Bitfield-Mask: 0x07)                        */
30872 #define GPIO_PINCFG6_SR6_Pos              (12UL)                    /*!< SR6 (Bit 12)                                          */
30873 #define GPIO_PINCFG6_SR6_Msk              (0x1000UL)                /*!< SR6 (Bitfield-Mask: 0x01)                             */
30874 #define GPIO_PINCFG6_DS6_Pos              (10UL)                    /*!< DS6 (Bit 10)                                          */
30875 #define GPIO_PINCFG6_DS6_Msk              (0xc00UL)                 /*!< DS6 (Bitfield-Mask: 0x03)                             */
30876 #define GPIO_PINCFG6_OUTCFG6_Pos          (8UL)                     /*!< OUTCFG6 (Bit 8)                                       */
30877 #define GPIO_PINCFG6_OUTCFG6_Msk          (0x300UL)                 /*!< OUTCFG6 (Bitfield-Mask: 0x03)                         */
30878 #define GPIO_PINCFG6_IRPTEN6_Pos          (6UL)                     /*!< IRPTEN6 (Bit 6)                                       */
30879 #define GPIO_PINCFG6_IRPTEN6_Msk          (0xc0UL)                  /*!< IRPTEN6 (Bitfield-Mask: 0x03)                         */
30880 #define GPIO_PINCFG6_RDZERO6_Pos          (5UL)                     /*!< RDZERO6 (Bit 5)                                       */
30881 #define GPIO_PINCFG6_RDZERO6_Msk          (0x20UL)                  /*!< RDZERO6 (Bitfield-Mask: 0x01)                         */
30882 #define GPIO_PINCFG6_INPEN6_Pos           (4UL)                     /*!< INPEN6 (Bit 4)                                        */
30883 #define GPIO_PINCFG6_INPEN6_Msk           (0x10UL)                  /*!< INPEN6 (Bitfield-Mask: 0x01)                          */
30884 #define GPIO_PINCFG6_FNCSEL6_Pos          (0UL)                     /*!< FNCSEL6 (Bit 0)                                       */
30885 #define GPIO_PINCFG6_FNCSEL6_Msk          (0xfUL)                   /*!< FNCSEL6 (Bitfield-Mask: 0x0f)                         */
30886 /* ========================================================  PINCFG7  ======================================================== */
30887 #define GPIO_PINCFG7_FOEN7_Pos            (27UL)                    /*!< FOEN7 (Bit 27)                                        */
30888 #define GPIO_PINCFG7_FOEN7_Msk            (0x8000000UL)             /*!< FOEN7 (Bitfield-Mask: 0x01)                           */
30889 #define GPIO_PINCFG7_FIEN7_Pos            (26UL)                    /*!< FIEN7 (Bit 26)                                        */
30890 #define GPIO_PINCFG7_FIEN7_Msk            (0x4000000UL)             /*!< FIEN7 (Bitfield-Mask: 0x01)                           */
30891 #define GPIO_PINCFG7_NCEPOL7_Pos          (22UL)                    /*!< NCEPOL7 (Bit 22)                                      */
30892 #define GPIO_PINCFG7_NCEPOL7_Msk          (0x400000UL)              /*!< NCEPOL7 (Bitfield-Mask: 0x01)                         */
30893 #define GPIO_PINCFG7_NCESRC7_Pos          (16UL)                    /*!< NCESRC7 (Bit 16)                                      */
30894 #define GPIO_PINCFG7_NCESRC7_Msk          (0x3f0000UL)              /*!< NCESRC7 (Bitfield-Mask: 0x3f)                         */
30895 #define GPIO_PINCFG7_PULLCFG7_Pos         (13UL)                    /*!< PULLCFG7 (Bit 13)                                     */
30896 #define GPIO_PINCFG7_PULLCFG7_Msk         (0xe000UL)                /*!< PULLCFG7 (Bitfield-Mask: 0x07)                        */
30897 #define GPIO_PINCFG7_SR7_Pos              (12UL)                    /*!< SR7 (Bit 12)                                          */
30898 #define GPIO_PINCFG7_SR7_Msk              (0x1000UL)                /*!< SR7 (Bitfield-Mask: 0x01)                             */
30899 #define GPIO_PINCFG7_DS7_Pos              (10UL)                    /*!< DS7 (Bit 10)                                          */
30900 #define GPIO_PINCFG7_DS7_Msk              (0xc00UL)                 /*!< DS7 (Bitfield-Mask: 0x03)                             */
30901 #define GPIO_PINCFG7_OUTCFG7_Pos          (8UL)                     /*!< OUTCFG7 (Bit 8)                                       */
30902 #define GPIO_PINCFG7_OUTCFG7_Msk          (0x300UL)                 /*!< OUTCFG7 (Bitfield-Mask: 0x03)                         */
30903 #define GPIO_PINCFG7_IRPTEN7_Pos          (6UL)                     /*!< IRPTEN7 (Bit 6)                                       */
30904 #define GPIO_PINCFG7_IRPTEN7_Msk          (0xc0UL)                  /*!< IRPTEN7 (Bitfield-Mask: 0x03)                         */
30905 #define GPIO_PINCFG7_RDZERO7_Pos          (5UL)                     /*!< RDZERO7 (Bit 5)                                       */
30906 #define GPIO_PINCFG7_RDZERO7_Msk          (0x20UL)                  /*!< RDZERO7 (Bitfield-Mask: 0x01)                         */
30907 #define GPIO_PINCFG7_INPEN7_Pos           (4UL)                     /*!< INPEN7 (Bit 4)                                        */
30908 #define GPIO_PINCFG7_INPEN7_Msk           (0x10UL)                  /*!< INPEN7 (Bitfield-Mask: 0x01)                          */
30909 #define GPIO_PINCFG7_FNCSEL7_Pos          (0UL)                     /*!< FNCSEL7 (Bit 0)                                       */
30910 #define GPIO_PINCFG7_FNCSEL7_Msk          (0xfUL)                   /*!< FNCSEL7 (Bitfield-Mask: 0x0f)                         */
30911 /* ========================================================  PINCFG8  ======================================================== */
30912 #define GPIO_PINCFG8_FOEN8_Pos            (27UL)                    /*!< FOEN8 (Bit 27)                                        */
30913 #define GPIO_PINCFG8_FOEN8_Msk            (0x8000000UL)             /*!< FOEN8 (Bitfield-Mask: 0x01)                           */
30914 #define GPIO_PINCFG8_FIEN8_Pos            (26UL)                    /*!< FIEN8 (Bit 26)                                        */
30915 #define GPIO_PINCFG8_FIEN8_Msk            (0x4000000UL)             /*!< FIEN8 (Bitfield-Mask: 0x01)                           */
30916 #define GPIO_PINCFG8_NCEPOL8_Pos          (22UL)                    /*!< NCEPOL8 (Bit 22)                                      */
30917 #define GPIO_PINCFG8_NCEPOL8_Msk          (0x400000UL)              /*!< NCEPOL8 (Bitfield-Mask: 0x01)                         */
30918 #define GPIO_PINCFG8_NCESRC8_Pos          (16UL)                    /*!< NCESRC8 (Bit 16)                                      */
30919 #define GPIO_PINCFG8_NCESRC8_Msk          (0x3f0000UL)              /*!< NCESRC8 (Bitfield-Mask: 0x3f)                         */
30920 #define GPIO_PINCFG8_PULLCFG8_Pos         (13UL)                    /*!< PULLCFG8 (Bit 13)                                     */
30921 #define GPIO_PINCFG8_PULLCFG8_Msk         (0xe000UL)                /*!< PULLCFG8 (Bitfield-Mask: 0x07)                        */
30922 #define GPIO_PINCFG8_SR8_Pos              (12UL)                    /*!< SR8 (Bit 12)                                          */
30923 #define GPIO_PINCFG8_SR8_Msk              (0x1000UL)                /*!< SR8 (Bitfield-Mask: 0x01)                             */
30924 #define GPIO_PINCFG8_DS8_Pos              (10UL)                    /*!< DS8 (Bit 10)                                          */
30925 #define GPIO_PINCFG8_DS8_Msk              (0xc00UL)                 /*!< DS8 (Bitfield-Mask: 0x03)                             */
30926 #define GPIO_PINCFG8_OUTCFG8_Pos          (8UL)                     /*!< OUTCFG8 (Bit 8)                                       */
30927 #define GPIO_PINCFG8_OUTCFG8_Msk          (0x300UL)                 /*!< OUTCFG8 (Bitfield-Mask: 0x03)                         */
30928 #define GPIO_PINCFG8_IRPTEN8_Pos          (6UL)                     /*!< IRPTEN8 (Bit 6)                                       */
30929 #define GPIO_PINCFG8_IRPTEN8_Msk          (0xc0UL)                  /*!< IRPTEN8 (Bitfield-Mask: 0x03)                         */
30930 #define GPIO_PINCFG8_RDZERO8_Pos          (5UL)                     /*!< RDZERO8 (Bit 5)                                       */
30931 #define GPIO_PINCFG8_RDZERO8_Msk          (0x20UL)                  /*!< RDZERO8 (Bitfield-Mask: 0x01)                         */
30932 #define GPIO_PINCFG8_INPEN8_Pos           (4UL)                     /*!< INPEN8 (Bit 4)                                        */
30933 #define GPIO_PINCFG8_INPEN8_Msk           (0x10UL)                  /*!< INPEN8 (Bitfield-Mask: 0x01)                          */
30934 #define GPIO_PINCFG8_FNCSEL8_Pos          (0UL)                     /*!< FNCSEL8 (Bit 0)                                       */
30935 #define GPIO_PINCFG8_FNCSEL8_Msk          (0xfUL)                   /*!< FNCSEL8 (Bitfield-Mask: 0x0f)                         */
30936 /* ========================================================  PINCFG9  ======================================================== */
30937 #define GPIO_PINCFG9_FOEN9_Pos            (27UL)                    /*!< FOEN9 (Bit 27)                                        */
30938 #define GPIO_PINCFG9_FOEN9_Msk            (0x8000000UL)             /*!< FOEN9 (Bitfield-Mask: 0x01)                           */
30939 #define GPIO_PINCFG9_FIEN9_Pos            (26UL)                    /*!< FIEN9 (Bit 26)                                        */
30940 #define GPIO_PINCFG9_FIEN9_Msk            (0x4000000UL)             /*!< FIEN9 (Bitfield-Mask: 0x01)                           */
30941 #define GPIO_PINCFG9_NCEPOL9_Pos          (22UL)                    /*!< NCEPOL9 (Bit 22)                                      */
30942 #define GPIO_PINCFG9_NCEPOL9_Msk          (0x400000UL)              /*!< NCEPOL9 (Bitfield-Mask: 0x01)                         */
30943 #define GPIO_PINCFG9_NCESRC9_Pos          (16UL)                    /*!< NCESRC9 (Bit 16)                                      */
30944 #define GPIO_PINCFG9_NCESRC9_Msk          (0x3f0000UL)              /*!< NCESRC9 (Bitfield-Mask: 0x3f)                         */
30945 #define GPIO_PINCFG9_PULLCFG9_Pos         (13UL)                    /*!< PULLCFG9 (Bit 13)                                     */
30946 #define GPIO_PINCFG9_PULLCFG9_Msk         (0xe000UL)                /*!< PULLCFG9 (Bitfield-Mask: 0x07)                        */
30947 #define GPIO_PINCFG9_SR9_Pos              (12UL)                    /*!< SR9 (Bit 12)                                          */
30948 #define GPIO_PINCFG9_SR9_Msk              (0x1000UL)                /*!< SR9 (Bitfield-Mask: 0x01)                             */
30949 #define GPIO_PINCFG9_DS9_Pos              (10UL)                    /*!< DS9 (Bit 10)                                          */
30950 #define GPIO_PINCFG9_DS9_Msk              (0xc00UL)                 /*!< DS9 (Bitfield-Mask: 0x03)                             */
30951 #define GPIO_PINCFG9_OUTCFG9_Pos          (8UL)                     /*!< OUTCFG9 (Bit 8)                                       */
30952 #define GPIO_PINCFG9_OUTCFG9_Msk          (0x300UL)                 /*!< OUTCFG9 (Bitfield-Mask: 0x03)                         */
30953 #define GPIO_PINCFG9_IRPTEN9_Pos          (6UL)                     /*!< IRPTEN9 (Bit 6)                                       */
30954 #define GPIO_PINCFG9_IRPTEN9_Msk          (0xc0UL)                  /*!< IRPTEN9 (Bitfield-Mask: 0x03)                         */
30955 #define GPIO_PINCFG9_RDZERO9_Pos          (5UL)                     /*!< RDZERO9 (Bit 5)                                       */
30956 #define GPIO_PINCFG9_RDZERO9_Msk          (0x20UL)                  /*!< RDZERO9 (Bitfield-Mask: 0x01)                         */
30957 #define GPIO_PINCFG9_INPEN9_Pos           (4UL)                     /*!< INPEN9 (Bit 4)                                        */
30958 #define GPIO_PINCFG9_INPEN9_Msk           (0x10UL)                  /*!< INPEN9 (Bitfield-Mask: 0x01)                          */
30959 #define GPIO_PINCFG9_FNCSEL9_Pos          (0UL)                     /*!< FNCSEL9 (Bit 0)                                       */
30960 #define GPIO_PINCFG9_FNCSEL9_Msk          (0xfUL)                   /*!< FNCSEL9 (Bitfield-Mask: 0x0f)                         */
30961 /* =======================================================  PINCFG10  ======================================================== */
30962 #define GPIO_PINCFG10_FOEN10_Pos          (27UL)                    /*!< FOEN10 (Bit 27)                                       */
30963 #define GPIO_PINCFG10_FOEN10_Msk          (0x8000000UL)             /*!< FOEN10 (Bitfield-Mask: 0x01)                          */
30964 #define GPIO_PINCFG10_FIEN10_Pos          (26UL)                    /*!< FIEN10 (Bit 26)                                       */
30965 #define GPIO_PINCFG10_FIEN10_Msk          (0x4000000UL)             /*!< FIEN10 (Bitfield-Mask: 0x01)                          */
30966 #define GPIO_PINCFG10_NCEPOL10_Pos        (22UL)                    /*!< NCEPOL10 (Bit 22)                                     */
30967 #define GPIO_PINCFG10_NCEPOL10_Msk        (0x400000UL)              /*!< NCEPOL10 (Bitfield-Mask: 0x01)                        */
30968 #define GPIO_PINCFG10_NCESRC10_Pos        (16UL)                    /*!< NCESRC10 (Bit 16)                                     */
30969 #define GPIO_PINCFG10_NCESRC10_Msk        (0x3f0000UL)              /*!< NCESRC10 (Bitfield-Mask: 0x3f)                        */
30970 #define GPIO_PINCFG10_PULLCFG10_Pos       (13UL)                    /*!< PULLCFG10 (Bit 13)                                    */
30971 #define GPIO_PINCFG10_PULLCFG10_Msk       (0xe000UL)                /*!< PULLCFG10 (Bitfield-Mask: 0x07)                       */
30972 #define GPIO_PINCFG10_SR10_Pos            (12UL)                    /*!< SR10 (Bit 12)                                         */
30973 #define GPIO_PINCFG10_SR10_Msk            (0x1000UL)                /*!< SR10 (Bitfield-Mask: 0x01)                            */
30974 #define GPIO_PINCFG10_DS10_Pos            (10UL)                    /*!< DS10 (Bit 10)                                         */
30975 #define GPIO_PINCFG10_DS10_Msk            (0xc00UL)                 /*!< DS10 (Bitfield-Mask: 0x03)                            */
30976 #define GPIO_PINCFG10_OUTCFG10_Pos        (8UL)                     /*!< OUTCFG10 (Bit 8)                                      */
30977 #define GPIO_PINCFG10_OUTCFG10_Msk        (0x300UL)                 /*!< OUTCFG10 (Bitfield-Mask: 0x03)                        */
30978 #define GPIO_PINCFG10_IRPTEN10_Pos        (6UL)                     /*!< IRPTEN10 (Bit 6)                                      */
30979 #define GPIO_PINCFG10_IRPTEN10_Msk        (0xc0UL)                  /*!< IRPTEN10 (Bitfield-Mask: 0x03)                        */
30980 #define GPIO_PINCFG10_RDZERO10_Pos        (5UL)                     /*!< RDZERO10 (Bit 5)                                      */
30981 #define GPIO_PINCFG10_RDZERO10_Msk        (0x20UL)                  /*!< RDZERO10 (Bitfield-Mask: 0x01)                        */
30982 #define GPIO_PINCFG10_INPEN10_Pos         (4UL)                     /*!< INPEN10 (Bit 4)                                       */
30983 #define GPIO_PINCFG10_INPEN10_Msk         (0x10UL)                  /*!< INPEN10 (Bitfield-Mask: 0x01)                         */
30984 #define GPIO_PINCFG10_FNCSEL10_Pos        (0UL)                     /*!< FNCSEL10 (Bit 0)                                      */
30985 #define GPIO_PINCFG10_FNCSEL10_Msk        (0xfUL)                   /*!< FNCSEL10 (Bitfield-Mask: 0x0f)                        */
30986 /* =======================================================  PINCFG11  ======================================================== */
30987 #define GPIO_PINCFG11_FOEN11_Pos          (27UL)                    /*!< FOEN11 (Bit 27)                                       */
30988 #define GPIO_PINCFG11_FOEN11_Msk          (0x8000000UL)             /*!< FOEN11 (Bitfield-Mask: 0x01)                          */
30989 #define GPIO_PINCFG11_FIEN11_Pos          (26UL)                    /*!< FIEN11 (Bit 26)                                       */
30990 #define GPIO_PINCFG11_FIEN11_Msk          (0x4000000UL)             /*!< FIEN11 (Bitfield-Mask: 0x01)                          */
30991 #define GPIO_PINCFG11_NCEPOL11_Pos        (22UL)                    /*!< NCEPOL11 (Bit 22)                                     */
30992 #define GPIO_PINCFG11_NCEPOL11_Msk        (0x400000UL)              /*!< NCEPOL11 (Bitfield-Mask: 0x01)                        */
30993 #define GPIO_PINCFG11_NCESRC11_Pos        (16UL)                    /*!< NCESRC11 (Bit 16)                                     */
30994 #define GPIO_PINCFG11_NCESRC11_Msk        (0x3f0000UL)              /*!< NCESRC11 (Bitfield-Mask: 0x3f)                        */
30995 #define GPIO_PINCFG11_PULLCFG11_Pos       (13UL)                    /*!< PULLCFG11 (Bit 13)                                    */
30996 #define GPIO_PINCFG11_PULLCFG11_Msk       (0xe000UL)                /*!< PULLCFG11 (Bitfield-Mask: 0x07)                       */
30997 #define GPIO_PINCFG11_SR11_Pos            (12UL)                    /*!< SR11 (Bit 12)                                         */
30998 #define GPIO_PINCFG11_SR11_Msk            (0x1000UL)                /*!< SR11 (Bitfield-Mask: 0x01)                            */
30999 #define GPIO_PINCFG11_DS11_Pos            (10UL)                    /*!< DS11 (Bit 10)                                         */
31000 #define GPIO_PINCFG11_DS11_Msk            (0xc00UL)                 /*!< DS11 (Bitfield-Mask: 0x03)                            */
31001 #define GPIO_PINCFG11_OUTCFG11_Pos        (8UL)                     /*!< OUTCFG11 (Bit 8)                                      */
31002 #define GPIO_PINCFG11_OUTCFG11_Msk        (0x300UL)                 /*!< OUTCFG11 (Bitfield-Mask: 0x03)                        */
31003 #define GPIO_PINCFG11_IRPTEN11_Pos        (6UL)                     /*!< IRPTEN11 (Bit 6)                                      */
31004 #define GPIO_PINCFG11_IRPTEN11_Msk        (0xc0UL)                  /*!< IRPTEN11 (Bitfield-Mask: 0x03)                        */
31005 #define GPIO_PINCFG11_RDZERO11_Pos        (5UL)                     /*!< RDZERO11 (Bit 5)                                      */
31006 #define GPIO_PINCFG11_RDZERO11_Msk        (0x20UL)                  /*!< RDZERO11 (Bitfield-Mask: 0x01)                        */
31007 #define GPIO_PINCFG11_INPEN11_Pos         (4UL)                     /*!< INPEN11 (Bit 4)                                       */
31008 #define GPIO_PINCFG11_INPEN11_Msk         (0x10UL)                  /*!< INPEN11 (Bitfield-Mask: 0x01)                         */
31009 #define GPIO_PINCFG11_FNCSEL11_Pos        (0UL)                     /*!< FNCSEL11 (Bit 0)                                      */
31010 #define GPIO_PINCFG11_FNCSEL11_Msk        (0xfUL)                   /*!< FNCSEL11 (Bitfield-Mask: 0x0f)                        */
31011 /* =======================================================  PINCFG12  ======================================================== */
31012 #define GPIO_PINCFG12_FOEN12_Pos          (27UL)                    /*!< FOEN12 (Bit 27)                                       */
31013 #define GPIO_PINCFG12_FOEN12_Msk          (0x8000000UL)             /*!< FOEN12 (Bitfield-Mask: 0x01)                          */
31014 #define GPIO_PINCFG12_FIEN12_Pos          (26UL)                    /*!< FIEN12 (Bit 26)                                       */
31015 #define GPIO_PINCFG12_FIEN12_Msk          (0x4000000UL)             /*!< FIEN12 (Bitfield-Mask: 0x01)                          */
31016 #define GPIO_PINCFG12_NCEPOL12_Pos        (22UL)                    /*!< NCEPOL12 (Bit 22)                                     */
31017 #define GPIO_PINCFG12_NCEPOL12_Msk        (0x400000UL)              /*!< NCEPOL12 (Bitfield-Mask: 0x01)                        */
31018 #define GPIO_PINCFG12_NCESRC12_Pos        (16UL)                    /*!< NCESRC12 (Bit 16)                                     */
31019 #define GPIO_PINCFG12_NCESRC12_Msk        (0x3f0000UL)              /*!< NCESRC12 (Bitfield-Mask: 0x3f)                        */
31020 #define GPIO_PINCFG12_PULLCFG12_Pos       (13UL)                    /*!< PULLCFG12 (Bit 13)                                    */
31021 #define GPIO_PINCFG12_PULLCFG12_Msk       (0xe000UL)                /*!< PULLCFG12 (Bitfield-Mask: 0x07)                       */
31022 #define GPIO_PINCFG12_SR12_Pos            (12UL)                    /*!< SR12 (Bit 12)                                         */
31023 #define GPIO_PINCFG12_SR12_Msk            (0x1000UL)                /*!< SR12 (Bitfield-Mask: 0x01)                            */
31024 #define GPIO_PINCFG12_DS12_Pos            (10UL)                    /*!< DS12 (Bit 10)                                         */
31025 #define GPIO_PINCFG12_DS12_Msk            (0xc00UL)                 /*!< DS12 (Bitfield-Mask: 0x03)                            */
31026 #define GPIO_PINCFG12_OUTCFG12_Pos        (8UL)                     /*!< OUTCFG12 (Bit 8)                                      */
31027 #define GPIO_PINCFG12_OUTCFG12_Msk        (0x300UL)                 /*!< OUTCFG12 (Bitfield-Mask: 0x03)                        */
31028 #define GPIO_PINCFG12_IRPTEN12_Pos        (6UL)                     /*!< IRPTEN12 (Bit 6)                                      */
31029 #define GPIO_PINCFG12_IRPTEN12_Msk        (0xc0UL)                  /*!< IRPTEN12 (Bitfield-Mask: 0x03)                        */
31030 #define GPIO_PINCFG12_RDZERO12_Pos        (5UL)                     /*!< RDZERO12 (Bit 5)                                      */
31031 #define GPIO_PINCFG12_RDZERO12_Msk        (0x20UL)                  /*!< RDZERO12 (Bitfield-Mask: 0x01)                        */
31032 #define GPIO_PINCFG12_INPEN12_Pos         (4UL)                     /*!< INPEN12 (Bit 4)                                       */
31033 #define GPIO_PINCFG12_INPEN12_Msk         (0x10UL)                  /*!< INPEN12 (Bitfield-Mask: 0x01)                         */
31034 #define GPIO_PINCFG12_FNCSEL12_Pos        (0UL)                     /*!< FNCSEL12 (Bit 0)                                      */
31035 #define GPIO_PINCFG12_FNCSEL12_Msk        (0xfUL)                   /*!< FNCSEL12 (Bitfield-Mask: 0x0f)                        */
31036 /* =======================================================  PINCFG13  ======================================================== */
31037 #define GPIO_PINCFG13_FOEN13_Pos          (27UL)                    /*!< FOEN13 (Bit 27)                                       */
31038 #define GPIO_PINCFG13_FOEN13_Msk          (0x8000000UL)             /*!< FOEN13 (Bitfield-Mask: 0x01)                          */
31039 #define GPIO_PINCFG13_FIEN13_Pos          (26UL)                    /*!< FIEN13 (Bit 26)                                       */
31040 #define GPIO_PINCFG13_FIEN13_Msk          (0x4000000UL)             /*!< FIEN13 (Bitfield-Mask: 0x01)                          */
31041 #define GPIO_PINCFG13_NCEPOL13_Pos        (22UL)                    /*!< NCEPOL13 (Bit 22)                                     */
31042 #define GPIO_PINCFG13_NCEPOL13_Msk        (0x400000UL)              /*!< NCEPOL13 (Bitfield-Mask: 0x01)                        */
31043 #define GPIO_PINCFG13_NCESRC13_Pos        (16UL)                    /*!< NCESRC13 (Bit 16)                                     */
31044 #define GPIO_PINCFG13_NCESRC13_Msk        (0x3f0000UL)              /*!< NCESRC13 (Bitfield-Mask: 0x3f)                        */
31045 #define GPIO_PINCFG13_PULLCFG13_Pos       (13UL)                    /*!< PULLCFG13 (Bit 13)                                    */
31046 #define GPIO_PINCFG13_PULLCFG13_Msk       (0xe000UL)                /*!< PULLCFG13 (Bitfield-Mask: 0x07)                       */
31047 #define GPIO_PINCFG13_SR13_Pos            (12UL)                    /*!< SR13 (Bit 12)                                         */
31048 #define GPIO_PINCFG13_SR13_Msk            (0x1000UL)                /*!< SR13 (Bitfield-Mask: 0x01)                            */
31049 #define GPIO_PINCFG13_DS13_Pos            (10UL)                    /*!< DS13 (Bit 10)                                         */
31050 #define GPIO_PINCFG13_DS13_Msk            (0xc00UL)                 /*!< DS13 (Bitfield-Mask: 0x03)                            */
31051 #define GPIO_PINCFG13_OUTCFG13_Pos        (8UL)                     /*!< OUTCFG13 (Bit 8)                                      */
31052 #define GPIO_PINCFG13_OUTCFG13_Msk        (0x300UL)                 /*!< OUTCFG13 (Bitfield-Mask: 0x03)                        */
31053 #define GPIO_PINCFG13_IRPTEN13_Pos        (6UL)                     /*!< IRPTEN13 (Bit 6)                                      */
31054 #define GPIO_PINCFG13_IRPTEN13_Msk        (0xc0UL)                  /*!< IRPTEN13 (Bitfield-Mask: 0x03)                        */
31055 #define GPIO_PINCFG13_RDZERO13_Pos        (5UL)                     /*!< RDZERO13 (Bit 5)                                      */
31056 #define GPIO_PINCFG13_RDZERO13_Msk        (0x20UL)                  /*!< RDZERO13 (Bitfield-Mask: 0x01)                        */
31057 #define GPIO_PINCFG13_INPEN13_Pos         (4UL)                     /*!< INPEN13 (Bit 4)                                       */
31058 #define GPIO_PINCFG13_INPEN13_Msk         (0x10UL)                  /*!< INPEN13 (Bitfield-Mask: 0x01)                         */
31059 #define GPIO_PINCFG13_FNCSEL13_Pos        (0UL)                     /*!< FNCSEL13 (Bit 0)                                      */
31060 #define GPIO_PINCFG13_FNCSEL13_Msk        (0xfUL)                   /*!< FNCSEL13 (Bitfield-Mask: 0x0f)                        */
31061 /* =======================================================  PINCFG14  ======================================================== */
31062 #define GPIO_PINCFG14_FOEN14_Pos          (27UL)                    /*!< FOEN14 (Bit 27)                                       */
31063 #define GPIO_PINCFG14_FOEN14_Msk          (0x8000000UL)             /*!< FOEN14 (Bitfield-Mask: 0x01)                          */
31064 #define GPIO_PINCFG14_FIEN14_Pos          (26UL)                    /*!< FIEN14 (Bit 26)                                       */
31065 #define GPIO_PINCFG14_FIEN14_Msk          (0x4000000UL)             /*!< FIEN14 (Bitfield-Mask: 0x01)                          */
31066 #define GPIO_PINCFG14_NCEPOL14_Pos        (22UL)                    /*!< NCEPOL14 (Bit 22)                                     */
31067 #define GPIO_PINCFG14_NCEPOL14_Msk        (0x400000UL)              /*!< NCEPOL14 (Bitfield-Mask: 0x01)                        */
31068 #define GPIO_PINCFG14_NCESRC14_Pos        (16UL)                    /*!< NCESRC14 (Bit 16)                                     */
31069 #define GPIO_PINCFG14_NCESRC14_Msk        (0x3f0000UL)              /*!< NCESRC14 (Bitfield-Mask: 0x3f)                        */
31070 #define GPIO_PINCFG14_PULLCFG14_Pos       (13UL)                    /*!< PULLCFG14 (Bit 13)                                    */
31071 #define GPIO_PINCFG14_PULLCFG14_Msk       (0xe000UL)                /*!< PULLCFG14 (Bitfield-Mask: 0x07)                       */
31072 #define GPIO_PINCFG14_SR14_Pos            (12UL)                    /*!< SR14 (Bit 12)                                         */
31073 #define GPIO_PINCFG14_SR14_Msk            (0x1000UL)                /*!< SR14 (Bitfield-Mask: 0x01)                            */
31074 #define GPIO_PINCFG14_DS14_Pos            (10UL)                    /*!< DS14 (Bit 10)                                         */
31075 #define GPIO_PINCFG14_DS14_Msk            (0xc00UL)                 /*!< DS14 (Bitfield-Mask: 0x03)                            */
31076 #define GPIO_PINCFG14_OUTCFG14_Pos        (8UL)                     /*!< OUTCFG14 (Bit 8)                                      */
31077 #define GPIO_PINCFG14_OUTCFG14_Msk        (0x300UL)                 /*!< OUTCFG14 (Bitfield-Mask: 0x03)                        */
31078 #define GPIO_PINCFG14_IRPTEN14_Pos        (6UL)                     /*!< IRPTEN14 (Bit 6)                                      */
31079 #define GPIO_PINCFG14_IRPTEN14_Msk        (0xc0UL)                  /*!< IRPTEN14 (Bitfield-Mask: 0x03)                        */
31080 #define GPIO_PINCFG14_RDZERO14_Pos        (5UL)                     /*!< RDZERO14 (Bit 5)                                      */
31081 #define GPIO_PINCFG14_RDZERO14_Msk        (0x20UL)                  /*!< RDZERO14 (Bitfield-Mask: 0x01)                        */
31082 #define GPIO_PINCFG14_INPEN14_Pos         (4UL)                     /*!< INPEN14 (Bit 4)                                       */
31083 #define GPIO_PINCFG14_INPEN14_Msk         (0x10UL)                  /*!< INPEN14 (Bitfield-Mask: 0x01)                         */
31084 #define GPIO_PINCFG14_FNCSEL14_Pos        (0UL)                     /*!< FNCSEL14 (Bit 0)                                      */
31085 #define GPIO_PINCFG14_FNCSEL14_Msk        (0xfUL)                   /*!< FNCSEL14 (Bitfield-Mask: 0x0f)                        */
31086 /* =======================================================  PINCFG15  ======================================================== */
31087 #define GPIO_PINCFG15_FOEN15_Pos          (27UL)                    /*!< FOEN15 (Bit 27)                                       */
31088 #define GPIO_PINCFG15_FOEN15_Msk          (0x8000000UL)             /*!< FOEN15 (Bitfield-Mask: 0x01)                          */
31089 #define GPIO_PINCFG15_FIEN15_Pos          (26UL)                    /*!< FIEN15 (Bit 26)                                       */
31090 #define GPIO_PINCFG15_FIEN15_Msk          (0x4000000UL)             /*!< FIEN15 (Bitfield-Mask: 0x01)                          */
31091 #define GPIO_PINCFG15_NCEPOL15_Pos        (22UL)                    /*!< NCEPOL15 (Bit 22)                                     */
31092 #define GPIO_PINCFG15_NCEPOL15_Msk        (0x400000UL)              /*!< NCEPOL15 (Bitfield-Mask: 0x01)                        */
31093 #define GPIO_PINCFG15_NCESRC15_Pos        (16UL)                    /*!< NCESRC15 (Bit 16)                                     */
31094 #define GPIO_PINCFG15_NCESRC15_Msk        (0x3f0000UL)              /*!< NCESRC15 (Bitfield-Mask: 0x3f)                        */
31095 #define GPIO_PINCFG15_PULLCFG15_Pos       (13UL)                    /*!< PULLCFG15 (Bit 13)                                    */
31096 #define GPIO_PINCFG15_PULLCFG15_Msk       (0xe000UL)                /*!< PULLCFG15 (Bitfield-Mask: 0x07)                       */
31097 #define GPIO_PINCFG15_SR15_Pos            (12UL)                    /*!< SR15 (Bit 12)                                         */
31098 #define GPIO_PINCFG15_SR15_Msk            (0x1000UL)                /*!< SR15 (Bitfield-Mask: 0x01)                            */
31099 #define GPIO_PINCFG15_DS15_Pos            (10UL)                    /*!< DS15 (Bit 10)                                         */
31100 #define GPIO_PINCFG15_DS15_Msk            (0xc00UL)                 /*!< DS15 (Bitfield-Mask: 0x03)                            */
31101 #define GPIO_PINCFG15_OUTCFG15_Pos        (8UL)                     /*!< OUTCFG15 (Bit 8)                                      */
31102 #define GPIO_PINCFG15_OUTCFG15_Msk        (0x300UL)                 /*!< OUTCFG15 (Bitfield-Mask: 0x03)                        */
31103 #define GPIO_PINCFG15_IRPTEN15_Pos        (6UL)                     /*!< IRPTEN15 (Bit 6)                                      */
31104 #define GPIO_PINCFG15_IRPTEN15_Msk        (0xc0UL)                  /*!< IRPTEN15 (Bitfield-Mask: 0x03)                        */
31105 #define GPIO_PINCFG15_RDZERO15_Pos        (5UL)                     /*!< RDZERO15 (Bit 5)                                      */
31106 #define GPIO_PINCFG15_RDZERO15_Msk        (0x20UL)                  /*!< RDZERO15 (Bitfield-Mask: 0x01)                        */
31107 #define GPIO_PINCFG15_INPEN15_Pos         (4UL)                     /*!< INPEN15 (Bit 4)                                       */
31108 #define GPIO_PINCFG15_INPEN15_Msk         (0x10UL)                  /*!< INPEN15 (Bitfield-Mask: 0x01)                         */
31109 #define GPIO_PINCFG15_FNCSEL15_Pos        (0UL)                     /*!< FNCSEL15 (Bit 0)                                      */
31110 #define GPIO_PINCFG15_FNCSEL15_Msk        (0xfUL)                   /*!< FNCSEL15 (Bitfield-Mask: 0x0f)                        */
31111 /* =======================================================  PINCFG16  ======================================================== */
31112 #define GPIO_PINCFG16_FOEN16_Pos          (27UL)                    /*!< FOEN16 (Bit 27)                                       */
31113 #define GPIO_PINCFG16_FOEN16_Msk          (0x8000000UL)             /*!< FOEN16 (Bitfield-Mask: 0x01)                          */
31114 #define GPIO_PINCFG16_FIEN16_Pos          (26UL)                    /*!< FIEN16 (Bit 26)                                       */
31115 #define GPIO_PINCFG16_FIEN16_Msk          (0x4000000UL)             /*!< FIEN16 (Bitfield-Mask: 0x01)                          */
31116 #define GPIO_PINCFG16_NCEPOL16_Pos        (22UL)                    /*!< NCEPOL16 (Bit 22)                                     */
31117 #define GPIO_PINCFG16_NCEPOL16_Msk        (0x400000UL)              /*!< NCEPOL16 (Bitfield-Mask: 0x01)                        */
31118 #define GPIO_PINCFG16_NCESRC16_Pos        (16UL)                    /*!< NCESRC16 (Bit 16)                                     */
31119 #define GPIO_PINCFG16_NCESRC16_Msk        (0x3f0000UL)              /*!< NCESRC16 (Bitfield-Mask: 0x3f)                        */
31120 #define GPIO_PINCFG16_PULLCFG16_Pos       (13UL)                    /*!< PULLCFG16 (Bit 13)                                    */
31121 #define GPIO_PINCFG16_PULLCFG16_Msk       (0xe000UL)                /*!< PULLCFG16 (Bitfield-Mask: 0x07)                       */
31122 #define GPIO_PINCFG16_SR16_Pos            (12UL)                    /*!< SR16 (Bit 12)                                         */
31123 #define GPIO_PINCFG16_SR16_Msk            (0x1000UL)                /*!< SR16 (Bitfield-Mask: 0x01)                            */
31124 #define GPIO_PINCFG16_DS16_Pos            (10UL)                    /*!< DS16 (Bit 10)                                         */
31125 #define GPIO_PINCFG16_DS16_Msk            (0xc00UL)                 /*!< DS16 (Bitfield-Mask: 0x03)                            */
31126 #define GPIO_PINCFG16_OUTCFG16_Pos        (8UL)                     /*!< OUTCFG16 (Bit 8)                                      */
31127 #define GPIO_PINCFG16_OUTCFG16_Msk        (0x300UL)                 /*!< OUTCFG16 (Bitfield-Mask: 0x03)                        */
31128 #define GPIO_PINCFG16_IRPTEN16_Pos        (6UL)                     /*!< IRPTEN16 (Bit 6)                                      */
31129 #define GPIO_PINCFG16_IRPTEN16_Msk        (0xc0UL)                  /*!< IRPTEN16 (Bitfield-Mask: 0x03)                        */
31130 #define GPIO_PINCFG16_RDZERO16_Pos        (5UL)                     /*!< RDZERO16 (Bit 5)                                      */
31131 #define GPIO_PINCFG16_RDZERO16_Msk        (0x20UL)                  /*!< RDZERO16 (Bitfield-Mask: 0x01)                        */
31132 #define GPIO_PINCFG16_INPEN16_Pos         (4UL)                     /*!< INPEN16 (Bit 4)                                       */
31133 #define GPIO_PINCFG16_INPEN16_Msk         (0x10UL)                  /*!< INPEN16 (Bitfield-Mask: 0x01)                         */
31134 #define GPIO_PINCFG16_FNCSEL16_Pos        (0UL)                     /*!< FNCSEL16 (Bit 0)                                      */
31135 #define GPIO_PINCFG16_FNCSEL16_Msk        (0xfUL)                   /*!< FNCSEL16 (Bitfield-Mask: 0x0f)                        */
31136 /* =======================================================  PINCFG17  ======================================================== */
31137 #define GPIO_PINCFG17_FOEN17_Pos          (27UL)                    /*!< FOEN17 (Bit 27)                                       */
31138 #define GPIO_PINCFG17_FOEN17_Msk          (0x8000000UL)             /*!< FOEN17 (Bitfield-Mask: 0x01)                          */
31139 #define GPIO_PINCFG17_FIEN17_Pos          (26UL)                    /*!< FIEN17 (Bit 26)                                       */
31140 #define GPIO_PINCFG17_FIEN17_Msk          (0x4000000UL)             /*!< FIEN17 (Bitfield-Mask: 0x01)                          */
31141 #define GPIO_PINCFG17_NCEPOL17_Pos        (22UL)                    /*!< NCEPOL17 (Bit 22)                                     */
31142 #define GPIO_PINCFG17_NCEPOL17_Msk        (0x400000UL)              /*!< NCEPOL17 (Bitfield-Mask: 0x01)                        */
31143 #define GPIO_PINCFG17_NCESRC17_Pos        (16UL)                    /*!< NCESRC17 (Bit 16)                                     */
31144 #define GPIO_PINCFG17_NCESRC17_Msk        (0x3f0000UL)              /*!< NCESRC17 (Bitfield-Mask: 0x3f)                        */
31145 #define GPIO_PINCFG17_PULLCFG17_Pos       (13UL)                    /*!< PULLCFG17 (Bit 13)                                    */
31146 #define GPIO_PINCFG17_PULLCFG17_Msk       (0xe000UL)                /*!< PULLCFG17 (Bitfield-Mask: 0x07)                       */
31147 #define GPIO_PINCFG17_SR17_Pos            (12UL)                    /*!< SR17 (Bit 12)                                         */
31148 #define GPIO_PINCFG17_SR17_Msk            (0x1000UL)                /*!< SR17 (Bitfield-Mask: 0x01)                            */
31149 #define GPIO_PINCFG17_DS17_Pos            (10UL)                    /*!< DS17 (Bit 10)                                         */
31150 #define GPIO_PINCFG17_DS17_Msk            (0xc00UL)                 /*!< DS17 (Bitfield-Mask: 0x03)                            */
31151 #define GPIO_PINCFG17_OUTCFG17_Pos        (8UL)                     /*!< OUTCFG17 (Bit 8)                                      */
31152 #define GPIO_PINCFG17_OUTCFG17_Msk        (0x300UL)                 /*!< OUTCFG17 (Bitfield-Mask: 0x03)                        */
31153 #define GPIO_PINCFG17_IRPTEN17_Pos        (6UL)                     /*!< IRPTEN17 (Bit 6)                                      */
31154 #define GPIO_PINCFG17_IRPTEN17_Msk        (0xc0UL)                  /*!< IRPTEN17 (Bitfield-Mask: 0x03)                        */
31155 #define GPIO_PINCFG17_RDZERO17_Pos        (5UL)                     /*!< RDZERO17 (Bit 5)                                      */
31156 #define GPIO_PINCFG17_RDZERO17_Msk        (0x20UL)                  /*!< RDZERO17 (Bitfield-Mask: 0x01)                        */
31157 #define GPIO_PINCFG17_INPEN17_Pos         (4UL)                     /*!< INPEN17 (Bit 4)                                       */
31158 #define GPIO_PINCFG17_INPEN17_Msk         (0x10UL)                  /*!< INPEN17 (Bitfield-Mask: 0x01)                         */
31159 #define GPIO_PINCFG17_FNCSEL17_Pos        (0UL)                     /*!< FNCSEL17 (Bit 0)                                      */
31160 #define GPIO_PINCFG17_FNCSEL17_Msk        (0xfUL)                   /*!< FNCSEL17 (Bitfield-Mask: 0x0f)                        */
31161 /* =======================================================  PINCFG18  ======================================================== */
31162 #define GPIO_PINCFG18_FOEN18_Pos          (27UL)                    /*!< FOEN18 (Bit 27)                                       */
31163 #define GPIO_PINCFG18_FOEN18_Msk          (0x8000000UL)             /*!< FOEN18 (Bitfield-Mask: 0x01)                          */
31164 #define GPIO_PINCFG18_FIEN18_Pos          (26UL)                    /*!< FIEN18 (Bit 26)                                       */
31165 #define GPIO_PINCFG18_FIEN18_Msk          (0x4000000UL)             /*!< FIEN18 (Bitfield-Mask: 0x01)                          */
31166 #define GPIO_PINCFG18_NCEPOL18_Pos        (22UL)                    /*!< NCEPOL18 (Bit 22)                                     */
31167 #define GPIO_PINCFG18_NCEPOL18_Msk        (0x400000UL)              /*!< NCEPOL18 (Bitfield-Mask: 0x01)                        */
31168 #define GPIO_PINCFG18_NCESRC18_Pos        (16UL)                    /*!< NCESRC18 (Bit 16)                                     */
31169 #define GPIO_PINCFG18_NCESRC18_Msk        (0x3f0000UL)              /*!< NCESRC18 (Bitfield-Mask: 0x3f)                        */
31170 #define GPIO_PINCFG18_PULLCFG18_Pos       (13UL)                    /*!< PULLCFG18 (Bit 13)                                    */
31171 #define GPIO_PINCFG18_PULLCFG18_Msk       (0xe000UL)                /*!< PULLCFG18 (Bitfield-Mask: 0x07)                       */
31172 #define GPIO_PINCFG18_SR18_Pos            (12UL)                    /*!< SR18 (Bit 12)                                         */
31173 #define GPIO_PINCFG18_SR18_Msk            (0x1000UL)                /*!< SR18 (Bitfield-Mask: 0x01)                            */
31174 #define GPIO_PINCFG18_DS18_Pos            (10UL)                    /*!< DS18 (Bit 10)                                         */
31175 #define GPIO_PINCFG18_DS18_Msk            (0xc00UL)                 /*!< DS18 (Bitfield-Mask: 0x03)                            */
31176 #define GPIO_PINCFG18_OUTCFG18_Pos        (8UL)                     /*!< OUTCFG18 (Bit 8)                                      */
31177 #define GPIO_PINCFG18_OUTCFG18_Msk        (0x300UL)                 /*!< OUTCFG18 (Bitfield-Mask: 0x03)                        */
31178 #define GPIO_PINCFG18_IRPTEN18_Pos        (6UL)                     /*!< IRPTEN18 (Bit 6)                                      */
31179 #define GPIO_PINCFG18_IRPTEN18_Msk        (0xc0UL)                  /*!< IRPTEN18 (Bitfield-Mask: 0x03)                        */
31180 #define GPIO_PINCFG18_RDZERO18_Pos        (5UL)                     /*!< RDZERO18 (Bit 5)                                      */
31181 #define GPIO_PINCFG18_RDZERO18_Msk        (0x20UL)                  /*!< RDZERO18 (Bitfield-Mask: 0x01)                        */
31182 #define GPIO_PINCFG18_INPEN18_Pos         (4UL)                     /*!< INPEN18 (Bit 4)                                       */
31183 #define GPIO_PINCFG18_INPEN18_Msk         (0x10UL)                  /*!< INPEN18 (Bitfield-Mask: 0x01)                         */
31184 #define GPIO_PINCFG18_FNCSEL18_Pos        (0UL)                     /*!< FNCSEL18 (Bit 0)                                      */
31185 #define GPIO_PINCFG18_FNCSEL18_Msk        (0xfUL)                   /*!< FNCSEL18 (Bitfield-Mask: 0x0f)                        */
31186 /* =======================================================  PINCFG19  ======================================================== */
31187 #define GPIO_PINCFG19_FOEN19_Pos          (27UL)                    /*!< FOEN19 (Bit 27)                                       */
31188 #define GPIO_PINCFG19_FOEN19_Msk          (0x8000000UL)             /*!< FOEN19 (Bitfield-Mask: 0x01)                          */
31189 #define GPIO_PINCFG19_FIEN19_Pos          (26UL)                    /*!< FIEN19 (Bit 26)                                       */
31190 #define GPIO_PINCFG19_FIEN19_Msk          (0x4000000UL)             /*!< FIEN19 (Bitfield-Mask: 0x01)                          */
31191 #define GPIO_PINCFG19_NCEPOL19_Pos        (22UL)                    /*!< NCEPOL19 (Bit 22)                                     */
31192 #define GPIO_PINCFG19_NCEPOL19_Msk        (0x400000UL)              /*!< NCEPOL19 (Bitfield-Mask: 0x01)                        */
31193 #define GPIO_PINCFG19_NCESRC19_Pos        (16UL)                    /*!< NCESRC19 (Bit 16)                                     */
31194 #define GPIO_PINCFG19_NCESRC19_Msk        (0x3f0000UL)              /*!< NCESRC19 (Bitfield-Mask: 0x3f)                        */
31195 #define GPIO_PINCFG19_PULLCFG19_Pos       (13UL)                    /*!< PULLCFG19 (Bit 13)                                    */
31196 #define GPIO_PINCFG19_PULLCFG19_Msk       (0xe000UL)                /*!< PULLCFG19 (Bitfield-Mask: 0x07)                       */
31197 #define GPIO_PINCFG19_SR19_Pos            (12UL)                    /*!< SR19 (Bit 12)                                         */
31198 #define GPIO_PINCFG19_SR19_Msk            (0x1000UL)                /*!< SR19 (Bitfield-Mask: 0x01)                            */
31199 #define GPIO_PINCFG19_DS19_Pos            (10UL)                    /*!< DS19 (Bit 10)                                         */
31200 #define GPIO_PINCFG19_DS19_Msk            (0xc00UL)                 /*!< DS19 (Bitfield-Mask: 0x03)                            */
31201 #define GPIO_PINCFG19_OUTCFG19_Pos        (8UL)                     /*!< OUTCFG19 (Bit 8)                                      */
31202 #define GPIO_PINCFG19_OUTCFG19_Msk        (0x300UL)                 /*!< OUTCFG19 (Bitfield-Mask: 0x03)                        */
31203 #define GPIO_PINCFG19_IRPTEN19_Pos        (6UL)                     /*!< IRPTEN19 (Bit 6)                                      */
31204 #define GPIO_PINCFG19_IRPTEN19_Msk        (0xc0UL)                  /*!< IRPTEN19 (Bitfield-Mask: 0x03)                        */
31205 #define GPIO_PINCFG19_RDZERO19_Pos        (5UL)                     /*!< RDZERO19 (Bit 5)                                      */
31206 #define GPIO_PINCFG19_RDZERO19_Msk        (0x20UL)                  /*!< RDZERO19 (Bitfield-Mask: 0x01)                        */
31207 #define GPIO_PINCFG19_INPEN19_Pos         (4UL)                     /*!< INPEN19 (Bit 4)                                       */
31208 #define GPIO_PINCFG19_INPEN19_Msk         (0x10UL)                  /*!< INPEN19 (Bitfield-Mask: 0x01)                         */
31209 #define GPIO_PINCFG19_FNCSEL19_Pos        (0UL)                     /*!< FNCSEL19 (Bit 0)                                      */
31210 #define GPIO_PINCFG19_FNCSEL19_Msk        (0xfUL)                   /*!< FNCSEL19 (Bitfield-Mask: 0x0f)                        */
31211 /* =======================================================  PINCFG20  ======================================================== */
31212 #define GPIO_PINCFG20_FOEN20_Pos          (27UL)                    /*!< FOEN20 (Bit 27)                                       */
31213 #define GPIO_PINCFG20_FOEN20_Msk          (0x8000000UL)             /*!< FOEN20 (Bitfield-Mask: 0x01)                          */
31214 #define GPIO_PINCFG20_FIEN20_Pos          (26UL)                    /*!< FIEN20 (Bit 26)                                       */
31215 #define GPIO_PINCFG20_FIEN20_Msk          (0x4000000UL)             /*!< FIEN20 (Bitfield-Mask: 0x01)                          */
31216 #define GPIO_PINCFG20_NCEPOL20_Pos        (22UL)                    /*!< NCEPOL20 (Bit 22)                                     */
31217 #define GPIO_PINCFG20_NCEPOL20_Msk        (0x400000UL)              /*!< NCEPOL20 (Bitfield-Mask: 0x01)                        */
31218 #define GPIO_PINCFG20_NCESRC20_Pos        (16UL)                    /*!< NCESRC20 (Bit 16)                                     */
31219 #define GPIO_PINCFG20_NCESRC20_Msk        (0x3f0000UL)              /*!< NCESRC20 (Bitfield-Mask: 0x3f)                        */
31220 #define GPIO_PINCFG20_PULLCFG20_Pos       (13UL)                    /*!< PULLCFG20 (Bit 13)                                    */
31221 #define GPIO_PINCFG20_PULLCFG20_Msk       (0xe000UL)                /*!< PULLCFG20 (Bitfield-Mask: 0x07)                       */
31222 #define GPIO_PINCFG20_SR20_Pos            (12UL)                    /*!< SR20 (Bit 12)                                         */
31223 #define GPIO_PINCFG20_SR20_Msk            (0x1000UL)                /*!< SR20 (Bitfield-Mask: 0x01)                            */
31224 #define GPIO_PINCFG20_DS20_Pos            (10UL)                    /*!< DS20 (Bit 10)                                         */
31225 #define GPIO_PINCFG20_DS20_Msk            (0xc00UL)                 /*!< DS20 (Bitfield-Mask: 0x03)                            */
31226 #define GPIO_PINCFG20_OUTCFG20_Pos        (8UL)                     /*!< OUTCFG20 (Bit 8)                                      */
31227 #define GPIO_PINCFG20_OUTCFG20_Msk        (0x300UL)                 /*!< OUTCFG20 (Bitfield-Mask: 0x03)                        */
31228 #define GPIO_PINCFG20_IRPTEN20_Pos        (6UL)                     /*!< IRPTEN20 (Bit 6)                                      */
31229 #define GPIO_PINCFG20_IRPTEN20_Msk        (0xc0UL)                  /*!< IRPTEN20 (Bitfield-Mask: 0x03)                        */
31230 #define GPIO_PINCFG20_RDZERO20_Pos        (5UL)                     /*!< RDZERO20 (Bit 5)                                      */
31231 #define GPIO_PINCFG20_RDZERO20_Msk        (0x20UL)                  /*!< RDZERO20 (Bitfield-Mask: 0x01)                        */
31232 #define GPIO_PINCFG20_INPEN20_Pos         (4UL)                     /*!< INPEN20 (Bit 4)                                       */
31233 #define GPIO_PINCFG20_INPEN20_Msk         (0x10UL)                  /*!< INPEN20 (Bitfield-Mask: 0x01)                         */
31234 #define GPIO_PINCFG20_FNCSEL20_Pos        (0UL)                     /*!< FNCSEL20 (Bit 0)                                      */
31235 #define GPIO_PINCFG20_FNCSEL20_Msk        (0xfUL)                   /*!< FNCSEL20 (Bitfield-Mask: 0x0f)                        */
31236 /* =======================================================  PINCFG21  ======================================================== */
31237 #define GPIO_PINCFG21_FOEN21_Pos          (27UL)                    /*!< FOEN21 (Bit 27)                                       */
31238 #define GPIO_PINCFG21_FOEN21_Msk          (0x8000000UL)             /*!< FOEN21 (Bitfield-Mask: 0x01)                          */
31239 #define GPIO_PINCFG21_FIEN21_Pos          (26UL)                    /*!< FIEN21 (Bit 26)                                       */
31240 #define GPIO_PINCFG21_FIEN21_Msk          (0x4000000UL)             /*!< FIEN21 (Bitfield-Mask: 0x01)                          */
31241 #define GPIO_PINCFG21_NCEPOL21_Pos        (22UL)                    /*!< NCEPOL21 (Bit 22)                                     */
31242 #define GPIO_PINCFG21_NCEPOL21_Msk        (0x400000UL)              /*!< NCEPOL21 (Bitfield-Mask: 0x01)                        */
31243 #define GPIO_PINCFG21_NCESRC21_Pos        (16UL)                    /*!< NCESRC21 (Bit 16)                                     */
31244 #define GPIO_PINCFG21_NCESRC21_Msk        (0x3f0000UL)              /*!< NCESRC21 (Bitfield-Mask: 0x3f)                        */
31245 #define GPIO_PINCFG21_PULLCFG21_Pos       (13UL)                    /*!< PULLCFG21 (Bit 13)                                    */
31246 #define GPIO_PINCFG21_PULLCFG21_Msk       (0xe000UL)                /*!< PULLCFG21 (Bitfield-Mask: 0x07)                       */
31247 #define GPIO_PINCFG21_SR21_Pos            (12UL)                    /*!< SR21 (Bit 12)                                         */
31248 #define GPIO_PINCFG21_SR21_Msk            (0x1000UL)                /*!< SR21 (Bitfield-Mask: 0x01)                            */
31249 #define GPIO_PINCFG21_DS21_Pos            (10UL)                    /*!< DS21 (Bit 10)                                         */
31250 #define GPIO_PINCFG21_DS21_Msk            (0xc00UL)                 /*!< DS21 (Bitfield-Mask: 0x03)                            */
31251 #define GPIO_PINCFG21_OUTCFG21_Pos        (8UL)                     /*!< OUTCFG21 (Bit 8)                                      */
31252 #define GPIO_PINCFG21_OUTCFG21_Msk        (0x300UL)                 /*!< OUTCFG21 (Bitfield-Mask: 0x03)                        */
31253 #define GPIO_PINCFG21_IRPTEN21_Pos        (6UL)                     /*!< IRPTEN21 (Bit 6)                                      */
31254 #define GPIO_PINCFG21_IRPTEN21_Msk        (0xc0UL)                  /*!< IRPTEN21 (Bitfield-Mask: 0x03)                        */
31255 #define GPIO_PINCFG21_RDZERO21_Pos        (5UL)                     /*!< RDZERO21 (Bit 5)                                      */
31256 #define GPIO_PINCFG21_RDZERO21_Msk        (0x20UL)                  /*!< RDZERO21 (Bitfield-Mask: 0x01)                        */
31257 #define GPIO_PINCFG21_INPEN21_Pos         (4UL)                     /*!< INPEN21 (Bit 4)                                       */
31258 #define GPIO_PINCFG21_INPEN21_Msk         (0x10UL)                  /*!< INPEN21 (Bitfield-Mask: 0x01)                         */
31259 #define GPIO_PINCFG21_FNCSEL21_Pos        (0UL)                     /*!< FNCSEL21 (Bit 0)                                      */
31260 #define GPIO_PINCFG21_FNCSEL21_Msk        (0xfUL)                   /*!< FNCSEL21 (Bitfield-Mask: 0x0f)                        */
31261 /* =======================================================  PINCFG22  ======================================================== */
31262 #define GPIO_PINCFG22_FOEN22_Pos          (27UL)                    /*!< FOEN22 (Bit 27)                                       */
31263 #define GPIO_PINCFG22_FOEN22_Msk          (0x8000000UL)             /*!< FOEN22 (Bitfield-Mask: 0x01)                          */
31264 #define GPIO_PINCFG22_FIEN22_Pos          (26UL)                    /*!< FIEN22 (Bit 26)                                       */
31265 #define GPIO_PINCFG22_FIEN22_Msk          (0x4000000UL)             /*!< FIEN22 (Bitfield-Mask: 0x01)                          */
31266 #define GPIO_PINCFG22_NCEPOL22_Pos        (22UL)                    /*!< NCEPOL22 (Bit 22)                                     */
31267 #define GPIO_PINCFG22_NCEPOL22_Msk        (0x400000UL)              /*!< NCEPOL22 (Bitfield-Mask: 0x01)                        */
31268 #define GPIO_PINCFG22_NCESRC22_Pos        (16UL)                    /*!< NCESRC22 (Bit 16)                                     */
31269 #define GPIO_PINCFG22_NCESRC22_Msk        (0x3f0000UL)              /*!< NCESRC22 (Bitfield-Mask: 0x3f)                        */
31270 #define GPIO_PINCFG22_PULLCFG22_Pos       (13UL)                    /*!< PULLCFG22 (Bit 13)                                    */
31271 #define GPIO_PINCFG22_PULLCFG22_Msk       (0xe000UL)                /*!< PULLCFG22 (Bitfield-Mask: 0x07)                       */
31272 #define GPIO_PINCFG22_SR22_Pos            (12UL)                    /*!< SR22 (Bit 12)                                         */
31273 #define GPIO_PINCFG22_SR22_Msk            (0x1000UL)                /*!< SR22 (Bitfield-Mask: 0x01)                            */
31274 #define GPIO_PINCFG22_DS22_Pos            (10UL)                    /*!< DS22 (Bit 10)                                         */
31275 #define GPIO_PINCFG22_DS22_Msk            (0xc00UL)                 /*!< DS22 (Bitfield-Mask: 0x03)                            */
31276 #define GPIO_PINCFG22_OUTCFG22_Pos        (8UL)                     /*!< OUTCFG22 (Bit 8)                                      */
31277 #define GPIO_PINCFG22_OUTCFG22_Msk        (0x300UL)                 /*!< OUTCFG22 (Bitfield-Mask: 0x03)                        */
31278 #define GPIO_PINCFG22_IRPTEN22_Pos        (6UL)                     /*!< IRPTEN22 (Bit 6)                                      */
31279 #define GPIO_PINCFG22_IRPTEN22_Msk        (0xc0UL)                  /*!< IRPTEN22 (Bitfield-Mask: 0x03)                        */
31280 #define GPIO_PINCFG22_RDZERO22_Pos        (5UL)                     /*!< RDZERO22 (Bit 5)                                      */
31281 #define GPIO_PINCFG22_RDZERO22_Msk        (0x20UL)                  /*!< RDZERO22 (Bitfield-Mask: 0x01)                        */
31282 #define GPIO_PINCFG22_INPEN22_Pos         (4UL)                     /*!< INPEN22 (Bit 4)                                       */
31283 #define GPIO_PINCFG22_INPEN22_Msk         (0x10UL)                  /*!< INPEN22 (Bitfield-Mask: 0x01)                         */
31284 #define GPIO_PINCFG22_FNCSEL22_Pos        (0UL)                     /*!< FNCSEL22 (Bit 0)                                      */
31285 #define GPIO_PINCFG22_FNCSEL22_Msk        (0xfUL)                   /*!< FNCSEL22 (Bitfield-Mask: 0x0f)                        */
31286 /* =======================================================  PINCFG23  ======================================================== */
31287 #define GPIO_PINCFG23_FOEN23_Pos          (27UL)                    /*!< FOEN23 (Bit 27)                                       */
31288 #define GPIO_PINCFG23_FOEN23_Msk          (0x8000000UL)             /*!< FOEN23 (Bitfield-Mask: 0x01)                          */
31289 #define GPIO_PINCFG23_FIEN23_Pos          (26UL)                    /*!< FIEN23 (Bit 26)                                       */
31290 #define GPIO_PINCFG23_FIEN23_Msk          (0x4000000UL)             /*!< FIEN23 (Bitfield-Mask: 0x01)                          */
31291 #define GPIO_PINCFG23_NCEPOL23_Pos        (22UL)                    /*!< NCEPOL23 (Bit 22)                                     */
31292 #define GPIO_PINCFG23_NCEPOL23_Msk        (0x400000UL)              /*!< NCEPOL23 (Bitfield-Mask: 0x01)                        */
31293 #define GPIO_PINCFG23_NCESRC23_Pos        (16UL)                    /*!< NCESRC23 (Bit 16)                                     */
31294 #define GPIO_PINCFG23_NCESRC23_Msk        (0x3f0000UL)              /*!< NCESRC23 (Bitfield-Mask: 0x3f)                        */
31295 #define GPIO_PINCFG23_PULLCFG23_Pos       (13UL)                    /*!< PULLCFG23 (Bit 13)                                    */
31296 #define GPIO_PINCFG23_PULLCFG23_Msk       (0xe000UL)                /*!< PULLCFG23 (Bitfield-Mask: 0x07)                       */
31297 #define GPIO_PINCFG23_SR23_Pos            (12UL)                    /*!< SR23 (Bit 12)                                         */
31298 #define GPIO_PINCFG23_SR23_Msk            (0x1000UL)                /*!< SR23 (Bitfield-Mask: 0x01)                            */
31299 #define GPIO_PINCFG23_DS23_Pos            (10UL)                    /*!< DS23 (Bit 10)                                         */
31300 #define GPIO_PINCFG23_DS23_Msk            (0xc00UL)                 /*!< DS23 (Bitfield-Mask: 0x03)                            */
31301 #define GPIO_PINCFG23_OUTCFG23_Pos        (8UL)                     /*!< OUTCFG23 (Bit 8)                                      */
31302 #define GPIO_PINCFG23_OUTCFG23_Msk        (0x300UL)                 /*!< OUTCFG23 (Bitfield-Mask: 0x03)                        */
31303 #define GPIO_PINCFG23_IRPTEN23_Pos        (6UL)                     /*!< IRPTEN23 (Bit 6)                                      */
31304 #define GPIO_PINCFG23_IRPTEN23_Msk        (0xc0UL)                  /*!< IRPTEN23 (Bitfield-Mask: 0x03)                        */
31305 #define GPIO_PINCFG23_RDZERO23_Pos        (5UL)                     /*!< RDZERO23 (Bit 5)                                      */
31306 #define GPIO_PINCFG23_RDZERO23_Msk        (0x20UL)                  /*!< RDZERO23 (Bitfield-Mask: 0x01)                        */
31307 #define GPIO_PINCFG23_INPEN23_Pos         (4UL)                     /*!< INPEN23 (Bit 4)                                       */
31308 #define GPIO_PINCFG23_INPEN23_Msk         (0x10UL)                  /*!< INPEN23 (Bitfield-Mask: 0x01)                         */
31309 #define GPIO_PINCFG23_FNCSEL23_Pos        (0UL)                     /*!< FNCSEL23 (Bit 0)                                      */
31310 #define GPIO_PINCFG23_FNCSEL23_Msk        (0xfUL)                   /*!< FNCSEL23 (Bitfield-Mask: 0x0f)                        */
31311 /* =======================================================  PINCFG24  ======================================================== */
31312 #define GPIO_PINCFG24_FOEN24_Pos          (27UL)                    /*!< FOEN24 (Bit 27)                                       */
31313 #define GPIO_PINCFG24_FOEN24_Msk          (0x8000000UL)             /*!< FOEN24 (Bitfield-Mask: 0x01)                          */
31314 #define GPIO_PINCFG24_FIEN24_Pos          (26UL)                    /*!< FIEN24 (Bit 26)                                       */
31315 #define GPIO_PINCFG24_FIEN24_Msk          (0x4000000UL)             /*!< FIEN24 (Bitfield-Mask: 0x01)                          */
31316 #define GPIO_PINCFG24_NCEPOL24_Pos        (22UL)                    /*!< NCEPOL24 (Bit 22)                                     */
31317 #define GPIO_PINCFG24_NCEPOL24_Msk        (0x400000UL)              /*!< NCEPOL24 (Bitfield-Mask: 0x01)                        */
31318 #define GPIO_PINCFG24_NCESRC24_Pos        (16UL)                    /*!< NCESRC24 (Bit 16)                                     */
31319 #define GPIO_PINCFG24_NCESRC24_Msk        (0x3f0000UL)              /*!< NCESRC24 (Bitfield-Mask: 0x3f)                        */
31320 #define GPIO_PINCFG24_PULLCFG24_Pos       (13UL)                    /*!< PULLCFG24 (Bit 13)                                    */
31321 #define GPIO_PINCFG24_PULLCFG24_Msk       (0xe000UL)                /*!< PULLCFG24 (Bitfield-Mask: 0x07)                       */
31322 #define GPIO_PINCFG24_SR24_Pos            (12UL)                    /*!< SR24 (Bit 12)                                         */
31323 #define GPIO_PINCFG24_SR24_Msk            (0x1000UL)                /*!< SR24 (Bitfield-Mask: 0x01)                            */
31324 #define GPIO_PINCFG24_DS24_Pos            (10UL)                    /*!< DS24 (Bit 10)                                         */
31325 #define GPIO_PINCFG24_DS24_Msk            (0xc00UL)                 /*!< DS24 (Bitfield-Mask: 0x03)                            */
31326 #define GPIO_PINCFG24_OUTCFG24_Pos        (8UL)                     /*!< OUTCFG24 (Bit 8)                                      */
31327 #define GPIO_PINCFG24_OUTCFG24_Msk        (0x300UL)                 /*!< OUTCFG24 (Bitfield-Mask: 0x03)                        */
31328 #define GPIO_PINCFG24_IRPTEN24_Pos        (6UL)                     /*!< IRPTEN24 (Bit 6)                                      */
31329 #define GPIO_PINCFG24_IRPTEN24_Msk        (0xc0UL)                  /*!< IRPTEN24 (Bitfield-Mask: 0x03)                        */
31330 #define GPIO_PINCFG24_RDZERO24_Pos        (5UL)                     /*!< RDZERO24 (Bit 5)                                      */
31331 #define GPIO_PINCFG24_RDZERO24_Msk        (0x20UL)                  /*!< RDZERO24 (Bitfield-Mask: 0x01)                        */
31332 #define GPIO_PINCFG24_INPEN24_Pos         (4UL)                     /*!< INPEN24 (Bit 4)                                       */
31333 #define GPIO_PINCFG24_INPEN24_Msk         (0x10UL)                  /*!< INPEN24 (Bitfield-Mask: 0x01)                         */
31334 #define GPIO_PINCFG24_FNCSEL24_Pos        (0UL)                     /*!< FNCSEL24 (Bit 0)                                      */
31335 #define GPIO_PINCFG24_FNCSEL24_Msk        (0xfUL)                   /*!< FNCSEL24 (Bitfield-Mask: 0x0f)                        */
31336 /* =======================================================  PINCFG25  ======================================================== */
31337 #define GPIO_PINCFG25_FOEN25_Pos          (27UL)                    /*!< FOEN25 (Bit 27)                                       */
31338 #define GPIO_PINCFG25_FOEN25_Msk          (0x8000000UL)             /*!< FOEN25 (Bitfield-Mask: 0x01)                          */
31339 #define GPIO_PINCFG25_FIEN25_Pos          (26UL)                    /*!< FIEN25 (Bit 26)                                       */
31340 #define GPIO_PINCFG25_FIEN25_Msk          (0x4000000UL)             /*!< FIEN25 (Bitfield-Mask: 0x01)                          */
31341 #define GPIO_PINCFG25_NCEPOL25_Pos        (22UL)                    /*!< NCEPOL25 (Bit 22)                                     */
31342 #define GPIO_PINCFG25_NCEPOL25_Msk        (0x400000UL)              /*!< NCEPOL25 (Bitfield-Mask: 0x01)                        */
31343 #define GPIO_PINCFG25_NCESRC25_Pos        (16UL)                    /*!< NCESRC25 (Bit 16)                                     */
31344 #define GPIO_PINCFG25_NCESRC25_Msk        (0x3f0000UL)              /*!< NCESRC25 (Bitfield-Mask: 0x3f)                        */
31345 #define GPIO_PINCFG25_PULLCFG25_Pos       (13UL)                    /*!< PULLCFG25 (Bit 13)                                    */
31346 #define GPIO_PINCFG25_PULLCFG25_Msk       (0xe000UL)                /*!< PULLCFG25 (Bitfield-Mask: 0x07)                       */
31347 #define GPIO_PINCFG25_SR25_Pos            (12UL)                    /*!< SR25 (Bit 12)                                         */
31348 #define GPIO_PINCFG25_SR25_Msk            (0x1000UL)                /*!< SR25 (Bitfield-Mask: 0x01)                            */
31349 #define GPIO_PINCFG25_DS25_Pos            (10UL)                    /*!< DS25 (Bit 10)                                         */
31350 #define GPIO_PINCFG25_DS25_Msk            (0xc00UL)                 /*!< DS25 (Bitfield-Mask: 0x03)                            */
31351 #define GPIO_PINCFG25_OUTCFG25_Pos        (8UL)                     /*!< OUTCFG25 (Bit 8)                                      */
31352 #define GPIO_PINCFG25_OUTCFG25_Msk        (0x300UL)                 /*!< OUTCFG25 (Bitfield-Mask: 0x03)                        */
31353 #define GPIO_PINCFG25_IRPTEN25_Pos        (6UL)                     /*!< IRPTEN25 (Bit 6)                                      */
31354 #define GPIO_PINCFG25_IRPTEN25_Msk        (0xc0UL)                  /*!< IRPTEN25 (Bitfield-Mask: 0x03)                        */
31355 #define GPIO_PINCFG25_RDZERO25_Pos        (5UL)                     /*!< RDZERO25 (Bit 5)                                      */
31356 #define GPIO_PINCFG25_RDZERO25_Msk        (0x20UL)                  /*!< RDZERO25 (Bitfield-Mask: 0x01)                        */
31357 #define GPIO_PINCFG25_INPEN25_Pos         (4UL)                     /*!< INPEN25 (Bit 4)                                       */
31358 #define GPIO_PINCFG25_INPEN25_Msk         (0x10UL)                  /*!< INPEN25 (Bitfield-Mask: 0x01)                         */
31359 #define GPIO_PINCFG25_FNCSEL25_Pos        (0UL)                     /*!< FNCSEL25 (Bit 0)                                      */
31360 #define GPIO_PINCFG25_FNCSEL25_Msk        (0xfUL)                   /*!< FNCSEL25 (Bitfield-Mask: 0x0f)                        */
31361 /* =======================================================  PINCFG26  ======================================================== */
31362 #define GPIO_PINCFG26_FOEN26_Pos          (27UL)                    /*!< FOEN26 (Bit 27)                                       */
31363 #define GPIO_PINCFG26_FOEN26_Msk          (0x8000000UL)             /*!< FOEN26 (Bitfield-Mask: 0x01)                          */
31364 #define GPIO_PINCFG26_FIEN26_Pos          (26UL)                    /*!< FIEN26 (Bit 26)                                       */
31365 #define GPIO_PINCFG26_FIEN26_Msk          (0x4000000UL)             /*!< FIEN26 (Bitfield-Mask: 0x01)                          */
31366 #define GPIO_PINCFG26_NCEPOL26_Pos        (22UL)                    /*!< NCEPOL26 (Bit 22)                                     */
31367 #define GPIO_PINCFG26_NCEPOL26_Msk        (0x400000UL)              /*!< NCEPOL26 (Bitfield-Mask: 0x01)                        */
31368 #define GPIO_PINCFG26_NCESRC26_Pos        (16UL)                    /*!< NCESRC26 (Bit 16)                                     */
31369 #define GPIO_PINCFG26_NCESRC26_Msk        (0x3f0000UL)              /*!< NCESRC26 (Bitfield-Mask: 0x3f)                        */
31370 #define GPIO_PINCFG26_PULLCFG26_Pos       (13UL)                    /*!< PULLCFG26 (Bit 13)                                    */
31371 #define GPIO_PINCFG26_PULLCFG26_Msk       (0xe000UL)                /*!< PULLCFG26 (Bitfield-Mask: 0x07)                       */
31372 #define GPIO_PINCFG26_SR26_Pos            (12UL)                    /*!< SR26 (Bit 12)                                         */
31373 #define GPIO_PINCFG26_SR26_Msk            (0x1000UL)                /*!< SR26 (Bitfield-Mask: 0x01)                            */
31374 #define GPIO_PINCFG26_DS26_Pos            (10UL)                    /*!< DS26 (Bit 10)                                         */
31375 #define GPIO_PINCFG26_DS26_Msk            (0xc00UL)                 /*!< DS26 (Bitfield-Mask: 0x03)                            */
31376 #define GPIO_PINCFG26_OUTCFG26_Pos        (8UL)                     /*!< OUTCFG26 (Bit 8)                                      */
31377 #define GPIO_PINCFG26_OUTCFG26_Msk        (0x300UL)                 /*!< OUTCFG26 (Bitfield-Mask: 0x03)                        */
31378 #define GPIO_PINCFG26_IRPTEN26_Pos        (6UL)                     /*!< IRPTEN26 (Bit 6)                                      */
31379 #define GPIO_PINCFG26_IRPTEN26_Msk        (0xc0UL)                  /*!< IRPTEN26 (Bitfield-Mask: 0x03)                        */
31380 #define GPIO_PINCFG26_RDZERO26_Pos        (5UL)                     /*!< RDZERO26 (Bit 5)                                      */
31381 #define GPIO_PINCFG26_RDZERO26_Msk        (0x20UL)                  /*!< RDZERO26 (Bitfield-Mask: 0x01)                        */
31382 #define GPIO_PINCFG26_INPEN26_Pos         (4UL)                     /*!< INPEN26 (Bit 4)                                       */
31383 #define GPIO_PINCFG26_INPEN26_Msk         (0x10UL)                  /*!< INPEN26 (Bitfield-Mask: 0x01)                         */
31384 #define GPIO_PINCFG26_FNCSEL26_Pos        (0UL)                     /*!< FNCSEL26 (Bit 0)                                      */
31385 #define GPIO_PINCFG26_FNCSEL26_Msk        (0xfUL)                   /*!< FNCSEL26 (Bitfield-Mask: 0x0f)                        */
31386 /* =======================================================  PINCFG27  ======================================================== */
31387 #define GPIO_PINCFG27_FOEN27_Pos          (27UL)                    /*!< FOEN27 (Bit 27)                                       */
31388 #define GPIO_PINCFG27_FOEN27_Msk          (0x8000000UL)             /*!< FOEN27 (Bitfield-Mask: 0x01)                          */
31389 #define GPIO_PINCFG27_FIEN27_Pos          (26UL)                    /*!< FIEN27 (Bit 26)                                       */
31390 #define GPIO_PINCFG27_FIEN27_Msk          (0x4000000UL)             /*!< FIEN27 (Bitfield-Mask: 0x01)                          */
31391 #define GPIO_PINCFG27_NCEPOL27_Pos        (22UL)                    /*!< NCEPOL27 (Bit 22)                                     */
31392 #define GPIO_PINCFG27_NCEPOL27_Msk        (0x400000UL)              /*!< NCEPOL27 (Bitfield-Mask: 0x01)                        */
31393 #define GPIO_PINCFG27_NCESRC27_Pos        (16UL)                    /*!< NCESRC27 (Bit 16)                                     */
31394 #define GPIO_PINCFG27_NCESRC27_Msk        (0x3f0000UL)              /*!< NCESRC27 (Bitfield-Mask: 0x3f)                        */
31395 #define GPIO_PINCFG27_PULLCFG27_Pos       (13UL)                    /*!< PULLCFG27 (Bit 13)                                    */
31396 #define GPIO_PINCFG27_PULLCFG27_Msk       (0xe000UL)                /*!< PULLCFG27 (Bitfield-Mask: 0x07)                       */
31397 #define GPIO_PINCFG27_SR27_Pos            (12UL)                    /*!< SR27 (Bit 12)                                         */
31398 #define GPIO_PINCFG27_SR27_Msk            (0x1000UL)                /*!< SR27 (Bitfield-Mask: 0x01)                            */
31399 #define GPIO_PINCFG27_DS27_Pos            (10UL)                    /*!< DS27 (Bit 10)                                         */
31400 #define GPIO_PINCFG27_DS27_Msk            (0xc00UL)                 /*!< DS27 (Bitfield-Mask: 0x03)                            */
31401 #define GPIO_PINCFG27_OUTCFG27_Pos        (8UL)                     /*!< OUTCFG27 (Bit 8)                                      */
31402 #define GPIO_PINCFG27_OUTCFG27_Msk        (0x300UL)                 /*!< OUTCFG27 (Bitfield-Mask: 0x03)                        */
31403 #define GPIO_PINCFG27_IRPTEN27_Pos        (6UL)                     /*!< IRPTEN27 (Bit 6)                                      */
31404 #define GPIO_PINCFG27_IRPTEN27_Msk        (0xc0UL)                  /*!< IRPTEN27 (Bitfield-Mask: 0x03)                        */
31405 #define GPIO_PINCFG27_RDZERO27_Pos        (5UL)                     /*!< RDZERO27 (Bit 5)                                      */
31406 #define GPIO_PINCFG27_RDZERO27_Msk        (0x20UL)                  /*!< RDZERO27 (Bitfield-Mask: 0x01)                        */
31407 #define GPIO_PINCFG27_INPEN27_Pos         (4UL)                     /*!< INPEN27 (Bit 4)                                       */
31408 #define GPIO_PINCFG27_INPEN27_Msk         (0x10UL)                  /*!< INPEN27 (Bitfield-Mask: 0x01)                         */
31409 #define GPIO_PINCFG27_FNCSEL27_Pos        (0UL)                     /*!< FNCSEL27 (Bit 0)                                      */
31410 #define GPIO_PINCFG27_FNCSEL27_Msk        (0xfUL)                   /*!< FNCSEL27 (Bitfield-Mask: 0x0f)                        */
31411 /* =======================================================  PINCFG28  ======================================================== */
31412 #define GPIO_PINCFG28_FOEN28_Pos          (27UL)                    /*!< FOEN28 (Bit 27)                                       */
31413 #define GPIO_PINCFG28_FOEN28_Msk          (0x8000000UL)             /*!< FOEN28 (Bitfield-Mask: 0x01)                          */
31414 #define GPIO_PINCFG28_FIEN28_Pos          (26UL)                    /*!< FIEN28 (Bit 26)                                       */
31415 #define GPIO_PINCFG28_FIEN28_Msk          (0x4000000UL)             /*!< FIEN28 (Bitfield-Mask: 0x01)                          */
31416 #define GPIO_PINCFG28_NCEPOL28_Pos        (22UL)                    /*!< NCEPOL28 (Bit 22)                                     */
31417 #define GPIO_PINCFG28_NCEPOL28_Msk        (0x400000UL)              /*!< NCEPOL28 (Bitfield-Mask: 0x01)                        */
31418 #define GPIO_PINCFG28_NCESRC28_Pos        (16UL)                    /*!< NCESRC28 (Bit 16)                                     */
31419 #define GPIO_PINCFG28_NCESRC28_Msk        (0x3f0000UL)              /*!< NCESRC28 (Bitfield-Mask: 0x3f)                        */
31420 #define GPIO_PINCFG28_PULLCFG28_Pos       (13UL)                    /*!< PULLCFG28 (Bit 13)                                    */
31421 #define GPIO_PINCFG28_PULLCFG28_Msk       (0xe000UL)                /*!< PULLCFG28 (Bitfield-Mask: 0x07)                       */
31422 #define GPIO_PINCFG28_SR28_Pos            (12UL)                    /*!< SR28 (Bit 12)                                         */
31423 #define GPIO_PINCFG28_SR28_Msk            (0x1000UL)                /*!< SR28 (Bitfield-Mask: 0x01)                            */
31424 #define GPIO_PINCFG28_DS28_Pos            (10UL)                    /*!< DS28 (Bit 10)                                         */
31425 #define GPIO_PINCFG28_DS28_Msk            (0xc00UL)                 /*!< DS28 (Bitfield-Mask: 0x03)                            */
31426 #define GPIO_PINCFG28_OUTCFG28_Pos        (8UL)                     /*!< OUTCFG28 (Bit 8)                                      */
31427 #define GPIO_PINCFG28_OUTCFG28_Msk        (0x300UL)                 /*!< OUTCFG28 (Bitfield-Mask: 0x03)                        */
31428 #define GPIO_PINCFG28_IRPTEN28_Pos        (6UL)                     /*!< IRPTEN28 (Bit 6)                                      */
31429 #define GPIO_PINCFG28_IRPTEN28_Msk        (0xc0UL)                  /*!< IRPTEN28 (Bitfield-Mask: 0x03)                        */
31430 #define GPIO_PINCFG28_RDZERO28_Pos        (5UL)                     /*!< RDZERO28 (Bit 5)                                      */
31431 #define GPIO_PINCFG28_RDZERO28_Msk        (0x20UL)                  /*!< RDZERO28 (Bitfield-Mask: 0x01)                        */
31432 #define GPIO_PINCFG28_INPEN28_Pos         (4UL)                     /*!< INPEN28 (Bit 4)                                       */
31433 #define GPIO_PINCFG28_INPEN28_Msk         (0x10UL)                  /*!< INPEN28 (Bitfield-Mask: 0x01)                         */
31434 #define GPIO_PINCFG28_FNCSEL28_Pos        (0UL)                     /*!< FNCSEL28 (Bit 0)                                      */
31435 #define GPIO_PINCFG28_FNCSEL28_Msk        (0xfUL)                   /*!< FNCSEL28 (Bitfield-Mask: 0x0f)                        */
31436 /* =======================================================  PINCFG29  ======================================================== */
31437 #define GPIO_PINCFG29_FOEN29_Pos          (27UL)                    /*!< FOEN29 (Bit 27)                                       */
31438 #define GPIO_PINCFG29_FOEN29_Msk          (0x8000000UL)             /*!< FOEN29 (Bitfield-Mask: 0x01)                          */
31439 #define GPIO_PINCFG29_FIEN29_Pos          (26UL)                    /*!< FIEN29 (Bit 26)                                       */
31440 #define GPIO_PINCFG29_FIEN29_Msk          (0x4000000UL)             /*!< FIEN29 (Bitfield-Mask: 0x01)                          */
31441 #define GPIO_PINCFG29_VSSPWRSWEN29_Pos    (25UL)                    /*!< VSSPWRSWEN29 (Bit 25)                                 */
31442 #define GPIO_PINCFG29_VSSPWRSWEN29_Msk    (0x2000000UL)             /*!< VSSPWRSWEN29 (Bitfield-Mask: 0x01)                    */
31443 #define GPIO_PINCFG29_NCEPOL29_Pos        (22UL)                    /*!< NCEPOL29 (Bit 22)                                     */
31444 #define GPIO_PINCFG29_NCEPOL29_Msk        (0x400000UL)              /*!< NCEPOL29 (Bitfield-Mask: 0x01)                        */
31445 #define GPIO_PINCFG29_NCESRC29_Pos        (16UL)                    /*!< NCESRC29 (Bit 16)                                     */
31446 #define GPIO_PINCFG29_NCESRC29_Msk        (0x3f0000UL)              /*!< NCESRC29 (Bitfield-Mask: 0x3f)                        */
31447 #define GPIO_PINCFG29_PULLCFG29_Pos       (13UL)                    /*!< PULLCFG29 (Bit 13)                                    */
31448 #define GPIO_PINCFG29_PULLCFG29_Msk       (0xe000UL)                /*!< PULLCFG29 (Bitfield-Mask: 0x07)                       */
31449 #define GPIO_PINCFG29_SR29_Pos            (12UL)                    /*!< SR29 (Bit 12)                                         */
31450 #define GPIO_PINCFG29_SR29_Msk            (0x1000UL)                /*!< SR29 (Bitfield-Mask: 0x01)                            */
31451 #define GPIO_PINCFG29_DS29_Pos            (10UL)                    /*!< DS29 (Bit 10)                                         */
31452 #define GPIO_PINCFG29_DS29_Msk            (0xc00UL)                 /*!< DS29 (Bitfield-Mask: 0x03)                            */
31453 #define GPIO_PINCFG29_OUTCFG29_Pos        (8UL)                     /*!< OUTCFG29 (Bit 8)                                      */
31454 #define GPIO_PINCFG29_OUTCFG29_Msk        (0x300UL)                 /*!< OUTCFG29 (Bitfield-Mask: 0x03)                        */
31455 #define GPIO_PINCFG29_IRPTEN29_Pos        (6UL)                     /*!< IRPTEN29 (Bit 6)                                      */
31456 #define GPIO_PINCFG29_IRPTEN29_Msk        (0xc0UL)                  /*!< IRPTEN29 (Bitfield-Mask: 0x03)                        */
31457 #define GPIO_PINCFG29_RDZERO29_Pos        (5UL)                     /*!< RDZERO29 (Bit 5)                                      */
31458 #define GPIO_PINCFG29_RDZERO29_Msk        (0x20UL)                  /*!< RDZERO29 (Bitfield-Mask: 0x01)                        */
31459 #define GPIO_PINCFG29_INPEN29_Pos         (4UL)                     /*!< INPEN29 (Bit 4)                                       */
31460 #define GPIO_PINCFG29_INPEN29_Msk         (0x10UL)                  /*!< INPEN29 (Bitfield-Mask: 0x01)                         */
31461 #define GPIO_PINCFG29_FNCSEL29_Pos        (0UL)                     /*!< FNCSEL29 (Bit 0)                                      */
31462 #define GPIO_PINCFG29_FNCSEL29_Msk        (0xfUL)                   /*!< FNCSEL29 (Bitfield-Mask: 0x0f)                        */
31463 /* =======================================================  PINCFG30  ======================================================== */
31464 #define GPIO_PINCFG30_FOEN30_Pos          (27UL)                    /*!< FOEN30 (Bit 27)                                       */
31465 #define GPIO_PINCFG30_FOEN30_Msk          (0x8000000UL)             /*!< FOEN30 (Bitfield-Mask: 0x01)                          */
31466 #define GPIO_PINCFG30_FIEN30_Pos          (26UL)                    /*!< FIEN30 (Bit 26)                                       */
31467 #define GPIO_PINCFG30_FIEN30_Msk          (0x4000000UL)             /*!< FIEN30 (Bitfield-Mask: 0x01)                          */
31468 #define GPIO_PINCFG30_VDDPWRSWEN30_Pos    (25UL)                    /*!< VDDPWRSWEN30 (Bit 25)                                 */
31469 #define GPIO_PINCFG30_VDDPWRSWEN30_Msk    (0x2000000UL)             /*!< VDDPWRSWEN30 (Bitfield-Mask: 0x01)                    */
31470 #define GPIO_PINCFG30_NCEPOL30_Pos        (22UL)                    /*!< NCEPOL30 (Bit 22)                                     */
31471 #define GPIO_PINCFG30_NCEPOL30_Msk        (0x400000UL)              /*!< NCEPOL30 (Bitfield-Mask: 0x01)                        */
31472 #define GPIO_PINCFG30_NCESRC30_Pos        (16UL)                    /*!< NCESRC30 (Bit 16)                                     */
31473 #define GPIO_PINCFG30_NCESRC30_Msk        (0x3f0000UL)              /*!< NCESRC30 (Bitfield-Mask: 0x3f)                        */
31474 #define GPIO_PINCFG30_PULLCFG30_Pos       (13UL)                    /*!< PULLCFG30 (Bit 13)                                    */
31475 #define GPIO_PINCFG30_PULLCFG30_Msk       (0xe000UL)                /*!< PULLCFG30 (Bitfield-Mask: 0x07)                       */
31476 #define GPIO_PINCFG30_SR30_Pos            (12UL)                    /*!< SR30 (Bit 12)                                         */
31477 #define GPIO_PINCFG30_SR30_Msk            (0x1000UL)                /*!< SR30 (Bitfield-Mask: 0x01)                            */
31478 #define GPIO_PINCFG30_DS30_Pos            (10UL)                    /*!< DS30 (Bit 10)                                         */
31479 #define GPIO_PINCFG30_DS30_Msk            (0xc00UL)                 /*!< DS30 (Bitfield-Mask: 0x03)                            */
31480 #define GPIO_PINCFG30_OUTCFG30_Pos        (8UL)                     /*!< OUTCFG30 (Bit 8)                                      */
31481 #define GPIO_PINCFG30_OUTCFG30_Msk        (0x300UL)                 /*!< OUTCFG30 (Bitfield-Mask: 0x03)                        */
31482 #define GPIO_PINCFG30_IRPTEN30_Pos        (6UL)                     /*!< IRPTEN30 (Bit 6)                                      */
31483 #define GPIO_PINCFG30_IRPTEN30_Msk        (0xc0UL)                  /*!< IRPTEN30 (Bitfield-Mask: 0x03)                        */
31484 #define GPIO_PINCFG30_RDZERO30_Pos        (5UL)                     /*!< RDZERO30 (Bit 5)                                      */
31485 #define GPIO_PINCFG30_RDZERO30_Msk        (0x20UL)                  /*!< RDZERO30 (Bitfield-Mask: 0x01)                        */
31486 #define GPIO_PINCFG30_INPEN30_Pos         (4UL)                     /*!< INPEN30 (Bit 4)                                       */
31487 #define GPIO_PINCFG30_INPEN30_Msk         (0x10UL)                  /*!< INPEN30 (Bitfield-Mask: 0x01)                         */
31488 #define GPIO_PINCFG30_FNCSEL30_Pos        (0UL)                     /*!< FNCSEL30 (Bit 0)                                      */
31489 #define GPIO_PINCFG30_FNCSEL30_Msk        (0xfUL)                   /*!< FNCSEL30 (Bitfield-Mask: 0x0f)                        */
31490 /* =======================================================  PINCFG31  ======================================================== */
31491 #define GPIO_PINCFG31_FOEN31_Pos          (27UL)                    /*!< FOEN31 (Bit 27)                                       */
31492 #define GPIO_PINCFG31_FOEN31_Msk          (0x8000000UL)             /*!< FOEN31 (Bitfield-Mask: 0x01)                          */
31493 #define GPIO_PINCFG31_FIEN31_Pos          (26UL)                    /*!< FIEN31 (Bit 26)                                       */
31494 #define GPIO_PINCFG31_FIEN31_Msk          (0x4000000UL)             /*!< FIEN31 (Bitfield-Mask: 0x01)                          */
31495 #define GPIO_PINCFG31_NCEPOL31_Pos        (22UL)                    /*!< NCEPOL31 (Bit 22)                                     */
31496 #define GPIO_PINCFG31_NCEPOL31_Msk        (0x400000UL)              /*!< NCEPOL31 (Bitfield-Mask: 0x01)                        */
31497 #define GPIO_PINCFG31_NCESRC31_Pos        (16UL)                    /*!< NCESRC31 (Bit 16)                                     */
31498 #define GPIO_PINCFG31_NCESRC31_Msk        (0x3f0000UL)              /*!< NCESRC31 (Bitfield-Mask: 0x3f)                        */
31499 #define GPIO_PINCFG31_PULLCFG31_Pos       (13UL)                    /*!< PULLCFG31 (Bit 13)                                    */
31500 #define GPIO_PINCFG31_PULLCFG31_Msk       (0xe000UL)                /*!< PULLCFG31 (Bitfield-Mask: 0x07)                       */
31501 #define GPIO_PINCFG31_SR31_Pos            (12UL)                    /*!< SR31 (Bit 12)                                         */
31502 #define GPIO_PINCFG31_SR31_Msk            (0x1000UL)                /*!< SR31 (Bitfield-Mask: 0x01)                            */
31503 #define GPIO_PINCFG31_DS31_Pos            (10UL)                    /*!< DS31 (Bit 10)                                         */
31504 #define GPIO_PINCFG31_DS31_Msk            (0xc00UL)                 /*!< DS31 (Bitfield-Mask: 0x03)                            */
31505 #define GPIO_PINCFG31_OUTCFG31_Pos        (8UL)                     /*!< OUTCFG31 (Bit 8)                                      */
31506 #define GPIO_PINCFG31_OUTCFG31_Msk        (0x300UL)                 /*!< OUTCFG31 (Bitfield-Mask: 0x03)                        */
31507 #define GPIO_PINCFG31_IRPTEN31_Pos        (6UL)                     /*!< IRPTEN31 (Bit 6)                                      */
31508 #define GPIO_PINCFG31_IRPTEN31_Msk        (0xc0UL)                  /*!< IRPTEN31 (Bitfield-Mask: 0x03)                        */
31509 #define GPIO_PINCFG31_RDZERO31_Pos        (5UL)                     /*!< RDZERO31 (Bit 5)                                      */
31510 #define GPIO_PINCFG31_RDZERO31_Msk        (0x20UL)                  /*!< RDZERO31 (Bitfield-Mask: 0x01)                        */
31511 #define GPIO_PINCFG31_INPEN31_Pos         (4UL)                     /*!< INPEN31 (Bit 4)                                       */
31512 #define GPIO_PINCFG31_INPEN31_Msk         (0x10UL)                  /*!< INPEN31 (Bitfield-Mask: 0x01)                         */
31513 #define GPIO_PINCFG31_FNCSEL31_Pos        (0UL)                     /*!< FNCSEL31 (Bit 0)                                      */
31514 #define GPIO_PINCFG31_FNCSEL31_Msk        (0xfUL)                   /*!< FNCSEL31 (Bitfield-Mask: 0x0f)                        */
31515 /* =======================================================  PINCFG32  ======================================================== */
31516 #define GPIO_PINCFG32_FOEN32_Pos          (27UL)                    /*!< FOEN32 (Bit 27)                                       */
31517 #define GPIO_PINCFG32_FOEN32_Msk          (0x8000000UL)             /*!< FOEN32 (Bitfield-Mask: 0x01)                          */
31518 #define GPIO_PINCFG32_FIEN32_Pos          (26UL)                    /*!< FIEN32 (Bit 26)                                       */
31519 #define GPIO_PINCFG32_FIEN32_Msk          (0x4000000UL)             /*!< FIEN32 (Bitfield-Mask: 0x01)                          */
31520 #define GPIO_PINCFG32_NCEPOL32_Pos        (22UL)                    /*!< NCEPOL32 (Bit 22)                                     */
31521 #define GPIO_PINCFG32_NCEPOL32_Msk        (0x400000UL)              /*!< NCEPOL32 (Bitfield-Mask: 0x01)                        */
31522 #define GPIO_PINCFG32_NCESRC32_Pos        (16UL)                    /*!< NCESRC32 (Bit 16)                                     */
31523 #define GPIO_PINCFG32_NCESRC32_Msk        (0x3f0000UL)              /*!< NCESRC32 (Bitfield-Mask: 0x3f)                        */
31524 #define GPIO_PINCFG32_PULLCFG32_Pos       (13UL)                    /*!< PULLCFG32 (Bit 13)                                    */
31525 #define GPIO_PINCFG32_PULLCFG32_Msk       (0xe000UL)                /*!< PULLCFG32 (Bitfield-Mask: 0x07)                       */
31526 #define GPIO_PINCFG32_SR32_Pos            (12UL)                    /*!< SR32 (Bit 12)                                         */
31527 #define GPIO_PINCFG32_SR32_Msk            (0x1000UL)                /*!< SR32 (Bitfield-Mask: 0x01)                            */
31528 #define GPIO_PINCFG32_DS32_Pos            (10UL)                    /*!< DS32 (Bit 10)                                         */
31529 #define GPIO_PINCFG32_DS32_Msk            (0xc00UL)                 /*!< DS32 (Bitfield-Mask: 0x03)                            */
31530 #define GPIO_PINCFG32_OUTCFG32_Pos        (8UL)                     /*!< OUTCFG32 (Bit 8)                                      */
31531 #define GPIO_PINCFG32_OUTCFG32_Msk        (0x300UL)                 /*!< OUTCFG32 (Bitfield-Mask: 0x03)                        */
31532 #define GPIO_PINCFG32_IRPTEN32_Pos        (6UL)                     /*!< IRPTEN32 (Bit 6)                                      */
31533 #define GPIO_PINCFG32_IRPTEN32_Msk        (0xc0UL)                  /*!< IRPTEN32 (Bitfield-Mask: 0x03)                        */
31534 #define GPIO_PINCFG32_RDZERO32_Pos        (5UL)                     /*!< RDZERO32 (Bit 5)                                      */
31535 #define GPIO_PINCFG32_RDZERO32_Msk        (0x20UL)                  /*!< RDZERO32 (Bitfield-Mask: 0x01)                        */
31536 #define GPIO_PINCFG32_INPEN32_Pos         (4UL)                     /*!< INPEN32 (Bit 4)                                       */
31537 #define GPIO_PINCFG32_INPEN32_Msk         (0x10UL)                  /*!< INPEN32 (Bitfield-Mask: 0x01)                         */
31538 #define GPIO_PINCFG32_FNCSEL32_Pos        (0UL)                     /*!< FNCSEL32 (Bit 0)                                      */
31539 #define GPIO_PINCFG32_FNCSEL32_Msk        (0xfUL)                   /*!< FNCSEL32 (Bitfield-Mask: 0x0f)                        */
31540 /* =======================================================  PINCFG33  ======================================================== */
31541 #define GPIO_PINCFG33_FOEN33_Pos          (27UL)                    /*!< FOEN33 (Bit 27)                                       */
31542 #define GPIO_PINCFG33_FOEN33_Msk          (0x8000000UL)             /*!< FOEN33 (Bitfield-Mask: 0x01)                          */
31543 #define GPIO_PINCFG33_FIEN33_Pos          (26UL)                    /*!< FIEN33 (Bit 26)                                       */
31544 #define GPIO_PINCFG33_FIEN33_Msk          (0x4000000UL)             /*!< FIEN33 (Bitfield-Mask: 0x01)                          */
31545 #define GPIO_PINCFG33_NCEPOL33_Pos        (22UL)                    /*!< NCEPOL33 (Bit 22)                                     */
31546 #define GPIO_PINCFG33_NCEPOL33_Msk        (0x400000UL)              /*!< NCEPOL33 (Bitfield-Mask: 0x01)                        */
31547 #define GPIO_PINCFG33_NCESRC33_Pos        (16UL)                    /*!< NCESRC33 (Bit 16)                                     */
31548 #define GPIO_PINCFG33_NCESRC33_Msk        (0x3f0000UL)              /*!< NCESRC33 (Bitfield-Mask: 0x3f)                        */
31549 #define GPIO_PINCFG33_PULLCFG33_Pos       (13UL)                    /*!< PULLCFG33 (Bit 13)                                    */
31550 #define GPIO_PINCFG33_PULLCFG33_Msk       (0xe000UL)                /*!< PULLCFG33 (Bitfield-Mask: 0x07)                       */
31551 #define GPIO_PINCFG33_SR33_Pos            (12UL)                    /*!< SR33 (Bit 12)                                         */
31552 #define GPIO_PINCFG33_SR33_Msk            (0x1000UL)                /*!< SR33 (Bitfield-Mask: 0x01)                            */
31553 #define GPIO_PINCFG33_DS33_Pos            (10UL)                    /*!< DS33 (Bit 10)                                         */
31554 #define GPIO_PINCFG33_DS33_Msk            (0xc00UL)                 /*!< DS33 (Bitfield-Mask: 0x03)                            */
31555 #define GPIO_PINCFG33_OUTCFG33_Pos        (8UL)                     /*!< OUTCFG33 (Bit 8)                                      */
31556 #define GPIO_PINCFG33_OUTCFG33_Msk        (0x300UL)                 /*!< OUTCFG33 (Bitfield-Mask: 0x03)                        */
31557 #define GPIO_PINCFG33_IRPTEN33_Pos        (6UL)                     /*!< IRPTEN33 (Bit 6)                                      */
31558 #define GPIO_PINCFG33_IRPTEN33_Msk        (0xc0UL)                  /*!< IRPTEN33 (Bitfield-Mask: 0x03)                        */
31559 #define GPIO_PINCFG33_RDZERO33_Pos        (5UL)                     /*!< RDZERO33 (Bit 5)                                      */
31560 #define GPIO_PINCFG33_RDZERO33_Msk        (0x20UL)                  /*!< RDZERO33 (Bitfield-Mask: 0x01)                        */
31561 #define GPIO_PINCFG33_INPEN33_Pos         (4UL)                     /*!< INPEN33 (Bit 4)                                       */
31562 #define GPIO_PINCFG33_INPEN33_Msk         (0x10UL)                  /*!< INPEN33 (Bitfield-Mask: 0x01)                         */
31563 #define GPIO_PINCFG33_FNCSEL33_Pos        (0UL)                     /*!< FNCSEL33 (Bit 0)                                      */
31564 #define GPIO_PINCFG33_FNCSEL33_Msk        (0xfUL)                   /*!< FNCSEL33 (Bitfield-Mask: 0x0f)                        */
31565 /* =======================================================  PINCFG34  ======================================================== */
31566 #define GPIO_PINCFG34_FOEN34_Pos          (27UL)                    /*!< FOEN34 (Bit 27)                                       */
31567 #define GPIO_PINCFG34_FOEN34_Msk          (0x8000000UL)             /*!< FOEN34 (Bitfield-Mask: 0x01)                          */
31568 #define GPIO_PINCFG34_FIEN34_Pos          (26UL)                    /*!< FIEN34 (Bit 26)                                       */
31569 #define GPIO_PINCFG34_FIEN34_Msk          (0x4000000UL)             /*!< FIEN34 (Bitfield-Mask: 0x01)                          */
31570 #define GPIO_PINCFG34_NCEPOL34_Pos        (22UL)                    /*!< NCEPOL34 (Bit 22)                                     */
31571 #define GPIO_PINCFG34_NCEPOL34_Msk        (0x400000UL)              /*!< NCEPOL34 (Bitfield-Mask: 0x01)                        */
31572 #define GPIO_PINCFG34_NCESRC34_Pos        (16UL)                    /*!< NCESRC34 (Bit 16)                                     */
31573 #define GPIO_PINCFG34_NCESRC34_Msk        (0x3f0000UL)              /*!< NCESRC34 (Bitfield-Mask: 0x3f)                        */
31574 #define GPIO_PINCFG34_PULLCFG34_Pos       (13UL)                    /*!< PULLCFG34 (Bit 13)                                    */
31575 #define GPIO_PINCFG34_PULLCFG34_Msk       (0xe000UL)                /*!< PULLCFG34 (Bitfield-Mask: 0x07)                       */
31576 #define GPIO_PINCFG34_SR34_Pos            (12UL)                    /*!< SR34 (Bit 12)                                         */
31577 #define GPIO_PINCFG34_SR34_Msk            (0x1000UL)                /*!< SR34 (Bitfield-Mask: 0x01)                            */
31578 #define GPIO_PINCFG34_DS34_Pos            (10UL)                    /*!< DS34 (Bit 10)                                         */
31579 #define GPIO_PINCFG34_DS34_Msk            (0xc00UL)                 /*!< DS34 (Bitfield-Mask: 0x03)                            */
31580 #define GPIO_PINCFG34_OUTCFG34_Pos        (8UL)                     /*!< OUTCFG34 (Bit 8)                                      */
31581 #define GPIO_PINCFG34_OUTCFG34_Msk        (0x300UL)                 /*!< OUTCFG34 (Bitfield-Mask: 0x03)                        */
31582 #define GPIO_PINCFG34_IRPTEN34_Pos        (6UL)                     /*!< IRPTEN34 (Bit 6)                                      */
31583 #define GPIO_PINCFG34_IRPTEN34_Msk        (0xc0UL)                  /*!< IRPTEN34 (Bitfield-Mask: 0x03)                        */
31584 #define GPIO_PINCFG34_RDZERO34_Pos        (5UL)                     /*!< RDZERO34 (Bit 5)                                      */
31585 #define GPIO_PINCFG34_RDZERO34_Msk        (0x20UL)                  /*!< RDZERO34 (Bitfield-Mask: 0x01)                        */
31586 #define GPIO_PINCFG34_INPEN34_Pos         (4UL)                     /*!< INPEN34 (Bit 4)                                       */
31587 #define GPIO_PINCFG34_INPEN34_Msk         (0x10UL)                  /*!< INPEN34 (Bitfield-Mask: 0x01)                         */
31588 #define GPIO_PINCFG34_FNCSEL34_Pos        (0UL)                     /*!< FNCSEL34 (Bit 0)                                      */
31589 #define GPIO_PINCFG34_FNCSEL34_Msk        (0xfUL)                   /*!< FNCSEL34 (Bitfield-Mask: 0x0f)                        */
31590 /* =======================================================  PINCFG35  ======================================================== */
31591 #define GPIO_PINCFG35_FOEN35_Pos          (27UL)                    /*!< FOEN35 (Bit 27)                                       */
31592 #define GPIO_PINCFG35_FOEN35_Msk          (0x8000000UL)             /*!< FOEN35 (Bitfield-Mask: 0x01)                          */
31593 #define GPIO_PINCFG35_FIEN35_Pos          (26UL)                    /*!< FIEN35 (Bit 26)                                       */
31594 #define GPIO_PINCFG35_FIEN35_Msk          (0x4000000UL)             /*!< FIEN35 (Bitfield-Mask: 0x01)                          */
31595 #define GPIO_PINCFG35_NCEPOL35_Pos        (22UL)                    /*!< NCEPOL35 (Bit 22)                                     */
31596 #define GPIO_PINCFG35_NCEPOL35_Msk        (0x400000UL)              /*!< NCEPOL35 (Bitfield-Mask: 0x01)                        */
31597 #define GPIO_PINCFG35_NCESRC35_Pos        (16UL)                    /*!< NCESRC35 (Bit 16)                                     */
31598 #define GPIO_PINCFG35_NCESRC35_Msk        (0x3f0000UL)              /*!< NCESRC35 (Bitfield-Mask: 0x3f)                        */
31599 #define GPIO_PINCFG35_PULLCFG35_Pos       (13UL)                    /*!< PULLCFG35 (Bit 13)                                    */
31600 #define GPIO_PINCFG35_PULLCFG35_Msk       (0xe000UL)                /*!< PULLCFG35 (Bitfield-Mask: 0x07)                       */
31601 #define GPIO_PINCFG35_SR35_Pos            (12UL)                    /*!< SR35 (Bit 12)                                         */
31602 #define GPIO_PINCFG35_SR35_Msk            (0x1000UL)                /*!< SR35 (Bitfield-Mask: 0x01)                            */
31603 #define GPIO_PINCFG35_DS35_Pos            (10UL)                    /*!< DS35 (Bit 10)                                         */
31604 #define GPIO_PINCFG35_DS35_Msk            (0xc00UL)                 /*!< DS35 (Bitfield-Mask: 0x03)                            */
31605 #define GPIO_PINCFG35_OUTCFG35_Pos        (8UL)                     /*!< OUTCFG35 (Bit 8)                                      */
31606 #define GPIO_PINCFG35_OUTCFG35_Msk        (0x300UL)                 /*!< OUTCFG35 (Bitfield-Mask: 0x03)                        */
31607 #define GPIO_PINCFG35_IRPTEN35_Pos        (6UL)                     /*!< IRPTEN35 (Bit 6)                                      */
31608 #define GPIO_PINCFG35_IRPTEN35_Msk        (0xc0UL)                  /*!< IRPTEN35 (Bitfield-Mask: 0x03)                        */
31609 #define GPIO_PINCFG35_RDZERO35_Pos        (5UL)                     /*!< RDZERO35 (Bit 5)                                      */
31610 #define GPIO_PINCFG35_RDZERO35_Msk        (0x20UL)                  /*!< RDZERO35 (Bitfield-Mask: 0x01)                        */
31611 #define GPIO_PINCFG35_INPEN35_Pos         (4UL)                     /*!< INPEN35 (Bit 4)                                       */
31612 #define GPIO_PINCFG35_INPEN35_Msk         (0x10UL)                  /*!< INPEN35 (Bitfield-Mask: 0x01)                         */
31613 #define GPIO_PINCFG35_FNCSEL35_Pos        (0UL)                     /*!< FNCSEL35 (Bit 0)                                      */
31614 #define GPIO_PINCFG35_FNCSEL35_Msk        (0xfUL)                   /*!< FNCSEL35 (Bitfield-Mask: 0x0f)                        */
31615 /* =======================================================  PINCFG36  ======================================================== */
31616 #define GPIO_PINCFG36_FOEN36_Pos          (27UL)                    /*!< FOEN36 (Bit 27)                                       */
31617 #define GPIO_PINCFG36_FOEN36_Msk          (0x8000000UL)             /*!< FOEN36 (Bitfield-Mask: 0x01)                          */
31618 #define GPIO_PINCFG36_FIEN36_Pos          (26UL)                    /*!< FIEN36 (Bit 26)                                       */
31619 #define GPIO_PINCFG36_FIEN36_Msk          (0x4000000UL)             /*!< FIEN36 (Bitfield-Mask: 0x01)                          */
31620 #define GPIO_PINCFG36_NCEPOL36_Pos        (22UL)                    /*!< NCEPOL36 (Bit 22)                                     */
31621 #define GPIO_PINCFG36_NCEPOL36_Msk        (0x400000UL)              /*!< NCEPOL36 (Bitfield-Mask: 0x01)                        */
31622 #define GPIO_PINCFG36_NCESRC36_Pos        (16UL)                    /*!< NCESRC36 (Bit 16)                                     */
31623 #define GPIO_PINCFG36_NCESRC36_Msk        (0x3f0000UL)              /*!< NCESRC36 (Bitfield-Mask: 0x3f)                        */
31624 #define GPIO_PINCFG36_PULLCFG36_Pos       (13UL)                    /*!< PULLCFG36 (Bit 13)                                    */
31625 #define GPIO_PINCFG36_PULLCFG36_Msk       (0xe000UL)                /*!< PULLCFG36 (Bitfield-Mask: 0x07)                       */
31626 #define GPIO_PINCFG36_SR36_Pos            (12UL)                    /*!< SR36 (Bit 12)                                         */
31627 #define GPIO_PINCFG36_SR36_Msk            (0x1000UL)                /*!< SR36 (Bitfield-Mask: 0x01)                            */
31628 #define GPIO_PINCFG36_DS36_Pos            (10UL)                    /*!< DS36 (Bit 10)                                         */
31629 #define GPIO_PINCFG36_DS36_Msk            (0xc00UL)                 /*!< DS36 (Bitfield-Mask: 0x03)                            */
31630 #define GPIO_PINCFG36_OUTCFG36_Pos        (8UL)                     /*!< OUTCFG36 (Bit 8)                                      */
31631 #define GPIO_PINCFG36_OUTCFG36_Msk        (0x300UL)                 /*!< OUTCFG36 (Bitfield-Mask: 0x03)                        */
31632 #define GPIO_PINCFG36_IRPTEN36_Pos        (6UL)                     /*!< IRPTEN36 (Bit 6)                                      */
31633 #define GPIO_PINCFG36_IRPTEN36_Msk        (0xc0UL)                  /*!< IRPTEN36 (Bitfield-Mask: 0x03)                        */
31634 #define GPIO_PINCFG36_RDZERO36_Pos        (5UL)                     /*!< RDZERO36 (Bit 5)                                      */
31635 #define GPIO_PINCFG36_RDZERO36_Msk        (0x20UL)                  /*!< RDZERO36 (Bitfield-Mask: 0x01)                        */
31636 #define GPIO_PINCFG36_INPEN36_Pos         (4UL)                     /*!< INPEN36 (Bit 4)                                       */
31637 #define GPIO_PINCFG36_INPEN36_Msk         (0x10UL)                  /*!< INPEN36 (Bitfield-Mask: 0x01)                         */
31638 #define GPIO_PINCFG36_FNCSEL36_Pos        (0UL)                     /*!< FNCSEL36 (Bit 0)                                      */
31639 #define GPIO_PINCFG36_FNCSEL36_Msk        (0xfUL)                   /*!< FNCSEL36 (Bitfield-Mask: 0x0f)                        */
31640 /* =======================================================  PINCFG37  ======================================================== */
31641 #define GPIO_PINCFG37_FOEN37_Pos          (27UL)                    /*!< FOEN37 (Bit 27)                                       */
31642 #define GPIO_PINCFG37_FOEN37_Msk          (0x8000000UL)             /*!< FOEN37 (Bitfield-Mask: 0x01)                          */
31643 #define GPIO_PINCFG37_FIEN37_Pos          (26UL)                    /*!< FIEN37 (Bit 26)                                       */
31644 #define GPIO_PINCFG37_FIEN37_Msk          (0x4000000UL)             /*!< FIEN37 (Bitfield-Mask: 0x01)                          */
31645 #define GPIO_PINCFG37_NCEPOL37_Pos        (22UL)                    /*!< NCEPOL37 (Bit 22)                                     */
31646 #define GPIO_PINCFG37_NCEPOL37_Msk        (0x400000UL)              /*!< NCEPOL37 (Bitfield-Mask: 0x01)                        */
31647 #define GPIO_PINCFG37_NCESRC37_Pos        (16UL)                    /*!< NCESRC37 (Bit 16)                                     */
31648 #define GPIO_PINCFG37_NCESRC37_Msk        (0x3f0000UL)              /*!< NCESRC37 (Bitfield-Mask: 0x3f)                        */
31649 #define GPIO_PINCFG37_PULLCFG37_Pos       (13UL)                    /*!< PULLCFG37 (Bit 13)                                    */
31650 #define GPIO_PINCFG37_PULLCFG37_Msk       (0xe000UL)                /*!< PULLCFG37 (Bitfield-Mask: 0x07)                       */
31651 #define GPIO_PINCFG37_SR37_Pos            (12UL)                    /*!< SR37 (Bit 12)                                         */
31652 #define GPIO_PINCFG37_SR37_Msk            (0x1000UL)                /*!< SR37 (Bitfield-Mask: 0x01)                            */
31653 #define GPIO_PINCFG37_DS37_Pos            (10UL)                    /*!< DS37 (Bit 10)                                         */
31654 #define GPIO_PINCFG37_DS37_Msk            (0xc00UL)                 /*!< DS37 (Bitfield-Mask: 0x03)                            */
31655 #define GPIO_PINCFG37_OUTCFG37_Pos        (8UL)                     /*!< OUTCFG37 (Bit 8)                                      */
31656 #define GPIO_PINCFG37_OUTCFG37_Msk        (0x300UL)                 /*!< OUTCFG37 (Bitfield-Mask: 0x03)                        */
31657 #define GPIO_PINCFG37_IRPTEN37_Pos        (6UL)                     /*!< IRPTEN37 (Bit 6)                                      */
31658 #define GPIO_PINCFG37_IRPTEN37_Msk        (0xc0UL)                  /*!< IRPTEN37 (Bitfield-Mask: 0x03)                        */
31659 #define GPIO_PINCFG37_RDZERO37_Pos        (5UL)                     /*!< RDZERO37 (Bit 5)                                      */
31660 #define GPIO_PINCFG37_RDZERO37_Msk        (0x20UL)                  /*!< RDZERO37 (Bitfield-Mask: 0x01)                        */
31661 #define GPIO_PINCFG37_INPEN37_Pos         (4UL)                     /*!< INPEN37 (Bit 4)                                       */
31662 #define GPIO_PINCFG37_INPEN37_Msk         (0x10UL)                  /*!< INPEN37 (Bitfield-Mask: 0x01)                         */
31663 #define GPIO_PINCFG37_FNCSEL37_Pos        (0UL)                     /*!< FNCSEL37 (Bit 0)                                      */
31664 #define GPIO_PINCFG37_FNCSEL37_Msk        (0xfUL)                   /*!< FNCSEL37 (Bitfield-Mask: 0x0f)                        */
31665 /* =======================================================  PINCFG38  ======================================================== */
31666 #define GPIO_PINCFG38_FOEN38_Pos          (27UL)                    /*!< FOEN38 (Bit 27)                                       */
31667 #define GPIO_PINCFG38_FOEN38_Msk          (0x8000000UL)             /*!< FOEN38 (Bitfield-Mask: 0x01)                          */
31668 #define GPIO_PINCFG38_FIEN38_Pos          (26UL)                    /*!< FIEN38 (Bit 26)                                       */
31669 #define GPIO_PINCFG38_FIEN38_Msk          (0x4000000UL)             /*!< FIEN38 (Bitfield-Mask: 0x01)                          */
31670 #define GPIO_PINCFG38_NCEPOL38_Pos        (22UL)                    /*!< NCEPOL38 (Bit 22)                                     */
31671 #define GPIO_PINCFG38_NCEPOL38_Msk        (0x400000UL)              /*!< NCEPOL38 (Bitfield-Mask: 0x01)                        */
31672 #define GPIO_PINCFG38_NCESRC38_Pos        (16UL)                    /*!< NCESRC38 (Bit 16)                                     */
31673 #define GPIO_PINCFG38_NCESRC38_Msk        (0x3f0000UL)              /*!< NCESRC38 (Bitfield-Mask: 0x3f)                        */
31674 #define GPIO_PINCFG38_PULLCFG38_Pos       (13UL)                    /*!< PULLCFG38 (Bit 13)                                    */
31675 #define GPIO_PINCFG38_PULLCFG38_Msk       (0xe000UL)                /*!< PULLCFG38 (Bitfield-Mask: 0x07)                       */
31676 #define GPIO_PINCFG38_SR38_Pos            (12UL)                    /*!< SR38 (Bit 12)                                         */
31677 #define GPIO_PINCFG38_SR38_Msk            (0x1000UL)                /*!< SR38 (Bitfield-Mask: 0x01)                            */
31678 #define GPIO_PINCFG38_DS38_Pos            (10UL)                    /*!< DS38 (Bit 10)                                         */
31679 #define GPIO_PINCFG38_DS38_Msk            (0xc00UL)                 /*!< DS38 (Bitfield-Mask: 0x03)                            */
31680 #define GPIO_PINCFG38_OUTCFG38_Pos        (8UL)                     /*!< OUTCFG38 (Bit 8)                                      */
31681 #define GPIO_PINCFG38_OUTCFG38_Msk        (0x300UL)                 /*!< OUTCFG38 (Bitfield-Mask: 0x03)                        */
31682 #define GPIO_PINCFG38_IRPTEN38_Pos        (6UL)                     /*!< IRPTEN38 (Bit 6)                                      */
31683 #define GPIO_PINCFG38_IRPTEN38_Msk        (0xc0UL)                  /*!< IRPTEN38 (Bitfield-Mask: 0x03)                        */
31684 #define GPIO_PINCFG38_RDZERO38_Pos        (5UL)                     /*!< RDZERO38 (Bit 5)                                      */
31685 #define GPIO_PINCFG38_RDZERO38_Msk        (0x20UL)                  /*!< RDZERO38 (Bitfield-Mask: 0x01)                        */
31686 #define GPIO_PINCFG38_INPEN38_Pos         (4UL)                     /*!< INPEN38 (Bit 4)                                       */
31687 #define GPIO_PINCFG38_INPEN38_Msk         (0x10UL)                  /*!< INPEN38 (Bitfield-Mask: 0x01)                         */
31688 #define GPIO_PINCFG38_FNCSEL38_Pos        (0UL)                     /*!< FNCSEL38 (Bit 0)                                      */
31689 #define GPIO_PINCFG38_FNCSEL38_Msk        (0xfUL)                   /*!< FNCSEL38 (Bitfield-Mask: 0x0f)                        */
31690 /* =======================================================  PINCFG39  ======================================================== */
31691 #define GPIO_PINCFG39_FOEN39_Pos          (27UL)                    /*!< FOEN39 (Bit 27)                                       */
31692 #define GPIO_PINCFG39_FOEN39_Msk          (0x8000000UL)             /*!< FOEN39 (Bitfield-Mask: 0x01)                          */
31693 #define GPIO_PINCFG39_FIEN39_Pos          (26UL)                    /*!< FIEN39 (Bit 26)                                       */
31694 #define GPIO_PINCFG39_FIEN39_Msk          (0x4000000UL)             /*!< FIEN39 (Bitfield-Mask: 0x01)                          */
31695 #define GPIO_PINCFG39_NCEPOL39_Pos        (22UL)                    /*!< NCEPOL39 (Bit 22)                                     */
31696 #define GPIO_PINCFG39_NCEPOL39_Msk        (0x400000UL)              /*!< NCEPOL39 (Bitfield-Mask: 0x01)                        */
31697 #define GPIO_PINCFG39_NCESRC39_Pos        (16UL)                    /*!< NCESRC39 (Bit 16)                                     */
31698 #define GPIO_PINCFG39_NCESRC39_Msk        (0x3f0000UL)              /*!< NCESRC39 (Bitfield-Mask: 0x3f)                        */
31699 #define GPIO_PINCFG39_PULLCFG39_Pos       (13UL)                    /*!< PULLCFG39 (Bit 13)                                    */
31700 #define GPIO_PINCFG39_PULLCFG39_Msk       (0xe000UL)                /*!< PULLCFG39 (Bitfield-Mask: 0x07)                       */
31701 #define GPIO_PINCFG39_SR39_Pos            (12UL)                    /*!< SR39 (Bit 12)                                         */
31702 #define GPIO_PINCFG39_SR39_Msk            (0x1000UL)                /*!< SR39 (Bitfield-Mask: 0x01)                            */
31703 #define GPIO_PINCFG39_DS39_Pos            (10UL)                    /*!< DS39 (Bit 10)                                         */
31704 #define GPIO_PINCFG39_DS39_Msk            (0xc00UL)                 /*!< DS39 (Bitfield-Mask: 0x03)                            */
31705 #define GPIO_PINCFG39_OUTCFG39_Pos        (8UL)                     /*!< OUTCFG39 (Bit 8)                                      */
31706 #define GPIO_PINCFG39_OUTCFG39_Msk        (0x300UL)                 /*!< OUTCFG39 (Bitfield-Mask: 0x03)                        */
31707 #define GPIO_PINCFG39_IRPTEN39_Pos        (6UL)                     /*!< IRPTEN39 (Bit 6)                                      */
31708 #define GPIO_PINCFG39_IRPTEN39_Msk        (0xc0UL)                  /*!< IRPTEN39 (Bitfield-Mask: 0x03)                        */
31709 #define GPIO_PINCFG39_RDZERO39_Pos        (5UL)                     /*!< RDZERO39 (Bit 5)                                      */
31710 #define GPIO_PINCFG39_RDZERO39_Msk        (0x20UL)                  /*!< RDZERO39 (Bitfield-Mask: 0x01)                        */
31711 #define GPIO_PINCFG39_INPEN39_Pos         (4UL)                     /*!< INPEN39 (Bit 4)                                       */
31712 #define GPIO_PINCFG39_INPEN39_Msk         (0x10UL)                  /*!< INPEN39 (Bitfield-Mask: 0x01)                         */
31713 #define GPIO_PINCFG39_FNCSEL39_Pos        (0UL)                     /*!< FNCSEL39 (Bit 0)                                      */
31714 #define GPIO_PINCFG39_FNCSEL39_Msk        (0xfUL)                   /*!< FNCSEL39 (Bitfield-Mask: 0x0f)                        */
31715 /* =======================================================  PINCFG40  ======================================================== */
31716 #define GPIO_PINCFG40_FOEN40_Pos          (27UL)                    /*!< FOEN40 (Bit 27)                                       */
31717 #define GPIO_PINCFG40_FOEN40_Msk          (0x8000000UL)             /*!< FOEN40 (Bitfield-Mask: 0x01)                          */
31718 #define GPIO_PINCFG40_FIEN40_Pos          (26UL)                    /*!< FIEN40 (Bit 26)                                       */
31719 #define GPIO_PINCFG40_FIEN40_Msk          (0x4000000UL)             /*!< FIEN40 (Bitfield-Mask: 0x01)                          */
31720 #define GPIO_PINCFG40_NCEPOL40_Pos        (22UL)                    /*!< NCEPOL40 (Bit 22)                                     */
31721 #define GPIO_PINCFG40_NCEPOL40_Msk        (0x400000UL)              /*!< NCEPOL40 (Bitfield-Mask: 0x01)                        */
31722 #define GPIO_PINCFG40_NCESRC40_Pos        (16UL)                    /*!< NCESRC40 (Bit 16)                                     */
31723 #define GPIO_PINCFG40_NCESRC40_Msk        (0x3f0000UL)              /*!< NCESRC40 (Bitfield-Mask: 0x3f)                        */
31724 #define GPIO_PINCFG40_PULLCFG40_Pos       (13UL)                    /*!< PULLCFG40 (Bit 13)                                    */
31725 #define GPIO_PINCFG40_PULLCFG40_Msk       (0xe000UL)                /*!< PULLCFG40 (Bitfield-Mask: 0x07)                       */
31726 #define GPIO_PINCFG40_SR40_Pos            (12UL)                    /*!< SR40 (Bit 12)                                         */
31727 #define GPIO_PINCFG40_SR40_Msk            (0x1000UL)                /*!< SR40 (Bitfield-Mask: 0x01)                            */
31728 #define GPIO_PINCFG40_DS40_Pos            (10UL)                    /*!< DS40 (Bit 10)                                         */
31729 #define GPIO_PINCFG40_DS40_Msk            (0xc00UL)                 /*!< DS40 (Bitfield-Mask: 0x03)                            */
31730 #define GPIO_PINCFG40_OUTCFG40_Pos        (8UL)                     /*!< OUTCFG40 (Bit 8)                                      */
31731 #define GPIO_PINCFG40_OUTCFG40_Msk        (0x300UL)                 /*!< OUTCFG40 (Bitfield-Mask: 0x03)                        */
31732 #define GPIO_PINCFG40_IRPTEN40_Pos        (6UL)                     /*!< IRPTEN40 (Bit 6)                                      */
31733 #define GPIO_PINCFG40_IRPTEN40_Msk        (0xc0UL)                  /*!< IRPTEN40 (Bitfield-Mask: 0x03)                        */
31734 #define GPIO_PINCFG40_RDZERO40_Pos        (5UL)                     /*!< RDZERO40 (Bit 5)                                      */
31735 #define GPIO_PINCFG40_RDZERO40_Msk        (0x20UL)                  /*!< RDZERO40 (Bitfield-Mask: 0x01)                        */
31736 #define GPIO_PINCFG40_INPEN40_Pos         (4UL)                     /*!< INPEN40 (Bit 4)                                       */
31737 #define GPIO_PINCFG40_INPEN40_Msk         (0x10UL)                  /*!< INPEN40 (Bitfield-Mask: 0x01)                         */
31738 #define GPIO_PINCFG40_FNCSEL40_Pos        (0UL)                     /*!< FNCSEL40 (Bit 0)                                      */
31739 #define GPIO_PINCFG40_FNCSEL40_Msk        (0xfUL)                   /*!< FNCSEL40 (Bitfield-Mask: 0x0f)                        */
31740 /* =======================================================  PINCFG41  ======================================================== */
31741 #define GPIO_PINCFG41_FOEN41_Pos          (27UL)                    /*!< FOEN41 (Bit 27)                                       */
31742 #define GPIO_PINCFG41_FOEN41_Msk          (0x8000000UL)             /*!< FOEN41 (Bitfield-Mask: 0x01)                          */
31743 #define GPIO_PINCFG41_FIEN41_Pos          (26UL)                    /*!< FIEN41 (Bit 26)                                       */
31744 #define GPIO_PINCFG41_FIEN41_Msk          (0x4000000UL)             /*!< FIEN41 (Bitfield-Mask: 0x01)                          */
31745 #define GPIO_PINCFG41_NCEPOL41_Pos        (22UL)                    /*!< NCEPOL41 (Bit 22)                                     */
31746 #define GPIO_PINCFG41_NCEPOL41_Msk        (0x400000UL)              /*!< NCEPOL41 (Bitfield-Mask: 0x01)                        */
31747 #define GPIO_PINCFG41_NCESRC41_Pos        (16UL)                    /*!< NCESRC41 (Bit 16)                                     */
31748 #define GPIO_PINCFG41_NCESRC41_Msk        (0x3f0000UL)              /*!< NCESRC41 (Bitfield-Mask: 0x3f)                        */
31749 #define GPIO_PINCFG41_PULLCFG41_Pos       (13UL)                    /*!< PULLCFG41 (Bit 13)                                    */
31750 #define GPIO_PINCFG41_PULLCFG41_Msk       (0xe000UL)                /*!< PULLCFG41 (Bitfield-Mask: 0x07)                       */
31751 #define GPIO_PINCFG41_SR41_Pos            (12UL)                    /*!< SR41 (Bit 12)                                         */
31752 #define GPIO_PINCFG41_SR41_Msk            (0x1000UL)                /*!< SR41 (Bitfield-Mask: 0x01)                            */
31753 #define GPIO_PINCFG41_DS41_Pos            (10UL)                    /*!< DS41 (Bit 10)                                         */
31754 #define GPIO_PINCFG41_DS41_Msk            (0xc00UL)                 /*!< DS41 (Bitfield-Mask: 0x03)                            */
31755 #define GPIO_PINCFG41_OUTCFG41_Pos        (8UL)                     /*!< OUTCFG41 (Bit 8)                                      */
31756 #define GPIO_PINCFG41_OUTCFG41_Msk        (0x300UL)                 /*!< OUTCFG41 (Bitfield-Mask: 0x03)                        */
31757 #define GPIO_PINCFG41_IRPTEN41_Pos        (6UL)                     /*!< IRPTEN41 (Bit 6)                                      */
31758 #define GPIO_PINCFG41_IRPTEN41_Msk        (0xc0UL)                  /*!< IRPTEN41 (Bitfield-Mask: 0x03)                        */
31759 #define GPIO_PINCFG41_RDZERO41_Pos        (5UL)                     /*!< RDZERO41 (Bit 5)                                      */
31760 #define GPIO_PINCFG41_RDZERO41_Msk        (0x20UL)                  /*!< RDZERO41 (Bitfield-Mask: 0x01)                        */
31761 #define GPIO_PINCFG41_INPEN41_Pos         (4UL)                     /*!< INPEN41 (Bit 4)                                       */
31762 #define GPIO_PINCFG41_INPEN41_Msk         (0x10UL)                  /*!< INPEN41 (Bitfield-Mask: 0x01)                         */
31763 #define GPIO_PINCFG41_FNCSEL41_Pos        (0UL)                     /*!< FNCSEL41 (Bit 0)                                      */
31764 #define GPIO_PINCFG41_FNCSEL41_Msk        (0xfUL)                   /*!< FNCSEL41 (Bitfield-Mask: 0x0f)                        */
31765 /* =======================================================  PINCFG42  ======================================================== */
31766 #define GPIO_PINCFG42_FOEN42_Pos          (27UL)                    /*!< FOEN42 (Bit 27)                                       */
31767 #define GPIO_PINCFG42_FOEN42_Msk          (0x8000000UL)             /*!< FOEN42 (Bitfield-Mask: 0x01)                          */
31768 #define GPIO_PINCFG42_FIEN42_Pos          (26UL)                    /*!< FIEN42 (Bit 26)                                       */
31769 #define GPIO_PINCFG42_FIEN42_Msk          (0x4000000UL)             /*!< FIEN42 (Bitfield-Mask: 0x01)                          */
31770 #define GPIO_PINCFG42_NCEPOL42_Pos        (22UL)                    /*!< NCEPOL42 (Bit 22)                                     */
31771 #define GPIO_PINCFG42_NCEPOL42_Msk        (0x400000UL)              /*!< NCEPOL42 (Bitfield-Mask: 0x01)                        */
31772 #define GPIO_PINCFG42_NCESRC42_Pos        (16UL)                    /*!< NCESRC42 (Bit 16)                                     */
31773 #define GPIO_PINCFG42_NCESRC42_Msk        (0x3f0000UL)              /*!< NCESRC42 (Bitfield-Mask: 0x3f)                        */
31774 #define GPIO_PINCFG42_PULLCFG42_Pos       (13UL)                    /*!< PULLCFG42 (Bit 13)                                    */
31775 #define GPIO_PINCFG42_PULLCFG42_Msk       (0xe000UL)                /*!< PULLCFG42 (Bitfield-Mask: 0x07)                       */
31776 #define GPIO_PINCFG42_SR42_Pos            (12UL)                    /*!< SR42 (Bit 12)                                         */
31777 #define GPIO_PINCFG42_SR42_Msk            (0x1000UL)                /*!< SR42 (Bitfield-Mask: 0x01)                            */
31778 #define GPIO_PINCFG42_DS42_Pos            (10UL)                    /*!< DS42 (Bit 10)                                         */
31779 #define GPIO_PINCFG42_DS42_Msk            (0xc00UL)                 /*!< DS42 (Bitfield-Mask: 0x03)                            */
31780 #define GPIO_PINCFG42_OUTCFG42_Pos        (8UL)                     /*!< OUTCFG42 (Bit 8)                                      */
31781 #define GPIO_PINCFG42_OUTCFG42_Msk        (0x300UL)                 /*!< OUTCFG42 (Bitfield-Mask: 0x03)                        */
31782 #define GPIO_PINCFG42_IRPTEN42_Pos        (6UL)                     /*!< IRPTEN42 (Bit 6)                                      */
31783 #define GPIO_PINCFG42_IRPTEN42_Msk        (0xc0UL)                  /*!< IRPTEN42 (Bitfield-Mask: 0x03)                        */
31784 #define GPIO_PINCFG42_RDZERO42_Pos        (5UL)                     /*!< RDZERO42 (Bit 5)                                      */
31785 #define GPIO_PINCFG42_RDZERO42_Msk        (0x20UL)                  /*!< RDZERO42 (Bitfield-Mask: 0x01)                        */
31786 #define GPIO_PINCFG42_INPEN42_Pos         (4UL)                     /*!< INPEN42 (Bit 4)                                       */
31787 #define GPIO_PINCFG42_INPEN42_Msk         (0x10UL)                  /*!< INPEN42 (Bitfield-Mask: 0x01)                         */
31788 #define GPIO_PINCFG42_FNCSEL42_Pos        (0UL)                     /*!< FNCSEL42 (Bit 0)                                      */
31789 #define GPIO_PINCFG42_FNCSEL42_Msk        (0xfUL)                   /*!< FNCSEL42 (Bitfield-Mask: 0x0f)                        */
31790 /* =======================================================  PINCFG43  ======================================================== */
31791 #define GPIO_PINCFG43_FOEN43_Pos          (27UL)                    /*!< FOEN43 (Bit 27)                                       */
31792 #define GPIO_PINCFG43_FOEN43_Msk          (0x8000000UL)             /*!< FOEN43 (Bitfield-Mask: 0x01)                          */
31793 #define GPIO_PINCFG43_FIEN43_Pos          (26UL)                    /*!< FIEN43 (Bit 26)                                       */
31794 #define GPIO_PINCFG43_FIEN43_Msk          (0x4000000UL)             /*!< FIEN43 (Bitfield-Mask: 0x01)                          */
31795 #define GPIO_PINCFG43_NCEPOL43_Pos        (22UL)                    /*!< NCEPOL43 (Bit 22)                                     */
31796 #define GPIO_PINCFG43_NCEPOL43_Msk        (0x400000UL)              /*!< NCEPOL43 (Bitfield-Mask: 0x01)                        */
31797 #define GPIO_PINCFG43_NCESRC43_Pos        (16UL)                    /*!< NCESRC43 (Bit 16)                                     */
31798 #define GPIO_PINCFG43_NCESRC43_Msk        (0x3f0000UL)              /*!< NCESRC43 (Bitfield-Mask: 0x3f)                        */
31799 #define GPIO_PINCFG43_PULLCFG43_Pos       (13UL)                    /*!< PULLCFG43 (Bit 13)                                    */
31800 #define GPIO_PINCFG43_PULLCFG43_Msk       (0xe000UL)                /*!< PULLCFG43 (Bitfield-Mask: 0x07)                       */
31801 #define GPIO_PINCFG43_SR43_Pos            (12UL)                    /*!< SR43 (Bit 12)                                         */
31802 #define GPIO_PINCFG43_SR43_Msk            (0x1000UL)                /*!< SR43 (Bitfield-Mask: 0x01)                            */
31803 #define GPIO_PINCFG43_DS43_Pos            (10UL)                    /*!< DS43 (Bit 10)                                         */
31804 #define GPIO_PINCFG43_DS43_Msk            (0xc00UL)                 /*!< DS43 (Bitfield-Mask: 0x03)                            */
31805 #define GPIO_PINCFG43_OUTCFG43_Pos        (8UL)                     /*!< OUTCFG43 (Bit 8)                                      */
31806 #define GPIO_PINCFG43_OUTCFG43_Msk        (0x300UL)                 /*!< OUTCFG43 (Bitfield-Mask: 0x03)                        */
31807 #define GPIO_PINCFG43_IRPTEN43_Pos        (6UL)                     /*!< IRPTEN43 (Bit 6)                                      */
31808 #define GPIO_PINCFG43_IRPTEN43_Msk        (0xc0UL)                  /*!< IRPTEN43 (Bitfield-Mask: 0x03)                        */
31809 #define GPIO_PINCFG43_RDZERO43_Pos        (5UL)                     /*!< RDZERO43 (Bit 5)                                      */
31810 #define GPIO_PINCFG43_RDZERO43_Msk        (0x20UL)                  /*!< RDZERO43 (Bitfield-Mask: 0x01)                        */
31811 #define GPIO_PINCFG43_INPEN43_Pos         (4UL)                     /*!< INPEN43 (Bit 4)                                       */
31812 #define GPIO_PINCFG43_INPEN43_Msk         (0x10UL)                  /*!< INPEN43 (Bitfield-Mask: 0x01)                         */
31813 #define GPIO_PINCFG43_FNCSEL43_Pos        (0UL)                     /*!< FNCSEL43 (Bit 0)                                      */
31814 #define GPIO_PINCFG43_FNCSEL43_Msk        (0xfUL)                   /*!< FNCSEL43 (Bitfield-Mask: 0x0f)                        */
31815 /* =======================================================  PINCFG44  ======================================================== */
31816 #define GPIO_PINCFG44_FOEN44_Pos          (27UL)                    /*!< FOEN44 (Bit 27)                                       */
31817 #define GPIO_PINCFG44_FOEN44_Msk          (0x8000000UL)             /*!< FOEN44 (Bitfield-Mask: 0x01)                          */
31818 #define GPIO_PINCFG44_FIEN44_Pos          (26UL)                    /*!< FIEN44 (Bit 26)                                       */
31819 #define GPIO_PINCFG44_FIEN44_Msk          (0x4000000UL)             /*!< FIEN44 (Bitfield-Mask: 0x01)                          */
31820 #define GPIO_PINCFG44_NCEPOL44_Pos        (22UL)                    /*!< NCEPOL44 (Bit 22)                                     */
31821 #define GPIO_PINCFG44_NCEPOL44_Msk        (0x400000UL)              /*!< NCEPOL44 (Bitfield-Mask: 0x01)                        */
31822 #define GPIO_PINCFG44_NCESRC44_Pos        (16UL)                    /*!< NCESRC44 (Bit 16)                                     */
31823 #define GPIO_PINCFG44_NCESRC44_Msk        (0x3f0000UL)              /*!< NCESRC44 (Bitfield-Mask: 0x3f)                        */
31824 #define GPIO_PINCFG44_PULLCFG44_Pos       (13UL)                    /*!< PULLCFG44 (Bit 13)                                    */
31825 #define GPIO_PINCFG44_PULLCFG44_Msk       (0xe000UL)                /*!< PULLCFG44 (Bitfield-Mask: 0x07)                       */
31826 #define GPIO_PINCFG44_SR44_Pos            (12UL)                    /*!< SR44 (Bit 12)                                         */
31827 #define GPIO_PINCFG44_SR44_Msk            (0x1000UL)                /*!< SR44 (Bitfield-Mask: 0x01)                            */
31828 #define GPIO_PINCFG44_DS44_Pos            (10UL)                    /*!< DS44 (Bit 10)                                         */
31829 #define GPIO_PINCFG44_DS44_Msk            (0xc00UL)                 /*!< DS44 (Bitfield-Mask: 0x03)                            */
31830 #define GPIO_PINCFG44_OUTCFG44_Pos        (8UL)                     /*!< OUTCFG44 (Bit 8)                                      */
31831 #define GPIO_PINCFG44_OUTCFG44_Msk        (0x300UL)                 /*!< OUTCFG44 (Bitfield-Mask: 0x03)                        */
31832 #define GPIO_PINCFG44_IRPTEN44_Pos        (6UL)                     /*!< IRPTEN44 (Bit 6)                                      */
31833 #define GPIO_PINCFG44_IRPTEN44_Msk        (0xc0UL)                  /*!< IRPTEN44 (Bitfield-Mask: 0x03)                        */
31834 #define GPIO_PINCFG44_RDZERO44_Pos        (5UL)                     /*!< RDZERO44 (Bit 5)                                      */
31835 #define GPIO_PINCFG44_RDZERO44_Msk        (0x20UL)                  /*!< RDZERO44 (Bitfield-Mask: 0x01)                        */
31836 #define GPIO_PINCFG44_INPEN44_Pos         (4UL)                     /*!< INPEN44 (Bit 4)                                       */
31837 #define GPIO_PINCFG44_INPEN44_Msk         (0x10UL)                  /*!< INPEN44 (Bitfield-Mask: 0x01)                         */
31838 #define GPIO_PINCFG44_FNCSEL44_Pos        (0UL)                     /*!< FNCSEL44 (Bit 0)                                      */
31839 #define GPIO_PINCFG44_FNCSEL44_Msk        (0xfUL)                   /*!< FNCSEL44 (Bitfield-Mask: 0x0f)                        */
31840 /* =======================================================  PINCFG45  ======================================================== */
31841 #define GPIO_PINCFG45_FOEN45_Pos          (27UL)                    /*!< FOEN45 (Bit 27)                                       */
31842 #define GPIO_PINCFG45_FOEN45_Msk          (0x8000000UL)             /*!< FOEN45 (Bitfield-Mask: 0x01)                          */
31843 #define GPIO_PINCFG45_FIEN45_Pos          (26UL)                    /*!< FIEN45 (Bit 26)                                       */
31844 #define GPIO_PINCFG45_FIEN45_Msk          (0x4000000UL)             /*!< FIEN45 (Bitfield-Mask: 0x01)                          */
31845 #define GPIO_PINCFG45_NCEPOL45_Pos        (22UL)                    /*!< NCEPOL45 (Bit 22)                                     */
31846 #define GPIO_PINCFG45_NCEPOL45_Msk        (0x400000UL)              /*!< NCEPOL45 (Bitfield-Mask: 0x01)                        */
31847 #define GPIO_PINCFG45_NCESRC45_Pos        (16UL)                    /*!< NCESRC45 (Bit 16)                                     */
31848 #define GPIO_PINCFG45_NCESRC45_Msk        (0x3f0000UL)              /*!< NCESRC45 (Bitfield-Mask: 0x3f)                        */
31849 #define GPIO_PINCFG45_PULLCFG45_Pos       (13UL)                    /*!< PULLCFG45 (Bit 13)                                    */
31850 #define GPIO_PINCFG45_PULLCFG45_Msk       (0xe000UL)                /*!< PULLCFG45 (Bitfield-Mask: 0x07)                       */
31851 #define GPIO_PINCFG45_SR45_Pos            (12UL)                    /*!< SR45 (Bit 12)                                         */
31852 #define GPIO_PINCFG45_SR45_Msk            (0x1000UL)                /*!< SR45 (Bitfield-Mask: 0x01)                            */
31853 #define GPIO_PINCFG45_DS45_Pos            (10UL)                    /*!< DS45 (Bit 10)                                         */
31854 #define GPIO_PINCFG45_DS45_Msk            (0xc00UL)                 /*!< DS45 (Bitfield-Mask: 0x03)                            */
31855 #define GPIO_PINCFG45_OUTCFG45_Pos        (8UL)                     /*!< OUTCFG45 (Bit 8)                                      */
31856 #define GPIO_PINCFG45_OUTCFG45_Msk        (0x300UL)                 /*!< OUTCFG45 (Bitfield-Mask: 0x03)                        */
31857 #define GPIO_PINCFG45_IRPTEN45_Pos        (6UL)                     /*!< IRPTEN45 (Bit 6)                                      */
31858 #define GPIO_PINCFG45_IRPTEN45_Msk        (0xc0UL)                  /*!< IRPTEN45 (Bitfield-Mask: 0x03)                        */
31859 #define GPIO_PINCFG45_RDZERO45_Pos        (5UL)                     /*!< RDZERO45 (Bit 5)                                      */
31860 #define GPIO_PINCFG45_RDZERO45_Msk        (0x20UL)                  /*!< RDZERO45 (Bitfield-Mask: 0x01)                        */
31861 #define GPIO_PINCFG45_INPEN45_Pos         (4UL)                     /*!< INPEN45 (Bit 4)                                       */
31862 #define GPIO_PINCFG45_INPEN45_Msk         (0x10UL)                  /*!< INPEN45 (Bitfield-Mask: 0x01)                         */
31863 #define GPIO_PINCFG45_FNCSEL45_Pos        (0UL)                     /*!< FNCSEL45 (Bit 0)                                      */
31864 #define GPIO_PINCFG45_FNCSEL45_Msk        (0xfUL)                   /*!< FNCSEL45 (Bitfield-Mask: 0x0f)                        */
31865 /* =======================================================  PINCFG46  ======================================================== */
31866 #define GPIO_PINCFG46_FOEN46_Pos          (27UL)                    /*!< FOEN46 (Bit 27)                                       */
31867 #define GPIO_PINCFG46_FOEN46_Msk          (0x8000000UL)             /*!< FOEN46 (Bitfield-Mask: 0x01)                          */
31868 #define GPIO_PINCFG46_FIEN46_Pos          (26UL)                    /*!< FIEN46 (Bit 26)                                       */
31869 #define GPIO_PINCFG46_FIEN46_Msk          (0x4000000UL)             /*!< FIEN46 (Bitfield-Mask: 0x01)                          */
31870 #define GPIO_PINCFG46_NCEPOL46_Pos        (22UL)                    /*!< NCEPOL46 (Bit 22)                                     */
31871 #define GPIO_PINCFG46_NCEPOL46_Msk        (0x400000UL)              /*!< NCEPOL46 (Bitfield-Mask: 0x01)                        */
31872 #define GPIO_PINCFG46_NCESRC46_Pos        (16UL)                    /*!< NCESRC46 (Bit 16)                                     */
31873 #define GPIO_PINCFG46_NCESRC46_Msk        (0x3f0000UL)              /*!< NCESRC46 (Bitfield-Mask: 0x3f)                        */
31874 #define GPIO_PINCFG46_PULLCFG46_Pos       (13UL)                    /*!< PULLCFG46 (Bit 13)                                    */
31875 #define GPIO_PINCFG46_PULLCFG46_Msk       (0xe000UL)                /*!< PULLCFG46 (Bitfield-Mask: 0x07)                       */
31876 #define GPIO_PINCFG46_SR46_Pos            (12UL)                    /*!< SR46 (Bit 12)                                         */
31877 #define GPIO_PINCFG46_SR46_Msk            (0x1000UL)                /*!< SR46 (Bitfield-Mask: 0x01)                            */
31878 #define GPIO_PINCFG46_DS46_Pos            (10UL)                    /*!< DS46 (Bit 10)                                         */
31879 #define GPIO_PINCFG46_DS46_Msk            (0xc00UL)                 /*!< DS46 (Bitfield-Mask: 0x03)                            */
31880 #define GPIO_PINCFG46_OUTCFG46_Pos        (8UL)                     /*!< OUTCFG46 (Bit 8)                                      */
31881 #define GPIO_PINCFG46_OUTCFG46_Msk        (0x300UL)                 /*!< OUTCFG46 (Bitfield-Mask: 0x03)                        */
31882 #define GPIO_PINCFG46_IRPTEN46_Pos        (6UL)                     /*!< IRPTEN46 (Bit 6)                                      */
31883 #define GPIO_PINCFG46_IRPTEN46_Msk        (0xc0UL)                  /*!< IRPTEN46 (Bitfield-Mask: 0x03)                        */
31884 #define GPIO_PINCFG46_RDZERO46_Pos        (5UL)                     /*!< RDZERO46 (Bit 5)                                      */
31885 #define GPIO_PINCFG46_RDZERO46_Msk        (0x20UL)                  /*!< RDZERO46 (Bitfield-Mask: 0x01)                        */
31886 #define GPIO_PINCFG46_INPEN46_Pos         (4UL)                     /*!< INPEN46 (Bit 4)                                       */
31887 #define GPIO_PINCFG46_INPEN46_Msk         (0x10UL)                  /*!< INPEN46 (Bitfield-Mask: 0x01)                         */
31888 #define GPIO_PINCFG46_FNCSEL46_Pos        (0UL)                     /*!< FNCSEL46 (Bit 0)                                      */
31889 #define GPIO_PINCFG46_FNCSEL46_Msk        (0xfUL)                   /*!< FNCSEL46 (Bitfield-Mask: 0x0f)                        */
31890 /* =======================================================  PINCFG47  ======================================================== */
31891 #define GPIO_PINCFG47_FOEN47_Pos          (27UL)                    /*!< FOEN47 (Bit 27)                                       */
31892 #define GPIO_PINCFG47_FOEN47_Msk          (0x8000000UL)             /*!< FOEN47 (Bitfield-Mask: 0x01)                          */
31893 #define GPIO_PINCFG47_FIEN47_Pos          (26UL)                    /*!< FIEN47 (Bit 26)                                       */
31894 #define GPIO_PINCFG47_FIEN47_Msk          (0x4000000UL)             /*!< FIEN47 (Bitfield-Mask: 0x01)                          */
31895 #define GPIO_PINCFG47_NCEPOL47_Pos        (22UL)                    /*!< NCEPOL47 (Bit 22)                                     */
31896 #define GPIO_PINCFG47_NCEPOL47_Msk        (0x400000UL)              /*!< NCEPOL47 (Bitfield-Mask: 0x01)                        */
31897 #define GPIO_PINCFG47_NCESRC47_Pos        (16UL)                    /*!< NCESRC47 (Bit 16)                                     */
31898 #define GPIO_PINCFG47_NCESRC47_Msk        (0x3f0000UL)              /*!< NCESRC47 (Bitfield-Mask: 0x3f)                        */
31899 #define GPIO_PINCFG47_PULLCFG47_Pos       (13UL)                    /*!< PULLCFG47 (Bit 13)                                    */
31900 #define GPIO_PINCFG47_PULLCFG47_Msk       (0xe000UL)                /*!< PULLCFG47 (Bitfield-Mask: 0x07)                       */
31901 #define GPIO_PINCFG47_SR47_Pos            (12UL)                    /*!< SR47 (Bit 12)                                         */
31902 #define GPIO_PINCFG47_SR47_Msk            (0x1000UL)                /*!< SR47 (Bitfield-Mask: 0x01)                            */
31903 #define GPIO_PINCFG47_DS47_Pos            (10UL)                    /*!< DS47 (Bit 10)                                         */
31904 #define GPIO_PINCFG47_DS47_Msk            (0xc00UL)                 /*!< DS47 (Bitfield-Mask: 0x03)                            */
31905 #define GPIO_PINCFG47_OUTCFG47_Pos        (8UL)                     /*!< OUTCFG47 (Bit 8)                                      */
31906 #define GPIO_PINCFG47_OUTCFG47_Msk        (0x300UL)                 /*!< OUTCFG47 (Bitfield-Mask: 0x03)                        */
31907 #define GPIO_PINCFG47_IRPTEN47_Pos        (6UL)                     /*!< IRPTEN47 (Bit 6)                                      */
31908 #define GPIO_PINCFG47_IRPTEN47_Msk        (0xc0UL)                  /*!< IRPTEN47 (Bitfield-Mask: 0x03)                        */
31909 #define GPIO_PINCFG47_RDZERO47_Pos        (5UL)                     /*!< RDZERO47 (Bit 5)                                      */
31910 #define GPIO_PINCFG47_RDZERO47_Msk        (0x20UL)                  /*!< RDZERO47 (Bitfield-Mask: 0x01)                        */
31911 #define GPIO_PINCFG47_INPEN47_Pos         (4UL)                     /*!< INPEN47 (Bit 4)                                       */
31912 #define GPIO_PINCFG47_INPEN47_Msk         (0x10UL)                  /*!< INPEN47 (Bitfield-Mask: 0x01)                         */
31913 #define GPIO_PINCFG47_FNCSEL47_Pos        (0UL)                     /*!< FNCSEL47 (Bit 0)                                      */
31914 #define GPIO_PINCFG47_FNCSEL47_Msk        (0xfUL)                   /*!< FNCSEL47 (Bitfield-Mask: 0x0f)                        */
31915 /* =======================================================  PINCFG48  ======================================================== */
31916 #define GPIO_PINCFG48_FOEN48_Pos          (27UL)                    /*!< FOEN48 (Bit 27)                                       */
31917 #define GPIO_PINCFG48_FOEN48_Msk          (0x8000000UL)             /*!< FOEN48 (Bitfield-Mask: 0x01)                          */
31918 #define GPIO_PINCFG48_FIEN48_Pos          (26UL)                    /*!< FIEN48 (Bit 26)                                       */
31919 #define GPIO_PINCFG48_FIEN48_Msk          (0x4000000UL)             /*!< FIEN48 (Bitfield-Mask: 0x01)                          */
31920 #define GPIO_PINCFG48_NCEPOL48_Pos        (22UL)                    /*!< NCEPOL48 (Bit 22)                                     */
31921 #define GPIO_PINCFG48_NCEPOL48_Msk        (0x400000UL)              /*!< NCEPOL48 (Bitfield-Mask: 0x01)                        */
31922 #define GPIO_PINCFG48_NCESRC48_Pos        (16UL)                    /*!< NCESRC48 (Bit 16)                                     */
31923 #define GPIO_PINCFG48_NCESRC48_Msk        (0x3f0000UL)              /*!< NCESRC48 (Bitfield-Mask: 0x3f)                        */
31924 #define GPIO_PINCFG48_PULLCFG48_Pos       (13UL)                    /*!< PULLCFG48 (Bit 13)                                    */
31925 #define GPIO_PINCFG48_PULLCFG48_Msk       (0xe000UL)                /*!< PULLCFG48 (Bitfield-Mask: 0x07)                       */
31926 #define GPIO_PINCFG48_SR48_Pos            (12UL)                    /*!< SR48 (Bit 12)                                         */
31927 #define GPIO_PINCFG48_SR48_Msk            (0x1000UL)                /*!< SR48 (Bitfield-Mask: 0x01)                            */
31928 #define GPIO_PINCFG48_DS48_Pos            (10UL)                    /*!< DS48 (Bit 10)                                         */
31929 #define GPIO_PINCFG48_DS48_Msk            (0xc00UL)                 /*!< DS48 (Bitfield-Mask: 0x03)                            */
31930 #define GPIO_PINCFG48_OUTCFG48_Pos        (8UL)                     /*!< OUTCFG48 (Bit 8)                                      */
31931 #define GPIO_PINCFG48_OUTCFG48_Msk        (0x300UL)                 /*!< OUTCFG48 (Bitfield-Mask: 0x03)                        */
31932 #define GPIO_PINCFG48_IRPTEN48_Pos        (6UL)                     /*!< IRPTEN48 (Bit 6)                                      */
31933 #define GPIO_PINCFG48_IRPTEN48_Msk        (0xc0UL)                  /*!< IRPTEN48 (Bitfield-Mask: 0x03)                        */
31934 #define GPIO_PINCFG48_RDZERO48_Pos        (5UL)                     /*!< RDZERO48 (Bit 5)                                      */
31935 #define GPIO_PINCFG48_RDZERO48_Msk        (0x20UL)                  /*!< RDZERO48 (Bitfield-Mask: 0x01)                        */
31936 #define GPIO_PINCFG48_INPEN48_Pos         (4UL)                     /*!< INPEN48 (Bit 4)                                       */
31937 #define GPIO_PINCFG48_INPEN48_Msk         (0x10UL)                  /*!< INPEN48 (Bitfield-Mask: 0x01)                         */
31938 #define GPIO_PINCFG48_FNCSEL48_Pos        (0UL)                     /*!< FNCSEL48 (Bit 0)                                      */
31939 #define GPIO_PINCFG48_FNCSEL48_Msk        (0xfUL)                   /*!< FNCSEL48 (Bitfield-Mask: 0x0f)                        */
31940 /* =======================================================  PINCFG49  ======================================================== */
31941 #define GPIO_PINCFG49_FOEN49_Pos          (27UL)                    /*!< FOEN49 (Bit 27)                                       */
31942 #define GPIO_PINCFG49_FOEN49_Msk          (0x8000000UL)             /*!< FOEN49 (Bitfield-Mask: 0x01)                          */
31943 #define GPIO_PINCFG49_FIEN49_Pos          (26UL)                    /*!< FIEN49 (Bit 26)                                       */
31944 #define GPIO_PINCFG49_FIEN49_Msk          (0x4000000UL)             /*!< FIEN49 (Bitfield-Mask: 0x01)                          */
31945 #define GPIO_PINCFG49_NCEPOL49_Pos        (22UL)                    /*!< NCEPOL49 (Bit 22)                                     */
31946 #define GPIO_PINCFG49_NCEPOL49_Msk        (0x400000UL)              /*!< NCEPOL49 (Bitfield-Mask: 0x01)                        */
31947 #define GPIO_PINCFG49_NCESRC49_Pos        (16UL)                    /*!< NCESRC49 (Bit 16)                                     */
31948 #define GPIO_PINCFG49_NCESRC49_Msk        (0x3f0000UL)              /*!< NCESRC49 (Bitfield-Mask: 0x3f)                        */
31949 #define GPIO_PINCFG49_PULLCFG49_Pos       (13UL)                    /*!< PULLCFG49 (Bit 13)                                    */
31950 #define GPIO_PINCFG49_PULLCFG49_Msk       (0xe000UL)                /*!< PULLCFG49 (Bitfield-Mask: 0x07)                       */
31951 #define GPIO_PINCFG49_SR49_Pos            (12UL)                    /*!< SR49 (Bit 12)                                         */
31952 #define GPIO_PINCFG49_SR49_Msk            (0x1000UL)                /*!< SR49 (Bitfield-Mask: 0x01)                            */
31953 #define GPIO_PINCFG49_DS49_Pos            (10UL)                    /*!< DS49 (Bit 10)                                         */
31954 #define GPIO_PINCFG49_DS49_Msk            (0xc00UL)                 /*!< DS49 (Bitfield-Mask: 0x03)                            */
31955 #define GPIO_PINCFG49_OUTCFG49_Pos        (8UL)                     /*!< OUTCFG49 (Bit 8)                                      */
31956 #define GPIO_PINCFG49_OUTCFG49_Msk        (0x300UL)                 /*!< OUTCFG49 (Bitfield-Mask: 0x03)                        */
31957 #define GPIO_PINCFG49_IRPTEN49_Pos        (6UL)                     /*!< IRPTEN49 (Bit 6)                                      */
31958 #define GPIO_PINCFG49_IRPTEN49_Msk        (0xc0UL)                  /*!< IRPTEN49 (Bitfield-Mask: 0x03)                        */
31959 #define GPIO_PINCFG49_RDZERO49_Pos        (5UL)                     /*!< RDZERO49 (Bit 5)                                      */
31960 #define GPIO_PINCFG49_RDZERO49_Msk        (0x20UL)                  /*!< RDZERO49 (Bitfield-Mask: 0x01)                        */
31961 #define GPIO_PINCFG49_INPEN49_Pos         (4UL)                     /*!< INPEN49 (Bit 4)                                       */
31962 #define GPIO_PINCFG49_INPEN49_Msk         (0x10UL)                  /*!< INPEN49 (Bitfield-Mask: 0x01)                         */
31963 #define GPIO_PINCFG49_FNCSEL49_Pos        (0UL)                     /*!< FNCSEL49 (Bit 0)                                      */
31964 #define GPIO_PINCFG49_FNCSEL49_Msk        (0xfUL)                   /*!< FNCSEL49 (Bitfield-Mask: 0x0f)                        */
31965 /* =======================================================  PINCFG50  ======================================================== */
31966 #define GPIO_PINCFG50_FOEN50_Pos          (27UL)                    /*!< FOEN50 (Bit 27)                                       */
31967 #define GPIO_PINCFG50_FOEN50_Msk          (0x8000000UL)             /*!< FOEN50 (Bitfield-Mask: 0x01)                          */
31968 #define GPIO_PINCFG50_FIEN50_Pos          (26UL)                    /*!< FIEN50 (Bit 26)                                       */
31969 #define GPIO_PINCFG50_FIEN50_Msk          (0x4000000UL)             /*!< FIEN50 (Bitfield-Mask: 0x01)                          */
31970 #define GPIO_PINCFG50_NCEPOL50_Pos        (22UL)                    /*!< NCEPOL50 (Bit 22)                                     */
31971 #define GPIO_PINCFG50_NCEPOL50_Msk        (0x400000UL)              /*!< NCEPOL50 (Bitfield-Mask: 0x01)                        */
31972 #define GPIO_PINCFG50_NCESRC50_Pos        (16UL)                    /*!< NCESRC50 (Bit 16)                                     */
31973 #define GPIO_PINCFG50_NCESRC50_Msk        (0x3f0000UL)              /*!< NCESRC50 (Bitfield-Mask: 0x3f)                        */
31974 #define GPIO_PINCFG50_PULLCFG50_Pos       (13UL)                    /*!< PULLCFG50 (Bit 13)                                    */
31975 #define GPIO_PINCFG50_PULLCFG50_Msk       (0xe000UL)                /*!< PULLCFG50 (Bitfield-Mask: 0x07)                       */
31976 #define GPIO_PINCFG50_SR50_Pos            (12UL)                    /*!< SR50 (Bit 12)                                         */
31977 #define GPIO_PINCFG50_SR50_Msk            (0x1000UL)                /*!< SR50 (Bitfield-Mask: 0x01)                            */
31978 #define GPIO_PINCFG50_DS50_Pos            (10UL)                    /*!< DS50 (Bit 10)                                         */
31979 #define GPIO_PINCFG50_DS50_Msk            (0xc00UL)                 /*!< DS50 (Bitfield-Mask: 0x03)                            */
31980 #define GPIO_PINCFG50_OUTCFG50_Pos        (8UL)                     /*!< OUTCFG50 (Bit 8)                                      */
31981 #define GPIO_PINCFG50_OUTCFG50_Msk        (0x300UL)                 /*!< OUTCFG50 (Bitfield-Mask: 0x03)                        */
31982 #define GPIO_PINCFG50_IRPTEN50_Pos        (6UL)                     /*!< IRPTEN50 (Bit 6)                                      */
31983 #define GPIO_PINCFG50_IRPTEN50_Msk        (0xc0UL)                  /*!< IRPTEN50 (Bitfield-Mask: 0x03)                        */
31984 #define GPIO_PINCFG50_RDZERO50_Pos        (5UL)                     /*!< RDZERO50 (Bit 5)                                      */
31985 #define GPIO_PINCFG50_RDZERO50_Msk        (0x20UL)                  /*!< RDZERO50 (Bitfield-Mask: 0x01)                        */
31986 #define GPIO_PINCFG50_INPEN50_Pos         (4UL)                     /*!< INPEN50 (Bit 4)                                       */
31987 #define GPIO_PINCFG50_INPEN50_Msk         (0x10UL)                  /*!< INPEN50 (Bitfield-Mask: 0x01)                         */
31988 #define GPIO_PINCFG50_FNCSEL50_Pos        (0UL)                     /*!< FNCSEL50 (Bit 0)                                      */
31989 #define GPIO_PINCFG50_FNCSEL50_Msk        (0xfUL)                   /*!< FNCSEL50 (Bitfield-Mask: 0x0f)                        */
31990 /* =======================================================  PINCFG51  ======================================================== */
31991 #define GPIO_PINCFG51_FOEN51_Pos          (27UL)                    /*!< FOEN51 (Bit 27)                                       */
31992 #define GPIO_PINCFG51_FOEN51_Msk          (0x8000000UL)             /*!< FOEN51 (Bitfield-Mask: 0x01)                          */
31993 #define GPIO_PINCFG51_FIEN51_Pos          (26UL)                    /*!< FIEN51 (Bit 26)                                       */
31994 #define GPIO_PINCFG51_FIEN51_Msk          (0x4000000UL)             /*!< FIEN51 (Bitfield-Mask: 0x01)                          */
31995 #define GPIO_PINCFG51_NCEPOL51_Pos        (22UL)                    /*!< NCEPOL51 (Bit 22)                                     */
31996 #define GPIO_PINCFG51_NCEPOL51_Msk        (0x400000UL)              /*!< NCEPOL51 (Bitfield-Mask: 0x01)                        */
31997 #define GPIO_PINCFG51_NCESRC51_Pos        (16UL)                    /*!< NCESRC51 (Bit 16)                                     */
31998 #define GPIO_PINCFG51_NCESRC51_Msk        (0x3f0000UL)              /*!< NCESRC51 (Bitfield-Mask: 0x3f)                        */
31999 #define GPIO_PINCFG51_PULLCFG51_Pos       (13UL)                    /*!< PULLCFG51 (Bit 13)                                    */
32000 #define GPIO_PINCFG51_PULLCFG51_Msk       (0xe000UL)                /*!< PULLCFG51 (Bitfield-Mask: 0x07)                       */
32001 #define GPIO_PINCFG51_SR51_Pos            (12UL)                    /*!< SR51 (Bit 12)                                         */
32002 #define GPIO_PINCFG51_SR51_Msk            (0x1000UL)                /*!< SR51 (Bitfield-Mask: 0x01)                            */
32003 #define GPIO_PINCFG51_DS51_Pos            (10UL)                    /*!< DS51 (Bit 10)                                         */
32004 #define GPIO_PINCFG51_DS51_Msk            (0xc00UL)                 /*!< DS51 (Bitfield-Mask: 0x03)                            */
32005 #define GPIO_PINCFG51_OUTCFG51_Pos        (8UL)                     /*!< OUTCFG51 (Bit 8)                                      */
32006 #define GPIO_PINCFG51_OUTCFG51_Msk        (0x300UL)                 /*!< OUTCFG51 (Bitfield-Mask: 0x03)                        */
32007 #define GPIO_PINCFG51_IRPTEN51_Pos        (6UL)                     /*!< IRPTEN51 (Bit 6)                                      */
32008 #define GPIO_PINCFG51_IRPTEN51_Msk        (0xc0UL)                  /*!< IRPTEN51 (Bitfield-Mask: 0x03)                        */
32009 #define GPIO_PINCFG51_RDZERO51_Pos        (5UL)                     /*!< RDZERO51 (Bit 5)                                      */
32010 #define GPIO_PINCFG51_RDZERO51_Msk        (0x20UL)                  /*!< RDZERO51 (Bitfield-Mask: 0x01)                        */
32011 #define GPIO_PINCFG51_INPEN51_Pos         (4UL)                     /*!< INPEN51 (Bit 4)                                       */
32012 #define GPIO_PINCFG51_INPEN51_Msk         (0x10UL)                  /*!< INPEN51 (Bitfield-Mask: 0x01)                         */
32013 #define GPIO_PINCFG51_FNCSEL51_Pos        (0UL)                     /*!< FNCSEL51 (Bit 0)                                      */
32014 #define GPIO_PINCFG51_FNCSEL51_Msk        (0xfUL)                   /*!< FNCSEL51 (Bitfield-Mask: 0x0f)                        */
32015 /* =======================================================  PINCFG52  ======================================================== */
32016 #define GPIO_PINCFG52_FOEN52_Pos          (27UL)                    /*!< FOEN52 (Bit 27)                                       */
32017 #define GPIO_PINCFG52_FOEN52_Msk          (0x8000000UL)             /*!< FOEN52 (Bitfield-Mask: 0x01)                          */
32018 #define GPIO_PINCFG52_FIEN52_Pos          (26UL)                    /*!< FIEN52 (Bit 26)                                       */
32019 #define GPIO_PINCFG52_FIEN52_Msk          (0x4000000UL)             /*!< FIEN52 (Bitfield-Mask: 0x01)                          */
32020 #define GPIO_PINCFG52_NCEPOL52_Pos        (22UL)                    /*!< NCEPOL52 (Bit 22)                                     */
32021 #define GPIO_PINCFG52_NCEPOL52_Msk        (0x400000UL)              /*!< NCEPOL52 (Bitfield-Mask: 0x01)                        */
32022 #define GPIO_PINCFG52_NCESRC52_Pos        (16UL)                    /*!< NCESRC52 (Bit 16)                                     */
32023 #define GPIO_PINCFG52_NCESRC52_Msk        (0x3f0000UL)              /*!< NCESRC52 (Bitfield-Mask: 0x3f)                        */
32024 #define GPIO_PINCFG52_PULLCFG52_Pos       (13UL)                    /*!< PULLCFG52 (Bit 13)                                    */
32025 #define GPIO_PINCFG52_PULLCFG52_Msk       (0xe000UL)                /*!< PULLCFG52 (Bitfield-Mask: 0x07)                       */
32026 #define GPIO_PINCFG52_SR52_Pos            (12UL)                    /*!< SR52 (Bit 12)                                         */
32027 #define GPIO_PINCFG52_SR52_Msk            (0x1000UL)                /*!< SR52 (Bitfield-Mask: 0x01)                            */
32028 #define GPIO_PINCFG52_DS52_Pos            (10UL)                    /*!< DS52 (Bit 10)                                         */
32029 #define GPIO_PINCFG52_DS52_Msk            (0xc00UL)                 /*!< DS52 (Bitfield-Mask: 0x03)                            */
32030 #define GPIO_PINCFG52_OUTCFG52_Pos        (8UL)                     /*!< OUTCFG52 (Bit 8)                                      */
32031 #define GPIO_PINCFG52_OUTCFG52_Msk        (0x300UL)                 /*!< OUTCFG52 (Bitfield-Mask: 0x03)                        */
32032 #define GPIO_PINCFG52_IRPTEN52_Pos        (6UL)                     /*!< IRPTEN52 (Bit 6)                                      */
32033 #define GPIO_PINCFG52_IRPTEN52_Msk        (0xc0UL)                  /*!< IRPTEN52 (Bitfield-Mask: 0x03)                        */
32034 #define GPIO_PINCFG52_RDZERO52_Pos        (5UL)                     /*!< RDZERO52 (Bit 5)                                      */
32035 #define GPIO_PINCFG52_RDZERO52_Msk        (0x20UL)                  /*!< RDZERO52 (Bitfield-Mask: 0x01)                        */
32036 #define GPIO_PINCFG52_INPEN52_Pos         (4UL)                     /*!< INPEN52 (Bit 4)                                       */
32037 #define GPIO_PINCFG52_INPEN52_Msk         (0x10UL)                  /*!< INPEN52 (Bitfield-Mask: 0x01)                         */
32038 #define GPIO_PINCFG52_FNCSEL52_Pos        (0UL)                     /*!< FNCSEL52 (Bit 0)                                      */
32039 #define GPIO_PINCFG52_FNCSEL52_Msk        (0xfUL)                   /*!< FNCSEL52 (Bitfield-Mask: 0x0f)                        */
32040 /* =======================================================  PINCFG53  ======================================================== */
32041 #define GPIO_PINCFG53_FOEN53_Pos          (27UL)                    /*!< FOEN53 (Bit 27)                                       */
32042 #define GPIO_PINCFG53_FOEN53_Msk          (0x8000000UL)             /*!< FOEN53 (Bitfield-Mask: 0x01)                          */
32043 #define GPIO_PINCFG53_FIEN53_Pos          (26UL)                    /*!< FIEN53 (Bit 26)                                       */
32044 #define GPIO_PINCFG53_FIEN53_Msk          (0x4000000UL)             /*!< FIEN53 (Bitfield-Mask: 0x01)                          */
32045 #define GPIO_PINCFG53_NCEPOL53_Pos        (22UL)                    /*!< NCEPOL53 (Bit 22)                                     */
32046 #define GPIO_PINCFG53_NCEPOL53_Msk        (0x400000UL)              /*!< NCEPOL53 (Bitfield-Mask: 0x01)                        */
32047 #define GPIO_PINCFG53_NCESRC53_Pos        (16UL)                    /*!< NCESRC53 (Bit 16)                                     */
32048 #define GPIO_PINCFG53_NCESRC53_Msk        (0x3f0000UL)              /*!< NCESRC53 (Bitfield-Mask: 0x3f)                        */
32049 #define GPIO_PINCFG53_PULLCFG53_Pos       (13UL)                    /*!< PULLCFG53 (Bit 13)                                    */
32050 #define GPIO_PINCFG53_PULLCFG53_Msk       (0xe000UL)                /*!< PULLCFG53 (Bitfield-Mask: 0x07)                       */
32051 #define GPIO_PINCFG53_SR53_Pos            (12UL)                    /*!< SR53 (Bit 12)                                         */
32052 #define GPIO_PINCFG53_SR53_Msk            (0x1000UL)                /*!< SR53 (Bitfield-Mask: 0x01)                            */
32053 #define GPIO_PINCFG53_DS53_Pos            (10UL)                    /*!< DS53 (Bit 10)                                         */
32054 #define GPIO_PINCFG53_DS53_Msk            (0xc00UL)                 /*!< DS53 (Bitfield-Mask: 0x03)                            */
32055 #define GPIO_PINCFG53_OUTCFG53_Pos        (8UL)                     /*!< OUTCFG53 (Bit 8)                                      */
32056 #define GPIO_PINCFG53_OUTCFG53_Msk        (0x300UL)                 /*!< OUTCFG53 (Bitfield-Mask: 0x03)                        */
32057 #define GPIO_PINCFG53_IRPTEN53_Pos        (6UL)                     /*!< IRPTEN53 (Bit 6)                                      */
32058 #define GPIO_PINCFG53_IRPTEN53_Msk        (0xc0UL)                  /*!< IRPTEN53 (Bitfield-Mask: 0x03)                        */
32059 #define GPIO_PINCFG53_RDZERO53_Pos        (5UL)                     /*!< RDZERO53 (Bit 5)                                      */
32060 #define GPIO_PINCFG53_RDZERO53_Msk        (0x20UL)                  /*!< RDZERO53 (Bitfield-Mask: 0x01)                        */
32061 #define GPIO_PINCFG53_INPEN53_Pos         (4UL)                     /*!< INPEN53 (Bit 4)                                       */
32062 #define GPIO_PINCFG53_INPEN53_Msk         (0x10UL)                  /*!< INPEN53 (Bitfield-Mask: 0x01)                         */
32063 #define GPIO_PINCFG53_FNCSEL53_Pos        (0UL)                     /*!< FNCSEL53 (Bit 0)                                      */
32064 #define GPIO_PINCFG53_FNCSEL53_Msk        (0xfUL)                   /*!< FNCSEL53 (Bitfield-Mask: 0x0f)                        */
32065 /* =======================================================  PINCFG54  ======================================================== */
32066 #define GPIO_PINCFG54_FOEN54_Pos          (27UL)                    /*!< FOEN54 (Bit 27)                                       */
32067 #define GPIO_PINCFG54_FOEN54_Msk          (0x8000000UL)             /*!< FOEN54 (Bitfield-Mask: 0x01)                          */
32068 #define GPIO_PINCFG54_FIEN54_Pos          (26UL)                    /*!< FIEN54 (Bit 26)                                       */
32069 #define GPIO_PINCFG54_FIEN54_Msk          (0x4000000UL)             /*!< FIEN54 (Bitfield-Mask: 0x01)                          */
32070 #define GPIO_PINCFG54_NCEPOL54_Pos        (22UL)                    /*!< NCEPOL54 (Bit 22)                                     */
32071 #define GPIO_PINCFG54_NCEPOL54_Msk        (0x400000UL)              /*!< NCEPOL54 (Bitfield-Mask: 0x01)                        */
32072 #define GPIO_PINCFG54_NCESRC54_Pos        (16UL)                    /*!< NCESRC54 (Bit 16)                                     */
32073 #define GPIO_PINCFG54_NCESRC54_Msk        (0x3f0000UL)              /*!< NCESRC54 (Bitfield-Mask: 0x3f)                        */
32074 #define GPIO_PINCFG54_PULLCFG54_Pos       (13UL)                    /*!< PULLCFG54 (Bit 13)                                    */
32075 #define GPIO_PINCFG54_PULLCFG54_Msk       (0xe000UL)                /*!< PULLCFG54 (Bitfield-Mask: 0x07)                       */
32076 #define GPIO_PINCFG54_SR54_Pos            (12UL)                    /*!< SR54 (Bit 12)                                         */
32077 #define GPIO_PINCFG54_SR54_Msk            (0x1000UL)                /*!< SR54 (Bitfield-Mask: 0x01)                            */
32078 #define GPIO_PINCFG54_DS54_Pos            (10UL)                    /*!< DS54 (Bit 10)                                         */
32079 #define GPIO_PINCFG54_DS54_Msk            (0xc00UL)                 /*!< DS54 (Bitfield-Mask: 0x03)                            */
32080 #define GPIO_PINCFG54_OUTCFG54_Pos        (8UL)                     /*!< OUTCFG54 (Bit 8)                                      */
32081 #define GPIO_PINCFG54_OUTCFG54_Msk        (0x300UL)                 /*!< OUTCFG54 (Bitfield-Mask: 0x03)                        */
32082 #define GPIO_PINCFG54_IRPTEN54_Pos        (6UL)                     /*!< IRPTEN54 (Bit 6)                                      */
32083 #define GPIO_PINCFG54_IRPTEN54_Msk        (0xc0UL)                  /*!< IRPTEN54 (Bitfield-Mask: 0x03)                        */
32084 #define GPIO_PINCFG54_RDZERO54_Pos        (5UL)                     /*!< RDZERO54 (Bit 5)                                      */
32085 #define GPIO_PINCFG54_RDZERO54_Msk        (0x20UL)                  /*!< RDZERO54 (Bitfield-Mask: 0x01)                        */
32086 #define GPIO_PINCFG54_INPEN54_Pos         (4UL)                     /*!< INPEN54 (Bit 4)                                       */
32087 #define GPIO_PINCFG54_INPEN54_Msk         (0x10UL)                  /*!< INPEN54 (Bitfield-Mask: 0x01)                         */
32088 #define GPIO_PINCFG54_FNCSEL54_Pos        (0UL)                     /*!< FNCSEL54 (Bit 0)                                      */
32089 #define GPIO_PINCFG54_FNCSEL54_Msk        (0xfUL)                   /*!< FNCSEL54 (Bitfield-Mask: 0x0f)                        */
32090 /* =======================================================  PINCFG55  ======================================================== */
32091 #define GPIO_PINCFG55_FOEN55_Pos          (27UL)                    /*!< FOEN55 (Bit 27)                                       */
32092 #define GPIO_PINCFG55_FOEN55_Msk          (0x8000000UL)             /*!< FOEN55 (Bitfield-Mask: 0x01)                          */
32093 #define GPIO_PINCFG55_FIEN55_Pos          (26UL)                    /*!< FIEN55 (Bit 26)                                       */
32094 #define GPIO_PINCFG55_FIEN55_Msk          (0x4000000UL)             /*!< FIEN55 (Bitfield-Mask: 0x01)                          */
32095 #define GPIO_PINCFG55_NCEPOL55_Pos        (22UL)                    /*!< NCEPOL55 (Bit 22)                                     */
32096 #define GPIO_PINCFG55_NCEPOL55_Msk        (0x400000UL)              /*!< NCEPOL55 (Bitfield-Mask: 0x01)                        */
32097 #define GPIO_PINCFG55_NCESRC55_Pos        (16UL)                    /*!< NCESRC55 (Bit 16)                                     */
32098 #define GPIO_PINCFG55_NCESRC55_Msk        (0x3f0000UL)              /*!< NCESRC55 (Bitfield-Mask: 0x3f)                        */
32099 #define GPIO_PINCFG55_PULLCFG55_Pos       (13UL)                    /*!< PULLCFG55 (Bit 13)                                    */
32100 #define GPIO_PINCFG55_PULLCFG55_Msk       (0xe000UL)                /*!< PULLCFG55 (Bitfield-Mask: 0x07)                       */
32101 #define GPIO_PINCFG55_SR55_Pos            (12UL)                    /*!< SR55 (Bit 12)                                         */
32102 #define GPIO_PINCFG55_SR55_Msk            (0x1000UL)                /*!< SR55 (Bitfield-Mask: 0x01)                            */
32103 #define GPIO_PINCFG55_DS55_Pos            (10UL)                    /*!< DS55 (Bit 10)                                         */
32104 #define GPIO_PINCFG55_DS55_Msk            (0xc00UL)                 /*!< DS55 (Bitfield-Mask: 0x03)                            */
32105 #define GPIO_PINCFG55_OUTCFG55_Pos        (8UL)                     /*!< OUTCFG55 (Bit 8)                                      */
32106 #define GPIO_PINCFG55_OUTCFG55_Msk        (0x300UL)                 /*!< OUTCFG55 (Bitfield-Mask: 0x03)                        */
32107 #define GPIO_PINCFG55_IRPTEN55_Pos        (6UL)                     /*!< IRPTEN55 (Bit 6)                                      */
32108 #define GPIO_PINCFG55_IRPTEN55_Msk        (0xc0UL)                  /*!< IRPTEN55 (Bitfield-Mask: 0x03)                        */
32109 #define GPIO_PINCFG55_RDZERO55_Pos        (5UL)                     /*!< RDZERO55 (Bit 5)                                      */
32110 #define GPIO_PINCFG55_RDZERO55_Msk        (0x20UL)                  /*!< RDZERO55 (Bitfield-Mask: 0x01)                        */
32111 #define GPIO_PINCFG55_INPEN55_Pos         (4UL)                     /*!< INPEN55 (Bit 4)                                       */
32112 #define GPIO_PINCFG55_INPEN55_Msk         (0x10UL)                  /*!< INPEN55 (Bitfield-Mask: 0x01)                         */
32113 #define GPIO_PINCFG55_FNCSEL55_Pos        (0UL)                     /*!< FNCSEL55 (Bit 0)                                      */
32114 #define GPIO_PINCFG55_FNCSEL55_Msk        (0xfUL)                   /*!< FNCSEL55 (Bitfield-Mask: 0x0f)                        */
32115 /* =======================================================  PINCFG56  ======================================================== */
32116 #define GPIO_PINCFG56_FOEN56_Pos          (27UL)                    /*!< FOEN56 (Bit 27)                                       */
32117 #define GPIO_PINCFG56_FOEN56_Msk          (0x8000000UL)             /*!< FOEN56 (Bitfield-Mask: 0x01)                          */
32118 #define GPIO_PINCFG56_FIEN56_Pos          (26UL)                    /*!< FIEN56 (Bit 26)                                       */
32119 #define GPIO_PINCFG56_FIEN56_Msk          (0x4000000UL)             /*!< FIEN56 (Bitfield-Mask: 0x01)                          */
32120 #define GPIO_PINCFG56_NCEPOL56_Pos        (22UL)                    /*!< NCEPOL56 (Bit 22)                                     */
32121 #define GPIO_PINCFG56_NCEPOL56_Msk        (0x400000UL)              /*!< NCEPOL56 (Bitfield-Mask: 0x01)                        */
32122 #define GPIO_PINCFG56_NCESRC56_Pos        (16UL)                    /*!< NCESRC56 (Bit 16)                                     */
32123 #define GPIO_PINCFG56_NCESRC56_Msk        (0x3f0000UL)              /*!< NCESRC56 (Bitfield-Mask: 0x3f)                        */
32124 #define GPIO_PINCFG56_PULLCFG56_Pos       (13UL)                    /*!< PULLCFG56 (Bit 13)                                    */
32125 #define GPIO_PINCFG56_PULLCFG56_Msk       (0xe000UL)                /*!< PULLCFG56 (Bitfield-Mask: 0x07)                       */
32126 #define GPIO_PINCFG56_SR56_Pos            (12UL)                    /*!< SR56 (Bit 12)                                         */
32127 #define GPIO_PINCFG56_SR56_Msk            (0x1000UL)                /*!< SR56 (Bitfield-Mask: 0x01)                            */
32128 #define GPIO_PINCFG56_DS56_Pos            (10UL)                    /*!< DS56 (Bit 10)                                         */
32129 #define GPIO_PINCFG56_DS56_Msk            (0xc00UL)                 /*!< DS56 (Bitfield-Mask: 0x03)                            */
32130 #define GPIO_PINCFG56_OUTCFG56_Pos        (8UL)                     /*!< OUTCFG56 (Bit 8)                                      */
32131 #define GPIO_PINCFG56_OUTCFG56_Msk        (0x300UL)                 /*!< OUTCFG56 (Bitfield-Mask: 0x03)                        */
32132 #define GPIO_PINCFG56_IRPTEN56_Pos        (6UL)                     /*!< IRPTEN56 (Bit 6)                                      */
32133 #define GPIO_PINCFG56_IRPTEN56_Msk        (0xc0UL)                  /*!< IRPTEN56 (Bitfield-Mask: 0x03)                        */
32134 #define GPIO_PINCFG56_RDZERO56_Pos        (5UL)                     /*!< RDZERO56 (Bit 5)                                      */
32135 #define GPIO_PINCFG56_RDZERO56_Msk        (0x20UL)                  /*!< RDZERO56 (Bitfield-Mask: 0x01)                        */
32136 #define GPIO_PINCFG56_INPEN56_Pos         (4UL)                     /*!< INPEN56 (Bit 4)                                       */
32137 #define GPIO_PINCFG56_INPEN56_Msk         (0x10UL)                  /*!< INPEN56 (Bitfield-Mask: 0x01)                         */
32138 #define GPIO_PINCFG56_FNCSEL56_Pos        (0UL)                     /*!< FNCSEL56 (Bit 0)                                      */
32139 #define GPIO_PINCFG56_FNCSEL56_Msk        (0xfUL)                   /*!< FNCSEL56 (Bitfield-Mask: 0x0f)                        */
32140 /* =======================================================  PINCFG57  ======================================================== */
32141 #define GPIO_PINCFG57_FOEN57_Pos          (27UL)                    /*!< FOEN57 (Bit 27)                                       */
32142 #define GPIO_PINCFG57_FOEN57_Msk          (0x8000000UL)             /*!< FOEN57 (Bitfield-Mask: 0x01)                          */
32143 #define GPIO_PINCFG57_FIEN57_Pos          (26UL)                    /*!< FIEN57 (Bit 26)                                       */
32144 #define GPIO_PINCFG57_FIEN57_Msk          (0x4000000UL)             /*!< FIEN57 (Bitfield-Mask: 0x01)                          */
32145 #define GPIO_PINCFG57_NCEPOL57_Pos        (22UL)                    /*!< NCEPOL57 (Bit 22)                                     */
32146 #define GPIO_PINCFG57_NCEPOL57_Msk        (0x400000UL)              /*!< NCEPOL57 (Bitfield-Mask: 0x01)                        */
32147 #define GPIO_PINCFG57_NCESRC57_Pos        (16UL)                    /*!< NCESRC57 (Bit 16)                                     */
32148 #define GPIO_PINCFG57_NCESRC57_Msk        (0x3f0000UL)              /*!< NCESRC57 (Bitfield-Mask: 0x3f)                        */
32149 #define GPIO_PINCFG57_PULLCFG57_Pos       (13UL)                    /*!< PULLCFG57 (Bit 13)                                    */
32150 #define GPIO_PINCFG57_PULLCFG57_Msk       (0xe000UL)                /*!< PULLCFG57 (Bitfield-Mask: 0x07)                       */
32151 #define GPIO_PINCFG57_SR57_Pos            (12UL)                    /*!< SR57 (Bit 12)                                         */
32152 #define GPIO_PINCFG57_SR57_Msk            (0x1000UL)                /*!< SR57 (Bitfield-Mask: 0x01)                            */
32153 #define GPIO_PINCFG57_DS57_Pos            (10UL)                    /*!< DS57 (Bit 10)                                         */
32154 #define GPIO_PINCFG57_DS57_Msk            (0xc00UL)                 /*!< DS57 (Bitfield-Mask: 0x03)                            */
32155 #define GPIO_PINCFG57_OUTCFG57_Pos        (8UL)                     /*!< OUTCFG57 (Bit 8)                                      */
32156 #define GPIO_PINCFG57_OUTCFG57_Msk        (0x300UL)                 /*!< OUTCFG57 (Bitfield-Mask: 0x03)                        */
32157 #define GPIO_PINCFG57_IRPTEN57_Pos        (6UL)                     /*!< IRPTEN57 (Bit 6)                                      */
32158 #define GPIO_PINCFG57_IRPTEN57_Msk        (0xc0UL)                  /*!< IRPTEN57 (Bitfield-Mask: 0x03)                        */
32159 #define GPIO_PINCFG57_RDZERO57_Pos        (5UL)                     /*!< RDZERO57 (Bit 5)                                      */
32160 #define GPIO_PINCFG57_RDZERO57_Msk        (0x20UL)                  /*!< RDZERO57 (Bitfield-Mask: 0x01)                        */
32161 #define GPIO_PINCFG57_INPEN57_Pos         (4UL)                     /*!< INPEN57 (Bit 4)                                       */
32162 #define GPIO_PINCFG57_INPEN57_Msk         (0x10UL)                  /*!< INPEN57 (Bitfield-Mask: 0x01)                         */
32163 #define GPIO_PINCFG57_FNCSEL57_Pos        (0UL)                     /*!< FNCSEL57 (Bit 0)                                      */
32164 #define GPIO_PINCFG57_FNCSEL57_Msk        (0xfUL)                   /*!< FNCSEL57 (Bitfield-Mask: 0x0f)                        */
32165 /* =======================================================  PINCFG58  ======================================================== */
32166 #define GPIO_PINCFG58_FOEN58_Pos          (27UL)                    /*!< FOEN58 (Bit 27)                                       */
32167 #define GPIO_PINCFG58_FOEN58_Msk          (0x8000000UL)             /*!< FOEN58 (Bitfield-Mask: 0x01)                          */
32168 #define GPIO_PINCFG58_FIEN58_Pos          (26UL)                    /*!< FIEN58 (Bit 26)                                       */
32169 #define GPIO_PINCFG58_FIEN58_Msk          (0x4000000UL)             /*!< FIEN58 (Bitfield-Mask: 0x01)                          */
32170 #define GPIO_PINCFG58_NCEPOL58_Pos        (22UL)                    /*!< NCEPOL58 (Bit 22)                                     */
32171 #define GPIO_PINCFG58_NCEPOL58_Msk        (0x400000UL)              /*!< NCEPOL58 (Bitfield-Mask: 0x01)                        */
32172 #define GPIO_PINCFG58_NCESRC58_Pos        (16UL)                    /*!< NCESRC58 (Bit 16)                                     */
32173 #define GPIO_PINCFG58_NCESRC58_Msk        (0x3f0000UL)              /*!< NCESRC58 (Bitfield-Mask: 0x3f)                        */
32174 #define GPIO_PINCFG58_PULLCFG58_Pos       (13UL)                    /*!< PULLCFG58 (Bit 13)                                    */
32175 #define GPIO_PINCFG58_PULLCFG58_Msk       (0xe000UL)                /*!< PULLCFG58 (Bitfield-Mask: 0x07)                       */
32176 #define GPIO_PINCFG58_SR58_Pos            (12UL)                    /*!< SR58 (Bit 12)                                         */
32177 #define GPIO_PINCFG58_SR58_Msk            (0x1000UL)                /*!< SR58 (Bitfield-Mask: 0x01)                            */
32178 #define GPIO_PINCFG58_DS58_Pos            (10UL)                    /*!< DS58 (Bit 10)                                         */
32179 #define GPIO_PINCFG58_DS58_Msk            (0xc00UL)                 /*!< DS58 (Bitfield-Mask: 0x03)                            */
32180 #define GPIO_PINCFG58_OUTCFG58_Pos        (8UL)                     /*!< OUTCFG58 (Bit 8)                                      */
32181 #define GPIO_PINCFG58_OUTCFG58_Msk        (0x300UL)                 /*!< OUTCFG58 (Bitfield-Mask: 0x03)                        */
32182 #define GPIO_PINCFG58_IRPTEN58_Pos        (6UL)                     /*!< IRPTEN58 (Bit 6)                                      */
32183 #define GPIO_PINCFG58_IRPTEN58_Msk        (0xc0UL)                  /*!< IRPTEN58 (Bitfield-Mask: 0x03)                        */
32184 #define GPIO_PINCFG58_RDZERO58_Pos        (5UL)                     /*!< RDZERO58 (Bit 5)                                      */
32185 #define GPIO_PINCFG58_RDZERO58_Msk        (0x20UL)                  /*!< RDZERO58 (Bitfield-Mask: 0x01)                        */
32186 #define GPIO_PINCFG58_INPEN58_Pos         (4UL)                     /*!< INPEN58 (Bit 4)                                       */
32187 #define GPIO_PINCFG58_INPEN58_Msk         (0x10UL)                  /*!< INPEN58 (Bitfield-Mask: 0x01)                         */
32188 #define GPIO_PINCFG58_FNCSEL58_Pos        (0UL)                     /*!< FNCSEL58 (Bit 0)                                      */
32189 #define GPIO_PINCFG58_FNCSEL58_Msk        (0xfUL)                   /*!< FNCSEL58 (Bitfield-Mask: 0x0f)                        */
32190 /* =======================================================  PINCFG59  ======================================================== */
32191 #define GPIO_PINCFG59_FOEN59_Pos          (27UL)                    /*!< FOEN59 (Bit 27)                                       */
32192 #define GPIO_PINCFG59_FOEN59_Msk          (0x8000000UL)             /*!< FOEN59 (Bitfield-Mask: 0x01)                          */
32193 #define GPIO_PINCFG59_FIEN59_Pos          (26UL)                    /*!< FIEN59 (Bit 26)                                       */
32194 #define GPIO_PINCFG59_FIEN59_Msk          (0x4000000UL)             /*!< FIEN59 (Bitfield-Mask: 0x01)                          */
32195 #define GPIO_PINCFG59_NCEPOL59_Pos        (22UL)                    /*!< NCEPOL59 (Bit 22)                                     */
32196 #define GPIO_PINCFG59_NCEPOL59_Msk        (0x400000UL)              /*!< NCEPOL59 (Bitfield-Mask: 0x01)                        */
32197 #define GPIO_PINCFG59_NCESRC59_Pos        (16UL)                    /*!< NCESRC59 (Bit 16)                                     */
32198 #define GPIO_PINCFG59_NCESRC59_Msk        (0x3f0000UL)              /*!< NCESRC59 (Bitfield-Mask: 0x3f)                        */
32199 #define GPIO_PINCFG59_PULLCFG59_Pos       (13UL)                    /*!< PULLCFG59 (Bit 13)                                    */
32200 #define GPIO_PINCFG59_PULLCFG59_Msk       (0xe000UL)                /*!< PULLCFG59 (Bitfield-Mask: 0x07)                       */
32201 #define GPIO_PINCFG59_SR59_Pos            (12UL)                    /*!< SR59 (Bit 12)                                         */
32202 #define GPIO_PINCFG59_SR59_Msk            (0x1000UL)                /*!< SR59 (Bitfield-Mask: 0x01)                            */
32203 #define GPIO_PINCFG59_DS59_Pos            (10UL)                    /*!< DS59 (Bit 10)                                         */
32204 #define GPIO_PINCFG59_DS59_Msk            (0xc00UL)                 /*!< DS59 (Bitfield-Mask: 0x03)                            */
32205 #define GPIO_PINCFG59_OUTCFG59_Pos        (8UL)                     /*!< OUTCFG59 (Bit 8)                                      */
32206 #define GPIO_PINCFG59_OUTCFG59_Msk        (0x300UL)                 /*!< OUTCFG59 (Bitfield-Mask: 0x03)                        */
32207 #define GPIO_PINCFG59_IRPTEN59_Pos        (6UL)                     /*!< IRPTEN59 (Bit 6)                                      */
32208 #define GPIO_PINCFG59_IRPTEN59_Msk        (0xc0UL)                  /*!< IRPTEN59 (Bitfield-Mask: 0x03)                        */
32209 #define GPIO_PINCFG59_RDZERO59_Pos        (5UL)                     /*!< RDZERO59 (Bit 5)                                      */
32210 #define GPIO_PINCFG59_RDZERO59_Msk        (0x20UL)                  /*!< RDZERO59 (Bitfield-Mask: 0x01)                        */
32211 #define GPIO_PINCFG59_INPEN59_Pos         (4UL)                     /*!< INPEN59 (Bit 4)                                       */
32212 #define GPIO_PINCFG59_INPEN59_Msk         (0x10UL)                  /*!< INPEN59 (Bitfield-Mask: 0x01)                         */
32213 #define GPIO_PINCFG59_FNCSEL59_Pos        (0UL)                     /*!< FNCSEL59 (Bit 0)                                      */
32214 #define GPIO_PINCFG59_FNCSEL59_Msk        (0xfUL)                   /*!< FNCSEL59 (Bitfield-Mask: 0x0f)                        */
32215 /* =======================================================  PINCFG60  ======================================================== */
32216 #define GPIO_PINCFG60_FOEN60_Pos          (27UL)                    /*!< FOEN60 (Bit 27)                                       */
32217 #define GPIO_PINCFG60_FOEN60_Msk          (0x8000000UL)             /*!< FOEN60 (Bitfield-Mask: 0x01)                          */
32218 #define GPIO_PINCFG60_FIEN60_Pos          (26UL)                    /*!< FIEN60 (Bit 26)                                       */
32219 #define GPIO_PINCFG60_FIEN60_Msk          (0x4000000UL)             /*!< FIEN60 (Bitfield-Mask: 0x01)                          */
32220 #define GPIO_PINCFG60_NCEPOL60_Pos        (22UL)                    /*!< NCEPOL60 (Bit 22)                                     */
32221 #define GPIO_PINCFG60_NCEPOL60_Msk        (0x400000UL)              /*!< NCEPOL60 (Bitfield-Mask: 0x01)                        */
32222 #define GPIO_PINCFG60_NCESRC60_Pos        (16UL)                    /*!< NCESRC60 (Bit 16)                                     */
32223 #define GPIO_PINCFG60_NCESRC60_Msk        (0x3f0000UL)              /*!< NCESRC60 (Bitfield-Mask: 0x3f)                        */
32224 #define GPIO_PINCFG60_PULLCFG60_Pos       (13UL)                    /*!< PULLCFG60 (Bit 13)                                    */
32225 #define GPIO_PINCFG60_PULLCFG60_Msk       (0xe000UL)                /*!< PULLCFG60 (Bitfield-Mask: 0x07)                       */
32226 #define GPIO_PINCFG60_SR60_Pos            (12UL)                    /*!< SR60 (Bit 12)                                         */
32227 #define GPIO_PINCFG60_SR60_Msk            (0x1000UL)                /*!< SR60 (Bitfield-Mask: 0x01)                            */
32228 #define GPIO_PINCFG60_DS60_Pos            (10UL)                    /*!< DS60 (Bit 10)                                         */
32229 #define GPIO_PINCFG60_DS60_Msk            (0xc00UL)                 /*!< DS60 (Bitfield-Mask: 0x03)                            */
32230 #define GPIO_PINCFG60_OUTCFG60_Pos        (8UL)                     /*!< OUTCFG60 (Bit 8)                                      */
32231 #define GPIO_PINCFG60_OUTCFG60_Msk        (0x300UL)                 /*!< OUTCFG60 (Bitfield-Mask: 0x03)                        */
32232 #define GPIO_PINCFG60_IRPTEN60_Pos        (6UL)                     /*!< IRPTEN60 (Bit 6)                                      */
32233 #define GPIO_PINCFG60_IRPTEN60_Msk        (0xc0UL)                  /*!< IRPTEN60 (Bitfield-Mask: 0x03)                        */
32234 #define GPIO_PINCFG60_RDZERO60_Pos        (5UL)                     /*!< RDZERO60 (Bit 5)                                      */
32235 #define GPIO_PINCFG60_RDZERO60_Msk        (0x20UL)                  /*!< RDZERO60 (Bitfield-Mask: 0x01)                        */
32236 #define GPIO_PINCFG60_INPEN60_Pos         (4UL)                     /*!< INPEN60 (Bit 4)                                       */
32237 #define GPIO_PINCFG60_INPEN60_Msk         (0x10UL)                  /*!< INPEN60 (Bitfield-Mask: 0x01)                         */
32238 #define GPIO_PINCFG60_FNCSEL60_Pos        (0UL)                     /*!< FNCSEL60 (Bit 0)                                      */
32239 #define GPIO_PINCFG60_FNCSEL60_Msk        (0xfUL)                   /*!< FNCSEL60 (Bitfield-Mask: 0x0f)                        */
32240 /* =======================================================  PINCFG61  ======================================================== */
32241 #define GPIO_PINCFG61_FOEN61_Pos          (27UL)                    /*!< FOEN61 (Bit 27)                                       */
32242 #define GPIO_PINCFG61_FOEN61_Msk          (0x8000000UL)             /*!< FOEN61 (Bitfield-Mask: 0x01)                          */
32243 #define GPIO_PINCFG61_FIEN61_Pos          (26UL)                    /*!< FIEN61 (Bit 26)                                       */
32244 #define GPIO_PINCFG61_FIEN61_Msk          (0x4000000UL)             /*!< FIEN61 (Bitfield-Mask: 0x01)                          */
32245 #define GPIO_PINCFG61_NCEPOL61_Pos        (22UL)                    /*!< NCEPOL61 (Bit 22)                                     */
32246 #define GPIO_PINCFG61_NCEPOL61_Msk        (0x400000UL)              /*!< NCEPOL61 (Bitfield-Mask: 0x01)                        */
32247 #define GPIO_PINCFG61_NCESRC61_Pos        (16UL)                    /*!< NCESRC61 (Bit 16)                                     */
32248 #define GPIO_PINCFG61_NCESRC61_Msk        (0x3f0000UL)              /*!< NCESRC61 (Bitfield-Mask: 0x3f)                        */
32249 #define GPIO_PINCFG61_PULLCFG61_Pos       (13UL)                    /*!< PULLCFG61 (Bit 13)                                    */
32250 #define GPIO_PINCFG61_PULLCFG61_Msk       (0xe000UL)                /*!< PULLCFG61 (Bitfield-Mask: 0x07)                       */
32251 #define GPIO_PINCFG61_SR61_Pos            (12UL)                    /*!< SR61 (Bit 12)                                         */
32252 #define GPIO_PINCFG61_SR61_Msk            (0x1000UL)                /*!< SR61 (Bitfield-Mask: 0x01)                            */
32253 #define GPIO_PINCFG61_DS61_Pos            (10UL)                    /*!< DS61 (Bit 10)                                         */
32254 #define GPIO_PINCFG61_DS61_Msk            (0xc00UL)                 /*!< DS61 (Bitfield-Mask: 0x03)                            */
32255 #define GPIO_PINCFG61_OUTCFG61_Pos        (8UL)                     /*!< OUTCFG61 (Bit 8)                                      */
32256 #define GPIO_PINCFG61_OUTCFG61_Msk        (0x300UL)                 /*!< OUTCFG61 (Bitfield-Mask: 0x03)                        */
32257 #define GPIO_PINCFG61_IRPTEN61_Pos        (6UL)                     /*!< IRPTEN61 (Bit 6)                                      */
32258 #define GPIO_PINCFG61_IRPTEN61_Msk        (0xc0UL)                  /*!< IRPTEN61 (Bitfield-Mask: 0x03)                        */
32259 #define GPIO_PINCFG61_RDZERO61_Pos        (5UL)                     /*!< RDZERO61 (Bit 5)                                      */
32260 #define GPIO_PINCFG61_RDZERO61_Msk        (0x20UL)                  /*!< RDZERO61 (Bitfield-Mask: 0x01)                        */
32261 #define GPIO_PINCFG61_INPEN61_Pos         (4UL)                     /*!< INPEN61 (Bit 4)                                       */
32262 #define GPIO_PINCFG61_INPEN61_Msk         (0x10UL)                  /*!< INPEN61 (Bitfield-Mask: 0x01)                         */
32263 #define GPIO_PINCFG61_FNCSEL61_Pos        (0UL)                     /*!< FNCSEL61 (Bit 0)                                      */
32264 #define GPIO_PINCFG61_FNCSEL61_Msk        (0xfUL)                   /*!< FNCSEL61 (Bitfield-Mask: 0x0f)                        */
32265 /* =======================================================  PINCFG62  ======================================================== */
32266 #define GPIO_PINCFG62_FOEN62_Pos          (27UL)                    /*!< FOEN62 (Bit 27)                                       */
32267 #define GPIO_PINCFG62_FOEN62_Msk          (0x8000000UL)             /*!< FOEN62 (Bitfield-Mask: 0x01)                          */
32268 #define GPIO_PINCFG62_FIEN62_Pos          (26UL)                    /*!< FIEN62 (Bit 26)                                       */
32269 #define GPIO_PINCFG62_FIEN62_Msk          (0x4000000UL)             /*!< FIEN62 (Bitfield-Mask: 0x01)                          */
32270 #define GPIO_PINCFG62_NCEPOL62_Pos        (22UL)                    /*!< NCEPOL62 (Bit 22)                                     */
32271 #define GPIO_PINCFG62_NCEPOL62_Msk        (0x400000UL)              /*!< NCEPOL62 (Bitfield-Mask: 0x01)                        */
32272 #define GPIO_PINCFG62_NCESRC62_Pos        (16UL)                    /*!< NCESRC62 (Bit 16)                                     */
32273 #define GPIO_PINCFG62_NCESRC62_Msk        (0x3f0000UL)              /*!< NCESRC62 (Bitfield-Mask: 0x3f)                        */
32274 #define GPIO_PINCFG62_PULLCFG62_Pos       (13UL)                    /*!< PULLCFG62 (Bit 13)                                    */
32275 #define GPIO_PINCFG62_PULLCFG62_Msk       (0xe000UL)                /*!< PULLCFG62 (Bitfield-Mask: 0x07)                       */
32276 #define GPIO_PINCFG62_SR62_Pos            (12UL)                    /*!< SR62 (Bit 12)                                         */
32277 #define GPIO_PINCFG62_SR62_Msk            (0x1000UL)                /*!< SR62 (Bitfield-Mask: 0x01)                            */
32278 #define GPIO_PINCFG62_DS62_Pos            (10UL)                    /*!< DS62 (Bit 10)                                         */
32279 #define GPIO_PINCFG62_DS62_Msk            (0xc00UL)                 /*!< DS62 (Bitfield-Mask: 0x03)                            */
32280 #define GPIO_PINCFG62_OUTCFG62_Pos        (8UL)                     /*!< OUTCFG62 (Bit 8)                                      */
32281 #define GPIO_PINCFG62_OUTCFG62_Msk        (0x300UL)                 /*!< OUTCFG62 (Bitfield-Mask: 0x03)                        */
32282 #define GPIO_PINCFG62_IRPTEN62_Pos        (6UL)                     /*!< IRPTEN62 (Bit 6)                                      */
32283 #define GPIO_PINCFG62_IRPTEN62_Msk        (0xc0UL)                  /*!< IRPTEN62 (Bitfield-Mask: 0x03)                        */
32284 #define GPIO_PINCFG62_RDZERO62_Pos        (5UL)                     /*!< RDZERO62 (Bit 5)                                      */
32285 #define GPIO_PINCFG62_RDZERO62_Msk        (0x20UL)                  /*!< RDZERO62 (Bitfield-Mask: 0x01)                        */
32286 #define GPIO_PINCFG62_INPEN62_Pos         (4UL)                     /*!< INPEN62 (Bit 4)                                       */
32287 #define GPIO_PINCFG62_INPEN62_Msk         (0x10UL)                  /*!< INPEN62 (Bitfield-Mask: 0x01)                         */
32288 #define GPIO_PINCFG62_FNCSEL62_Pos        (0UL)                     /*!< FNCSEL62 (Bit 0)                                      */
32289 #define GPIO_PINCFG62_FNCSEL62_Msk        (0xfUL)                   /*!< FNCSEL62 (Bitfield-Mask: 0x0f)                        */
32290 /* =======================================================  PINCFG63  ======================================================== */
32291 #define GPIO_PINCFG63_FOEN63_Pos          (27UL)                    /*!< FOEN63 (Bit 27)                                       */
32292 #define GPIO_PINCFG63_FOEN63_Msk          (0x8000000UL)             /*!< FOEN63 (Bitfield-Mask: 0x01)                          */
32293 #define GPIO_PINCFG63_FIEN63_Pos          (26UL)                    /*!< FIEN63 (Bit 26)                                       */
32294 #define GPIO_PINCFG63_FIEN63_Msk          (0x4000000UL)             /*!< FIEN63 (Bitfield-Mask: 0x01)                          */
32295 #define GPIO_PINCFG63_NCEPOL63_Pos        (22UL)                    /*!< NCEPOL63 (Bit 22)                                     */
32296 #define GPIO_PINCFG63_NCEPOL63_Msk        (0x400000UL)              /*!< NCEPOL63 (Bitfield-Mask: 0x01)                        */
32297 #define GPIO_PINCFG63_NCESRC63_Pos        (16UL)                    /*!< NCESRC63 (Bit 16)                                     */
32298 #define GPIO_PINCFG63_NCESRC63_Msk        (0x3f0000UL)              /*!< NCESRC63 (Bitfield-Mask: 0x3f)                        */
32299 #define GPIO_PINCFG63_PULLCFG63_Pos       (13UL)                    /*!< PULLCFG63 (Bit 13)                                    */
32300 #define GPIO_PINCFG63_PULLCFG63_Msk       (0xe000UL)                /*!< PULLCFG63 (Bitfield-Mask: 0x07)                       */
32301 #define GPIO_PINCFG63_SR63_Pos            (12UL)                    /*!< SR63 (Bit 12)                                         */
32302 #define GPIO_PINCFG63_SR63_Msk            (0x1000UL)                /*!< SR63 (Bitfield-Mask: 0x01)                            */
32303 #define GPIO_PINCFG63_DS63_Pos            (10UL)                    /*!< DS63 (Bit 10)                                         */
32304 #define GPIO_PINCFG63_DS63_Msk            (0xc00UL)                 /*!< DS63 (Bitfield-Mask: 0x03)                            */
32305 #define GPIO_PINCFG63_OUTCFG63_Pos        (8UL)                     /*!< OUTCFG63 (Bit 8)                                      */
32306 #define GPIO_PINCFG63_OUTCFG63_Msk        (0x300UL)                 /*!< OUTCFG63 (Bitfield-Mask: 0x03)                        */
32307 #define GPIO_PINCFG63_IRPTEN63_Pos        (6UL)                     /*!< IRPTEN63 (Bit 6)                                      */
32308 #define GPIO_PINCFG63_IRPTEN63_Msk        (0xc0UL)                  /*!< IRPTEN63 (Bitfield-Mask: 0x03)                        */
32309 #define GPIO_PINCFG63_RDZERO63_Pos        (5UL)                     /*!< RDZERO63 (Bit 5)                                      */
32310 #define GPIO_PINCFG63_RDZERO63_Msk        (0x20UL)                  /*!< RDZERO63 (Bitfield-Mask: 0x01)                        */
32311 #define GPIO_PINCFG63_INPEN63_Pos         (4UL)                     /*!< INPEN63 (Bit 4)                                       */
32312 #define GPIO_PINCFG63_INPEN63_Msk         (0x10UL)                  /*!< INPEN63 (Bitfield-Mask: 0x01)                         */
32313 #define GPIO_PINCFG63_FNCSEL63_Pos        (0UL)                     /*!< FNCSEL63 (Bit 0)                                      */
32314 #define GPIO_PINCFG63_FNCSEL63_Msk        (0xfUL)                   /*!< FNCSEL63 (Bitfield-Mask: 0x0f)                        */
32315 /* =======================================================  PINCFG64  ======================================================== */
32316 #define GPIO_PINCFG64_FOEN64_Pos          (27UL)                    /*!< FOEN64 (Bit 27)                                       */
32317 #define GPIO_PINCFG64_FOEN64_Msk          (0x8000000UL)             /*!< FOEN64 (Bitfield-Mask: 0x01)                          */
32318 #define GPIO_PINCFG64_FIEN64_Pos          (26UL)                    /*!< FIEN64 (Bit 26)                                       */
32319 #define GPIO_PINCFG64_FIEN64_Msk          (0x4000000UL)             /*!< FIEN64 (Bitfield-Mask: 0x01)                          */
32320 #define GPIO_PINCFG64_NCEPOL64_Pos        (22UL)                    /*!< NCEPOL64 (Bit 22)                                     */
32321 #define GPIO_PINCFG64_NCEPOL64_Msk        (0x400000UL)              /*!< NCEPOL64 (Bitfield-Mask: 0x01)                        */
32322 #define GPIO_PINCFG64_NCESRC64_Pos        (16UL)                    /*!< NCESRC64 (Bit 16)                                     */
32323 #define GPIO_PINCFG64_NCESRC64_Msk        (0x3f0000UL)              /*!< NCESRC64 (Bitfield-Mask: 0x3f)                        */
32324 #define GPIO_PINCFG64_PULLCFG64_Pos       (13UL)                    /*!< PULLCFG64 (Bit 13)                                    */
32325 #define GPIO_PINCFG64_PULLCFG64_Msk       (0xe000UL)                /*!< PULLCFG64 (Bitfield-Mask: 0x07)                       */
32326 #define GPIO_PINCFG64_SR64_Pos            (12UL)                    /*!< SR64 (Bit 12)                                         */
32327 #define GPIO_PINCFG64_SR64_Msk            (0x1000UL)                /*!< SR64 (Bitfield-Mask: 0x01)                            */
32328 #define GPIO_PINCFG64_DS64_Pos            (10UL)                    /*!< DS64 (Bit 10)                                         */
32329 #define GPIO_PINCFG64_DS64_Msk            (0xc00UL)                 /*!< DS64 (Bitfield-Mask: 0x03)                            */
32330 #define GPIO_PINCFG64_OUTCFG64_Pos        (8UL)                     /*!< OUTCFG64 (Bit 8)                                      */
32331 #define GPIO_PINCFG64_OUTCFG64_Msk        (0x300UL)                 /*!< OUTCFG64 (Bitfield-Mask: 0x03)                        */
32332 #define GPIO_PINCFG64_IRPTEN64_Pos        (6UL)                     /*!< IRPTEN64 (Bit 6)                                      */
32333 #define GPIO_PINCFG64_IRPTEN64_Msk        (0xc0UL)                  /*!< IRPTEN64 (Bitfield-Mask: 0x03)                        */
32334 #define GPIO_PINCFG64_RDZERO64_Pos        (5UL)                     /*!< RDZERO64 (Bit 5)                                      */
32335 #define GPIO_PINCFG64_RDZERO64_Msk        (0x20UL)                  /*!< RDZERO64 (Bitfield-Mask: 0x01)                        */
32336 #define GPIO_PINCFG64_INPEN64_Pos         (4UL)                     /*!< INPEN64 (Bit 4)                                       */
32337 #define GPIO_PINCFG64_INPEN64_Msk         (0x10UL)                  /*!< INPEN64 (Bitfield-Mask: 0x01)                         */
32338 #define GPIO_PINCFG64_FNCSEL64_Pos        (0UL)                     /*!< FNCSEL64 (Bit 0)                                      */
32339 #define GPIO_PINCFG64_FNCSEL64_Msk        (0xfUL)                   /*!< FNCSEL64 (Bitfield-Mask: 0x0f)                        */
32340 /* =======================================================  PINCFG65  ======================================================== */
32341 #define GPIO_PINCFG65_FOEN65_Pos          (27UL)                    /*!< FOEN65 (Bit 27)                                       */
32342 #define GPIO_PINCFG65_FOEN65_Msk          (0x8000000UL)             /*!< FOEN65 (Bitfield-Mask: 0x01)                          */
32343 #define GPIO_PINCFG65_FIEN65_Pos          (26UL)                    /*!< FIEN65 (Bit 26)                                       */
32344 #define GPIO_PINCFG65_FIEN65_Msk          (0x4000000UL)             /*!< FIEN65 (Bitfield-Mask: 0x01)                          */
32345 #define GPIO_PINCFG65_NCEPOL65_Pos        (22UL)                    /*!< NCEPOL65 (Bit 22)                                     */
32346 #define GPIO_PINCFG65_NCEPOL65_Msk        (0x400000UL)              /*!< NCEPOL65 (Bitfield-Mask: 0x01)                        */
32347 #define GPIO_PINCFG65_NCESRC65_Pos        (16UL)                    /*!< NCESRC65 (Bit 16)                                     */
32348 #define GPIO_PINCFG65_NCESRC65_Msk        (0x3f0000UL)              /*!< NCESRC65 (Bitfield-Mask: 0x3f)                        */
32349 #define GPIO_PINCFG65_PULLCFG65_Pos       (13UL)                    /*!< PULLCFG65 (Bit 13)                                    */
32350 #define GPIO_PINCFG65_PULLCFG65_Msk       (0xe000UL)                /*!< PULLCFG65 (Bitfield-Mask: 0x07)                       */
32351 #define GPIO_PINCFG65_SR65_Pos            (12UL)                    /*!< SR65 (Bit 12)                                         */
32352 #define GPIO_PINCFG65_SR65_Msk            (0x1000UL)                /*!< SR65 (Bitfield-Mask: 0x01)                            */
32353 #define GPIO_PINCFG65_DS65_Pos            (10UL)                    /*!< DS65 (Bit 10)                                         */
32354 #define GPIO_PINCFG65_DS65_Msk            (0xc00UL)                 /*!< DS65 (Bitfield-Mask: 0x03)                            */
32355 #define GPIO_PINCFG65_OUTCFG65_Pos        (8UL)                     /*!< OUTCFG65 (Bit 8)                                      */
32356 #define GPIO_PINCFG65_OUTCFG65_Msk        (0x300UL)                 /*!< OUTCFG65 (Bitfield-Mask: 0x03)                        */
32357 #define GPIO_PINCFG65_IRPTEN65_Pos        (6UL)                     /*!< IRPTEN65 (Bit 6)                                      */
32358 #define GPIO_PINCFG65_IRPTEN65_Msk        (0xc0UL)                  /*!< IRPTEN65 (Bitfield-Mask: 0x03)                        */
32359 #define GPIO_PINCFG65_RDZERO65_Pos        (5UL)                     /*!< RDZERO65 (Bit 5)                                      */
32360 #define GPIO_PINCFG65_RDZERO65_Msk        (0x20UL)                  /*!< RDZERO65 (Bitfield-Mask: 0x01)                        */
32361 #define GPIO_PINCFG65_INPEN65_Pos         (4UL)                     /*!< INPEN65 (Bit 4)                                       */
32362 #define GPIO_PINCFG65_INPEN65_Msk         (0x10UL)                  /*!< INPEN65 (Bitfield-Mask: 0x01)                         */
32363 #define GPIO_PINCFG65_FNCSEL65_Pos        (0UL)                     /*!< FNCSEL65 (Bit 0)                                      */
32364 #define GPIO_PINCFG65_FNCSEL65_Msk        (0xfUL)                   /*!< FNCSEL65 (Bitfield-Mask: 0x0f)                        */
32365 /* =======================================================  PINCFG66  ======================================================== */
32366 #define GPIO_PINCFG66_FOEN66_Pos          (27UL)                    /*!< FOEN66 (Bit 27)                                       */
32367 #define GPIO_PINCFG66_FOEN66_Msk          (0x8000000UL)             /*!< FOEN66 (Bitfield-Mask: 0x01)                          */
32368 #define GPIO_PINCFG66_FIEN66_Pos          (26UL)                    /*!< FIEN66 (Bit 26)                                       */
32369 #define GPIO_PINCFG66_FIEN66_Msk          (0x4000000UL)             /*!< FIEN66 (Bitfield-Mask: 0x01)                          */
32370 #define GPIO_PINCFG66_NCEPOL66_Pos        (22UL)                    /*!< NCEPOL66 (Bit 22)                                     */
32371 #define GPIO_PINCFG66_NCEPOL66_Msk        (0x400000UL)              /*!< NCEPOL66 (Bitfield-Mask: 0x01)                        */
32372 #define GPIO_PINCFG66_NCESRC66_Pos        (16UL)                    /*!< NCESRC66 (Bit 16)                                     */
32373 #define GPIO_PINCFG66_NCESRC66_Msk        (0x3f0000UL)              /*!< NCESRC66 (Bitfield-Mask: 0x3f)                        */
32374 #define GPIO_PINCFG66_PULLCFG66_Pos       (13UL)                    /*!< PULLCFG66 (Bit 13)                                    */
32375 #define GPIO_PINCFG66_PULLCFG66_Msk       (0xe000UL)                /*!< PULLCFG66 (Bitfield-Mask: 0x07)                       */
32376 #define GPIO_PINCFG66_SR66_Pos            (12UL)                    /*!< SR66 (Bit 12)                                         */
32377 #define GPIO_PINCFG66_SR66_Msk            (0x1000UL)                /*!< SR66 (Bitfield-Mask: 0x01)                            */
32378 #define GPIO_PINCFG66_DS66_Pos            (10UL)                    /*!< DS66 (Bit 10)                                         */
32379 #define GPIO_PINCFG66_DS66_Msk            (0xc00UL)                 /*!< DS66 (Bitfield-Mask: 0x03)                            */
32380 #define GPIO_PINCFG66_OUTCFG66_Pos        (8UL)                     /*!< OUTCFG66 (Bit 8)                                      */
32381 #define GPIO_PINCFG66_OUTCFG66_Msk        (0x300UL)                 /*!< OUTCFG66 (Bitfield-Mask: 0x03)                        */
32382 #define GPIO_PINCFG66_IRPTEN66_Pos        (6UL)                     /*!< IRPTEN66 (Bit 6)                                      */
32383 #define GPIO_PINCFG66_IRPTEN66_Msk        (0xc0UL)                  /*!< IRPTEN66 (Bitfield-Mask: 0x03)                        */
32384 #define GPIO_PINCFG66_RDZERO66_Pos        (5UL)                     /*!< RDZERO66 (Bit 5)                                      */
32385 #define GPIO_PINCFG66_RDZERO66_Msk        (0x20UL)                  /*!< RDZERO66 (Bitfield-Mask: 0x01)                        */
32386 #define GPIO_PINCFG66_INPEN66_Pos         (4UL)                     /*!< INPEN66 (Bit 4)                                       */
32387 #define GPIO_PINCFG66_INPEN66_Msk         (0x10UL)                  /*!< INPEN66 (Bitfield-Mask: 0x01)                         */
32388 #define GPIO_PINCFG66_FNCSEL66_Pos        (0UL)                     /*!< FNCSEL66 (Bit 0)                                      */
32389 #define GPIO_PINCFG66_FNCSEL66_Msk        (0xfUL)                   /*!< FNCSEL66 (Bitfield-Mask: 0x0f)                        */
32390 /* =======================================================  PINCFG67  ======================================================== */
32391 #define GPIO_PINCFG67_FOEN67_Pos          (27UL)                    /*!< FOEN67 (Bit 27)                                       */
32392 #define GPIO_PINCFG67_FOEN67_Msk          (0x8000000UL)             /*!< FOEN67 (Bitfield-Mask: 0x01)                          */
32393 #define GPIO_PINCFG67_FIEN67_Pos          (26UL)                    /*!< FIEN67 (Bit 26)                                       */
32394 #define GPIO_PINCFG67_FIEN67_Msk          (0x4000000UL)             /*!< FIEN67 (Bitfield-Mask: 0x01)                          */
32395 #define GPIO_PINCFG67_NCEPOL67_Pos        (22UL)                    /*!< NCEPOL67 (Bit 22)                                     */
32396 #define GPIO_PINCFG67_NCEPOL67_Msk        (0x400000UL)              /*!< NCEPOL67 (Bitfield-Mask: 0x01)                        */
32397 #define GPIO_PINCFG67_NCESRC67_Pos        (16UL)                    /*!< NCESRC67 (Bit 16)                                     */
32398 #define GPIO_PINCFG67_NCESRC67_Msk        (0x3f0000UL)              /*!< NCESRC67 (Bitfield-Mask: 0x3f)                        */
32399 #define GPIO_PINCFG67_PULLCFG67_Pos       (13UL)                    /*!< PULLCFG67 (Bit 13)                                    */
32400 #define GPIO_PINCFG67_PULLCFG67_Msk       (0xe000UL)                /*!< PULLCFG67 (Bitfield-Mask: 0x07)                       */
32401 #define GPIO_PINCFG67_SR67_Pos            (12UL)                    /*!< SR67 (Bit 12)                                         */
32402 #define GPIO_PINCFG67_SR67_Msk            (0x1000UL)                /*!< SR67 (Bitfield-Mask: 0x01)                            */
32403 #define GPIO_PINCFG67_DS67_Pos            (10UL)                    /*!< DS67 (Bit 10)                                         */
32404 #define GPIO_PINCFG67_DS67_Msk            (0xc00UL)                 /*!< DS67 (Bitfield-Mask: 0x03)                            */
32405 #define GPIO_PINCFG67_OUTCFG67_Pos        (8UL)                     /*!< OUTCFG67 (Bit 8)                                      */
32406 #define GPIO_PINCFG67_OUTCFG67_Msk        (0x300UL)                 /*!< OUTCFG67 (Bitfield-Mask: 0x03)                        */
32407 #define GPIO_PINCFG67_IRPTEN67_Pos        (6UL)                     /*!< IRPTEN67 (Bit 6)                                      */
32408 #define GPIO_PINCFG67_IRPTEN67_Msk        (0xc0UL)                  /*!< IRPTEN67 (Bitfield-Mask: 0x03)                        */
32409 #define GPIO_PINCFG67_RDZERO67_Pos        (5UL)                     /*!< RDZERO67 (Bit 5)                                      */
32410 #define GPIO_PINCFG67_RDZERO67_Msk        (0x20UL)                  /*!< RDZERO67 (Bitfield-Mask: 0x01)                        */
32411 #define GPIO_PINCFG67_INPEN67_Pos         (4UL)                     /*!< INPEN67 (Bit 4)                                       */
32412 #define GPIO_PINCFG67_INPEN67_Msk         (0x10UL)                  /*!< INPEN67 (Bitfield-Mask: 0x01)                         */
32413 #define GPIO_PINCFG67_FNCSEL67_Pos        (0UL)                     /*!< FNCSEL67 (Bit 0)                                      */
32414 #define GPIO_PINCFG67_FNCSEL67_Msk        (0xfUL)                   /*!< FNCSEL67 (Bitfield-Mask: 0x0f)                        */
32415 /* =======================================================  PINCFG68  ======================================================== */
32416 #define GPIO_PINCFG68_FOEN68_Pos          (27UL)                    /*!< FOEN68 (Bit 27)                                       */
32417 #define GPIO_PINCFG68_FOEN68_Msk          (0x8000000UL)             /*!< FOEN68 (Bitfield-Mask: 0x01)                          */
32418 #define GPIO_PINCFG68_FIEN68_Pos          (26UL)                    /*!< FIEN68 (Bit 26)                                       */
32419 #define GPIO_PINCFG68_FIEN68_Msk          (0x4000000UL)             /*!< FIEN68 (Bitfield-Mask: 0x01)                          */
32420 #define GPIO_PINCFG68_NCEPOL68_Pos        (22UL)                    /*!< NCEPOL68 (Bit 22)                                     */
32421 #define GPIO_PINCFG68_NCEPOL68_Msk        (0x400000UL)              /*!< NCEPOL68 (Bitfield-Mask: 0x01)                        */
32422 #define GPIO_PINCFG68_NCESRC68_Pos        (16UL)                    /*!< NCESRC68 (Bit 16)                                     */
32423 #define GPIO_PINCFG68_NCESRC68_Msk        (0x3f0000UL)              /*!< NCESRC68 (Bitfield-Mask: 0x3f)                        */
32424 #define GPIO_PINCFG68_PULLCFG68_Pos       (13UL)                    /*!< PULLCFG68 (Bit 13)                                    */
32425 #define GPIO_PINCFG68_PULLCFG68_Msk       (0xe000UL)                /*!< PULLCFG68 (Bitfield-Mask: 0x07)                       */
32426 #define GPIO_PINCFG68_SR68_Pos            (12UL)                    /*!< SR68 (Bit 12)                                         */
32427 #define GPIO_PINCFG68_SR68_Msk            (0x1000UL)                /*!< SR68 (Bitfield-Mask: 0x01)                            */
32428 #define GPIO_PINCFG68_DS68_Pos            (10UL)                    /*!< DS68 (Bit 10)                                         */
32429 #define GPIO_PINCFG68_DS68_Msk            (0xc00UL)                 /*!< DS68 (Bitfield-Mask: 0x03)                            */
32430 #define GPIO_PINCFG68_OUTCFG68_Pos        (8UL)                     /*!< OUTCFG68 (Bit 8)                                      */
32431 #define GPIO_PINCFG68_OUTCFG68_Msk        (0x300UL)                 /*!< OUTCFG68 (Bitfield-Mask: 0x03)                        */
32432 #define GPIO_PINCFG68_IRPTEN68_Pos        (6UL)                     /*!< IRPTEN68 (Bit 6)                                      */
32433 #define GPIO_PINCFG68_IRPTEN68_Msk        (0xc0UL)                  /*!< IRPTEN68 (Bitfield-Mask: 0x03)                        */
32434 #define GPIO_PINCFG68_RDZERO68_Pos        (5UL)                     /*!< RDZERO68 (Bit 5)                                      */
32435 #define GPIO_PINCFG68_RDZERO68_Msk        (0x20UL)                  /*!< RDZERO68 (Bitfield-Mask: 0x01)                        */
32436 #define GPIO_PINCFG68_INPEN68_Pos         (4UL)                     /*!< INPEN68 (Bit 4)                                       */
32437 #define GPIO_PINCFG68_INPEN68_Msk         (0x10UL)                  /*!< INPEN68 (Bitfield-Mask: 0x01)                         */
32438 #define GPIO_PINCFG68_FNCSEL68_Pos        (0UL)                     /*!< FNCSEL68 (Bit 0)                                      */
32439 #define GPIO_PINCFG68_FNCSEL68_Msk        (0xfUL)                   /*!< FNCSEL68 (Bitfield-Mask: 0x0f)                        */
32440 /* =======================================================  PINCFG69  ======================================================== */
32441 #define GPIO_PINCFG69_FOEN69_Pos          (27UL)                    /*!< FOEN69 (Bit 27)                                       */
32442 #define GPIO_PINCFG69_FOEN69_Msk          (0x8000000UL)             /*!< FOEN69 (Bitfield-Mask: 0x01)                          */
32443 #define GPIO_PINCFG69_FIEN69_Pos          (26UL)                    /*!< FIEN69 (Bit 26)                                       */
32444 #define GPIO_PINCFG69_FIEN69_Msk          (0x4000000UL)             /*!< FIEN69 (Bitfield-Mask: 0x01)                          */
32445 #define GPIO_PINCFG69_NCEPOL69_Pos        (22UL)                    /*!< NCEPOL69 (Bit 22)                                     */
32446 #define GPIO_PINCFG69_NCEPOL69_Msk        (0x400000UL)              /*!< NCEPOL69 (Bitfield-Mask: 0x01)                        */
32447 #define GPIO_PINCFG69_NCESRC69_Pos        (16UL)                    /*!< NCESRC69 (Bit 16)                                     */
32448 #define GPIO_PINCFG69_NCESRC69_Msk        (0x3f0000UL)              /*!< NCESRC69 (Bitfield-Mask: 0x3f)                        */
32449 #define GPIO_PINCFG69_PULLCFG69_Pos       (13UL)                    /*!< PULLCFG69 (Bit 13)                                    */
32450 #define GPIO_PINCFG69_PULLCFG69_Msk       (0xe000UL)                /*!< PULLCFG69 (Bitfield-Mask: 0x07)                       */
32451 #define GPIO_PINCFG69_SR69_Pos            (12UL)                    /*!< SR69 (Bit 12)                                         */
32452 #define GPIO_PINCFG69_SR69_Msk            (0x1000UL)                /*!< SR69 (Bitfield-Mask: 0x01)                            */
32453 #define GPIO_PINCFG69_DS69_Pos            (10UL)                    /*!< DS69 (Bit 10)                                         */
32454 #define GPIO_PINCFG69_DS69_Msk            (0xc00UL)                 /*!< DS69 (Bitfield-Mask: 0x03)                            */
32455 #define GPIO_PINCFG69_OUTCFG69_Pos        (8UL)                     /*!< OUTCFG69 (Bit 8)                                      */
32456 #define GPIO_PINCFG69_OUTCFG69_Msk        (0x300UL)                 /*!< OUTCFG69 (Bitfield-Mask: 0x03)                        */
32457 #define GPIO_PINCFG69_IRPTEN69_Pos        (6UL)                     /*!< IRPTEN69 (Bit 6)                                      */
32458 #define GPIO_PINCFG69_IRPTEN69_Msk        (0xc0UL)                  /*!< IRPTEN69 (Bitfield-Mask: 0x03)                        */
32459 #define GPIO_PINCFG69_RDZERO69_Pos        (5UL)                     /*!< RDZERO69 (Bit 5)                                      */
32460 #define GPIO_PINCFG69_RDZERO69_Msk        (0x20UL)                  /*!< RDZERO69 (Bitfield-Mask: 0x01)                        */
32461 #define GPIO_PINCFG69_INPEN69_Pos         (4UL)                     /*!< INPEN69 (Bit 4)                                       */
32462 #define GPIO_PINCFG69_INPEN69_Msk         (0x10UL)                  /*!< INPEN69 (Bitfield-Mask: 0x01)                         */
32463 #define GPIO_PINCFG69_FNCSEL69_Pos        (0UL)                     /*!< FNCSEL69 (Bit 0)                                      */
32464 #define GPIO_PINCFG69_FNCSEL69_Msk        (0xfUL)                   /*!< FNCSEL69 (Bitfield-Mask: 0x0f)                        */
32465 /* =======================================================  PINCFG70  ======================================================== */
32466 #define GPIO_PINCFG70_FOEN70_Pos          (27UL)                    /*!< FOEN70 (Bit 27)                                       */
32467 #define GPIO_PINCFG70_FOEN70_Msk          (0x8000000UL)             /*!< FOEN70 (Bitfield-Mask: 0x01)                          */
32468 #define GPIO_PINCFG70_FIEN70_Pos          (26UL)                    /*!< FIEN70 (Bit 26)                                       */
32469 #define GPIO_PINCFG70_FIEN70_Msk          (0x4000000UL)             /*!< FIEN70 (Bitfield-Mask: 0x01)                          */
32470 #define GPIO_PINCFG70_NCEPOL70_Pos        (22UL)                    /*!< NCEPOL70 (Bit 22)                                     */
32471 #define GPIO_PINCFG70_NCEPOL70_Msk        (0x400000UL)              /*!< NCEPOL70 (Bitfield-Mask: 0x01)                        */
32472 #define GPIO_PINCFG70_NCESRC70_Pos        (16UL)                    /*!< NCESRC70 (Bit 16)                                     */
32473 #define GPIO_PINCFG70_NCESRC70_Msk        (0x3f0000UL)              /*!< NCESRC70 (Bitfield-Mask: 0x3f)                        */
32474 #define GPIO_PINCFG70_PULLCFG70_Pos       (13UL)                    /*!< PULLCFG70 (Bit 13)                                    */
32475 #define GPIO_PINCFG70_PULLCFG70_Msk       (0xe000UL)                /*!< PULLCFG70 (Bitfield-Mask: 0x07)                       */
32476 #define GPIO_PINCFG70_SR70_Pos            (12UL)                    /*!< SR70 (Bit 12)                                         */
32477 #define GPIO_PINCFG70_SR70_Msk            (0x1000UL)                /*!< SR70 (Bitfield-Mask: 0x01)                            */
32478 #define GPIO_PINCFG70_DS70_Pos            (10UL)                    /*!< DS70 (Bit 10)                                         */
32479 #define GPIO_PINCFG70_DS70_Msk            (0xc00UL)                 /*!< DS70 (Bitfield-Mask: 0x03)                            */
32480 #define GPIO_PINCFG70_OUTCFG70_Pos        (8UL)                     /*!< OUTCFG70 (Bit 8)                                      */
32481 #define GPIO_PINCFG70_OUTCFG70_Msk        (0x300UL)                 /*!< OUTCFG70 (Bitfield-Mask: 0x03)                        */
32482 #define GPIO_PINCFG70_IRPTEN70_Pos        (6UL)                     /*!< IRPTEN70 (Bit 6)                                      */
32483 #define GPIO_PINCFG70_IRPTEN70_Msk        (0xc0UL)                  /*!< IRPTEN70 (Bitfield-Mask: 0x03)                        */
32484 #define GPIO_PINCFG70_RDZERO70_Pos        (5UL)                     /*!< RDZERO70 (Bit 5)                                      */
32485 #define GPIO_PINCFG70_RDZERO70_Msk        (0x20UL)                  /*!< RDZERO70 (Bitfield-Mask: 0x01)                        */
32486 #define GPIO_PINCFG70_INPEN70_Pos         (4UL)                     /*!< INPEN70 (Bit 4)                                       */
32487 #define GPIO_PINCFG70_INPEN70_Msk         (0x10UL)                  /*!< INPEN70 (Bitfield-Mask: 0x01)                         */
32488 #define GPIO_PINCFG70_FNCSEL70_Pos        (0UL)                     /*!< FNCSEL70 (Bit 0)                                      */
32489 #define GPIO_PINCFG70_FNCSEL70_Msk        (0xfUL)                   /*!< FNCSEL70 (Bitfield-Mask: 0x0f)                        */
32490 /* =======================================================  PINCFG71  ======================================================== */
32491 #define GPIO_PINCFG71_FOEN71_Pos          (27UL)                    /*!< FOEN71 (Bit 27)                                       */
32492 #define GPIO_PINCFG71_FOEN71_Msk          (0x8000000UL)             /*!< FOEN71 (Bitfield-Mask: 0x01)                          */
32493 #define GPIO_PINCFG71_FIEN71_Pos          (26UL)                    /*!< FIEN71 (Bit 26)                                       */
32494 #define GPIO_PINCFG71_FIEN71_Msk          (0x4000000UL)             /*!< FIEN71 (Bitfield-Mask: 0x01)                          */
32495 #define GPIO_PINCFG71_NCEPOL71_Pos        (22UL)                    /*!< NCEPOL71 (Bit 22)                                     */
32496 #define GPIO_PINCFG71_NCEPOL71_Msk        (0x400000UL)              /*!< NCEPOL71 (Bitfield-Mask: 0x01)                        */
32497 #define GPIO_PINCFG71_NCESRC71_Pos        (16UL)                    /*!< NCESRC71 (Bit 16)                                     */
32498 #define GPIO_PINCFG71_NCESRC71_Msk        (0x3f0000UL)              /*!< NCESRC71 (Bitfield-Mask: 0x3f)                        */
32499 #define GPIO_PINCFG71_PULLCFG71_Pos       (13UL)                    /*!< PULLCFG71 (Bit 13)                                    */
32500 #define GPIO_PINCFG71_PULLCFG71_Msk       (0xe000UL)                /*!< PULLCFG71 (Bitfield-Mask: 0x07)                       */
32501 #define GPIO_PINCFG71_SR71_Pos            (12UL)                    /*!< SR71 (Bit 12)                                         */
32502 #define GPIO_PINCFG71_SR71_Msk            (0x1000UL)                /*!< SR71 (Bitfield-Mask: 0x01)                            */
32503 #define GPIO_PINCFG71_DS71_Pos            (10UL)                    /*!< DS71 (Bit 10)                                         */
32504 #define GPIO_PINCFG71_DS71_Msk            (0xc00UL)                 /*!< DS71 (Bitfield-Mask: 0x03)                            */
32505 #define GPIO_PINCFG71_OUTCFG71_Pos        (8UL)                     /*!< OUTCFG71 (Bit 8)                                      */
32506 #define GPIO_PINCFG71_OUTCFG71_Msk        (0x300UL)                 /*!< OUTCFG71 (Bitfield-Mask: 0x03)                        */
32507 #define GPIO_PINCFG71_IRPTEN71_Pos        (6UL)                     /*!< IRPTEN71 (Bit 6)                                      */
32508 #define GPIO_PINCFG71_IRPTEN71_Msk        (0xc0UL)                  /*!< IRPTEN71 (Bitfield-Mask: 0x03)                        */
32509 #define GPIO_PINCFG71_RDZERO71_Pos        (5UL)                     /*!< RDZERO71 (Bit 5)                                      */
32510 #define GPIO_PINCFG71_RDZERO71_Msk        (0x20UL)                  /*!< RDZERO71 (Bitfield-Mask: 0x01)                        */
32511 #define GPIO_PINCFG71_INPEN71_Pos         (4UL)                     /*!< INPEN71 (Bit 4)                                       */
32512 #define GPIO_PINCFG71_INPEN71_Msk         (0x10UL)                  /*!< INPEN71 (Bitfield-Mask: 0x01)                         */
32513 #define GPIO_PINCFG71_FNCSEL71_Pos        (0UL)                     /*!< FNCSEL71 (Bit 0)                                      */
32514 #define GPIO_PINCFG71_FNCSEL71_Msk        (0xfUL)                   /*!< FNCSEL71 (Bitfield-Mask: 0x0f)                        */
32515 /* =======================================================  PINCFG72  ======================================================== */
32516 #define GPIO_PINCFG72_FOEN72_Pos          (27UL)                    /*!< FOEN72 (Bit 27)                                       */
32517 #define GPIO_PINCFG72_FOEN72_Msk          (0x8000000UL)             /*!< FOEN72 (Bitfield-Mask: 0x01)                          */
32518 #define GPIO_PINCFG72_FIEN72_Pos          (26UL)                    /*!< FIEN72 (Bit 26)                                       */
32519 #define GPIO_PINCFG72_FIEN72_Msk          (0x4000000UL)             /*!< FIEN72 (Bitfield-Mask: 0x01)                          */
32520 #define GPIO_PINCFG72_NCEPOL72_Pos        (22UL)                    /*!< NCEPOL72 (Bit 22)                                     */
32521 #define GPIO_PINCFG72_NCEPOL72_Msk        (0x400000UL)              /*!< NCEPOL72 (Bitfield-Mask: 0x01)                        */
32522 #define GPIO_PINCFG72_NCESRC72_Pos        (16UL)                    /*!< NCESRC72 (Bit 16)                                     */
32523 #define GPIO_PINCFG72_NCESRC72_Msk        (0x3f0000UL)              /*!< NCESRC72 (Bitfield-Mask: 0x3f)                        */
32524 #define GPIO_PINCFG72_PULLCFG72_Pos       (13UL)                    /*!< PULLCFG72 (Bit 13)                                    */
32525 #define GPIO_PINCFG72_PULLCFG72_Msk       (0xe000UL)                /*!< PULLCFG72 (Bitfield-Mask: 0x07)                       */
32526 #define GPIO_PINCFG72_SR72_Pos            (12UL)                    /*!< SR72 (Bit 12)                                         */
32527 #define GPIO_PINCFG72_SR72_Msk            (0x1000UL)                /*!< SR72 (Bitfield-Mask: 0x01)                            */
32528 #define GPIO_PINCFG72_DS72_Pos            (10UL)                    /*!< DS72 (Bit 10)                                         */
32529 #define GPIO_PINCFG72_DS72_Msk            (0xc00UL)                 /*!< DS72 (Bitfield-Mask: 0x03)                            */
32530 #define GPIO_PINCFG72_OUTCFG72_Pos        (8UL)                     /*!< OUTCFG72 (Bit 8)                                      */
32531 #define GPIO_PINCFG72_OUTCFG72_Msk        (0x300UL)                 /*!< OUTCFG72 (Bitfield-Mask: 0x03)                        */
32532 #define GPIO_PINCFG72_IRPTEN72_Pos        (6UL)                     /*!< IRPTEN72 (Bit 6)                                      */
32533 #define GPIO_PINCFG72_IRPTEN72_Msk        (0xc0UL)                  /*!< IRPTEN72 (Bitfield-Mask: 0x03)                        */
32534 #define GPIO_PINCFG72_RDZERO72_Pos        (5UL)                     /*!< RDZERO72 (Bit 5)                                      */
32535 #define GPIO_PINCFG72_RDZERO72_Msk        (0x20UL)                  /*!< RDZERO72 (Bitfield-Mask: 0x01)                        */
32536 #define GPIO_PINCFG72_INPEN72_Pos         (4UL)                     /*!< INPEN72 (Bit 4)                                       */
32537 #define GPIO_PINCFG72_INPEN72_Msk         (0x10UL)                  /*!< INPEN72 (Bitfield-Mask: 0x01)                         */
32538 #define GPIO_PINCFG72_FNCSEL72_Pos        (0UL)                     /*!< FNCSEL72 (Bit 0)                                      */
32539 #define GPIO_PINCFG72_FNCSEL72_Msk        (0xfUL)                   /*!< FNCSEL72 (Bitfield-Mask: 0x0f)                        */
32540 /* =======================================================  PINCFG73  ======================================================== */
32541 #define GPIO_PINCFG73_FOEN73_Pos          (27UL)                    /*!< FOEN73 (Bit 27)                                       */
32542 #define GPIO_PINCFG73_FOEN73_Msk          (0x8000000UL)             /*!< FOEN73 (Bitfield-Mask: 0x01)                          */
32543 #define GPIO_PINCFG73_FIEN73_Pos          (26UL)                    /*!< FIEN73 (Bit 26)                                       */
32544 #define GPIO_PINCFG73_FIEN73_Msk          (0x4000000UL)             /*!< FIEN73 (Bitfield-Mask: 0x01)                          */
32545 #define GPIO_PINCFG73_NCEPOL73_Pos        (22UL)                    /*!< NCEPOL73 (Bit 22)                                     */
32546 #define GPIO_PINCFG73_NCEPOL73_Msk        (0x400000UL)              /*!< NCEPOL73 (Bitfield-Mask: 0x01)                        */
32547 #define GPIO_PINCFG73_NCESRC73_Pos        (16UL)                    /*!< NCESRC73 (Bit 16)                                     */
32548 #define GPIO_PINCFG73_NCESRC73_Msk        (0x3f0000UL)              /*!< NCESRC73 (Bitfield-Mask: 0x3f)                        */
32549 #define GPIO_PINCFG73_PULLCFG73_Pos       (13UL)                    /*!< PULLCFG73 (Bit 13)                                    */
32550 #define GPIO_PINCFG73_PULLCFG73_Msk       (0xe000UL)                /*!< PULLCFG73 (Bitfield-Mask: 0x07)                       */
32551 #define GPIO_PINCFG73_SR73_Pos            (12UL)                    /*!< SR73 (Bit 12)                                         */
32552 #define GPIO_PINCFG73_SR73_Msk            (0x1000UL)                /*!< SR73 (Bitfield-Mask: 0x01)                            */
32553 #define GPIO_PINCFG73_DS73_Pos            (10UL)                    /*!< DS73 (Bit 10)                                         */
32554 #define GPIO_PINCFG73_DS73_Msk            (0xc00UL)                 /*!< DS73 (Bitfield-Mask: 0x03)                            */
32555 #define GPIO_PINCFG73_OUTCFG73_Pos        (8UL)                     /*!< OUTCFG73 (Bit 8)                                      */
32556 #define GPIO_PINCFG73_OUTCFG73_Msk        (0x300UL)                 /*!< OUTCFG73 (Bitfield-Mask: 0x03)                        */
32557 #define GPIO_PINCFG73_IRPTEN73_Pos        (6UL)                     /*!< IRPTEN73 (Bit 6)                                      */
32558 #define GPIO_PINCFG73_IRPTEN73_Msk        (0xc0UL)                  /*!< IRPTEN73 (Bitfield-Mask: 0x03)                        */
32559 #define GPIO_PINCFG73_RDZERO73_Pos        (5UL)                     /*!< RDZERO73 (Bit 5)                                      */
32560 #define GPIO_PINCFG73_RDZERO73_Msk        (0x20UL)                  /*!< RDZERO73 (Bitfield-Mask: 0x01)                        */
32561 #define GPIO_PINCFG73_INPEN73_Pos         (4UL)                     /*!< INPEN73 (Bit 4)                                       */
32562 #define GPIO_PINCFG73_INPEN73_Msk         (0x10UL)                  /*!< INPEN73 (Bitfield-Mask: 0x01)                         */
32563 #define GPIO_PINCFG73_FNCSEL73_Pos        (0UL)                     /*!< FNCSEL73 (Bit 0)                                      */
32564 #define GPIO_PINCFG73_FNCSEL73_Msk        (0xfUL)                   /*!< FNCSEL73 (Bitfield-Mask: 0x0f)                        */
32565 /* =======================================================  PINCFG74  ======================================================== */
32566 #define GPIO_PINCFG74_FOEN74_Pos          (27UL)                    /*!< FOEN74 (Bit 27)                                       */
32567 #define GPIO_PINCFG74_FOEN74_Msk          (0x8000000UL)             /*!< FOEN74 (Bitfield-Mask: 0x01)                          */
32568 #define GPIO_PINCFG74_FIEN74_Pos          (26UL)                    /*!< FIEN74 (Bit 26)                                       */
32569 #define GPIO_PINCFG74_FIEN74_Msk          (0x4000000UL)             /*!< FIEN74 (Bitfield-Mask: 0x01)                          */
32570 #define GPIO_PINCFG74_NCEPOL74_Pos        (22UL)                    /*!< NCEPOL74 (Bit 22)                                     */
32571 #define GPIO_PINCFG74_NCEPOL74_Msk        (0x400000UL)              /*!< NCEPOL74 (Bitfield-Mask: 0x01)                        */
32572 #define GPIO_PINCFG74_NCESRC74_Pos        (16UL)                    /*!< NCESRC74 (Bit 16)                                     */
32573 #define GPIO_PINCFG74_NCESRC74_Msk        (0x3f0000UL)              /*!< NCESRC74 (Bitfield-Mask: 0x3f)                        */
32574 #define GPIO_PINCFG74_PULLCFG74_Pos       (13UL)                    /*!< PULLCFG74 (Bit 13)                                    */
32575 #define GPIO_PINCFG74_PULLCFG74_Msk       (0xe000UL)                /*!< PULLCFG74 (Bitfield-Mask: 0x07)                       */
32576 #define GPIO_PINCFG74_SR74_Pos            (12UL)                    /*!< SR74 (Bit 12)                                         */
32577 #define GPIO_PINCFG74_SR74_Msk            (0x1000UL)                /*!< SR74 (Bitfield-Mask: 0x01)                            */
32578 #define GPIO_PINCFG74_DS74_Pos            (10UL)                    /*!< DS74 (Bit 10)                                         */
32579 #define GPIO_PINCFG74_DS74_Msk            (0xc00UL)                 /*!< DS74 (Bitfield-Mask: 0x03)                            */
32580 #define GPIO_PINCFG74_OUTCFG74_Pos        (8UL)                     /*!< OUTCFG74 (Bit 8)                                      */
32581 #define GPIO_PINCFG74_OUTCFG74_Msk        (0x300UL)                 /*!< OUTCFG74 (Bitfield-Mask: 0x03)                        */
32582 #define GPIO_PINCFG74_IRPTEN74_Pos        (6UL)                     /*!< IRPTEN74 (Bit 6)                                      */
32583 #define GPIO_PINCFG74_IRPTEN74_Msk        (0xc0UL)                  /*!< IRPTEN74 (Bitfield-Mask: 0x03)                        */
32584 #define GPIO_PINCFG74_RDZERO74_Pos        (5UL)                     /*!< RDZERO74 (Bit 5)                                      */
32585 #define GPIO_PINCFG74_RDZERO74_Msk        (0x20UL)                  /*!< RDZERO74 (Bitfield-Mask: 0x01)                        */
32586 #define GPIO_PINCFG74_INPEN74_Pos         (4UL)                     /*!< INPEN74 (Bit 4)                                       */
32587 #define GPIO_PINCFG74_INPEN74_Msk         (0x10UL)                  /*!< INPEN74 (Bitfield-Mask: 0x01)                         */
32588 #define GPIO_PINCFG74_FNCSEL74_Pos        (0UL)                     /*!< FNCSEL74 (Bit 0)                                      */
32589 #define GPIO_PINCFG74_FNCSEL74_Msk        (0xfUL)                   /*!< FNCSEL74 (Bitfield-Mask: 0x0f)                        */
32590 /* =======================================================  PINCFG75  ======================================================== */
32591 #define GPIO_PINCFG75_FOEN75_Pos          (27UL)                    /*!< FOEN75 (Bit 27)                                       */
32592 #define GPIO_PINCFG75_FOEN75_Msk          (0x8000000UL)             /*!< FOEN75 (Bitfield-Mask: 0x01)                          */
32593 #define GPIO_PINCFG75_FIEN75_Pos          (26UL)                    /*!< FIEN75 (Bit 26)                                       */
32594 #define GPIO_PINCFG75_FIEN75_Msk          (0x4000000UL)             /*!< FIEN75 (Bitfield-Mask: 0x01)                          */
32595 #define GPIO_PINCFG75_NCEPOL75_Pos        (22UL)                    /*!< NCEPOL75 (Bit 22)                                     */
32596 #define GPIO_PINCFG75_NCEPOL75_Msk        (0x400000UL)              /*!< NCEPOL75 (Bitfield-Mask: 0x01)                        */
32597 #define GPIO_PINCFG75_NCESRC75_Pos        (16UL)                    /*!< NCESRC75 (Bit 16)                                     */
32598 #define GPIO_PINCFG75_NCESRC75_Msk        (0x3f0000UL)              /*!< NCESRC75 (Bitfield-Mask: 0x3f)                        */
32599 #define GPIO_PINCFG75_PULLCFG75_Pos       (13UL)                    /*!< PULLCFG75 (Bit 13)                                    */
32600 #define GPIO_PINCFG75_PULLCFG75_Msk       (0xe000UL)                /*!< PULLCFG75 (Bitfield-Mask: 0x07)                       */
32601 #define GPIO_PINCFG75_SR75_Pos            (12UL)                    /*!< SR75 (Bit 12)                                         */
32602 #define GPIO_PINCFG75_SR75_Msk            (0x1000UL)                /*!< SR75 (Bitfield-Mask: 0x01)                            */
32603 #define GPIO_PINCFG75_DS75_Pos            (10UL)                    /*!< DS75 (Bit 10)                                         */
32604 #define GPIO_PINCFG75_DS75_Msk            (0xc00UL)                 /*!< DS75 (Bitfield-Mask: 0x03)                            */
32605 #define GPIO_PINCFG75_OUTCFG75_Pos        (8UL)                     /*!< OUTCFG75 (Bit 8)                                      */
32606 #define GPIO_PINCFG75_OUTCFG75_Msk        (0x300UL)                 /*!< OUTCFG75 (Bitfield-Mask: 0x03)                        */
32607 #define GPIO_PINCFG75_IRPTEN75_Pos        (6UL)                     /*!< IRPTEN75 (Bit 6)                                      */
32608 #define GPIO_PINCFG75_IRPTEN75_Msk        (0xc0UL)                  /*!< IRPTEN75 (Bitfield-Mask: 0x03)                        */
32609 #define GPIO_PINCFG75_RDZERO75_Pos        (5UL)                     /*!< RDZERO75 (Bit 5)                                      */
32610 #define GPIO_PINCFG75_RDZERO75_Msk        (0x20UL)                  /*!< RDZERO75 (Bitfield-Mask: 0x01)                        */
32611 #define GPIO_PINCFG75_INPEN75_Pos         (4UL)                     /*!< INPEN75 (Bit 4)                                       */
32612 #define GPIO_PINCFG75_INPEN75_Msk         (0x10UL)                  /*!< INPEN75 (Bitfield-Mask: 0x01)                         */
32613 #define GPIO_PINCFG75_FNCSEL75_Pos        (0UL)                     /*!< FNCSEL75 (Bit 0)                                      */
32614 #define GPIO_PINCFG75_FNCSEL75_Msk        (0xfUL)                   /*!< FNCSEL75 (Bitfield-Mask: 0x0f)                        */
32615 /* =======================================================  PINCFG76  ======================================================== */
32616 #define GPIO_PINCFG76_FOEN76_Pos          (27UL)                    /*!< FOEN76 (Bit 27)                                       */
32617 #define GPIO_PINCFG76_FOEN76_Msk          (0x8000000UL)             /*!< FOEN76 (Bitfield-Mask: 0x01)                          */
32618 #define GPIO_PINCFG76_FIEN76_Pos          (26UL)                    /*!< FIEN76 (Bit 26)                                       */
32619 #define GPIO_PINCFG76_FIEN76_Msk          (0x4000000UL)             /*!< FIEN76 (Bitfield-Mask: 0x01)                          */
32620 #define GPIO_PINCFG76_NCEPOL76_Pos        (22UL)                    /*!< NCEPOL76 (Bit 22)                                     */
32621 #define GPIO_PINCFG76_NCEPOL76_Msk        (0x400000UL)              /*!< NCEPOL76 (Bitfield-Mask: 0x01)                        */
32622 #define GPIO_PINCFG76_NCESRC76_Pos        (16UL)                    /*!< NCESRC76 (Bit 16)                                     */
32623 #define GPIO_PINCFG76_NCESRC76_Msk        (0x3f0000UL)              /*!< NCESRC76 (Bitfield-Mask: 0x3f)                        */
32624 #define GPIO_PINCFG76_PULLCFG76_Pos       (13UL)                    /*!< PULLCFG76 (Bit 13)                                    */
32625 #define GPIO_PINCFG76_PULLCFG76_Msk       (0xe000UL)                /*!< PULLCFG76 (Bitfield-Mask: 0x07)                       */
32626 #define GPIO_PINCFG76_SR76_Pos            (12UL)                    /*!< SR76 (Bit 12)                                         */
32627 #define GPIO_PINCFG76_SR76_Msk            (0x1000UL)                /*!< SR76 (Bitfield-Mask: 0x01)                            */
32628 #define GPIO_PINCFG76_DS76_Pos            (10UL)                    /*!< DS76 (Bit 10)                                         */
32629 #define GPIO_PINCFG76_DS76_Msk            (0xc00UL)                 /*!< DS76 (Bitfield-Mask: 0x03)                            */
32630 #define GPIO_PINCFG76_OUTCFG76_Pos        (8UL)                     /*!< OUTCFG76 (Bit 8)                                      */
32631 #define GPIO_PINCFG76_OUTCFG76_Msk        (0x300UL)                 /*!< OUTCFG76 (Bitfield-Mask: 0x03)                        */
32632 #define GPIO_PINCFG76_IRPTEN76_Pos        (6UL)                     /*!< IRPTEN76 (Bit 6)                                      */
32633 #define GPIO_PINCFG76_IRPTEN76_Msk        (0xc0UL)                  /*!< IRPTEN76 (Bitfield-Mask: 0x03)                        */
32634 #define GPIO_PINCFG76_RDZERO76_Pos        (5UL)                     /*!< RDZERO76 (Bit 5)                                      */
32635 #define GPIO_PINCFG76_RDZERO76_Msk        (0x20UL)                  /*!< RDZERO76 (Bitfield-Mask: 0x01)                        */
32636 #define GPIO_PINCFG76_INPEN76_Pos         (4UL)                     /*!< INPEN76 (Bit 4)                                       */
32637 #define GPIO_PINCFG76_INPEN76_Msk         (0x10UL)                  /*!< INPEN76 (Bitfield-Mask: 0x01)                         */
32638 #define GPIO_PINCFG76_FNCSEL76_Pos        (0UL)                     /*!< FNCSEL76 (Bit 0)                                      */
32639 #define GPIO_PINCFG76_FNCSEL76_Msk        (0xfUL)                   /*!< FNCSEL76 (Bitfield-Mask: 0x0f)                        */
32640 /* =======================================================  PINCFG77  ======================================================== */
32641 #define GPIO_PINCFG77_FOEN77_Pos          (27UL)                    /*!< FOEN77 (Bit 27)                                       */
32642 #define GPIO_PINCFG77_FOEN77_Msk          (0x8000000UL)             /*!< FOEN77 (Bitfield-Mask: 0x01)                          */
32643 #define GPIO_PINCFG77_FIEN77_Pos          (26UL)                    /*!< FIEN77 (Bit 26)                                       */
32644 #define GPIO_PINCFG77_FIEN77_Msk          (0x4000000UL)             /*!< FIEN77 (Bitfield-Mask: 0x01)                          */
32645 #define GPIO_PINCFG77_NCEPOL77_Pos        (22UL)                    /*!< NCEPOL77 (Bit 22)                                     */
32646 #define GPIO_PINCFG77_NCEPOL77_Msk        (0x400000UL)              /*!< NCEPOL77 (Bitfield-Mask: 0x01)                        */
32647 #define GPIO_PINCFG77_NCESRC77_Pos        (16UL)                    /*!< NCESRC77 (Bit 16)                                     */
32648 #define GPIO_PINCFG77_NCESRC77_Msk        (0x3f0000UL)              /*!< NCESRC77 (Bitfield-Mask: 0x3f)                        */
32649 #define GPIO_PINCFG77_PULLCFG77_Pos       (13UL)                    /*!< PULLCFG77 (Bit 13)                                    */
32650 #define GPIO_PINCFG77_PULLCFG77_Msk       (0xe000UL)                /*!< PULLCFG77 (Bitfield-Mask: 0x07)                       */
32651 #define GPIO_PINCFG77_SR77_Pos            (12UL)                    /*!< SR77 (Bit 12)                                         */
32652 #define GPIO_PINCFG77_SR77_Msk            (0x1000UL)                /*!< SR77 (Bitfield-Mask: 0x01)                            */
32653 #define GPIO_PINCFG77_DS77_Pos            (10UL)                    /*!< DS77 (Bit 10)                                         */
32654 #define GPIO_PINCFG77_DS77_Msk            (0xc00UL)                 /*!< DS77 (Bitfield-Mask: 0x03)                            */
32655 #define GPIO_PINCFG77_OUTCFG77_Pos        (8UL)                     /*!< OUTCFG77 (Bit 8)                                      */
32656 #define GPIO_PINCFG77_OUTCFG77_Msk        (0x300UL)                 /*!< OUTCFG77 (Bitfield-Mask: 0x03)                        */
32657 #define GPIO_PINCFG77_IRPTEN77_Pos        (6UL)                     /*!< IRPTEN77 (Bit 6)                                      */
32658 #define GPIO_PINCFG77_IRPTEN77_Msk        (0xc0UL)                  /*!< IRPTEN77 (Bitfield-Mask: 0x03)                        */
32659 #define GPIO_PINCFG77_RDZERO77_Pos        (5UL)                     /*!< RDZERO77 (Bit 5)                                      */
32660 #define GPIO_PINCFG77_RDZERO77_Msk        (0x20UL)                  /*!< RDZERO77 (Bitfield-Mask: 0x01)                        */
32661 #define GPIO_PINCFG77_INPEN77_Pos         (4UL)                     /*!< INPEN77 (Bit 4)                                       */
32662 #define GPIO_PINCFG77_INPEN77_Msk         (0x10UL)                  /*!< INPEN77 (Bitfield-Mask: 0x01)                         */
32663 #define GPIO_PINCFG77_FNCSEL77_Pos        (0UL)                     /*!< FNCSEL77 (Bit 0)                                      */
32664 #define GPIO_PINCFG77_FNCSEL77_Msk        (0xfUL)                   /*!< FNCSEL77 (Bitfield-Mask: 0x0f)                        */
32665 /* =======================================================  PINCFG78  ======================================================== */
32666 #define GPIO_PINCFG78_FOEN78_Pos          (27UL)                    /*!< FOEN78 (Bit 27)                                       */
32667 #define GPIO_PINCFG78_FOEN78_Msk          (0x8000000UL)             /*!< FOEN78 (Bitfield-Mask: 0x01)                          */
32668 #define GPIO_PINCFG78_FIEN78_Pos          (26UL)                    /*!< FIEN78 (Bit 26)                                       */
32669 #define GPIO_PINCFG78_FIEN78_Msk          (0x4000000UL)             /*!< FIEN78 (Bitfield-Mask: 0x01)                          */
32670 #define GPIO_PINCFG78_NCEPOL78_Pos        (22UL)                    /*!< NCEPOL78 (Bit 22)                                     */
32671 #define GPIO_PINCFG78_NCEPOL78_Msk        (0x400000UL)              /*!< NCEPOL78 (Bitfield-Mask: 0x01)                        */
32672 #define GPIO_PINCFG78_NCESRC78_Pos        (16UL)                    /*!< NCESRC78 (Bit 16)                                     */
32673 #define GPIO_PINCFG78_NCESRC78_Msk        (0x3f0000UL)              /*!< NCESRC78 (Bitfield-Mask: 0x3f)                        */
32674 #define GPIO_PINCFG78_PULLCFG78_Pos       (13UL)                    /*!< PULLCFG78 (Bit 13)                                    */
32675 #define GPIO_PINCFG78_PULLCFG78_Msk       (0xe000UL)                /*!< PULLCFG78 (Bitfield-Mask: 0x07)                       */
32676 #define GPIO_PINCFG78_SR78_Pos            (12UL)                    /*!< SR78 (Bit 12)                                         */
32677 #define GPIO_PINCFG78_SR78_Msk            (0x1000UL)                /*!< SR78 (Bitfield-Mask: 0x01)                            */
32678 #define GPIO_PINCFG78_DS78_Pos            (10UL)                    /*!< DS78 (Bit 10)                                         */
32679 #define GPIO_PINCFG78_DS78_Msk            (0xc00UL)                 /*!< DS78 (Bitfield-Mask: 0x03)                            */
32680 #define GPIO_PINCFG78_OUTCFG78_Pos        (8UL)                     /*!< OUTCFG78 (Bit 8)                                      */
32681 #define GPIO_PINCFG78_OUTCFG78_Msk        (0x300UL)                 /*!< OUTCFG78 (Bitfield-Mask: 0x03)                        */
32682 #define GPIO_PINCFG78_IRPTEN78_Pos        (6UL)                     /*!< IRPTEN78 (Bit 6)                                      */
32683 #define GPIO_PINCFG78_IRPTEN78_Msk        (0xc0UL)                  /*!< IRPTEN78 (Bitfield-Mask: 0x03)                        */
32684 #define GPIO_PINCFG78_RDZERO78_Pos        (5UL)                     /*!< RDZERO78 (Bit 5)                                      */
32685 #define GPIO_PINCFG78_RDZERO78_Msk        (0x20UL)                  /*!< RDZERO78 (Bitfield-Mask: 0x01)                        */
32686 #define GPIO_PINCFG78_INPEN78_Pos         (4UL)                     /*!< INPEN78 (Bit 4)                                       */
32687 #define GPIO_PINCFG78_INPEN78_Msk         (0x10UL)                  /*!< INPEN78 (Bitfield-Mask: 0x01)                         */
32688 #define GPIO_PINCFG78_FNCSEL78_Pos        (0UL)                     /*!< FNCSEL78 (Bit 0)                                      */
32689 #define GPIO_PINCFG78_FNCSEL78_Msk        (0xfUL)                   /*!< FNCSEL78 (Bitfield-Mask: 0x0f)                        */
32690 /* =======================================================  PINCFG79  ======================================================== */
32691 #define GPIO_PINCFG79_FOEN79_Pos          (27UL)                    /*!< FOEN79 (Bit 27)                                       */
32692 #define GPIO_PINCFG79_FOEN79_Msk          (0x8000000UL)             /*!< FOEN79 (Bitfield-Mask: 0x01)                          */
32693 #define GPIO_PINCFG79_FIEN79_Pos          (26UL)                    /*!< FIEN79 (Bit 26)                                       */
32694 #define GPIO_PINCFG79_FIEN79_Msk          (0x4000000UL)             /*!< FIEN79 (Bitfield-Mask: 0x01)                          */
32695 #define GPIO_PINCFG79_NCEPOL79_Pos        (22UL)                    /*!< NCEPOL79 (Bit 22)                                     */
32696 #define GPIO_PINCFG79_NCEPOL79_Msk        (0x400000UL)              /*!< NCEPOL79 (Bitfield-Mask: 0x01)                        */
32697 #define GPIO_PINCFG79_NCESRC79_Pos        (16UL)                    /*!< NCESRC79 (Bit 16)                                     */
32698 #define GPIO_PINCFG79_NCESRC79_Msk        (0x3f0000UL)              /*!< NCESRC79 (Bitfield-Mask: 0x3f)                        */
32699 #define GPIO_PINCFG79_PULLCFG79_Pos       (13UL)                    /*!< PULLCFG79 (Bit 13)                                    */
32700 #define GPIO_PINCFG79_PULLCFG79_Msk       (0xe000UL)                /*!< PULLCFG79 (Bitfield-Mask: 0x07)                       */
32701 #define GPIO_PINCFG79_SR79_Pos            (12UL)                    /*!< SR79 (Bit 12)                                         */
32702 #define GPIO_PINCFG79_SR79_Msk            (0x1000UL)                /*!< SR79 (Bitfield-Mask: 0x01)                            */
32703 #define GPIO_PINCFG79_DS79_Pos            (10UL)                    /*!< DS79 (Bit 10)                                         */
32704 #define GPIO_PINCFG79_DS79_Msk            (0xc00UL)                 /*!< DS79 (Bitfield-Mask: 0x03)                            */
32705 #define GPIO_PINCFG79_OUTCFG79_Pos        (8UL)                     /*!< OUTCFG79 (Bit 8)                                      */
32706 #define GPIO_PINCFG79_OUTCFG79_Msk        (0x300UL)                 /*!< OUTCFG79 (Bitfield-Mask: 0x03)                        */
32707 #define GPIO_PINCFG79_IRPTEN79_Pos        (6UL)                     /*!< IRPTEN79 (Bit 6)                                      */
32708 #define GPIO_PINCFG79_IRPTEN79_Msk        (0xc0UL)                  /*!< IRPTEN79 (Bitfield-Mask: 0x03)                        */
32709 #define GPIO_PINCFG79_RDZERO79_Pos        (5UL)                     /*!< RDZERO79 (Bit 5)                                      */
32710 #define GPIO_PINCFG79_RDZERO79_Msk        (0x20UL)                  /*!< RDZERO79 (Bitfield-Mask: 0x01)                        */
32711 #define GPIO_PINCFG79_INPEN79_Pos         (4UL)                     /*!< INPEN79 (Bit 4)                                       */
32712 #define GPIO_PINCFG79_INPEN79_Msk         (0x10UL)                  /*!< INPEN79 (Bitfield-Mask: 0x01)                         */
32713 #define GPIO_PINCFG79_FNCSEL79_Pos        (0UL)                     /*!< FNCSEL79 (Bit 0)                                      */
32714 #define GPIO_PINCFG79_FNCSEL79_Msk        (0xfUL)                   /*!< FNCSEL79 (Bitfield-Mask: 0x0f)                        */
32715 /* =======================================================  PINCFG80  ======================================================== */
32716 #define GPIO_PINCFG80_FOEN80_Pos          (27UL)                    /*!< FOEN80 (Bit 27)                                       */
32717 #define GPIO_PINCFG80_FOEN80_Msk          (0x8000000UL)             /*!< FOEN80 (Bitfield-Mask: 0x01)                          */
32718 #define GPIO_PINCFG80_FIEN80_Pos          (26UL)                    /*!< FIEN80 (Bit 26)                                       */
32719 #define GPIO_PINCFG80_FIEN80_Msk          (0x4000000UL)             /*!< FIEN80 (Bitfield-Mask: 0x01)                          */
32720 #define GPIO_PINCFG80_NCEPOL80_Pos        (22UL)                    /*!< NCEPOL80 (Bit 22)                                     */
32721 #define GPIO_PINCFG80_NCEPOL80_Msk        (0x400000UL)              /*!< NCEPOL80 (Bitfield-Mask: 0x01)                        */
32722 #define GPIO_PINCFG80_NCESRC80_Pos        (16UL)                    /*!< NCESRC80 (Bit 16)                                     */
32723 #define GPIO_PINCFG80_NCESRC80_Msk        (0x3f0000UL)              /*!< NCESRC80 (Bitfield-Mask: 0x3f)                        */
32724 #define GPIO_PINCFG80_PULLCFG80_Pos       (13UL)                    /*!< PULLCFG80 (Bit 13)                                    */
32725 #define GPIO_PINCFG80_PULLCFG80_Msk       (0xe000UL)                /*!< PULLCFG80 (Bitfield-Mask: 0x07)                       */
32726 #define GPIO_PINCFG80_SR80_Pos            (12UL)                    /*!< SR80 (Bit 12)                                         */
32727 #define GPIO_PINCFG80_SR80_Msk            (0x1000UL)                /*!< SR80 (Bitfield-Mask: 0x01)                            */
32728 #define GPIO_PINCFG80_DS80_Pos            (10UL)                    /*!< DS80 (Bit 10)                                         */
32729 #define GPIO_PINCFG80_DS80_Msk            (0xc00UL)                 /*!< DS80 (Bitfield-Mask: 0x03)                            */
32730 #define GPIO_PINCFG80_OUTCFG80_Pos        (8UL)                     /*!< OUTCFG80 (Bit 8)                                      */
32731 #define GPIO_PINCFG80_OUTCFG80_Msk        (0x300UL)                 /*!< OUTCFG80 (Bitfield-Mask: 0x03)                        */
32732 #define GPIO_PINCFG80_IRPTEN80_Pos        (6UL)                     /*!< IRPTEN80 (Bit 6)                                      */
32733 #define GPIO_PINCFG80_IRPTEN80_Msk        (0xc0UL)                  /*!< IRPTEN80 (Bitfield-Mask: 0x03)                        */
32734 #define GPIO_PINCFG80_RDZERO80_Pos        (5UL)                     /*!< RDZERO80 (Bit 5)                                      */
32735 #define GPIO_PINCFG80_RDZERO80_Msk        (0x20UL)                  /*!< RDZERO80 (Bitfield-Mask: 0x01)                        */
32736 #define GPIO_PINCFG80_INPEN80_Pos         (4UL)                     /*!< INPEN80 (Bit 4)                                       */
32737 #define GPIO_PINCFG80_INPEN80_Msk         (0x10UL)                  /*!< INPEN80 (Bitfield-Mask: 0x01)                         */
32738 #define GPIO_PINCFG80_FNCSEL80_Pos        (0UL)                     /*!< FNCSEL80 (Bit 0)                                      */
32739 #define GPIO_PINCFG80_FNCSEL80_Msk        (0xfUL)                   /*!< FNCSEL80 (Bitfield-Mask: 0x0f)                        */
32740 /* =======================================================  PINCFG81  ======================================================== */
32741 #define GPIO_PINCFG81_FOEN81_Pos          (27UL)                    /*!< FOEN81 (Bit 27)                                       */
32742 #define GPIO_PINCFG81_FOEN81_Msk          (0x8000000UL)             /*!< FOEN81 (Bitfield-Mask: 0x01)                          */
32743 #define GPIO_PINCFG81_FIEN81_Pos          (26UL)                    /*!< FIEN81 (Bit 26)                                       */
32744 #define GPIO_PINCFG81_FIEN81_Msk          (0x4000000UL)             /*!< FIEN81 (Bitfield-Mask: 0x01)                          */
32745 #define GPIO_PINCFG81_NCEPOL81_Pos        (22UL)                    /*!< NCEPOL81 (Bit 22)                                     */
32746 #define GPIO_PINCFG81_NCEPOL81_Msk        (0x400000UL)              /*!< NCEPOL81 (Bitfield-Mask: 0x01)                        */
32747 #define GPIO_PINCFG81_NCESRC81_Pos        (16UL)                    /*!< NCESRC81 (Bit 16)                                     */
32748 #define GPIO_PINCFG81_NCESRC81_Msk        (0x3f0000UL)              /*!< NCESRC81 (Bitfield-Mask: 0x3f)                        */
32749 #define GPIO_PINCFG81_PULLCFG81_Pos       (13UL)                    /*!< PULLCFG81 (Bit 13)                                    */
32750 #define GPIO_PINCFG81_PULLCFG81_Msk       (0xe000UL)                /*!< PULLCFG81 (Bitfield-Mask: 0x07)                       */
32751 #define GPIO_PINCFG81_SR81_Pos            (12UL)                    /*!< SR81 (Bit 12)                                         */
32752 #define GPIO_PINCFG81_SR81_Msk            (0x1000UL)                /*!< SR81 (Bitfield-Mask: 0x01)                            */
32753 #define GPIO_PINCFG81_DS81_Pos            (10UL)                    /*!< DS81 (Bit 10)                                         */
32754 #define GPIO_PINCFG81_DS81_Msk            (0xc00UL)                 /*!< DS81 (Bitfield-Mask: 0x03)                            */
32755 #define GPIO_PINCFG81_OUTCFG81_Pos        (8UL)                     /*!< OUTCFG81 (Bit 8)                                      */
32756 #define GPIO_PINCFG81_OUTCFG81_Msk        (0x300UL)                 /*!< OUTCFG81 (Bitfield-Mask: 0x03)                        */
32757 #define GPIO_PINCFG81_IRPTEN81_Pos        (6UL)                     /*!< IRPTEN81 (Bit 6)                                      */
32758 #define GPIO_PINCFG81_IRPTEN81_Msk        (0xc0UL)                  /*!< IRPTEN81 (Bitfield-Mask: 0x03)                        */
32759 #define GPIO_PINCFG81_RDZERO81_Pos        (5UL)                     /*!< RDZERO81 (Bit 5)                                      */
32760 #define GPIO_PINCFG81_RDZERO81_Msk        (0x20UL)                  /*!< RDZERO81 (Bitfield-Mask: 0x01)                        */
32761 #define GPIO_PINCFG81_INPEN81_Pos         (4UL)                     /*!< INPEN81 (Bit 4)                                       */
32762 #define GPIO_PINCFG81_INPEN81_Msk         (0x10UL)                  /*!< INPEN81 (Bitfield-Mask: 0x01)                         */
32763 #define GPIO_PINCFG81_FNCSEL81_Pos        (0UL)                     /*!< FNCSEL81 (Bit 0)                                      */
32764 #define GPIO_PINCFG81_FNCSEL81_Msk        (0xfUL)                   /*!< FNCSEL81 (Bitfield-Mask: 0x0f)                        */
32765 /* =======================================================  PINCFG82  ======================================================== */
32766 #define GPIO_PINCFG82_FOEN82_Pos          (27UL)                    /*!< FOEN82 (Bit 27)                                       */
32767 #define GPIO_PINCFG82_FOEN82_Msk          (0x8000000UL)             /*!< FOEN82 (Bitfield-Mask: 0x01)                          */
32768 #define GPIO_PINCFG82_FIEN82_Pos          (26UL)                    /*!< FIEN82 (Bit 26)                                       */
32769 #define GPIO_PINCFG82_FIEN82_Msk          (0x4000000UL)             /*!< FIEN82 (Bitfield-Mask: 0x01)                          */
32770 #define GPIO_PINCFG82_NCEPOL82_Pos        (22UL)                    /*!< NCEPOL82 (Bit 22)                                     */
32771 #define GPIO_PINCFG82_NCEPOL82_Msk        (0x400000UL)              /*!< NCEPOL82 (Bitfield-Mask: 0x01)                        */
32772 #define GPIO_PINCFG82_NCESRC82_Pos        (16UL)                    /*!< NCESRC82 (Bit 16)                                     */
32773 #define GPIO_PINCFG82_NCESRC82_Msk        (0x3f0000UL)              /*!< NCESRC82 (Bitfield-Mask: 0x3f)                        */
32774 #define GPIO_PINCFG82_PULLCFG82_Pos       (13UL)                    /*!< PULLCFG82 (Bit 13)                                    */
32775 #define GPIO_PINCFG82_PULLCFG82_Msk       (0xe000UL)                /*!< PULLCFG82 (Bitfield-Mask: 0x07)                       */
32776 #define GPIO_PINCFG82_SR82_Pos            (12UL)                    /*!< SR82 (Bit 12)                                         */
32777 #define GPIO_PINCFG82_SR82_Msk            (0x1000UL)                /*!< SR82 (Bitfield-Mask: 0x01)                            */
32778 #define GPIO_PINCFG82_DS82_Pos            (10UL)                    /*!< DS82 (Bit 10)                                         */
32779 #define GPIO_PINCFG82_DS82_Msk            (0xc00UL)                 /*!< DS82 (Bitfield-Mask: 0x03)                            */
32780 #define GPIO_PINCFG82_OUTCFG82_Pos        (8UL)                     /*!< OUTCFG82 (Bit 8)                                      */
32781 #define GPIO_PINCFG82_OUTCFG82_Msk        (0x300UL)                 /*!< OUTCFG82 (Bitfield-Mask: 0x03)                        */
32782 #define GPIO_PINCFG82_IRPTEN82_Pos        (6UL)                     /*!< IRPTEN82 (Bit 6)                                      */
32783 #define GPIO_PINCFG82_IRPTEN82_Msk        (0xc0UL)                  /*!< IRPTEN82 (Bitfield-Mask: 0x03)                        */
32784 #define GPIO_PINCFG82_RDZERO82_Pos        (5UL)                     /*!< RDZERO82 (Bit 5)                                      */
32785 #define GPIO_PINCFG82_RDZERO82_Msk        (0x20UL)                  /*!< RDZERO82 (Bitfield-Mask: 0x01)                        */
32786 #define GPIO_PINCFG82_INPEN82_Pos         (4UL)                     /*!< INPEN82 (Bit 4)                                       */
32787 #define GPIO_PINCFG82_INPEN82_Msk         (0x10UL)                  /*!< INPEN82 (Bitfield-Mask: 0x01)                         */
32788 #define GPIO_PINCFG82_FNCSEL82_Pos        (0UL)                     /*!< FNCSEL82 (Bit 0)                                      */
32789 #define GPIO_PINCFG82_FNCSEL82_Msk        (0xfUL)                   /*!< FNCSEL82 (Bitfield-Mask: 0x0f)                        */
32790 /* =======================================================  PINCFG83  ======================================================== */
32791 #define GPIO_PINCFG83_FOEN83_Pos          (27UL)                    /*!< FOEN83 (Bit 27)                                       */
32792 #define GPIO_PINCFG83_FOEN83_Msk          (0x8000000UL)             /*!< FOEN83 (Bitfield-Mask: 0x01)                          */
32793 #define GPIO_PINCFG83_FIEN83_Pos          (26UL)                    /*!< FIEN83 (Bit 26)                                       */
32794 #define GPIO_PINCFG83_FIEN83_Msk          (0x4000000UL)             /*!< FIEN83 (Bitfield-Mask: 0x01)                          */
32795 #define GPIO_PINCFG83_NCEPOL83_Pos        (22UL)                    /*!< NCEPOL83 (Bit 22)                                     */
32796 #define GPIO_PINCFG83_NCEPOL83_Msk        (0x400000UL)              /*!< NCEPOL83 (Bitfield-Mask: 0x01)                        */
32797 #define GPIO_PINCFG83_NCESRC83_Pos        (16UL)                    /*!< NCESRC83 (Bit 16)                                     */
32798 #define GPIO_PINCFG83_NCESRC83_Msk        (0x3f0000UL)              /*!< NCESRC83 (Bitfield-Mask: 0x3f)                        */
32799 #define GPIO_PINCFG83_PULLCFG83_Pos       (13UL)                    /*!< PULLCFG83 (Bit 13)                                    */
32800 #define GPIO_PINCFG83_PULLCFG83_Msk       (0xe000UL)                /*!< PULLCFG83 (Bitfield-Mask: 0x07)                       */
32801 #define GPIO_PINCFG83_SR83_Pos            (12UL)                    /*!< SR83 (Bit 12)                                         */
32802 #define GPIO_PINCFG83_SR83_Msk            (0x1000UL)                /*!< SR83 (Bitfield-Mask: 0x01)                            */
32803 #define GPIO_PINCFG83_DS83_Pos            (10UL)                    /*!< DS83 (Bit 10)                                         */
32804 #define GPIO_PINCFG83_DS83_Msk            (0xc00UL)                 /*!< DS83 (Bitfield-Mask: 0x03)                            */
32805 #define GPIO_PINCFG83_OUTCFG83_Pos        (8UL)                     /*!< OUTCFG83 (Bit 8)                                      */
32806 #define GPIO_PINCFG83_OUTCFG83_Msk        (0x300UL)                 /*!< OUTCFG83 (Bitfield-Mask: 0x03)                        */
32807 #define GPIO_PINCFG83_IRPTEN83_Pos        (6UL)                     /*!< IRPTEN83 (Bit 6)                                      */
32808 #define GPIO_PINCFG83_IRPTEN83_Msk        (0xc0UL)                  /*!< IRPTEN83 (Bitfield-Mask: 0x03)                        */
32809 #define GPIO_PINCFG83_RDZERO83_Pos        (5UL)                     /*!< RDZERO83 (Bit 5)                                      */
32810 #define GPIO_PINCFG83_RDZERO83_Msk        (0x20UL)                  /*!< RDZERO83 (Bitfield-Mask: 0x01)                        */
32811 #define GPIO_PINCFG83_INPEN83_Pos         (4UL)                     /*!< INPEN83 (Bit 4)                                       */
32812 #define GPIO_PINCFG83_INPEN83_Msk         (0x10UL)                  /*!< INPEN83 (Bitfield-Mask: 0x01)                         */
32813 #define GPIO_PINCFG83_FNCSEL83_Pos        (0UL)                     /*!< FNCSEL83 (Bit 0)                                      */
32814 #define GPIO_PINCFG83_FNCSEL83_Msk        (0xfUL)                   /*!< FNCSEL83 (Bitfield-Mask: 0x0f)                        */
32815 /* =======================================================  PINCFG84  ======================================================== */
32816 #define GPIO_PINCFG84_FOEN84_Pos          (27UL)                    /*!< FOEN84 (Bit 27)                                       */
32817 #define GPIO_PINCFG84_FOEN84_Msk          (0x8000000UL)             /*!< FOEN84 (Bitfield-Mask: 0x01)                          */
32818 #define GPIO_PINCFG84_FIEN84_Pos          (26UL)                    /*!< FIEN84 (Bit 26)                                       */
32819 #define GPIO_PINCFG84_FIEN84_Msk          (0x4000000UL)             /*!< FIEN84 (Bitfield-Mask: 0x01)                          */
32820 #define GPIO_PINCFG84_NCEPOL84_Pos        (22UL)                    /*!< NCEPOL84 (Bit 22)                                     */
32821 #define GPIO_PINCFG84_NCEPOL84_Msk        (0x400000UL)              /*!< NCEPOL84 (Bitfield-Mask: 0x01)                        */
32822 #define GPIO_PINCFG84_NCESRC84_Pos        (16UL)                    /*!< NCESRC84 (Bit 16)                                     */
32823 #define GPIO_PINCFG84_NCESRC84_Msk        (0x3f0000UL)              /*!< NCESRC84 (Bitfield-Mask: 0x3f)                        */
32824 #define GPIO_PINCFG84_PULLCFG84_Pos       (13UL)                    /*!< PULLCFG84 (Bit 13)                                    */
32825 #define GPIO_PINCFG84_PULLCFG84_Msk       (0xe000UL)                /*!< PULLCFG84 (Bitfield-Mask: 0x07)                       */
32826 #define GPIO_PINCFG84_SR84_Pos            (12UL)                    /*!< SR84 (Bit 12)                                         */
32827 #define GPIO_PINCFG84_SR84_Msk            (0x1000UL)                /*!< SR84 (Bitfield-Mask: 0x01)                            */
32828 #define GPIO_PINCFG84_DS84_Pos            (10UL)                    /*!< DS84 (Bit 10)                                         */
32829 #define GPIO_PINCFG84_DS84_Msk            (0xc00UL)                 /*!< DS84 (Bitfield-Mask: 0x03)                            */
32830 #define GPIO_PINCFG84_OUTCFG84_Pos        (8UL)                     /*!< OUTCFG84 (Bit 8)                                      */
32831 #define GPIO_PINCFG84_OUTCFG84_Msk        (0x300UL)                 /*!< OUTCFG84 (Bitfield-Mask: 0x03)                        */
32832 #define GPIO_PINCFG84_IRPTEN84_Pos        (6UL)                     /*!< IRPTEN84 (Bit 6)                                      */
32833 #define GPIO_PINCFG84_IRPTEN84_Msk        (0xc0UL)                  /*!< IRPTEN84 (Bitfield-Mask: 0x03)                        */
32834 #define GPIO_PINCFG84_RDZERO84_Pos        (5UL)                     /*!< RDZERO84 (Bit 5)                                      */
32835 #define GPIO_PINCFG84_RDZERO84_Msk        (0x20UL)                  /*!< RDZERO84 (Bitfield-Mask: 0x01)                        */
32836 #define GPIO_PINCFG84_INPEN84_Pos         (4UL)                     /*!< INPEN84 (Bit 4)                                       */
32837 #define GPIO_PINCFG84_INPEN84_Msk         (0x10UL)                  /*!< INPEN84 (Bitfield-Mask: 0x01)                         */
32838 #define GPIO_PINCFG84_FNCSEL84_Pos        (0UL)                     /*!< FNCSEL84 (Bit 0)                                      */
32839 #define GPIO_PINCFG84_FNCSEL84_Msk        (0xfUL)                   /*!< FNCSEL84 (Bitfield-Mask: 0x0f)                        */
32840 /* =======================================================  PINCFG85  ======================================================== */
32841 #define GPIO_PINCFG85_FOEN85_Pos          (27UL)                    /*!< FOEN85 (Bit 27)                                       */
32842 #define GPIO_PINCFG85_FOEN85_Msk          (0x8000000UL)             /*!< FOEN85 (Bitfield-Mask: 0x01)                          */
32843 #define GPIO_PINCFG85_FIEN85_Pos          (26UL)                    /*!< FIEN85 (Bit 26)                                       */
32844 #define GPIO_PINCFG85_FIEN85_Msk          (0x4000000UL)             /*!< FIEN85 (Bitfield-Mask: 0x01)                          */
32845 #define GPIO_PINCFG85_NCEPOL85_Pos        (22UL)                    /*!< NCEPOL85 (Bit 22)                                     */
32846 #define GPIO_PINCFG85_NCEPOL85_Msk        (0x400000UL)              /*!< NCEPOL85 (Bitfield-Mask: 0x01)                        */
32847 #define GPIO_PINCFG85_NCESRC85_Pos        (16UL)                    /*!< NCESRC85 (Bit 16)                                     */
32848 #define GPIO_PINCFG85_NCESRC85_Msk        (0x3f0000UL)              /*!< NCESRC85 (Bitfield-Mask: 0x3f)                        */
32849 #define GPIO_PINCFG85_PULLCFG85_Pos       (13UL)                    /*!< PULLCFG85 (Bit 13)                                    */
32850 #define GPIO_PINCFG85_PULLCFG85_Msk       (0xe000UL)                /*!< PULLCFG85 (Bitfield-Mask: 0x07)                       */
32851 #define GPIO_PINCFG85_SR85_Pos            (12UL)                    /*!< SR85 (Bit 12)                                         */
32852 #define GPIO_PINCFG85_SR85_Msk            (0x1000UL)                /*!< SR85 (Bitfield-Mask: 0x01)                            */
32853 #define GPIO_PINCFG85_DS85_Pos            (10UL)                    /*!< DS85 (Bit 10)                                         */
32854 #define GPIO_PINCFG85_DS85_Msk            (0xc00UL)                 /*!< DS85 (Bitfield-Mask: 0x03)                            */
32855 #define GPIO_PINCFG85_OUTCFG85_Pos        (8UL)                     /*!< OUTCFG85 (Bit 8)                                      */
32856 #define GPIO_PINCFG85_OUTCFG85_Msk        (0x300UL)                 /*!< OUTCFG85 (Bitfield-Mask: 0x03)                        */
32857 #define GPIO_PINCFG85_IRPTEN85_Pos        (6UL)                     /*!< IRPTEN85 (Bit 6)                                      */
32858 #define GPIO_PINCFG85_IRPTEN85_Msk        (0xc0UL)                  /*!< IRPTEN85 (Bitfield-Mask: 0x03)                        */
32859 #define GPIO_PINCFG85_RDZERO85_Pos        (5UL)                     /*!< RDZERO85 (Bit 5)                                      */
32860 #define GPIO_PINCFG85_RDZERO85_Msk        (0x20UL)                  /*!< RDZERO85 (Bitfield-Mask: 0x01)                        */
32861 #define GPIO_PINCFG85_INPEN85_Pos         (4UL)                     /*!< INPEN85 (Bit 4)                                       */
32862 #define GPIO_PINCFG85_INPEN85_Msk         (0x10UL)                  /*!< INPEN85 (Bitfield-Mask: 0x01)                         */
32863 #define GPIO_PINCFG85_FNCSEL85_Pos        (0UL)                     /*!< FNCSEL85 (Bit 0)                                      */
32864 #define GPIO_PINCFG85_FNCSEL85_Msk        (0xfUL)                   /*!< FNCSEL85 (Bitfield-Mask: 0x0f)                        */
32865 /* =======================================================  PINCFG86  ======================================================== */
32866 #define GPIO_PINCFG86_FOEN86_Pos          (27UL)                    /*!< FOEN86 (Bit 27)                                       */
32867 #define GPIO_PINCFG86_FOEN86_Msk          (0x8000000UL)             /*!< FOEN86 (Bitfield-Mask: 0x01)                          */
32868 #define GPIO_PINCFG86_FIEN86_Pos          (26UL)                    /*!< FIEN86 (Bit 26)                                       */
32869 #define GPIO_PINCFG86_FIEN86_Msk          (0x4000000UL)             /*!< FIEN86 (Bitfield-Mask: 0x01)                          */
32870 #define GPIO_PINCFG86_NCEPOL86_Pos        (22UL)                    /*!< NCEPOL86 (Bit 22)                                     */
32871 #define GPIO_PINCFG86_NCEPOL86_Msk        (0x400000UL)              /*!< NCEPOL86 (Bitfield-Mask: 0x01)                        */
32872 #define GPIO_PINCFG86_NCESRC86_Pos        (16UL)                    /*!< NCESRC86 (Bit 16)                                     */
32873 #define GPIO_PINCFG86_NCESRC86_Msk        (0x3f0000UL)              /*!< NCESRC86 (Bitfield-Mask: 0x3f)                        */
32874 #define GPIO_PINCFG86_PULLCFG86_Pos       (13UL)                    /*!< PULLCFG86 (Bit 13)                                    */
32875 #define GPIO_PINCFG86_PULLCFG86_Msk       (0xe000UL)                /*!< PULLCFG86 (Bitfield-Mask: 0x07)                       */
32876 #define GPIO_PINCFG86_SR86_Pos            (12UL)                    /*!< SR86 (Bit 12)                                         */
32877 #define GPIO_PINCFG86_SR86_Msk            (0x1000UL)                /*!< SR86 (Bitfield-Mask: 0x01)                            */
32878 #define GPIO_PINCFG86_DS86_Pos            (10UL)                    /*!< DS86 (Bit 10)                                         */
32879 #define GPIO_PINCFG86_DS86_Msk            (0xc00UL)                 /*!< DS86 (Bitfield-Mask: 0x03)                            */
32880 #define GPIO_PINCFG86_OUTCFG86_Pos        (8UL)                     /*!< OUTCFG86 (Bit 8)                                      */
32881 #define GPIO_PINCFG86_OUTCFG86_Msk        (0x300UL)                 /*!< OUTCFG86 (Bitfield-Mask: 0x03)                        */
32882 #define GPIO_PINCFG86_IRPTEN86_Pos        (6UL)                     /*!< IRPTEN86 (Bit 6)                                      */
32883 #define GPIO_PINCFG86_IRPTEN86_Msk        (0xc0UL)                  /*!< IRPTEN86 (Bitfield-Mask: 0x03)                        */
32884 #define GPIO_PINCFG86_RDZERO86_Pos        (5UL)                     /*!< RDZERO86 (Bit 5)                                      */
32885 #define GPIO_PINCFG86_RDZERO86_Msk        (0x20UL)                  /*!< RDZERO86 (Bitfield-Mask: 0x01)                        */
32886 #define GPIO_PINCFG86_INPEN86_Pos         (4UL)                     /*!< INPEN86 (Bit 4)                                       */
32887 #define GPIO_PINCFG86_INPEN86_Msk         (0x10UL)                  /*!< INPEN86 (Bitfield-Mask: 0x01)                         */
32888 #define GPIO_PINCFG86_FNCSEL86_Pos        (0UL)                     /*!< FNCSEL86 (Bit 0)                                      */
32889 #define GPIO_PINCFG86_FNCSEL86_Msk        (0xfUL)                   /*!< FNCSEL86 (Bitfield-Mask: 0x0f)                        */
32890 /* =======================================================  PINCFG87  ======================================================== */
32891 #define GPIO_PINCFG87_FOEN87_Pos          (27UL)                    /*!< FOEN87 (Bit 27)                                       */
32892 #define GPIO_PINCFG87_FOEN87_Msk          (0x8000000UL)             /*!< FOEN87 (Bitfield-Mask: 0x01)                          */
32893 #define GPIO_PINCFG87_FIEN87_Pos          (26UL)                    /*!< FIEN87 (Bit 26)                                       */
32894 #define GPIO_PINCFG87_FIEN87_Msk          (0x4000000UL)             /*!< FIEN87 (Bitfield-Mask: 0x01)                          */
32895 #define GPIO_PINCFG87_NCEPOL87_Pos        (22UL)                    /*!< NCEPOL87 (Bit 22)                                     */
32896 #define GPIO_PINCFG87_NCEPOL87_Msk        (0x400000UL)              /*!< NCEPOL87 (Bitfield-Mask: 0x01)                        */
32897 #define GPIO_PINCFG87_NCESRC87_Pos        (16UL)                    /*!< NCESRC87 (Bit 16)                                     */
32898 #define GPIO_PINCFG87_NCESRC87_Msk        (0x3f0000UL)              /*!< NCESRC87 (Bitfield-Mask: 0x3f)                        */
32899 #define GPIO_PINCFG87_PULLCFG87_Pos       (13UL)                    /*!< PULLCFG87 (Bit 13)                                    */
32900 #define GPIO_PINCFG87_PULLCFG87_Msk       (0xe000UL)                /*!< PULLCFG87 (Bitfield-Mask: 0x07)                       */
32901 #define GPIO_PINCFG87_SR87_Pos            (12UL)                    /*!< SR87 (Bit 12)                                         */
32902 #define GPIO_PINCFG87_SR87_Msk            (0x1000UL)                /*!< SR87 (Bitfield-Mask: 0x01)                            */
32903 #define GPIO_PINCFG87_DS87_Pos            (10UL)                    /*!< DS87 (Bit 10)                                         */
32904 #define GPIO_PINCFG87_DS87_Msk            (0xc00UL)                 /*!< DS87 (Bitfield-Mask: 0x03)                            */
32905 #define GPIO_PINCFG87_OUTCFG87_Pos        (8UL)                     /*!< OUTCFG87 (Bit 8)                                      */
32906 #define GPIO_PINCFG87_OUTCFG87_Msk        (0x300UL)                 /*!< OUTCFG87 (Bitfield-Mask: 0x03)                        */
32907 #define GPIO_PINCFG87_IRPTEN87_Pos        (6UL)                     /*!< IRPTEN87 (Bit 6)                                      */
32908 #define GPIO_PINCFG87_IRPTEN87_Msk        (0xc0UL)                  /*!< IRPTEN87 (Bitfield-Mask: 0x03)                        */
32909 #define GPIO_PINCFG87_RDZERO87_Pos        (5UL)                     /*!< RDZERO87 (Bit 5)                                      */
32910 #define GPIO_PINCFG87_RDZERO87_Msk        (0x20UL)                  /*!< RDZERO87 (Bitfield-Mask: 0x01)                        */
32911 #define GPIO_PINCFG87_INPEN87_Pos         (4UL)                     /*!< INPEN87 (Bit 4)                                       */
32912 #define GPIO_PINCFG87_INPEN87_Msk         (0x10UL)                  /*!< INPEN87 (Bitfield-Mask: 0x01)                         */
32913 #define GPIO_PINCFG87_FNCSEL87_Pos        (0UL)                     /*!< FNCSEL87 (Bit 0)                                      */
32914 #define GPIO_PINCFG87_FNCSEL87_Msk        (0xfUL)                   /*!< FNCSEL87 (Bitfield-Mask: 0x0f)                        */
32915 /* =======================================================  PINCFG88  ======================================================== */
32916 #define GPIO_PINCFG88_FOEN88_Pos          (27UL)                    /*!< FOEN88 (Bit 27)                                       */
32917 #define GPIO_PINCFG88_FOEN88_Msk          (0x8000000UL)             /*!< FOEN88 (Bitfield-Mask: 0x01)                          */
32918 #define GPIO_PINCFG88_FIEN88_Pos          (26UL)                    /*!< FIEN88 (Bit 26)                                       */
32919 #define GPIO_PINCFG88_FIEN88_Msk          (0x4000000UL)             /*!< FIEN88 (Bitfield-Mask: 0x01)                          */
32920 #define GPIO_PINCFG88_NCEPOL88_Pos        (22UL)                    /*!< NCEPOL88 (Bit 22)                                     */
32921 #define GPIO_PINCFG88_NCEPOL88_Msk        (0x400000UL)              /*!< NCEPOL88 (Bitfield-Mask: 0x01)                        */
32922 #define GPIO_PINCFG88_NCESRC88_Pos        (16UL)                    /*!< NCESRC88 (Bit 16)                                     */
32923 #define GPIO_PINCFG88_NCESRC88_Msk        (0x3f0000UL)              /*!< NCESRC88 (Bitfield-Mask: 0x3f)                        */
32924 #define GPIO_PINCFG88_PULLCFG88_Pos       (13UL)                    /*!< PULLCFG88 (Bit 13)                                    */
32925 #define GPIO_PINCFG88_PULLCFG88_Msk       (0xe000UL)                /*!< PULLCFG88 (Bitfield-Mask: 0x07)                       */
32926 #define GPIO_PINCFG88_SR88_Pos            (12UL)                    /*!< SR88 (Bit 12)                                         */
32927 #define GPIO_PINCFG88_SR88_Msk            (0x1000UL)                /*!< SR88 (Bitfield-Mask: 0x01)                            */
32928 #define GPIO_PINCFG88_DS88_Pos            (10UL)                    /*!< DS88 (Bit 10)                                         */
32929 #define GPIO_PINCFG88_DS88_Msk            (0xc00UL)                 /*!< DS88 (Bitfield-Mask: 0x03)                            */
32930 #define GPIO_PINCFG88_OUTCFG88_Pos        (8UL)                     /*!< OUTCFG88 (Bit 8)                                      */
32931 #define GPIO_PINCFG88_OUTCFG88_Msk        (0x300UL)                 /*!< OUTCFG88 (Bitfield-Mask: 0x03)                        */
32932 #define GPIO_PINCFG88_IRPTEN88_Pos        (6UL)                     /*!< IRPTEN88 (Bit 6)                                      */
32933 #define GPIO_PINCFG88_IRPTEN88_Msk        (0xc0UL)                  /*!< IRPTEN88 (Bitfield-Mask: 0x03)                        */
32934 #define GPIO_PINCFG88_RDZERO88_Pos        (5UL)                     /*!< RDZERO88 (Bit 5)                                      */
32935 #define GPIO_PINCFG88_RDZERO88_Msk        (0x20UL)                  /*!< RDZERO88 (Bitfield-Mask: 0x01)                        */
32936 #define GPIO_PINCFG88_INPEN88_Pos         (4UL)                     /*!< INPEN88 (Bit 4)                                       */
32937 #define GPIO_PINCFG88_INPEN88_Msk         (0x10UL)                  /*!< INPEN88 (Bitfield-Mask: 0x01)                         */
32938 #define GPIO_PINCFG88_FNCSEL88_Pos        (0UL)                     /*!< FNCSEL88 (Bit 0)                                      */
32939 #define GPIO_PINCFG88_FNCSEL88_Msk        (0xfUL)                   /*!< FNCSEL88 (Bitfield-Mask: 0x0f)                        */
32940 /* =======================================================  PINCFG89  ======================================================== */
32941 #define GPIO_PINCFG89_FOEN89_Pos          (27UL)                    /*!< FOEN89 (Bit 27)                                       */
32942 #define GPIO_PINCFG89_FOEN89_Msk          (0x8000000UL)             /*!< FOEN89 (Bitfield-Mask: 0x01)                          */
32943 #define GPIO_PINCFG89_FIEN89_Pos          (26UL)                    /*!< FIEN89 (Bit 26)                                       */
32944 #define GPIO_PINCFG89_FIEN89_Msk          (0x4000000UL)             /*!< FIEN89 (Bitfield-Mask: 0x01)                          */
32945 #define GPIO_PINCFG89_NCEPOL89_Pos        (22UL)                    /*!< NCEPOL89 (Bit 22)                                     */
32946 #define GPIO_PINCFG89_NCEPOL89_Msk        (0x400000UL)              /*!< NCEPOL89 (Bitfield-Mask: 0x01)                        */
32947 #define GPIO_PINCFG89_NCESRC89_Pos        (16UL)                    /*!< NCESRC89 (Bit 16)                                     */
32948 #define GPIO_PINCFG89_NCESRC89_Msk        (0x3f0000UL)              /*!< NCESRC89 (Bitfield-Mask: 0x3f)                        */
32949 #define GPIO_PINCFG89_PULLCFG89_Pos       (13UL)                    /*!< PULLCFG89 (Bit 13)                                    */
32950 #define GPIO_PINCFG89_PULLCFG89_Msk       (0xe000UL)                /*!< PULLCFG89 (Bitfield-Mask: 0x07)                       */
32951 #define GPIO_PINCFG89_SR89_Pos            (12UL)                    /*!< SR89 (Bit 12)                                         */
32952 #define GPIO_PINCFG89_SR89_Msk            (0x1000UL)                /*!< SR89 (Bitfield-Mask: 0x01)                            */
32953 #define GPIO_PINCFG89_DS89_Pos            (10UL)                    /*!< DS89 (Bit 10)                                         */
32954 #define GPIO_PINCFG89_DS89_Msk            (0xc00UL)                 /*!< DS89 (Bitfield-Mask: 0x03)                            */
32955 #define GPIO_PINCFG89_OUTCFG89_Pos        (8UL)                     /*!< OUTCFG89 (Bit 8)                                      */
32956 #define GPIO_PINCFG89_OUTCFG89_Msk        (0x300UL)                 /*!< OUTCFG89 (Bitfield-Mask: 0x03)                        */
32957 #define GPIO_PINCFG89_IRPTEN89_Pos        (6UL)                     /*!< IRPTEN89 (Bit 6)                                      */
32958 #define GPIO_PINCFG89_IRPTEN89_Msk        (0xc0UL)                  /*!< IRPTEN89 (Bitfield-Mask: 0x03)                        */
32959 #define GPIO_PINCFG89_RDZERO89_Pos        (5UL)                     /*!< RDZERO89 (Bit 5)                                      */
32960 #define GPIO_PINCFG89_RDZERO89_Msk        (0x20UL)                  /*!< RDZERO89 (Bitfield-Mask: 0x01)                        */
32961 #define GPIO_PINCFG89_INPEN89_Pos         (4UL)                     /*!< INPEN89 (Bit 4)                                       */
32962 #define GPIO_PINCFG89_INPEN89_Msk         (0x10UL)                  /*!< INPEN89 (Bitfield-Mask: 0x01)                         */
32963 #define GPIO_PINCFG89_FNCSEL89_Pos        (0UL)                     /*!< FNCSEL89 (Bit 0)                                      */
32964 #define GPIO_PINCFG89_FNCSEL89_Msk        (0xfUL)                   /*!< FNCSEL89 (Bitfield-Mask: 0x0f)                        */
32965 /* =======================================================  PINCFG90  ======================================================== */
32966 #define GPIO_PINCFG90_FOEN90_Pos          (27UL)                    /*!< FOEN90 (Bit 27)                                       */
32967 #define GPIO_PINCFG90_FOEN90_Msk          (0x8000000UL)             /*!< FOEN90 (Bitfield-Mask: 0x01)                          */
32968 #define GPIO_PINCFG90_FIEN90_Pos          (26UL)                    /*!< FIEN90 (Bit 26)                                       */
32969 #define GPIO_PINCFG90_FIEN90_Msk          (0x4000000UL)             /*!< FIEN90 (Bitfield-Mask: 0x01)                          */
32970 #define GPIO_PINCFG90_NCEPOL90_Pos        (22UL)                    /*!< NCEPOL90 (Bit 22)                                     */
32971 #define GPIO_PINCFG90_NCEPOL90_Msk        (0x400000UL)              /*!< NCEPOL90 (Bitfield-Mask: 0x01)                        */
32972 #define GPIO_PINCFG90_NCESRC90_Pos        (16UL)                    /*!< NCESRC90 (Bit 16)                                     */
32973 #define GPIO_PINCFG90_NCESRC90_Msk        (0x3f0000UL)              /*!< NCESRC90 (Bitfield-Mask: 0x3f)                        */
32974 #define GPIO_PINCFG90_PULLCFG90_Pos       (13UL)                    /*!< PULLCFG90 (Bit 13)                                    */
32975 #define GPIO_PINCFG90_PULLCFG90_Msk       (0xe000UL)                /*!< PULLCFG90 (Bitfield-Mask: 0x07)                       */
32976 #define GPIO_PINCFG90_SR90_Pos            (12UL)                    /*!< SR90 (Bit 12)                                         */
32977 #define GPIO_PINCFG90_SR90_Msk            (0x1000UL)                /*!< SR90 (Bitfield-Mask: 0x01)                            */
32978 #define GPIO_PINCFG90_DS90_Pos            (10UL)                    /*!< DS90 (Bit 10)                                         */
32979 #define GPIO_PINCFG90_DS90_Msk            (0xc00UL)                 /*!< DS90 (Bitfield-Mask: 0x03)                            */
32980 #define GPIO_PINCFG90_OUTCFG90_Pos        (8UL)                     /*!< OUTCFG90 (Bit 8)                                      */
32981 #define GPIO_PINCFG90_OUTCFG90_Msk        (0x300UL)                 /*!< OUTCFG90 (Bitfield-Mask: 0x03)                        */
32982 #define GPIO_PINCFG90_IRPTEN90_Pos        (6UL)                     /*!< IRPTEN90 (Bit 6)                                      */
32983 #define GPIO_PINCFG90_IRPTEN90_Msk        (0xc0UL)                  /*!< IRPTEN90 (Bitfield-Mask: 0x03)                        */
32984 #define GPIO_PINCFG90_RDZERO90_Pos        (5UL)                     /*!< RDZERO90 (Bit 5)                                      */
32985 #define GPIO_PINCFG90_RDZERO90_Msk        (0x20UL)                  /*!< RDZERO90 (Bitfield-Mask: 0x01)                        */
32986 #define GPIO_PINCFG90_INPEN90_Pos         (4UL)                     /*!< INPEN90 (Bit 4)                                       */
32987 #define GPIO_PINCFG90_INPEN90_Msk         (0x10UL)                  /*!< INPEN90 (Bitfield-Mask: 0x01)                         */
32988 #define GPIO_PINCFG90_FNCSEL90_Pos        (0UL)                     /*!< FNCSEL90 (Bit 0)                                      */
32989 #define GPIO_PINCFG90_FNCSEL90_Msk        (0xfUL)                   /*!< FNCSEL90 (Bitfield-Mask: 0x0f)                        */
32990 /* =======================================================  PINCFG91  ======================================================== */
32991 #define GPIO_PINCFG91_FOEN91_Pos          (27UL)                    /*!< FOEN91 (Bit 27)                                       */
32992 #define GPIO_PINCFG91_FOEN91_Msk          (0x8000000UL)             /*!< FOEN91 (Bitfield-Mask: 0x01)                          */
32993 #define GPIO_PINCFG91_FIEN91_Pos          (26UL)                    /*!< FIEN91 (Bit 26)                                       */
32994 #define GPIO_PINCFG91_FIEN91_Msk          (0x4000000UL)             /*!< FIEN91 (Bitfield-Mask: 0x01)                          */
32995 #define GPIO_PINCFG91_NCEPOL91_Pos        (22UL)                    /*!< NCEPOL91 (Bit 22)                                     */
32996 #define GPIO_PINCFG91_NCEPOL91_Msk        (0x400000UL)              /*!< NCEPOL91 (Bitfield-Mask: 0x01)                        */
32997 #define GPIO_PINCFG91_NCESRC91_Pos        (16UL)                    /*!< NCESRC91 (Bit 16)                                     */
32998 #define GPIO_PINCFG91_NCESRC91_Msk        (0x3f0000UL)              /*!< NCESRC91 (Bitfield-Mask: 0x3f)                        */
32999 #define GPIO_PINCFG91_PULLCFG91_Pos       (13UL)                    /*!< PULLCFG91 (Bit 13)                                    */
33000 #define GPIO_PINCFG91_PULLCFG91_Msk       (0xe000UL)                /*!< PULLCFG91 (Bitfield-Mask: 0x07)                       */
33001 #define GPIO_PINCFG91_SR91_Pos            (12UL)                    /*!< SR91 (Bit 12)                                         */
33002 #define GPIO_PINCFG91_SR91_Msk            (0x1000UL)                /*!< SR91 (Bitfield-Mask: 0x01)                            */
33003 #define GPIO_PINCFG91_DS91_Pos            (10UL)                    /*!< DS91 (Bit 10)                                         */
33004 #define GPIO_PINCFG91_DS91_Msk            (0xc00UL)                 /*!< DS91 (Bitfield-Mask: 0x03)                            */
33005 #define GPIO_PINCFG91_OUTCFG91_Pos        (8UL)                     /*!< OUTCFG91 (Bit 8)                                      */
33006 #define GPIO_PINCFG91_OUTCFG91_Msk        (0x300UL)                 /*!< OUTCFG91 (Bitfield-Mask: 0x03)                        */
33007 #define GPIO_PINCFG91_IRPTEN91_Pos        (6UL)                     /*!< IRPTEN91 (Bit 6)                                      */
33008 #define GPIO_PINCFG91_IRPTEN91_Msk        (0xc0UL)                  /*!< IRPTEN91 (Bitfield-Mask: 0x03)                        */
33009 #define GPIO_PINCFG91_RDZERO91_Pos        (5UL)                     /*!< RDZERO91 (Bit 5)                                      */
33010 #define GPIO_PINCFG91_RDZERO91_Msk        (0x20UL)                  /*!< RDZERO91 (Bitfield-Mask: 0x01)                        */
33011 #define GPIO_PINCFG91_INPEN91_Pos         (4UL)                     /*!< INPEN91 (Bit 4)                                       */
33012 #define GPIO_PINCFG91_INPEN91_Msk         (0x10UL)                  /*!< INPEN91 (Bitfield-Mask: 0x01)                         */
33013 #define GPIO_PINCFG91_FNCSEL91_Pos        (0UL)                     /*!< FNCSEL91 (Bit 0)                                      */
33014 #define GPIO_PINCFG91_FNCSEL91_Msk        (0xfUL)                   /*!< FNCSEL91 (Bitfield-Mask: 0x0f)                        */
33015 /* =======================================================  PINCFG92  ======================================================== */
33016 #define GPIO_PINCFG92_FOEN92_Pos          (27UL)                    /*!< FOEN92 (Bit 27)                                       */
33017 #define GPIO_PINCFG92_FOEN92_Msk          (0x8000000UL)             /*!< FOEN92 (Bitfield-Mask: 0x01)                          */
33018 #define GPIO_PINCFG92_FIEN92_Pos          (26UL)                    /*!< FIEN92 (Bit 26)                                       */
33019 #define GPIO_PINCFG92_FIEN92_Msk          (0x4000000UL)             /*!< FIEN92 (Bitfield-Mask: 0x01)                          */
33020 #define GPIO_PINCFG92_NCEPOL92_Pos        (22UL)                    /*!< NCEPOL92 (Bit 22)                                     */
33021 #define GPIO_PINCFG92_NCEPOL92_Msk        (0x400000UL)              /*!< NCEPOL92 (Bitfield-Mask: 0x01)                        */
33022 #define GPIO_PINCFG92_NCESRC92_Pos        (16UL)                    /*!< NCESRC92 (Bit 16)                                     */
33023 #define GPIO_PINCFG92_NCESRC92_Msk        (0x3f0000UL)              /*!< NCESRC92 (Bitfield-Mask: 0x3f)                        */
33024 #define GPIO_PINCFG92_PULLCFG92_Pos       (13UL)                    /*!< PULLCFG92 (Bit 13)                                    */
33025 #define GPIO_PINCFG92_PULLCFG92_Msk       (0xe000UL)                /*!< PULLCFG92 (Bitfield-Mask: 0x07)                       */
33026 #define GPIO_PINCFG92_SR92_Pos            (12UL)                    /*!< SR92 (Bit 12)                                         */
33027 #define GPIO_PINCFG92_SR92_Msk            (0x1000UL)                /*!< SR92 (Bitfield-Mask: 0x01)                            */
33028 #define GPIO_PINCFG92_DS92_Pos            (10UL)                    /*!< DS92 (Bit 10)                                         */
33029 #define GPIO_PINCFG92_DS92_Msk            (0xc00UL)                 /*!< DS92 (Bitfield-Mask: 0x03)                            */
33030 #define GPIO_PINCFG92_OUTCFG92_Pos        (8UL)                     /*!< OUTCFG92 (Bit 8)                                      */
33031 #define GPIO_PINCFG92_OUTCFG92_Msk        (0x300UL)                 /*!< OUTCFG92 (Bitfield-Mask: 0x03)                        */
33032 #define GPIO_PINCFG92_IRPTEN92_Pos        (6UL)                     /*!< IRPTEN92 (Bit 6)                                      */
33033 #define GPIO_PINCFG92_IRPTEN92_Msk        (0xc0UL)                  /*!< IRPTEN92 (Bitfield-Mask: 0x03)                        */
33034 #define GPIO_PINCFG92_RDZERO92_Pos        (5UL)                     /*!< RDZERO92 (Bit 5)                                      */
33035 #define GPIO_PINCFG92_RDZERO92_Msk        (0x20UL)                  /*!< RDZERO92 (Bitfield-Mask: 0x01)                        */
33036 #define GPIO_PINCFG92_INPEN92_Pos         (4UL)                     /*!< INPEN92 (Bit 4)                                       */
33037 #define GPIO_PINCFG92_INPEN92_Msk         (0x10UL)                  /*!< INPEN92 (Bitfield-Mask: 0x01)                         */
33038 #define GPIO_PINCFG92_FNCSEL92_Pos        (0UL)                     /*!< FNCSEL92 (Bit 0)                                      */
33039 #define GPIO_PINCFG92_FNCSEL92_Msk        (0xfUL)                   /*!< FNCSEL92 (Bitfield-Mask: 0x0f)                        */
33040 /* =======================================================  PINCFG93  ======================================================== */
33041 #define GPIO_PINCFG93_FOEN93_Pos          (27UL)                    /*!< FOEN93 (Bit 27)                                       */
33042 #define GPIO_PINCFG93_FOEN93_Msk          (0x8000000UL)             /*!< FOEN93 (Bitfield-Mask: 0x01)                          */
33043 #define GPIO_PINCFG93_FIEN93_Pos          (26UL)                    /*!< FIEN93 (Bit 26)                                       */
33044 #define GPIO_PINCFG93_FIEN93_Msk          (0x4000000UL)             /*!< FIEN93 (Bitfield-Mask: 0x01)                          */
33045 #define GPIO_PINCFG93_NCEPOL93_Pos        (22UL)                    /*!< NCEPOL93 (Bit 22)                                     */
33046 #define GPIO_PINCFG93_NCEPOL93_Msk        (0x400000UL)              /*!< NCEPOL93 (Bitfield-Mask: 0x01)                        */
33047 #define GPIO_PINCFG93_NCESRC93_Pos        (16UL)                    /*!< NCESRC93 (Bit 16)                                     */
33048 #define GPIO_PINCFG93_NCESRC93_Msk        (0x3f0000UL)              /*!< NCESRC93 (Bitfield-Mask: 0x3f)                        */
33049 #define GPIO_PINCFG93_PULLCFG93_Pos       (13UL)                    /*!< PULLCFG93 (Bit 13)                                    */
33050 #define GPIO_PINCFG93_PULLCFG93_Msk       (0xe000UL)                /*!< PULLCFG93 (Bitfield-Mask: 0x07)                       */
33051 #define GPIO_PINCFG93_SR93_Pos            (12UL)                    /*!< SR93 (Bit 12)                                         */
33052 #define GPIO_PINCFG93_SR93_Msk            (0x1000UL)                /*!< SR93 (Bitfield-Mask: 0x01)                            */
33053 #define GPIO_PINCFG93_DS93_Pos            (10UL)                    /*!< DS93 (Bit 10)                                         */
33054 #define GPIO_PINCFG93_DS93_Msk            (0xc00UL)                 /*!< DS93 (Bitfield-Mask: 0x03)                            */
33055 #define GPIO_PINCFG93_OUTCFG93_Pos        (8UL)                     /*!< OUTCFG93 (Bit 8)                                      */
33056 #define GPIO_PINCFG93_OUTCFG93_Msk        (0x300UL)                 /*!< OUTCFG93 (Bitfield-Mask: 0x03)                        */
33057 #define GPIO_PINCFG93_IRPTEN93_Pos        (6UL)                     /*!< IRPTEN93 (Bit 6)                                      */
33058 #define GPIO_PINCFG93_IRPTEN93_Msk        (0xc0UL)                  /*!< IRPTEN93 (Bitfield-Mask: 0x03)                        */
33059 #define GPIO_PINCFG93_RDZERO93_Pos        (5UL)                     /*!< RDZERO93 (Bit 5)                                      */
33060 #define GPIO_PINCFG93_RDZERO93_Msk        (0x20UL)                  /*!< RDZERO93 (Bitfield-Mask: 0x01)                        */
33061 #define GPIO_PINCFG93_INPEN93_Pos         (4UL)                     /*!< INPEN93 (Bit 4)                                       */
33062 #define GPIO_PINCFG93_INPEN93_Msk         (0x10UL)                  /*!< INPEN93 (Bitfield-Mask: 0x01)                         */
33063 #define GPIO_PINCFG93_FNCSEL93_Pos        (0UL)                     /*!< FNCSEL93 (Bit 0)                                      */
33064 #define GPIO_PINCFG93_FNCSEL93_Msk        (0xfUL)                   /*!< FNCSEL93 (Bitfield-Mask: 0x0f)                        */
33065 /* =======================================================  PINCFG94  ======================================================== */
33066 #define GPIO_PINCFG94_FOEN94_Pos          (27UL)                    /*!< FOEN94 (Bit 27)                                       */
33067 #define GPIO_PINCFG94_FOEN94_Msk          (0x8000000UL)             /*!< FOEN94 (Bitfield-Mask: 0x01)                          */
33068 #define GPIO_PINCFG94_FIEN94_Pos          (26UL)                    /*!< FIEN94 (Bit 26)                                       */
33069 #define GPIO_PINCFG94_FIEN94_Msk          (0x4000000UL)             /*!< FIEN94 (Bitfield-Mask: 0x01)                          */
33070 #define GPIO_PINCFG94_NCEPOL94_Pos        (22UL)                    /*!< NCEPOL94 (Bit 22)                                     */
33071 #define GPIO_PINCFG94_NCEPOL94_Msk        (0x400000UL)              /*!< NCEPOL94 (Bitfield-Mask: 0x01)                        */
33072 #define GPIO_PINCFG94_NCESRC94_Pos        (16UL)                    /*!< NCESRC94 (Bit 16)                                     */
33073 #define GPIO_PINCFG94_NCESRC94_Msk        (0x3f0000UL)              /*!< NCESRC94 (Bitfield-Mask: 0x3f)                        */
33074 #define GPIO_PINCFG94_PULLCFG94_Pos       (13UL)                    /*!< PULLCFG94 (Bit 13)                                    */
33075 #define GPIO_PINCFG94_PULLCFG94_Msk       (0xe000UL)                /*!< PULLCFG94 (Bitfield-Mask: 0x07)                       */
33076 #define GPIO_PINCFG94_SR94_Pos            (12UL)                    /*!< SR94 (Bit 12)                                         */
33077 #define GPIO_PINCFG94_SR94_Msk            (0x1000UL)                /*!< SR94 (Bitfield-Mask: 0x01)                            */
33078 #define GPIO_PINCFG94_DS94_Pos            (10UL)                    /*!< DS94 (Bit 10)                                         */
33079 #define GPIO_PINCFG94_DS94_Msk            (0xc00UL)                 /*!< DS94 (Bitfield-Mask: 0x03)                            */
33080 #define GPIO_PINCFG94_OUTCFG94_Pos        (8UL)                     /*!< OUTCFG94 (Bit 8)                                      */
33081 #define GPIO_PINCFG94_OUTCFG94_Msk        (0x300UL)                 /*!< OUTCFG94 (Bitfield-Mask: 0x03)                        */
33082 #define GPIO_PINCFG94_IRPTEN94_Pos        (6UL)                     /*!< IRPTEN94 (Bit 6)                                      */
33083 #define GPIO_PINCFG94_IRPTEN94_Msk        (0xc0UL)                  /*!< IRPTEN94 (Bitfield-Mask: 0x03)                        */
33084 #define GPIO_PINCFG94_RDZERO94_Pos        (5UL)                     /*!< RDZERO94 (Bit 5)                                      */
33085 #define GPIO_PINCFG94_RDZERO94_Msk        (0x20UL)                  /*!< RDZERO94 (Bitfield-Mask: 0x01)                        */
33086 #define GPIO_PINCFG94_INPEN94_Pos         (4UL)                     /*!< INPEN94 (Bit 4)                                       */
33087 #define GPIO_PINCFG94_INPEN94_Msk         (0x10UL)                  /*!< INPEN94 (Bitfield-Mask: 0x01)                         */
33088 #define GPIO_PINCFG94_FNCSEL94_Pos        (0UL)                     /*!< FNCSEL94 (Bit 0)                                      */
33089 #define GPIO_PINCFG94_FNCSEL94_Msk        (0xfUL)                   /*!< FNCSEL94 (Bitfield-Mask: 0x0f)                        */
33090 /* =======================================================  PINCFG95  ======================================================== */
33091 #define GPIO_PINCFG95_FOEN95_Pos          (27UL)                    /*!< FOEN95 (Bit 27)                                       */
33092 #define GPIO_PINCFG95_FOEN95_Msk          (0x8000000UL)             /*!< FOEN95 (Bitfield-Mask: 0x01)                          */
33093 #define GPIO_PINCFG95_FIEN95_Pos          (26UL)                    /*!< FIEN95 (Bit 26)                                       */
33094 #define GPIO_PINCFG95_FIEN95_Msk          (0x4000000UL)             /*!< FIEN95 (Bitfield-Mask: 0x01)                          */
33095 #define GPIO_PINCFG95_NCEPOL95_Pos        (22UL)                    /*!< NCEPOL95 (Bit 22)                                     */
33096 #define GPIO_PINCFG95_NCEPOL95_Msk        (0x400000UL)              /*!< NCEPOL95 (Bitfield-Mask: 0x01)                        */
33097 #define GPIO_PINCFG95_NCESRC95_Pos        (16UL)                    /*!< NCESRC95 (Bit 16)                                     */
33098 #define GPIO_PINCFG95_NCESRC95_Msk        (0x3f0000UL)              /*!< NCESRC95 (Bitfield-Mask: 0x3f)                        */
33099 #define GPIO_PINCFG95_PULLCFG95_Pos       (13UL)                    /*!< PULLCFG95 (Bit 13)                                    */
33100 #define GPIO_PINCFG95_PULLCFG95_Msk       (0xe000UL)                /*!< PULLCFG95 (Bitfield-Mask: 0x07)                       */
33101 #define GPIO_PINCFG95_SR95_Pos            (12UL)                    /*!< SR95 (Bit 12)                                         */
33102 #define GPIO_PINCFG95_SR95_Msk            (0x1000UL)                /*!< SR95 (Bitfield-Mask: 0x01)                            */
33103 #define GPIO_PINCFG95_DS95_Pos            (10UL)                    /*!< DS95 (Bit 10)                                         */
33104 #define GPIO_PINCFG95_DS95_Msk            (0xc00UL)                 /*!< DS95 (Bitfield-Mask: 0x03)                            */
33105 #define GPIO_PINCFG95_OUTCFG95_Pos        (8UL)                     /*!< OUTCFG95 (Bit 8)                                      */
33106 #define GPIO_PINCFG95_OUTCFG95_Msk        (0x300UL)                 /*!< OUTCFG95 (Bitfield-Mask: 0x03)                        */
33107 #define GPIO_PINCFG95_IRPTEN95_Pos        (6UL)                     /*!< IRPTEN95 (Bit 6)                                      */
33108 #define GPIO_PINCFG95_IRPTEN95_Msk        (0xc0UL)                  /*!< IRPTEN95 (Bitfield-Mask: 0x03)                        */
33109 #define GPIO_PINCFG95_RDZERO95_Pos        (5UL)                     /*!< RDZERO95 (Bit 5)                                      */
33110 #define GPIO_PINCFG95_RDZERO95_Msk        (0x20UL)                  /*!< RDZERO95 (Bitfield-Mask: 0x01)                        */
33111 #define GPIO_PINCFG95_INPEN95_Pos         (4UL)                     /*!< INPEN95 (Bit 4)                                       */
33112 #define GPIO_PINCFG95_INPEN95_Msk         (0x10UL)                  /*!< INPEN95 (Bitfield-Mask: 0x01)                         */
33113 #define GPIO_PINCFG95_FNCSEL95_Pos        (0UL)                     /*!< FNCSEL95 (Bit 0)                                      */
33114 #define GPIO_PINCFG95_FNCSEL95_Msk        (0xfUL)                   /*!< FNCSEL95 (Bitfield-Mask: 0x0f)                        */
33115 /* =======================================================  PINCFG96  ======================================================== */
33116 #define GPIO_PINCFG96_FOEN96_Pos          (27UL)                    /*!< FOEN96 (Bit 27)                                       */
33117 #define GPIO_PINCFG96_FOEN96_Msk          (0x8000000UL)             /*!< FOEN96 (Bitfield-Mask: 0x01)                          */
33118 #define GPIO_PINCFG96_FIEN96_Pos          (26UL)                    /*!< FIEN96 (Bit 26)                                       */
33119 #define GPIO_PINCFG96_FIEN96_Msk          (0x4000000UL)             /*!< FIEN96 (Bitfield-Mask: 0x01)                          */
33120 #define GPIO_PINCFG96_NCEPOL96_Pos        (22UL)                    /*!< NCEPOL96 (Bit 22)                                     */
33121 #define GPIO_PINCFG96_NCEPOL96_Msk        (0x400000UL)              /*!< NCEPOL96 (Bitfield-Mask: 0x01)                        */
33122 #define GPIO_PINCFG96_NCESRC96_Pos        (16UL)                    /*!< NCESRC96 (Bit 16)                                     */
33123 #define GPIO_PINCFG96_NCESRC96_Msk        (0x3f0000UL)              /*!< NCESRC96 (Bitfield-Mask: 0x3f)                        */
33124 #define GPIO_PINCFG96_PULLCFG96_Pos       (13UL)                    /*!< PULLCFG96 (Bit 13)                                    */
33125 #define GPIO_PINCFG96_PULLCFG96_Msk       (0xe000UL)                /*!< PULLCFG96 (Bitfield-Mask: 0x07)                       */
33126 #define GPIO_PINCFG96_SR96_Pos            (12UL)                    /*!< SR96 (Bit 12)                                         */
33127 #define GPIO_PINCFG96_SR96_Msk            (0x1000UL)                /*!< SR96 (Bitfield-Mask: 0x01)                            */
33128 #define GPIO_PINCFG96_DS96_Pos            (10UL)                    /*!< DS96 (Bit 10)                                         */
33129 #define GPIO_PINCFG96_DS96_Msk            (0xc00UL)                 /*!< DS96 (Bitfield-Mask: 0x03)                            */
33130 #define GPIO_PINCFG96_OUTCFG96_Pos        (8UL)                     /*!< OUTCFG96 (Bit 8)                                      */
33131 #define GPIO_PINCFG96_OUTCFG96_Msk        (0x300UL)                 /*!< OUTCFG96 (Bitfield-Mask: 0x03)                        */
33132 #define GPIO_PINCFG96_IRPTEN96_Pos        (6UL)                     /*!< IRPTEN96 (Bit 6)                                      */
33133 #define GPIO_PINCFG96_IRPTEN96_Msk        (0xc0UL)                  /*!< IRPTEN96 (Bitfield-Mask: 0x03)                        */
33134 #define GPIO_PINCFG96_RDZERO96_Pos        (5UL)                     /*!< RDZERO96 (Bit 5)                                      */
33135 #define GPIO_PINCFG96_RDZERO96_Msk        (0x20UL)                  /*!< RDZERO96 (Bitfield-Mask: 0x01)                        */
33136 #define GPIO_PINCFG96_INPEN96_Pos         (4UL)                     /*!< INPEN96 (Bit 4)                                       */
33137 #define GPIO_PINCFG96_INPEN96_Msk         (0x10UL)                  /*!< INPEN96 (Bitfield-Mask: 0x01)                         */
33138 #define GPIO_PINCFG96_FNCSEL96_Pos        (0UL)                     /*!< FNCSEL96 (Bit 0)                                      */
33139 #define GPIO_PINCFG96_FNCSEL96_Msk        (0xfUL)                   /*!< FNCSEL96 (Bitfield-Mask: 0x0f)                        */
33140 /* =======================================================  PINCFG97  ======================================================== */
33141 #define GPIO_PINCFG97_FOEN97_Pos          (27UL)                    /*!< FOEN97 (Bit 27)                                       */
33142 #define GPIO_PINCFG97_FOEN97_Msk          (0x8000000UL)             /*!< FOEN97 (Bitfield-Mask: 0x01)                          */
33143 #define GPIO_PINCFG97_FIEN97_Pos          (26UL)                    /*!< FIEN97 (Bit 26)                                       */
33144 #define GPIO_PINCFG97_FIEN97_Msk          (0x4000000UL)             /*!< FIEN97 (Bitfield-Mask: 0x01)                          */
33145 #define GPIO_PINCFG97_NCEPOL97_Pos        (22UL)                    /*!< NCEPOL97 (Bit 22)                                     */
33146 #define GPIO_PINCFG97_NCEPOL97_Msk        (0x400000UL)              /*!< NCEPOL97 (Bitfield-Mask: 0x01)                        */
33147 #define GPIO_PINCFG97_NCESRC97_Pos        (16UL)                    /*!< NCESRC97 (Bit 16)                                     */
33148 #define GPIO_PINCFG97_NCESRC97_Msk        (0x3f0000UL)              /*!< NCESRC97 (Bitfield-Mask: 0x3f)                        */
33149 #define GPIO_PINCFG97_PULLCFG97_Pos       (13UL)                    /*!< PULLCFG97 (Bit 13)                                    */
33150 #define GPIO_PINCFG97_PULLCFG97_Msk       (0xe000UL)                /*!< PULLCFG97 (Bitfield-Mask: 0x07)                       */
33151 #define GPIO_PINCFG97_SR97_Pos            (12UL)                    /*!< SR97 (Bit 12)                                         */
33152 #define GPIO_PINCFG97_SR97_Msk            (0x1000UL)                /*!< SR97 (Bitfield-Mask: 0x01)                            */
33153 #define GPIO_PINCFG97_DS97_Pos            (10UL)                    /*!< DS97 (Bit 10)                                         */
33154 #define GPIO_PINCFG97_DS97_Msk            (0xc00UL)                 /*!< DS97 (Bitfield-Mask: 0x03)                            */
33155 #define GPIO_PINCFG97_OUTCFG97_Pos        (8UL)                     /*!< OUTCFG97 (Bit 8)                                      */
33156 #define GPIO_PINCFG97_OUTCFG97_Msk        (0x300UL)                 /*!< OUTCFG97 (Bitfield-Mask: 0x03)                        */
33157 #define GPIO_PINCFG97_IRPTEN97_Pos        (6UL)                     /*!< IRPTEN97 (Bit 6)                                      */
33158 #define GPIO_PINCFG97_IRPTEN97_Msk        (0xc0UL)                  /*!< IRPTEN97 (Bitfield-Mask: 0x03)                        */
33159 #define GPIO_PINCFG97_RDZERO97_Pos        (5UL)                     /*!< RDZERO97 (Bit 5)                                      */
33160 #define GPIO_PINCFG97_RDZERO97_Msk        (0x20UL)                  /*!< RDZERO97 (Bitfield-Mask: 0x01)                        */
33161 #define GPIO_PINCFG97_INPEN97_Pos         (4UL)                     /*!< INPEN97 (Bit 4)                                       */
33162 #define GPIO_PINCFG97_INPEN97_Msk         (0x10UL)                  /*!< INPEN97 (Bitfield-Mask: 0x01)                         */
33163 #define GPIO_PINCFG97_FNCSEL97_Pos        (0UL)                     /*!< FNCSEL97 (Bit 0)                                      */
33164 #define GPIO_PINCFG97_FNCSEL97_Msk        (0xfUL)                   /*!< FNCSEL97 (Bitfield-Mask: 0x0f)                        */
33165 /* =======================================================  PINCFG98  ======================================================== */
33166 #define GPIO_PINCFG98_FOEN98_Pos          (27UL)                    /*!< FOEN98 (Bit 27)                                       */
33167 #define GPIO_PINCFG98_FOEN98_Msk          (0x8000000UL)             /*!< FOEN98 (Bitfield-Mask: 0x01)                          */
33168 #define GPIO_PINCFG98_FIEN98_Pos          (26UL)                    /*!< FIEN98 (Bit 26)                                       */
33169 #define GPIO_PINCFG98_FIEN98_Msk          (0x4000000UL)             /*!< FIEN98 (Bitfield-Mask: 0x01)                          */
33170 #define GPIO_PINCFG98_NCEPOL98_Pos        (22UL)                    /*!< NCEPOL98 (Bit 22)                                     */
33171 #define GPIO_PINCFG98_NCEPOL98_Msk        (0x400000UL)              /*!< NCEPOL98 (Bitfield-Mask: 0x01)                        */
33172 #define GPIO_PINCFG98_NCESRC98_Pos        (16UL)                    /*!< NCESRC98 (Bit 16)                                     */
33173 #define GPIO_PINCFG98_NCESRC98_Msk        (0x3f0000UL)              /*!< NCESRC98 (Bitfield-Mask: 0x3f)                        */
33174 #define GPIO_PINCFG98_PULLCFG98_Pos       (13UL)                    /*!< PULLCFG98 (Bit 13)                                    */
33175 #define GPIO_PINCFG98_PULLCFG98_Msk       (0xe000UL)                /*!< PULLCFG98 (Bitfield-Mask: 0x07)                       */
33176 #define GPIO_PINCFG98_SR98_Pos            (12UL)                    /*!< SR98 (Bit 12)                                         */
33177 #define GPIO_PINCFG98_SR98_Msk            (0x1000UL)                /*!< SR98 (Bitfield-Mask: 0x01)                            */
33178 #define GPIO_PINCFG98_DS98_Pos            (10UL)                    /*!< DS98 (Bit 10)                                         */
33179 #define GPIO_PINCFG98_DS98_Msk            (0xc00UL)                 /*!< DS98 (Bitfield-Mask: 0x03)                            */
33180 #define GPIO_PINCFG98_OUTCFG98_Pos        (8UL)                     /*!< OUTCFG98 (Bit 8)                                      */
33181 #define GPIO_PINCFG98_OUTCFG98_Msk        (0x300UL)                 /*!< OUTCFG98 (Bitfield-Mask: 0x03)                        */
33182 #define GPIO_PINCFG98_IRPTEN98_Pos        (6UL)                     /*!< IRPTEN98 (Bit 6)                                      */
33183 #define GPIO_PINCFG98_IRPTEN98_Msk        (0xc0UL)                  /*!< IRPTEN98 (Bitfield-Mask: 0x03)                        */
33184 #define GPIO_PINCFG98_RDZERO98_Pos        (5UL)                     /*!< RDZERO98 (Bit 5)                                      */
33185 #define GPIO_PINCFG98_RDZERO98_Msk        (0x20UL)                  /*!< RDZERO98 (Bitfield-Mask: 0x01)                        */
33186 #define GPIO_PINCFG98_INPEN98_Pos         (4UL)                     /*!< INPEN98 (Bit 4)                                       */
33187 #define GPIO_PINCFG98_INPEN98_Msk         (0x10UL)                  /*!< INPEN98 (Bitfield-Mask: 0x01)                         */
33188 #define GPIO_PINCFG98_FNCSEL98_Pos        (0UL)                     /*!< FNCSEL98 (Bit 0)                                      */
33189 #define GPIO_PINCFG98_FNCSEL98_Msk        (0xfUL)                   /*!< FNCSEL98 (Bitfield-Mask: 0x0f)                        */
33190 /* =======================================================  PINCFG99  ======================================================== */
33191 #define GPIO_PINCFG99_FOEN99_Pos          (27UL)                    /*!< FOEN99 (Bit 27)                                       */
33192 #define GPIO_PINCFG99_FOEN99_Msk          (0x8000000UL)             /*!< FOEN99 (Bitfield-Mask: 0x01)                          */
33193 #define GPIO_PINCFG99_FIEN99_Pos          (26UL)                    /*!< FIEN99 (Bit 26)                                       */
33194 #define GPIO_PINCFG99_FIEN99_Msk          (0x4000000UL)             /*!< FIEN99 (Bitfield-Mask: 0x01)                          */
33195 #define GPIO_PINCFG99_NCEPOL99_Pos        (22UL)                    /*!< NCEPOL99 (Bit 22)                                     */
33196 #define GPIO_PINCFG99_NCEPOL99_Msk        (0x400000UL)              /*!< NCEPOL99 (Bitfield-Mask: 0x01)                        */
33197 #define GPIO_PINCFG99_NCESRC99_Pos        (16UL)                    /*!< NCESRC99 (Bit 16)                                     */
33198 #define GPIO_PINCFG99_NCESRC99_Msk        (0x3f0000UL)              /*!< NCESRC99 (Bitfield-Mask: 0x3f)                        */
33199 #define GPIO_PINCFG99_PULLCFG99_Pos       (13UL)                    /*!< PULLCFG99 (Bit 13)                                    */
33200 #define GPIO_PINCFG99_PULLCFG99_Msk       (0xe000UL)                /*!< PULLCFG99 (Bitfield-Mask: 0x07)                       */
33201 #define GPIO_PINCFG99_SR99_Pos            (12UL)                    /*!< SR99 (Bit 12)                                         */
33202 #define GPIO_PINCFG99_SR99_Msk            (0x1000UL)                /*!< SR99 (Bitfield-Mask: 0x01)                            */
33203 #define GPIO_PINCFG99_DS99_Pos            (10UL)                    /*!< DS99 (Bit 10)                                         */
33204 #define GPIO_PINCFG99_DS99_Msk            (0xc00UL)                 /*!< DS99 (Bitfield-Mask: 0x03)                            */
33205 #define GPIO_PINCFG99_OUTCFG99_Pos        (8UL)                     /*!< OUTCFG99 (Bit 8)                                      */
33206 #define GPIO_PINCFG99_OUTCFG99_Msk        (0x300UL)                 /*!< OUTCFG99 (Bitfield-Mask: 0x03)                        */
33207 #define GPIO_PINCFG99_IRPTEN99_Pos        (6UL)                     /*!< IRPTEN99 (Bit 6)                                      */
33208 #define GPIO_PINCFG99_IRPTEN99_Msk        (0xc0UL)                  /*!< IRPTEN99 (Bitfield-Mask: 0x03)                        */
33209 #define GPIO_PINCFG99_RDZERO99_Pos        (5UL)                     /*!< RDZERO99 (Bit 5)                                      */
33210 #define GPIO_PINCFG99_RDZERO99_Msk        (0x20UL)                  /*!< RDZERO99 (Bitfield-Mask: 0x01)                        */
33211 #define GPIO_PINCFG99_INPEN99_Pos         (4UL)                     /*!< INPEN99 (Bit 4)                                       */
33212 #define GPIO_PINCFG99_INPEN99_Msk         (0x10UL)                  /*!< INPEN99 (Bitfield-Mask: 0x01)                         */
33213 #define GPIO_PINCFG99_FNCSEL99_Pos        (0UL)                     /*!< FNCSEL99 (Bit 0)                                      */
33214 #define GPIO_PINCFG99_FNCSEL99_Msk        (0xfUL)                   /*!< FNCSEL99 (Bitfield-Mask: 0x0f)                        */
33215 /* =======================================================  PINCFG100  ======================================================= */
33216 #define GPIO_PINCFG100_FOEN100_Pos        (27UL)                    /*!< FOEN100 (Bit 27)                                      */
33217 #define GPIO_PINCFG100_FOEN100_Msk        (0x8000000UL)             /*!< FOEN100 (Bitfield-Mask: 0x01)                         */
33218 #define GPIO_PINCFG100_FIEN100_Pos        (26UL)                    /*!< FIEN100 (Bit 26)                                      */
33219 #define GPIO_PINCFG100_FIEN100_Msk        (0x4000000UL)             /*!< FIEN100 (Bitfield-Mask: 0x01)                         */
33220 #define GPIO_PINCFG100_NCEPOL100_Pos      (22UL)                    /*!< NCEPOL100 (Bit 22)                                    */
33221 #define GPIO_PINCFG100_NCEPOL100_Msk      (0x400000UL)              /*!< NCEPOL100 (Bitfield-Mask: 0x01)                       */
33222 #define GPIO_PINCFG100_NCESRC100_Pos      (16UL)                    /*!< NCESRC100 (Bit 16)                                    */
33223 #define GPIO_PINCFG100_NCESRC100_Msk      (0x3f0000UL)              /*!< NCESRC100 (Bitfield-Mask: 0x3f)                       */
33224 #define GPIO_PINCFG100_PULLCFG100_Pos     (13UL)                    /*!< PULLCFG100 (Bit 13)                                   */
33225 #define GPIO_PINCFG100_PULLCFG100_Msk     (0xe000UL)                /*!< PULLCFG100 (Bitfield-Mask: 0x07)                      */
33226 #define GPIO_PINCFG100_SR100_Pos          (12UL)                    /*!< SR100 (Bit 12)                                        */
33227 #define GPIO_PINCFG100_SR100_Msk          (0x1000UL)                /*!< SR100 (Bitfield-Mask: 0x01)                           */
33228 #define GPIO_PINCFG100_DS100_Pos          (10UL)                    /*!< DS100 (Bit 10)                                        */
33229 #define GPIO_PINCFG100_DS100_Msk          (0xc00UL)                 /*!< DS100 (Bitfield-Mask: 0x03)                           */
33230 #define GPIO_PINCFG100_OUTCFG100_Pos      (8UL)                     /*!< OUTCFG100 (Bit 8)                                     */
33231 #define GPIO_PINCFG100_OUTCFG100_Msk      (0x300UL)                 /*!< OUTCFG100 (Bitfield-Mask: 0x03)                       */
33232 #define GPIO_PINCFG100_IRPTEN100_Pos      (6UL)                     /*!< IRPTEN100 (Bit 6)                                     */
33233 #define GPIO_PINCFG100_IRPTEN100_Msk      (0xc0UL)                  /*!< IRPTEN100 (Bitfield-Mask: 0x03)                       */
33234 #define GPIO_PINCFG100_RDZERO100_Pos      (5UL)                     /*!< RDZERO100 (Bit 5)                                     */
33235 #define GPIO_PINCFG100_RDZERO100_Msk      (0x20UL)                  /*!< RDZERO100 (Bitfield-Mask: 0x01)                       */
33236 #define GPIO_PINCFG100_INPEN100_Pos       (4UL)                     /*!< INPEN100 (Bit 4)                                      */
33237 #define GPIO_PINCFG100_INPEN100_Msk       (0x10UL)                  /*!< INPEN100 (Bitfield-Mask: 0x01)                        */
33238 #define GPIO_PINCFG100_FNCSEL100_Pos      (0UL)                     /*!< FNCSEL100 (Bit 0)                                     */
33239 #define GPIO_PINCFG100_FNCSEL100_Msk      (0xfUL)                   /*!< FNCSEL100 (Bitfield-Mask: 0x0f)                       */
33240 /* =======================================================  PINCFG101  ======================================================= */
33241 #define GPIO_PINCFG101_FOEN101_Pos        (27UL)                    /*!< FOEN101 (Bit 27)                                      */
33242 #define GPIO_PINCFG101_FOEN101_Msk        (0x8000000UL)             /*!< FOEN101 (Bitfield-Mask: 0x01)                         */
33243 #define GPIO_PINCFG101_FIEN101_Pos        (26UL)                    /*!< FIEN101 (Bit 26)                                      */
33244 #define GPIO_PINCFG101_FIEN101_Msk        (0x4000000UL)             /*!< FIEN101 (Bitfield-Mask: 0x01)                         */
33245 #define GPIO_PINCFG101_NCEPOL101_Pos      (22UL)                    /*!< NCEPOL101 (Bit 22)                                    */
33246 #define GPIO_PINCFG101_NCEPOL101_Msk      (0x400000UL)              /*!< NCEPOL101 (Bitfield-Mask: 0x01)                       */
33247 #define GPIO_PINCFG101_NCESRC101_Pos      (16UL)                    /*!< NCESRC101 (Bit 16)                                    */
33248 #define GPIO_PINCFG101_NCESRC101_Msk      (0x3f0000UL)              /*!< NCESRC101 (Bitfield-Mask: 0x3f)                       */
33249 #define GPIO_PINCFG101_PULLCFG101_Pos     (13UL)                    /*!< PULLCFG101 (Bit 13)                                   */
33250 #define GPIO_PINCFG101_PULLCFG101_Msk     (0xe000UL)                /*!< PULLCFG101 (Bitfield-Mask: 0x07)                      */
33251 #define GPIO_PINCFG101_SR101_Pos          (12UL)                    /*!< SR101 (Bit 12)                                        */
33252 #define GPIO_PINCFG101_SR101_Msk          (0x1000UL)                /*!< SR101 (Bitfield-Mask: 0x01)                           */
33253 #define GPIO_PINCFG101_DS101_Pos          (10UL)                    /*!< DS101 (Bit 10)                                        */
33254 #define GPIO_PINCFG101_DS101_Msk          (0xc00UL)                 /*!< DS101 (Bitfield-Mask: 0x03)                           */
33255 #define GPIO_PINCFG101_OUTCFG101_Pos      (8UL)                     /*!< OUTCFG101 (Bit 8)                                     */
33256 #define GPIO_PINCFG101_OUTCFG101_Msk      (0x300UL)                 /*!< OUTCFG101 (Bitfield-Mask: 0x03)                       */
33257 #define GPIO_PINCFG101_IRPTEN101_Pos      (6UL)                     /*!< IRPTEN101 (Bit 6)                                     */
33258 #define GPIO_PINCFG101_IRPTEN101_Msk      (0xc0UL)                  /*!< IRPTEN101 (Bitfield-Mask: 0x03)                       */
33259 #define GPIO_PINCFG101_RDZERO101_Pos      (5UL)                     /*!< RDZERO101 (Bit 5)                                     */
33260 #define GPIO_PINCFG101_RDZERO101_Msk      (0x20UL)                  /*!< RDZERO101 (Bitfield-Mask: 0x01)                       */
33261 #define GPIO_PINCFG101_INPEN101_Pos       (4UL)                     /*!< INPEN101 (Bit 4)                                      */
33262 #define GPIO_PINCFG101_INPEN101_Msk       (0x10UL)                  /*!< INPEN101 (Bitfield-Mask: 0x01)                        */
33263 #define GPIO_PINCFG101_FNCSEL101_Pos      (0UL)                     /*!< FNCSEL101 (Bit 0)                                     */
33264 #define GPIO_PINCFG101_FNCSEL101_Msk      (0xfUL)                   /*!< FNCSEL101 (Bitfield-Mask: 0x0f)                       */
33265 /* =======================================================  PINCFG102  ======================================================= */
33266 #define GPIO_PINCFG102_FOEN102_Pos        (27UL)                    /*!< FOEN102 (Bit 27)                                      */
33267 #define GPIO_PINCFG102_FOEN102_Msk        (0x8000000UL)             /*!< FOEN102 (Bitfield-Mask: 0x01)                         */
33268 #define GPIO_PINCFG102_FIEN102_Pos        (26UL)                    /*!< FIEN102 (Bit 26)                                      */
33269 #define GPIO_PINCFG102_FIEN102_Msk        (0x4000000UL)             /*!< FIEN102 (Bitfield-Mask: 0x01)                         */
33270 #define GPIO_PINCFG102_NCEPOL102_Pos      (22UL)                    /*!< NCEPOL102 (Bit 22)                                    */
33271 #define GPIO_PINCFG102_NCEPOL102_Msk      (0x400000UL)              /*!< NCEPOL102 (Bitfield-Mask: 0x01)                       */
33272 #define GPIO_PINCFG102_NCESRC102_Pos      (16UL)                    /*!< NCESRC102 (Bit 16)                                    */
33273 #define GPIO_PINCFG102_NCESRC102_Msk      (0x3f0000UL)              /*!< NCESRC102 (Bitfield-Mask: 0x3f)                       */
33274 #define GPIO_PINCFG102_PULLCFG102_Pos     (13UL)                    /*!< PULLCFG102 (Bit 13)                                   */
33275 #define GPIO_PINCFG102_PULLCFG102_Msk     (0xe000UL)                /*!< PULLCFG102 (Bitfield-Mask: 0x07)                      */
33276 #define GPIO_PINCFG102_SR102_Pos          (12UL)                    /*!< SR102 (Bit 12)                                        */
33277 #define GPIO_PINCFG102_SR102_Msk          (0x1000UL)                /*!< SR102 (Bitfield-Mask: 0x01)                           */
33278 #define GPIO_PINCFG102_DS102_Pos          (10UL)                    /*!< DS102 (Bit 10)                                        */
33279 #define GPIO_PINCFG102_DS102_Msk          (0xc00UL)                 /*!< DS102 (Bitfield-Mask: 0x03)                           */
33280 #define GPIO_PINCFG102_OUTCFG102_Pos      (8UL)                     /*!< OUTCFG102 (Bit 8)                                     */
33281 #define GPIO_PINCFG102_OUTCFG102_Msk      (0x300UL)                 /*!< OUTCFG102 (Bitfield-Mask: 0x03)                       */
33282 #define GPIO_PINCFG102_IRPTEN102_Pos      (6UL)                     /*!< IRPTEN102 (Bit 6)                                     */
33283 #define GPIO_PINCFG102_IRPTEN102_Msk      (0xc0UL)                  /*!< IRPTEN102 (Bitfield-Mask: 0x03)                       */
33284 #define GPIO_PINCFG102_RDZERO102_Pos      (5UL)                     /*!< RDZERO102 (Bit 5)                                     */
33285 #define GPIO_PINCFG102_RDZERO102_Msk      (0x20UL)                  /*!< RDZERO102 (Bitfield-Mask: 0x01)                       */
33286 #define GPIO_PINCFG102_INPEN102_Pos       (4UL)                     /*!< INPEN102 (Bit 4)                                      */
33287 #define GPIO_PINCFG102_INPEN102_Msk       (0x10UL)                  /*!< INPEN102 (Bitfield-Mask: 0x01)                        */
33288 #define GPIO_PINCFG102_FNCSEL102_Pos      (0UL)                     /*!< FNCSEL102 (Bit 0)                                     */
33289 #define GPIO_PINCFG102_FNCSEL102_Msk      (0xfUL)                   /*!< FNCSEL102 (Bitfield-Mask: 0x0f)                       */
33290 /* =======================================================  PINCFG103  ======================================================= */
33291 #define GPIO_PINCFG103_FOEN103_Pos        (27UL)                    /*!< FOEN103 (Bit 27)                                      */
33292 #define GPIO_PINCFG103_FOEN103_Msk        (0x8000000UL)             /*!< FOEN103 (Bitfield-Mask: 0x01)                         */
33293 #define GPIO_PINCFG103_FIEN103_Pos        (26UL)                    /*!< FIEN103 (Bit 26)                                      */
33294 #define GPIO_PINCFG103_FIEN103_Msk        (0x4000000UL)             /*!< FIEN103 (Bitfield-Mask: 0x01)                         */
33295 #define GPIO_PINCFG103_NCEPOL103_Pos      (22UL)                    /*!< NCEPOL103 (Bit 22)                                    */
33296 #define GPIO_PINCFG103_NCEPOL103_Msk      (0x400000UL)              /*!< NCEPOL103 (Bitfield-Mask: 0x01)                       */
33297 #define GPIO_PINCFG103_NCESRC103_Pos      (16UL)                    /*!< NCESRC103 (Bit 16)                                    */
33298 #define GPIO_PINCFG103_NCESRC103_Msk      (0x3f0000UL)              /*!< NCESRC103 (Bitfield-Mask: 0x3f)                       */
33299 #define GPIO_PINCFG103_PULLCFG103_Pos     (13UL)                    /*!< PULLCFG103 (Bit 13)                                   */
33300 #define GPIO_PINCFG103_PULLCFG103_Msk     (0xe000UL)                /*!< PULLCFG103 (Bitfield-Mask: 0x07)                      */
33301 #define GPIO_PINCFG103_SR103_Pos          (12UL)                    /*!< SR103 (Bit 12)                                        */
33302 #define GPIO_PINCFG103_SR103_Msk          (0x1000UL)                /*!< SR103 (Bitfield-Mask: 0x01)                           */
33303 #define GPIO_PINCFG103_DS103_Pos          (10UL)                    /*!< DS103 (Bit 10)                                        */
33304 #define GPIO_PINCFG103_DS103_Msk          (0xc00UL)                 /*!< DS103 (Bitfield-Mask: 0x03)                           */
33305 #define GPIO_PINCFG103_OUTCFG103_Pos      (8UL)                     /*!< OUTCFG103 (Bit 8)                                     */
33306 #define GPIO_PINCFG103_OUTCFG103_Msk      (0x300UL)                 /*!< OUTCFG103 (Bitfield-Mask: 0x03)                       */
33307 #define GPIO_PINCFG103_IRPTEN103_Pos      (6UL)                     /*!< IRPTEN103 (Bit 6)                                     */
33308 #define GPIO_PINCFG103_IRPTEN103_Msk      (0xc0UL)                  /*!< IRPTEN103 (Bitfield-Mask: 0x03)                       */
33309 #define GPIO_PINCFG103_RDZERO103_Pos      (5UL)                     /*!< RDZERO103 (Bit 5)                                     */
33310 #define GPIO_PINCFG103_RDZERO103_Msk      (0x20UL)                  /*!< RDZERO103 (Bitfield-Mask: 0x01)                       */
33311 #define GPIO_PINCFG103_INPEN103_Pos       (4UL)                     /*!< INPEN103 (Bit 4)                                      */
33312 #define GPIO_PINCFG103_INPEN103_Msk       (0x10UL)                  /*!< INPEN103 (Bitfield-Mask: 0x01)                        */
33313 #define GPIO_PINCFG103_FNCSEL103_Pos      (0UL)                     /*!< FNCSEL103 (Bit 0)                                     */
33314 #define GPIO_PINCFG103_FNCSEL103_Msk      (0xfUL)                   /*!< FNCSEL103 (Bitfield-Mask: 0x0f)                       */
33315 /* =======================================================  PINCFG104  ======================================================= */
33316 #define GPIO_PINCFG104_FOEN104_Pos        (27UL)                    /*!< FOEN104 (Bit 27)                                      */
33317 #define GPIO_PINCFG104_FOEN104_Msk        (0x8000000UL)             /*!< FOEN104 (Bitfield-Mask: 0x01)                         */
33318 #define GPIO_PINCFG104_FIEN104_Pos        (26UL)                    /*!< FIEN104 (Bit 26)                                      */
33319 #define GPIO_PINCFG104_FIEN104_Msk        (0x4000000UL)             /*!< FIEN104 (Bitfield-Mask: 0x01)                         */
33320 #define GPIO_PINCFG104_NCEPOL104_Pos      (22UL)                    /*!< NCEPOL104 (Bit 22)                                    */
33321 #define GPIO_PINCFG104_NCEPOL104_Msk      (0x400000UL)              /*!< NCEPOL104 (Bitfield-Mask: 0x01)                       */
33322 #define GPIO_PINCFG104_NCESRC104_Pos      (16UL)                    /*!< NCESRC104 (Bit 16)                                    */
33323 #define GPIO_PINCFG104_NCESRC104_Msk      (0x3f0000UL)              /*!< NCESRC104 (Bitfield-Mask: 0x3f)                       */
33324 #define GPIO_PINCFG104_PULLCFG104_Pos     (13UL)                    /*!< PULLCFG104 (Bit 13)                                   */
33325 #define GPIO_PINCFG104_PULLCFG104_Msk     (0xe000UL)                /*!< PULLCFG104 (Bitfield-Mask: 0x07)                      */
33326 #define GPIO_PINCFG104_SR104_Pos          (12UL)                    /*!< SR104 (Bit 12)                                        */
33327 #define GPIO_PINCFG104_SR104_Msk          (0x1000UL)                /*!< SR104 (Bitfield-Mask: 0x01)                           */
33328 #define GPIO_PINCFG104_DS104_Pos          (10UL)                    /*!< DS104 (Bit 10)                                        */
33329 #define GPIO_PINCFG104_DS104_Msk          (0xc00UL)                 /*!< DS104 (Bitfield-Mask: 0x03)                           */
33330 #define GPIO_PINCFG104_OUTCFG104_Pos      (8UL)                     /*!< OUTCFG104 (Bit 8)                                     */
33331 #define GPIO_PINCFG104_OUTCFG104_Msk      (0x300UL)                 /*!< OUTCFG104 (Bitfield-Mask: 0x03)                       */
33332 #define GPIO_PINCFG104_IRPTEN104_Pos      (6UL)                     /*!< IRPTEN104 (Bit 6)                                     */
33333 #define GPIO_PINCFG104_IRPTEN104_Msk      (0xc0UL)                  /*!< IRPTEN104 (Bitfield-Mask: 0x03)                       */
33334 #define GPIO_PINCFG104_RDZERO104_Pos      (5UL)                     /*!< RDZERO104 (Bit 5)                                     */
33335 #define GPIO_PINCFG104_RDZERO104_Msk      (0x20UL)                  /*!< RDZERO104 (Bitfield-Mask: 0x01)                       */
33336 #define GPIO_PINCFG104_INPEN104_Pos       (4UL)                     /*!< INPEN104 (Bit 4)                                      */
33337 #define GPIO_PINCFG104_INPEN104_Msk       (0x10UL)                  /*!< INPEN104 (Bitfield-Mask: 0x01)                        */
33338 #define GPIO_PINCFG104_FNCSEL104_Pos      (0UL)                     /*!< FNCSEL104 (Bit 0)                                     */
33339 #define GPIO_PINCFG104_FNCSEL104_Msk      (0xfUL)                   /*!< FNCSEL104 (Bitfield-Mask: 0x0f)                       */
33340 /* =======================================================  PINCFG105  ======================================================= */
33341 #define GPIO_PINCFG105_OUTCFG105_Pos      (8UL)                     /*!< OUTCFG105 (Bit 8)                                     */
33342 #define GPIO_PINCFG105_OUTCFG105_Msk      (0x300UL)                 /*!< OUTCFG105 (Bitfield-Mask: 0x03)                       */
33343 #define GPIO_PINCFG105_IRPTEN105_Pos      (6UL)                     /*!< IRPTEN105 (Bit 6)                                     */
33344 #define GPIO_PINCFG105_IRPTEN105_Msk      (0xc0UL)                  /*!< IRPTEN105 (Bitfield-Mask: 0x03)                       */
33345 #define GPIO_PINCFG105_RDZERO105_Pos      (5UL)                     /*!< RDZERO105 (Bit 5)                                     */
33346 #define GPIO_PINCFG105_RDZERO105_Msk      (0x20UL)                  /*!< RDZERO105 (Bitfield-Mask: 0x01)                       */
33347 #define GPIO_PINCFG105_INPEN105_Pos       (4UL)                     /*!< INPEN105 (Bit 4)                                      */
33348 #define GPIO_PINCFG105_INPEN105_Msk       (0x10UL)                  /*!< INPEN105 (Bitfield-Mask: 0x01)                        */
33349 #define GPIO_PINCFG105_FNCSEL105_Pos      (0UL)                     /*!< FNCSEL105 (Bit 0)                                     */
33350 #define GPIO_PINCFG105_FNCSEL105_Msk      (0xfUL)                   /*!< FNCSEL105 (Bitfield-Mask: 0x0f)                       */
33351 /* =======================================================  PINCFG106  ======================================================= */
33352 #define GPIO_PINCFG106_OUTCFG106_Pos      (8UL)                     /*!< OUTCFG106 (Bit 8)                                     */
33353 #define GPIO_PINCFG106_OUTCFG106_Msk      (0x300UL)                 /*!< OUTCFG106 (Bitfield-Mask: 0x03)                       */
33354 #define GPIO_PINCFG106_IRPTEN106_Pos      (6UL)                     /*!< IRPTEN106 (Bit 6)                                     */
33355 #define GPIO_PINCFG106_IRPTEN106_Msk      (0xc0UL)                  /*!< IRPTEN106 (Bitfield-Mask: 0x03)                       */
33356 #define GPIO_PINCFG106_RDZERO106_Pos      (5UL)                     /*!< RDZERO106 (Bit 5)                                     */
33357 #define GPIO_PINCFG106_RDZERO106_Msk      (0x20UL)                  /*!< RDZERO106 (Bitfield-Mask: 0x01)                       */
33358 #define GPIO_PINCFG106_INPEN106_Pos       (4UL)                     /*!< INPEN106 (Bit 4)                                      */
33359 #define GPIO_PINCFG106_INPEN106_Msk       (0x10UL)                  /*!< INPEN106 (Bitfield-Mask: 0x01)                        */
33360 #define GPIO_PINCFG106_FNCSEL106_Pos      (0UL)                     /*!< FNCSEL106 (Bit 0)                                     */
33361 #define GPIO_PINCFG106_FNCSEL106_Msk      (0xfUL)                   /*!< FNCSEL106 (Bitfield-Mask: 0x0f)                       */
33362 /* =======================================================  PINCFG107  ======================================================= */
33363 #define GPIO_PINCFG107_OUTCFG107_Pos      (8UL)                     /*!< OUTCFG107 (Bit 8)                                     */
33364 #define GPIO_PINCFG107_OUTCFG107_Msk      (0x300UL)                 /*!< OUTCFG107 (Bitfield-Mask: 0x03)                       */
33365 #define GPIO_PINCFG107_IRPTEN107_Pos      (6UL)                     /*!< IRPTEN107 (Bit 6)                                     */
33366 #define GPIO_PINCFG107_IRPTEN107_Msk      (0xc0UL)                  /*!< IRPTEN107 (Bitfield-Mask: 0x03)                       */
33367 #define GPIO_PINCFG107_RDZERO107_Pos      (5UL)                     /*!< RDZERO107 (Bit 5)                                     */
33368 #define GPIO_PINCFG107_RDZERO107_Msk      (0x20UL)                  /*!< RDZERO107 (Bitfield-Mask: 0x01)                       */
33369 #define GPIO_PINCFG107_INPEN107_Pos       (4UL)                     /*!< INPEN107 (Bit 4)                                      */
33370 #define GPIO_PINCFG107_INPEN107_Msk       (0x10UL)                  /*!< INPEN107 (Bitfield-Mask: 0x01)                        */
33371 #define GPIO_PINCFG107_FNCSEL107_Pos      (0UL)                     /*!< FNCSEL107 (Bit 0)                                     */
33372 #define GPIO_PINCFG107_FNCSEL107_Msk      (0xfUL)                   /*!< FNCSEL107 (Bitfield-Mask: 0x0f)                       */
33373 /* =======================================================  PINCFG108  ======================================================= */
33374 #define GPIO_PINCFG108_OUTCFG108_Pos      (8UL)                     /*!< OUTCFG108 (Bit 8)                                     */
33375 #define GPIO_PINCFG108_OUTCFG108_Msk      (0x300UL)                 /*!< OUTCFG108 (Bitfield-Mask: 0x03)                       */
33376 #define GPIO_PINCFG108_IRPTEN108_Pos      (6UL)                     /*!< IRPTEN108 (Bit 6)                                     */
33377 #define GPIO_PINCFG108_IRPTEN108_Msk      (0xc0UL)                  /*!< IRPTEN108 (Bitfield-Mask: 0x03)                       */
33378 #define GPIO_PINCFG108_RDZERO108_Pos      (5UL)                     /*!< RDZERO108 (Bit 5)                                     */
33379 #define GPIO_PINCFG108_RDZERO108_Msk      (0x20UL)                  /*!< RDZERO108 (Bitfield-Mask: 0x01)                       */
33380 #define GPIO_PINCFG108_INPEN108_Pos       (4UL)                     /*!< INPEN108 (Bit 4)                                      */
33381 #define GPIO_PINCFG108_INPEN108_Msk       (0x10UL)                  /*!< INPEN108 (Bitfield-Mask: 0x01)                        */
33382 #define GPIO_PINCFG108_FNCSEL108_Pos      (0UL)                     /*!< FNCSEL108 (Bit 0)                                     */
33383 #define GPIO_PINCFG108_FNCSEL108_Msk      (0xfUL)                   /*!< FNCSEL108 (Bitfield-Mask: 0x0f)                       */
33384 /* =======================================================  PINCFG109  ======================================================= */
33385 #define GPIO_PINCFG109_OUTCFG109_Pos      (8UL)                     /*!< OUTCFG109 (Bit 8)                                     */
33386 #define GPIO_PINCFG109_OUTCFG109_Msk      (0x300UL)                 /*!< OUTCFG109 (Bitfield-Mask: 0x03)                       */
33387 #define GPIO_PINCFG109_IRPTEN109_Pos      (6UL)                     /*!< IRPTEN109 (Bit 6)                                     */
33388 #define GPIO_PINCFG109_IRPTEN109_Msk      (0xc0UL)                  /*!< IRPTEN109 (Bitfield-Mask: 0x03)                       */
33389 #define GPIO_PINCFG109_RDZERO109_Pos      (5UL)                     /*!< RDZERO109 (Bit 5)                                     */
33390 #define GPIO_PINCFG109_RDZERO109_Msk      (0x20UL)                  /*!< RDZERO109 (Bitfield-Mask: 0x01)                       */
33391 #define GPIO_PINCFG109_INPEN109_Pos       (4UL)                     /*!< INPEN109 (Bit 4)                                      */
33392 #define GPIO_PINCFG109_INPEN109_Msk       (0x10UL)                  /*!< INPEN109 (Bitfield-Mask: 0x01)                        */
33393 #define GPIO_PINCFG109_FNCSEL109_Pos      (0UL)                     /*!< FNCSEL109 (Bit 0)                                     */
33394 #define GPIO_PINCFG109_FNCSEL109_Msk      (0xfUL)                   /*!< FNCSEL109 (Bitfield-Mask: 0x0f)                       */
33395 /* =======================================================  PINCFG110  ======================================================= */
33396 #define GPIO_PINCFG110_OUTCFG110_Pos      (8UL)                     /*!< OUTCFG110 (Bit 8)                                     */
33397 #define GPIO_PINCFG110_OUTCFG110_Msk      (0x300UL)                 /*!< OUTCFG110 (Bitfield-Mask: 0x03)                       */
33398 #define GPIO_PINCFG110_IRPTEN110_Pos      (6UL)                     /*!< IRPTEN110 (Bit 6)                                     */
33399 #define GPIO_PINCFG110_IRPTEN110_Msk      (0xc0UL)                  /*!< IRPTEN110 (Bitfield-Mask: 0x03)                       */
33400 #define GPIO_PINCFG110_RDZERO110_Pos      (5UL)                     /*!< RDZERO110 (Bit 5)                                     */
33401 #define GPIO_PINCFG110_RDZERO110_Msk      (0x20UL)                  /*!< RDZERO110 (Bitfield-Mask: 0x01)                       */
33402 #define GPIO_PINCFG110_INPEN110_Pos       (4UL)                     /*!< INPEN110 (Bit 4)                                      */
33403 #define GPIO_PINCFG110_INPEN110_Msk       (0x10UL)                  /*!< INPEN110 (Bitfield-Mask: 0x01)                        */
33404 #define GPIO_PINCFG110_FNCSEL110_Pos      (0UL)                     /*!< FNCSEL110 (Bit 0)                                     */
33405 #define GPIO_PINCFG110_FNCSEL110_Msk      (0xfUL)                   /*!< FNCSEL110 (Bitfield-Mask: 0x0f)                       */
33406 /* =======================================================  PINCFG111  ======================================================= */
33407 #define GPIO_PINCFG111_OUTCFG111_Pos      (8UL)                     /*!< OUTCFG111 (Bit 8)                                     */
33408 #define GPIO_PINCFG111_OUTCFG111_Msk      (0x300UL)                 /*!< OUTCFG111 (Bitfield-Mask: 0x03)                       */
33409 #define GPIO_PINCFG111_IRPTEN111_Pos      (6UL)                     /*!< IRPTEN111 (Bit 6)                                     */
33410 #define GPIO_PINCFG111_IRPTEN111_Msk      (0xc0UL)                  /*!< IRPTEN111 (Bitfield-Mask: 0x03)                       */
33411 #define GPIO_PINCFG111_RDZERO111_Pos      (5UL)                     /*!< RDZERO111 (Bit 5)                                     */
33412 #define GPIO_PINCFG111_RDZERO111_Msk      (0x20UL)                  /*!< RDZERO111 (Bitfield-Mask: 0x01)                       */
33413 #define GPIO_PINCFG111_INPEN111_Pos       (4UL)                     /*!< INPEN111 (Bit 4)                                      */
33414 #define GPIO_PINCFG111_INPEN111_Msk       (0x10UL)                  /*!< INPEN111 (Bitfield-Mask: 0x01)                        */
33415 #define GPIO_PINCFG111_FNCSEL111_Pos      (0UL)                     /*!< FNCSEL111 (Bit 0)                                     */
33416 #define GPIO_PINCFG111_FNCSEL111_Msk      (0xfUL)                   /*!< FNCSEL111 (Bitfield-Mask: 0x0f)                       */
33417 /* =======================================================  PINCFG112  ======================================================= */
33418 #define GPIO_PINCFG112_OUTCFG112_Pos      (8UL)                     /*!< OUTCFG112 (Bit 8)                                     */
33419 #define GPIO_PINCFG112_OUTCFG112_Msk      (0x300UL)                 /*!< OUTCFG112 (Bitfield-Mask: 0x03)                       */
33420 #define GPIO_PINCFG112_IRPTEN112_Pos      (6UL)                     /*!< IRPTEN112 (Bit 6)                                     */
33421 #define GPIO_PINCFG112_IRPTEN112_Msk      (0xc0UL)                  /*!< IRPTEN112 (Bitfield-Mask: 0x03)                       */
33422 #define GPIO_PINCFG112_RDZERO112_Pos      (5UL)                     /*!< RDZERO112 (Bit 5)                                     */
33423 #define GPIO_PINCFG112_RDZERO112_Msk      (0x20UL)                  /*!< RDZERO112 (Bitfield-Mask: 0x01)                       */
33424 #define GPIO_PINCFG112_INPEN112_Pos       (4UL)                     /*!< INPEN112 (Bit 4)                                      */
33425 #define GPIO_PINCFG112_INPEN112_Msk       (0x10UL)                  /*!< INPEN112 (Bitfield-Mask: 0x01)                        */
33426 #define GPIO_PINCFG112_FNCSEL112_Pos      (0UL)                     /*!< FNCSEL112 (Bit 0)                                     */
33427 #define GPIO_PINCFG112_FNCSEL112_Msk      (0xfUL)                   /*!< FNCSEL112 (Bitfield-Mask: 0x0f)                       */
33428 /* =======================================================  PINCFG113  ======================================================= */
33429 #define GPIO_PINCFG113_OUTCFG113_Pos      (8UL)                     /*!< OUTCFG113 (Bit 8)                                     */
33430 #define GPIO_PINCFG113_OUTCFG113_Msk      (0x300UL)                 /*!< OUTCFG113 (Bitfield-Mask: 0x03)                       */
33431 #define GPIO_PINCFG113_IRPTEN113_Pos      (6UL)                     /*!< IRPTEN113 (Bit 6)                                     */
33432 #define GPIO_PINCFG113_IRPTEN113_Msk      (0xc0UL)                  /*!< IRPTEN113 (Bitfield-Mask: 0x03)                       */
33433 #define GPIO_PINCFG113_RDZERO113_Pos      (5UL)                     /*!< RDZERO113 (Bit 5)                                     */
33434 #define GPIO_PINCFG113_RDZERO113_Msk      (0x20UL)                  /*!< RDZERO113 (Bitfield-Mask: 0x01)                       */
33435 #define GPIO_PINCFG113_INPEN113_Pos       (4UL)                     /*!< INPEN113 (Bit 4)                                      */
33436 #define GPIO_PINCFG113_INPEN113_Msk       (0x10UL)                  /*!< INPEN113 (Bitfield-Mask: 0x01)                        */
33437 #define GPIO_PINCFG113_FNCSEL113_Pos      (0UL)                     /*!< FNCSEL113 (Bit 0)                                     */
33438 #define GPIO_PINCFG113_FNCSEL113_Msk      (0xfUL)                   /*!< FNCSEL113 (Bitfield-Mask: 0x0f)                       */
33439 /* =======================================================  PINCFG114  ======================================================= */
33440 #define GPIO_PINCFG114_OUTCFG114_Pos      (8UL)                     /*!< OUTCFG114 (Bit 8)                                     */
33441 #define GPIO_PINCFG114_OUTCFG114_Msk      (0x300UL)                 /*!< OUTCFG114 (Bitfield-Mask: 0x03)                       */
33442 #define GPIO_PINCFG114_IRPTEN114_Pos      (6UL)                     /*!< IRPTEN114 (Bit 6)                                     */
33443 #define GPIO_PINCFG114_IRPTEN114_Msk      (0xc0UL)                  /*!< IRPTEN114 (Bitfield-Mask: 0x03)                       */
33444 #define GPIO_PINCFG114_RDZERO114_Pos      (5UL)                     /*!< RDZERO114 (Bit 5)                                     */
33445 #define GPIO_PINCFG114_RDZERO114_Msk      (0x20UL)                  /*!< RDZERO114 (Bitfield-Mask: 0x01)                       */
33446 #define GPIO_PINCFG114_INPEN114_Pos       (4UL)                     /*!< INPEN114 (Bit 4)                                      */
33447 #define GPIO_PINCFG114_INPEN114_Msk       (0x10UL)                  /*!< INPEN114 (Bitfield-Mask: 0x01)                        */
33448 #define GPIO_PINCFG114_FNCSEL114_Pos      (0UL)                     /*!< FNCSEL114 (Bit 0)                                     */
33449 #define GPIO_PINCFG114_FNCSEL114_Msk      (0xfUL)                   /*!< FNCSEL114 (Bitfield-Mask: 0x0f)                       */
33450 /* =======================================================  PINCFG115  ======================================================= */
33451 #define GPIO_PINCFG115_OUTCFG115_Pos      (8UL)                     /*!< OUTCFG115 (Bit 8)                                     */
33452 #define GPIO_PINCFG115_OUTCFG115_Msk      (0x300UL)                 /*!< OUTCFG115 (Bitfield-Mask: 0x03)                       */
33453 #define GPIO_PINCFG115_IRPTEN115_Pos      (6UL)                     /*!< IRPTEN115 (Bit 6)                                     */
33454 #define GPIO_PINCFG115_IRPTEN115_Msk      (0xc0UL)                  /*!< IRPTEN115 (Bitfield-Mask: 0x03)                       */
33455 #define GPIO_PINCFG115_RDZERO115_Pos      (5UL)                     /*!< RDZERO115 (Bit 5)                                     */
33456 #define GPIO_PINCFG115_RDZERO115_Msk      (0x20UL)                  /*!< RDZERO115 (Bitfield-Mask: 0x01)                       */
33457 #define GPIO_PINCFG115_INPEN115_Pos       (4UL)                     /*!< INPEN115 (Bit 4)                                      */
33458 #define GPIO_PINCFG115_INPEN115_Msk       (0x10UL)                  /*!< INPEN115 (Bitfield-Mask: 0x01)                        */
33459 #define GPIO_PINCFG115_FNCSEL115_Pos      (0UL)                     /*!< FNCSEL115 (Bit 0)                                     */
33460 #define GPIO_PINCFG115_FNCSEL115_Msk      (0xfUL)                   /*!< FNCSEL115 (Bitfield-Mask: 0x0f)                       */
33461 /* =======================================================  PINCFG116  ======================================================= */
33462 #define GPIO_PINCFG116_OUTCFG116_Pos      (8UL)                     /*!< OUTCFG116 (Bit 8)                                     */
33463 #define GPIO_PINCFG116_OUTCFG116_Msk      (0x300UL)                 /*!< OUTCFG116 (Bitfield-Mask: 0x03)                       */
33464 #define GPIO_PINCFG116_IRPTEN116_Pos      (6UL)                     /*!< IRPTEN116 (Bit 6)                                     */
33465 #define GPIO_PINCFG116_IRPTEN116_Msk      (0xc0UL)                  /*!< IRPTEN116 (Bitfield-Mask: 0x03)                       */
33466 #define GPIO_PINCFG116_RDZERO116_Pos      (5UL)                     /*!< RDZERO116 (Bit 5)                                     */
33467 #define GPIO_PINCFG116_RDZERO116_Msk      (0x20UL)                  /*!< RDZERO116 (Bitfield-Mask: 0x01)                       */
33468 #define GPIO_PINCFG116_INPEN116_Pos       (4UL)                     /*!< INPEN116 (Bit 4)                                      */
33469 #define GPIO_PINCFG116_INPEN116_Msk       (0x10UL)                  /*!< INPEN116 (Bitfield-Mask: 0x01)                        */
33470 #define GPIO_PINCFG116_FNCSEL116_Pos      (0UL)                     /*!< FNCSEL116 (Bit 0)                                     */
33471 #define GPIO_PINCFG116_FNCSEL116_Msk      (0xfUL)                   /*!< FNCSEL116 (Bitfield-Mask: 0x0f)                       */
33472 /* =======================================================  PINCFG117  ======================================================= */
33473 #define GPIO_PINCFG117_OUTCFG117_Pos      (8UL)                     /*!< OUTCFG117 (Bit 8)                                     */
33474 #define GPIO_PINCFG117_OUTCFG117_Msk      (0x300UL)                 /*!< OUTCFG117 (Bitfield-Mask: 0x03)                       */
33475 #define GPIO_PINCFG117_IRPTEN117_Pos      (6UL)                     /*!< IRPTEN117 (Bit 6)                                     */
33476 #define GPIO_PINCFG117_IRPTEN117_Msk      (0xc0UL)                  /*!< IRPTEN117 (Bitfield-Mask: 0x03)                       */
33477 #define GPIO_PINCFG117_RDZERO117_Pos      (5UL)                     /*!< RDZERO117 (Bit 5)                                     */
33478 #define GPIO_PINCFG117_RDZERO117_Msk      (0x20UL)                  /*!< RDZERO117 (Bitfield-Mask: 0x01)                       */
33479 #define GPIO_PINCFG117_INPEN117_Pos       (4UL)                     /*!< INPEN117 (Bit 4)                                      */
33480 #define GPIO_PINCFG117_INPEN117_Msk       (0x10UL)                  /*!< INPEN117 (Bitfield-Mask: 0x01)                        */
33481 #define GPIO_PINCFG117_FNCSEL117_Pos      (0UL)                     /*!< FNCSEL117 (Bit 0)                                     */
33482 #define GPIO_PINCFG117_FNCSEL117_Msk      (0xfUL)                   /*!< FNCSEL117 (Bitfield-Mask: 0x0f)                       */
33483 /* =======================================================  PINCFG118  ======================================================= */
33484 #define GPIO_PINCFG118_OUTCFG118_Pos      (8UL)                     /*!< OUTCFG118 (Bit 8)                                     */
33485 #define GPIO_PINCFG118_OUTCFG118_Msk      (0x300UL)                 /*!< OUTCFG118 (Bitfield-Mask: 0x03)                       */
33486 #define GPIO_PINCFG118_IRPTEN118_Pos      (6UL)                     /*!< IRPTEN118 (Bit 6)                                     */
33487 #define GPIO_PINCFG118_IRPTEN118_Msk      (0xc0UL)                  /*!< IRPTEN118 (Bitfield-Mask: 0x03)                       */
33488 #define GPIO_PINCFG118_RDZERO118_Pos      (5UL)                     /*!< RDZERO118 (Bit 5)                                     */
33489 #define GPIO_PINCFG118_RDZERO118_Msk      (0x20UL)                  /*!< RDZERO118 (Bitfield-Mask: 0x01)                       */
33490 #define GPIO_PINCFG118_INPEN118_Pos       (4UL)                     /*!< INPEN118 (Bit 4)                                      */
33491 #define GPIO_PINCFG118_INPEN118_Msk       (0x10UL)                  /*!< INPEN118 (Bitfield-Mask: 0x01)                        */
33492 #define GPIO_PINCFG118_FNCSEL118_Pos      (0UL)                     /*!< FNCSEL118 (Bit 0)                                     */
33493 #define GPIO_PINCFG118_FNCSEL118_Msk      (0xfUL)                   /*!< FNCSEL118 (Bitfield-Mask: 0x0f)                       */
33494 /* =======================================================  PINCFG119  ======================================================= */
33495 #define GPIO_PINCFG119_OUTCFG119_Pos      (8UL)                     /*!< OUTCFG119 (Bit 8)                                     */
33496 #define GPIO_PINCFG119_OUTCFG119_Msk      (0x300UL)                 /*!< OUTCFG119 (Bitfield-Mask: 0x03)                       */
33497 #define GPIO_PINCFG119_IRPTEN119_Pos      (6UL)                     /*!< IRPTEN119 (Bit 6)                                     */
33498 #define GPIO_PINCFG119_IRPTEN119_Msk      (0xc0UL)                  /*!< IRPTEN119 (Bitfield-Mask: 0x03)                       */
33499 #define GPIO_PINCFG119_RDZERO119_Pos      (5UL)                     /*!< RDZERO119 (Bit 5)                                     */
33500 #define GPIO_PINCFG119_RDZERO119_Msk      (0x20UL)                  /*!< RDZERO119 (Bitfield-Mask: 0x01)                       */
33501 #define GPIO_PINCFG119_INPEN119_Pos       (4UL)                     /*!< INPEN119 (Bit 4)                                      */
33502 #define GPIO_PINCFG119_INPEN119_Msk       (0x10UL)                  /*!< INPEN119 (Bitfield-Mask: 0x01)                        */
33503 #define GPIO_PINCFG119_FNCSEL119_Pos      (0UL)                     /*!< FNCSEL119 (Bit 0)                                     */
33504 #define GPIO_PINCFG119_FNCSEL119_Msk      (0xfUL)                   /*!< FNCSEL119 (Bitfield-Mask: 0x0f)                       */
33505 /* =======================================================  PINCFG120  ======================================================= */
33506 #define GPIO_PINCFG120_OUTCFG120_Pos      (8UL)                     /*!< OUTCFG120 (Bit 8)                                     */
33507 #define GPIO_PINCFG120_OUTCFG120_Msk      (0x300UL)                 /*!< OUTCFG120 (Bitfield-Mask: 0x03)                       */
33508 #define GPIO_PINCFG120_IRPTEN120_Pos      (6UL)                     /*!< IRPTEN120 (Bit 6)                                     */
33509 #define GPIO_PINCFG120_IRPTEN120_Msk      (0xc0UL)                  /*!< IRPTEN120 (Bitfield-Mask: 0x03)                       */
33510 #define GPIO_PINCFG120_RDZERO120_Pos      (5UL)                     /*!< RDZERO120 (Bit 5)                                     */
33511 #define GPIO_PINCFG120_RDZERO120_Msk      (0x20UL)                  /*!< RDZERO120 (Bitfield-Mask: 0x01)                       */
33512 #define GPIO_PINCFG120_INPEN120_Pos       (4UL)                     /*!< INPEN120 (Bit 4)                                      */
33513 #define GPIO_PINCFG120_INPEN120_Msk       (0x10UL)                  /*!< INPEN120 (Bitfield-Mask: 0x01)                        */
33514 #define GPIO_PINCFG120_FNCSEL120_Pos      (0UL)                     /*!< FNCSEL120 (Bit 0)                                     */
33515 #define GPIO_PINCFG120_FNCSEL120_Msk      (0xfUL)                   /*!< FNCSEL120 (Bitfield-Mask: 0x0f)                       */
33516 /* =======================================================  PINCFG121  ======================================================= */
33517 #define GPIO_PINCFG121_OUTCFG121_Pos      (8UL)                     /*!< OUTCFG121 (Bit 8)                                     */
33518 #define GPIO_PINCFG121_OUTCFG121_Msk      (0x300UL)                 /*!< OUTCFG121 (Bitfield-Mask: 0x03)                       */
33519 #define GPIO_PINCFG121_IRPTEN121_Pos      (6UL)                     /*!< IRPTEN121 (Bit 6)                                     */
33520 #define GPIO_PINCFG121_IRPTEN121_Msk      (0xc0UL)                  /*!< IRPTEN121 (Bitfield-Mask: 0x03)                       */
33521 #define GPIO_PINCFG121_RDZERO121_Pos      (5UL)                     /*!< RDZERO121 (Bit 5)                                     */
33522 #define GPIO_PINCFG121_RDZERO121_Msk      (0x20UL)                  /*!< RDZERO121 (Bitfield-Mask: 0x01)                       */
33523 #define GPIO_PINCFG121_INPEN121_Pos       (4UL)                     /*!< INPEN121 (Bit 4)                                      */
33524 #define GPIO_PINCFG121_INPEN121_Msk       (0x10UL)                  /*!< INPEN121 (Bitfield-Mask: 0x01)                        */
33525 #define GPIO_PINCFG121_FNCSEL121_Pos      (0UL)                     /*!< FNCSEL121 (Bit 0)                                     */
33526 #define GPIO_PINCFG121_FNCSEL121_Msk      (0xfUL)                   /*!< FNCSEL121 (Bitfield-Mask: 0x0f)                       */
33527 /* =======================================================  PINCFG122  ======================================================= */
33528 #define GPIO_PINCFG122_OUTCFG122_Pos      (8UL)                     /*!< OUTCFG122 (Bit 8)                                     */
33529 #define GPIO_PINCFG122_OUTCFG122_Msk      (0x300UL)                 /*!< OUTCFG122 (Bitfield-Mask: 0x03)                       */
33530 #define GPIO_PINCFG122_IRPTEN122_Pos      (6UL)                     /*!< IRPTEN122 (Bit 6)                                     */
33531 #define GPIO_PINCFG122_IRPTEN122_Msk      (0xc0UL)                  /*!< IRPTEN122 (Bitfield-Mask: 0x03)                       */
33532 #define GPIO_PINCFG122_RDZERO122_Pos      (5UL)                     /*!< RDZERO122 (Bit 5)                                     */
33533 #define GPIO_PINCFG122_RDZERO122_Msk      (0x20UL)                  /*!< RDZERO122 (Bitfield-Mask: 0x01)                       */
33534 #define GPIO_PINCFG122_INPEN122_Pos       (4UL)                     /*!< INPEN122 (Bit 4)                                      */
33535 #define GPIO_PINCFG122_INPEN122_Msk       (0x10UL)                  /*!< INPEN122 (Bitfield-Mask: 0x01)                        */
33536 #define GPIO_PINCFG122_FNCSEL122_Pos      (0UL)                     /*!< FNCSEL122 (Bit 0)                                     */
33537 #define GPIO_PINCFG122_FNCSEL122_Msk      (0xfUL)                   /*!< FNCSEL122 (Bitfield-Mask: 0x0f)                       */
33538 /* =======================================================  PINCFG123  ======================================================= */
33539 #define GPIO_PINCFG123_OUTCFG123_Pos      (8UL)                     /*!< OUTCFG123 (Bit 8)                                     */
33540 #define GPIO_PINCFG123_OUTCFG123_Msk      (0x300UL)                 /*!< OUTCFG123 (Bitfield-Mask: 0x03)                       */
33541 #define GPIO_PINCFG123_IRPTEN123_Pos      (6UL)                     /*!< IRPTEN123 (Bit 6)                                     */
33542 #define GPIO_PINCFG123_IRPTEN123_Msk      (0xc0UL)                  /*!< IRPTEN123 (Bitfield-Mask: 0x03)                       */
33543 #define GPIO_PINCFG123_RDZERO123_Pos      (5UL)                     /*!< RDZERO123 (Bit 5)                                     */
33544 #define GPIO_PINCFG123_RDZERO123_Msk      (0x20UL)                  /*!< RDZERO123 (Bitfield-Mask: 0x01)                       */
33545 #define GPIO_PINCFG123_INPEN123_Pos       (4UL)                     /*!< INPEN123 (Bit 4)                                      */
33546 #define GPIO_PINCFG123_INPEN123_Msk       (0x10UL)                  /*!< INPEN123 (Bitfield-Mask: 0x01)                        */
33547 #define GPIO_PINCFG123_FNCSEL123_Pos      (0UL)                     /*!< FNCSEL123 (Bit 0)                                     */
33548 #define GPIO_PINCFG123_FNCSEL123_Msk      (0xfUL)                   /*!< FNCSEL123 (Bitfield-Mask: 0x0f)                       */
33549 /* =======================================================  PINCFG124  ======================================================= */
33550 #define GPIO_PINCFG124_OUTCFG124_Pos      (8UL)                     /*!< OUTCFG124 (Bit 8)                                     */
33551 #define GPIO_PINCFG124_OUTCFG124_Msk      (0x300UL)                 /*!< OUTCFG124 (Bitfield-Mask: 0x03)                       */
33552 #define GPIO_PINCFG124_IRPTEN124_Pos      (6UL)                     /*!< IRPTEN124 (Bit 6)                                     */
33553 #define GPIO_PINCFG124_IRPTEN124_Msk      (0xc0UL)                  /*!< IRPTEN124 (Bitfield-Mask: 0x03)                       */
33554 #define GPIO_PINCFG124_RDZERO124_Pos      (5UL)                     /*!< RDZERO124 (Bit 5)                                     */
33555 #define GPIO_PINCFG124_RDZERO124_Msk      (0x20UL)                  /*!< RDZERO124 (Bitfield-Mask: 0x01)                       */
33556 #define GPIO_PINCFG124_INPEN124_Pos       (4UL)                     /*!< INPEN124 (Bit 4)                                      */
33557 #define GPIO_PINCFG124_INPEN124_Msk       (0x10UL)                  /*!< INPEN124 (Bitfield-Mask: 0x01)                        */
33558 #define GPIO_PINCFG124_FNCSEL124_Pos      (0UL)                     /*!< FNCSEL124 (Bit 0)                                     */
33559 #define GPIO_PINCFG124_FNCSEL124_Msk      (0xfUL)                   /*!< FNCSEL124 (Bitfield-Mask: 0x0f)                       */
33560 /* =======================================================  PINCFG125  ======================================================= */
33561 #define GPIO_PINCFG125_OUTCFG125_Pos      (8UL)                     /*!< OUTCFG125 (Bit 8)                                     */
33562 #define GPIO_PINCFG125_OUTCFG125_Msk      (0x300UL)                 /*!< OUTCFG125 (Bitfield-Mask: 0x03)                       */
33563 #define GPIO_PINCFG125_IRPTEN125_Pos      (6UL)                     /*!< IRPTEN125 (Bit 6)                                     */
33564 #define GPIO_PINCFG125_IRPTEN125_Msk      (0xc0UL)                  /*!< IRPTEN125 (Bitfield-Mask: 0x03)                       */
33565 #define GPIO_PINCFG125_RDZERO125_Pos      (5UL)                     /*!< RDZERO125 (Bit 5)                                     */
33566 #define GPIO_PINCFG125_RDZERO125_Msk      (0x20UL)                  /*!< RDZERO125 (Bitfield-Mask: 0x01)                       */
33567 #define GPIO_PINCFG125_INPEN125_Pos       (4UL)                     /*!< INPEN125 (Bit 4)                                      */
33568 #define GPIO_PINCFG125_INPEN125_Msk       (0x10UL)                  /*!< INPEN125 (Bitfield-Mask: 0x01)                        */
33569 #define GPIO_PINCFG125_FNCSEL125_Pos      (0UL)                     /*!< FNCSEL125 (Bit 0)                                     */
33570 #define GPIO_PINCFG125_FNCSEL125_Msk      (0xfUL)                   /*!< FNCSEL125 (Bitfield-Mask: 0x0f)                       */
33571 /* =======================================================  PINCFG126  ======================================================= */
33572 #define GPIO_PINCFG126_OUTCFG126_Pos      (8UL)                     /*!< OUTCFG126 (Bit 8)                                     */
33573 #define GPIO_PINCFG126_OUTCFG126_Msk      (0x300UL)                 /*!< OUTCFG126 (Bitfield-Mask: 0x03)                       */
33574 #define GPIO_PINCFG126_IRPTEN126_Pos      (6UL)                     /*!< IRPTEN126 (Bit 6)                                     */
33575 #define GPIO_PINCFG126_IRPTEN126_Msk      (0xc0UL)                  /*!< IRPTEN126 (Bitfield-Mask: 0x03)                       */
33576 #define GPIO_PINCFG126_RDZERO126_Pos      (5UL)                     /*!< RDZERO126 (Bit 5)                                     */
33577 #define GPIO_PINCFG126_RDZERO126_Msk      (0x20UL)                  /*!< RDZERO126 (Bitfield-Mask: 0x01)                       */
33578 #define GPIO_PINCFG126_INPEN126_Pos       (4UL)                     /*!< INPEN126 (Bit 4)                                      */
33579 #define GPIO_PINCFG126_INPEN126_Msk       (0x10UL)                  /*!< INPEN126 (Bitfield-Mask: 0x01)                        */
33580 #define GPIO_PINCFG126_FNCSEL126_Pos      (0UL)                     /*!< FNCSEL126 (Bit 0)                                     */
33581 #define GPIO_PINCFG126_FNCSEL126_Msk      (0xfUL)                   /*!< FNCSEL126 (Bitfield-Mask: 0x0f)                       */
33582 /* =======================================================  PINCFG127  ======================================================= */
33583 #define GPIO_PINCFG127_OUTCFG127_Pos      (8UL)                     /*!< OUTCFG127 (Bit 8)                                     */
33584 #define GPIO_PINCFG127_OUTCFG127_Msk      (0x300UL)                 /*!< OUTCFG127 (Bitfield-Mask: 0x03)                       */
33585 #define GPIO_PINCFG127_IRPTEN127_Pos      (6UL)                     /*!< IRPTEN127 (Bit 6)                                     */
33586 #define GPIO_PINCFG127_IRPTEN127_Msk      (0xc0UL)                  /*!< IRPTEN127 (Bitfield-Mask: 0x03)                       */
33587 #define GPIO_PINCFG127_RDZERO127_Pos      (5UL)                     /*!< RDZERO127 (Bit 5)                                     */
33588 #define GPIO_PINCFG127_RDZERO127_Msk      (0x20UL)                  /*!< RDZERO127 (Bitfield-Mask: 0x01)                       */
33589 #define GPIO_PINCFG127_INPEN127_Pos       (4UL)                     /*!< INPEN127 (Bit 4)                                      */
33590 #define GPIO_PINCFG127_INPEN127_Msk       (0x10UL)                  /*!< INPEN127 (Bitfield-Mask: 0x01)                        */
33591 #define GPIO_PINCFG127_FNCSEL127_Pos      (0UL)                     /*!< FNCSEL127 (Bit 0)                                     */
33592 #define GPIO_PINCFG127_FNCSEL127_Msk      (0xfUL)                   /*!< FNCSEL127 (Bitfield-Mask: 0x0f)                       */
33593 /* ========================================================  PADKEY  ========================================================= */
33594 #define GPIO_PADKEY_PADKEY_Pos            (0UL)                     /*!< PADKEY (Bit 0)                                        */
33595 #define GPIO_PADKEY_PADKEY_Msk            (0xffffffffUL)            /*!< PADKEY (Bitfield-Mask: 0xffffffff)                    */
33596 /* ==========================================================  RD0  ========================================================== */
33597 #define GPIO_RD0_RD0_Pos                  (0UL)                     /*!< RD0 (Bit 0)                                           */
33598 #define GPIO_RD0_RD0_Msk                  (0xffffffffUL)            /*!< RD0 (Bitfield-Mask: 0xffffffff)                       */
33599 /* ==========================================================  RD1  ========================================================== */
33600 #define GPIO_RD1_RD1_Pos                  (0UL)                     /*!< RD1 (Bit 0)                                           */
33601 #define GPIO_RD1_RD1_Msk                  (0xffffffffUL)            /*!< RD1 (Bitfield-Mask: 0xffffffff)                       */
33602 /* ==========================================================  RD2  ========================================================== */
33603 #define GPIO_RD2_RD2_Pos                  (0UL)                     /*!< RD2 (Bit 0)                                           */
33604 #define GPIO_RD2_RD2_Msk                  (0xffffffffUL)            /*!< RD2 (Bitfield-Mask: 0xffffffff)                       */
33605 /* ==========================================================  RD3  ========================================================== */
33606 #define GPIO_RD3_RD3_Pos                  (0UL)                     /*!< RD3 (Bit 0)                                           */
33607 #define GPIO_RD3_RD3_Msk                  (0xffffffffUL)            /*!< RD3 (Bitfield-Mask: 0xffffffff)                       */
33608 /* ==========================================================  WT0  ========================================================== */
33609 #define GPIO_WT0_WT0_Pos                  (0UL)                     /*!< WT0 (Bit 0)                                           */
33610 #define GPIO_WT0_WT0_Msk                  (0xffffffffUL)            /*!< WT0 (Bitfield-Mask: 0xffffffff)                       */
33611 /* ==========================================================  WT1  ========================================================== */
33612 #define GPIO_WT1_WT1_Pos                  (0UL)                     /*!< WT1 (Bit 0)                                           */
33613 #define GPIO_WT1_WT1_Msk                  (0xffffffffUL)            /*!< WT1 (Bitfield-Mask: 0xffffffff)                       */
33614 /* ==========================================================  WT2  ========================================================== */
33615 #define GPIO_WT2_WT2_Pos                  (0UL)                     /*!< WT2 (Bit 0)                                           */
33616 #define GPIO_WT2_WT2_Msk                  (0xffffffffUL)            /*!< WT2 (Bitfield-Mask: 0xffffffff)                       */
33617 /* ==========================================================  WT3  ========================================================== */
33618 #define GPIO_WT3_WT3_Pos                  (0UL)                     /*!< WT3 (Bit 0)                                           */
33619 #define GPIO_WT3_WT3_Msk                  (0xffffffffUL)            /*!< WT3 (Bitfield-Mask: 0xffffffff)                       */
33620 /* =========================================================  WTS0  ========================================================== */
33621 #define GPIO_WTS0_WTS0_Pos                (0UL)                     /*!< WTS0 (Bit 0)                                          */
33622 #define GPIO_WTS0_WTS0_Msk                (0xffffffffUL)            /*!< WTS0 (Bitfield-Mask: 0xffffffff)                      */
33623 /* =========================================================  WTS1  ========================================================== */
33624 #define GPIO_WTS1_WTS1_Pos                (0UL)                     /*!< WTS1 (Bit 0)                                          */
33625 #define GPIO_WTS1_WTS1_Msk                (0xffffffffUL)            /*!< WTS1 (Bitfield-Mask: 0xffffffff)                      */
33626 /* =========================================================  WTS2  ========================================================== */
33627 #define GPIO_WTS2_WTS2_Pos                (0UL)                     /*!< WTS2 (Bit 0)                                          */
33628 #define GPIO_WTS2_WTS2_Msk                (0xffffffffUL)            /*!< WTS2 (Bitfield-Mask: 0xffffffff)                      */
33629 /* =========================================================  WTS3  ========================================================== */
33630 #define GPIO_WTS3_WTS3_Pos                (0UL)                     /*!< WTS3 (Bit 0)                                          */
33631 #define GPIO_WTS3_WTS3_Msk                (0xffffffffUL)            /*!< WTS3 (Bitfield-Mask: 0xffffffff)                      */
33632 /* =========================================================  WTC0  ========================================================== */
33633 #define GPIO_WTC0_WTC0_Pos                (0UL)                     /*!< WTC0 (Bit 0)                                          */
33634 #define GPIO_WTC0_WTC0_Msk                (0xffffffffUL)            /*!< WTC0 (Bitfield-Mask: 0xffffffff)                      */
33635 /* =========================================================  WTC1  ========================================================== */
33636 #define GPIO_WTC1_WTC1_Pos                (0UL)                     /*!< WTC1 (Bit 0)                                          */
33637 #define GPIO_WTC1_WTC1_Msk                (0xffffffffUL)            /*!< WTC1 (Bitfield-Mask: 0xffffffff)                      */
33638 /* =========================================================  WTC2  ========================================================== */
33639 #define GPIO_WTC2_WTC2_Pos                (0UL)                     /*!< WTC2 (Bit 0)                                          */
33640 #define GPIO_WTC2_WTC2_Msk                (0xffffffffUL)            /*!< WTC2 (Bitfield-Mask: 0xffffffff)                      */
33641 /* =========================================================  WTC3  ========================================================== */
33642 #define GPIO_WTC3_WTC3_Pos                (0UL)                     /*!< WTC3 (Bit 0)                                          */
33643 #define GPIO_WTC3_WTC3_Msk                (0xffffffffUL)            /*!< WTC3 (Bitfield-Mask: 0xffffffff)                      */
33644 /* ==========================================================  EN0  ========================================================== */
33645 #define GPIO_EN0_EN0_Pos                  (0UL)                     /*!< EN0 (Bit 0)                                           */
33646 #define GPIO_EN0_EN0_Msk                  (0xffffffffUL)            /*!< EN0 (Bitfield-Mask: 0xffffffff)                       */
33647 /* ==========================================================  EN1  ========================================================== */
33648 #define GPIO_EN1_EN1_Pos                  (0UL)                     /*!< EN1 (Bit 0)                                           */
33649 #define GPIO_EN1_EN1_Msk                  (0xffffffffUL)            /*!< EN1 (Bitfield-Mask: 0xffffffff)                       */
33650 /* ==========================================================  EN2  ========================================================== */
33651 #define GPIO_EN2_EN2_Pos                  (0UL)                     /*!< EN2 (Bit 0)                                           */
33652 #define GPIO_EN2_EN2_Msk                  (0xffffffffUL)            /*!< EN2 (Bitfield-Mask: 0xffffffff)                       */
33653 /* ==========================================================  EN3  ========================================================== */
33654 #define GPIO_EN3_EN3_Pos                  (0UL)                     /*!< EN3 (Bit 0)                                           */
33655 #define GPIO_EN3_EN3_Msk                  (0xffffffffUL)            /*!< EN3 (Bitfield-Mask: 0xffffffff)                       */
33656 /* =========================================================  ENS0  ========================================================== */
33657 #define GPIO_ENS0_ENS0_Pos                (0UL)                     /*!< ENS0 (Bit 0)                                          */
33658 #define GPIO_ENS0_ENS0_Msk                (0xffffffffUL)            /*!< ENS0 (Bitfield-Mask: 0xffffffff)                      */
33659 /* =========================================================  ENS1  ========================================================== */
33660 #define GPIO_ENS1_ENS1_Pos                (0UL)                     /*!< ENS1 (Bit 0)                                          */
33661 #define GPIO_ENS1_ENS1_Msk                (0xffffffffUL)            /*!< ENS1 (Bitfield-Mask: 0xffffffff)                      */
33662 /* =========================================================  ENS2  ========================================================== */
33663 #define GPIO_ENS2_ENS2_Pos                (0UL)                     /*!< ENS2 (Bit 0)                                          */
33664 #define GPIO_ENS2_ENS2_Msk                (0xffffffffUL)            /*!< ENS2 (Bitfield-Mask: 0xffffffff)                      */
33665 /* =========================================================  ENS3  ========================================================== */
33666 #define GPIO_ENS3_ENS3_Pos                (0UL)                     /*!< ENS3 (Bit 0)                                          */
33667 #define GPIO_ENS3_ENS3_Msk                (0xffffffffUL)            /*!< ENS3 (Bitfield-Mask: 0xffffffff)                      */
33668 /* =========================================================  ENC0  ========================================================== */
33669 #define GPIO_ENC0_ENC0_Pos                (0UL)                     /*!< ENC0 (Bit 0)                                          */
33670 #define GPIO_ENC0_ENC0_Msk                (0xffffffffUL)            /*!< ENC0 (Bitfield-Mask: 0xffffffff)                      */
33671 /* =========================================================  ENC1  ========================================================== */
33672 #define GPIO_ENC1_ENC1_Pos                (0UL)                     /*!< ENC1 (Bit 0)                                          */
33673 #define GPIO_ENC1_ENC1_Msk                (0xffffffffUL)            /*!< ENC1 (Bitfield-Mask: 0xffffffff)                      */
33674 /* =========================================================  ENC2  ========================================================== */
33675 #define GPIO_ENC2_ENC2_Pos                (0UL)                     /*!< ENC2 (Bit 0)                                          */
33676 #define GPIO_ENC2_ENC2_Msk                (0xffffffffUL)            /*!< ENC2 (Bitfield-Mask: 0xffffffff)                      */
33677 /* =========================================================  ENC3  ========================================================== */
33678 #define GPIO_ENC3_ENC3_Pos                (0UL)                     /*!< ENC3 (Bit 0)                                          */
33679 #define GPIO_ENC3_ENC3_Msk                (0xffffffffUL)            /*!< ENC3 (Bitfield-Mask: 0xffffffff)                      */
33680 /* ========================================================  IOM0IRQ  ======================================================== */
33681 #define GPIO_IOM0IRQ_IOM0IRQ_Pos          (0UL)                     /*!< IOM0IRQ (Bit 0)                                       */
33682 #define GPIO_IOM0IRQ_IOM0IRQ_Msk          (0x7fUL)                  /*!< IOM0IRQ (Bitfield-Mask: 0x7f)                         */
33683 /* ========================================================  IOM1IRQ  ======================================================== */
33684 #define GPIO_IOM1IRQ_IOM1IRQ_Pos          (0UL)                     /*!< IOM1IRQ (Bit 0)                                       */
33685 #define GPIO_IOM1IRQ_IOM1IRQ_Msk          (0x7fUL)                  /*!< IOM1IRQ (Bitfield-Mask: 0x7f)                         */
33686 /* ========================================================  IOM2IRQ  ======================================================== */
33687 #define GPIO_IOM2IRQ_IOM2IRQ_Pos          (0UL)                     /*!< IOM2IRQ (Bit 0)                                       */
33688 #define GPIO_IOM2IRQ_IOM2IRQ_Msk          (0x7fUL)                  /*!< IOM2IRQ (Bitfield-Mask: 0x7f)                         */
33689 /* ========================================================  IOM3IRQ  ======================================================== */
33690 #define GPIO_IOM3IRQ_IOM3IRQ_Pos          (0UL)                     /*!< IOM3IRQ (Bit 0)                                       */
33691 #define GPIO_IOM3IRQ_IOM3IRQ_Msk          (0x7fUL)                  /*!< IOM3IRQ (Bitfield-Mask: 0x7f)                         */
33692 /* ========================================================  IOM4IRQ  ======================================================== */
33693 #define GPIO_IOM4IRQ_IOM4IRQ_Pos          (0UL)                     /*!< IOM4IRQ (Bit 0)                                       */
33694 #define GPIO_IOM4IRQ_IOM4IRQ_Msk          (0x7fUL)                  /*!< IOM4IRQ (Bitfield-Mask: 0x7f)                         */
33695 /* ========================================================  IOM5IRQ  ======================================================== */
33696 #define GPIO_IOM5IRQ_IOM5IRQ_Pos          (0UL)                     /*!< IOM5IRQ (Bit 0)                                       */
33697 #define GPIO_IOM5IRQ_IOM5IRQ_Msk          (0x7fUL)                  /*!< IOM5IRQ (Bitfield-Mask: 0x7f)                         */
33698 /* ========================================================  IOM6IRQ  ======================================================== */
33699 #define GPIO_IOM6IRQ_IOM6IRQ_Pos          (0UL)                     /*!< IOM6IRQ (Bit 0)                                       */
33700 #define GPIO_IOM6IRQ_IOM6IRQ_Msk          (0x7fUL)                  /*!< IOM6IRQ (Bitfield-Mask: 0x7f)                         */
33701 /* ========================================================  IOM7IRQ  ======================================================== */
33702 #define GPIO_IOM7IRQ_IOM7IRQ_Pos          (0UL)                     /*!< IOM7IRQ (Bit 0)                                       */
33703 #define GPIO_IOM7IRQ_IOM7IRQ_Msk          (0x7fUL)                  /*!< IOM7IRQ (Bitfield-Mask: 0x7f)                         */
33704 /* =======================================================  SDIFCDWP  ======================================================== */
33705 #define GPIO_SDIFCDWP_SDIFWP_Pos          (8UL)                     /*!< SDIFWP (Bit 8)                                        */
33706 #define GPIO_SDIFCDWP_SDIFWP_Msk          (0x7f00UL)                /*!< SDIFWP (Bitfield-Mask: 0x7f)                          */
33707 #define GPIO_SDIFCDWP_SDIFCD_Pos          (0UL)                     /*!< SDIFCD (Bit 0)                                        */
33708 #define GPIO_SDIFCDWP_SDIFCD_Msk          (0x7fUL)                  /*!< SDIFCD (Bitfield-Mask: 0x7f)                          */
33709 /* ========================================================  OBSDATA  ======================================================== */
33710 #define GPIO_OBSDATA_OBSDATA_Pos          (0UL)                     /*!< OBSDATA (Bit 0)                                       */
33711 #define GPIO_OBSDATA_OBSDATA_Msk          (0xffffUL)                /*!< OBSDATA (Bitfield-Mask: 0xffff)                       */
33712 /* ========================================================  IEOBS0  ========================================================= */
33713 #define GPIO_IEOBS0_IEDATA0_Pos           (0UL)                     /*!< IEDATA0 (Bit 0)                                       */
33714 #define GPIO_IEOBS0_IEDATA0_Msk           (0xffffffffUL)            /*!< IEDATA0 (Bitfield-Mask: 0xffffffff)                   */
33715 /* ========================================================  IEOBS1  ========================================================= */
33716 #define GPIO_IEOBS1_IEDATA1_Pos           (0UL)                     /*!< IEDATA1 (Bit 0)                                       */
33717 #define GPIO_IEOBS1_IEDATA1_Msk           (0xffffffffUL)            /*!< IEDATA1 (Bitfield-Mask: 0xffffffff)                   */
33718 /* ========================================================  IEOBS2  ========================================================= */
33719 #define GPIO_IEOBS2_IEDATA2_Pos           (0UL)                     /*!< IEDATA2 (Bit 0)                                       */
33720 #define GPIO_IEOBS2_IEDATA2_Msk           (0xffffffffUL)            /*!< IEDATA2 (Bitfield-Mask: 0xffffffff)                   */
33721 /* ========================================================  IEOBS3  ========================================================= */
33722 #define GPIO_IEOBS3_IEDATA3_Pos           (0UL)                     /*!< IEDATA3 (Bit 0)                                       */
33723 #define GPIO_IEOBS3_IEDATA3_Msk           (0xffffffffUL)            /*!< IEDATA3 (Bitfield-Mask: 0xffffffff)                   */
33724 /* ========================================================  OEOBS0  ========================================================= */
33725 #define GPIO_OEOBS0_OEDATA0_Pos           (0UL)                     /*!< OEDATA0 (Bit 0)                                       */
33726 #define GPIO_OEOBS0_OEDATA0_Msk           (0xffffffffUL)            /*!< OEDATA0 (Bitfield-Mask: 0xffffffff)                   */
33727 /* ========================================================  OEOBS1  ========================================================= */
33728 #define GPIO_OEOBS1_OEDATA1_Pos           (0UL)                     /*!< OEDATA1 (Bit 0)                                       */
33729 #define GPIO_OEOBS1_OEDATA1_Msk           (0xffffffffUL)            /*!< OEDATA1 (Bitfield-Mask: 0xffffffff)                   */
33730 /* ========================================================  OEOBS2  ========================================================= */
33731 #define GPIO_OEOBS2_OEDATA2_Pos           (0UL)                     /*!< OEDATA2 (Bit 0)                                       */
33732 #define GPIO_OEOBS2_OEDATA2_Msk           (0xffffffffUL)            /*!< OEDATA2 (Bitfield-Mask: 0xffffffff)                   */
33733 /* ========================================================  OEOBS3  ========================================================= */
33734 #define GPIO_OEOBS3_OEDATA3_Pos           (0UL)                     /*!< OEDATA3 (Bit 0)                                       */
33735 #define GPIO_OEOBS3_OEDATA3_Msk           (0xffffffffUL)            /*!< OEDATA3 (Bitfield-Mask: 0xffffffff)                   */
33736 /* ======================================================  MCUN0INT0EN  ====================================================== */
33737 #define GPIO_MCUN0INT0EN_MCUN0GPIO31_Pos  (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
33738 #define GPIO_MCUN0INT0EN_MCUN0GPIO31_Msk  (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
33739 #define GPIO_MCUN0INT0EN_MCUN0GPIO30_Pos  (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
33740 #define GPIO_MCUN0INT0EN_MCUN0GPIO30_Msk  (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
33741 #define GPIO_MCUN0INT0EN_MCUN0GPIO29_Pos  (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
33742 #define GPIO_MCUN0INT0EN_MCUN0GPIO29_Msk  (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
33743 #define GPIO_MCUN0INT0EN_MCUN0GPIO28_Pos  (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
33744 #define GPIO_MCUN0INT0EN_MCUN0GPIO28_Msk  (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
33745 #define GPIO_MCUN0INT0EN_MCUN0GPIO27_Pos  (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
33746 #define GPIO_MCUN0INT0EN_MCUN0GPIO27_Msk  (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
33747 #define GPIO_MCUN0INT0EN_MCUN0GPIO26_Pos  (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
33748 #define GPIO_MCUN0INT0EN_MCUN0GPIO26_Msk  (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
33749 #define GPIO_MCUN0INT0EN_MCUN0GPIO25_Pos  (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
33750 #define GPIO_MCUN0INT0EN_MCUN0GPIO25_Msk  (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
33751 #define GPIO_MCUN0INT0EN_MCUN0GPIO24_Pos  (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
33752 #define GPIO_MCUN0INT0EN_MCUN0GPIO24_Msk  (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
33753 #define GPIO_MCUN0INT0EN_MCUN0GPIO23_Pos  (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
33754 #define GPIO_MCUN0INT0EN_MCUN0GPIO23_Msk  (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
33755 #define GPIO_MCUN0INT0EN_MCUN0GPIO22_Pos  (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
33756 #define GPIO_MCUN0INT0EN_MCUN0GPIO22_Msk  (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
33757 #define GPIO_MCUN0INT0EN_MCUN0GPIO21_Pos  (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
33758 #define GPIO_MCUN0INT0EN_MCUN0GPIO21_Msk  (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
33759 #define GPIO_MCUN0INT0EN_MCUN0GPIO20_Pos  (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
33760 #define GPIO_MCUN0INT0EN_MCUN0GPIO20_Msk  (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
33761 #define GPIO_MCUN0INT0EN_MCUN0GPIO19_Pos  (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
33762 #define GPIO_MCUN0INT0EN_MCUN0GPIO19_Msk  (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
33763 #define GPIO_MCUN0INT0EN_MCUN0GPIO18_Pos  (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
33764 #define GPIO_MCUN0INT0EN_MCUN0GPIO18_Msk  (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
33765 #define GPIO_MCUN0INT0EN_MCUN0GPIO17_Pos  (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
33766 #define GPIO_MCUN0INT0EN_MCUN0GPIO17_Msk  (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
33767 #define GPIO_MCUN0INT0EN_MCUN0GPIO16_Pos  (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
33768 #define GPIO_MCUN0INT0EN_MCUN0GPIO16_Msk  (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
33769 #define GPIO_MCUN0INT0EN_MCUN0GPIO15_Pos  (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
33770 #define GPIO_MCUN0INT0EN_MCUN0GPIO15_Msk  (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
33771 #define GPIO_MCUN0INT0EN_MCUN0GPIO14_Pos  (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
33772 #define GPIO_MCUN0INT0EN_MCUN0GPIO14_Msk  (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
33773 #define GPIO_MCUN0INT0EN_MCUN0GPIO13_Pos  (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
33774 #define GPIO_MCUN0INT0EN_MCUN0GPIO13_Msk  (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
33775 #define GPIO_MCUN0INT0EN_MCUN0GPIO12_Pos  (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
33776 #define GPIO_MCUN0INT0EN_MCUN0GPIO12_Msk  (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
33777 #define GPIO_MCUN0INT0EN_MCUN0GPIO11_Pos  (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
33778 #define GPIO_MCUN0INT0EN_MCUN0GPIO11_Msk  (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
33779 #define GPIO_MCUN0INT0EN_MCUN0GPIO10_Pos  (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
33780 #define GPIO_MCUN0INT0EN_MCUN0GPIO10_Msk  (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
33781 #define GPIO_MCUN0INT0EN_MCUN0GPIO9_Pos   (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
33782 #define GPIO_MCUN0INT0EN_MCUN0GPIO9_Msk   (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
33783 #define GPIO_MCUN0INT0EN_MCUN0GPIO8_Pos   (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
33784 #define GPIO_MCUN0INT0EN_MCUN0GPIO8_Msk   (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
33785 #define GPIO_MCUN0INT0EN_MCUN0GPIO7_Pos   (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
33786 #define GPIO_MCUN0INT0EN_MCUN0GPIO7_Msk   (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
33787 #define GPIO_MCUN0INT0EN_MCUN0GPIO6_Pos   (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
33788 #define GPIO_MCUN0INT0EN_MCUN0GPIO6_Msk   (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
33789 #define GPIO_MCUN0INT0EN_MCUN0GPIO5_Pos   (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
33790 #define GPIO_MCUN0INT0EN_MCUN0GPIO5_Msk   (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
33791 #define GPIO_MCUN0INT0EN_MCUN0GPIO4_Pos   (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
33792 #define GPIO_MCUN0INT0EN_MCUN0GPIO4_Msk   (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
33793 #define GPIO_MCUN0INT0EN_MCUN0GPIO3_Pos   (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
33794 #define GPIO_MCUN0INT0EN_MCUN0GPIO3_Msk   (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
33795 #define GPIO_MCUN0INT0EN_MCUN0GPIO2_Pos   (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
33796 #define GPIO_MCUN0INT0EN_MCUN0GPIO2_Msk   (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
33797 #define GPIO_MCUN0INT0EN_MCUN0GPIO1_Pos   (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
33798 #define GPIO_MCUN0INT0EN_MCUN0GPIO1_Msk   (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
33799 #define GPIO_MCUN0INT0EN_MCUN0GPIO0_Pos   (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
33800 #define GPIO_MCUN0INT0EN_MCUN0GPIO0_Msk   (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
33801 /* =====================================================  MCUN0INT0STAT  ===================================================== */
33802 #define GPIO_MCUN0INT0STAT_MCUN0GPIO31_Pos (31UL)                   /*!< MCUN0GPIO31 (Bit 31)                                  */
33803 #define GPIO_MCUN0INT0STAT_MCUN0GPIO31_Msk (0x80000000UL)           /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
33804 #define GPIO_MCUN0INT0STAT_MCUN0GPIO30_Pos (30UL)                   /*!< MCUN0GPIO30 (Bit 30)                                  */
33805 #define GPIO_MCUN0INT0STAT_MCUN0GPIO30_Msk (0x40000000UL)           /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
33806 #define GPIO_MCUN0INT0STAT_MCUN0GPIO29_Pos (29UL)                   /*!< MCUN0GPIO29 (Bit 29)                                  */
33807 #define GPIO_MCUN0INT0STAT_MCUN0GPIO29_Msk (0x20000000UL)           /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
33808 #define GPIO_MCUN0INT0STAT_MCUN0GPIO28_Pos (28UL)                   /*!< MCUN0GPIO28 (Bit 28)                                  */
33809 #define GPIO_MCUN0INT0STAT_MCUN0GPIO28_Msk (0x10000000UL)           /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
33810 #define GPIO_MCUN0INT0STAT_MCUN0GPIO27_Pos (27UL)                   /*!< MCUN0GPIO27 (Bit 27)                                  */
33811 #define GPIO_MCUN0INT0STAT_MCUN0GPIO27_Msk (0x8000000UL)            /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
33812 #define GPIO_MCUN0INT0STAT_MCUN0GPIO26_Pos (26UL)                   /*!< MCUN0GPIO26 (Bit 26)                                  */
33813 #define GPIO_MCUN0INT0STAT_MCUN0GPIO26_Msk (0x4000000UL)            /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
33814 #define GPIO_MCUN0INT0STAT_MCUN0GPIO25_Pos (25UL)                   /*!< MCUN0GPIO25 (Bit 25)                                  */
33815 #define GPIO_MCUN0INT0STAT_MCUN0GPIO25_Msk (0x2000000UL)            /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
33816 #define GPIO_MCUN0INT0STAT_MCUN0GPIO24_Pos (24UL)                   /*!< MCUN0GPIO24 (Bit 24)                                  */
33817 #define GPIO_MCUN0INT0STAT_MCUN0GPIO24_Msk (0x1000000UL)            /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
33818 #define GPIO_MCUN0INT0STAT_MCUN0GPIO23_Pos (23UL)                   /*!< MCUN0GPIO23 (Bit 23)                                  */
33819 #define GPIO_MCUN0INT0STAT_MCUN0GPIO23_Msk (0x800000UL)             /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
33820 #define GPIO_MCUN0INT0STAT_MCUN0GPIO22_Pos (22UL)                   /*!< MCUN0GPIO22 (Bit 22)                                  */
33821 #define GPIO_MCUN0INT0STAT_MCUN0GPIO22_Msk (0x400000UL)             /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
33822 #define GPIO_MCUN0INT0STAT_MCUN0GPIO21_Pos (21UL)                   /*!< MCUN0GPIO21 (Bit 21)                                  */
33823 #define GPIO_MCUN0INT0STAT_MCUN0GPIO21_Msk (0x200000UL)             /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
33824 #define GPIO_MCUN0INT0STAT_MCUN0GPIO20_Pos (20UL)                   /*!< MCUN0GPIO20 (Bit 20)                                  */
33825 #define GPIO_MCUN0INT0STAT_MCUN0GPIO20_Msk (0x100000UL)             /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
33826 #define GPIO_MCUN0INT0STAT_MCUN0GPIO19_Pos (19UL)                   /*!< MCUN0GPIO19 (Bit 19)                                  */
33827 #define GPIO_MCUN0INT0STAT_MCUN0GPIO19_Msk (0x80000UL)              /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
33828 #define GPIO_MCUN0INT0STAT_MCUN0GPIO18_Pos (18UL)                   /*!< MCUN0GPIO18 (Bit 18)                                  */
33829 #define GPIO_MCUN0INT0STAT_MCUN0GPIO18_Msk (0x40000UL)              /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
33830 #define GPIO_MCUN0INT0STAT_MCUN0GPIO17_Pos (17UL)                   /*!< MCUN0GPIO17 (Bit 17)                                  */
33831 #define GPIO_MCUN0INT0STAT_MCUN0GPIO17_Msk (0x20000UL)              /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
33832 #define GPIO_MCUN0INT0STAT_MCUN0GPIO16_Pos (16UL)                   /*!< MCUN0GPIO16 (Bit 16)                                  */
33833 #define GPIO_MCUN0INT0STAT_MCUN0GPIO16_Msk (0x10000UL)              /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
33834 #define GPIO_MCUN0INT0STAT_MCUN0GPIO15_Pos (15UL)                   /*!< MCUN0GPIO15 (Bit 15)                                  */
33835 #define GPIO_MCUN0INT0STAT_MCUN0GPIO15_Msk (0x8000UL)               /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
33836 #define GPIO_MCUN0INT0STAT_MCUN0GPIO14_Pos (14UL)                   /*!< MCUN0GPIO14 (Bit 14)                                  */
33837 #define GPIO_MCUN0INT0STAT_MCUN0GPIO14_Msk (0x4000UL)               /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
33838 #define GPIO_MCUN0INT0STAT_MCUN0GPIO13_Pos (13UL)                   /*!< MCUN0GPIO13 (Bit 13)                                  */
33839 #define GPIO_MCUN0INT0STAT_MCUN0GPIO13_Msk (0x2000UL)               /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
33840 #define GPIO_MCUN0INT0STAT_MCUN0GPIO12_Pos (12UL)                   /*!< MCUN0GPIO12 (Bit 12)                                  */
33841 #define GPIO_MCUN0INT0STAT_MCUN0GPIO12_Msk (0x1000UL)               /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
33842 #define GPIO_MCUN0INT0STAT_MCUN0GPIO11_Pos (11UL)                   /*!< MCUN0GPIO11 (Bit 11)                                  */
33843 #define GPIO_MCUN0INT0STAT_MCUN0GPIO11_Msk (0x800UL)                /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
33844 #define GPIO_MCUN0INT0STAT_MCUN0GPIO10_Pos (10UL)                   /*!< MCUN0GPIO10 (Bit 10)                                  */
33845 #define GPIO_MCUN0INT0STAT_MCUN0GPIO10_Msk (0x400UL)                /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
33846 #define GPIO_MCUN0INT0STAT_MCUN0GPIO9_Pos (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
33847 #define GPIO_MCUN0INT0STAT_MCUN0GPIO9_Msk (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
33848 #define GPIO_MCUN0INT0STAT_MCUN0GPIO8_Pos (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
33849 #define GPIO_MCUN0INT0STAT_MCUN0GPIO8_Msk (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
33850 #define GPIO_MCUN0INT0STAT_MCUN0GPIO7_Pos (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
33851 #define GPIO_MCUN0INT0STAT_MCUN0GPIO7_Msk (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
33852 #define GPIO_MCUN0INT0STAT_MCUN0GPIO6_Pos (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
33853 #define GPIO_MCUN0INT0STAT_MCUN0GPIO6_Msk (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
33854 #define GPIO_MCUN0INT0STAT_MCUN0GPIO5_Pos (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
33855 #define GPIO_MCUN0INT0STAT_MCUN0GPIO5_Msk (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
33856 #define GPIO_MCUN0INT0STAT_MCUN0GPIO4_Pos (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
33857 #define GPIO_MCUN0INT0STAT_MCUN0GPIO4_Msk (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
33858 #define GPIO_MCUN0INT0STAT_MCUN0GPIO3_Pos (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
33859 #define GPIO_MCUN0INT0STAT_MCUN0GPIO3_Msk (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
33860 #define GPIO_MCUN0INT0STAT_MCUN0GPIO2_Pos (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
33861 #define GPIO_MCUN0INT0STAT_MCUN0GPIO2_Msk (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
33862 #define GPIO_MCUN0INT0STAT_MCUN0GPIO1_Pos (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
33863 #define GPIO_MCUN0INT0STAT_MCUN0GPIO1_Msk (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
33864 #define GPIO_MCUN0INT0STAT_MCUN0GPIO0_Pos (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
33865 #define GPIO_MCUN0INT0STAT_MCUN0GPIO0_Msk (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
33866 /* =====================================================  MCUN0INT0CLR  ====================================================== */
33867 #define GPIO_MCUN0INT0CLR_MCUN0GPIO31_Pos (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
33868 #define GPIO_MCUN0INT0CLR_MCUN0GPIO31_Msk (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
33869 #define GPIO_MCUN0INT0CLR_MCUN0GPIO30_Pos (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
33870 #define GPIO_MCUN0INT0CLR_MCUN0GPIO30_Msk (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
33871 #define GPIO_MCUN0INT0CLR_MCUN0GPIO29_Pos (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
33872 #define GPIO_MCUN0INT0CLR_MCUN0GPIO29_Msk (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
33873 #define GPIO_MCUN0INT0CLR_MCUN0GPIO28_Pos (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
33874 #define GPIO_MCUN0INT0CLR_MCUN0GPIO28_Msk (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
33875 #define GPIO_MCUN0INT0CLR_MCUN0GPIO27_Pos (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
33876 #define GPIO_MCUN0INT0CLR_MCUN0GPIO27_Msk (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
33877 #define GPIO_MCUN0INT0CLR_MCUN0GPIO26_Pos (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
33878 #define GPIO_MCUN0INT0CLR_MCUN0GPIO26_Msk (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
33879 #define GPIO_MCUN0INT0CLR_MCUN0GPIO25_Pos (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
33880 #define GPIO_MCUN0INT0CLR_MCUN0GPIO25_Msk (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
33881 #define GPIO_MCUN0INT0CLR_MCUN0GPIO24_Pos (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
33882 #define GPIO_MCUN0INT0CLR_MCUN0GPIO24_Msk (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
33883 #define GPIO_MCUN0INT0CLR_MCUN0GPIO23_Pos (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
33884 #define GPIO_MCUN0INT0CLR_MCUN0GPIO23_Msk (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
33885 #define GPIO_MCUN0INT0CLR_MCUN0GPIO22_Pos (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
33886 #define GPIO_MCUN0INT0CLR_MCUN0GPIO22_Msk (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
33887 #define GPIO_MCUN0INT0CLR_MCUN0GPIO21_Pos (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
33888 #define GPIO_MCUN0INT0CLR_MCUN0GPIO21_Msk (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
33889 #define GPIO_MCUN0INT0CLR_MCUN0GPIO20_Pos (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
33890 #define GPIO_MCUN0INT0CLR_MCUN0GPIO20_Msk (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
33891 #define GPIO_MCUN0INT0CLR_MCUN0GPIO19_Pos (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
33892 #define GPIO_MCUN0INT0CLR_MCUN0GPIO19_Msk (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
33893 #define GPIO_MCUN0INT0CLR_MCUN0GPIO18_Pos (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
33894 #define GPIO_MCUN0INT0CLR_MCUN0GPIO18_Msk (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
33895 #define GPIO_MCUN0INT0CLR_MCUN0GPIO17_Pos (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
33896 #define GPIO_MCUN0INT0CLR_MCUN0GPIO17_Msk (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
33897 #define GPIO_MCUN0INT0CLR_MCUN0GPIO16_Pos (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
33898 #define GPIO_MCUN0INT0CLR_MCUN0GPIO16_Msk (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
33899 #define GPIO_MCUN0INT0CLR_MCUN0GPIO15_Pos (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
33900 #define GPIO_MCUN0INT0CLR_MCUN0GPIO15_Msk (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
33901 #define GPIO_MCUN0INT0CLR_MCUN0GPIO14_Pos (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
33902 #define GPIO_MCUN0INT0CLR_MCUN0GPIO14_Msk (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
33903 #define GPIO_MCUN0INT0CLR_MCUN0GPIO13_Pos (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
33904 #define GPIO_MCUN0INT0CLR_MCUN0GPIO13_Msk (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
33905 #define GPIO_MCUN0INT0CLR_MCUN0GPIO12_Pos (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
33906 #define GPIO_MCUN0INT0CLR_MCUN0GPIO12_Msk (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
33907 #define GPIO_MCUN0INT0CLR_MCUN0GPIO11_Pos (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
33908 #define GPIO_MCUN0INT0CLR_MCUN0GPIO11_Msk (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
33909 #define GPIO_MCUN0INT0CLR_MCUN0GPIO10_Pos (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
33910 #define GPIO_MCUN0INT0CLR_MCUN0GPIO10_Msk (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
33911 #define GPIO_MCUN0INT0CLR_MCUN0GPIO9_Pos  (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
33912 #define GPIO_MCUN0INT0CLR_MCUN0GPIO9_Msk  (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
33913 #define GPIO_MCUN0INT0CLR_MCUN0GPIO8_Pos  (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
33914 #define GPIO_MCUN0INT0CLR_MCUN0GPIO8_Msk  (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
33915 #define GPIO_MCUN0INT0CLR_MCUN0GPIO7_Pos  (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
33916 #define GPIO_MCUN0INT0CLR_MCUN0GPIO7_Msk  (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
33917 #define GPIO_MCUN0INT0CLR_MCUN0GPIO6_Pos  (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
33918 #define GPIO_MCUN0INT0CLR_MCUN0GPIO6_Msk  (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
33919 #define GPIO_MCUN0INT0CLR_MCUN0GPIO5_Pos  (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
33920 #define GPIO_MCUN0INT0CLR_MCUN0GPIO5_Msk  (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
33921 #define GPIO_MCUN0INT0CLR_MCUN0GPIO4_Pos  (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
33922 #define GPIO_MCUN0INT0CLR_MCUN0GPIO4_Msk  (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
33923 #define GPIO_MCUN0INT0CLR_MCUN0GPIO3_Pos  (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
33924 #define GPIO_MCUN0INT0CLR_MCUN0GPIO3_Msk  (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
33925 #define GPIO_MCUN0INT0CLR_MCUN0GPIO2_Pos  (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
33926 #define GPIO_MCUN0INT0CLR_MCUN0GPIO2_Msk  (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
33927 #define GPIO_MCUN0INT0CLR_MCUN0GPIO1_Pos  (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
33928 #define GPIO_MCUN0INT0CLR_MCUN0GPIO1_Msk  (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
33929 #define GPIO_MCUN0INT0CLR_MCUN0GPIO0_Pos  (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
33930 #define GPIO_MCUN0INT0CLR_MCUN0GPIO0_Msk  (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
33931 /* =====================================================  MCUN0INT0SET  ====================================================== */
33932 #define GPIO_MCUN0INT0SET_MCUN0GPIO31_Pos (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
33933 #define GPIO_MCUN0INT0SET_MCUN0GPIO31_Msk (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
33934 #define GPIO_MCUN0INT0SET_MCUN0GPIO30_Pos (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
33935 #define GPIO_MCUN0INT0SET_MCUN0GPIO30_Msk (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
33936 #define GPIO_MCUN0INT0SET_MCUN0GPIO29_Pos (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
33937 #define GPIO_MCUN0INT0SET_MCUN0GPIO29_Msk (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
33938 #define GPIO_MCUN0INT0SET_MCUN0GPIO28_Pos (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
33939 #define GPIO_MCUN0INT0SET_MCUN0GPIO28_Msk (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
33940 #define GPIO_MCUN0INT0SET_MCUN0GPIO27_Pos (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
33941 #define GPIO_MCUN0INT0SET_MCUN0GPIO27_Msk (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
33942 #define GPIO_MCUN0INT0SET_MCUN0GPIO26_Pos (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
33943 #define GPIO_MCUN0INT0SET_MCUN0GPIO26_Msk (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
33944 #define GPIO_MCUN0INT0SET_MCUN0GPIO25_Pos (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
33945 #define GPIO_MCUN0INT0SET_MCUN0GPIO25_Msk (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
33946 #define GPIO_MCUN0INT0SET_MCUN0GPIO24_Pos (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
33947 #define GPIO_MCUN0INT0SET_MCUN0GPIO24_Msk (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
33948 #define GPIO_MCUN0INT0SET_MCUN0GPIO23_Pos (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
33949 #define GPIO_MCUN0INT0SET_MCUN0GPIO23_Msk (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
33950 #define GPIO_MCUN0INT0SET_MCUN0GPIO22_Pos (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
33951 #define GPIO_MCUN0INT0SET_MCUN0GPIO22_Msk (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
33952 #define GPIO_MCUN0INT0SET_MCUN0GPIO21_Pos (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
33953 #define GPIO_MCUN0INT0SET_MCUN0GPIO21_Msk (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
33954 #define GPIO_MCUN0INT0SET_MCUN0GPIO20_Pos (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
33955 #define GPIO_MCUN0INT0SET_MCUN0GPIO20_Msk (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
33956 #define GPIO_MCUN0INT0SET_MCUN0GPIO19_Pos (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
33957 #define GPIO_MCUN0INT0SET_MCUN0GPIO19_Msk (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
33958 #define GPIO_MCUN0INT0SET_MCUN0GPIO18_Pos (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
33959 #define GPIO_MCUN0INT0SET_MCUN0GPIO18_Msk (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
33960 #define GPIO_MCUN0INT0SET_MCUN0GPIO17_Pos (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
33961 #define GPIO_MCUN0INT0SET_MCUN0GPIO17_Msk (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
33962 #define GPIO_MCUN0INT0SET_MCUN0GPIO16_Pos (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
33963 #define GPIO_MCUN0INT0SET_MCUN0GPIO16_Msk (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
33964 #define GPIO_MCUN0INT0SET_MCUN0GPIO15_Pos (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
33965 #define GPIO_MCUN0INT0SET_MCUN0GPIO15_Msk (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
33966 #define GPIO_MCUN0INT0SET_MCUN0GPIO14_Pos (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
33967 #define GPIO_MCUN0INT0SET_MCUN0GPIO14_Msk (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
33968 #define GPIO_MCUN0INT0SET_MCUN0GPIO13_Pos (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
33969 #define GPIO_MCUN0INT0SET_MCUN0GPIO13_Msk (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
33970 #define GPIO_MCUN0INT0SET_MCUN0GPIO12_Pos (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
33971 #define GPIO_MCUN0INT0SET_MCUN0GPIO12_Msk (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
33972 #define GPIO_MCUN0INT0SET_MCUN0GPIO11_Pos (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
33973 #define GPIO_MCUN0INT0SET_MCUN0GPIO11_Msk (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
33974 #define GPIO_MCUN0INT0SET_MCUN0GPIO10_Pos (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
33975 #define GPIO_MCUN0INT0SET_MCUN0GPIO10_Msk (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
33976 #define GPIO_MCUN0INT0SET_MCUN0GPIO9_Pos  (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
33977 #define GPIO_MCUN0INT0SET_MCUN0GPIO9_Msk  (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
33978 #define GPIO_MCUN0INT0SET_MCUN0GPIO8_Pos  (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
33979 #define GPIO_MCUN0INT0SET_MCUN0GPIO8_Msk  (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
33980 #define GPIO_MCUN0INT0SET_MCUN0GPIO7_Pos  (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
33981 #define GPIO_MCUN0INT0SET_MCUN0GPIO7_Msk  (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
33982 #define GPIO_MCUN0INT0SET_MCUN0GPIO6_Pos  (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
33983 #define GPIO_MCUN0INT0SET_MCUN0GPIO6_Msk  (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
33984 #define GPIO_MCUN0INT0SET_MCUN0GPIO5_Pos  (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
33985 #define GPIO_MCUN0INT0SET_MCUN0GPIO5_Msk  (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
33986 #define GPIO_MCUN0INT0SET_MCUN0GPIO4_Pos  (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
33987 #define GPIO_MCUN0INT0SET_MCUN0GPIO4_Msk  (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
33988 #define GPIO_MCUN0INT0SET_MCUN0GPIO3_Pos  (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
33989 #define GPIO_MCUN0INT0SET_MCUN0GPIO3_Msk  (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
33990 #define GPIO_MCUN0INT0SET_MCUN0GPIO2_Pos  (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
33991 #define GPIO_MCUN0INT0SET_MCUN0GPIO2_Msk  (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
33992 #define GPIO_MCUN0INT0SET_MCUN0GPIO1_Pos  (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
33993 #define GPIO_MCUN0INT0SET_MCUN0GPIO1_Msk  (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
33994 #define GPIO_MCUN0INT0SET_MCUN0GPIO0_Pos  (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
33995 #define GPIO_MCUN0INT0SET_MCUN0GPIO0_Msk  (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
33996 /* ======================================================  MCUN0INT1EN  ====================================================== */
33997 #define GPIO_MCUN0INT1EN_MCUN0GPIO63_Pos  (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
33998 #define GPIO_MCUN0INT1EN_MCUN0GPIO63_Msk  (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
33999 #define GPIO_MCUN0INT1EN_MCUN0GPIO62_Pos  (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
34000 #define GPIO_MCUN0INT1EN_MCUN0GPIO62_Msk  (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34001 #define GPIO_MCUN0INT1EN_MCUN0GPIO61_Pos  (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
34002 #define GPIO_MCUN0INT1EN_MCUN0GPIO61_Msk  (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34003 #define GPIO_MCUN0INT1EN_MCUN0GPIO60_Pos  (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
34004 #define GPIO_MCUN0INT1EN_MCUN0GPIO60_Msk  (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34005 #define GPIO_MCUN0INT1EN_MCUN0GPIO59_Pos  (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
34006 #define GPIO_MCUN0INT1EN_MCUN0GPIO59_Msk  (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34007 #define GPIO_MCUN0INT1EN_MCUN0GPIO58_Pos  (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
34008 #define GPIO_MCUN0INT1EN_MCUN0GPIO58_Msk  (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34009 #define GPIO_MCUN0INT1EN_MCUN0GPIO57_Pos  (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
34010 #define GPIO_MCUN0INT1EN_MCUN0GPIO57_Msk  (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34011 #define GPIO_MCUN0INT1EN_MCUN0GPIO56_Pos  (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
34012 #define GPIO_MCUN0INT1EN_MCUN0GPIO56_Msk  (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34013 #define GPIO_MCUN0INT1EN_MCUN0GPIO55_Pos  (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
34014 #define GPIO_MCUN0INT1EN_MCUN0GPIO55_Msk  (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34015 #define GPIO_MCUN0INT1EN_MCUN0GPIO54_Pos  (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
34016 #define GPIO_MCUN0INT1EN_MCUN0GPIO54_Msk  (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34017 #define GPIO_MCUN0INT1EN_MCUN0GPIO53_Pos  (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
34018 #define GPIO_MCUN0INT1EN_MCUN0GPIO53_Msk  (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34019 #define GPIO_MCUN0INT1EN_MCUN0GPIO52_Pos  (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
34020 #define GPIO_MCUN0INT1EN_MCUN0GPIO52_Msk  (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34021 #define GPIO_MCUN0INT1EN_MCUN0GPIO51_Pos  (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
34022 #define GPIO_MCUN0INT1EN_MCUN0GPIO51_Msk  (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34023 #define GPIO_MCUN0INT1EN_MCUN0GPIO50_Pos  (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
34024 #define GPIO_MCUN0INT1EN_MCUN0GPIO50_Msk  (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34025 #define GPIO_MCUN0INT1EN_MCUN0GPIO49_Pos  (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
34026 #define GPIO_MCUN0INT1EN_MCUN0GPIO49_Msk  (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34027 #define GPIO_MCUN0INT1EN_MCUN0GPIO48_Pos  (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
34028 #define GPIO_MCUN0INT1EN_MCUN0GPIO48_Msk  (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34029 #define GPIO_MCUN0INT1EN_MCUN0GPIO47_Pos  (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
34030 #define GPIO_MCUN0INT1EN_MCUN0GPIO47_Msk  (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34031 #define GPIO_MCUN0INT1EN_MCUN0GPIO46_Pos  (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
34032 #define GPIO_MCUN0INT1EN_MCUN0GPIO46_Msk  (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34033 #define GPIO_MCUN0INT1EN_MCUN0GPIO45_Pos  (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
34034 #define GPIO_MCUN0INT1EN_MCUN0GPIO45_Msk  (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34035 #define GPIO_MCUN0INT1EN_MCUN0GPIO44_Pos  (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
34036 #define GPIO_MCUN0INT1EN_MCUN0GPIO44_Msk  (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34037 #define GPIO_MCUN0INT1EN_MCUN0GPIO43_Pos  (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
34038 #define GPIO_MCUN0INT1EN_MCUN0GPIO43_Msk  (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34039 #define GPIO_MCUN0INT1EN_MCUN0GPIO42_Pos  (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
34040 #define GPIO_MCUN0INT1EN_MCUN0GPIO42_Msk  (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34041 #define GPIO_MCUN0INT1EN_MCUN0GPIO41_Pos  (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
34042 #define GPIO_MCUN0INT1EN_MCUN0GPIO41_Msk  (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34043 #define GPIO_MCUN0INT1EN_MCUN0GPIO40_Pos  (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
34044 #define GPIO_MCUN0INT1EN_MCUN0GPIO40_Msk  (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34045 #define GPIO_MCUN0INT1EN_MCUN0GPIO39_Pos  (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
34046 #define GPIO_MCUN0INT1EN_MCUN0GPIO39_Msk  (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34047 #define GPIO_MCUN0INT1EN_MCUN0GPIO38_Pos  (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
34048 #define GPIO_MCUN0INT1EN_MCUN0GPIO38_Msk  (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34049 #define GPIO_MCUN0INT1EN_MCUN0GPIO37_Pos  (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
34050 #define GPIO_MCUN0INT1EN_MCUN0GPIO37_Msk  (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34051 #define GPIO_MCUN0INT1EN_MCUN0GPIO36_Pos  (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
34052 #define GPIO_MCUN0INT1EN_MCUN0GPIO36_Msk  (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34053 #define GPIO_MCUN0INT1EN_MCUN0GPIO35_Pos  (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
34054 #define GPIO_MCUN0INT1EN_MCUN0GPIO35_Msk  (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34055 #define GPIO_MCUN0INT1EN_MCUN0GPIO34_Pos  (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
34056 #define GPIO_MCUN0INT1EN_MCUN0GPIO34_Msk  (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34057 #define GPIO_MCUN0INT1EN_MCUN0GPIO33_Pos  (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
34058 #define GPIO_MCUN0INT1EN_MCUN0GPIO33_Msk  (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34059 #define GPIO_MCUN0INT1EN_MCUN0GPIO32_Pos  (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
34060 #define GPIO_MCUN0INT1EN_MCUN0GPIO32_Msk  (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34061 /* =====================================================  MCUN0INT1STAT  ===================================================== */
34062 #define GPIO_MCUN0INT1STAT_MCUN0GPIO63_Pos (31UL)                   /*!< MCUN0GPIO63 (Bit 31)                                  */
34063 #define GPIO_MCUN0INT1STAT_MCUN0GPIO63_Msk (0x80000000UL)           /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
34064 #define GPIO_MCUN0INT1STAT_MCUN0GPIO62_Pos (30UL)                   /*!< MCUN0GPIO62 (Bit 30)                                  */
34065 #define GPIO_MCUN0INT1STAT_MCUN0GPIO62_Msk (0x40000000UL)           /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34066 #define GPIO_MCUN0INT1STAT_MCUN0GPIO61_Pos (29UL)                   /*!< MCUN0GPIO61 (Bit 29)                                  */
34067 #define GPIO_MCUN0INT1STAT_MCUN0GPIO61_Msk (0x20000000UL)           /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34068 #define GPIO_MCUN0INT1STAT_MCUN0GPIO60_Pos (28UL)                   /*!< MCUN0GPIO60 (Bit 28)                                  */
34069 #define GPIO_MCUN0INT1STAT_MCUN0GPIO60_Msk (0x10000000UL)           /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34070 #define GPIO_MCUN0INT1STAT_MCUN0GPIO59_Pos (27UL)                   /*!< MCUN0GPIO59 (Bit 27)                                  */
34071 #define GPIO_MCUN0INT1STAT_MCUN0GPIO59_Msk (0x8000000UL)            /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34072 #define GPIO_MCUN0INT1STAT_MCUN0GPIO58_Pos (26UL)                   /*!< MCUN0GPIO58 (Bit 26)                                  */
34073 #define GPIO_MCUN0INT1STAT_MCUN0GPIO58_Msk (0x4000000UL)            /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34074 #define GPIO_MCUN0INT1STAT_MCUN0GPIO57_Pos (25UL)                   /*!< MCUN0GPIO57 (Bit 25)                                  */
34075 #define GPIO_MCUN0INT1STAT_MCUN0GPIO57_Msk (0x2000000UL)            /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34076 #define GPIO_MCUN0INT1STAT_MCUN0GPIO56_Pos (24UL)                   /*!< MCUN0GPIO56 (Bit 24)                                  */
34077 #define GPIO_MCUN0INT1STAT_MCUN0GPIO56_Msk (0x1000000UL)            /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34078 #define GPIO_MCUN0INT1STAT_MCUN0GPIO55_Pos (23UL)                   /*!< MCUN0GPIO55 (Bit 23)                                  */
34079 #define GPIO_MCUN0INT1STAT_MCUN0GPIO55_Msk (0x800000UL)             /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34080 #define GPIO_MCUN0INT1STAT_MCUN0GPIO54_Pos (22UL)                   /*!< MCUN0GPIO54 (Bit 22)                                  */
34081 #define GPIO_MCUN0INT1STAT_MCUN0GPIO54_Msk (0x400000UL)             /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34082 #define GPIO_MCUN0INT1STAT_MCUN0GPIO53_Pos (21UL)                   /*!< MCUN0GPIO53 (Bit 21)                                  */
34083 #define GPIO_MCUN0INT1STAT_MCUN0GPIO53_Msk (0x200000UL)             /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34084 #define GPIO_MCUN0INT1STAT_MCUN0GPIO52_Pos (20UL)                   /*!< MCUN0GPIO52 (Bit 20)                                  */
34085 #define GPIO_MCUN0INT1STAT_MCUN0GPIO52_Msk (0x100000UL)             /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34086 #define GPIO_MCUN0INT1STAT_MCUN0GPIO51_Pos (19UL)                   /*!< MCUN0GPIO51 (Bit 19)                                  */
34087 #define GPIO_MCUN0INT1STAT_MCUN0GPIO51_Msk (0x80000UL)              /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34088 #define GPIO_MCUN0INT1STAT_MCUN0GPIO50_Pos (18UL)                   /*!< MCUN0GPIO50 (Bit 18)                                  */
34089 #define GPIO_MCUN0INT1STAT_MCUN0GPIO50_Msk (0x40000UL)              /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34090 #define GPIO_MCUN0INT1STAT_MCUN0GPIO49_Pos (17UL)                   /*!< MCUN0GPIO49 (Bit 17)                                  */
34091 #define GPIO_MCUN0INT1STAT_MCUN0GPIO49_Msk (0x20000UL)              /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34092 #define GPIO_MCUN0INT1STAT_MCUN0GPIO48_Pos (16UL)                   /*!< MCUN0GPIO48 (Bit 16)                                  */
34093 #define GPIO_MCUN0INT1STAT_MCUN0GPIO48_Msk (0x10000UL)              /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34094 #define GPIO_MCUN0INT1STAT_MCUN0GPIO47_Pos (15UL)                   /*!< MCUN0GPIO47 (Bit 15)                                  */
34095 #define GPIO_MCUN0INT1STAT_MCUN0GPIO47_Msk (0x8000UL)               /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34096 #define GPIO_MCUN0INT1STAT_MCUN0GPIO46_Pos (14UL)                   /*!< MCUN0GPIO46 (Bit 14)                                  */
34097 #define GPIO_MCUN0INT1STAT_MCUN0GPIO46_Msk (0x4000UL)               /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34098 #define GPIO_MCUN0INT1STAT_MCUN0GPIO45_Pos (13UL)                   /*!< MCUN0GPIO45 (Bit 13)                                  */
34099 #define GPIO_MCUN0INT1STAT_MCUN0GPIO45_Msk (0x2000UL)               /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34100 #define GPIO_MCUN0INT1STAT_MCUN0GPIO44_Pos (12UL)                   /*!< MCUN0GPIO44 (Bit 12)                                  */
34101 #define GPIO_MCUN0INT1STAT_MCUN0GPIO44_Msk (0x1000UL)               /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34102 #define GPIO_MCUN0INT1STAT_MCUN0GPIO43_Pos (11UL)                   /*!< MCUN0GPIO43 (Bit 11)                                  */
34103 #define GPIO_MCUN0INT1STAT_MCUN0GPIO43_Msk (0x800UL)                /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34104 #define GPIO_MCUN0INT1STAT_MCUN0GPIO42_Pos (10UL)                   /*!< MCUN0GPIO42 (Bit 10)                                  */
34105 #define GPIO_MCUN0INT1STAT_MCUN0GPIO42_Msk (0x400UL)                /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34106 #define GPIO_MCUN0INT1STAT_MCUN0GPIO41_Pos (9UL)                    /*!< MCUN0GPIO41 (Bit 9)                                   */
34107 #define GPIO_MCUN0INT1STAT_MCUN0GPIO41_Msk (0x200UL)                /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34108 #define GPIO_MCUN0INT1STAT_MCUN0GPIO40_Pos (8UL)                    /*!< MCUN0GPIO40 (Bit 8)                                   */
34109 #define GPIO_MCUN0INT1STAT_MCUN0GPIO40_Msk (0x100UL)                /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34110 #define GPIO_MCUN0INT1STAT_MCUN0GPIO39_Pos (7UL)                    /*!< MCUN0GPIO39 (Bit 7)                                   */
34111 #define GPIO_MCUN0INT1STAT_MCUN0GPIO39_Msk (0x80UL)                 /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34112 #define GPIO_MCUN0INT1STAT_MCUN0GPIO38_Pos (6UL)                    /*!< MCUN0GPIO38 (Bit 6)                                   */
34113 #define GPIO_MCUN0INT1STAT_MCUN0GPIO38_Msk (0x40UL)                 /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34114 #define GPIO_MCUN0INT1STAT_MCUN0GPIO37_Pos (5UL)                    /*!< MCUN0GPIO37 (Bit 5)                                   */
34115 #define GPIO_MCUN0INT1STAT_MCUN0GPIO37_Msk (0x20UL)                 /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34116 #define GPIO_MCUN0INT1STAT_MCUN0GPIO36_Pos (4UL)                    /*!< MCUN0GPIO36 (Bit 4)                                   */
34117 #define GPIO_MCUN0INT1STAT_MCUN0GPIO36_Msk (0x10UL)                 /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34118 #define GPIO_MCUN0INT1STAT_MCUN0GPIO35_Pos (3UL)                    /*!< MCUN0GPIO35 (Bit 3)                                   */
34119 #define GPIO_MCUN0INT1STAT_MCUN0GPIO35_Msk (0x8UL)                  /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34120 #define GPIO_MCUN0INT1STAT_MCUN0GPIO34_Pos (2UL)                    /*!< MCUN0GPIO34 (Bit 2)                                   */
34121 #define GPIO_MCUN0INT1STAT_MCUN0GPIO34_Msk (0x4UL)                  /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34122 #define GPIO_MCUN0INT1STAT_MCUN0GPIO33_Pos (1UL)                    /*!< MCUN0GPIO33 (Bit 1)                                   */
34123 #define GPIO_MCUN0INT1STAT_MCUN0GPIO33_Msk (0x2UL)                  /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34124 #define GPIO_MCUN0INT1STAT_MCUN0GPIO32_Pos (0UL)                    /*!< MCUN0GPIO32 (Bit 0)                                   */
34125 #define GPIO_MCUN0INT1STAT_MCUN0GPIO32_Msk (0x1UL)                  /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34126 /* =====================================================  MCUN0INT1CLR  ====================================================== */
34127 #define GPIO_MCUN0INT1CLR_MCUN0GPIO63_Pos (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
34128 #define GPIO_MCUN0INT1CLR_MCUN0GPIO63_Msk (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
34129 #define GPIO_MCUN0INT1CLR_MCUN0GPIO62_Pos (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
34130 #define GPIO_MCUN0INT1CLR_MCUN0GPIO62_Msk (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34131 #define GPIO_MCUN0INT1CLR_MCUN0GPIO61_Pos (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
34132 #define GPIO_MCUN0INT1CLR_MCUN0GPIO61_Msk (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34133 #define GPIO_MCUN0INT1CLR_MCUN0GPIO60_Pos (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
34134 #define GPIO_MCUN0INT1CLR_MCUN0GPIO60_Msk (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34135 #define GPIO_MCUN0INT1CLR_MCUN0GPIO59_Pos (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
34136 #define GPIO_MCUN0INT1CLR_MCUN0GPIO59_Msk (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34137 #define GPIO_MCUN0INT1CLR_MCUN0GPIO58_Pos (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
34138 #define GPIO_MCUN0INT1CLR_MCUN0GPIO58_Msk (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34139 #define GPIO_MCUN0INT1CLR_MCUN0GPIO57_Pos (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
34140 #define GPIO_MCUN0INT1CLR_MCUN0GPIO57_Msk (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34141 #define GPIO_MCUN0INT1CLR_MCUN0GPIO56_Pos (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
34142 #define GPIO_MCUN0INT1CLR_MCUN0GPIO56_Msk (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34143 #define GPIO_MCUN0INT1CLR_MCUN0GPIO55_Pos (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
34144 #define GPIO_MCUN0INT1CLR_MCUN0GPIO55_Msk (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34145 #define GPIO_MCUN0INT1CLR_MCUN0GPIO54_Pos (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
34146 #define GPIO_MCUN0INT1CLR_MCUN0GPIO54_Msk (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34147 #define GPIO_MCUN0INT1CLR_MCUN0GPIO53_Pos (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
34148 #define GPIO_MCUN0INT1CLR_MCUN0GPIO53_Msk (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34149 #define GPIO_MCUN0INT1CLR_MCUN0GPIO52_Pos (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
34150 #define GPIO_MCUN0INT1CLR_MCUN0GPIO52_Msk (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34151 #define GPIO_MCUN0INT1CLR_MCUN0GPIO51_Pos (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
34152 #define GPIO_MCUN0INT1CLR_MCUN0GPIO51_Msk (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34153 #define GPIO_MCUN0INT1CLR_MCUN0GPIO50_Pos (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
34154 #define GPIO_MCUN0INT1CLR_MCUN0GPIO50_Msk (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34155 #define GPIO_MCUN0INT1CLR_MCUN0GPIO49_Pos (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
34156 #define GPIO_MCUN0INT1CLR_MCUN0GPIO49_Msk (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34157 #define GPIO_MCUN0INT1CLR_MCUN0GPIO48_Pos (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
34158 #define GPIO_MCUN0INT1CLR_MCUN0GPIO48_Msk (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34159 #define GPIO_MCUN0INT1CLR_MCUN0GPIO47_Pos (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
34160 #define GPIO_MCUN0INT1CLR_MCUN0GPIO47_Msk (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34161 #define GPIO_MCUN0INT1CLR_MCUN0GPIO46_Pos (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
34162 #define GPIO_MCUN0INT1CLR_MCUN0GPIO46_Msk (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34163 #define GPIO_MCUN0INT1CLR_MCUN0GPIO45_Pos (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
34164 #define GPIO_MCUN0INT1CLR_MCUN0GPIO45_Msk (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34165 #define GPIO_MCUN0INT1CLR_MCUN0GPIO44_Pos (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
34166 #define GPIO_MCUN0INT1CLR_MCUN0GPIO44_Msk (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34167 #define GPIO_MCUN0INT1CLR_MCUN0GPIO43_Pos (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
34168 #define GPIO_MCUN0INT1CLR_MCUN0GPIO43_Msk (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34169 #define GPIO_MCUN0INT1CLR_MCUN0GPIO42_Pos (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
34170 #define GPIO_MCUN0INT1CLR_MCUN0GPIO42_Msk (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34171 #define GPIO_MCUN0INT1CLR_MCUN0GPIO41_Pos (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
34172 #define GPIO_MCUN0INT1CLR_MCUN0GPIO41_Msk (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34173 #define GPIO_MCUN0INT1CLR_MCUN0GPIO40_Pos (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
34174 #define GPIO_MCUN0INT1CLR_MCUN0GPIO40_Msk (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34175 #define GPIO_MCUN0INT1CLR_MCUN0GPIO39_Pos (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
34176 #define GPIO_MCUN0INT1CLR_MCUN0GPIO39_Msk (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34177 #define GPIO_MCUN0INT1CLR_MCUN0GPIO38_Pos (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
34178 #define GPIO_MCUN0INT1CLR_MCUN0GPIO38_Msk (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34179 #define GPIO_MCUN0INT1CLR_MCUN0GPIO37_Pos (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
34180 #define GPIO_MCUN0INT1CLR_MCUN0GPIO37_Msk (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34181 #define GPIO_MCUN0INT1CLR_MCUN0GPIO36_Pos (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
34182 #define GPIO_MCUN0INT1CLR_MCUN0GPIO36_Msk (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34183 #define GPIO_MCUN0INT1CLR_MCUN0GPIO35_Pos (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
34184 #define GPIO_MCUN0INT1CLR_MCUN0GPIO35_Msk (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34185 #define GPIO_MCUN0INT1CLR_MCUN0GPIO34_Pos (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
34186 #define GPIO_MCUN0INT1CLR_MCUN0GPIO34_Msk (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34187 #define GPIO_MCUN0INT1CLR_MCUN0GPIO33_Pos (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
34188 #define GPIO_MCUN0INT1CLR_MCUN0GPIO33_Msk (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34189 #define GPIO_MCUN0INT1CLR_MCUN0GPIO32_Pos (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
34190 #define GPIO_MCUN0INT1CLR_MCUN0GPIO32_Msk (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34191 /* =====================================================  MCUN0INT1SET  ====================================================== */
34192 #define GPIO_MCUN0INT1SET_MCUN0GPIO63_Pos (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
34193 #define GPIO_MCUN0INT1SET_MCUN0GPIO63_Msk (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
34194 #define GPIO_MCUN0INT1SET_MCUN0GPIO62_Pos (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
34195 #define GPIO_MCUN0INT1SET_MCUN0GPIO62_Msk (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34196 #define GPIO_MCUN0INT1SET_MCUN0GPIO61_Pos (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
34197 #define GPIO_MCUN0INT1SET_MCUN0GPIO61_Msk (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34198 #define GPIO_MCUN0INT1SET_MCUN0GPIO60_Pos (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
34199 #define GPIO_MCUN0INT1SET_MCUN0GPIO60_Msk (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34200 #define GPIO_MCUN0INT1SET_MCUN0GPIO59_Pos (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
34201 #define GPIO_MCUN0INT1SET_MCUN0GPIO59_Msk (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34202 #define GPIO_MCUN0INT1SET_MCUN0GPIO58_Pos (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
34203 #define GPIO_MCUN0INT1SET_MCUN0GPIO58_Msk (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34204 #define GPIO_MCUN0INT1SET_MCUN0GPIO57_Pos (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
34205 #define GPIO_MCUN0INT1SET_MCUN0GPIO57_Msk (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34206 #define GPIO_MCUN0INT1SET_MCUN0GPIO56_Pos (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
34207 #define GPIO_MCUN0INT1SET_MCUN0GPIO56_Msk (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34208 #define GPIO_MCUN0INT1SET_MCUN0GPIO55_Pos (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
34209 #define GPIO_MCUN0INT1SET_MCUN0GPIO55_Msk (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34210 #define GPIO_MCUN0INT1SET_MCUN0GPIO54_Pos (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
34211 #define GPIO_MCUN0INT1SET_MCUN0GPIO54_Msk (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34212 #define GPIO_MCUN0INT1SET_MCUN0GPIO53_Pos (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
34213 #define GPIO_MCUN0INT1SET_MCUN0GPIO53_Msk (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34214 #define GPIO_MCUN0INT1SET_MCUN0GPIO52_Pos (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
34215 #define GPIO_MCUN0INT1SET_MCUN0GPIO52_Msk (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34216 #define GPIO_MCUN0INT1SET_MCUN0GPIO51_Pos (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
34217 #define GPIO_MCUN0INT1SET_MCUN0GPIO51_Msk (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34218 #define GPIO_MCUN0INT1SET_MCUN0GPIO50_Pos (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
34219 #define GPIO_MCUN0INT1SET_MCUN0GPIO50_Msk (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34220 #define GPIO_MCUN0INT1SET_MCUN0GPIO49_Pos (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
34221 #define GPIO_MCUN0INT1SET_MCUN0GPIO49_Msk (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34222 #define GPIO_MCUN0INT1SET_MCUN0GPIO48_Pos (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
34223 #define GPIO_MCUN0INT1SET_MCUN0GPIO48_Msk (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34224 #define GPIO_MCUN0INT1SET_MCUN0GPIO47_Pos (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
34225 #define GPIO_MCUN0INT1SET_MCUN0GPIO47_Msk (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34226 #define GPIO_MCUN0INT1SET_MCUN0GPIO46_Pos (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
34227 #define GPIO_MCUN0INT1SET_MCUN0GPIO46_Msk (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34228 #define GPIO_MCUN0INT1SET_MCUN0GPIO45_Pos (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
34229 #define GPIO_MCUN0INT1SET_MCUN0GPIO45_Msk (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34230 #define GPIO_MCUN0INT1SET_MCUN0GPIO44_Pos (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
34231 #define GPIO_MCUN0INT1SET_MCUN0GPIO44_Msk (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34232 #define GPIO_MCUN0INT1SET_MCUN0GPIO43_Pos (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
34233 #define GPIO_MCUN0INT1SET_MCUN0GPIO43_Msk (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34234 #define GPIO_MCUN0INT1SET_MCUN0GPIO42_Pos (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
34235 #define GPIO_MCUN0INT1SET_MCUN0GPIO42_Msk (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34236 #define GPIO_MCUN0INT1SET_MCUN0GPIO41_Pos (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
34237 #define GPIO_MCUN0INT1SET_MCUN0GPIO41_Msk (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34238 #define GPIO_MCUN0INT1SET_MCUN0GPIO40_Pos (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
34239 #define GPIO_MCUN0INT1SET_MCUN0GPIO40_Msk (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34240 #define GPIO_MCUN0INT1SET_MCUN0GPIO39_Pos (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
34241 #define GPIO_MCUN0INT1SET_MCUN0GPIO39_Msk (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34242 #define GPIO_MCUN0INT1SET_MCUN0GPIO38_Pos (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
34243 #define GPIO_MCUN0INT1SET_MCUN0GPIO38_Msk (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34244 #define GPIO_MCUN0INT1SET_MCUN0GPIO37_Pos (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
34245 #define GPIO_MCUN0INT1SET_MCUN0GPIO37_Msk (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34246 #define GPIO_MCUN0INT1SET_MCUN0GPIO36_Pos (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
34247 #define GPIO_MCUN0INT1SET_MCUN0GPIO36_Msk (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34248 #define GPIO_MCUN0INT1SET_MCUN0GPIO35_Pos (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
34249 #define GPIO_MCUN0INT1SET_MCUN0GPIO35_Msk (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34250 #define GPIO_MCUN0INT1SET_MCUN0GPIO34_Pos (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
34251 #define GPIO_MCUN0INT1SET_MCUN0GPIO34_Msk (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34252 #define GPIO_MCUN0INT1SET_MCUN0GPIO33_Pos (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
34253 #define GPIO_MCUN0INT1SET_MCUN0GPIO33_Msk (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34254 #define GPIO_MCUN0INT1SET_MCUN0GPIO32_Pos (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
34255 #define GPIO_MCUN0INT1SET_MCUN0GPIO32_Msk (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34256 /* ======================================================  MCUN0INT2EN  ====================================================== */
34257 #define GPIO_MCUN0INT2EN_MCUN0GPIO95_Pos  (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
34258 #define GPIO_MCUN0INT2EN_MCUN0GPIO95_Msk  (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
34259 #define GPIO_MCUN0INT2EN_MCUN0GPIO94_Pos  (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
34260 #define GPIO_MCUN0INT2EN_MCUN0GPIO94_Msk  (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
34261 #define GPIO_MCUN0INT2EN_MCUN0GPIO93_Pos  (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
34262 #define GPIO_MCUN0INT2EN_MCUN0GPIO93_Msk  (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
34263 #define GPIO_MCUN0INT2EN_MCUN0GPIO92_Pos  (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
34264 #define GPIO_MCUN0INT2EN_MCUN0GPIO92_Msk  (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
34265 #define GPIO_MCUN0INT2EN_MCUN0GPIO91_Pos  (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
34266 #define GPIO_MCUN0INT2EN_MCUN0GPIO91_Msk  (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
34267 #define GPIO_MCUN0INT2EN_MCUN0GPIO90_Pos  (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
34268 #define GPIO_MCUN0INT2EN_MCUN0GPIO90_Msk  (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
34269 #define GPIO_MCUN0INT2EN_MCUN0GPIO89_Pos  (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
34270 #define GPIO_MCUN0INT2EN_MCUN0GPIO89_Msk  (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
34271 #define GPIO_MCUN0INT2EN_MCUN0GPIO88_Pos  (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
34272 #define GPIO_MCUN0INT2EN_MCUN0GPIO88_Msk  (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
34273 #define GPIO_MCUN0INT2EN_MCUN0GPIO87_Pos  (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
34274 #define GPIO_MCUN0INT2EN_MCUN0GPIO87_Msk  (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
34275 #define GPIO_MCUN0INT2EN_MCUN0GPIO86_Pos  (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
34276 #define GPIO_MCUN0INT2EN_MCUN0GPIO86_Msk  (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
34277 #define GPIO_MCUN0INT2EN_MCUN0GPIO85_Pos  (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
34278 #define GPIO_MCUN0INT2EN_MCUN0GPIO85_Msk  (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
34279 #define GPIO_MCUN0INT2EN_MCUN0GPIO84_Pos  (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
34280 #define GPIO_MCUN0INT2EN_MCUN0GPIO84_Msk  (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
34281 #define GPIO_MCUN0INT2EN_MCUN0GPIO83_Pos  (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
34282 #define GPIO_MCUN0INT2EN_MCUN0GPIO83_Msk  (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
34283 #define GPIO_MCUN0INT2EN_MCUN0GPIO82_Pos  (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
34284 #define GPIO_MCUN0INT2EN_MCUN0GPIO82_Msk  (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
34285 #define GPIO_MCUN0INT2EN_MCUN0GPIO81_Pos  (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
34286 #define GPIO_MCUN0INT2EN_MCUN0GPIO81_Msk  (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
34287 #define GPIO_MCUN0INT2EN_MCUN0GPIO80_Pos  (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
34288 #define GPIO_MCUN0INT2EN_MCUN0GPIO80_Msk  (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
34289 #define GPIO_MCUN0INT2EN_MCUN0GPIO79_Pos  (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
34290 #define GPIO_MCUN0INT2EN_MCUN0GPIO79_Msk  (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
34291 #define GPIO_MCUN0INT2EN_MCUN0GPIO78_Pos  (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
34292 #define GPIO_MCUN0INT2EN_MCUN0GPIO78_Msk  (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
34293 #define GPIO_MCUN0INT2EN_MCUN0GPIO77_Pos  (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
34294 #define GPIO_MCUN0INT2EN_MCUN0GPIO77_Msk  (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
34295 #define GPIO_MCUN0INT2EN_MCUN0GPIO76_Pos  (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
34296 #define GPIO_MCUN0INT2EN_MCUN0GPIO76_Msk  (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
34297 #define GPIO_MCUN0INT2EN_MCUN0GPIO75_Pos  (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
34298 #define GPIO_MCUN0INT2EN_MCUN0GPIO75_Msk  (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
34299 #define GPIO_MCUN0INT2EN_MCUN0GPIO74_Pos  (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
34300 #define GPIO_MCUN0INT2EN_MCUN0GPIO74_Msk  (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
34301 #define GPIO_MCUN0INT2EN_MCUN0GPIO73_Pos  (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
34302 #define GPIO_MCUN0INT2EN_MCUN0GPIO73_Msk  (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
34303 #define GPIO_MCUN0INT2EN_MCUN0GPIO72_Pos  (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
34304 #define GPIO_MCUN0INT2EN_MCUN0GPIO72_Msk  (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
34305 #define GPIO_MCUN0INT2EN_MCUN0GPIO71_Pos  (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
34306 #define GPIO_MCUN0INT2EN_MCUN0GPIO71_Msk  (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
34307 #define GPIO_MCUN0INT2EN_MCUN0GPIO70_Pos  (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
34308 #define GPIO_MCUN0INT2EN_MCUN0GPIO70_Msk  (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
34309 #define GPIO_MCUN0INT2EN_MCUN0GPIO69_Pos  (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
34310 #define GPIO_MCUN0INT2EN_MCUN0GPIO69_Msk  (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
34311 #define GPIO_MCUN0INT2EN_MCUN0GPIO68_Pos  (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
34312 #define GPIO_MCUN0INT2EN_MCUN0GPIO68_Msk  (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
34313 #define GPIO_MCUN0INT2EN_MCUN0GPIO67_Pos  (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
34314 #define GPIO_MCUN0INT2EN_MCUN0GPIO67_Msk  (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
34315 #define GPIO_MCUN0INT2EN_MCUN0GPIO66_Pos  (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
34316 #define GPIO_MCUN0INT2EN_MCUN0GPIO66_Msk  (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
34317 #define GPIO_MCUN0INT2EN_MCUN0GPIO65_Pos  (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
34318 #define GPIO_MCUN0INT2EN_MCUN0GPIO65_Msk  (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
34319 #define GPIO_MCUN0INT2EN_MCUN0GPIO64_Pos  (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
34320 #define GPIO_MCUN0INT2EN_MCUN0GPIO64_Msk  (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
34321 /* =====================================================  MCUN0INT2STAT  ===================================================== */
34322 #define GPIO_MCUN0INT2STAT_MCUN0GPIO95_Pos (31UL)                   /*!< MCUN0GPIO95 (Bit 31)                                  */
34323 #define GPIO_MCUN0INT2STAT_MCUN0GPIO95_Msk (0x80000000UL)           /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
34324 #define GPIO_MCUN0INT2STAT_MCUN0GPIO94_Pos (30UL)                   /*!< MCUN0GPIO94 (Bit 30)                                  */
34325 #define GPIO_MCUN0INT2STAT_MCUN0GPIO94_Msk (0x40000000UL)           /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
34326 #define GPIO_MCUN0INT2STAT_MCUN0GPIO93_Pos (29UL)                   /*!< MCUN0GPIO93 (Bit 29)                                  */
34327 #define GPIO_MCUN0INT2STAT_MCUN0GPIO93_Msk (0x20000000UL)           /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
34328 #define GPIO_MCUN0INT2STAT_MCUN0GPIO92_Pos (28UL)                   /*!< MCUN0GPIO92 (Bit 28)                                  */
34329 #define GPIO_MCUN0INT2STAT_MCUN0GPIO92_Msk (0x10000000UL)           /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
34330 #define GPIO_MCUN0INT2STAT_MCUN0GPIO91_Pos (27UL)                   /*!< MCUN0GPIO91 (Bit 27)                                  */
34331 #define GPIO_MCUN0INT2STAT_MCUN0GPIO91_Msk (0x8000000UL)            /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
34332 #define GPIO_MCUN0INT2STAT_MCUN0GPIO90_Pos (26UL)                   /*!< MCUN0GPIO90 (Bit 26)                                  */
34333 #define GPIO_MCUN0INT2STAT_MCUN0GPIO90_Msk (0x4000000UL)            /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
34334 #define GPIO_MCUN0INT2STAT_MCUN0GPIO89_Pos (25UL)                   /*!< MCUN0GPIO89 (Bit 25)                                  */
34335 #define GPIO_MCUN0INT2STAT_MCUN0GPIO89_Msk (0x2000000UL)            /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
34336 #define GPIO_MCUN0INT2STAT_MCUN0GPIO88_Pos (24UL)                   /*!< MCUN0GPIO88 (Bit 24)                                  */
34337 #define GPIO_MCUN0INT2STAT_MCUN0GPIO88_Msk (0x1000000UL)            /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
34338 #define GPIO_MCUN0INT2STAT_MCUN0GPIO87_Pos (23UL)                   /*!< MCUN0GPIO87 (Bit 23)                                  */
34339 #define GPIO_MCUN0INT2STAT_MCUN0GPIO87_Msk (0x800000UL)             /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
34340 #define GPIO_MCUN0INT2STAT_MCUN0GPIO86_Pos (22UL)                   /*!< MCUN0GPIO86 (Bit 22)                                  */
34341 #define GPIO_MCUN0INT2STAT_MCUN0GPIO86_Msk (0x400000UL)             /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
34342 #define GPIO_MCUN0INT2STAT_MCUN0GPIO85_Pos (21UL)                   /*!< MCUN0GPIO85 (Bit 21)                                  */
34343 #define GPIO_MCUN0INT2STAT_MCUN0GPIO85_Msk (0x200000UL)             /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
34344 #define GPIO_MCUN0INT2STAT_MCUN0GPIO84_Pos (20UL)                   /*!< MCUN0GPIO84 (Bit 20)                                  */
34345 #define GPIO_MCUN0INT2STAT_MCUN0GPIO84_Msk (0x100000UL)             /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
34346 #define GPIO_MCUN0INT2STAT_MCUN0GPIO83_Pos (19UL)                   /*!< MCUN0GPIO83 (Bit 19)                                  */
34347 #define GPIO_MCUN0INT2STAT_MCUN0GPIO83_Msk (0x80000UL)              /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
34348 #define GPIO_MCUN0INT2STAT_MCUN0GPIO82_Pos (18UL)                   /*!< MCUN0GPIO82 (Bit 18)                                  */
34349 #define GPIO_MCUN0INT2STAT_MCUN0GPIO82_Msk (0x40000UL)              /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
34350 #define GPIO_MCUN0INT2STAT_MCUN0GPIO81_Pos (17UL)                   /*!< MCUN0GPIO81 (Bit 17)                                  */
34351 #define GPIO_MCUN0INT2STAT_MCUN0GPIO81_Msk (0x20000UL)              /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
34352 #define GPIO_MCUN0INT2STAT_MCUN0GPIO80_Pos (16UL)                   /*!< MCUN0GPIO80 (Bit 16)                                  */
34353 #define GPIO_MCUN0INT2STAT_MCUN0GPIO80_Msk (0x10000UL)              /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
34354 #define GPIO_MCUN0INT2STAT_MCUN0GPIO79_Pos (15UL)                   /*!< MCUN0GPIO79 (Bit 15)                                  */
34355 #define GPIO_MCUN0INT2STAT_MCUN0GPIO79_Msk (0x8000UL)               /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
34356 #define GPIO_MCUN0INT2STAT_MCUN0GPIO78_Pos (14UL)                   /*!< MCUN0GPIO78 (Bit 14)                                  */
34357 #define GPIO_MCUN0INT2STAT_MCUN0GPIO78_Msk (0x4000UL)               /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
34358 #define GPIO_MCUN0INT2STAT_MCUN0GPIO77_Pos (13UL)                   /*!< MCUN0GPIO77 (Bit 13)                                  */
34359 #define GPIO_MCUN0INT2STAT_MCUN0GPIO77_Msk (0x2000UL)               /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
34360 #define GPIO_MCUN0INT2STAT_MCUN0GPIO76_Pos (12UL)                   /*!< MCUN0GPIO76 (Bit 12)                                  */
34361 #define GPIO_MCUN0INT2STAT_MCUN0GPIO76_Msk (0x1000UL)               /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
34362 #define GPIO_MCUN0INT2STAT_MCUN0GPIO75_Pos (11UL)                   /*!< MCUN0GPIO75 (Bit 11)                                  */
34363 #define GPIO_MCUN0INT2STAT_MCUN0GPIO75_Msk (0x800UL)                /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
34364 #define GPIO_MCUN0INT2STAT_MCUN0GPIO74_Pos (10UL)                   /*!< MCUN0GPIO74 (Bit 10)                                  */
34365 #define GPIO_MCUN0INT2STAT_MCUN0GPIO74_Msk (0x400UL)                /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
34366 #define GPIO_MCUN0INT2STAT_MCUN0GPIO73_Pos (9UL)                    /*!< MCUN0GPIO73 (Bit 9)                                   */
34367 #define GPIO_MCUN0INT2STAT_MCUN0GPIO73_Msk (0x200UL)                /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
34368 #define GPIO_MCUN0INT2STAT_MCUN0GPIO72_Pos (8UL)                    /*!< MCUN0GPIO72 (Bit 8)                                   */
34369 #define GPIO_MCUN0INT2STAT_MCUN0GPIO72_Msk (0x100UL)                /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
34370 #define GPIO_MCUN0INT2STAT_MCUN0GPIO71_Pos (7UL)                    /*!< MCUN0GPIO71 (Bit 7)                                   */
34371 #define GPIO_MCUN0INT2STAT_MCUN0GPIO71_Msk (0x80UL)                 /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
34372 #define GPIO_MCUN0INT2STAT_MCUN0GPIO70_Pos (6UL)                    /*!< MCUN0GPIO70 (Bit 6)                                   */
34373 #define GPIO_MCUN0INT2STAT_MCUN0GPIO70_Msk (0x40UL)                 /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
34374 #define GPIO_MCUN0INT2STAT_MCUN0GPIO69_Pos (5UL)                    /*!< MCUN0GPIO69 (Bit 5)                                   */
34375 #define GPIO_MCUN0INT2STAT_MCUN0GPIO69_Msk (0x20UL)                 /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
34376 #define GPIO_MCUN0INT2STAT_MCUN0GPIO68_Pos (4UL)                    /*!< MCUN0GPIO68 (Bit 4)                                   */
34377 #define GPIO_MCUN0INT2STAT_MCUN0GPIO68_Msk (0x10UL)                 /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
34378 #define GPIO_MCUN0INT2STAT_MCUN0GPIO67_Pos (3UL)                    /*!< MCUN0GPIO67 (Bit 3)                                   */
34379 #define GPIO_MCUN0INT2STAT_MCUN0GPIO67_Msk (0x8UL)                  /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
34380 #define GPIO_MCUN0INT2STAT_MCUN0GPIO66_Pos (2UL)                    /*!< MCUN0GPIO66 (Bit 2)                                   */
34381 #define GPIO_MCUN0INT2STAT_MCUN0GPIO66_Msk (0x4UL)                  /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
34382 #define GPIO_MCUN0INT2STAT_MCUN0GPIO65_Pos (1UL)                    /*!< MCUN0GPIO65 (Bit 1)                                   */
34383 #define GPIO_MCUN0INT2STAT_MCUN0GPIO65_Msk (0x2UL)                  /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
34384 #define GPIO_MCUN0INT2STAT_MCUN0GPIO64_Pos (0UL)                    /*!< MCUN0GPIO64 (Bit 0)                                   */
34385 #define GPIO_MCUN0INT2STAT_MCUN0GPIO64_Msk (0x1UL)                  /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
34386 /* =====================================================  MCUN0INT2CLR  ====================================================== */
34387 #define GPIO_MCUN0INT2CLR_MCUN0GPIO95_Pos (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
34388 #define GPIO_MCUN0INT2CLR_MCUN0GPIO95_Msk (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
34389 #define GPIO_MCUN0INT2CLR_MCUN0GPIO94_Pos (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
34390 #define GPIO_MCUN0INT2CLR_MCUN0GPIO94_Msk (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
34391 #define GPIO_MCUN0INT2CLR_MCUN0GPIO93_Pos (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
34392 #define GPIO_MCUN0INT2CLR_MCUN0GPIO93_Msk (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
34393 #define GPIO_MCUN0INT2CLR_MCUN0GPIO92_Pos (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
34394 #define GPIO_MCUN0INT2CLR_MCUN0GPIO92_Msk (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
34395 #define GPIO_MCUN0INT2CLR_MCUN0GPIO91_Pos (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
34396 #define GPIO_MCUN0INT2CLR_MCUN0GPIO91_Msk (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
34397 #define GPIO_MCUN0INT2CLR_MCUN0GPIO90_Pos (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
34398 #define GPIO_MCUN0INT2CLR_MCUN0GPIO90_Msk (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
34399 #define GPIO_MCUN0INT2CLR_MCUN0GPIO89_Pos (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
34400 #define GPIO_MCUN0INT2CLR_MCUN0GPIO89_Msk (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
34401 #define GPIO_MCUN0INT2CLR_MCUN0GPIO88_Pos (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
34402 #define GPIO_MCUN0INT2CLR_MCUN0GPIO88_Msk (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
34403 #define GPIO_MCUN0INT2CLR_MCUN0GPIO87_Pos (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
34404 #define GPIO_MCUN0INT2CLR_MCUN0GPIO87_Msk (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
34405 #define GPIO_MCUN0INT2CLR_MCUN0GPIO86_Pos (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
34406 #define GPIO_MCUN0INT2CLR_MCUN0GPIO86_Msk (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
34407 #define GPIO_MCUN0INT2CLR_MCUN0GPIO85_Pos (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
34408 #define GPIO_MCUN0INT2CLR_MCUN0GPIO85_Msk (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
34409 #define GPIO_MCUN0INT2CLR_MCUN0GPIO84_Pos (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
34410 #define GPIO_MCUN0INT2CLR_MCUN0GPIO84_Msk (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
34411 #define GPIO_MCUN0INT2CLR_MCUN0GPIO83_Pos (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
34412 #define GPIO_MCUN0INT2CLR_MCUN0GPIO83_Msk (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
34413 #define GPIO_MCUN0INT2CLR_MCUN0GPIO82_Pos (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
34414 #define GPIO_MCUN0INT2CLR_MCUN0GPIO82_Msk (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
34415 #define GPIO_MCUN0INT2CLR_MCUN0GPIO81_Pos (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
34416 #define GPIO_MCUN0INT2CLR_MCUN0GPIO81_Msk (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
34417 #define GPIO_MCUN0INT2CLR_MCUN0GPIO80_Pos (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
34418 #define GPIO_MCUN0INT2CLR_MCUN0GPIO80_Msk (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
34419 #define GPIO_MCUN0INT2CLR_MCUN0GPIO79_Pos (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
34420 #define GPIO_MCUN0INT2CLR_MCUN0GPIO79_Msk (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
34421 #define GPIO_MCUN0INT2CLR_MCUN0GPIO78_Pos (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
34422 #define GPIO_MCUN0INT2CLR_MCUN0GPIO78_Msk (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
34423 #define GPIO_MCUN0INT2CLR_MCUN0GPIO77_Pos (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
34424 #define GPIO_MCUN0INT2CLR_MCUN0GPIO77_Msk (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
34425 #define GPIO_MCUN0INT2CLR_MCUN0GPIO76_Pos (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
34426 #define GPIO_MCUN0INT2CLR_MCUN0GPIO76_Msk (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
34427 #define GPIO_MCUN0INT2CLR_MCUN0GPIO75_Pos (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
34428 #define GPIO_MCUN0INT2CLR_MCUN0GPIO75_Msk (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
34429 #define GPIO_MCUN0INT2CLR_MCUN0GPIO74_Pos (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
34430 #define GPIO_MCUN0INT2CLR_MCUN0GPIO74_Msk (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
34431 #define GPIO_MCUN0INT2CLR_MCUN0GPIO73_Pos (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
34432 #define GPIO_MCUN0INT2CLR_MCUN0GPIO73_Msk (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
34433 #define GPIO_MCUN0INT2CLR_MCUN0GPIO72_Pos (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
34434 #define GPIO_MCUN0INT2CLR_MCUN0GPIO72_Msk (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
34435 #define GPIO_MCUN0INT2CLR_MCUN0GPIO71_Pos (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
34436 #define GPIO_MCUN0INT2CLR_MCUN0GPIO71_Msk (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
34437 #define GPIO_MCUN0INT2CLR_MCUN0GPIO70_Pos (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
34438 #define GPIO_MCUN0INT2CLR_MCUN0GPIO70_Msk (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
34439 #define GPIO_MCUN0INT2CLR_MCUN0GPIO69_Pos (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
34440 #define GPIO_MCUN0INT2CLR_MCUN0GPIO69_Msk (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
34441 #define GPIO_MCUN0INT2CLR_MCUN0GPIO68_Pos (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
34442 #define GPIO_MCUN0INT2CLR_MCUN0GPIO68_Msk (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
34443 #define GPIO_MCUN0INT2CLR_MCUN0GPIO67_Pos (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
34444 #define GPIO_MCUN0INT2CLR_MCUN0GPIO67_Msk (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
34445 #define GPIO_MCUN0INT2CLR_MCUN0GPIO66_Pos (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
34446 #define GPIO_MCUN0INT2CLR_MCUN0GPIO66_Msk (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
34447 #define GPIO_MCUN0INT2CLR_MCUN0GPIO65_Pos (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
34448 #define GPIO_MCUN0INT2CLR_MCUN0GPIO65_Msk (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
34449 #define GPIO_MCUN0INT2CLR_MCUN0GPIO64_Pos (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
34450 #define GPIO_MCUN0INT2CLR_MCUN0GPIO64_Msk (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
34451 /* =====================================================  MCUN0INT2SET  ====================================================== */
34452 #define GPIO_MCUN0INT2SET_MCUN0GPIO95_Pos (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
34453 #define GPIO_MCUN0INT2SET_MCUN0GPIO95_Msk (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
34454 #define GPIO_MCUN0INT2SET_MCUN0GPIO94_Pos (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
34455 #define GPIO_MCUN0INT2SET_MCUN0GPIO94_Msk (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
34456 #define GPIO_MCUN0INT2SET_MCUN0GPIO93_Pos (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
34457 #define GPIO_MCUN0INT2SET_MCUN0GPIO93_Msk (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
34458 #define GPIO_MCUN0INT2SET_MCUN0GPIO92_Pos (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
34459 #define GPIO_MCUN0INT2SET_MCUN0GPIO92_Msk (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
34460 #define GPIO_MCUN0INT2SET_MCUN0GPIO91_Pos (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
34461 #define GPIO_MCUN0INT2SET_MCUN0GPIO91_Msk (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
34462 #define GPIO_MCUN0INT2SET_MCUN0GPIO90_Pos (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
34463 #define GPIO_MCUN0INT2SET_MCUN0GPIO90_Msk (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
34464 #define GPIO_MCUN0INT2SET_MCUN0GPIO89_Pos (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
34465 #define GPIO_MCUN0INT2SET_MCUN0GPIO89_Msk (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
34466 #define GPIO_MCUN0INT2SET_MCUN0GPIO88_Pos (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
34467 #define GPIO_MCUN0INT2SET_MCUN0GPIO88_Msk (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
34468 #define GPIO_MCUN0INT2SET_MCUN0GPIO87_Pos (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
34469 #define GPIO_MCUN0INT2SET_MCUN0GPIO87_Msk (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
34470 #define GPIO_MCUN0INT2SET_MCUN0GPIO86_Pos (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
34471 #define GPIO_MCUN0INT2SET_MCUN0GPIO86_Msk (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
34472 #define GPIO_MCUN0INT2SET_MCUN0GPIO85_Pos (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
34473 #define GPIO_MCUN0INT2SET_MCUN0GPIO85_Msk (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
34474 #define GPIO_MCUN0INT2SET_MCUN0GPIO84_Pos (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
34475 #define GPIO_MCUN0INT2SET_MCUN0GPIO84_Msk (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
34476 #define GPIO_MCUN0INT2SET_MCUN0GPIO83_Pos (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
34477 #define GPIO_MCUN0INT2SET_MCUN0GPIO83_Msk (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
34478 #define GPIO_MCUN0INT2SET_MCUN0GPIO82_Pos (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
34479 #define GPIO_MCUN0INT2SET_MCUN0GPIO82_Msk (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
34480 #define GPIO_MCUN0INT2SET_MCUN0GPIO81_Pos (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
34481 #define GPIO_MCUN0INT2SET_MCUN0GPIO81_Msk (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
34482 #define GPIO_MCUN0INT2SET_MCUN0GPIO80_Pos (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
34483 #define GPIO_MCUN0INT2SET_MCUN0GPIO80_Msk (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
34484 #define GPIO_MCUN0INT2SET_MCUN0GPIO79_Pos (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
34485 #define GPIO_MCUN0INT2SET_MCUN0GPIO79_Msk (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
34486 #define GPIO_MCUN0INT2SET_MCUN0GPIO78_Pos (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
34487 #define GPIO_MCUN0INT2SET_MCUN0GPIO78_Msk (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
34488 #define GPIO_MCUN0INT2SET_MCUN0GPIO77_Pos (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
34489 #define GPIO_MCUN0INT2SET_MCUN0GPIO77_Msk (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
34490 #define GPIO_MCUN0INT2SET_MCUN0GPIO76_Pos (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
34491 #define GPIO_MCUN0INT2SET_MCUN0GPIO76_Msk (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
34492 #define GPIO_MCUN0INT2SET_MCUN0GPIO75_Pos (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
34493 #define GPIO_MCUN0INT2SET_MCUN0GPIO75_Msk (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
34494 #define GPIO_MCUN0INT2SET_MCUN0GPIO74_Pos (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
34495 #define GPIO_MCUN0INT2SET_MCUN0GPIO74_Msk (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
34496 #define GPIO_MCUN0INT2SET_MCUN0GPIO73_Pos (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
34497 #define GPIO_MCUN0INT2SET_MCUN0GPIO73_Msk (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
34498 #define GPIO_MCUN0INT2SET_MCUN0GPIO72_Pos (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
34499 #define GPIO_MCUN0INT2SET_MCUN0GPIO72_Msk (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
34500 #define GPIO_MCUN0INT2SET_MCUN0GPIO71_Pos (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
34501 #define GPIO_MCUN0INT2SET_MCUN0GPIO71_Msk (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
34502 #define GPIO_MCUN0INT2SET_MCUN0GPIO70_Pos (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
34503 #define GPIO_MCUN0INT2SET_MCUN0GPIO70_Msk (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
34504 #define GPIO_MCUN0INT2SET_MCUN0GPIO69_Pos (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
34505 #define GPIO_MCUN0INT2SET_MCUN0GPIO69_Msk (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
34506 #define GPIO_MCUN0INT2SET_MCUN0GPIO68_Pos (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
34507 #define GPIO_MCUN0INT2SET_MCUN0GPIO68_Msk (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
34508 #define GPIO_MCUN0INT2SET_MCUN0GPIO67_Pos (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
34509 #define GPIO_MCUN0INT2SET_MCUN0GPIO67_Msk (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
34510 #define GPIO_MCUN0INT2SET_MCUN0GPIO66_Pos (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
34511 #define GPIO_MCUN0INT2SET_MCUN0GPIO66_Msk (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
34512 #define GPIO_MCUN0INT2SET_MCUN0GPIO65_Pos (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
34513 #define GPIO_MCUN0INT2SET_MCUN0GPIO65_Msk (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
34514 #define GPIO_MCUN0INT2SET_MCUN0GPIO64_Pos (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
34515 #define GPIO_MCUN0INT2SET_MCUN0GPIO64_Msk (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
34516 /* ======================================================  MCUN0INT3EN  ====================================================== */
34517 #define GPIO_MCUN0INT3EN_MCUN0GPIO127_Pos (31UL)                    /*!< MCUN0GPIO127 (Bit 31)                                 */
34518 #define GPIO_MCUN0INT3EN_MCUN0GPIO127_Msk (0x80000000UL)            /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
34519 #define GPIO_MCUN0INT3EN_MCUN0GPIO126_Pos (30UL)                    /*!< MCUN0GPIO126 (Bit 30)                                 */
34520 #define GPIO_MCUN0INT3EN_MCUN0GPIO126_Msk (0x40000000UL)            /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
34521 #define GPIO_MCUN0INT3EN_MCUN0GPIO125_Pos (29UL)                    /*!< MCUN0GPIO125 (Bit 29)                                 */
34522 #define GPIO_MCUN0INT3EN_MCUN0GPIO125_Msk (0x20000000UL)            /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
34523 #define GPIO_MCUN0INT3EN_MCUN0GPIO124_Pos (28UL)                    /*!< MCUN0GPIO124 (Bit 28)                                 */
34524 #define GPIO_MCUN0INT3EN_MCUN0GPIO124_Msk (0x10000000UL)            /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
34525 #define GPIO_MCUN0INT3EN_MCUN0GPIO123_Pos (27UL)                    /*!< MCUN0GPIO123 (Bit 27)                                 */
34526 #define GPIO_MCUN0INT3EN_MCUN0GPIO123_Msk (0x8000000UL)             /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
34527 #define GPIO_MCUN0INT3EN_MCUN0GPIO122_Pos (26UL)                    /*!< MCUN0GPIO122 (Bit 26)                                 */
34528 #define GPIO_MCUN0INT3EN_MCUN0GPIO122_Msk (0x4000000UL)             /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
34529 #define GPIO_MCUN0INT3EN_MCUN0GPIO121_Pos (25UL)                    /*!< MCUN0GPIO121 (Bit 25)                                 */
34530 #define GPIO_MCUN0INT3EN_MCUN0GPIO121_Msk (0x2000000UL)             /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
34531 #define GPIO_MCUN0INT3EN_MCUN0GPIO120_Pos (24UL)                    /*!< MCUN0GPIO120 (Bit 24)                                 */
34532 #define GPIO_MCUN0INT3EN_MCUN0GPIO120_Msk (0x1000000UL)             /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
34533 #define GPIO_MCUN0INT3EN_MCUN0GPIO119_Pos (23UL)                    /*!< MCUN0GPIO119 (Bit 23)                                 */
34534 #define GPIO_MCUN0INT3EN_MCUN0GPIO119_Msk (0x800000UL)              /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
34535 #define GPIO_MCUN0INT3EN_MCUN0GPIO118_Pos (22UL)                    /*!< MCUN0GPIO118 (Bit 22)                                 */
34536 #define GPIO_MCUN0INT3EN_MCUN0GPIO118_Msk (0x400000UL)              /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
34537 #define GPIO_MCUN0INT3EN_MCUN0GPIO117_Pos (21UL)                    /*!< MCUN0GPIO117 (Bit 21)                                 */
34538 #define GPIO_MCUN0INT3EN_MCUN0GPIO117_Msk (0x200000UL)              /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
34539 #define GPIO_MCUN0INT3EN_MCUN0GPIO116_Pos (20UL)                    /*!< MCUN0GPIO116 (Bit 20)                                 */
34540 #define GPIO_MCUN0INT3EN_MCUN0GPIO116_Msk (0x100000UL)              /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
34541 #define GPIO_MCUN0INT3EN_MCUN0GPIO115_Pos (19UL)                    /*!< MCUN0GPIO115 (Bit 19)                                 */
34542 #define GPIO_MCUN0INT3EN_MCUN0GPIO115_Msk (0x80000UL)               /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
34543 #define GPIO_MCUN0INT3EN_MCUN0GPIO114_Pos (18UL)                    /*!< MCUN0GPIO114 (Bit 18)                                 */
34544 #define GPIO_MCUN0INT3EN_MCUN0GPIO114_Msk (0x40000UL)               /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
34545 #define GPIO_MCUN0INT3EN_MCUN0GPIO113_Pos (17UL)                    /*!< MCUN0GPIO113 (Bit 17)                                 */
34546 #define GPIO_MCUN0INT3EN_MCUN0GPIO113_Msk (0x20000UL)               /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
34547 #define GPIO_MCUN0INT3EN_MCUN0GPIO112_Pos (16UL)                    /*!< MCUN0GPIO112 (Bit 16)                                 */
34548 #define GPIO_MCUN0INT3EN_MCUN0GPIO112_Msk (0x10000UL)               /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
34549 #define GPIO_MCUN0INT3EN_MCUN0GPIO111_Pos (15UL)                    /*!< MCUN0GPIO111 (Bit 15)                                 */
34550 #define GPIO_MCUN0INT3EN_MCUN0GPIO111_Msk (0x8000UL)                /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
34551 #define GPIO_MCUN0INT3EN_MCUN0GPIO110_Pos (14UL)                    /*!< MCUN0GPIO110 (Bit 14)                                 */
34552 #define GPIO_MCUN0INT3EN_MCUN0GPIO110_Msk (0x4000UL)                /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
34553 #define GPIO_MCUN0INT3EN_MCUN0GPIO109_Pos (13UL)                    /*!< MCUN0GPIO109 (Bit 13)                                 */
34554 #define GPIO_MCUN0INT3EN_MCUN0GPIO109_Msk (0x2000UL)                /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
34555 #define GPIO_MCUN0INT3EN_MCUN0GPIO108_Pos (12UL)                    /*!< MCUN0GPIO108 (Bit 12)                                 */
34556 #define GPIO_MCUN0INT3EN_MCUN0GPIO108_Msk (0x1000UL)                /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
34557 #define GPIO_MCUN0INT3EN_MCUN0GPIO107_Pos (11UL)                    /*!< MCUN0GPIO107 (Bit 11)                                 */
34558 #define GPIO_MCUN0INT3EN_MCUN0GPIO107_Msk (0x800UL)                 /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
34559 #define GPIO_MCUN0INT3EN_MCUN0GPIO106_Pos (10UL)                    /*!< MCUN0GPIO106 (Bit 10)                                 */
34560 #define GPIO_MCUN0INT3EN_MCUN0GPIO106_Msk (0x400UL)                 /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
34561 #define GPIO_MCUN0INT3EN_MCUN0GPIO105_Pos (9UL)                     /*!< MCUN0GPIO105 (Bit 9)                                  */
34562 #define GPIO_MCUN0INT3EN_MCUN0GPIO105_Msk (0x200UL)                 /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
34563 #define GPIO_MCUN0INT3EN_MCUN0GPIO104_Pos (8UL)                     /*!< MCUN0GPIO104 (Bit 8)                                  */
34564 #define GPIO_MCUN0INT3EN_MCUN0GPIO104_Msk (0x100UL)                 /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
34565 #define GPIO_MCUN0INT3EN_MCUN0GPIO103_Pos (7UL)                     /*!< MCUN0GPIO103 (Bit 7)                                  */
34566 #define GPIO_MCUN0INT3EN_MCUN0GPIO103_Msk (0x80UL)                  /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
34567 #define GPIO_MCUN0INT3EN_MCUN0GPIO102_Pos (6UL)                     /*!< MCUN0GPIO102 (Bit 6)                                  */
34568 #define GPIO_MCUN0INT3EN_MCUN0GPIO102_Msk (0x40UL)                  /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
34569 #define GPIO_MCUN0INT3EN_MCUN0GPIO101_Pos (5UL)                     /*!< MCUN0GPIO101 (Bit 5)                                  */
34570 #define GPIO_MCUN0INT3EN_MCUN0GPIO101_Msk (0x20UL)                  /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
34571 #define GPIO_MCUN0INT3EN_MCUN0GPIO100_Pos (4UL)                     /*!< MCUN0GPIO100 (Bit 4)                                  */
34572 #define GPIO_MCUN0INT3EN_MCUN0GPIO100_Msk (0x10UL)                  /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
34573 #define GPIO_MCUN0INT3EN_MCUN0GPIO99_Pos  (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
34574 #define GPIO_MCUN0INT3EN_MCUN0GPIO99_Msk  (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
34575 #define GPIO_MCUN0INT3EN_MCUN0GPIO98_Pos  (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
34576 #define GPIO_MCUN0INT3EN_MCUN0GPIO98_Msk  (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
34577 #define GPIO_MCUN0INT3EN_MCUN0GPIO97_Pos  (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
34578 #define GPIO_MCUN0INT3EN_MCUN0GPIO97_Msk  (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
34579 #define GPIO_MCUN0INT3EN_MCUN0GPIO96_Pos  (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
34580 #define GPIO_MCUN0INT3EN_MCUN0GPIO96_Msk  (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
34581 /* =====================================================  MCUN0INT3STAT  ===================================================== */
34582 #define GPIO_MCUN0INT3STAT_MCUN0GPIO127_Pos (31UL)                  /*!< MCUN0GPIO127 (Bit 31)                                 */
34583 #define GPIO_MCUN0INT3STAT_MCUN0GPIO127_Msk (0x80000000UL)          /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
34584 #define GPIO_MCUN0INT3STAT_MCUN0GPIO126_Pos (30UL)                  /*!< MCUN0GPIO126 (Bit 30)                                 */
34585 #define GPIO_MCUN0INT3STAT_MCUN0GPIO126_Msk (0x40000000UL)          /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
34586 #define GPIO_MCUN0INT3STAT_MCUN0GPIO125_Pos (29UL)                  /*!< MCUN0GPIO125 (Bit 29)                                 */
34587 #define GPIO_MCUN0INT3STAT_MCUN0GPIO125_Msk (0x20000000UL)          /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
34588 #define GPIO_MCUN0INT3STAT_MCUN0GPIO124_Pos (28UL)                  /*!< MCUN0GPIO124 (Bit 28)                                 */
34589 #define GPIO_MCUN0INT3STAT_MCUN0GPIO124_Msk (0x10000000UL)          /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
34590 #define GPIO_MCUN0INT3STAT_MCUN0GPIO123_Pos (27UL)                  /*!< MCUN0GPIO123 (Bit 27)                                 */
34591 #define GPIO_MCUN0INT3STAT_MCUN0GPIO123_Msk (0x8000000UL)           /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
34592 #define GPIO_MCUN0INT3STAT_MCUN0GPIO122_Pos (26UL)                  /*!< MCUN0GPIO122 (Bit 26)                                 */
34593 #define GPIO_MCUN0INT3STAT_MCUN0GPIO122_Msk (0x4000000UL)           /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
34594 #define GPIO_MCUN0INT3STAT_MCUN0GPIO121_Pos (25UL)                  /*!< MCUN0GPIO121 (Bit 25)                                 */
34595 #define GPIO_MCUN0INT3STAT_MCUN0GPIO121_Msk (0x2000000UL)           /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
34596 #define GPIO_MCUN0INT3STAT_MCUN0GPIO120_Pos (24UL)                  /*!< MCUN0GPIO120 (Bit 24)                                 */
34597 #define GPIO_MCUN0INT3STAT_MCUN0GPIO120_Msk (0x1000000UL)           /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
34598 #define GPIO_MCUN0INT3STAT_MCUN0GPIO119_Pos (23UL)                  /*!< MCUN0GPIO119 (Bit 23)                                 */
34599 #define GPIO_MCUN0INT3STAT_MCUN0GPIO119_Msk (0x800000UL)            /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
34600 #define GPIO_MCUN0INT3STAT_MCUN0GPIO118_Pos (22UL)                  /*!< MCUN0GPIO118 (Bit 22)                                 */
34601 #define GPIO_MCUN0INT3STAT_MCUN0GPIO118_Msk (0x400000UL)            /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
34602 #define GPIO_MCUN0INT3STAT_MCUN0GPIO117_Pos (21UL)                  /*!< MCUN0GPIO117 (Bit 21)                                 */
34603 #define GPIO_MCUN0INT3STAT_MCUN0GPIO117_Msk (0x200000UL)            /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
34604 #define GPIO_MCUN0INT3STAT_MCUN0GPIO116_Pos (20UL)                  /*!< MCUN0GPIO116 (Bit 20)                                 */
34605 #define GPIO_MCUN0INT3STAT_MCUN0GPIO116_Msk (0x100000UL)            /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
34606 #define GPIO_MCUN0INT3STAT_MCUN0GPIO115_Pos (19UL)                  /*!< MCUN0GPIO115 (Bit 19)                                 */
34607 #define GPIO_MCUN0INT3STAT_MCUN0GPIO115_Msk (0x80000UL)             /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
34608 #define GPIO_MCUN0INT3STAT_MCUN0GPIO114_Pos (18UL)                  /*!< MCUN0GPIO114 (Bit 18)                                 */
34609 #define GPIO_MCUN0INT3STAT_MCUN0GPIO114_Msk (0x40000UL)             /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
34610 #define GPIO_MCUN0INT3STAT_MCUN0GPIO113_Pos (17UL)                  /*!< MCUN0GPIO113 (Bit 17)                                 */
34611 #define GPIO_MCUN0INT3STAT_MCUN0GPIO113_Msk (0x20000UL)             /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
34612 #define GPIO_MCUN0INT3STAT_MCUN0GPIO112_Pos (16UL)                  /*!< MCUN0GPIO112 (Bit 16)                                 */
34613 #define GPIO_MCUN0INT3STAT_MCUN0GPIO112_Msk (0x10000UL)             /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
34614 #define GPIO_MCUN0INT3STAT_MCUN0GPIO111_Pos (15UL)                  /*!< MCUN0GPIO111 (Bit 15)                                 */
34615 #define GPIO_MCUN0INT3STAT_MCUN0GPIO111_Msk (0x8000UL)              /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
34616 #define GPIO_MCUN0INT3STAT_MCUN0GPIO110_Pos (14UL)                  /*!< MCUN0GPIO110 (Bit 14)                                 */
34617 #define GPIO_MCUN0INT3STAT_MCUN0GPIO110_Msk (0x4000UL)              /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
34618 #define GPIO_MCUN0INT3STAT_MCUN0GPIO109_Pos (13UL)                  /*!< MCUN0GPIO109 (Bit 13)                                 */
34619 #define GPIO_MCUN0INT3STAT_MCUN0GPIO109_Msk (0x2000UL)              /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
34620 #define GPIO_MCUN0INT3STAT_MCUN0GPIO108_Pos (12UL)                  /*!< MCUN0GPIO108 (Bit 12)                                 */
34621 #define GPIO_MCUN0INT3STAT_MCUN0GPIO108_Msk (0x1000UL)              /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
34622 #define GPIO_MCUN0INT3STAT_MCUN0GPIO107_Pos (11UL)                  /*!< MCUN0GPIO107 (Bit 11)                                 */
34623 #define GPIO_MCUN0INT3STAT_MCUN0GPIO107_Msk (0x800UL)               /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
34624 #define GPIO_MCUN0INT3STAT_MCUN0GPIO106_Pos (10UL)                  /*!< MCUN0GPIO106 (Bit 10)                                 */
34625 #define GPIO_MCUN0INT3STAT_MCUN0GPIO106_Msk (0x400UL)               /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
34626 #define GPIO_MCUN0INT3STAT_MCUN0GPIO105_Pos (9UL)                   /*!< MCUN0GPIO105 (Bit 9)                                  */
34627 #define GPIO_MCUN0INT3STAT_MCUN0GPIO105_Msk (0x200UL)               /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
34628 #define GPIO_MCUN0INT3STAT_MCUN0GPIO104_Pos (8UL)                   /*!< MCUN0GPIO104 (Bit 8)                                  */
34629 #define GPIO_MCUN0INT3STAT_MCUN0GPIO104_Msk (0x100UL)               /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
34630 #define GPIO_MCUN0INT3STAT_MCUN0GPIO103_Pos (7UL)                   /*!< MCUN0GPIO103 (Bit 7)                                  */
34631 #define GPIO_MCUN0INT3STAT_MCUN0GPIO103_Msk (0x80UL)                /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
34632 #define GPIO_MCUN0INT3STAT_MCUN0GPIO102_Pos (6UL)                   /*!< MCUN0GPIO102 (Bit 6)                                  */
34633 #define GPIO_MCUN0INT3STAT_MCUN0GPIO102_Msk (0x40UL)                /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
34634 #define GPIO_MCUN0INT3STAT_MCUN0GPIO101_Pos (5UL)                   /*!< MCUN0GPIO101 (Bit 5)                                  */
34635 #define GPIO_MCUN0INT3STAT_MCUN0GPIO101_Msk (0x20UL)                /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
34636 #define GPIO_MCUN0INT3STAT_MCUN0GPIO100_Pos (4UL)                   /*!< MCUN0GPIO100 (Bit 4)                                  */
34637 #define GPIO_MCUN0INT3STAT_MCUN0GPIO100_Msk (0x10UL)                /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
34638 #define GPIO_MCUN0INT3STAT_MCUN0GPIO99_Pos (3UL)                    /*!< MCUN0GPIO99 (Bit 3)                                   */
34639 #define GPIO_MCUN0INT3STAT_MCUN0GPIO99_Msk (0x8UL)                  /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
34640 #define GPIO_MCUN0INT3STAT_MCUN0GPIO98_Pos (2UL)                    /*!< MCUN0GPIO98 (Bit 2)                                   */
34641 #define GPIO_MCUN0INT3STAT_MCUN0GPIO98_Msk (0x4UL)                  /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
34642 #define GPIO_MCUN0INT3STAT_MCUN0GPIO97_Pos (1UL)                    /*!< MCUN0GPIO97 (Bit 1)                                   */
34643 #define GPIO_MCUN0INT3STAT_MCUN0GPIO97_Msk (0x2UL)                  /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
34644 #define GPIO_MCUN0INT3STAT_MCUN0GPIO96_Pos (0UL)                    /*!< MCUN0GPIO96 (Bit 0)                                   */
34645 #define GPIO_MCUN0INT3STAT_MCUN0GPIO96_Msk (0x1UL)                  /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
34646 /* =====================================================  MCUN0INT3CLR  ====================================================== */
34647 #define GPIO_MCUN0INT3CLR_MCUN0GPIO127_Pos (31UL)                   /*!< MCUN0GPIO127 (Bit 31)                                 */
34648 #define GPIO_MCUN0INT3CLR_MCUN0GPIO127_Msk (0x80000000UL)           /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
34649 #define GPIO_MCUN0INT3CLR_MCUN0GPIO126_Pos (30UL)                   /*!< MCUN0GPIO126 (Bit 30)                                 */
34650 #define GPIO_MCUN0INT3CLR_MCUN0GPIO126_Msk (0x40000000UL)           /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
34651 #define GPIO_MCUN0INT3CLR_MCUN0GPIO125_Pos (29UL)                   /*!< MCUN0GPIO125 (Bit 29)                                 */
34652 #define GPIO_MCUN0INT3CLR_MCUN0GPIO125_Msk (0x20000000UL)           /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
34653 #define GPIO_MCUN0INT3CLR_MCUN0GPIO124_Pos (28UL)                   /*!< MCUN0GPIO124 (Bit 28)                                 */
34654 #define GPIO_MCUN0INT3CLR_MCUN0GPIO124_Msk (0x10000000UL)           /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
34655 #define GPIO_MCUN0INT3CLR_MCUN0GPIO123_Pos (27UL)                   /*!< MCUN0GPIO123 (Bit 27)                                 */
34656 #define GPIO_MCUN0INT3CLR_MCUN0GPIO123_Msk (0x8000000UL)            /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
34657 #define GPIO_MCUN0INT3CLR_MCUN0GPIO122_Pos (26UL)                   /*!< MCUN0GPIO122 (Bit 26)                                 */
34658 #define GPIO_MCUN0INT3CLR_MCUN0GPIO122_Msk (0x4000000UL)            /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
34659 #define GPIO_MCUN0INT3CLR_MCUN0GPIO121_Pos (25UL)                   /*!< MCUN0GPIO121 (Bit 25)                                 */
34660 #define GPIO_MCUN0INT3CLR_MCUN0GPIO121_Msk (0x2000000UL)            /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
34661 #define GPIO_MCUN0INT3CLR_MCUN0GPIO120_Pos (24UL)                   /*!< MCUN0GPIO120 (Bit 24)                                 */
34662 #define GPIO_MCUN0INT3CLR_MCUN0GPIO120_Msk (0x1000000UL)            /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
34663 #define GPIO_MCUN0INT3CLR_MCUN0GPIO119_Pos (23UL)                   /*!< MCUN0GPIO119 (Bit 23)                                 */
34664 #define GPIO_MCUN0INT3CLR_MCUN0GPIO119_Msk (0x800000UL)             /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
34665 #define GPIO_MCUN0INT3CLR_MCUN0GPIO118_Pos (22UL)                   /*!< MCUN0GPIO118 (Bit 22)                                 */
34666 #define GPIO_MCUN0INT3CLR_MCUN0GPIO118_Msk (0x400000UL)             /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
34667 #define GPIO_MCUN0INT3CLR_MCUN0GPIO117_Pos (21UL)                   /*!< MCUN0GPIO117 (Bit 21)                                 */
34668 #define GPIO_MCUN0INT3CLR_MCUN0GPIO117_Msk (0x200000UL)             /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
34669 #define GPIO_MCUN0INT3CLR_MCUN0GPIO116_Pos (20UL)                   /*!< MCUN0GPIO116 (Bit 20)                                 */
34670 #define GPIO_MCUN0INT3CLR_MCUN0GPIO116_Msk (0x100000UL)             /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
34671 #define GPIO_MCUN0INT3CLR_MCUN0GPIO115_Pos (19UL)                   /*!< MCUN0GPIO115 (Bit 19)                                 */
34672 #define GPIO_MCUN0INT3CLR_MCUN0GPIO115_Msk (0x80000UL)              /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
34673 #define GPIO_MCUN0INT3CLR_MCUN0GPIO114_Pos (18UL)                   /*!< MCUN0GPIO114 (Bit 18)                                 */
34674 #define GPIO_MCUN0INT3CLR_MCUN0GPIO114_Msk (0x40000UL)              /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
34675 #define GPIO_MCUN0INT3CLR_MCUN0GPIO113_Pos (17UL)                   /*!< MCUN0GPIO113 (Bit 17)                                 */
34676 #define GPIO_MCUN0INT3CLR_MCUN0GPIO113_Msk (0x20000UL)              /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
34677 #define GPIO_MCUN0INT3CLR_MCUN0GPIO112_Pos (16UL)                   /*!< MCUN0GPIO112 (Bit 16)                                 */
34678 #define GPIO_MCUN0INT3CLR_MCUN0GPIO112_Msk (0x10000UL)              /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
34679 #define GPIO_MCUN0INT3CLR_MCUN0GPIO111_Pos (15UL)                   /*!< MCUN0GPIO111 (Bit 15)                                 */
34680 #define GPIO_MCUN0INT3CLR_MCUN0GPIO111_Msk (0x8000UL)               /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
34681 #define GPIO_MCUN0INT3CLR_MCUN0GPIO110_Pos (14UL)                   /*!< MCUN0GPIO110 (Bit 14)                                 */
34682 #define GPIO_MCUN0INT3CLR_MCUN0GPIO110_Msk (0x4000UL)               /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
34683 #define GPIO_MCUN0INT3CLR_MCUN0GPIO109_Pos (13UL)                   /*!< MCUN0GPIO109 (Bit 13)                                 */
34684 #define GPIO_MCUN0INT3CLR_MCUN0GPIO109_Msk (0x2000UL)               /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
34685 #define GPIO_MCUN0INT3CLR_MCUN0GPIO108_Pos (12UL)                   /*!< MCUN0GPIO108 (Bit 12)                                 */
34686 #define GPIO_MCUN0INT3CLR_MCUN0GPIO108_Msk (0x1000UL)               /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
34687 #define GPIO_MCUN0INT3CLR_MCUN0GPIO107_Pos (11UL)                   /*!< MCUN0GPIO107 (Bit 11)                                 */
34688 #define GPIO_MCUN0INT3CLR_MCUN0GPIO107_Msk (0x800UL)                /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
34689 #define GPIO_MCUN0INT3CLR_MCUN0GPIO106_Pos (10UL)                   /*!< MCUN0GPIO106 (Bit 10)                                 */
34690 #define GPIO_MCUN0INT3CLR_MCUN0GPIO106_Msk (0x400UL)                /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
34691 #define GPIO_MCUN0INT3CLR_MCUN0GPIO105_Pos (9UL)                    /*!< MCUN0GPIO105 (Bit 9)                                  */
34692 #define GPIO_MCUN0INT3CLR_MCUN0GPIO105_Msk (0x200UL)                /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
34693 #define GPIO_MCUN0INT3CLR_MCUN0GPIO104_Pos (8UL)                    /*!< MCUN0GPIO104 (Bit 8)                                  */
34694 #define GPIO_MCUN0INT3CLR_MCUN0GPIO104_Msk (0x100UL)                /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
34695 #define GPIO_MCUN0INT3CLR_MCUN0GPIO103_Pos (7UL)                    /*!< MCUN0GPIO103 (Bit 7)                                  */
34696 #define GPIO_MCUN0INT3CLR_MCUN0GPIO103_Msk (0x80UL)                 /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
34697 #define GPIO_MCUN0INT3CLR_MCUN0GPIO102_Pos (6UL)                    /*!< MCUN0GPIO102 (Bit 6)                                  */
34698 #define GPIO_MCUN0INT3CLR_MCUN0GPIO102_Msk (0x40UL)                 /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
34699 #define GPIO_MCUN0INT3CLR_MCUN0GPIO101_Pos (5UL)                    /*!< MCUN0GPIO101 (Bit 5)                                  */
34700 #define GPIO_MCUN0INT3CLR_MCUN0GPIO101_Msk (0x20UL)                 /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
34701 #define GPIO_MCUN0INT3CLR_MCUN0GPIO100_Pos (4UL)                    /*!< MCUN0GPIO100 (Bit 4)                                  */
34702 #define GPIO_MCUN0INT3CLR_MCUN0GPIO100_Msk (0x10UL)                 /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
34703 #define GPIO_MCUN0INT3CLR_MCUN0GPIO99_Pos (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
34704 #define GPIO_MCUN0INT3CLR_MCUN0GPIO99_Msk (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
34705 #define GPIO_MCUN0INT3CLR_MCUN0GPIO98_Pos (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
34706 #define GPIO_MCUN0INT3CLR_MCUN0GPIO98_Msk (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
34707 #define GPIO_MCUN0INT3CLR_MCUN0GPIO97_Pos (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
34708 #define GPIO_MCUN0INT3CLR_MCUN0GPIO97_Msk (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
34709 #define GPIO_MCUN0INT3CLR_MCUN0GPIO96_Pos (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
34710 #define GPIO_MCUN0INT3CLR_MCUN0GPIO96_Msk (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
34711 /* =====================================================  MCUN0INT3SET  ====================================================== */
34712 #define GPIO_MCUN0INT3SET_MCUN0GPIO127_Pos (31UL)                   /*!< MCUN0GPIO127 (Bit 31)                                 */
34713 #define GPIO_MCUN0INT3SET_MCUN0GPIO127_Msk (0x80000000UL)           /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
34714 #define GPIO_MCUN0INT3SET_MCUN0GPIO126_Pos (30UL)                   /*!< MCUN0GPIO126 (Bit 30)                                 */
34715 #define GPIO_MCUN0INT3SET_MCUN0GPIO126_Msk (0x40000000UL)           /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
34716 #define GPIO_MCUN0INT3SET_MCUN0GPIO125_Pos (29UL)                   /*!< MCUN0GPIO125 (Bit 29)                                 */
34717 #define GPIO_MCUN0INT3SET_MCUN0GPIO125_Msk (0x20000000UL)           /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
34718 #define GPIO_MCUN0INT3SET_MCUN0GPIO124_Pos (28UL)                   /*!< MCUN0GPIO124 (Bit 28)                                 */
34719 #define GPIO_MCUN0INT3SET_MCUN0GPIO124_Msk (0x10000000UL)           /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
34720 #define GPIO_MCUN0INT3SET_MCUN0GPIO123_Pos (27UL)                   /*!< MCUN0GPIO123 (Bit 27)                                 */
34721 #define GPIO_MCUN0INT3SET_MCUN0GPIO123_Msk (0x8000000UL)            /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
34722 #define GPIO_MCUN0INT3SET_MCUN0GPIO122_Pos (26UL)                   /*!< MCUN0GPIO122 (Bit 26)                                 */
34723 #define GPIO_MCUN0INT3SET_MCUN0GPIO122_Msk (0x4000000UL)            /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
34724 #define GPIO_MCUN0INT3SET_MCUN0GPIO121_Pos (25UL)                   /*!< MCUN0GPIO121 (Bit 25)                                 */
34725 #define GPIO_MCUN0INT3SET_MCUN0GPIO121_Msk (0x2000000UL)            /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
34726 #define GPIO_MCUN0INT3SET_MCUN0GPIO120_Pos (24UL)                   /*!< MCUN0GPIO120 (Bit 24)                                 */
34727 #define GPIO_MCUN0INT3SET_MCUN0GPIO120_Msk (0x1000000UL)            /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
34728 #define GPIO_MCUN0INT3SET_MCUN0GPIO119_Pos (23UL)                   /*!< MCUN0GPIO119 (Bit 23)                                 */
34729 #define GPIO_MCUN0INT3SET_MCUN0GPIO119_Msk (0x800000UL)             /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
34730 #define GPIO_MCUN0INT3SET_MCUN0GPIO118_Pos (22UL)                   /*!< MCUN0GPIO118 (Bit 22)                                 */
34731 #define GPIO_MCUN0INT3SET_MCUN0GPIO118_Msk (0x400000UL)             /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
34732 #define GPIO_MCUN0INT3SET_MCUN0GPIO117_Pos (21UL)                   /*!< MCUN0GPIO117 (Bit 21)                                 */
34733 #define GPIO_MCUN0INT3SET_MCUN0GPIO117_Msk (0x200000UL)             /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
34734 #define GPIO_MCUN0INT3SET_MCUN0GPIO116_Pos (20UL)                   /*!< MCUN0GPIO116 (Bit 20)                                 */
34735 #define GPIO_MCUN0INT3SET_MCUN0GPIO116_Msk (0x100000UL)             /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
34736 #define GPIO_MCUN0INT3SET_MCUN0GPIO115_Pos (19UL)                   /*!< MCUN0GPIO115 (Bit 19)                                 */
34737 #define GPIO_MCUN0INT3SET_MCUN0GPIO115_Msk (0x80000UL)              /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
34738 #define GPIO_MCUN0INT3SET_MCUN0GPIO114_Pos (18UL)                   /*!< MCUN0GPIO114 (Bit 18)                                 */
34739 #define GPIO_MCUN0INT3SET_MCUN0GPIO114_Msk (0x40000UL)              /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
34740 #define GPIO_MCUN0INT3SET_MCUN0GPIO113_Pos (17UL)                   /*!< MCUN0GPIO113 (Bit 17)                                 */
34741 #define GPIO_MCUN0INT3SET_MCUN0GPIO113_Msk (0x20000UL)              /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
34742 #define GPIO_MCUN0INT3SET_MCUN0GPIO112_Pos (16UL)                   /*!< MCUN0GPIO112 (Bit 16)                                 */
34743 #define GPIO_MCUN0INT3SET_MCUN0GPIO112_Msk (0x10000UL)              /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
34744 #define GPIO_MCUN0INT3SET_MCUN0GPIO111_Pos (15UL)                   /*!< MCUN0GPIO111 (Bit 15)                                 */
34745 #define GPIO_MCUN0INT3SET_MCUN0GPIO111_Msk (0x8000UL)               /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
34746 #define GPIO_MCUN0INT3SET_MCUN0GPIO110_Pos (14UL)                   /*!< MCUN0GPIO110 (Bit 14)                                 */
34747 #define GPIO_MCUN0INT3SET_MCUN0GPIO110_Msk (0x4000UL)               /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
34748 #define GPIO_MCUN0INT3SET_MCUN0GPIO109_Pos (13UL)                   /*!< MCUN0GPIO109 (Bit 13)                                 */
34749 #define GPIO_MCUN0INT3SET_MCUN0GPIO109_Msk (0x2000UL)               /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
34750 #define GPIO_MCUN0INT3SET_MCUN0GPIO108_Pos (12UL)                   /*!< MCUN0GPIO108 (Bit 12)                                 */
34751 #define GPIO_MCUN0INT3SET_MCUN0GPIO108_Msk (0x1000UL)               /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
34752 #define GPIO_MCUN0INT3SET_MCUN0GPIO107_Pos (11UL)                   /*!< MCUN0GPIO107 (Bit 11)                                 */
34753 #define GPIO_MCUN0INT3SET_MCUN0GPIO107_Msk (0x800UL)                /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
34754 #define GPIO_MCUN0INT3SET_MCUN0GPIO106_Pos (10UL)                   /*!< MCUN0GPIO106 (Bit 10)                                 */
34755 #define GPIO_MCUN0INT3SET_MCUN0GPIO106_Msk (0x400UL)                /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
34756 #define GPIO_MCUN0INT3SET_MCUN0GPIO105_Pos (9UL)                    /*!< MCUN0GPIO105 (Bit 9)                                  */
34757 #define GPIO_MCUN0INT3SET_MCUN0GPIO105_Msk (0x200UL)                /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
34758 #define GPIO_MCUN0INT3SET_MCUN0GPIO104_Pos (8UL)                    /*!< MCUN0GPIO104 (Bit 8)                                  */
34759 #define GPIO_MCUN0INT3SET_MCUN0GPIO104_Msk (0x100UL)                /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
34760 #define GPIO_MCUN0INT3SET_MCUN0GPIO103_Pos (7UL)                    /*!< MCUN0GPIO103 (Bit 7)                                  */
34761 #define GPIO_MCUN0INT3SET_MCUN0GPIO103_Msk (0x80UL)                 /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
34762 #define GPIO_MCUN0INT3SET_MCUN0GPIO102_Pos (6UL)                    /*!< MCUN0GPIO102 (Bit 6)                                  */
34763 #define GPIO_MCUN0INT3SET_MCUN0GPIO102_Msk (0x40UL)                 /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
34764 #define GPIO_MCUN0INT3SET_MCUN0GPIO101_Pos (5UL)                    /*!< MCUN0GPIO101 (Bit 5)                                  */
34765 #define GPIO_MCUN0INT3SET_MCUN0GPIO101_Msk (0x20UL)                 /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
34766 #define GPIO_MCUN0INT3SET_MCUN0GPIO100_Pos (4UL)                    /*!< MCUN0GPIO100 (Bit 4)                                  */
34767 #define GPIO_MCUN0INT3SET_MCUN0GPIO100_Msk (0x10UL)                 /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
34768 #define GPIO_MCUN0INT3SET_MCUN0GPIO99_Pos (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
34769 #define GPIO_MCUN0INT3SET_MCUN0GPIO99_Msk (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
34770 #define GPIO_MCUN0INT3SET_MCUN0GPIO98_Pos (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
34771 #define GPIO_MCUN0INT3SET_MCUN0GPIO98_Msk (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
34772 #define GPIO_MCUN0INT3SET_MCUN0GPIO97_Pos (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
34773 #define GPIO_MCUN0INT3SET_MCUN0GPIO97_Msk (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
34774 #define GPIO_MCUN0INT3SET_MCUN0GPIO96_Pos (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
34775 #define GPIO_MCUN0INT3SET_MCUN0GPIO96_Msk (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
34776 /* ======================================================  MCUN1INT0EN  ====================================================== */
34777 #define GPIO_MCUN1INT0EN_MCUN1GPIO31_Pos  (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
34778 #define GPIO_MCUN1INT0EN_MCUN1GPIO31_Msk  (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
34779 #define GPIO_MCUN1INT0EN_MCUN1GPIO30_Pos  (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
34780 #define GPIO_MCUN1INT0EN_MCUN1GPIO30_Msk  (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
34781 #define GPIO_MCUN1INT0EN_MCUN1GPIO29_Pos  (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
34782 #define GPIO_MCUN1INT0EN_MCUN1GPIO29_Msk  (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
34783 #define GPIO_MCUN1INT0EN_MCUN1GPIO28_Pos  (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
34784 #define GPIO_MCUN1INT0EN_MCUN1GPIO28_Msk  (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
34785 #define GPIO_MCUN1INT0EN_MCUN1GPIO27_Pos  (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
34786 #define GPIO_MCUN1INT0EN_MCUN1GPIO27_Msk  (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
34787 #define GPIO_MCUN1INT0EN_MCUN1GPIO26_Pos  (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
34788 #define GPIO_MCUN1INT0EN_MCUN1GPIO26_Msk  (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
34789 #define GPIO_MCUN1INT0EN_MCUN1GPIO25_Pos  (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
34790 #define GPIO_MCUN1INT0EN_MCUN1GPIO25_Msk  (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
34791 #define GPIO_MCUN1INT0EN_MCUN1GPIO24_Pos  (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
34792 #define GPIO_MCUN1INT0EN_MCUN1GPIO24_Msk  (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
34793 #define GPIO_MCUN1INT0EN_MCUN1GPIO23_Pos  (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
34794 #define GPIO_MCUN1INT0EN_MCUN1GPIO23_Msk  (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
34795 #define GPIO_MCUN1INT0EN_MCUN1GPIO22_Pos  (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
34796 #define GPIO_MCUN1INT0EN_MCUN1GPIO22_Msk  (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
34797 #define GPIO_MCUN1INT0EN_MCUN1GPIO21_Pos  (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
34798 #define GPIO_MCUN1INT0EN_MCUN1GPIO21_Msk  (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
34799 #define GPIO_MCUN1INT0EN_MCUN1GPIO20_Pos  (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
34800 #define GPIO_MCUN1INT0EN_MCUN1GPIO20_Msk  (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
34801 #define GPIO_MCUN1INT0EN_MCUN1GPIO19_Pos  (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
34802 #define GPIO_MCUN1INT0EN_MCUN1GPIO19_Msk  (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
34803 #define GPIO_MCUN1INT0EN_MCUN1GPIO18_Pos  (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
34804 #define GPIO_MCUN1INT0EN_MCUN1GPIO18_Msk  (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
34805 #define GPIO_MCUN1INT0EN_MCUN1GPIO17_Pos  (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
34806 #define GPIO_MCUN1INT0EN_MCUN1GPIO17_Msk  (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
34807 #define GPIO_MCUN1INT0EN_MCUN1GPIO16_Pos  (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
34808 #define GPIO_MCUN1INT0EN_MCUN1GPIO16_Msk  (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
34809 #define GPIO_MCUN1INT0EN_MCUN1GPIO15_Pos  (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
34810 #define GPIO_MCUN1INT0EN_MCUN1GPIO15_Msk  (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
34811 #define GPIO_MCUN1INT0EN_MCUN1GPIO14_Pos  (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
34812 #define GPIO_MCUN1INT0EN_MCUN1GPIO14_Msk  (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
34813 #define GPIO_MCUN1INT0EN_MCUN1GPIO13_Pos  (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
34814 #define GPIO_MCUN1INT0EN_MCUN1GPIO13_Msk  (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
34815 #define GPIO_MCUN1INT0EN_MCUN1GPIO12_Pos  (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
34816 #define GPIO_MCUN1INT0EN_MCUN1GPIO12_Msk  (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
34817 #define GPIO_MCUN1INT0EN_MCUN1GPIO11_Pos  (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
34818 #define GPIO_MCUN1INT0EN_MCUN1GPIO11_Msk  (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
34819 #define GPIO_MCUN1INT0EN_MCUN1GPIO10_Pos  (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
34820 #define GPIO_MCUN1INT0EN_MCUN1GPIO10_Msk  (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
34821 #define GPIO_MCUN1INT0EN_MCUN1GPIO9_Pos   (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
34822 #define GPIO_MCUN1INT0EN_MCUN1GPIO9_Msk   (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
34823 #define GPIO_MCUN1INT0EN_MCUN1GPIO8_Pos   (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
34824 #define GPIO_MCUN1INT0EN_MCUN1GPIO8_Msk   (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
34825 #define GPIO_MCUN1INT0EN_MCUN1GPIO7_Pos   (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
34826 #define GPIO_MCUN1INT0EN_MCUN1GPIO7_Msk   (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
34827 #define GPIO_MCUN1INT0EN_MCUN1GPIO6_Pos   (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
34828 #define GPIO_MCUN1INT0EN_MCUN1GPIO6_Msk   (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
34829 #define GPIO_MCUN1INT0EN_MCUN1GPIO5_Pos   (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
34830 #define GPIO_MCUN1INT0EN_MCUN1GPIO5_Msk   (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
34831 #define GPIO_MCUN1INT0EN_MCUN1GPIO4_Pos   (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
34832 #define GPIO_MCUN1INT0EN_MCUN1GPIO4_Msk   (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
34833 #define GPIO_MCUN1INT0EN_MCUN1GPIO3_Pos   (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
34834 #define GPIO_MCUN1INT0EN_MCUN1GPIO3_Msk   (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
34835 #define GPIO_MCUN1INT0EN_MCUN1GPIO2_Pos   (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
34836 #define GPIO_MCUN1INT0EN_MCUN1GPIO2_Msk   (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
34837 #define GPIO_MCUN1INT0EN_MCUN1GPIO1_Pos   (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
34838 #define GPIO_MCUN1INT0EN_MCUN1GPIO1_Msk   (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
34839 #define GPIO_MCUN1INT0EN_MCUN1GPIO0_Pos   (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
34840 #define GPIO_MCUN1INT0EN_MCUN1GPIO0_Msk   (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
34841 /* =====================================================  MCUN1INT0STAT  ===================================================== */
34842 #define GPIO_MCUN1INT0STAT_MCUN1GPIO31_Pos (31UL)                   /*!< MCUN1GPIO31 (Bit 31)                                  */
34843 #define GPIO_MCUN1INT0STAT_MCUN1GPIO31_Msk (0x80000000UL)           /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
34844 #define GPIO_MCUN1INT0STAT_MCUN1GPIO30_Pos (30UL)                   /*!< MCUN1GPIO30 (Bit 30)                                  */
34845 #define GPIO_MCUN1INT0STAT_MCUN1GPIO30_Msk (0x40000000UL)           /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
34846 #define GPIO_MCUN1INT0STAT_MCUN1GPIO29_Pos (29UL)                   /*!< MCUN1GPIO29 (Bit 29)                                  */
34847 #define GPIO_MCUN1INT0STAT_MCUN1GPIO29_Msk (0x20000000UL)           /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
34848 #define GPIO_MCUN1INT0STAT_MCUN1GPIO28_Pos (28UL)                   /*!< MCUN1GPIO28 (Bit 28)                                  */
34849 #define GPIO_MCUN1INT0STAT_MCUN1GPIO28_Msk (0x10000000UL)           /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
34850 #define GPIO_MCUN1INT0STAT_MCUN1GPIO27_Pos (27UL)                   /*!< MCUN1GPIO27 (Bit 27)                                  */
34851 #define GPIO_MCUN1INT0STAT_MCUN1GPIO27_Msk (0x8000000UL)            /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
34852 #define GPIO_MCUN1INT0STAT_MCUN1GPIO26_Pos (26UL)                   /*!< MCUN1GPIO26 (Bit 26)                                  */
34853 #define GPIO_MCUN1INT0STAT_MCUN1GPIO26_Msk (0x4000000UL)            /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
34854 #define GPIO_MCUN1INT0STAT_MCUN1GPIO25_Pos (25UL)                   /*!< MCUN1GPIO25 (Bit 25)                                  */
34855 #define GPIO_MCUN1INT0STAT_MCUN1GPIO25_Msk (0x2000000UL)            /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
34856 #define GPIO_MCUN1INT0STAT_MCUN1GPIO24_Pos (24UL)                   /*!< MCUN1GPIO24 (Bit 24)                                  */
34857 #define GPIO_MCUN1INT0STAT_MCUN1GPIO24_Msk (0x1000000UL)            /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
34858 #define GPIO_MCUN1INT0STAT_MCUN1GPIO23_Pos (23UL)                   /*!< MCUN1GPIO23 (Bit 23)                                  */
34859 #define GPIO_MCUN1INT0STAT_MCUN1GPIO23_Msk (0x800000UL)             /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
34860 #define GPIO_MCUN1INT0STAT_MCUN1GPIO22_Pos (22UL)                   /*!< MCUN1GPIO22 (Bit 22)                                  */
34861 #define GPIO_MCUN1INT0STAT_MCUN1GPIO22_Msk (0x400000UL)             /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
34862 #define GPIO_MCUN1INT0STAT_MCUN1GPIO21_Pos (21UL)                   /*!< MCUN1GPIO21 (Bit 21)                                  */
34863 #define GPIO_MCUN1INT0STAT_MCUN1GPIO21_Msk (0x200000UL)             /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
34864 #define GPIO_MCUN1INT0STAT_MCUN1GPIO20_Pos (20UL)                   /*!< MCUN1GPIO20 (Bit 20)                                  */
34865 #define GPIO_MCUN1INT0STAT_MCUN1GPIO20_Msk (0x100000UL)             /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
34866 #define GPIO_MCUN1INT0STAT_MCUN1GPIO19_Pos (19UL)                   /*!< MCUN1GPIO19 (Bit 19)                                  */
34867 #define GPIO_MCUN1INT0STAT_MCUN1GPIO19_Msk (0x80000UL)              /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
34868 #define GPIO_MCUN1INT0STAT_MCUN1GPIO18_Pos (18UL)                   /*!< MCUN1GPIO18 (Bit 18)                                  */
34869 #define GPIO_MCUN1INT0STAT_MCUN1GPIO18_Msk (0x40000UL)              /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
34870 #define GPIO_MCUN1INT0STAT_MCUN1GPIO17_Pos (17UL)                   /*!< MCUN1GPIO17 (Bit 17)                                  */
34871 #define GPIO_MCUN1INT0STAT_MCUN1GPIO17_Msk (0x20000UL)              /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
34872 #define GPIO_MCUN1INT0STAT_MCUN1GPIO16_Pos (16UL)                   /*!< MCUN1GPIO16 (Bit 16)                                  */
34873 #define GPIO_MCUN1INT0STAT_MCUN1GPIO16_Msk (0x10000UL)              /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
34874 #define GPIO_MCUN1INT0STAT_MCUN1GPIO15_Pos (15UL)                   /*!< MCUN1GPIO15 (Bit 15)                                  */
34875 #define GPIO_MCUN1INT0STAT_MCUN1GPIO15_Msk (0x8000UL)               /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
34876 #define GPIO_MCUN1INT0STAT_MCUN1GPIO14_Pos (14UL)                   /*!< MCUN1GPIO14 (Bit 14)                                  */
34877 #define GPIO_MCUN1INT0STAT_MCUN1GPIO14_Msk (0x4000UL)               /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
34878 #define GPIO_MCUN1INT0STAT_MCUN1GPIO13_Pos (13UL)                   /*!< MCUN1GPIO13 (Bit 13)                                  */
34879 #define GPIO_MCUN1INT0STAT_MCUN1GPIO13_Msk (0x2000UL)               /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
34880 #define GPIO_MCUN1INT0STAT_MCUN1GPIO12_Pos (12UL)                   /*!< MCUN1GPIO12 (Bit 12)                                  */
34881 #define GPIO_MCUN1INT0STAT_MCUN1GPIO12_Msk (0x1000UL)               /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
34882 #define GPIO_MCUN1INT0STAT_MCUN1GPIO11_Pos (11UL)                   /*!< MCUN1GPIO11 (Bit 11)                                  */
34883 #define GPIO_MCUN1INT0STAT_MCUN1GPIO11_Msk (0x800UL)                /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
34884 #define GPIO_MCUN1INT0STAT_MCUN1GPIO10_Pos (10UL)                   /*!< MCUN1GPIO10 (Bit 10)                                  */
34885 #define GPIO_MCUN1INT0STAT_MCUN1GPIO10_Msk (0x400UL)                /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
34886 #define GPIO_MCUN1INT0STAT_MCUN1GPIO9_Pos (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
34887 #define GPIO_MCUN1INT0STAT_MCUN1GPIO9_Msk (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
34888 #define GPIO_MCUN1INT0STAT_MCUN1GPIO8_Pos (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
34889 #define GPIO_MCUN1INT0STAT_MCUN1GPIO8_Msk (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
34890 #define GPIO_MCUN1INT0STAT_MCUN1GPIO7_Pos (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
34891 #define GPIO_MCUN1INT0STAT_MCUN1GPIO7_Msk (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
34892 #define GPIO_MCUN1INT0STAT_MCUN1GPIO6_Pos (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
34893 #define GPIO_MCUN1INT0STAT_MCUN1GPIO6_Msk (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
34894 #define GPIO_MCUN1INT0STAT_MCUN1GPIO5_Pos (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
34895 #define GPIO_MCUN1INT0STAT_MCUN1GPIO5_Msk (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
34896 #define GPIO_MCUN1INT0STAT_MCUN1GPIO4_Pos (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
34897 #define GPIO_MCUN1INT0STAT_MCUN1GPIO4_Msk (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
34898 #define GPIO_MCUN1INT0STAT_MCUN1GPIO3_Pos (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
34899 #define GPIO_MCUN1INT0STAT_MCUN1GPIO3_Msk (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
34900 #define GPIO_MCUN1INT0STAT_MCUN1GPIO2_Pos (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
34901 #define GPIO_MCUN1INT0STAT_MCUN1GPIO2_Msk (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
34902 #define GPIO_MCUN1INT0STAT_MCUN1GPIO1_Pos (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
34903 #define GPIO_MCUN1INT0STAT_MCUN1GPIO1_Msk (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
34904 #define GPIO_MCUN1INT0STAT_MCUN1GPIO0_Pos (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
34905 #define GPIO_MCUN1INT0STAT_MCUN1GPIO0_Msk (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
34906 /* =====================================================  MCUN1INT0CLR  ====================================================== */
34907 #define GPIO_MCUN1INT0CLR_MCUN1GPIO31_Pos (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
34908 #define GPIO_MCUN1INT0CLR_MCUN1GPIO31_Msk (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
34909 #define GPIO_MCUN1INT0CLR_MCUN1GPIO30_Pos (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
34910 #define GPIO_MCUN1INT0CLR_MCUN1GPIO30_Msk (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
34911 #define GPIO_MCUN1INT0CLR_MCUN1GPIO29_Pos (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
34912 #define GPIO_MCUN1INT0CLR_MCUN1GPIO29_Msk (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
34913 #define GPIO_MCUN1INT0CLR_MCUN1GPIO28_Pos (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
34914 #define GPIO_MCUN1INT0CLR_MCUN1GPIO28_Msk (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
34915 #define GPIO_MCUN1INT0CLR_MCUN1GPIO27_Pos (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
34916 #define GPIO_MCUN1INT0CLR_MCUN1GPIO27_Msk (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
34917 #define GPIO_MCUN1INT0CLR_MCUN1GPIO26_Pos (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
34918 #define GPIO_MCUN1INT0CLR_MCUN1GPIO26_Msk (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
34919 #define GPIO_MCUN1INT0CLR_MCUN1GPIO25_Pos (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
34920 #define GPIO_MCUN1INT0CLR_MCUN1GPIO25_Msk (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
34921 #define GPIO_MCUN1INT0CLR_MCUN1GPIO24_Pos (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
34922 #define GPIO_MCUN1INT0CLR_MCUN1GPIO24_Msk (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
34923 #define GPIO_MCUN1INT0CLR_MCUN1GPIO23_Pos (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
34924 #define GPIO_MCUN1INT0CLR_MCUN1GPIO23_Msk (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
34925 #define GPIO_MCUN1INT0CLR_MCUN1GPIO22_Pos (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
34926 #define GPIO_MCUN1INT0CLR_MCUN1GPIO22_Msk (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
34927 #define GPIO_MCUN1INT0CLR_MCUN1GPIO21_Pos (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
34928 #define GPIO_MCUN1INT0CLR_MCUN1GPIO21_Msk (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
34929 #define GPIO_MCUN1INT0CLR_MCUN1GPIO20_Pos (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
34930 #define GPIO_MCUN1INT0CLR_MCUN1GPIO20_Msk (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
34931 #define GPIO_MCUN1INT0CLR_MCUN1GPIO19_Pos (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
34932 #define GPIO_MCUN1INT0CLR_MCUN1GPIO19_Msk (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
34933 #define GPIO_MCUN1INT0CLR_MCUN1GPIO18_Pos (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
34934 #define GPIO_MCUN1INT0CLR_MCUN1GPIO18_Msk (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
34935 #define GPIO_MCUN1INT0CLR_MCUN1GPIO17_Pos (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
34936 #define GPIO_MCUN1INT0CLR_MCUN1GPIO17_Msk (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
34937 #define GPIO_MCUN1INT0CLR_MCUN1GPIO16_Pos (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
34938 #define GPIO_MCUN1INT0CLR_MCUN1GPIO16_Msk (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
34939 #define GPIO_MCUN1INT0CLR_MCUN1GPIO15_Pos (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
34940 #define GPIO_MCUN1INT0CLR_MCUN1GPIO15_Msk (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
34941 #define GPIO_MCUN1INT0CLR_MCUN1GPIO14_Pos (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
34942 #define GPIO_MCUN1INT0CLR_MCUN1GPIO14_Msk (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
34943 #define GPIO_MCUN1INT0CLR_MCUN1GPIO13_Pos (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
34944 #define GPIO_MCUN1INT0CLR_MCUN1GPIO13_Msk (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
34945 #define GPIO_MCUN1INT0CLR_MCUN1GPIO12_Pos (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
34946 #define GPIO_MCUN1INT0CLR_MCUN1GPIO12_Msk (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
34947 #define GPIO_MCUN1INT0CLR_MCUN1GPIO11_Pos (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
34948 #define GPIO_MCUN1INT0CLR_MCUN1GPIO11_Msk (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
34949 #define GPIO_MCUN1INT0CLR_MCUN1GPIO10_Pos (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
34950 #define GPIO_MCUN1INT0CLR_MCUN1GPIO10_Msk (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
34951 #define GPIO_MCUN1INT0CLR_MCUN1GPIO9_Pos  (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
34952 #define GPIO_MCUN1INT0CLR_MCUN1GPIO9_Msk  (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
34953 #define GPIO_MCUN1INT0CLR_MCUN1GPIO8_Pos  (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
34954 #define GPIO_MCUN1INT0CLR_MCUN1GPIO8_Msk  (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
34955 #define GPIO_MCUN1INT0CLR_MCUN1GPIO7_Pos  (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
34956 #define GPIO_MCUN1INT0CLR_MCUN1GPIO7_Msk  (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
34957 #define GPIO_MCUN1INT0CLR_MCUN1GPIO6_Pos  (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
34958 #define GPIO_MCUN1INT0CLR_MCUN1GPIO6_Msk  (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
34959 #define GPIO_MCUN1INT0CLR_MCUN1GPIO5_Pos  (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
34960 #define GPIO_MCUN1INT0CLR_MCUN1GPIO5_Msk  (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
34961 #define GPIO_MCUN1INT0CLR_MCUN1GPIO4_Pos  (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
34962 #define GPIO_MCUN1INT0CLR_MCUN1GPIO4_Msk  (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
34963 #define GPIO_MCUN1INT0CLR_MCUN1GPIO3_Pos  (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
34964 #define GPIO_MCUN1INT0CLR_MCUN1GPIO3_Msk  (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
34965 #define GPIO_MCUN1INT0CLR_MCUN1GPIO2_Pos  (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
34966 #define GPIO_MCUN1INT0CLR_MCUN1GPIO2_Msk  (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
34967 #define GPIO_MCUN1INT0CLR_MCUN1GPIO1_Pos  (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
34968 #define GPIO_MCUN1INT0CLR_MCUN1GPIO1_Msk  (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
34969 #define GPIO_MCUN1INT0CLR_MCUN1GPIO0_Pos  (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
34970 #define GPIO_MCUN1INT0CLR_MCUN1GPIO0_Msk  (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
34971 /* =====================================================  MCUN1INT0SET  ====================================================== */
34972 #define GPIO_MCUN1INT0SET_MCUN1GPIO31_Pos (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
34973 #define GPIO_MCUN1INT0SET_MCUN1GPIO31_Msk (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
34974 #define GPIO_MCUN1INT0SET_MCUN1GPIO30_Pos (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
34975 #define GPIO_MCUN1INT0SET_MCUN1GPIO30_Msk (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
34976 #define GPIO_MCUN1INT0SET_MCUN1GPIO29_Pos (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
34977 #define GPIO_MCUN1INT0SET_MCUN1GPIO29_Msk (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
34978 #define GPIO_MCUN1INT0SET_MCUN1GPIO28_Pos (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
34979 #define GPIO_MCUN1INT0SET_MCUN1GPIO28_Msk (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
34980 #define GPIO_MCUN1INT0SET_MCUN1GPIO27_Pos (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
34981 #define GPIO_MCUN1INT0SET_MCUN1GPIO27_Msk (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
34982 #define GPIO_MCUN1INT0SET_MCUN1GPIO26_Pos (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
34983 #define GPIO_MCUN1INT0SET_MCUN1GPIO26_Msk (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
34984 #define GPIO_MCUN1INT0SET_MCUN1GPIO25_Pos (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
34985 #define GPIO_MCUN1INT0SET_MCUN1GPIO25_Msk (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
34986 #define GPIO_MCUN1INT0SET_MCUN1GPIO24_Pos (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
34987 #define GPIO_MCUN1INT0SET_MCUN1GPIO24_Msk (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
34988 #define GPIO_MCUN1INT0SET_MCUN1GPIO23_Pos (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
34989 #define GPIO_MCUN1INT0SET_MCUN1GPIO23_Msk (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
34990 #define GPIO_MCUN1INT0SET_MCUN1GPIO22_Pos (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
34991 #define GPIO_MCUN1INT0SET_MCUN1GPIO22_Msk (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
34992 #define GPIO_MCUN1INT0SET_MCUN1GPIO21_Pos (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
34993 #define GPIO_MCUN1INT0SET_MCUN1GPIO21_Msk (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
34994 #define GPIO_MCUN1INT0SET_MCUN1GPIO20_Pos (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
34995 #define GPIO_MCUN1INT0SET_MCUN1GPIO20_Msk (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
34996 #define GPIO_MCUN1INT0SET_MCUN1GPIO19_Pos (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
34997 #define GPIO_MCUN1INT0SET_MCUN1GPIO19_Msk (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
34998 #define GPIO_MCUN1INT0SET_MCUN1GPIO18_Pos (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
34999 #define GPIO_MCUN1INT0SET_MCUN1GPIO18_Msk (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
35000 #define GPIO_MCUN1INT0SET_MCUN1GPIO17_Pos (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
35001 #define GPIO_MCUN1INT0SET_MCUN1GPIO17_Msk (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
35002 #define GPIO_MCUN1INT0SET_MCUN1GPIO16_Pos (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
35003 #define GPIO_MCUN1INT0SET_MCUN1GPIO16_Msk (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
35004 #define GPIO_MCUN1INT0SET_MCUN1GPIO15_Pos (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
35005 #define GPIO_MCUN1INT0SET_MCUN1GPIO15_Msk (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
35006 #define GPIO_MCUN1INT0SET_MCUN1GPIO14_Pos (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
35007 #define GPIO_MCUN1INT0SET_MCUN1GPIO14_Msk (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
35008 #define GPIO_MCUN1INT0SET_MCUN1GPIO13_Pos (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
35009 #define GPIO_MCUN1INT0SET_MCUN1GPIO13_Msk (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
35010 #define GPIO_MCUN1INT0SET_MCUN1GPIO12_Pos (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
35011 #define GPIO_MCUN1INT0SET_MCUN1GPIO12_Msk (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
35012 #define GPIO_MCUN1INT0SET_MCUN1GPIO11_Pos (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
35013 #define GPIO_MCUN1INT0SET_MCUN1GPIO11_Msk (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
35014 #define GPIO_MCUN1INT0SET_MCUN1GPIO10_Pos (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
35015 #define GPIO_MCUN1INT0SET_MCUN1GPIO10_Msk (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
35016 #define GPIO_MCUN1INT0SET_MCUN1GPIO9_Pos  (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
35017 #define GPIO_MCUN1INT0SET_MCUN1GPIO9_Msk  (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
35018 #define GPIO_MCUN1INT0SET_MCUN1GPIO8_Pos  (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
35019 #define GPIO_MCUN1INT0SET_MCUN1GPIO8_Msk  (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
35020 #define GPIO_MCUN1INT0SET_MCUN1GPIO7_Pos  (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
35021 #define GPIO_MCUN1INT0SET_MCUN1GPIO7_Msk  (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
35022 #define GPIO_MCUN1INT0SET_MCUN1GPIO6_Pos  (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
35023 #define GPIO_MCUN1INT0SET_MCUN1GPIO6_Msk  (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
35024 #define GPIO_MCUN1INT0SET_MCUN1GPIO5_Pos  (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
35025 #define GPIO_MCUN1INT0SET_MCUN1GPIO5_Msk  (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
35026 #define GPIO_MCUN1INT0SET_MCUN1GPIO4_Pos  (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
35027 #define GPIO_MCUN1INT0SET_MCUN1GPIO4_Msk  (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
35028 #define GPIO_MCUN1INT0SET_MCUN1GPIO3_Pos  (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
35029 #define GPIO_MCUN1INT0SET_MCUN1GPIO3_Msk  (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
35030 #define GPIO_MCUN1INT0SET_MCUN1GPIO2_Pos  (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
35031 #define GPIO_MCUN1INT0SET_MCUN1GPIO2_Msk  (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
35032 #define GPIO_MCUN1INT0SET_MCUN1GPIO1_Pos  (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
35033 #define GPIO_MCUN1INT0SET_MCUN1GPIO1_Msk  (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
35034 #define GPIO_MCUN1INT0SET_MCUN1GPIO0_Pos  (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
35035 #define GPIO_MCUN1INT0SET_MCUN1GPIO0_Msk  (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
35036 /* ======================================================  MCUN1INT1EN  ====================================================== */
35037 #define GPIO_MCUN1INT1EN_MCUN1GPIO63_Pos  (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
35038 #define GPIO_MCUN1INT1EN_MCUN1GPIO63_Msk  (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35039 #define GPIO_MCUN1INT1EN_MCUN1GPIO62_Pos  (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
35040 #define GPIO_MCUN1INT1EN_MCUN1GPIO62_Msk  (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35041 #define GPIO_MCUN1INT1EN_MCUN1GPIO61_Pos  (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
35042 #define GPIO_MCUN1INT1EN_MCUN1GPIO61_Msk  (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35043 #define GPIO_MCUN1INT1EN_MCUN1GPIO60_Pos  (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
35044 #define GPIO_MCUN1INT1EN_MCUN1GPIO60_Msk  (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35045 #define GPIO_MCUN1INT1EN_MCUN1GPIO59_Pos  (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
35046 #define GPIO_MCUN1INT1EN_MCUN1GPIO59_Msk  (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35047 #define GPIO_MCUN1INT1EN_MCUN1GPIO58_Pos  (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
35048 #define GPIO_MCUN1INT1EN_MCUN1GPIO58_Msk  (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35049 #define GPIO_MCUN1INT1EN_MCUN1GPIO57_Pos  (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
35050 #define GPIO_MCUN1INT1EN_MCUN1GPIO57_Msk  (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35051 #define GPIO_MCUN1INT1EN_MCUN1GPIO56_Pos  (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
35052 #define GPIO_MCUN1INT1EN_MCUN1GPIO56_Msk  (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35053 #define GPIO_MCUN1INT1EN_MCUN1GPIO55_Pos  (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
35054 #define GPIO_MCUN1INT1EN_MCUN1GPIO55_Msk  (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35055 #define GPIO_MCUN1INT1EN_MCUN1GPIO54_Pos  (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
35056 #define GPIO_MCUN1INT1EN_MCUN1GPIO54_Msk  (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35057 #define GPIO_MCUN1INT1EN_MCUN1GPIO53_Pos  (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
35058 #define GPIO_MCUN1INT1EN_MCUN1GPIO53_Msk  (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35059 #define GPIO_MCUN1INT1EN_MCUN1GPIO52_Pos  (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
35060 #define GPIO_MCUN1INT1EN_MCUN1GPIO52_Msk  (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35061 #define GPIO_MCUN1INT1EN_MCUN1GPIO51_Pos  (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
35062 #define GPIO_MCUN1INT1EN_MCUN1GPIO51_Msk  (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35063 #define GPIO_MCUN1INT1EN_MCUN1GPIO50_Pos  (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
35064 #define GPIO_MCUN1INT1EN_MCUN1GPIO50_Msk  (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35065 #define GPIO_MCUN1INT1EN_MCUN1GPIO49_Pos  (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
35066 #define GPIO_MCUN1INT1EN_MCUN1GPIO49_Msk  (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35067 #define GPIO_MCUN1INT1EN_MCUN1GPIO48_Pos  (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
35068 #define GPIO_MCUN1INT1EN_MCUN1GPIO48_Msk  (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35069 #define GPIO_MCUN1INT1EN_MCUN1GPIO47_Pos  (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
35070 #define GPIO_MCUN1INT1EN_MCUN1GPIO47_Msk  (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35071 #define GPIO_MCUN1INT1EN_MCUN1GPIO46_Pos  (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
35072 #define GPIO_MCUN1INT1EN_MCUN1GPIO46_Msk  (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35073 #define GPIO_MCUN1INT1EN_MCUN1GPIO45_Pos  (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
35074 #define GPIO_MCUN1INT1EN_MCUN1GPIO45_Msk  (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35075 #define GPIO_MCUN1INT1EN_MCUN1GPIO44_Pos  (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
35076 #define GPIO_MCUN1INT1EN_MCUN1GPIO44_Msk  (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35077 #define GPIO_MCUN1INT1EN_MCUN1GPIO43_Pos  (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
35078 #define GPIO_MCUN1INT1EN_MCUN1GPIO43_Msk  (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35079 #define GPIO_MCUN1INT1EN_MCUN1GPIO42_Pos  (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
35080 #define GPIO_MCUN1INT1EN_MCUN1GPIO42_Msk  (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35081 #define GPIO_MCUN1INT1EN_MCUN1GPIO41_Pos  (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
35082 #define GPIO_MCUN1INT1EN_MCUN1GPIO41_Msk  (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35083 #define GPIO_MCUN1INT1EN_MCUN1GPIO40_Pos  (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
35084 #define GPIO_MCUN1INT1EN_MCUN1GPIO40_Msk  (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35085 #define GPIO_MCUN1INT1EN_MCUN1GPIO39_Pos  (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
35086 #define GPIO_MCUN1INT1EN_MCUN1GPIO39_Msk  (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35087 #define GPIO_MCUN1INT1EN_MCUN1GPIO38_Pos  (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
35088 #define GPIO_MCUN1INT1EN_MCUN1GPIO38_Msk  (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35089 #define GPIO_MCUN1INT1EN_MCUN1GPIO37_Pos  (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
35090 #define GPIO_MCUN1INT1EN_MCUN1GPIO37_Msk  (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35091 #define GPIO_MCUN1INT1EN_MCUN1GPIO36_Pos  (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
35092 #define GPIO_MCUN1INT1EN_MCUN1GPIO36_Msk  (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35093 #define GPIO_MCUN1INT1EN_MCUN1GPIO35_Pos  (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
35094 #define GPIO_MCUN1INT1EN_MCUN1GPIO35_Msk  (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35095 #define GPIO_MCUN1INT1EN_MCUN1GPIO34_Pos  (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
35096 #define GPIO_MCUN1INT1EN_MCUN1GPIO34_Msk  (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35097 #define GPIO_MCUN1INT1EN_MCUN1GPIO33_Pos  (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
35098 #define GPIO_MCUN1INT1EN_MCUN1GPIO33_Msk  (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35099 #define GPIO_MCUN1INT1EN_MCUN1GPIO32_Pos  (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
35100 #define GPIO_MCUN1INT1EN_MCUN1GPIO32_Msk  (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35101 /* =====================================================  MCUN1INT1STAT  ===================================================== */
35102 #define GPIO_MCUN1INT1STAT_MCUN1GPIO63_Pos (31UL)                   /*!< MCUN1GPIO63 (Bit 31)                                  */
35103 #define GPIO_MCUN1INT1STAT_MCUN1GPIO63_Msk (0x80000000UL)           /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35104 #define GPIO_MCUN1INT1STAT_MCUN1GPIO62_Pos (30UL)                   /*!< MCUN1GPIO62 (Bit 30)                                  */
35105 #define GPIO_MCUN1INT1STAT_MCUN1GPIO62_Msk (0x40000000UL)           /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35106 #define GPIO_MCUN1INT1STAT_MCUN1GPIO61_Pos (29UL)                   /*!< MCUN1GPIO61 (Bit 29)                                  */
35107 #define GPIO_MCUN1INT1STAT_MCUN1GPIO61_Msk (0x20000000UL)           /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35108 #define GPIO_MCUN1INT1STAT_MCUN1GPIO60_Pos (28UL)                   /*!< MCUN1GPIO60 (Bit 28)                                  */
35109 #define GPIO_MCUN1INT1STAT_MCUN1GPIO60_Msk (0x10000000UL)           /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35110 #define GPIO_MCUN1INT1STAT_MCUN1GPIO59_Pos (27UL)                   /*!< MCUN1GPIO59 (Bit 27)                                  */
35111 #define GPIO_MCUN1INT1STAT_MCUN1GPIO59_Msk (0x8000000UL)            /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35112 #define GPIO_MCUN1INT1STAT_MCUN1GPIO58_Pos (26UL)                   /*!< MCUN1GPIO58 (Bit 26)                                  */
35113 #define GPIO_MCUN1INT1STAT_MCUN1GPIO58_Msk (0x4000000UL)            /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35114 #define GPIO_MCUN1INT1STAT_MCUN1GPIO57_Pos (25UL)                   /*!< MCUN1GPIO57 (Bit 25)                                  */
35115 #define GPIO_MCUN1INT1STAT_MCUN1GPIO57_Msk (0x2000000UL)            /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35116 #define GPIO_MCUN1INT1STAT_MCUN1GPIO56_Pos (24UL)                   /*!< MCUN1GPIO56 (Bit 24)                                  */
35117 #define GPIO_MCUN1INT1STAT_MCUN1GPIO56_Msk (0x1000000UL)            /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35118 #define GPIO_MCUN1INT1STAT_MCUN1GPIO55_Pos (23UL)                   /*!< MCUN1GPIO55 (Bit 23)                                  */
35119 #define GPIO_MCUN1INT1STAT_MCUN1GPIO55_Msk (0x800000UL)             /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35120 #define GPIO_MCUN1INT1STAT_MCUN1GPIO54_Pos (22UL)                   /*!< MCUN1GPIO54 (Bit 22)                                  */
35121 #define GPIO_MCUN1INT1STAT_MCUN1GPIO54_Msk (0x400000UL)             /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35122 #define GPIO_MCUN1INT1STAT_MCUN1GPIO53_Pos (21UL)                   /*!< MCUN1GPIO53 (Bit 21)                                  */
35123 #define GPIO_MCUN1INT1STAT_MCUN1GPIO53_Msk (0x200000UL)             /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35124 #define GPIO_MCUN1INT1STAT_MCUN1GPIO52_Pos (20UL)                   /*!< MCUN1GPIO52 (Bit 20)                                  */
35125 #define GPIO_MCUN1INT1STAT_MCUN1GPIO52_Msk (0x100000UL)             /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35126 #define GPIO_MCUN1INT1STAT_MCUN1GPIO51_Pos (19UL)                   /*!< MCUN1GPIO51 (Bit 19)                                  */
35127 #define GPIO_MCUN1INT1STAT_MCUN1GPIO51_Msk (0x80000UL)              /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35128 #define GPIO_MCUN1INT1STAT_MCUN1GPIO50_Pos (18UL)                   /*!< MCUN1GPIO50 (Bit 18)                                  */
35129 #define GPIO_MCUN1INT1STAT_MCUN1GPIO50_Msk (0x40000UL)              /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35130 #define GPIO_MCUN1INT1STAT_MCUN1GPIO49_Pos (17UL)                   /*!< MCUN1GPIO49 (Bit 17)                                  */
35131 #define GPIO_MCUN1INT1STAT_MCUN1GPIO49_Msk (0x20000UL)              /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35132 #define GPIO_MCUN1INT1STAT_MCUN1GPIO48_Pos (16UL)                   /*!< MCUN1GPIO48 (Bit 16)                                  */
35133 #define GPIO_MCUN1INT1STAT_MCUN1GPIO48_Msk (0x10000UL)              /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35134 #define GPIO_MCUN1INT1STAT_MCUN1GPIO47_Pos (15UL)                   /*!< MCUN1GPIO47 (Bit 15)                                  */
35135 #define GPIO_MCUN1INT1STAT_MCUN1GPIO47_Msk (0x8000UL)               /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35136 #define GPIO_MCUN1INT1STAT_MCUN1GPIO46_Pos (14UL)                   /*!< MCUN1GPIO46 (Bit 14)                                  */
35137 #define GPIO_MCUN1INT1STAT_MCUN1GPIO46_Msk (0x4000UL)               /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35138 #define GPIO_MCUN1INT1STAT_MCUN1GPIO45_Pos (13UL)                   /*!< MCUN1GPIO45 (Bit 13)                                  */
35139 #define GPIO_MCUN1INT1STAT_MCUN1GPIO45_Msk (0x2000UL)               /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35140 #define GPIO_MCUN1INT1STAT_MCUN1GPIO44_Pos (12UL)                   /*!< MCUN1GPIO44 (Bit 12)                                  */
35141 #define GPIO_MCUN1INT1STAT_MCUN1GPIO44_Msk (0x1000UL)               /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35142 #define GPIO_MCUN1INT1STAT_MCUN1GPIO43_Pos (11UL)                   /*!< MCUN1GPIO43 (Bit 11)                                  */
35143 #define GPIO_MCUN1INT1STAT_MCUN1GPIO43_Msk (0x800UL)                /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35144 #define GPIO_MCUN1INT1STAT_MCUN1GPIO42_Pos (10UL)                   /*!< MCUN1GPIO42 (Bit 10)                                  */
35145 #define GPIO_MCUN1INT1STAT_MCUN1GPIO42_Msk (0x400UL)                /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35146 #define GPIO_MCUN1INT1STAT_MCUN1GPIO41_Pos (9UL)                    /*!< MCUN1GPIO41 (Bit 9)                                   */
35147 #define GPIO_MCUN1INT1STAT_MCUN1GPIO41_Msk (0x200UL)                /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35148 #define GPIO_MCUN1INT1STAT_MCUN1GPIO40_Pos (8UL)                    /*!< MCUN1GPIO40 (Bit 8)                                   */
35149 #define GPIO_MCUN1INT1STAT_MCUN1GPIO40_Msk (0x100UL)                /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35150 #define GPIO_MCUN1INT1STAT_MCUN1GPIO39_Pos (7UL)                    /*!< MCUN1GPIO39 (Bit 7)                                   */
35151 #define GPIO_MCUN1INT1STAT_MCUN1GPIO39_Msk (0x80UL)                 /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35152 #define GPIO_MCUN1INT1STAT_MCUN1GPIO38_Pos (6UL)                    /*!< MCUN1GPIO38 (Bit 6)                                   */
35153 #define GPIO_MCUN1INT1STAT_MCUN1GPIO38_Msk (0x40UL)                 /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35154 #define GPIO_MCUN1INT1STAT_MCUN1GPIO37_Pos (5UL)                    /*!< MCUN1GPIO37 (Bit 5)                                   */
35155 #define GPIO_MCUN1INT1STAT_MCUN1GPIO37_Msk (0x20UL)                 /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35156 #define GPIO_MCUN1INT1STAT_MCUN1GPIO36_Pos (4UL)                    /*!< MCUN1GPIO36 (Bit 4)                                   */
35157 #define GPIO_MCUN1INT1STAT_MCUN1GPIO36_Msk (0x10UL)                 /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35158 #define GPIO_MCUN1INT1STAT_MCUN1GPIO35_Pos (3UL)                    /*!< MCUN1GPIO35 (Bit 3)                                   */
35159 #define GPIO_MCUN1INT1STAT_MCUN1GPIO35_Msk (0x8UL)                  /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35160 #define GPIO_MCUN1INT1STAT_MCUN1GPIO34_Pos (2UL)                    /*!< MCUN1GPIO34 (Bit 2)                                   */
35161 #define GPIO_MCUN1INT1STAT_MCUN1GPIO34_Msk (0x4UL)                  /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35162 #define GPIO_MCUN1INT1STAT_MCUN1GPIO33_Pos (1UL)                    /*!< MCUN1GPIO33 (Bit 1)                                   */
35163 #define GPIO_MCUN1INT1STAT_MCUN1GPIO33_Msk (0x2UL)                  /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35164 #define GPIO_MCUN1INT1STAT_MCUN1GPIO32_Pos (0UL)                    /*!< MCUN1GPIO32 (Bit 0)                                   */
35165 #define GPIO_MCUN1INT1STAT_MCUN1GPIO32_Msk (0x1UL)                  /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35166 /* =====================================================  MCUN1INT1CLR  ====================================================== */
35167 #define GPIO_MCUN1INT1CLR_MCUN1GPIO63_Pos (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
35168 #define GPIO_MCUN1INT1CLR_MCUN1GPIO63_Msk (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35169 #define GPIO_MCUN1INT1CLR_MCUN1GPIO62_Pos (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
35170 #define GPIO_MCUN1INT1CLR_MCUN1GPIO62_Msk (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35171 #define GPIO_MCUN1INT1CLR_MCUN1GPIO61_Pos (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
35172 #define GPIO_MCUN1INT1CLR_MCUN1GPIO61_Msk (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35173 #define GPIO_MCUN1INT1CLR_MCUN1GPIO60_Pos (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
35174 #define GPIO_MCUN1INT1CLR_MCUN1GPIO60_Msk (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35175 #define GPIO_MCUN1INT1CLR_MCUN1GPIO59_Pos (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
35176 #define GPIO_MCUN1INT1CLR_MCUN1GPIO59_Msk (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35177 #define GPIO_MCUN1INT1CLR_MCUN1GPIO58_Pos (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
35178 #define GPIO_MCUN1INT1CLR_MCUN1GPIO58_Msk (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35179 #define GPIO_MCUN1INT1CLR_MCUN1GPIO57_Pos (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
35180 #define GPIO_MCUN1INT1CLR_MCUN1GPIO57_Msk (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35181 #define GPIO_MCUN1INT1CLR_MCUN1GPIO56_Pos (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
35182 #define GPIO_MCUN1INT1CLR_MCUN1GPIO56_Msk (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35183 #define GPIO_MCUN1INT1CLR_MCUN1GPIO55_Pos (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
35184 #define GPIO_MCUN1INT1CLR_MCUN1GPIO55_Msk (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35185 #define GPIO_MCUN1INT1CLR_MCUN1GPIO54_Pos (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
35186 #define GPIO_MCUN1INT1CLR_MCUN1GPIO54_Msk (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35187 #define GPIO_MCUN1INT1CLR_MCUN1GPIO53_Pos (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
35188 #define GPIO_MCUN1INT1CLR_MCUN1GPIO53_Msk (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35189 #define GPIO_MCUN1INT1CLR_MCUN1GPIO52_Pos (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
35190 #define GPIO_MCUN1INT1CLR_MCUN1GPIO52_Msk (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35191 #define GPIO_MCUN1INT1CLR_MCUN1GPIO51_Pos (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
35192 #define GPIO_MCUN1INT1CLR_MCUN1GPIO51_Msk (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35193 #define GPIO_MCUN1INT1CLR_MCUN1GPIO50_Pos (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
35194 #define GPIO_MCUN1INT1CLR_MCUN1GPIO50_Msk (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35195 #define GPIO_MCUN1INT1CLR_MCUN1GPIO49_Pos (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
35196 #define GPIO_MCUN1INT1CLR_MCUN1GPIO49_Msk (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35197 #define GPIO_MCUN1INT1CLR_MCUN1GPIO48_Pos (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
35198 #define GPIO_MCUN1INT1CLR_MCUN1GPIO48_Msk (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35199 #define GPIO_MCUN1INT1CLR_MCUN1GPIO47_Pos (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
35200 #define GPIO_MCUN1INT1CLR_MCUN1GPIO47_Msk (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35201 #define GPIO_MCUN1INT1CLR_MCUN1GPIO46_Pos (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
35202 #define GPIO_MCUN1INT1CLR_MCUN1GPIO46_Msk (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35203 #define GPIO_MCUN1INT1CLR_MCUN1GPIO45_Pos (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
35204 #define GPIO_MCUN1INT1CLR_MCUN1GPIO45_Msk (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35205 #define GPIO_MCUN1INT1CLR_MCUN1GPIO44_Pos (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
35206 #define GPIO_MCUN1INT1CLR_MCUN1GPIO44_Msk (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35207 #define GPIO_MCUN1INT1CLR_MCUN1GPIO43_Pos (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
35208 #define GPIO_MCUN1INT1CLR_MCUN1GPIO43_Msk (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35209 #define GPIO_MCUN1INT1CLR_MCUN1GPIO42_Pos (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
35210 #define GPIO_MCUN1INT1CLR_MCUN1GPIO42_Msk (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35211 #define GPIO_MCUN1INT1CLR_MCUN1GPIO41_Pos (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
35212 #define GPIO_MCUN1INT1CLR_MCUN1GPIO41_Msk (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35213 #define GPIO_MCUN1INT1CLR_MCUN1GPIO40_Pos (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
35214 #define GPIO_MCUN1INT1CLR_MCUN1GPIO40_Msk (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35215 #define GPIO_MCUN1INT1CLR_MCUN1GPIO39_Pos (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
35216 #define GPIO_MCUN1INT1CLR_MCUN1GPIO39_Msk (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35217 #define GPIO_MCUN1INT1CLR_MCUN1GPIO38_Pos (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
35218 #define GPIO_MCUN1INT1CLR_MCUN1GPIO38_Msk (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35219 #define GPIO_MCUN1INT1CLR_MCUN1GPIO37_Pos (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
35220 #define GPIO_MCUN1INT1CLR_MCUN1GPIO37_Msk (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35221 #define GPIO_MCUN1INT1CLR_MCUN1GPIO36_Pos (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
35222 #define GPIO_MCUN1INT1CLR_MCUN1GPIO36_Msk (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35223 #define GPIO_MCUN1INT1CLR_MCUN1GPIO35_Pos (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
35224 #define GPIO_MCUN1INT1CLR_MCUN1GPIO35_Msk (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35225 #define GPIO_MCUN1INT1CLR_MCUN1GPIO34_Pos (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
35226 #define GPIO_MCUN1INT1CLR_MCUN1GPIO34_Msk (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35227 #define GPIO_MCUN1INT1CLR_MCUN1GPIO33_Pos (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
35228 #define GPIO_MCUN1INT1CLR_MCUN1GPIO33_Msk (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35229 #define GPIO_MCUN1INT1CLR_MCUN1GPIO32_Pos (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
35230 #define GPIO_MCUN1INT1CLR_MCUN1GPIO32_Msk (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35231 /* =====================================================  MCUN1INT1SET  ====================================================== */
35232 #define GPIO_MCUN1INT1SET_MCUN1GPIO63_Pos (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
35233 #define GPIO_MCUN1INT1SET_MCUN1GPIO63_Msk (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35234 #define GPIO_MCUN1INT1SET_MCUN1GPIO62_Pos (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
35235 #define GPIO_MCUN1INT1SET_MCUN1GPIO62_Msk (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35236 #define GPIO_MCUN1INT1SET_MCUN1GPIO61_Pos (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
35237 #define GPIO_MCUN1INT1SET_MCUN1GPIO61_Msk (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35238 #define GPIO_MCUN1INT1SET_MCUN1GPIO60_Pos (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
35239 #define GPIO_MCUN1INT1SET_MCUN1GPIO60_Msk (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35240 #define GPIO_MCUN1INT1SET_MCUN1GPIO59_Pos (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
35241 #define GPIO_MCUN1INT1SET_MCUN1GPIO59_Msk (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35242 #define GPIO_MCUN1INT1SET_MCUN1GPIO58_Pos (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
35243 #define GPIO_MCUN1INT1SET_MCUN1GPIO58_Msk (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35244 #define GPIO_MCUN1INT1SET_MCUN1GPIO57_Pos (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
35245 #define GPIO_MCUN1INT1SET_MCUN1GPIO57_Msk (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35246 #define GPIO_MCUN1INT1SET_MCUN1GPIO56_Pos (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
35247 #define GPIO_MCUN1INT1SET_MCUN1GPIO56_Msk (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35248 #define GPIO_MCUN1INT1SET_MCUN1GPIO55_Pos (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
35249 #define GPIO_MCUN1INT1SET_MCUN1GPIO55_Msk (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35250 #define GPIO_MCUN1INT1SET_MCUN1GPIO54_Pos (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
35251 #define GPIO_MCUN1INT1SET_MCUN1GPIO54_Msk (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35252 #define GPIO_MCUN1INT1SET_MCUN1GPIO53_Pos (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
35253 #define GPIO_MCUN1INT1SET_MCUN1GPIO53_Msk (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35254 #define GPIO_MCUN1INT1SET_MCUN1GPIO52_Pos (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
35255 #define GPIO_MCUN1INT1SET_MCUN1GPIO52_Msk (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35256 #define GPIO_MCUN1INT1SET_MCUN1GPIO51_Pos (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
35257 #define GPIO_MCUN1INT1SET_MCUN1GPIO51_Msk (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35258 #define GPIO_MCUN1INT1SET_MCUN1GPIO50_Pos (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
35259 #define GPIO_MCUN1INT1SET_MCUN1GPIO50_Msk (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35260 #define GPIO_MCUN1INT1SET_MCUN1GPIO49_Pos (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
35261 #define GPIO_MCUN1INT1SET_MCUN1GPIO49_Msk (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35262 #define GPIO_MCUN1INT1SET_MCUN1GPIO48_Pos (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
35263 #define GPIO_MCUN1INT1SET_MCUN1GPIO48_Msk (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35264 #define GPIO_MCUN1INT1SET_MCUN1GPIO47_Pos (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
35265 #define GPIO_MCUN1INT1SET_MCUN1GPIO47_Msk (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35266 #define GPIO_MCUN1INT1SET_MCUN1GPIO46_Pos (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
35267 #define GPIO_MCUN1INT1SET_MCUN1GPIO46_Msk (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35268 #define GPIO_MCUN1INT1SET_MCUN1GPIO45_Pos (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
35269 #define GPIO_MCUN1INT1SET_MCUN1GPIO45_Msk (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35270 #define GPIO_MCUN1INT1SET_MCUN1GPIO44_Pos (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
35271 #define GPIO_MCUN1INT1SET_MCUN1GPIO44_Msk (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35272 #define GPIO_MCUN1INT1SET_MCUN1GPIO43_Pos (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
35273 #define GPIO_MCUN1INT1SET_MCUN1GPIO43_Msk (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35274 #define GPIO_MCUN1INT1SET_MCUN1GPIO42_Pos (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
35275 #define GPIO_MCUN1INT1SET_MCUN1GPIO42_Msk (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35276 #define GPIO_MCUN1INT1SET_MCUN1GPIO41_Pos (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
35277 #define GPIO_MCUN1INT1SET_MCUN1GPIO41_Msk (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35278 #define GPIO_MCUN1INT1SET_MCUN1GPIO40_Pos (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
35279 #define GPIO_MCUN1INT1SET_MCUN1GPIO40_Msk (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35280 #define GPIO_MCUN1INT1SET_MCUN1GPIO39_Pos (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
35281 #define GPIO_MCUN1INT1SET_MCUN1GPIO39_Msk (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35282 #define GPIO_MCUN1INT1SET_MCUN1GPIO38_Pos (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
35283 #define GPIO_MCUN1INT1SET_MCUN1GPIO38_Msk (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35284 #define GPIO_MCUN1INT1SET_MCUN1GPIO37_Pos (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
35285 #define GPIO_MCUN1INT1SET_MCUN1GPIO37_Msk (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35286 #define GPIO_MCUN1INT1SET_MCUN1GPIO36_Pos (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
35287 #define GPIO_MCUN1INT1SET_MCUN1GPIO36_Msk (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35288 #define GPIO_MCUN1INT1SET_MCUN1GPIO35_Pos (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
35289 #define GPIO_MCUN1INT1SET_MCUN1GPIO35_Msk (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35290 #define GPIO_MCUN1INT1SET_MCUN1GPIO34_Pos (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
35291 #define GPIO_MCUN1INT1SET_MCUN1GPIO34_Msk (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35292 #define GPIO_MCUN1INT1SET_MCUN1GPIO33_Pos (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
35293 #define GPIO_MCUN1INT1SET_MCUN1GPIO33_Msk (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35294 #define GPIO_MCUN1INT1SET_MCUN1GPIO32_Pos (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
35295 #define GPIO_MCUN1INT1SET_MCUN1GPIO32_Msk (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35296 /* ======================================================  MCUN1INT2EN  ====================================================== */
35297 #define GPIO_MCUN1INT2EN_MCUN1GPIO95_Pos  (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
35298 #define GPIO_MCUN1INT2EN_MCUN1GPIO95_Msk  (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
35299 #define GPIO_MCUN1INT2EN_MCUN1GPIO94_Pos  (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
35300 #define GPIO_MCUN1INT2EN_MCUN1GPIO94_Msk  (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
35301 #define GPIO_MCUN1INT2EN_MCUN1GPIO93_Pos  (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
35302 #define GPIO_MCUN1INT2EN_MCUN1GPIO93_Msk  (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
35303 #define GPIO_MCUN1INT2EN_MCUN1GPIO92_Pos  (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
35304 #define GPIO_MCUN1INT2EN_MCUN1GPIO92_Msk  (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
35305 #define GPIO_MCUN1INT2EN_MCUN1GPIO91_Pos  (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
35306 #define GPIO_MCUN1INT2EN_MCUN1GPIO91_Msk  (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
35307 #define GPIO_MCUN1INT2EN_MCUN1GPIO90_Pos  (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
35308 #define GPIO_MCUN1INT2EN_MCUN1GPIO90_Msk  (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
35309 #define GPIO_MCUN1INT2EN_MCUN1GPIO89_Pos  (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
35310 #define GPIO_MCUN1INT2EN_MCUN1GPIO89_Msk  (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
35311 #define GPIO_MCUN1INT2EN_MCUN1GPIO88_Pos  (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
35312 #define GPIO_MCUN1INT2EN_MCUN1GPIO88_Msk  (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
35313 #define GPIO_MCUN1INT2EN_MCUN1GPIO87_Pos  (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
35314 #define GPIO_MCUN1INT2EN_MCUN1GPIO87_Msk  (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
35315 #define GPIO_MCUN1INT2EN_MCUN1GPIO86_Pos  (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
35316 #define GPIO_MCUN1INT2EN_MCUN1GPIO86_Msk  (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
35317 #define GPIO_MCUN1INT2EN_MCUN1GPIO85_Pos  (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
35318 #define GPIO_MCUN1INT2EN_MCUN1GPIO85_Msk  (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
35319 #define GPIO_MCUN1INT2EN_MCUN1GPIO84_Pos  (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
35320 #define GPIO_MCUN1INT2EN_MCUN1GPIO84_Msk  (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
35321 #define GPIO_MCUN1INT2EN_MCUN1GPIO83_Pos  (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
35322 #define GPIO_MCUN1INT2EN_MCUN1GPIO83_Msk  (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
35323 #define GPIO_MCUN1INT2EN_MCUN1GPIO82_Pos  (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
35324 #define GPIO_MCUN1INT2EN_MCUN1GPIO82_Msk  (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
35325 #define GPIO_MCUN1INT2EN_MCUN1GPIO81_Pos  (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
35326 #define GPIO_MCUN1INT2EN_MCUN1GPIO81_Msk  (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
35327 #define GPIO_MCUN1INT2EN_MCUN1GPIO80_Pos  (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
35328 #define GPIO_MCUN1INT2EN_MCUN1GPIO80_Msk  (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
35329 #define GPIO_MCUN1INT2EN_MCUN1GPIO79_Pos  (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
35330 #define GPIO_MCUN1INT2EN_MCUN1GPIO79_Msk  (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
35331 #define GPIO_MCUN1INT2EN_MCUN1GPIO78_Pos  (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
35332 #define GPIO_MCUN1INT2EN_MCUN1GPIO78_Msk  (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
35333 #define GPIO_MCUN1INT2EN_MCUN1GPIO77_Pos  (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
35334 #define GPIO_MCUN1INT2EN_MCUN1GPIO77_Msk  (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
35335 #define GPIO_MCUN1INT2EN_MCUN1GPIO76_Pos  (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
35336 #define GPIO_MCUN1INT2EN_MCUN1GPIO76_Msk  (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
35337 #define GPIO_MCUN1INT2EN_MCUN1GPIO75_Pos  (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
35338 #define GPIO_MCUN1INT2EN_MCUN1GPIO75_Msk  (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
35339 #define GPIO_MCUN1INT2EN_MCUN1GPIO74_Pos  (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
35340 #define GPIO_MCUN1INT2EN_MCUN1GPIO74_Msk  (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
35341 #define GPIO_MCUN1INT2EN_MCUN1GPIO73_Pos  (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
35342 #define GPIO_MCUN1INT2EN_MCUN1GPIO73_Msk  (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
35343 #define GPIO_MCUN1INT2EN_MCUN1GPIO72_Pos  (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
35344 #define GPIO_MCUN1INT2EN_MCUN1GPIO72_Msk  (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
35345 #define GPIO_MCUN1INT2EN_MCUN1GPIO71_Pos  (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
35346 #define GPIO_MCUN1INT2EN_MCUN1GPIO71_Msk  (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
35347 #define GPIO_MCUN1INT2EN_MCUN1GPIO70_Pos  (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
35348 #define GPIO_MCUN1INT2EN_MCUN1GPIO70_Msk  (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
35349 #define GPIO_MCUN1INT2EN_MCUN1GPIO69_Pos  (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
35350 #define GPIO_MCUN1INT2EN_MCUN1GPIO69_Msk  (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
35351 #define GPIO_MCUN1INT2EN_MCUN1GPIO68_Pos  (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
35352 #define GPIO_MCUN1INT2EN_MCUN1GPIO68_Msk  (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
35353 #define GPIO_MCUN1INT2EN_MCUN1GPIO67_Pos  (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
35354 #define GPIO_MCUN1INT2EN_MCUN1GPIO67_Msk  (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
35355 #define GPIO_MCUN1INT2EN_MCUN1GPIO66_Pos  (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
35356 #define GPIO_MCUN1INT2EN_MCUN1GPIO66_Msk  (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
35357 #define GPIO_MCUN1INT2EN_MCUN1GPIO65_Pos  (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
35358 #define GPIO_MCUN1INT2EN_MCUN1GPIO65_Msk  (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
35359 #define GPIO_MCUN1INT2EN_MCUN1GPIO64_Pos  (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
35360 #define GPIO_MCUN1INT2EN_MCUN1GPIO64_Msk  (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
35361 /* =====================================================  MCUN1INT2STAT  ===================================================== */
35362 #define GPIO_MCUN1INT2STAT_MCUN1GPIO95_Pos (31UL)                   /*!< MCUN1GPIO95 (Bit 31)                                  */
35363 #define GPIO_MCUN1INT2STAT_MCUN1GPIO95_Msk (0x80000000UL)           /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
35364 #define GPIO_MCUN1INT2STAT_MCUN1GPIO94_Pos (30UL)                   /*!< MCUN1GPIO94 (Bit 30)                                  */
35365 #define GPIO_MCUN1INT2STAT_MCUN1GPIO94_Msk (0x40000000UL)           /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
35366 #define GPIO_MCUN1INT2STAT_MCUN1GPIO93_Pos (29UL)                   /*!< MCUN1GPIO93 (Bit 29)                                  */
35367 #define GPIO_MCUN1INT2STAT_MCUN1GPIO93_Msk (0x20000000UL)           /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
35368 #define GPIO_MCUN1INT2STAT_MCUN1GPIO92_Pos (28UL)                   /*!< MCUN1GPIO92 (Bit 28)                                  */
35369 #define GPIO_MCUN1INT2STAT_MCUN1GPIO92_Msk (0x10000000UL)           /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
35370 #define GPIO_MCUN1INT2STAT_MCUN1GPIO91_Pos (27UL)                   /*!< MCUN1GPIO91 (Bit 27)                                  */
35371 #define GPIO_MCUN1INT2STAT_MCUN1GPIO91_Msk (0x8000000UL)            /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
35372 #define GPIO_MCUN1INT2STAT_MCUN1GPIO90_Pos (26UL)                   /*!< MCUN1GPIO90 (Bit 26)                                  */
35373 #define GPIO_MCUN1INT2STAT_MCUN1GPIO90_Msk (0x4000000UL)            /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
35374 #define GPIO_MCUN1INT2STAT_MCUN1GPIO89_Pos (25UL)                   /*!< MCUN1GPIO89 (Bit 25)                                  */
35375 #define GPIO_MCUN1INT2STAT_MCUN1GPIO89_Msk (0x2000000UL)            /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
35376 #define GPIO_MCUN1INT2STAT_MCUN1GPIO88_Pos (24UL)                   /*!< MCUN1GPIO88 (Bit 24)                                  */
35377 #define GPIO_MCUN1INT2STAT_MCUN1GPIO88_Msk (0x1000000UL)            /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
35378 #define GPIO_MCUN1INT2STAT_MCUN1GPIO87_Pos (23UL)                   /*!< MCUN1GPIO87 (Bit 23)                                  */
35379 #define GPIO_MCUN1INT2STAT_MCUN1GPIO87_Msk (0x800000UL)             /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
35380 #define GPIO_MCUN1INT2STAT_MCUN1GPIO86_Pos (22UL)                   /*!< MCUN1GPIO86 (Bit 22)                                  */
35381 #define GPIO_MCUN1INT2STAT_MCUN1GPIO86_Msk (0x400000UL)             /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
35382 #define GPIO_MCUN1INT2STAT_MCUN1GPIO85_Pos (21UL)                   /*!< MCUN1GPIO85 (Bit 21)                                  */
35383 #define GPIO_MCUN1INT2STAT_MCUN1GPIO85_Msk (0x200000UL)             /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
35384 #define GPIO_MCUN1INT2STAT_MCUN1GPIO84_Pos (20UL)                   /*!< MCUN1GPIO84 (Bit 20)                                  */
35385 #define GPIO_MCUN1INT2STAT_MCUN1GPIO84_Msk (0x100000UL)             /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
35386 #define GPIO_MCUN1INT2STAT_MCUN1GPIO83_Pos (19UL)                   /*!< MCUN1GPIO83 (Bit 19)                                  */
35387 #define GPIO_MCUN1INT2STAT_MCUN1GPIO83_Msk (0x80000UL)              /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
35388 #define GPIO_MCUN1INT2STAT_MCUN1GPIO82_Pos (18UL)                   /*!< MCUN1GPIO82 (Bit 18)                                  */
35389 #define GPIO_MCUN1INT2STAT_MCUN1GPIO82_Msk (0x40000UL)              /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
35390 #define GPIO_MCUN1INT2STAT_MCUN1GPIO81_Pos (17UL)                   /*!< MCUN1GPIO81 (Bit 17)                                  */
35391 #define GPIO_MCUN1INT2STAT_MCUN1GPIO81_Msk (0x20000UL)              /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
35392 #define GPIO_MCUN1INT2STAT_MCUN1GPIO80_Pos (16UL)                   /*!< MCUN1GPIO80 (Bit 16)                                  */
35393 #define GPIO_MCUN1INT2STAT_MCUN1GPIO80_Msk (0x10000UL)              /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
35394 #define GPIO_MCUN1INT2STAT_MCUN1GPIO79_Pos (15UL)                   /*!< MCUN1GPIO79 (Bit 15)                                  */
35395 #define GPIO_MCUN1INT2STAT_MCUN1GPIO79_Msk (0x8000UL)               /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
35396 #define GPIO_MCUN1INT2STAT_MCUN1GPIO78_Pos (14UL)                   /*!< MCUN1GPIO78 (Bit 14)                                  */
35397 #define GPIO_MCUN1INT2STAT_MCUN1GPIO78_Msk (0x4000UL)               /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
35398 #define GPIO_MCUN1INT2STAT_MCUN1GPIO77_Pos (13UL)                   /*!< MCUN1GPIO77 (Bit 13)                                  */
35399 #define GPIO_MCUN1INT2STAT_MCUN1GPIO77_Msk (0x2000UL)               /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
35400 #define GPIO_MCUN1INT2STAT_MCUN1GPIO76_Pos (12UL)                   /*!< MCUN1GPIO76 (Bit 12)                                  */
35401 #define GPIO_MCUN1INT2STAT_MCUN1GPIO76_Msk (0x1000UL)               /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
35402 #define GPIO_MCUN1INT2STAT_MCUN1GPIO75_Pos (11UL)                   /*!< MCUN1GPIO75 (Bit 11)                                  */
35403 #define GPIO_MCUN1INT2STAT_MCUN1GPIO75_Msk (0x800UL)                /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
35404 #define GPIO_MCUN1INT2STAT_MCUN1GPIO74_Pos (10UL)                   /*!< MCUN1GPIO74 (Bit 10)                                  */
35405 #define GPIO_MCUN1INT2STAT_MCUN1GPIO74_Msk (0x400UL)                /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
35406 #define GPIO_MCUN1INT2STAT_MCUN1GPIO73_Pos (9UL)                    /*!< MCUN1GPIO73 (Bit 9)                                   */
35407 #define GPIO_MCUN1INT2STAT_MCUN1GPIO73_Msk (0x200UL)                /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
35408 #define GPIO_MCUN1INT2STAT_MCUN1GPIO72_Pos (8UL)                    /*!< MCUN1GPIO72 (Bit 8)                                   */
35409 #define GPIO_MCUN1INT2STAT_MCUN1GPIO72_Msk (0x100UL)                /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
35410 #define GPIO_MCUN1INT2STAT_MCUN1GPIO71_Pos (7UL)                    /*!< MCUN1GPIO71 (Bit 7)                                   */
35411 #define GPIO_MCUN1INT2STAT_MCUN1GPIO71_Msk (0x80UL)                 /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
35412 #define GPIO_MCUN1INT2STAT_MCUN1GPIO70_Pos (6UL)                    /*!< MCUN1GPIO70 (Bit 6)                                   */
35413 #define GPIO_MCUN1INT2STAT_MCUN1GPIO70_Msk (0x40UL)                 /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
35414 #define GPIO_MCUN1INT2STAT_MCUN1GPIO69_Pos (5UL)                    /*!< MCUN1GPIO69 (Bit 5)                                   */
35415 #define GPIO_MCUN1INT2STAT_MCUN1GPIO69_Msk (0x20UL)                 /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
35416 #define GPIO_MCUN1INT2STAT_MCUN1GPIO68_Pos (4UL)                    /*!< MCUN1GPIO68 (Bit 4)                                   */
35417 #define GPIO_MCUN1INT2STAT_MCUN1GPIO68_Msk (0x10UL)                 /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
35418 #define GPIO_MCUN1INT2STAT_MCUN1GPIO67_Pos (3UL)                    /*!< MCUN1GPIO67 (Bit 3)                                   */
35419 #define GPIO_MCUN1INT2STAT_MCUN1GPIO67_Msk (0x8UL)                  /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
35420 #define GPIO_MCUN1INT2STAT_MCUN1GPIO66_Pos (2UL)                    /*!< MCUN1GPIO66 (Bit 2)                                   */
35421 #define GPIO_MCUN1INT2STAT_MCUN1GPIO66_Msk (0x4UL)                  /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
35422 #define GPIO_MCUN1INT2STAT_MCUN1GPIO65_Pos (1UL)                    /*!< MCUN1GPIO65 (Bit 1)                                   */
35423 #define GPIO_MCUN1INT2STAT_MCUN1GPIO65_Msk (0x2UL)                  /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
35424 #define GPIO_MCUN1INT2STAT_MCUN1GPIO64_Pos (0UL)                    /*!< MCUN1GPIO64 (Bit 0)                                   */
35425 #define GPIO_MCUN1INT2STAT_MCUN1GPIO64_Msk (0x1UL)                  /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
35426 /* =====================================================  MCUN1INT2CLR  ====================================================== */
35427 #define GPIO_MCUN1INT2CLR_MCUN1GPIO95_Pos (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
35428 #define GPIO_MCUN1INT2CLR_MCUN1GPIO95_Msk (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
35429 #define GPIO_MCUN1INT2CLR_MCUN1GPIO94_Pos (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
35430 #define GPIO_MCUN1INT2CLR_MCUN1GPIO94_Msk (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
35431 #define GPIO_MCUN1INT2CLR_MCUN1GPIO93_Pos (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
35432 #define GPIO_MCUN1INT2CLR_MCUN1GPIO93_Msk (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
35433 #define GPIO_MCUN1INT2CLR_MCUN1GPIO92_Pos (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
35434 #define GPIO_MCUN1INT2CLR_MCUN1GPIO92_Msk (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
35435 #define GPIO_MCUN1INT2CLR_MCUN1GPIO91_Pos (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
35436 #define GPIO_MCUN1INT2CLR_MCUN1GPIO91_Msk (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
35437 #define GPIO_MCUN1INT2CLR_MCUN1GPIO90_Pos (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
35438 #define GPIO_MCUN1INT2CLR_MCUN1GPIO90_Msk (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
35439 #define GPIO_MCUN1INT2CLR_MCUN1GPIO89_Pos (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
35440 #define GPIO_MCUN1INT2CLR_MCUN1GPIO89_Msk (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
35441 #define GPIO_MCUN1INT2CLR_MCUN1GPIO88_Pos (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
35442 #define GPIO_MCUN1INT2CLR_MCUN1GPIO88_Msk (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
35443 #define GPIO_MCUN1INT2CLR_MCUN1GPIO87_Pos (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
35444 #define GPIO_MCUN1INT2CLR_MCUN1GPIO87_Msk (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
35445 #define GPIO_MCUN1INT2CLR_MCUN1GPIO86_Pos (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
35446 #define GPIO_MCUN1INT2CLR_MCUN1GPIO86_Msk (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
35447 #define GPIO_MCUN1INT2CLR_MCUN1GPIO85_Pos (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
35448 #define GPIO_MCUN1INT2CLR_MCUN1GPIO85_Msk (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
35449 #define GPIO_MCUN1INT2CLR_MCUN1GPIO84_Pos (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
35450 #define GPIO_MCUN1INT2CLR_MCUN1GPIO84_Msk (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
35451 #define GPIO_MCUN1INT2CLR_MCUN1GPIO83_Pos (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
35452 #define GPIO_MCUN1INT2CLR_MCUN1GPIO83_Msk (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
35453 #define GPIO_MCUN1INT2CLR_MCUN1GPIO82_Pos (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
35454 #define GPIO_MCUN1INT2CLR_MCUN1GPIO82_Msk (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
35455 #define GPIO_MCUN1INT2CLR_MCUN1GPIO81_Pos (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
35456 #define GPIO_MCUN1INT2CLR_MCUN1GPIO81_Msk (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
35457 #define GPIO_MCUN1INT2CLR_MCUN1GPIO80_Pos (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
35458 #define GPIO_MCUN1INT2CLR_MCUN1GPIO80_Msk (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
35459 #define GPIO_MCUN1INT2CLR_MCUN1GPIO79_Pos (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
35460 #define GPIO_MCUN1INT2CLR_MCUN1GPIO79_Msk (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
35461 #define GPIO_MCUN1INT2CLR_MCUN1GPIO78_Pos (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
35462 #define GPIO_MCUN1INT2CLR_MCUN1GPIO78_Msk (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
35463 #define GPIO_MCUN1INT2CLR_MCUN1GPIO77_Pos (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
35464 #define GPIO_MCUN1INT2CLR_MCUN1GPIO77_Msk (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
35465 #define GPIO_MCUN1INT2CLR_MCUN1GPIO76_Pos (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
35466 #define GPIO_MCUN1INT2CLR_MCUN1GPIO76_Msk (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
35467 #define GPIO_MCUN1INT2CLR_MCUN1GPIO75_Pos (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
35468 #define GPIO_MCUN1INT2CLR_MCUN1GPIO75_Msk (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
35469 #define GPIO_MCUN1INT2CLR_MCUN1GPIO74_Pos (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
35470 #define GPIO_MCUN1INT2CLR_MCUN1GPIO74_Msk (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
35471 #define GPIO_MCUN1INT2CLR_MCUN1GPIO73_Pos (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
35472 #define GPIO_MCUN1INT2CLR_MCUN1GPIO73_Msk (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
35473 #define GPIO_MCUN1INT2CLR_MCUN1GPIO72_Pos (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
35474 #define GPIO_MCUN1INT2CLR_MCUN1GPIO72_Msk (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
35475 #define GPIO_MCUN1INT2CLR_MCUN1GPIO71_Pos (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
35476 #define GPIO_MCUN1INT2CLR_MCUN1GPIO71_Msk (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
35477 #define GPIO_MCUN1INT2CLR_MCUN1GPIO70_Pos (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
35478 #define GPIO_MCUN1INT2CLR_MCUN1GPIO70_Msk (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
35479 #define GPIO_MCUN1INT2CLR_MCUN1GPIO69_Pos (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
35480 #define GPIO_MCUN1INT2CLR_MCUN1GPIO69_Msk (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
35481 #define GPIO_MCUN1INT2CLR_MCUN1GPIO68_Pos (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
35482 #define GPIO_MCUN1INT2CLR_MCUN1GPIO68_Msk (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
35483 #define GPIO_MCUN1INT2CLR_MCUN1GPIO67_Pos (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
35484 #define GPIO_MCUN1INT2CLR_MCUN1GPIO67_Msk (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
35485 #define GPIO_MCUN1INT2CLR_MCUN1GPIO66_Pos (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
35486 #define GPIO_MCUN1INT2CLR_MCUN1GPIO66_Msk (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
35487 #define GPIO_MCUN1INT2CLR_MCUN1GPIO65_Pos (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
35488 #define GPIO_MCUN1INT2CLR_MCUN1GPIO65_Msk (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
35489 #define GPIO_MCUN1INT2CLR_MCUN1GPIO64_Pos (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
35490 #define GPIO_MCUN1INT2CLR_MCUN1GPIO64_Msk (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
35491 /* =====================================================  MCUN1INT2SET  ====================================================== */
35492 #define GPIO_MCUN1INT2SET_MCUN1GPIO95_Pos (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
35493 #define GPIO_MCUN1INT2SET_MCUN1GPIO95_Msk (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
35494 #define GPIO_MCUN1INT2SET_MCUN1GPIO94_Pos (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
35495 #define GPIO_MCUN1INT2SET_MCUN1GPIO94_Msk (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
35496 #define GPIO_MCUN1INT2SET_MCUN1GPIO93_Pos (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
35497 #define GPIO_MCUN1INT2SET_MCUN1GPIO93_Msk (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
35498 #define GPIO_MCUN1INT2SET_MCUN1GPIO92_Pos (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
35499 #define GPIO_MCUN1INT2SET_MCUN1GPIO92_Msk (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
35500 #define GPIO_MCUN1INT2SET_MCUN1GPIO91_Pos (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
35501 #define GPIO_MCUN1INT2SET_MCUN1GPIO91_Msk (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
35502 #define GPIO_MCUN1INT2SET_MCUN1GPIO90_Pos (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
35503 #define GPIO_MCUN1INT2SET_MCUN1GPIO90_Msk (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
35504 #define GPIO_MCUN1INT2SET_MCUN1GPIO89_Pos (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
35505 #define GPIO_MCUN1INT2SET_MCUN1GPIO89_Msk (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
35506 #define GPIO_MCUN1INT2SET_MCUN1GPIO88_Pos (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
35507 #define GPIO_MCUN1INT2SET_MCUN1GPIO88_Msk (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
35508 #define GPIO_MCUN1INT2SET_MCUN1GPIO87_Pos (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
35509 #define GPIO_MCUN1INT2SET_MCUN1GPIO87_Msk (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
35510 #define GPIO_MCUN1INT2SET_MCUN1GPIO86_Pos (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
35511 #define GPIO_MCUN1INT2SET_MCUN1GPIO86_Msk (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
35512 #define GPIO_MCUN1INT2SET_MCUN1GPIO85_Pos (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
35513 #define GPIO_MCUN1INT2SET_MCUN1GPIO85_Msk (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
35514 #define GPIO_MCUN1INT2SET_MCUN1GPIO84_Pos (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
35515 #define GPIO_MCUN1INT2SET_MCUN1GPIO84_Msk (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
35516 #define GPIO_MCUN1INT2SET_MCUN1GPIO83_Pos (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
35517 #define GPIO_MCUN1INT2SET_MCUN1GPIO83_Msk (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
35518 #define GPIO_MCUN1INT2SET_MCUN1GPIO82_Pos (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
35519 #define GPIO_MCUN1INT2SET_MCUN1GPIO82_Msk (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
35520 #define GPIO_MCUN1INT2SET_MCUN1GPIO81_Pos (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
35521 #define GPIO_MCUN1INT2SET_MCUN1GPIO81_Msk (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
35522 #define GPIO_MCUN1INT2SET_MCUN1GPIO80_Pos (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
35523 #define GPIO_MCUN1INT2SET_MCUN1GPIO80_Msk (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
35524 #define GPIO_MCUN1INT2SET_MCUN1GPIO79_Pos (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
35525 #define GPIO_MCUN1INT2SET_MCUN1GPIO79_Msk (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
35526 #define GPIO_MCUN1INT2SET_MCUN1GPIO78_Pos (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
35527 #define GPIO_MCUN1INT2SET_MCUN1GPIO78_Msk (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
35528 #define GPIO_MCUN1INT2SET_MCUN1GPIO77_Pos (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
35529 #define GPIO_MCUN1INT2SET_MCUN1GPIO77_Msk (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
35530 #define GPIO_MCUN1INT2SET_MCUN1GPIO76_Pos (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
35531 #define GPIO_MCUN1INT2SET_MCUN1GPIO76_Msk (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
35532 #define GPIO_MCUN1INT2SET_MCUN1GPIO75_Pos (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
35533 #define GPIO_MCUN1INT2SET_MCUN1GPIO75_Msk (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
35534 #define GPIO_MCUN1INT2SET_MCUN1GPIO74_Pos (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
35535 #define GPIO_MCUN1INT2SET_MCUN1GPIO74_Msk (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
35536 #define GPIO_MCUN1INT2SET_MCUN1GPIO73_Pos (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
35537 #define GPIO_MCUN1INT2SET_MCUN1GPIO73_Msk (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
35538 #define GPIO_MCUN1INT2SET_MCUN1GPIO72_Pos (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
35539 #define GPIO_MCUN1INT2SET_MCUN1GPIO72_Msk (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
35540 #define GPIO_MCUN1INT2SET_MCUN1GPIO71_Pos (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
35541 #define GPIO_MCUN1INT2SET_MCUN1GPIO71_Msk (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
35542 #define GPIO_MCUN1INT2SET_MCUN1GPIO70_Pos (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
35543 #define GPIO_MCUN1INT2SET_MCUN1GPIO70_Msk (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
35544 #define GPIO_MCUN1INT2SET_MCUN1GPIO69_Pos (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
35545 #define GPIO_MCUN1INT2SET_MCUN1GPIO69_Msk (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
35546 #define GPIO_MCUN1INT2SET_MCUN1GPIO68_Pos (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
35547 #define GPIO_MCUN1INT2SET_MCUN1GPIO68_Msk (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
35548 #define GPIO_MCUN1INT2SET_MCUN1GPIO67_Pos (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
35549 #define GPIO_MCUN1INT2SET_MCUN1GPIO67_Msk (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
35550 #define GPIO_MCUN1INT2SET_MCUN1GPIO66_Pos (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
35551 #define GPIO_MCUN1INT2SET_MCUN1GPIO66_Msk (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
35552 #define GPIO_MCUN1INT2SET_MCUN1GPIO65_Pos (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
35553 #define GPIO_MCUN1INT2SET_MCUN1GPIO65_Msk (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
35554 #define GPIO_MCUN1INT2SET_MCUN1GPIO64_Pos (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
35555 #define GPIO_MCUN1INT2SET_MCUN1GPIO64_Msk (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
35556 /* ======================================================  MCUN1INT3EN  ====================================================== */
35557 #define GPIO_MCUN1INT3EN_MCUN1GPIO127_Pos (31UL)                    /*!< MCUN1GPIO127 (Bit 31)                                 */
35558 #define GPIO_MCUN1INT3EN_MCUN1GPIO127_Msk (0x80000000UL)            /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
35559 #define GPIO_MCUN1INT3EN_MCUN1GPIO126_Pos (30UL)                    /*!< MCUN1GPIO126 (Bit 30)                                 */
35560 #define GPIO_MCUN1INT3EN_MCUN1GPIO126_Msk (0x40000000UL)            /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
35561 #define GPIO_MCUN1INT3EN_MCUN1GPIO125_Pos (29UL)                    /*!< MCUN1GPIO125 (Bit 29)                                 */
35562 #define GPIO_MCUN1INT3EN_MCUN1GPIO125_Msk (0x20000000UL)            /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
35563 #define GPIO_MCUN1INT3EN_MCUN1GPIO124_Pos (28UL)                    /*!< MCUN1GPIO124 (Bit 28)                                 */
35564 #define GPIO_MCUN1INT3EN_MCUN1GPIO124_Msk (0x10000000UL)            /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
35565 #define GPIO_MCUN1INT3EN_MCUN1GPIO123_Pos (27UL)                    /*!< MCUN1GPIO123 (Bit 27)                                 */
35566 #define GPIO_MCUN1INT3EN_MCUN1GPIO123_Msk (0x8000000UL)             /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
35567 #define GPIO_MCUN1INT3EN_MCUN1GPIO122_Pos (26UL)                    /*!< MCUN1GPIO122 (Bit 26)                                 */
35568 #define GPIO_MCUN1INT3EN_MCUN1GPIO122_Msk (0x4000000UL)             /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
35569 #define GPIO_MCUN1INT3EN_MCUN1GPIO121_Pos (25UL)                    /*!< MCUN1GPIO121 (Bit 25)                                 */
35570 #define GPIO_MCUN1INT3EN_MCUN1GPIO121_Msk (0x2000000UL)             /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
35571 #define GPIO_MCUN1INT3EN_MCUN1GPIO120_Pos (24UL)                    /*!< MCUN1GPIO120 (Bit 24)                                 */
35572 #define GPIO_MCUN1INT3EN_MCUN1GPIO120_Msk (0x1000000UL)             /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
35573 #define GPIO_MCUN1INT3EN_MCUN1GPIO119_Pos (23UL)                    /*!< MCUN1GPIO119 (Bit 23)                                 */
35574 #define GPIO_MCUN1INT3EN_MCUN1GPIO119_Msk (0x800000UL)              /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
35575 #define GPIO_MCUN1INT3EN_MCUN1GPIO118_Pos (22UL)                    /*!< MCUN1GPIO118 (Bit 22)                                 */
35576 #define GPIO_MCUN1INT3EN_MCUN1GPIO118_Msk (0x400000UL)              /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
35577 #define GPIO_MCUN1INT3EN_MCUN1GPIO117_Pos (21UL)                    /*!< MCUN1GPIO117 (Bit 21)                                 */
35578 #define GPIO_MCUN1INT3EN_MCUN1GPIO117_Msk (0x200000UL)              /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
35579 #define GPIO_MCUN1INT3EN_MCUN1GPIO116_Pos (20UL)                    /*!< MCUN1GPIO116 (Bit 20)                                 */
35580 #define GPIO_MCUN1INT3EN_MCUN1GPIO116_Msk (0x100000UL)              /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
35581 #define GPIO_MCUN1INT3EN_MCUN1GPIO115_Pos (19UL)                    /*!< MCUN1GPIO115 (Bit 19)                                 */
35582 #define GPIO_MCUN1INT3EN_MCUN1GPIO115_Msk (0x80000UL)               /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
35583 #define GPIO_MCUN1INT3EN_MCUN1GPIO114_Pos (18UL)                    /*!< MCUN1GPIO114 (Bit 18)                                 */
35584 #define GPIO_MCUN1INT3EN_MCUN1GPIO114_Msk (0x40000UL)               /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
35585 #define GPIO_MCUN1INT3EN_MCUN1GPIO113_Pos (17UL)                    /*!< MCUN1GPIO113 (Bit 17)                                 */
35586 #define GPIO_MCUN1INT3EN_MCUN1GPIO113_Msk (0x20000UL)               /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
35587 #define GPIO_MCUN1INT3EN_MCUN1GPIO112_Pos (16UL)                    /*!< MCUN1GPIO112 (Bit 16)                                 */
35588 #define GPIO_MCUN1INT3EN_MCUN1GPIO112_Msk (0x10000UL)               /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
35589 #define GPIO_MCUN1INT3EN_MCUN1GPIO111_Pos (15UL)                    /*!< MCUN1GPIO111 (Bit 15)                                 */
35590 #define GPIO_MCUN1INT3EN_MCUN1GPIO111_Msk (0x8000UL)                /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
35591 #define GPIO_MCUN1INT3EN_MCUN1GPIO110_Pos (14UL)                    /*!< MCUN1GPIO110 (Bit 14)                                 */
35592 #define GPIO_MCUN1INT3EN_MCUN1GPIO110_Msk (0x4000UL)                /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
35593 #define GPIO_MCUN1INT3EN_MCUN1GPIO109_Pos (13UL)                    /*!< MCUN1GPIO109 (Bit 13)                                 */
35594 #define GPIO_MCUN1INT3EN_MCUN1GPIO109_Msk (0x2000UL)                /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
35595 #define GPIO_MCUN1INT3EN_MCUN1GPIO108_Pos (12UL)                    /*!< MCUN1GPIO108 (Bit 12)                                 */
35596 #define GPIO_MCUN1INT3EN_MCUN1GPIO108_Msk (0x1000UL)                /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
35597 #define GPIO_MCUN1INT3EN_MCUN1GPIO107_Pos (11UL)                    /*!< MCUN1GPIO107 (Bit 11)                                 */
35598 #define GPIO_MCUN1INT3EN_MCUN1GPIO107_Msk (0x800UL)                 /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
35599 #define GPIO_MCUN1INT3EN_MCUN1GPIO106_Pos (10UL)                    /*!< MCUN1GPIO106 (Bit 10)                                 */
35600 #define GPIO_MCUN1INT3EN_MCUN1GPIO106_Msk (0x400UL)                 /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
35601 #define GPIO_MCUN1INT3EN_MCUN1GPIO105_Pos (9UL)                     /*!< MCUN1GPIO105 (Bit 9)                                  */
35602 #define GPIO_MCUN1INT3EN_MCUN1GPIO105_Msk (0x200UL)                 /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
35603 #define GPIO_MCUN1INT3EN_MCUN1GPIO104_Pos (8UL)                     /*!< MCUN1GPIO104 (Bit 8)                                  */
35604 #define GPIO_MCUN1INT3EN_MCUN1GPIO104_Msk (0x100UL)                 /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
35605 #define GPIO_MCUN1INT3EN_MCUN1GPIO103_Pos (7UL)                     /*!< MCUN1GPIO103 (Bit 7)                                  */
35606 #define GPIO_MCUN1INT3EN_MCUN1GPIO103_Msk (0x80UL)                  /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
35607 #define GPIO_MCUN1INT3EN_MCUN1GPIO102_Pos (6UL)                     /*!< MCUN1GPIO102 (Bit 6)                                  */
35608 #define GPIO_MCUN1INT3EN_MCUN1GPIO102_Msk (0x40UL)                  /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
35609 #define GPIO_MCUN1INT3EN_MCUN1GPIO101_Pos (5UL)                     /*!< MCUN1GPIO101 (Bit 5)                                  */
35610 #define GPIO_MCUN1INT3EN_MCUN1GPIO101_Msk (0x20UL)                  /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
35611 #define GPIO_MCUN1INT3EN_MCUN1GPIO100_Pos (4UL)                     /*!< MCUN1GPIO100 (Bit 4)                                  */
35612 #define GPIO_MCUN1INT3EN_MCUN1GPIO100_Msk (0x10UL)                  /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
35613 #define GPIO_MCUN1INT3EN_MCUN1GPIO99_Pos  (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
35614 #define GPIO_MCUN1INT3EN_MCUN1GPIO99_Msk  (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
35615 #define GPIO_MCUN1INT3EN_MCUN1GPIO98_Pos  (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
35616 #define GPIO_MCUN1INT3EN_MCUN1GPIO98_Msk  (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
35617 #define GPIO_MCUN1INT3EN_MCUN1GPIO97_Pos  (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
35618 #define GPIO_MCUN1INT3EN_MCUN1GPIO97_Msk  (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
35619 #define GPIO_MCUN1INT3EN_MCUN1GPIO96_Pos  (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
35620 #define GPIO_MCUN1INT3EN_MCUN1GPIO96_Msk  (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
35621 /* =====================================================  MCUN1INT3STAT  ===================================================== */
35622 #define GPIO_MCUN1INT3STAT_MCUN1GPIO127_Pos (31UL)                  /*!< MCUN1GPIO127 (Bit 31)                                 */
35623 #define GPIO_MCUN1INT3STAT_MCUN1GPIO127_Msk (0x80000000UL)          /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
35624 #define GPIO_MCUN1INT3STAT_MCUN1GPIO126_Pos (30UL)                  /*!< MCUN1GPIO126 (Bit 30)                                 */
35625 #define GPIO_MCUN1INT3STAT_MCUN1GPIO126_Msk (0x40000000UL)          /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
35626 #define GPIO_MCUN1INT3STAT_MCUN1GPIO125_Pos (29UL)                  /*!< MCUN1GPIO125 (Bit 29)                                 */
35627 #define GPIO_MCUN1INT3STAT_MCUN1GPIO125_Msk (0x20000000UL)          /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
35628 #define GPIO_MCUN1INT3STAT_MCUN1GPIO124_Pos (28UL)                  /*!< MCUN1GPIO124 (Bit 28)                                 */
35629 #define GPIO_MCUN1INT3STAT_MCUN1GPIO124_Msk (0x10000000UL)          /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
35630 #define GPIO_MCUN1INT3STAT_MCUN1GPIO123_Pos (27UL)                  /*!< MCUN1GPIO123 (Bit 27)                                 */
35631 #define GPIO_MCUN1INT3STAT_MCUN1GPIO123_Msk (0x8000000UL)           /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
35632 #define GPIO_MCUN1INT3STAT_MCUN1GPIO122_Pos (26UL)                  /*!< MCUN1GPIO122 (Bit 26)                                 */
35633 #define GPIO_MCUN1INT3STAT_MCUN1GPIO122_Msk (0x4000000UL)           /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
35634 #define GPIO_MCUN1INT3STAT_MCUN1GPIO121_Pos (25UL)                  /*!< MCUN1GPIO121 (Bit 25)                                 */
35635 #define GPIO_MCUN1INT3STAT_MCUN1GPIO121_Msk (0x2000000UL)           /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
35636 #define GPIO_MCUN1INT3STAT_MCUN1GPIO120_Pos (24UL)                  /*!< MCUN1GPIO120 (Bit 24)                                 */
35637 #define GPIO_MCUN1INT3STAT_MCUN1GPIO120_Msk (0x1000000UL)           /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
35638 #define GPIO_MCUN1INT3STAT_MCUN1GPIO119_Pos (23UL)                  /*!< MCUN1GPIO119 (Bit 23)                                 */
35639 #define GPIO_MCUN1INT3STAT_MCUN1GPIO119_Msk (0x800000UL)            /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
35640 #define GPIO_MCUN1INT3STAT_MCUN1GPIO118_Pos (22UL)                  /*!< MCUN1GPIO118 (Bit 22)                                 */
35641 #define GPIO_MCUN1INT3STAT_MCUN1GPIO118_Msk (0x400000UL)            /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
35642 #define GPIO_MCUN1INT3STAT_MCUN1GPIO117_Pos (21UL)                  /*!< MCUN1GPIO117 (Bit 21)                                 */
35643 #define GPIO_MCUN1INT3STAT_MCUN1GPIO117_Msk (0x200000UL)            /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
35644 #define GPIO_MCUN1INT3STAT_MCUN1GPIO116_Pos (20UL)                  /*!< MCUN1GPIO116 (Bit 20)                                 */
35645 #define GPIO_MCUN1INT3STAT_MCUN1GPIO116_Msk (0x100000UL)            /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
35646 #define GPIO_MCUN1INT3STAT_MCUN1GPIO115_Pos (19UL)                  /*!< MCUN1GPIO115 (Bit 19)                                 */
35647 #define GPIO_MCUN1INT3STAT_MCUN1GPIO115_Msk (0x80000UL)             /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
35648 #define GPIO_MCUN1INT3STAT_MCUN1GPIO114_Pos (18UL)                  /*!< MCUN1GPIO114 (Bit 18)                                 */
35649 #define GPIO_MCUN1INT3STAT_MCUN1GPIO114_Msk (0x40000UL)             /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
35650 #define GPIO_MCUN1INT3STAT_MCUN1GPIO113_Pos (17UL)                  /*!< MCUN1GPIO113 (Bit 17)                                 */
35651 #define GPIO_MCUN1INT3STAT_MCUN1GPIO113_Msk (0x20000UL)             /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
35652 #define GPIO_MCUN1INT3STAT_MCUN1GPIO112_Pos (16UL)                  /*!< MCUN1GPIO112 (Bit 16)                                 */
35653 #define GPIO_MCUN1INT3STAT_MCUN1GPIO112_Msk (0x10000UL)             /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
35654 #define GPIO_MCUN1INT3STAT_MCUN1GPIO111_Pos (15UL)                  /*!< MCUN1GPIO111 (Bit 15)                                 */
35655 #define GPIO_MCUN1INT3STAT_MCUN1GPIO111_Msk (0x8000UL)              /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
35656 #define GPIO_MCUN1INT3STAT_MCUN1GPIO110_Pos (14UL)                  /*!< MCUN1GPIO110 (Bit 14)                                 */
35657 #define GPIO_MCUN1INT3STAT_MCUN1GPIO110_Msk (0x4000UL)              /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
35658 #define GPIO_MCUN1INT3STAT_MCUN1GPIO109_Pos (13UL)                  /*!< MCUN1GPIO109 (Bit 13)                                 */
35659 #define GPIO_MCUN1INT3STAT_MCUN1GPIO109_Msk (0x2000UL)              /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
35660 #define GPIO_MCUN1INT3STAT_MCUN1GPIO108_Pos (12UL)                  /*!< MCUN1GPIO108 (Bit 12)                                 */
35661 #define GPIO_MCUN1INT3STAT_MCUN1GPIO108_Msk (0x1000UL)              /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
35662 #define GPIO_MCUN1INT3STAT_MCUN1GPIO107_Pos (11UL)                  /*!< MCUN1GPIO107 (Bit 11)                                 */
35663 #define GPIO_MCUN1INT3STAT_MCUN1GPIO107_Msk (0x800UL)               /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
35664 #define GPIO_MCUN1INT3STAT_MCUN1GPIO106_Pos (10UL)                  /*!< MCUN1GPIO106 (Bit 10)                                 */
35665 #define GPIO_MCUN1INT3STAT_MCUN1GPIO106_Msk (0x400UL)               /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
35666 #define GPIO_MCUN1INT3STAT_MCUN1GPIO105_Pos (9UL)                   /*!< MCUN1GPIO105 (Bit 9)                                  */
35667 #define GPIO_MCUN1INT3STAT_MCUN1GPIO105_Msk (0x200UL)               /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
35668 #define GPIO_MCUN1INT3STAT_MCUN1GPIO104_Pos (8UL)                   /*!< MCUN1GPIO104 (Bit 8)                                  */
35669 #define GPIO_MCUN1INT3STAT_MCUN1GPIO104_Msk (0x100UL)               /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
35670 #define GPIO_MCUN1INT3STAT_MCUN1GPIO103_Pos (7UL)                   /*!< MCUN1GPIO103 (Bit 7)                                  */
35671 #define GPIO_MCUN1INT3STAT_MCUN1GPIO103_Msk (0x80UL)                /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
35672 #define GPIO_MCUN1INT3STAT_MCUN1GPIO102_Pos (6UL)                   /*!< MCUN1GPIO102 (Bit 6)                                  */
35673 #define GPIO_MCUN1INT3STAT_MCUN1GPIO102_Msk (0x40UL)                /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
35674 #define GPIO_MCUN1INT3STAT_MCUN1GPIO101_Pos (5UL)                   /*!< MCUN1GPIO101 (Bit 5)                                  */
35675 #define GPIO_MCUN1INT3STAT_MCUN1GPIO101_Msk (0x20UL)                /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
35676 #define GPIO_MCUN1INT3STAT_MCUN1GPIO100_Pos (4UL)                   /*!< MCUN1GPIO100 (Bit 4)                                  */
35677 #define GPIO_MCUN1INT3STAT_MCUN1GPIO100_Msk (0x10UL)                /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
35678 #define GPIO_MCUN1INT3STAT_MCUN1GPIO99_Pos (3UL)                    /*!< MCUN1GPIO99 (Bit 3)                                   */
35679 #define GPIO_MCUN1INT3STAT_MCUN1GPIO99_Msk (0x8UL)                  /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
35680 #define GPIO_MCUN1INT3STAT_MCUN1GPIO98_Pos (2UL)                    /*!< MCUN1GPIO98 (Bit 2)                                   */
35681 #define GPIO_MCUN1INT3STAT_MCUN1GPIO98_Msk (0x4UL)                  /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
35682 #define GPIO_MCUN1INT3STAT_MCUN1GPIO97_Pos (1UL)                    /*!< MCUN1GPIO97 (Bit 1)                                   */
35683 #define GPIO_MCUN1INT3STAT_MCUN1GPIO97_Msk (0x2UL)                  /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
35684 #define GPIO_MCUN1INT3STAT_MCUN1GPIO96_Pos (0UL)                    /*!< MCUN1GPIO96 (Bit 0)                                   */
35685 #define GPIO_MCUN1INT3STAT_MCUN1GPIO96_Msk (0x1UL)                  /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
35686 /* =====================================================  MCUN1INT3CLR  ====================================================== */
35687 #define GPIO_MCUN1INT3CLR_MCUN1GPIO127_Pos (31UL)                   /*!< MCUN1GPIO127 (Bit 31)                                 */
35688 #define GPIO_MCUN1INT3CLR_MCUN1GPIO127_Msk (0x80000000UL)           /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
35689 #define GPIO_MCUN1INT3CLR_MCUN1GPIO126_Pos (30UL)                   /*!< MCUN1GPIO126 (Bit 30)                                 */
35690 #define GPIO_MCUN1INT3CLR_MCUN1GPIO126_Msk (0x40000000UL)           /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
35691 #define GPIO_MCUN1INT3CLR_MCUN1GPIO125_Pos (29UL)                   /*!< MCUN1GPIO125 (Bit 29)                                 */
35692 #define GPIO_MCUN1INT3CLR_MCUN1GPIO125_Msk (0x20000000UL)           /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
35693 #define GPIO_MCUN1INT3CLR_MCUN1GPIO124_Pos (28UL)                   /*!< MCUN1GPIO124 (Bit 28)                                 */
35694 #define GPIO_MCUN1INT3CLR_MCUN1GPIO124_Msk (0x10000000UL)           /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
35695 #define GPIO_MCUN1INT3CLR_MCUN1GPIO123_Pos (27UL)                   /*!< MCUN1GPIO123 (Bit 27)                                 */
35696 #define GPIO_MCUN1INT3CLR_MCUN1GPIO123_Msk (0x8000000UL)            /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
35697 #define GPIO_MCUN1INT3CLR_MCUN1GPIO122_Pos (26UL)                   /*!< MCUN1GPIO122 (Bit 26)                                 */
35698 #define GPIO_MCUN1INT3CLR_MCUN1GPIO122_Msk (0x4000000UL)            /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
35699 #define GPIO_MCUN1INT3CLR_MCUN1GPIO121_Pos (25UL)                   /*!< MCUN1GPIO121 (Bit 25)                                 */
35700 #define GPIO_MCUN1INT3CLR_MCUN1GPIO121_Msk (0x2000000UL)            /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
35701 #define GPIO_MCUN1INT3CLR_MCUN1GPIO120_Pos (24UL)                   /*!< MCUN1GPIO120 (Bit 24)                                 */
35702 #define GPIO_MCUN1INT3CLR_MCUN1GPIO120_Msk (0x1000000UL)            /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
35703 #define GPIO_MCUN1INT3CLR_MCUN1GPIO119_Pos (23UL)                   /*!< MCUN1GPIO119 (Bit 23)                                 */
35704 #define GPIO_MCUN1INT3CLR_MCUN1GPIO119_Msk (0x800000UL)             /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
35705 #define GPIO_MCUN1INT3CLR_MCUN1GPIO118_Pos (22UL)                   /*!< MCUN1GPIO118 (Bit 22)                                 */
35706 #define GPIO_MCUN1INT3CLR_MCUN1GPIO118_Msk (0x400000UL)             /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
35707 #define GPIO_MCUN1INT3CLR_MCUN1GPIO117_Pos (21UL)                   /*!< MCUN1GPIO117 (Bit 21)                                 */
35708 #define GPIO_MCUN1INT3CLR_MCUN1GPIO117_Msk (0x200000UL)             /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
35709 #define GPIO_MCUN1INT3CLR_MCUN1GPIO116_Pos (20UL)                   /*!< MCUN1GPIO116 (Bit 20)                                 */
35710 #define GPIO_MCUN1INT3CLR_MCUN1GPIO116_Msk (0x100000UL)             /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
35711 #define GPIO_MCUN1INT3CLR_MCUN1GPIO115_Pos (19UL)                   /*!< MCUN1GPIO115 (Bit 19)                                 */
35712 #define GPIO_MCUN1INT3CLR_MCUN1GPIO115_Msk (0x80000UL)              /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
35713 #define GPIO_MCUN1INT3CLR_MCUN1GPIO114_Pos (18UL)                   /*!< MCUN1GPIO114 (Bit 18)                                 */
35714 #define GPIO_MCUN1INT3CLR_MCUN1GPIO114_Msk (0x40000UL)              /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
35715 #define GPIO_MCUN1INT3CLR_MCUN1GPIO113_Pos (17UL)                   /*!< MCUN1GPIO113 (Bit 17)                                 */
35716 #define GPIO_MCUN1INT3CLR_MCUN1GPIO113_Msk (0x20000UL)              /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
35717 #define GPIO_MCUN1INT3CLR_MCUN1GPIO112_Pos (16UL)                   /*!< MCUN1GPIO112 (Bit 16)                                 */
35718 #define GPIO_MCUN1INT3CLR_MCUN1GPIO112_Msk (0x10000UL)              /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
35719 #define GPIO_MCUN1INT3CLR_MCUN1GPIO111_Pos (15UL)                   /*!< MCUN1GPIO111 (Bit 15)                                 */
35720 #define GPIO_MCUN1INT3CLR_MCUN1GPIO111_Msk (0x8000UL)               /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
35721 #define GPIO_MCUN1INT3CLR_MCUN1GPIO110_Pos (14UL)                   /*!< MCUN1GPIO110 (Bit 14)                                 */
35722 #define GPIO_MCUN1INT3CLR_MCUN1GPIO110_Msk (0x4000UL)               /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
35723 #define GPIO_MCUN1INT3CLR_MCUN1GPIO109_Pos (13UL)                   /*!< MCUN1GPIO109 (Bit 13)                                 */
35724 #define GPIO_MCUN1INT3CLR_MCUN1GPIO109_Msk (0x2000UL)               /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
35725 #define GPIO_MCUN1INT3CLR_MCUN1GPIO108_Pos (12UL)                   /*!< MCUN1GPIO108 (Bit 12)                                 */
35726 #define GPIO_MCUN1INT3CLR_MCUN1GPIO108_Msk (0x1000UL)               /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
35727 #define GPIO_MCUN1INT3CLR_MCUN1GPIO107_Pos (11UL)                   /*!< MCUN1GPIO107 (Bit 11)                                 */
35728 #define GPIO_MCUN1INT3CLR_MCUN1GPIO107_Msk (0x800UL)                /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
35729 #define GPIO_MCUN1INT3CLR_MCUN1GPIO106_Pos (10UL)                   /*!< MCUN1GPIO106 (Bit 10)                                 */
35730 #define GPIO_MCUN1INT3CLR_MCUN1GPIO106_Msk (0x400UL)                /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
35731 #define GPIO_MCUN1INT3CLR_MCUN1GPIO105_Pos (9UL)                    /*!< MCUN1GPIO105 (Bit 9)                                  */
35732 #define GPIO_MCUN1INT3CLR_MCUN1GPIO105_Msk (0x200UL)                /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
35733 #define GPIO_MCUN1INT3CLR_MCUN1GPIO104_Pos (8UL)                    /*!< MCUN1GPIO104 (Bit 8)                                  */
35734 #define GPIO_MCUN1INT3CLR_MCUN1GPIO104_Msk (0x100UL)                /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
35735 #define GPIO_MCUN1INT3CLR_MCUN1GPIO103_Pos (7UL)                    /*!< MCUN1GPIO103 (Bit 7)                                  */
35736 #define GPIO_MCUN1INT3CLR_MCUN1GPIO103_Msk (0x80UL)                 /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
35737 #define GPIO_MCUN1INT3CLR_MCUN1GPIO102_Pos (6UL)                    /*!< MCUN1GPIO102 (Bit 6)                                  */
35738 #define GPIO_MCUN1INT3CLR_MCUN1GPIO102_Msk (0x40UL)                 /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
35739 #define GPIO_MCUN1INT3CLR_MCUN1GPIO101_Pos (5UL)                    /*!< MCUN1GPIO101 (Bit 5)                                  */
35740 #define GPIO_MCUN1INT3CLR_MCUN1GPIO101_Msk (0x20UL)                 /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
35741 #define GPIO_MCUN1INT3CLR_MCUN1GPIO100_Pos (4UL)                    /*!< MCUN1GPIO100 (Bit 4)                                  */
35742 #define GPIO_MCUN1INT3CLR_MCUN1GPIO100_Msk (0x10UL)                 /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
35743 #define GPIO_MCUN1INT3CLR_MCUN1GPIO99_Pos (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
35744 #define GPIO_MCUN1INT3CLR_MCUN1GPIO99_Msk (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
35745 #define GPIO_MCUN1INT3CLR_MCUN1GPIO98_Pos (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
35746 #define GPIO_MCUN1INT3CLR_MCUN1GPIO98_Msk (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
35747 #define GPIO_MCUN1INT3CLR_MCUN1GPIO97_Pos (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
35748 #define GPIO_MCUN1INT3CLR_MCUN1GPIO97_Msk (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
35749 #define GPIO_MCUN1INT3CLR_MCUN1GPIO96_Pos (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
35750 #define GPIO_MCUN1INT3CLR_MCUN1GPIO96_Msk (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
35751 /* =====================================================  MCUN1INT3SET  ====================================================== */
35752 #define GPIO_MCUN1INT3SET_MCUN1GPIO127_Pos (31UL)                   /*!< MCUN1GPIO127 (Bit 31)                                 */
35753 #define GPIO_MCUN1INT3SET_MCUN1GPIO127_Msk (0x80000000UL)           /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
35754 #define GPIO_MCUN1INT3SET_MCUN1GPIO126_Pos (30UL)                   /*!< MCUN1GPIO126 (Bit 30)                                 */
35755 #define GPIO_MCUN1INT3SET_MCUN1GPIO126_Msk (0x40000000UL)           /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
35756 #define GPIO_MCUN1INT3SET_MCUN1GPIO125_Pos (29UL)                   /*!< MCUN1GPIO125 (Bit 29)                                 */
35757 #define GPIO_MCUN1INT3SET_MCUN1GPIO125_Msk (0x20000000UL)           /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
35758 #define GPIO_MCUN1INT3SET_MCUN1GPIO124_Pos (28UL)                   /*!< MCUN1GPIO124 (Bit 28)                                 */
35759 #define GPIO_MCUN1INT3SET_MCUN1GPIO124_Msk (0x10000000UL)           /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
35760 #define GPIO_MCUN1INT3SET_MCUN1GPIO123_Pos (27UL)                   /*!< MCUN1GPIO123 (Bit 27)                                 */
35761 #define GPIO_MCUN1INT3SET_MCUN1GPIO123_Msk (0x8000000UL)            /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
35762 #define GPIO_MCUN1INT3SET_MCUN1GPIO122_Pos (26UL)                   /*!< MCUN1GPIO122 (Bit 26)                                 */
35763 #define GPIO_MCUN1INT3SET_MCUN1GPIO122_Msk (0x4000000UL)            /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
35764 #define GPIO_MCUN1INT3SET_MCUN1GPIO121_Pos (25UL)                   /*!< MCUN1GPIO121 (Bit 25)                                 */
35765 #define GPIO_MCUN1INT3SET_MCUN1GPIO121_Msk (0x2000000UL)            /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
35766 #define GPIO_MCUN1INT3SET_MCUN1GPIO120_Pos (24UL)                   /*!< MCUN1GPIO120 (Bit 24)                                 */
35767 #define GPIO_MCUN1INT3SET_MCUN1GPIO120_Msk (0x1000000UL)            /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
35768 #define GPIO_MCUN1INT3SET_MCUN1GPIO119_Pos (23UL)                   /*!< MCUN1GPIO119 (Bit 23)                                 */
35769 #define GPIO_MCUN1INT3SET_MCUN1GPIO119_Msk (0x800000UL)             /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
35770 #define GPIO_MCUN1INT3SET_MCUN1GPIO118_Pos (22UL)                   /*!< MCUN1GPIO118 (Bit 22)                                 */
35771 #define GPIO_MCUN1INT3SET_MCUN1GPIO118_Msk (0x400000UL)             /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
35772 #define GPIO_MCUN1INT3SET_MCUN1GPIO117_Pos (21UL)                   /*!< MCUN1GPIO117 (Bit 21)                                 */
35773 #define GPIO_MCUN1INT3SET_MCUN1GPIO117_Msk (0x200000UL)             /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
35774 #define GPIO_MCUN1INT3SET_MCUN1GPIO116_Pos (20UL)                   /*!< MCUN1GPIO116 (Bit 20)                                 */
35775 #define GPIO_MCUN1INT3SET_MCUN1GPIO116_Msk (0x100000UL)             /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
35776 #define GPIO_MCUN1INT3SET_MCUN1GPIO115_Pos (19UL)                   /*!< MCUN1GPIO115 (Bit 19)                                 */
35777 #define GPIO_MCUN1INT3SET_MCUN1GPIO115_Msk (0x80000UL)              /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
35778 #define GPIO_MCUN1INT3SET_MCUN1GPIO114_Pos (18UL)                   /*!< MCUN1GPIO114 (Bit 18)                                 */
35779 #define GPIO_MCUN1INT3SET_MCUN1GPIO114_Msk (0x40000UL)              /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
35780 #define GPIO_MCUN1INT3SET_MCUN1GPIO113_Pos (17UL)                   /*!< MCUN1GPIO113 (Bit 17)                                 */
35781 #define GPIO_MCUN1INT3SET_MCUN1GPIO113_Msk (0x20000UL)              /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
35782 #define GPIO_MCUN1INT3SET_MCUN1GPIO112_Pos (16UL)                   /*!< MCUN1GPIO112 (Bit 16)                                 */
35783 #define GPIO_MCUN1INT3SET_MCUN1GPIO112_Msk (0x10000UL)              /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
35784 #define GPIO_MCUN1INT3SET_MCUN1GPIO111_Pos (15UL)                   /*!< MCUN1GPIO111 (Bit 15)                                 */
35785 #define GPIO_MCUN1INT3SET_MCUN1GPIO111_Msk (0x8000UL)               /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
35786 #define GPIO_MCUN1INT3SET_MCUN1GPIO110_Pos (14UL)                   /*!< MCUN1GPIO110 (Bit 14)                                 */
35787 #define GPIO_MCUN1INT3SET_MCUN1GPIO110_Msk (0x4000UL)               /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
35788 #define GPIO_MCUN1INT3SET_MCUN1GPIO109_Pos (13UL)                   /*!< MCUN1GPIO109 (Bit 13)                                 */
35789 #define GPIO_MCUN1INT3SET_MCUN1GPIO109_Msk (0x2000UL)               /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
35790 #define GPIO_MCUN1INT3SET_MCUN1GPIO108_Pos (12UL)                   /*!< MCUN1GPIO108 (Bit 12)                                 */
35791 #define GPIO_MCUN1INT3SET_MCUN1GPIO108_Msk (0x1000UL)               /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
35792 #define GPIO_MCUN1INT3SET_MCUN1GPIO107_Pos (11UL)                   /*!< MCUN1GPIO107 (Bit 11)                                 */
35793 #define GPIO_MCUN1INT3SET_MCUN1GPIO107_Msk (0x800UL)                /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
35794 #define GPIO_MCUN1INT3SET_MCUN1GPIO106_Pos (10UL)                   /*!< MCUN1GPIO106 (Bit 10)                                 */
35795 #define GPIO_MCUN1INT3SET_MCUN1GPIO106_Msk (0x400UL)                /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
35796 #define GPIO_MCUN1INT3SET_MCUN1GPIO105_Pos (9UL)                    /*!< MCUN1GPIO105 (Bit 9)                                  */
35797 #define GPIO_MCUN1INT3SET_MCUN1GPIO105_Msk (0x200UL)                /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
35798 #define GPIO_MCUN1INT3SET_MCUN1GPIO104_Pos (8UL)                    /*!< MCUN1GPIO104 (Bit 8)                                  */
35799 #define GPIO_MCUN1INT3SET_MCUN1GPIO104_Msk (0x100UL)                /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
35800 #define GPIO_MCUN1INT3SET_MCUN1GPIO103_Pos (7UL)                    /*!< MCUN1GPIO103 (Bit 7)                                  */
35801 #define GPIO_MCUN1INT3SET_MCUN1GPIO103_Msk (0x80UL)                 /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
35802 #define GPIO_MCUN1INT3SET_MCUN1GPIO102_Pos (6UL)                    /*!< MCUN1GPIO102 (Bit 6)                                  */
35803 #define GPIO_MCUN1INT3SET_MCUN1GPIO102_Msk (0x40UL)                 /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
35804 #define GPIO_MCUN1INT3SET_MCUN1GPIO101_Pos (5UL)                    /*!< MCUN1GPIO101 (Bit 5)                                  */
35805 #define GPIO_MCUN1INT3SET_MCUN1GPIO101_Msk (0x20UL)                 /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
35806 #define GPIO_MCUN1INT3SET_MCUN1GPIO100_Pos (4UL)                    /*!< MCUN1GPIO100 (Bit 4)                                  */
35807 #define GPIO_MCUN1INT3SET_MCUN1GPIO100_Msk (0x10UL)                 /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
35808 #define GPIO_MCUN1INT3SET_MCUN1GPIO99_Pos (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
35809 #define GPIO_MCUN1INT3SET_MCUN1GPIO99_Msk (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
35810 #define GPIO_MCUN1INT3SET_MCUN1GPIO98_Pos (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
35811 #define GPIO_MCUN1INT3SET_MCUN1GPIO98_Msk (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
35812 #define GPIO_MCUN1INT3SET_MCUN1GPIO97_Pos (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
35813 #define GPIO_MCUN1INT3SET_MCUN1GPIO97_Msk (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
35814 #define GPIO_MCUN1INT3SET_MCUN1GPIO96_Pos (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
35815 #define GPIO_MCUN1INT3SET_MCUN1GPIO96_Msk (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
35816 /* =====================================================  DSP0N0INT0EN  ====================================================== */
35817 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO31_Pos (31UL)                   /*!< DSP0N0GPIO31 (Bit 31)                                 */
35818 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO31_Msk (0x80000000UL)           /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
35819 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO30_Pos (30UL)                   /*!< DSP0N0GPIO30 (Bit 30)                                 */
35820 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO30_Msk (0x40000000UL)           /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
35821 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO29_Pos (29UL)                   /*!< DSP0N0GPIO29 (Bit 29)                                 */
35822 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO29_Msk (0x20000000UL)           /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
35823 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO28_Pos (28UL)                   /*!< DSP0N0GPIO28 (Bit 28)                                 */
35824 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO28_Msk (0x10000000UL)           /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
35825 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO27_Pos (27UL)                   /*!< DSP0N0GPIO27 (Bit 27)                                 */
35826 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO27_Msk (0x8000000UL)            /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
35827 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO26_Pos (26UL)                   /*!< DSP0N0GPIO26 (Bit 26)                                 */
35828 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO26_Msk (0x4000000UL)            /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
35829 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO25_Pos (25UL)                   /*!< DSP0N0GPIO25 (Bit 25)                                 */
35830 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO25_Msk (0x2000000UL)            /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
35831 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO24_Pos (24UL)                   /*!< DSP0N0GPIO24 (Bit 24)                                 */
35832 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO24_Msk (0x1000000UL)            /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
35833 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO23_Pos (23UL)                   /*!< DSP0N0GPIO23 (Bit 23)                                 */
35834 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO23_Msk (0x800000UL)             /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
35835 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO22_Pos (22UL)                   /*!< DSP0N0GPIO22 (Bit 22)                                 */
35836 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO22_Msk (0x400000UL)             /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
35837 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO21_Pos (21UL)                   /*!< DSP0N0GPIO21 (Bit 21)                                 */
35838 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO21_Msk (0x200000UL)             /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
35839 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO20_Pos (20UL)                   /*!< DSP0N0GPIO20 (Bit 20)                                 */
35840 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO20_Msk (0x100000UL)             /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
35841 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO19_Pos (19UL)                   /*!< DSP0N0GPIO19 (Bit 19)                                 */
35842 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO19_Msk (0x80000UL)              /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
35843 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO18_Pos (18UL)                   /*!< DSP0N0GPIO18 (Bit 18)                                 */
35844 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO18_Msk (0x40000UL)              /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
35845 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO17_Pos (17UL)                   /*!< DSP0N0GPIO17 (Bit 17)                                 */
35846 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO17_Msk (0x20000UL)              /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
35847 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO16_Pos (16UL)                   /*!< DSP0N0GPIO16 (Bit 16)                                 */
35848 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO16_Msk (0x10000UL)              /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
35849 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO15_Pos (15UL)                   /*!< DSP0N0GPIO15 (Bit 15)                                 */
35850 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO15_Msk (0x8000UL)               /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
35851 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO14_Pos (14UL)                   /*!< DSP0N0GPIO14 (Bit 14)                                 */
35852 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO14_Msk (0x4000UL)               /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
35853 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO13_Pos (13UL)                   /*!< DSP0N0GPIO13 (Bit 13)                                 */
35854 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO13_Msk (0x2000UL)               /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
35855 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO12_Pos (12UL)                   /*!< DSP0N0GPIO12 (Bit 12)                                 */
35856 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO12_Msk (0x1000UL)               /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
35857 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO11_Pos (11UL)                   /*!< DSP0N0GPIO11 (Bit 11)                                 */
35858 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO11_Msk (0x800UL)                /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
35859 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO10_Pos (10UL)                   /*!< DSP0N0GPIO10 (Bit 10)                                 */
35860 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO10_Msk (0x400UL)                /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
35861 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO9_Pos (9UL)                     /*!< DSP0N0GPIO9 (Bit 9)                                   */
35862 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO9_Msk (0x200UL)                 /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
35863 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO8_Pos (8UL)                     /*!< DSP0N0GPIO8 (Bit 8)                                   */
35864 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO8_Msk (0x100UL)                 /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
35865 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO7_Pos (7UL)                     /*!< DSP0N0GPIO7 (Bit 7)                                   */
35866 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO7_Msk (0x80UL)                  /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
35867 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO6_Pos (6UL)                     /*!< DSP0N0GPIO6 (Bit 6)                                   */
35868 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO6_Msk (0x40UL)                  /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
35869 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO5_Pos (5UL)                     /*!< DSP0N0GPIO5 (Bit 5)                                   */
35870 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO5_Msk (0x20UL)                  /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
35871 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO4_Pos (4UL)                     /*!< DSP0N0GPIO4 (Bit 4)                                   */
35872 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO4_Msk (0x10UL)                  /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
35873 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO3_Pos (3UL)                     /*!< DSP0N0GPIO3 (Bit 3)                                   */
35874 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO3_Msk (0x8UL)                   /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
35875 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO2_Pos (2UL)                     /*!< DSP0N0GPIO2 (Bit 2)                                   */
35876 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO2_Msk (0x4UL)                   /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
35877 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO1_Pos (1UL)                     /*!< DSP0N0GPIO1 (Bit 1)                                   */
35878 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO1_Msk (0x2UL)                   /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
35879 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO0_Pos (0UL)                     /*!< DSP0N0GPIO0 (Bit 0)                                   */
35880 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO0_Msk (0x1UL)                   /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
35881 /* ====================================================  DSP0N0INT0STAT  ===================================================== */
35882 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO31_Pos (31UL)                 /*!< DSP0N0GPIO31 (Bit 31)                                 */
35883 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO31_Msk (0x80000000UL)         /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
35884 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO30_Pos (30UL)                 /*!< DSP0N0GPIO30 (Bit 30)                                 */
35885 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO30_Msk (0x40000000UL)         /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
35886 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO29_Pos (29UL)                 /*!< DSP0N0GPIO29 (Bit 29)                                 */
35887 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO29_Msk (0x20000000UL)         /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
35888 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO28_Pos (28UL)                 /*!< DSP0N0GPIO28 (Bit 28)                                 */
35889 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO28_Msk (0x10000000UL)         /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
35890 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO27_Pos (27UL)                 /*!< DSP0N0GPIO27 (Bit 27)                                 */
35891 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO27_Msk (0x8000000UL)          /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
35892 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO26_Pos (26UL)                 /*!< DSP0N0GPIO26 (Bit 26)                                 */
35893 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO26_Msk (0x4000000UL)          /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
35894 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO25_Pos (25UL)                 /*!< DSP0N0GPIO25 (Bit 25)                                 */
35895 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO25_Msk (0x2000000UL)          /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
35896 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO24_Pos (24UL)                 /*!< DSP0N0GPIO24 (Bit 24)                                 */
35897 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO24_Msk (0x1000000UL)          /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
35898 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO23_Pos (23UL)                 /*!< DSP0N0GPIO23 (Bit 23)                                 */
35899 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO23_Msk (0x800000UL)           /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
35900 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO22_Pos (22UL)                 /*!< DSP0N0GPIO22 (Bit 22)                                 */
35901 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO22_Msk (0x400000UL)           /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
35902 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO21_Pos (21UL)                 /*!< DSP0N0GPIO21 (Bit 21)                                 */
35903 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO21_Msk (0x200000UL)           /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
35904 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO20_Pos (20UL)                 /*!< DSP0N0GPIO20 (Bit 20)                                 */
35905 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO20_Msk (0x100000UL)           /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
35906 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO19_Pos (19UL)                 /*!< DSP0N0GPIO19 (Bit 19)                                 */
35907 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO19_Msk (0x80000UL)            /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
35908 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO18_Pos (18UL)                 /*!< DSP0N0GPIO18 (Bit 18)                                 */
35909 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO18_Msk (0x40000UL)            /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
35910 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO17_Pos (17UL)                 /*!< DSP0N0GPIO17 (Bit 17)                                 */
35911 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO17_Msk (0x20000UL)            /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
35912 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO16_Pos (16UL)                 /*!< DSP0N0GPIO16 (Bit 16)                                 */
35913 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO16_Msk (0x10000UL)            /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
35914 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO15_Pos (15UL)                 /*!< DSP0N0GPIO15 (Bit 15)                                 */
35915 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO15_Msk (0x8000UL)             /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
35916 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO14_Pos (14UL)                 /*!< DSP0N0GPIO14 (Bit 14)                                 */
35917 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO14_Msk (0x4000UL)             /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
35918 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO13_Pos (13UL)                 /*!< DSP0N0GPIO13 (Bit 13)                                 */
35919 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO13_Msk (0x2000UL)             /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
35920 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO12_Pos (12UL)                 /*!< DSP0N0GPIO12 (Bit 12)                                 */
35921 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO12_Msk (0x1000UL)             /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
35922 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO11_Pos (11UL)                 /*!< DSP0N0GPIO11 (Bit 11)                                 */
35923 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO11_Msk (0x800UL)              /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
35924 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO10_Pos (10UL)                 /*!< DSP0N0GPIO10 (Bit 10)                                 */
35925 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO10_Msk (0x400UL)              /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
35926 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO9_Pos (9UL)                   /*!< DSP0N0GPIO9 (Bit 9)                                   */
35927 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO9_Msk (0x200UL)               /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
35928 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO8_Pos (8UL)                   /*!< DSP0N0GPIO8 (Bit 8)                                   */
35929 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO8_Msk (0x100UL)               /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
35930 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO7_Pos (7UL)                   /*!< DSP0N0GPIO7 (Bit 7)                                   */
35931 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO7_Msk (0x80UL)                /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
35932 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO6_Pos (6UL)                   /*!< DSP0N0GPIO6 (Bit 6)                                   */
35933 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO6_Msk (0x40UL)                /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
35934 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO5_Pos (5UL)                   /*!< DSP0N0GPIO5 (Bit 5)                                   */
35935 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO5_Msk (0x20UL)                /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
35936 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO4_Pos (4UL)                   /*!< DSP0N0GPIO4 (Bit 4)                                   */
35937 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO4_Msk (0x10UL)                /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
35938 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO3_Pos (3UL)                   /*!< DSP0N0GPIO3 (Bit 3)                                   */
35939 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO3_Msk (0x8UL)                 /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
35940 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO2_Pos (2UL)                   /*!< DSP0N0GPIO2 (Bit 2)                                   */
35941 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO2_Msk (0x4UL)                 /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
35942 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO1_Pos (1UL)                   /*!< DSP0N0GPIO1 (Bit 1)                                   */
35943 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO1_Msk (0x2UL)                 /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
35944 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO0_Pos (0UL)                   /*!< DSP0N0GPIO0 (Bit 0)                                   */
35945 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO0_Msk (0x1UL)                 /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
35946 /* =====================================================  DSP0N0INT0CLR  ===================================================== */
35947 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO31_Pos (31UL)                  /*!< DSP0N0GPIO31 (Bit 31)                                 */
35948 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO31_Msk (0x80000000UL)          /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
35949 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO30_Pos (30UL)                  /*!< DSP0N0GPIO30 (Bit 30)                                 */
35950 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO30_Msk (0x40000000UL)          /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
35951 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO29_Pos (29UL)                  /*!< DSP0N0GPIO29 (Bit 29)                                 */
35952 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO29_Msk (0x20000000UL)          /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
35953 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO28_Pos (28UL)                  /*!< DSP0N0GPIO28 (Bit 28)                                 */
35954 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO28_Msk (0x10000000UL)          /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
35955 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO27_Pos (27UL)                  /*!< DSP0N0GPIO27 (Bit 27)                                 */
35956 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO27_Msk (0x8000000UL)           /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
35957 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO26_Pos (26UL)                  /*!< DSP0N0GPIO26 (Bit 26)                                 */
35958 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO26_Msk (0x4000000UL)           /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
35959 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO25_Pos (25UL)                  /*!< DSP0N0GPIO25 (Bit 25)                                 */
35960 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO25_Msk (0x2000000UL)           /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
35961 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO24_Pos (24UL)                  /*!< DSP0N0GPIO24 (Bit 24)                                 */
35962 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO24_Msk (0x1000000UL)           /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
35963 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO23_Pos (23UL)                  /*!< DSP0N0GPIO23 (Bit 23)                                 */
35964 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO23_Msk (0x800000UL)            /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
35965 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO22_Pos (22UL)                  /*!< DSP0N0GPIO22 (Bit 22)                                 */
35966 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO22_Msk (0x400000UL)            /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
35967 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO21_Pos (21UL)                  /*!< DSP0N0GPIO21 (Bit 21)                                 */
35968 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO21_Msk (0x200000UL)            /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
35969 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO20_Pos (20UL)                  /*!< DSP0N0GPIO20 (Bit 20)                                 */
35970 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO20_Msk (0x100000UL)            /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
35971 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO19_Pos (19UL)                  /*!< DSP0N0GPIO19 (Bit 19)                                 */
35972 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO19_Msk (0x80000UL)             /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
35973 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO18_Pos (18UL)                  /*!< DSP0N0GPIO18 (Bit 18)                                 */
35974 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO18_Msk (0x40000UL)             /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
35975 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO17_Pos (17UL)                  /*!< DSP0N0GPIO17 (Bit 17)                                 */
35976 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO17_Msk (0x20000UL)             /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
35977 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO16_Pos (16UL)                  /*!< DSP0N0GPIO16 (Bit 16)                                 */
35978 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO16_Msk (0x10000UL)             /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
35979 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO15_Pos (15UL)                  /*!< DSP0N0GPIO15 (Bit 15)                                 */
35980 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO15_Msk (0x8000UL)              /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
35981 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO14_Pos (14UL)                  /*!< DSP0N0GPIO14 (Bit 14)                                 */
35982 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO14_Msk (0x4000UL)              /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
35983 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO13_Pos (13UL)                  /*!< DSP0N0GPIO13 (Bit 13)                                 */
35984 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO13_Msk (0x2000UL)              /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
35985 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO12_Pos (12UL)                  /*!< DSP0N0GPIO12 (Bit 12)                                 */
35986 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO12_Msk (0x1000UL)              /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
35987 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO11_Pos (11UL)                  /*!< DSP0N0GPIO11 (Bit 11)                                 */
35988 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO11_Msk (0x800UL)               /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
35989 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO10_Pos (10UL)                  /*!< DSP0N0GPIO10 (Bit 10)                                 */
35990 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO10_Msk (0x400UL)               /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
35991 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO9_Pos (9UL)                    /*!< DSP0N0GPIO9 (Bit 9)                                   */
35992 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO9_Msk (0x200UL)                /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
35993 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO8_Pos (8UL)                    /*!< DSP0N0GPIO8 (Bit 8)                                   */
35994 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO8_Msk (0x100UL)                /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
35995 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO7_Pos (7UL)                    /*!< DSP0N0GPIO7 (Bit 7)                                   */
35996 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO7_Msk (0x80UL)                 /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
35997 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO6_Pos (6UL)                    /*!< DSP0N0GPIO6 (Bit 6)                                   */
35998 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO6_Msk (0x40UL)                 /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
35999 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO5_Pos (5UL)                    /*!< DSP0N0GPIO5 (Bit 5)                                   */
36000 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO5_Msk (0x20UL)                 /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
36001 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO4_Pos (4UL)                    /*!< DSP0N0GPIO4 (Bit 4)                                   */
36002 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO4_Msk (0x10UL)                 /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
36003 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO3_Pos (3UL)                    /*!< DSP0N0GPIO3 (Bit 3)                                   */
36004 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO3_Msk (0x8UL)                  /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
36005 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO2_Pos (2UL)                    /*!< DSP0N0GPIO2 (Bit 2)                                   */
36006 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO2_Msk (0x4UL)                  /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
36007 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO1_Pos (1UL)                    /*!< DSP0N0GPIO1 (Bit 1)                                   */
36008 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO1_Msk (0x2UL)                  /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
36009 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO0_Pos (0UL)                    /*!< DSP0N0GPIO0 (Bit 0)                                   */
36010 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO0_Msk (0x1UL)                  /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
36011 /* =====================================================  DSP0N0INT0SET  ===================================================== */
36012 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO31_Pos (31UL)                  /*!< DSP0N0GPIO31 (Bit 31)                                 */
36013 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO31_Msk (0x80000000UL)          /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
36014 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO30_Pos (30UL)                  /*!< DSP0N0GPIO30 (Bit 30)                                 */
36015 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO30_Msk (0x40000000UL)          /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
36016 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO29_Pos (29UL)                  /*!< DSP0N0GPIO29 (Bit 29)                                 */
36017 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO29_Msk (0x20000000UL)          /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
36018 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO28_Pos (28UL)                  /*!< DSP0N0GPIO28 (Bit 28)                                 */
36019 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO28_Msk (0x10000000UL)          /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
36020 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO27_Pos (27UL)                  /*!< DSP0N0GPIO27 (Bit 27)                                 */
36021 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO27_Msk (0x8000000UL)           /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
36022 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO26_Pos (26UL)                  /*!< DSP0N0GPIO26 (Bit 26)                                 */
36023 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO26_Msk (0x4000000UL)           /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
36024 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO25_Pos (25UL)                  /*!< DSP0N0GPIO25 (Bit 25)                                 */
36025 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO25_Msk (0x2000000UL)           /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
36026 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO24_Pos (24UL)                  /*!< DSP0N0GPIO24 (Bit 24)                                 */
36027 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO24_Msk (0x1000000UL)           /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
36028 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO23_Pos (23UL)                  /*!< DSP0N0GPIO23 (Bit 23)                                 */
36029 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO23_Msk (0x800000UL)            /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
36030 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO22_Pos (22UL)                  /*!< DSP0N0GPIO22 (Bit 22)                                 */
36031 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO22_Msk (0x400000UL)            /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
36032 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO21_Pos (21UL)                  /*!< DSP0N0GPIO21 (Bit 21)                                 */
36033 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO21_Msk (0x200000UL)            /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
36034 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO20_Pos (20UL)                  /*!< DSP0N0GPIO20 (Bit 20)                                 */
36035 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO20_Msk (0x100000UL)            /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
36036 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO19_Pos (19UL)                  /*!< DSP0N0GPIO19 (Bit 19)                                 */
36037 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO19_Msk (0x80000UL)             /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
36038 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO18_Pos (18UL)                  /*!< DSP0N0GPIO18 (Bit 18)                                 */
36039 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO18_Msk (0x40000UL)             /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
36040 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO17_Pos (17UL)                  /*!< DSP0N0GPIO17 (Bit 17)                                 */
36041 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO17_Msk (0x20000UL)             /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
36042 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO16_Pos (16UL)                  /*!< DSP0N0GPIO16 (Bit 16)                                 */
36043 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO16_Msk (0x10000UL)             /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
36044 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO15_Pos (15UL)                  /*!< DSP0N0GPIO15 (Bit 15)                                 */
36045 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO15_Msk (0x8000UL)              /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
36046 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO14_Pos (14UL)                  /*!< DSP0N0GPIO14 (Bit 14)                                 */
36047 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO14_Msk (0x4000UL)              /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
36048 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO13_Pos (13UL)                  /*!< DSP0N0GPIO13 (Bit 13)                                 */
36049 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO13_Msk (0x2000UL)              /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
36050 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO12_Pos (12UL)                  /*!< DSP0N0GPIO12 (Bit 12)                                 */
36051 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO12_Msk (0x1000UL)              /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
36052 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO11_Pos (11UL)                  /*!< DSP0N0GPIO11 (Bit 11)                                 */
36053 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO11_Msk (0x800UL)               /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
36054 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO10_Pos (10UL)                  /*!< DSP0N0GPIO10 (Bit 10)                                 */
36055 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO10_Msk (0x400UL)               /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
36056 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO9_Pos (9UL)                    /*!< DSP0N0GPIO9 (Bit 9)                                   */
36057 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO9_Msk (0x200UL)                /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
36058 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO8_Pos (8UL)                    /*!< DSP0N0GPIO8 (Bit 8)                                   */
36059 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO8_Msk (0x100UL)                /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
36060 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO7_Pos (7UL)                    /*!< DSP0N0GPIO7 (Bit 7)                                   */
36061 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO7_Msk (0x80UL)                 /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
36062 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO6_Pos (6UL)                    /*!< DSP0N0GPIO6 (Bit 6)                                   */
36063 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO6_Msk (0x40UL)                 /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
36064 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO5_Pos (5UL)                    /*!< DSP0N0GPIO5 (Bit 5)                                   */
36065 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO5_Msk (0x20UL)                 /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
36066 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO4_Pos (4UL)                    /*!< DSP0N0GPIO4 (Bit 4)                                   */
36067 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO4_Msk (0x10UL)                 /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
36068 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO3_Pos (3UL)                    /*!< DSP0N0GPIO3 (Bit 3)                                   */
36069 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO3_Msk (0x8UL)                  /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
36070 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO2_Pos (2UL)                    /*!< DSP0N0GPIO2 (Bit 2)                                   */
36071 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO2_Msk (0x4UL)                  /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
36072 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO1_Pos (1UL)                    /*!< DSP0N0GPIO1 (Bit 1)                                   */
36073 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO1_Msk (0x2UL)                  /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
36074 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO0_Pos (0UL)                    /*!< DSP0N0GPIO0 (Bit 0)                                   */
36075 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO0_Msk (0x1UL)                  /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
36076 /* =====================================================  DSP0N0INT1EN  ====================================================== */
36077 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO63_Pos (31UL)                   /*!< DSP0N0GPIO63 (Bit 31)                                 */
36078 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO63_Msk (0x80000000UL)           /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36079 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO62_Pos (30UL)                   /*!< DSP0N0GPIO62 (Bit 30)                                 */
36080 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO62_Msk (0x40000000UL)           /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36081 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO61_Pos (29UL)                   /*!< DSP0N0GPIO61 (Bit 29)                                 */
36082 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO61_Msk (0x20000000UL)           /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36083 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO60_Pos (28UL)                   /*!< DSP0N0GPIO60 (Bit 28)                                 */
36084 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO60_Msk (0x10000000UL)           /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36085 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO59_Pos (27UL)                   /*!< DSP0N0GPIO59 (Bit 27)                                 */
36086 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO59_Msk (0x8000000UL)            /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36087 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO58_Pos (26UL)                   /*!< DSP0N0GPIO58 (Bit 26)                                 */
36088 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO58_Msk (0x4000000UL)            /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36089 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO57_Pos (25UL)                   /*!< DSP0N0GPIO57 (Bit 25)                                 */
36090 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO57_Msk (0x2000000UL)            /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36091 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO56_Pos (24UL)                   /*!< DSP0N0GPIO56 (Bit 24)                                 */
36092 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO56_Msk (0x1000000UL)            /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36093 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO55_Pos (23UL)                   /*!< DSP0N0GPIO55 (Bit 23)                                 */
36094 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO55_Msk (0x800000UL)             /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36095 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO54_Pos (22UL)                   /*!< DSP0N0GPIO54 (Bit 22)                                 */
36096 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO54_Msk (0x400000UL)             /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36097 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO53_Pos (21UL)                   /*!< DSP0N0GPIO53 (Bit 21)                                 */
36098 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO53_Msk (0x200000UL)             /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36099 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO52_Pos (20UL)                   /*!< DSP0N0GPIO52 (Bit 20)                                 */
36100 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO52_Msk (0x100000UL)             /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36101 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO51_Pos (19UL)                   /*!< DSP0N0GPIO51 (Bit 19)                                 */
36102 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO51_Msk (0x80000UL)              /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36103 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO50_Pos (18UL)                   /*!< DSP0N0GPIO50 (Bit 18)                                 */
36104 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO50_Msk (0x40000UL)              /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36105 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO49_Pos (17UL)                   /*!< DSP0N0GPIO49 (Bit 17)                                 */
36106 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO49_Msk (0x20000UL)              /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36107 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO48_Pos (16UL)                   /*!< DSP0N0GPIO48 (Bit 16)                                 */
36108 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO48_Msk (0x10000UL)              /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36109 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO47_Pos (15UL)                   /*!< DSP0N0GPIO47 (Bit 15)                                 */
36110 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO47_Msk (0x8000UL)               /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36111 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO46_Pos (14UL)                   /*!< DSP0N0GPIO46 (Bit 14)                                 */
36112 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO46_Msk (0x4000UL)               /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36113 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO45_Pos (13UL)                   /*!< DSP0N0GPIO45 (Bit 13)                                 */
36114 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO45_Msk (0x2000UL)               /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36115 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO44_Pos (12UL)                   /*!< DSP0N0GPIO44 (Bit 12)                                 */
36116 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO44_Msk (0x1000UL)               /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36117 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO43_Pos (11UL)                   /*!< DSP0N0GPIO43 (Bit 11)                                 */
36118 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO43_Msk (0x800UL)                /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36119 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO42_Pos (10UL)                   /*!< DSP0N0GPIO42 (Bit 10)                                 */
36120 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO42_Msk (0x400UL)                /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36121 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO41_Pos (9UL)                    /*!< DSP0N0GPIO41 (Bit 9)                                  */
36122 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO41_Msk (0x200UL)                /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36123 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO40_Pos (8UL)                    /*!< DSP0N0GPIO40 (Bit 8)                                  */
36124 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO40_Msk (0x100UL)                /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36125 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO39_Pos (7UL)                    /*!< DSP0N0GPIO39 (Bit 7)                                  */
36126 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO39_Msk (0x80UL)                 /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36127 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO38_Pos (6UL)                    /*!< DSP0N0GPIO38 (Bit 6)                                  */
36128 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO38_Msk (0x40UL)                 /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36129 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO37_Pos (5UL)                    /*!< DSP0N0GPIO37 (Bit 5)                                  */
36130 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO37_Msk (0x20UL)                 /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36131 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO36_Pos (4UL)                    /*!< DSP0N0GPIO36 (Bit 4)                                  */
36132 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO36_Msk (0x10UL)                 /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36133 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO35_Pos (3UL)                    /*!< DSP0N0GPIO35 (Bit 3)                                  */
36134 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO35_Msk (0x8UL)                  /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36135 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO34_Pos (2UL)                    /*!< DSP0N0GPIO34 (Bit 2)                                  */
36136 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO34_Msk (0x4UL)                  /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36137 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO33_Pos (1UL)                    /*!< DSP0N0GPIO33 (Bit 1)                                  */
36138 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO33_Msk (0x2UL)                  /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36139 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO32_Pos (0UL)                    /*!< DSP0N0GPIO32 (Bit 0)                                  */
36140 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO32_Msk (0x1UL)                  /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36141 /* ====================================================  DSP0N0INT1STAT  ===================================================== */
36142 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO63_Pos (31UL)                 /*!< DSP0N0GPIO63 (Bit 31)                                 */
36143 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO63_Msk (0x80000000UL)         /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36144 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO62_Pos (30UL)                 /*!< DSP0N0GPIO62 (Bit 30)                                 */
36145 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO62_Msk (0x40000000UL)         /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36146 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO61_Pos (29UL)                 /*!< DSP0N0GPIO61 (Bit 29)                                 */
36147 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO61_Msk (0x20000000UL)         /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36148 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO60_Pos (28UL)                 /*!< DSP0N0GPIO60 (Bit 28)                                 */
36149 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO60_Msk (0x10000000UL)         /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36150 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO59_Pos (27UL)                 /*!< DSP0N0GPIO59 (Bit 27)                                 */
36151 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO59_Msk (0x8000000UL)          /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36152 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO58_Pos (26UL)                 /*!< DSP0N0GPIO58 (Bit 26)                                 */
36153 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO58_Msk (0x4000000UL)          /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36154 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO57_Pos (25UL)                 /*!< DSP0N0GPIO57 (Bit 25)                                 */
36155 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO57_Msk (0x2000000UL)          /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36156 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO56_Pos (24UL)                 /*!< DSP0N0GPIO56 (Bit 24)                                 */
36157 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO56_Msk (0x1000000UL)          /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36158 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO55_Pos (23UL)                 /*!< DSP0N0GPIO55 (Bit 23)                                 */
36159 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO55_Msk (0x800000UL)           /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36160 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO54_Pos (22UL)                 /*!< DSP0N0GPIO54 (Bit 22)                                 */
36161 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO54_Msk (0x400000UL)           /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36162 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO53_Pos (21UL)                 /*!< DSP0N0GPIO53 (Bit 21)                                 */
36163 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO53_Msk (0x200000UL)           /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36164 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO52_Pos (20UL)                 /*!< DSP0N0GPIO52 (Bit 20)                                 */
36165 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO52_Msk (0x100000UL)           /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36166 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO51_Pos (19UL)                 /*!< DSP0N0GPIO51 (Bit 19)                                 */
36167 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO51_Msk (0x80000UL)            /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36168 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO50_Pos (18UL)                 /*!< DSP0N0GPIO50 (Bit 18)                                 */
36169 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO50_Msk (0x40000UL)            /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36170 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO49_Pos (17UL)                 /*!< DSP0N0GPIO49 (Bit 17)                                 */
36171 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO49_Msk (0x20000UL)            /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36172 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO48_Pos (16UL)                 /*!< DSP0N0GPIO48 (Bit 16)                                 */
36173 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO48_Msk (0x10000UL)            /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36174 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO47_Pos (15UL)                 /*!< DSP0N0GPIO47 (Bit 15)                                 */
36175 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO47_Msk (0x8000UL)             /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36176 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO46_Pos (14UL)                 /*!< DSP0N0GPIO46 (Bit 14)                                 */
36177 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO46_Msk (0x4000UL)             /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36178 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO45_Pos (13UL)                 /*!< DSP0N0GPIO45 (Bit 13)                                 */
36179 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO45_Msk (0x2000UL)             /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36180 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO44_Pos (12UL)                 /*!< DSP0N0GPIO44 (Bit 12)                                 */
36181 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO44_Msk (0x1000UL)             /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36182 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO43_Pos (11UL)                 /*!< DSP0N0GPIO43 (Bit 11)                                 */
36183 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO43_Msk (0x800UL)              /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36184 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO42_Pos (10UL)                 /*!< DSP0N0GPIO42 (Bit 10)                                 */
36185 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO42_Msk (0x400UL)              /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36186 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO41_Pos (9UL)                  /*!< DSP0N0GPIO41 (Bit 9)                                  */
36187 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO41_Msk (0x200UL)              /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36188 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO40_Pos (8UL)                  /*!< DSP0N0GPIO40 (Bit 8)                                  */
36189 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO40_Msk (0x100UL)              /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36190 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO39_Pos (7UL)                  /*!< DSP0N0GPIO39 (Bit 7)                                  */
36191 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO39_Msk (0x80UL)               /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36192 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO38_Pos (6UL)                  /*!< DSP0N0GPIO38 (Bit 6)                                  */
36193 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO38_Msk (0x40UL)               /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36194 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO37_Pos (5UL)                  /*!< DSP0N0GPIO37 (Bit 5)                                  */
36195 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO37_Msk (0x20UL)               /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36196 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO36_Pos (4UL)                  /*!< DSP0N0GPIO36 (Bit 4)                                  */
36197 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO36_Msk (0x10UL)               /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36198 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO35_Pos (3UL)                  /*!< DSP0N0GPIO35 (Bit 3)                                  */
36199 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO35_Msk (0x8UL)                /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36200 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO34_Pos (2UL)                  /*!< DSP0N0GPIO34 (Bit 2)                                  */
36201 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO34_Msk (0x4UL)                /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36202 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO33_Pos (1UL)                  /*!< DSP0N0GPIO33 (Bit 1)                                  */
36203 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO33_Msk (0x2UL)                /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36204 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO32_Pos (0UL)                  /*!< DSP0N0GPIO32 (Bit 0)                                  */
36205 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO32_Msk (0x1UL)                /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36206 /* =====================================================  DSP0N0INT1CLR  ===================================================== */
36207 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO63_Pos (31UL)                  /*!< DSP0N0GPIO63 (Bit 31)                                 */
36208 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO63_Msk (0x80000000UL)          /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36209 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO62_Pos (30UL)                  /*!< DSP0N0GPIO62 (Bit 30)                                 */
36210 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO62_Msk (0x40000000UL)          /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36211 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO61_Pos (29UL)                  /*!< DSP0N0GPIO61 (Bit 29)                                 */
36212 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO61_Msk (0x20000000UL)          /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36213 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO60_Pos (28UL)                  /*!< DSP0N0GPIO60 (Bit 28)                                 */
36214 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO60_Msk (0x10000000UL)          /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36215 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO59_Pos (27UL)                  /*!< DSP0N0GPIO59 (Bit 27)                                 */
36216 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO59_Msk (0x8000000UL)           /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36217 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO58_Pos (26UL)                  /*!< DSP0N0GPIO58 (Bit 26)                                 */
36218 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO58_Msk (0x4000000UL)           /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36219 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO57_Pos (25UL)                  /*!< DSP0N0GPIO57 (Bit 25)                                 */
36220 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO57_Msk (0x2000000UL)           /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36221 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO56_Pos (24UL)                  /*!< DSP0N0GPIO56 (Bit 24)                                 */
36222 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO56_Msk (0x1000000UL)           /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36223 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO55_Pos (23UL)                  /*!< DSP0N0GPIO55 (Bit 23)                                 */
36224 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO55_Msk (0x800000UL)            /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36225 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO54_Pos (22UL)                  /*!< DSP0N0GPIO54 (Bit 22)                                 */
36226 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO54_Msk (0x400000UL)            /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36227 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO53_Pos (21UL)                  /*!< DSP0N0GPIO53 (Bit 21)                                 */
36228 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO53_Msk (0x200000UL)            /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36229 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO52_Pos (20UL)                  /*!< DSP0N0GPIO52 (Bit 20)                                 */
36230 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO52_Msk (0x100000UL)            /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36231 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO51_Pos (19UL)                  /*!< DSP0N0GPIO51 (Bit 19)                                 */
36232 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO51_Msk (0x80000UL)             /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36233 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO50_Pos (18UL)                  /*!< DSP0N0GPIO50 (Bit 18)                                 */
36234 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO50_Msk (0x40000UL)             /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36235 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO49_Pos (17UL)                  /*!< DSP0N0GPIO49 (Bit 17)                                 */
36236 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO49_Msk (0x20000UL)             /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36237 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO48_Pos (16UL)                  /*!< DSP0N0GPIO48 (Bit 16)                                 */
36238 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO48_Msk (0x10000UL)             /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36239 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO47_Pos (15UL)                  /*!< DSP0N0GPIO47 (Bit 15)                                 */
36240 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO47_Msk (0x8000UL)              /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36241 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO46_Pos (14UL)                  /*!< DSP0N0GPIO46 (Bit 14)                                 */
36242 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO46_Msk (0x4000UL)              /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36243 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO45_Pos (13UL)                  /*!< DSP0N0GPIO45 (Bit 13)                                 */
36244 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO45_Msk (0x2000UL)              /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36245 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO44_Pos (12UL)                  /*!< DSP0N0GPIO44 (Bit 12)                                 */
36246 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO44_Msk (0x1000UL)              /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36247 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO43_Pos (11UL)                  /*!< DSP0N0GPIO43 (Bit 11)                                 */
36248 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO43_Msk (0x800UL)               /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36249 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO42_Pos (10UL)                  /*!< DSP0N0GPIO42 (Bit 10)                                 */
36250 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO42_Msk (0x400UL)               /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36251 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO41_Pos (9UL)                   /*!< DSP0N0GPIO41 (Bit 9)                                  */
36252 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO41_Msk (0x200UL)               /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36253 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO40_Pos (8UL)                   /*!< DSP0N0GPIO40 (Bit 8)                                  */
36254 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO40_Msk (0x100UL)               /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36255 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO39_Pos (7UL)                   /*!< DSP0N0GPIO39 (Bit 7)                                  */
36256 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO39_Msk (0x80UL)                /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36257 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO38_Pos (6UL)                   /*!< DSP0N0GPIO38 (Bit 6)                                  */
36258 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO38_Msk (0x40UL)                /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36259 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO37_Pos (5UL)                   /*!< DSP0N0GPIO37 (Bit 5)                                  */
36260 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO37_Msk (0x20UL)                /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36261 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO36_Pos (4UL)                   /*!< DSP0N0GPIO36 (Bit 4)                                  */
36262 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO36_Msk (0x10UL)                /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36263 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO35_Pos (3UL)                   /*!< DSP0N0GPIO35 (Bit 3)                                  */
36264 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO35_Msk (0x8UL)                 /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36265 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO34_Pos (2UL)                   /*!< DSP0N0GPIO34 (Bit 2)                                  */
36266 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO34_Msk (0x4UL)                 /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36267 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO33_Pos (1UL)                   /*!< DSP0N0GPIO33 (Bit 1)                                  */
36268 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO33_Msk (0x2UL)                 /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36269 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO32_Pos (0UL)                   /*!< DSP0N0GPIO32 (Bit 0)                                  */
36270 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO32_Msk (0x1UL)                 /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36271 /* =====================================================  DSP0N0INT1SET  ===================================================== */
36272 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO63_Pos (31UL)                  /*!< DSP0N0GPIO63 (Bit 31)                                 */
36273 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO63_Msk (0x80000000UL)          /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36274 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO62_Pos (30UL)                  /*!< DSP0N0GPIO62 (Bit 30)                                 */
36275 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO62_Msk (0x40000000UL)          /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36276 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO61_Pos (29UL)                  /*!< DSP0N0GPIO61 (Bit 29)                                 */
36277 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO61_Msk (0x20000000UL)          /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36278 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO60_Pos (28UL)                  /*!< DSP0N0GPIO60 (Bit 28)                                 */
36279 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO60_Msk (0x10000000UL)          /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36280 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO59_Pos (27UL)                  /*!< DSP0N0GPIO59 (Bit 27)                                 */
36281 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO59_Msk (0x8000000UL)           /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36282 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO58_Pos (26UL)                  /*!< DSP0N0GPIO58 (Bit 26)                                 */
36283 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO58_Msk (0x4000000UL)           /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36284 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO57_Pos (25UL)                  /*!< DSP0N0GPIO57 (Bit 25)                                 */
36285 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO57_Msk (0x2000000UL)           /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36286 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO56_Pos (24UL)                  /*!< DSP0N0GPIO56 (Bit 24)                                 */
36287 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO56_Msk (0x1000000UL)           /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36288 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO55_Pos (23UL)                  /*!< DSP0N0GPIO55 (Bit 23)                                 */
36289 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO55_Msk (0x800000UL)            /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36290 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO54_Pos (22UL)                  /*!< DSP0N0GPIO54 (Bit 22)                                 */
36291 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO54_Msk (0x400000UL)            /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36292 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO53_Pos (21UL)                  /*!< DSP0N0GPIO53 (Bit 21)                                 */
36293 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO53_Msk (0x200000UL)            /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36294 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO52_Pos (20UL)                  /*!< DSP0N0GPIO52 (Bit 20)                                 */
36295 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO52_Msk (0x100000UL)            /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36296 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO51_Pos (19UL)                  /*!< DSP0N0GPIO51 (Bit 19)                                 */
36297 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO51_Msk (0x80000UL)             /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36298 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO50_Pos (18UL)                  /*!< DSP0N0GPIO50 (Bit 18)                                 */
36299 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO50_Msk (0x40000UL)             /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36300 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO49_Pos (17UL)                  /*!< DSP0N0GPIO49 (Bit 17)                                 */
36301 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO49_Msk (0x20000UL)             /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36302 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO48_Pos (16UL)                  /*!< DSP0N0GPIO48 (Bit 16)                                 */
36303 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO48_Msk (0x10000UL)             /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36304 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO47_Pos (15UL)                  /*!< DSP0N0GPIO47 (Bit 15)                                 */
36305 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO47_Msk (0x8000UL)              /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36306 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO46_Pos (14UL)                  /*!< DSP0N0GPIO46 (Bit 14)                                 */
36307 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO46_Msk (0x4000UL)              /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36308 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO45_Pos (13UL)                  /*!< DSP0N0GPIO45 (Bit 13)                                 */
36309 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO45_Msk (0x2000UL)              /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36310 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO44_Pos (12UL)                  /*!< DSP0N0GPIO44 (Bit 12)                                 */
36311 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO44_Msk (0x1000UL)              /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36312 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO43_Pos (11UL)                  /*!< DSP0N0GPIO43 (Bit 11)                                 */
36313 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO43_Msk (0x800UL)               /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36314 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO42_Pos (10UL)                  /*!< DSP0N0GPIO42 (Bit 10)                                 */
36315 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO42_Msk (0x400UL)               /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36316 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO41_Pos (9UL)                   /*!< DSP0N0GPIO41 (Bit 9)                                  */
36317 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO41_Msk (0x200UL)               /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36318 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO40_Pos (8UL)                   /*!< DSP0N0GPIO40 (Bit 8)                                  */
36319 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO40_Msk (0x100UL)               /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36320 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO39_Pos (7UL)                   /*!< DSP0N0GPIO39 (Bit 7)                                  */
36321 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO39_Msk (0x80UL)                /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36322 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO38_Pos (6UL)                   /*!< DSP0N0GPIO38 (Bit 6)                                  */
36323 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO38_Msk (0x40UL)                /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36324 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO37_Pos (5UL)                   /*!< DSP0N0GPIO37 (Bit 5)                                  */
36325 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO37_Msk (0x20UL)                /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36326 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO36_Pos (4UL)                   /*!< DSP0N0GPIO36 (Bit 4)                                  */
36327 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO36_Msk (0x10UL)                /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36328 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO35_Pos (3UL)                   /*!< DSP0N0GPIO35 (Bit 3)                                  */
36329 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO35_Msk (0x8UL)                 /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36330 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO34_Pos (2UL)                   /*!< DSP0N0GPIO34 (Bit 2)                                  */
36331 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO34_Msk (0x4UL)                 /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36332 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO33_Pos (1UL)                   /*!< DSP0N0GPIO33 (Bit 1)                                  */
36333 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO33_Msk (0x2UL)                 /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36334 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO32_Pos (0UL)                   /*!< DSP0N0GPIO32 (Bit 0)                                  */
36335 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO32_Msk (0x1UL)                 /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36336 /* =====================================================  DSP0N0INT2EN  ====================================================== */
36337 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO95_Pos (31UL)                   /*!< DSP0N0GPIO95 (Bit 31)                                 */
36338 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO95_Msk (0x80000000UL)           /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
36339 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO94_Pos (30UL)                   /*!< DSP0N0GPIO94 (Bit 30)                                 */
36340 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO94_Msk (0x40000000UL)           /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
36341 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO93_Pos (29UL)                   /*!< DSP0N0GPIO93 (Bit 29)                                 */
36342 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO93_Msk (0x20000000UL)           /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
36343 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO92_Pos (28UL)                   /*!< DSP0N0GPIO92 (Bit 28)                                 */
36344 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO92_Msk (0x10000000UL)           /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
36345 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO91_Pos (27UL)                   /*!< DSP0N0GPIO91 (Bit 27)                                 */
36346 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO91_Msk (0x8000000UL)            /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
36347 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO90_Pos (26UL)                   /*!< DSP0N0GPIO90 (Bit 26)                                 */
36348 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO90_Msk (0x4000000UL)            /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
36349 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO89_Pos (25UL)                   /*!< DSP0N0GPIO89 (Bit 25)                                 */
36350 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO89_Msk (0x2000000UL)            /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
36351 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO88_Pos (24UL)                   /*!< DSP0N0GPIO88 (Bit 24)                                 */
36352 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO88_Msk (0x1000000UL)            /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
36353 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO87_Pos (23UL)                   /*!< DSP0N0GPIO87 (Bit 23)                                 */
36354 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO87_Msk (0x800000UL)             /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
36355 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO86_Pos (22UL)                   /*!< DSP0N0GPIO86 (Bit 22)                                 */
36356 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO86_Msk (0x400000UL)             /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
36357 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO85_Pos (21UL)                   /*!< DSP0N0GPIO85 (Bit 21)                                 */
36358 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO85_Msk (0x200000UL)             /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
36359 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO84_Pos (20UL)                   /*!< DSP0N0GPIO84 (Bit 20)                                 */
36360 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO84_Msk (0x100000UL)             /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
36361 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO83_Pos (19UL)                   /*!< DSP0N0GPIO83 (Bit 19)                                 */
36362 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO83_Msk (0x80000UL)              /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
36363 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO82_Pos (18UL)                   /*!< DSP0N0GPIO82 (Bit 18)                                 */
36364 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO82_Msk (0x40000UL)              /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
36365 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO81_Pos (17UL)                   /*!< DSP0N0GPIO81 (Bit 17)                                 */
36366 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO81_Msk (0x20000UL)              /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
36367 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO80_Pos (16UL)                   /*!< DSP0N0GPIO80 (Bit 16)                                 */
36368 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO80_Msk (0x10000UL)              /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
36369 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO79_Pos (15UL)                   /*!< DSP0N0GPIO79 (Bit 15)                                 */
36370 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO79_Msk (0x8000UL)               /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
36371 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO78_Pos (14UL)                   /*!< DSP0N0GPIO78 (Bit 14)                                 */
36372 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO78_Msk (0x4000UL)               /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
36373 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO77_Pos (13UL)                   /*!< DSP0N0GPIO77 (Bit 13)                                 */
36374 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO77_Msk (0x2000UL)               /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
36375 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO76_Pos (12UL)                   /*!< DSP0N0GPIO76 (Bit 12)                                 */
36376 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO76_Msk (0x1000UL)               /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
36377 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO75_Pos (11UL)                   /*!< DSP0N0GPIO75 (Bit 11)                                 */
36378 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO75_Msk (0x800UL)                /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
36379 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO74_Pos (10UL)                   /*!< DSP0N0GPIO74 (Bit 10)                                 */
36380 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO74_Msk (0x400UL)                /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
36381 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO73_Pos (9UL)                    /*!< DSP0N0GPIO73 (Bit 9)                                  */
36382 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO73_Msk (0x200UL)                /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
36383 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO72_Pos (8UL)                    /*!< DSP0N0GPIO72 (Bit 8)                                  */
36384 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO72_Msk (0x100UL)                /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
36385 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO71_Pos (7UL)                    /*!< DSP0N0GPIO71 (Bit 7)                                  */
36386 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO71_Msk (0x80UL)                 /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
36387 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO70_Pos (6UL)                    /*!< DSP0N0GPIO70 (Bit 6)                                  */
36388 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO70_Msk (0x40UL)                 /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
36389 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO69_Pos (5UL)                    /*!< DSP0N0GPIO69 (Bit 5)                                  */
36390 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO69_Msk (0x20UL)                 /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
36391 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO68_Pos (4UL)                    /*!< DSP0N0GPIO68 (Bit 4)                                  */
36392 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO68_Msk (0x10UL)                 /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
36393 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO67_Pos (3UL)                    /*!< DSP0N0GPIO67 (Bit 3)                                  */
36394 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO67_Msk (0x8UL)                  /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
36395 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO66_Pos (2UL)                    /*!< DSP0N0GPIO66 (Bit 2)                                  */
36396 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO66_Msk (0x4UL)                  /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
36397 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO65_Pos (1UL)                    /*!< DSP0N0GPIO65 (Bit 1)                                  */
36398 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO65_Msk (0x2UL)                  /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
36399 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO64_Pos (0UL)                    /*!< DSP0N0GPIO64 (Bit 0)                                  */
36400 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO64_Msk (0x1UL)                  /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
36401 /* ====================================================  DSP0N0INT2STAT  ===================================================== */
36402 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO95_Pos (31UL)                 /*!< DSP0N0GPIO95 (Bit 31)                                 */
36403 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO95_Msk (0x80000000UL)         /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
36404 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO94_Pos (30UL)                 /*!< DSP0N0GPIO94 (Bit 30)                                 */
36405 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO94_Msk (0x40000000UL)         /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
36406 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO93_Pos (29UL)                 /*!< DSP0N0GPIO93 (Bit 29)                                 */
36407 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO93_Msk (0x20000000UL)         /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
36408 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO92_Pos (28UL)                 /*!< DSP0N0GPIO92 (Bit 28)                                 */
36409 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO92_Msk (0x10000000UL)         /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
36410 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO91_Pos (27UL)                 /*!< DSP0N0GPIO91 (Bit 27)                                 */
36411 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO91_Msk (0x8000000UL)          /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
36412 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO90_Pos (26UL)                 /*!< DSP0N0GPIO90 (Bit 26)                                 */
36413 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO90_Msk (0x4000000UL)          /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
36414 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO89_Pos (25UL)                 /*!< DSP0N0GPIO89 (Bit 25)                                 */
36415 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO89_Msk (0x2000000UL)          /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
36416 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO88_Pos (24UL)                 /*!< DSP0N0GPIO88 (Bit 24)                                 */
36417 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO88_Msk (0x1000000UL)          /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
36418 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO87_Pos (23UL)                 /*!< DSP0N0GPIO87 (Bit 23)                                 */
36419 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO87_Msk (0x800000UL)           /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
36420 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO86_Pos (22UL)                 /*!< DSP0N0GPIO86 (Bit 22)                                 */
36421 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO86_Msk (0x400000UL)           /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
36422 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO85_Pos (21UL)                 /*!< DSP0N0GPIO85 (Bit 21)                                 */
36423 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO85_Msk (0x200000UL)           /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
36424 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO84_Pos (20UL)                 /*!< DSP0N0GPIO84 (Bit 20)                                 */
36425 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO84_Msk (0x100000UL)           /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
36426 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO83_Pos (19UL)                 /*!< DSP0N0GPIO83 (Bit 19)                                 */
36427 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO83_Msk (0x80000UL)            /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
36428 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO82_Pos (18UL)                 /*!< DSP0N0GPIO82 (Bit 18)                                 */
36429 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO82_Msk (0x40000UL)            /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
36430 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO81_Pos (17UL)                 /*!< DSP0N0GPIO81 (Bit 17)                                 */
36431 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO81_Msk (0x20000UL)            /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
36432 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO80_Pos (16UL)                 /*!< DSP0N0GPIO80 (Bit 16)                                 */
36433 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO80_Msk (0x10000UL)            /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
36434 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO79_Pos (15UL)                 /*!< DSP0N0GPIO79 (Bit 15)                                 */
36435 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO79_Msk (0x8000UL)             /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
36436 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO78_Pos (14UL)                 /*!< DSP0N0GPIO78 (Bit 14)                                 */
36437 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO78_Msk (0x4000UL)             /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
36438 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO77_Pos (13UL)                 /*!< DSP0N0GPIO77 (Bit 13)                                 */
36439 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO77_Msk (0x2000UL)             /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
36440 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO76_Pos (12UL)                 /*!< DSP0N0GPIO76 (Bit 12)                                 */
36441 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO76_Msk (0x1000UL)             /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
36442 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO75_Pos (11UL)                 /*!< DSP0N0GPIO75 (Bit 11)                                 */
36443 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO75_Msk (0x800UL)              /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
36444 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO74_Pos (10UL)                 /*!< DSP0N0GPIO74 (Bit 10)                                 */
36445 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO74_Msk (0x400UL)              /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
36446 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO73_Pos (9UL)                  /*!< DSP0N0GPIO73 (Bit 9)                                  */
36447 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO73_Msk (0x200UL)              /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
36448 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO72_Pos (8UL)                  /*!< DSP0N0GPIO72 (Bit 8)                                  */
36449 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO72_Msk (0x100UL)              /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
36450 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO71_Pos (7UL)                  /*!< DSP0N0GPIO71 (Bit 7)                                  */
36451 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO71_Msk (0x80UL)               /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
36452 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO70_Pos (6UL)                  /*!< DSP0N0GPIO70 (Bit 6)                                  */
36453 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO70_Msk (0x40UL)               /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
36454 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO69_Pos (5UL)                  /*!< DSP0N0GPIO69 (Bit 5)                                  */
36455 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO69_Msk (0x20UL)               /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
36456 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO68_Pos (4UL)                  /*!< DSP0N0GPIO68 (Bit 4)                                  */
36457 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO68_Msk (0x10UL)               /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
36458 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO67_Pos (3UL)                  /*!< DSP0N0GPIO67 (Bit 3)                                  */
36459 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO67_Msk (0x8UL)                /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
36460 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO66_Pos (2UL)                  /*!< DSP0N0GPIO66 (Bit 2)                                  */
36461 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO66_Msk (0x4UL)                /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
36462 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO65_Pos (1UL)                  /*!< DSP0N0GPIO65 (Bit 1)                                  */
36463 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO65_Msk (0x2UL)                /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
36464 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO64_Pos (0UL)                  /*!< DSP0N0GPIO64 (Bit 0)                                  */
36465 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO64_Msk (0x1UL)                /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
36466 /* =====================================================  DSP0N0INT2CLR  ===================================================== */
36467 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO95_Pos (31UL)                  /*!< DSP0N0GPIO95 (Bit 31)                                 */
36468 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO95_Msk (0x80000000UL)          /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
36469 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO94_Pos (30UL)                  /*!< DSP0N0GPIO94 (Bit 30)                                 */
36470 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO94_Msk (0x40000000UL)          /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
36471 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO93_Pos (29UL)                  /*!< DSP0N0GPIO93 (Bit 29)                                 */
36472 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO93_Msk (0x20000000UL)          /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
36473 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO92_Pos (28UL)                  /*!< DSP0N0GPIO92 (Bit 28)                                 */
36474 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO92_Msk (0x10000000UL)          /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
36475 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO91_Pos (27UL)                  /*!< DSP0N0GPIO91 (Bit 27)                                 */
36476 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO91_Msk (0x8000000UL)           /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
36477 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO90_Pos (26UL)                  /*!< DSP0N0GPIO90 (Bit 26)                                 */
36478 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO90_Msk (0x4000000UL)           /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
36479 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO89_Pos (25UL)                  /*!< DSP0N0GPIO89 (Bit 25)                                 */
36480 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO89_Msk (0x2000000UL)           /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
36481 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO88_Pos (24UL)                  /*!< DSP0N0GPIO88 (Bit 24)                                 */
36482 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO88_Msk (0x1000000UL)           /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
36483 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO87_Pos (23UL)                  /*!< DSP0N0GPIO87 (Bit 23)                                 */
36484 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO87_Msk (0x800000UL)            /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
36485 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO86_Pos (22UL)                  /*!< DSP0N0GPIO86 (Bit 22)                                 */
36486 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO86_Msk (0x400000UL)            /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
36487 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO85_Pos (21UL)                  /*!< DSP0N0GPIO85 (Bit 21)                                 */
36488 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO85_Msk (0x200000UL)            /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
36489 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO84_Pos (20UL)                  /*!< DSP0N0GPIO84 (Bit 20)                                 */
36490 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO84_Msk (0x100000UL)            /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
36491 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO83_Pos (19UL)                  /*!< DSP0N0GPIO83 (Bit 19)                                 */
36492 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO83_Msk (0x80000UL)             /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
36493 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO82_Pos (18UL)                  /*!< DSP0N0GPIO82 (Bit 18)                                 */
36494 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO82_Msk (0x40000UL)             /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
36495 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO81_Pos (17UL)                  /*!< DSP0N0GPIO81 (Bit 17)                                 */
36496 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO81_Msk (0x20000UL)             /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
36497 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO80_Pos (16UL)                  /*!< DSP0N0GPIO80 (Bit 16)                                 */
36498 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO80_Msk (0x10000UL)             /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
36499 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO79_Pos (15UL)                  /*!< DSP0N0GPIO79 (Bit 15)                                 */
36500 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO79_Msk (0x8000UL)              /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
36501 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO78_Pos (14UL)                  /*!< DSP0N0GPIO78 (Bit 14)                                 */
36502 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO78_Msk (0x4000UL)              /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
36503 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO77_Pos (13UL)                  /*!< DSP0N0GPIO77 (Bit 13)                                 */
36504 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO77_Msk (0x2000UL)              /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
36505 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO76_Pos (12UL)                  /*!< DSP0N0GPIO76 (Bit 12)                                 */
36506 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO76_Msk (0x1000UL)              /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
36507 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO75_Pos (11UL)                  /*!< DSP0N0GPIO75 (Bit 11)                                 */
36508 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO75_Msk (0x800UL)               /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
36509 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO74_Pos (10UL)                  /*!< DSP0N0GPIO74 (Bit 10)                                 */
36510 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO74_Msk (0x400UL)               /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
36511 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO73_Pos (9UL)                   /*!< DSP0N0GPIO73 (Bit 9)                                  */
36512 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO73_Msk (0x200UL)               /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
36513 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO72_Pos (8UL)                   /*!< DSP0N0GPIO72 (Bit 8)                                  */
36514 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO72_Msk (0x100UL)               /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
36515 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO71_Pos (7UL)                   /*!< DSP0N0GPIO71 (Bit 7)                                  */
36516 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO71_Msk (0x80UL)                /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
36517 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO70_Pos (6UL)                   /*!< DSP0N0GPIO70 (Bit 6)                                  */
36518 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO70_Msk (0x40UL)                /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
36519 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO69_Pos (5UL)                   /*!< DSP0N0GPIO69 (Bit 5)                                  */
36520 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO69_Msk (0x20UL)                /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
36521 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO68_Pos (4UL)                   /*!< DSP0N0GPIO68 (Bit 4)                                  */
36522 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO68_Msk (0x10UL)                /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
36523 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO67_Pos (3UL)                   /*!< DSP0N0GPIO67 (Bit 3)                                  */
36524 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO67_Msk (0x8UL)                 /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
36525 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO66_Pos (2UL)                   /*!< DSP0N0GPIO66 (Bit 2)                                  */
36526 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO66_Msk (0x4UL)                 /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
36527 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO65_Pos (1UL)                   /*!< DSP0N0GPIO65 (Bit 1)                                  */
36528 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO65_Msk (0x2UL)                 /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
36529 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO64_Pos (0UL)                   /*!< DSP0N0GPIO64 (Bit 0)                                  */
36530 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO64_Msk (0x1UL)                 /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
36531 /* =====================================================  DSP0N0INT2SET  ===================================================== */
36532 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO95_Pos (31UL)                  /*!< DSP0N0GPIO95 (Bit 31)                                 */
36533 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO95_Msk (0x80000000UL)          /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
36534 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO94_Pos (30UL)                  /*!< DSP0N0GPIO94 (Bit 30)                                 */
36535 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO94_Msk (0x40000000UL)          /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
36536 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO93_Pos (29UL)                  /*!< DSP0N0GPIO93 (Bit 29)                                 */
36537 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO93_Msk (0x20000000UL)          /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
36538 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO92_Pos (28UL)                  /*!< DSP0N0GPIO92 (Bit 28)                                 */
36539 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO92_Msk (0x10000000UL)          /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
36540 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO91_Pos (27UL)                  /*!< DSP0N0GPIO91 (Bit 27)                                 */
36541 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO91_Msk (0x8000000UL)           /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
36542 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO90_Pos (26UL)                  /*!< DSP0N0GPIO90 (Bit 26)                                 */
36543 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO90_Msk (0x4000000UL)           /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
36544 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO89_Pos (25UL)                  /*!< DSP0N0GPIO89 (Bit 25)                                 */
36545 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO89_Msk (0x2000000UL)           /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
36546 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO88_Pos (24UL)                  /*!< DSP0N0GPIO88 (Bit 24)                                 */
36547 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO88_Msk (0x1000000UL)           /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
36548 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO87_Pos (23UL)                  /*!< DSP0N0GPIO87 (Bit 23)                                 */
36549 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO87_Msk (0x800000UL)            /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
36550 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO86_Pos (22UL)                  /*!< DSP0N0GPIO86 (Bit 22)                                 */
36551 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO86_Msk (0x400000UL)            /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
36552 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO85_Pos (21UL)                  /*!< DSP0N0GPIO85 (Bit 21)                                 */
36553 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO85_Msk (0x200000UL)            /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
36554 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO84_Pos (20UL)                  /*!< DSP0N0GPIO84 (Bit 20)                                 */
36555 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO84_Msk (0x100000UL)            /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
36556 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO83_Pos (19UL)                  /*!< DSP0N0GPIO83 (Bit 19)                                 */
36557 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO83_Msk (0x80000UL)             /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
36558 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO82_Pos (18UL)                  /*!< DSP0N0GPIO82 (Bit 18)                                 */
36559 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO82_Msk (0x40000UL)             /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
36560 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO81_Pos (17UL)                  /*!< DSP0N0GPIO81 (Bit 17)                                 */
36561 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO81_Msk (0x20000UL)             /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
36562 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO80_Pos (16UL)                  /*!< DSP0N0GPIO80 (Bit 16)                                 */
36563 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO80_Msk (0x10000UL)             /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
36564 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO79_Pos (15UL)                  /*!< DSP0N0GPIO79 (Bit 15)                                 */
36565 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO79_Msk (0x8000UL)              /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
36566 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO78_Pos (14UL)                  /*!< DSP0N0GPIO78 (Bit 14)                                 */
36567 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO78_Msk (0x4000UL)              /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
36568 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO77_Pos (13UL)                  /*!< DSP0N0GPIO77 (Bit 13)                                 */
36569 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO77_Msk (0x2000UL)              /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
36570 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO76_Pos (12UL)                  /*!< DSP0N0GPIO76 (Bit 12)                                 */
36571 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO76_Msk (0x1000UL)              /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
36572 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO75_Pos (11UL)                  /*!< DSP0N0GPIO75 (Bit 11)                                 */
36573 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO75_Msk (0x800UL)               /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
36574 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO74_Pos (10UL)                  /*!< DSP0N0GPIO74 (Bit 10)                                 */
36575 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO74_Msk (0x400UL)               /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
36576 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO73_Pos (9UL)                   /*!< DSP0N0GPIO73 (Bit 9)                                  */
36577 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO73_Msk (0x200UL)               /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
36578 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO72_Pos (8UL)                   /*!< DSP0N0GPIO72 (Bit 8)                                  */
36579 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO72_Msk (0x100UL)               /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
36580 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO71_Pos (7UL)                   /*!< DSP0N0GPIO71 (Bit 7)                                  */
36581 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO71_Msk (0x80UL)                /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
36582 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO70_Pos (6UL)                   /*!< DSP0N0GPIO70 (Bit 6)                                  */
36583 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO70_Msk (0x40UL)                /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
36584 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO69_Pos (5UL)                   /*!< DSP0N0GPIO69 (Bit 5)                                  */
36585 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO69_Msk (0x20UL)                /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
36586 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO68_Pos (4UL)                   /*!< DSP0N0GPIO68 (Bit 4)                                  */
36587 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO68_Msk (0x10UL)                /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
36588 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO67_Pos (3UL)                   /*!< DSP0N0GPIO67 (Bit 3)                                  */
36589 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO67_Msk (0x8UL)                 /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
36590 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO66_Pos (2UL)                   /*!< DSP0N0GPIO66 (Bit 2)                                  */
36591 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO66_Msk (0x4UL)                 /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
36592 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO65_Pos (1UL)                   /*!< DSP0N0GPIO65 (Bit 1)                                  */
36593 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO65_Msk (0x2UL)                 /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
36594 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO64_Pos (0UL)                   /*!< DSP0N0GPIO64 (Bit 0)                                  */
36595 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO64_Msk (0x1UL)                 /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
36596 /* =====================================================  DSP0N0INT3EN  ====================================================== */
36597 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO127_Pos (31UL)                  /*!< DSP0N0GPIO127 (Bit 31)                                */
36598 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO127_Msk (0x80000000UL)          /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
36599 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO126_Pos (30UL)                  /*!< DSP0N0GPIO126 (Bit 30)                                */
36600 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO126_Msk (0x40000000UL)          /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
36601 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO125_Pos (29UL)                  /*!< DSP0N0GPIO125 (Bit 29)                                */
36602 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO125_Msk (0x20000000UL)          /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
36603 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO124_Pos (28UL)                  /*!< DSP0N0GPIO124 (Bit 28)                                */
36604 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO124_Msk (0x10000000UL)          /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
36605 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO123_Pos (27UL)                  /*!< DSP0N0GPIO123 (Bit 27)                                */
36606 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO123_Msk (0x8000000UL)           /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
36607 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO122_Pos (26UL)                  /*!< DSP0N0GPIO122 (Bit 26)                                */
36608 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO122_Msk (0x4000000UL)           /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
36609 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO121_Pos (25UL)                  /*!< DSP0N0GPIO121 (Bit 25)                                */
36610 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO121_Msk (0x2000000UL)           /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
36611 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO120_Pos (24UL)                  /*!< DSP0N0GPIO120 (Bit 24)                                */
36612 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO120_Msk (0x1000000UL)           /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
36613 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO119_Pos (23UL)                  /*!< DSP0N0GPIO119 (Bit 23)                                */
36614 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO119_Msk (0x800000UL)            /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
36615 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO118_Pos (22UL)                  /*!< DSP0N0GPIO118 (Bit 22)                                */
36616 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO118_Msk (0x400000UL)            /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
36617 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO117_Pos (21UL)                  /*!< DSP0N0GPIO117 (Bit 21)                                */
36618 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO117_Msk (0x200000UL)            /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
36619 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO116_Pos (20UL)                  /*!< DSP0N0GPIO116 (Bit 20)                                */
36620 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO116_Msk (0x100000UL)            /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
36621 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO115_Pos (19UL)                  /*!< DSP0N0GPIO115 (Bit 19)                                */
36622 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO115_Msk (0x80000UL)             /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
36623 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO114_Pos (18UL)                  /*!< DSP0N0GPIO114 (Bit 18)                                */
36624 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO114_Msk (0x40000UL)             /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
36625 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO113_Pos (17UL)                  /*!< DSP0N0GPIO113 (Bit 17)                                */
36626 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO113_Msk (0x20000UL)             /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
36627 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO112_Pos (16UL)                  /*!< DSP0N0GPIO112 (Bit 16)                                */
36628 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO112_Msk (0x10000UL)             /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
36629 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO111_Pos (15UL)                  /*!< DSP0N0GPIO111 (Bit 15)                                */
36630 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO111_Msk (0x8000UL)              /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
36631 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO110_Pos (14UL)                  /*!< DSP0N0GPIO110 (Bit 14)                                */
36632 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO110_Msk (0x4000UL)              /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
36633 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO109_Pos (13UL)                  /*!< DSP0N0GPIO109 (Bit 13)                                */
36634 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO109_Msk (0x2000UL)              /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
36635 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO108_Pos (12UL)                  /*!< DSP0N0GPIO108 (Bit 12)                                */
36636 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO108_Msk (0x1000UL)              /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
36637 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO107_Pos (11UL)                  /*!< DSP0N0GPIO107 (Bit 11)                                */
36638 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO107_Msk (0x800UL)               /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
36639 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO106_Pos (10UL)                  /*!< DSP0N0GPIO106 (Bit 10)                                */
36640 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO106_Msk (0x400UL)               /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
36641 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO105_Pos (9UL)                   /*!< DSP0N0GPIO105 (Bit 9)                                 */
36642 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO105_Msk (0x200UL)               /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
36643 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO104_Pos (8UL)                   /*!< DSP0N0GPIO104 (Bit 8)                                 */
36644 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO104_Msk (0x100UL)               /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
36645 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO103_Pos (7UL)                   /*!< DSP0N0GPIO103 (Bit 7)                                 */
36646 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO103_Msk (0x80UL)                /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
36647 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO102_Pos (6UL)                   /*!< DSP0N0GPIO102 (Bit 6)                                 */
36648 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO102_Msk (0x40UL)                /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
36649 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO101_Pos (5UL)                   /*!< DSP0N0GPIO101 (Bit 5)                                 */
36650 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO101_Msk (0x20UL)                /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
36651 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO100_Pos (4UL)                   /*!< DSP0N0GPIO100 (Bit 4)                                 */
36652 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO100_Msk (0x10UL)                /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
36653 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO99_Pos (3UL)                    /*!< DSP0N0GPIO99 (Bit 3)                                  */
36654 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO99_Msk (0x8UL)                  /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
36655 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO98_Pos (2UL)                    /*!< DSP0N0GPIO98 (Bit 2)                                  */
36656 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO98_Msk (0x4UL)                  /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
36657 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO97_Pos (1UL)                    /*!< DSP0N0GPIO97 (Bit 1)                                  */
36658 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO97_Msk (0x2UL)                  /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
36659 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO96_Pos (0UL)                    /*!< DSP0N0GPIO96 (Bit 0)                                  */
36660 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO96_Msk (0x1UL)                  /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
36661 /* ====================================================  DSP0N0INT3STAT  ===================================================== */
36662 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO127_Pos (31UL)                /*!< DSP0N0GPIO127 (Bit 31)                                */
36663 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO127_Msk (0x80000000UL)        /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
36664 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO126_Pos (30UL)                /*!< DSP0N0GPIO126 (Bit 30)                                */
36665 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO126_Msk (0x40000000UL)        /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
36666 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO125_Pos (29UL)                /*!< DSP0N0GPIO125 (Bit 29)                                */
36667 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO125_Msk (0x20000000UL)        /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
36668 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO124_Pos (28UL)                /*!< DSP0N0GPIO124 (Bit 28)                                */
36669 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO124_Msk (0x10000000UL)        /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
36670 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO123_Pos (27UL)                /*!< DSP0N0GPIO123 (Bit 27)                                */
36671 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO123_Msk (0x8000000UL)         /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
36672 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO122_Pos (26UL)                /*!< DSP0N0GPIO122 (Bit 26)                                */
36673 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO122_Msk (0x4000000UL)         /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
36674 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO121_Pos (25UL)                /*!< DSP0N0GPIO121 (Bit 25)                                */
36675 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO121_Msk (0x2000000UL)         /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
36676 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO120_Pos (24UL)                /*!< DSP0N0GPIO120 (Bit 24)                                */
36677 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO120_Msk (0x1000000UL)         /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
36678 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO119_Pos (23UL)                /*!< DSP0N0GPIO119 (Bit 23)                                */
36679 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO119_Msk (0x800000UL)          /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
36680 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO118_Pos (22UL)                /*!< DSP0N0GPIO118 (Bit 22)                                */
36681 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO118_Msk (0x400000UL)          /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
36682 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO117_Pos (21UL)                /*!< DSP0N0GPIO117 (Bit 21)                                */
36683 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO117_Msk (0x200000UL)          /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
36684 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO116_Pos (20UL)                /*!< DSP0N0GPIO116 (Bit 20)                                */
36685 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO116_Msk (0x100000UL)          /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
36686 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO115_Pos (19UL)                /*!< DSP0N0GPIO115 (Bit 19)                                */
36687 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO115_Msk (0x80000UL)           /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
36688 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO114_Pos (18UL)                /*!< DSP0N0GPIO114 (Bit 18)                                */
36689 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO114_Msk (0x40000UL)           /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
36690 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO113_Pos (17UL)                /*!< DSP0N0GPIO113 (Bit 17)                                */
36691 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO113_Msk (0x20000UL)           /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
36692 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO112_Pos (16UL)                /*!< DSP0N0GPIO112 (Bit 16)                                */
36693 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO112_Msk (0x10000UL)           /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
36694 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO111_Pos (15UL)                /*!< DSP0N0GPIO111 (Bit 15)                                */
36695 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO111_Msk (0x8000UL)            /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
36696 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO110_Pos (14UL)                /*!< DSP0N0GPIO110 (Bit 14)                                */
36697 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO110_Msk (0x4000UL)            /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
36698 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO109_Pos (13UL)                /*!< DSP0N0GPIO109 (Bit 13)                                */
36699 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO109_Msk (0x2000UL)            /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
36700 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO108_Pos (12UL)                /*!< DSP0N0GPIO108 (Bit 12)                                */
36701 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO108_Msk (0x1000UL)            /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
36702 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO107_Pos (11UL)                /*!< DSP0N0GPIO107 (Bit 11)                                */
36703 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO107_Msk (0x800UL)             /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
36704 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO106_Pos (10UL)                /*!< DSP0N0GPIO106 (Bit 10)                                */
36705 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO106_Msk (0x400UL)             /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
36706 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO105_Pos (9UL)                 /*!< DSP0N0GPIO105 (Bit 9)                                 */
36707 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO105_Msk (0x200UL)             /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
36708 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO104_Pos (8UL)                 /*!< DSP0N0GPIO104 (Bit 8)                                 */
36709 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO104_Msk (0x100UL)             /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
36710 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO103_Pos (7UL)                 /*!< DSP0N0GPIO103 (Bit 7)                                 */
36711 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO103_Msk (0x80UL)              /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
36712 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO102_Pos (6UL)                 /*!< DSP0N0GPIO102 (Bit 6)                                 */
36713 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO102_Msk (0x40UL)              /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
36714 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO101_Pos (5UL)                 /*!< DSP0N0GPIO101 (Bit 5)                                 */
36715 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO101_Msk (0x20UL)              /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
36716 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO100_Pos (4UL)                 /*!< DSP0N0GPIO100 (Bit 4)                                 */
36717 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO100_Msk (0x10UL)              /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
36718 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO99_Pos (3UL)                  /*!< DSP0N0GPIO99 (Bit 3)                                  */
36719 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO99_Msk (0x8UL)                /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
36720 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO98_Pos (2UL)                  /*!< DSP0N0GPIO98 (Bit 2)                                  */
36721 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO98_Msk (0x4UL)                /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
36722 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO97_Pos (1UL)                  /*!< DSP0N0GPIO97 (Bit 1)                                  */
36723 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO97_Msk (0x2UL)                /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
36724 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO96_Pos (0UL)                  /*!< DSP0N0GPIO96 (Bit 0)                                  */
36725 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO96_Msk (0x1UL)                /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
36726 /* =====================================================  DSP0N0INT3CLR  ===================================================== */
36727 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO127_Pos (31UL)                 /*!< DSP0N0GPIO127 (Bit 31)                                */
36728 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO127_Msk (0x80000000UL)         /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
36729 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO126_Pos (30UL)                 /*!< DSP0N0GPIO126 (Bit 30)                                */
36730 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO126_Msk (0x40000000UL)         /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
36731 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO125_Pos (29UL)                 /*!< DSP0N0GPIO125 (Bit 29)                                */
36732 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO125_Msk (0x20000000UL)         /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
36733 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO124_Pos (28UL)                 /*!< DSP0N0GPIO124 (Bit 28)                                */
36734 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO124_Msk (0x10000000UL)         /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
36735 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO123_Pos (27UL)                 /*!< DSP0N0GPIO123 (Bit 27)                                */
36736 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO123_Msk (0x8000000UL)          /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
36737 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO122_Pos (26UL)                 /*!< DSP0N0GPIO122 (Bit 26)                                */
36738 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO122_Msk (0x4000000UL)          /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
36739 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO121_Pos (25UL)                 /*!< DSP0N0GPIO121 (Bit 25)                                */
36740 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO121_Msk (0x2000000UL)          /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
36741 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO120_Pos (24UL)                 /*!< DSP0N0GPIO120 (Bit 24)                                */
36742 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO120_Msk (0x1000000UL)          /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
36743 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO119_Pos (23UL)                 /*!< DSP0N0GPIO119 (Bit 23)                                */
36744 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO119_Msk (0x800000UL)           /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
36745 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO118_Pos (22UL)                 /*!< DSP0N0GPIO118 (Bit 22)                                */
36746 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO118_Msk (0x400000UL)           /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
36747 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO117_Pos (21UL)                 /*!< DSP0N0GPIO117 (Bit 21)                                */
36748 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO117_Msk (0x200000UL)           /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
36749 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO116_Pos (20UL)                 /*!< DSP0N0GPIO116 (Bit 20)                                */
36750 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO116_Msk (0x100000UL)           /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
36751 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO115_Pos (19UL)                 /*!< DSP0N0GPIO115 (Bit 19)                                */
36752 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO115_Msk (0x80000UL)            /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
36753 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO114_Pos (18UL)                 /*!< DSP0N0GPIO114 (Bit 18)                                */
36754 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO114_Msk (0x40000UL)            /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
36755 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO113_Pos (17UL)                 /*!< DSP0N0GPIO113 (Bit 17)                                */
36756 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO113_Msk (0x20000UL)            /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
36757 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO112_Pos (16UL)                 /*!< DSP0N0GPIO112 (Bit 16)                                */
36758 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO112_Msk (0x10000UL)            /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
36759 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO111_Pos (15UL)                 /*!< DSP0N0GPIO111 (Bit 15)                                */
36760 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO111_Msk (0x8000UL)             /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
36761 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO110_Pos (14UL)                 /*!< DSP0N0GPIO110 (Bit 14)                                */
36762 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO110_Msk (0x4000UL)             /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
36763 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO109_Pos (13UL)                 /*!< DSP0N0GPIO109 (Bit 13)                                */
36764 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO109_Msk (0x2000UL)             /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
36765 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO108_Pos (12UL)                 /*!< DSP0N0GPIO108 (Bit 12)                                */
36766 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO108_Msk (0x1000UL)             /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
36767 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO107_Pos (11UL)                 /*!< DSP0N0GPIO107 (Bit 11)                                */
36768 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO107_Msk (0x800UL)              /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
36769 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO106_Pos (10UL)                 /*!< DSP0N0GPIO106 (Bit 10)                                */
36770 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO106_Msk (0x400UL)              /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
36771 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO105_Pos (9UL)                  /*!< DSP0N0GPIO105 (Bit 9)                                 */
36772 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO105_Msk (0x200UL)              /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
36773 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO104_Pos (8UL)                  /*!< DSP0N0GPIO104 (Bit 8)                                 */
36774 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO104_Msk (0x100UL)              /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
36775 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO103_Pos (7UL)                  /*!< DSP0N0GPIO103 (Bit 7)                                 */
36776 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO103_Msk (0x80UL)               /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
36777 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO102_Pos (6UL)                  /*!< DSP0N0GPIO102 (Bit 6)                                 */
36778 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO102_Msk (0x40UL)               /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
36779 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO101_Pos (5UL)                  /*!< DSP0N0GPIO101 (Bit 5)                                 */
36780 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO101_Msk (0x20UL)               /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
36781 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO100_Pos (4UL)                  /*!< DSP0N0GPIO100 (Bit 4)                                 */
36782 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO100_Msk (0x10UL)               /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
36783 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO99_Pos (3UL)                   /*!< DSP0N0GPIO99 (Bit 3)                                  */
36784 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO99_Msk (0x8UL)                 /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
36785 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO98_Pos (2UL)                   /*!< DSP0N0GPIO98 (Bit 2)                                  */
36786 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO98_Msk (0x4UL)                 /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
36787 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO97_Pos (1UL)                   /*!< DSP0N0GPIO97 (Bit 1)                                  */
36788 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO97_Msk (0x2UL)                 /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
36789 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO96_Pos (0UL)                   /*!< DSP0N0GPIO96 (Bit 0)                                  */
36790 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO96_Msk (0x1UL)                 /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
36791 /* =====================================================  DSP0N0INT3SET  ===================================================== */
36792 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO127_Pos (31UL)                 /*!< DSP0N0GPIO127 (Bit 31)                                */
36793 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO127_Msk (0x80000000UL)         /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
36794 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO126_Pos (30UL)                 /*!< DSP0N0GPIO126 (Bit 30)                                */
36795 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO126_Msk (0x40000000UL)         /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
36796 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO125_Pos (29UL)                 /*!< DSP0N0GPIO125 (Bit 29)                                */
36797 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO125_Msk (0x20000000UL)         /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
36798 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO124_Pos (28UL)                 /*!< DSP0N0GPIO124 (Bit 28)                                */
36799 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO124_Msk (0x10000000UL)         /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
36800 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO123_Pos (27UL)                 /*!< DSP0N0GPIO123 (Bit 27)                                */
36801 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO123_Msk (0x8000000UL)          /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
36802 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO122_Pos (26UL)                 /*!< DSP0N0GPIO122 (Bit 26)                                */
36803 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO122_Msk (0x4000000UL)          /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
36804 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO121_Pos (25UL)                 /*!< DSP0N0GPIO121 (Bit 25)                                */
36805 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO121_Msk (0x2000000UL)          /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
36806 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO120_Pos (24UL)                 /*!< DSP0N0GPIO120 (Bit 24)                                */
36807 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO120_Msk (0x1000000UL)          /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
36808 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO119_Pos (23UL)                 /*!< DSP0N0GPIO119 (Bit 23)                                */
36809 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO119_Msk (0x800000UL)           /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
36810 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO118_Pos (22UL)                 /*!< DSP0N0GPIO118 (Bit 22)                                */
36811 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO118_Msk (0x400000UL)           /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
36812 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO117_Pos (21UL)                 /*!< DSP0N0GPIO117 (Bit 21)                                */
36813 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO117_Msk (0x200000UL)           /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
36814 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO116_Pos (20UL)                 /*!< DSP0N0GPIO116 (Bit 20)                                */
36815 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO116_Msk (0x100000UL)           /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
36816 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO115_Pos (19UL)                 /*!< DSP0N0GPIO115 (Bit 19)                                */
36817 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO115_Msk (0x80000UL)            /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
36818 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO114_Pos (18UL)                 /*!< DSP0N0GPIO114 (Bit 18)                                */
36819 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO114_Msk (0x40000UL)            /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
36820 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO113_Pos (17UL)                 /*!< DSP0N0GPIO113 (Bit 17)                                */
36821 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO113_Msk (0x20000UL)            /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
36822 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO112_Pos (16UL)                 /*!< DSP0N0GPIO112 (Bit 16)                                */
36823 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO112_Msk (0x10000UL)            /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
36824 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO111_Pos (15UL)                 /*!< DSP0N0GPIO111 (Bit 15)                                */
36825 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO111_Msk (0x8000UL)             /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
36826 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO110_Pos (14UL)                 /*!< DSP0N0GPIO110 (Bit 14)                                */
36827 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO110_Msk (0x4000UL)             /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
36828 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO109_Pos (13UL)                 /*!< DSP0N0GPIO109 (Bit 13)                                */
36829 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO109_Msk (0x2000UL)             /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
36830 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO108_Pos (12UL)                 /*!< DSP0N0GPIO108 (Bit 12)                                */
36831 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO108_Msk (0x1000UL)             /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
36832 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO107_Pos (11UL)                 /*!< DSP0N0GPIO107 (Bit 11)                                */
36833 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO107_Msk (0x800UL)              /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
36834 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO106_Pos (10UL)                 /*!< DSP0N0GPIO106 (Bit 10)                                */
36835 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO106_Msk (0x400UL)              /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
36836 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO105_Pos (9UL)                  /*!< DSP0N0GPIO105 (Bit 9)                                 */
36837 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO105_Msk (0x200UL)              /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
36838 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO104_Pos (8UL)                  /*!< DSP0N0GPIO104 (Bit 8)                                 */
36839 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO104_Msk (0x100UL)              /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
36840 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO103_Pos (7UL)                  /*!< DSP0N0GPIO103 (Bit 7)                                 */
36841 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO103_Msk (0x80UL)               /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
36842 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO102_Pos (6UL)                  /*!< DSP0N0GPIO102 (Bit 6)                                 */
36843 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO102_Msk (0x40UL)               /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
36844 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO101_Pos (5UL)                  /*!< DSP0N0GPIO101 (Bit 5)                                 */
36845 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO101_Msk (0x20UL)               /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
36846 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO100_Pos (4UL)                  /*!< DSP0N0GPIO100 (Bit 4)                                 */
36847 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO100_Msk (0x10UL)               /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
36848 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO99_Pos (3UL)                   /*!< DSP0N0GPIO99 (Bit 3)                                  */
36849 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO99_Msk (0x8UL)                 /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
36850 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO98_Pos (2UL)                   /*!< DSP0N0GPIO98 (Bit 2)                                  */
36851 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO98_Msk (0x4UL)                 /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
36852 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO97_Pos (1UL)                   /*!< DSP0N0GPIO97 (Bit 1)                                  */
36853 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO97_Msk (0x2UL)                 /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
36854 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO96_Pos (0UL)                   /*!< DSP0N0GPIO96 (Bit 0)                                  */
36855 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO96_Msk (0x1UL)                 /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
36856 /* =====================================================  DSP0N1INT0EN  ====================================================== */
36857 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO31_Pos (31UL)                   /*!< DSP0N1GPIO31 (Bit 31)                                 */
36858 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO31_Msk (0x80000000UL)           /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
36859 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO30_Pos (30UL)                   /*!< DSP0N1GPIO30 (Bit 30)                                 */
36860 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO30_Msk (0x40000000UL)           /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
36861 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO29_Pos (29UL)                   /*!< DSP0N1GPIO29 (Bit 29)                                 */
36862 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO29_Msk (0x20000000UL)           /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
36863 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO28_Pos (28UL)                   /*!< DSP0N1GPIO28 (Bit 28)                                 */
36864 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO28_Msk (0x10000000UL)           /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
36865 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO27_Pos (27UL)                   /*!< DSP0N1GPIO27 (Bit 27)                                 */
36866 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO27_Msk (0x8000000UL)            /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
36867 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO26_Pos (26UL)                   /*!< DSP0N1GPIO26 (Bit 26)                                 */
36868 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO26_Msk (0x4000000UL)            /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
36869 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO25_Pos (25UL)                   /*!< DSP0N1GPIO25 (Bit 25)                                 */
36870 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO25_Msk (0x2000000UL)            /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
36871 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO24_Pos (24UL)                   /*!< DSP0N1GPIO24 (Bit 24)                                 */
36872 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO24_Msk (0x1000000UL)            /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
36873 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO23_Pos (23UL)                   /*!< DSP0N1GPIO23 (Bit 23)                                 */
36874 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO23_Msk (0x800000UL)             /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
36875 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO22_Pos (22UL)                   /*!< DSP0N1GPIO22 (Bit 22)                                 */
36876 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO22_Msk (0x400000UL)             /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
36877 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO21_Pos (21UL)                   /*!< DSP0N1GPIO21 (Bit 21)                                 */
36878 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO21_Msk (0x200000UL)             /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
36879 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO20_Pos (20UL)                   /*!< DSP0N1GPIO20 (Bit 20)                                 */
36880 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO20_Msk (0x100000UL)             /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
36881 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO19_Pos (19UL)                   /*!< DSP0N1GPIO19 (Bit 19)                                 */
36882 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO19_Msk (0x80000UL)              /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
36883 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO18_Pos (18UL)                   /*!< DSP0N1GPIO18 (Bit 18)                                 */
36884 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO18_Msk (0x40000UL)              /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
36885 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO17_Pos (17UL)                   /*!< DSP0N1GPIO17 (Bit 17)                                 */
36886 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO17_Msk (0x20000UL)              /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
36887 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO16_Pos (16UL)                   /*!< DSP0N1GPIO16 (Bit 16)                                 */
36888 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO16_Msk (0x10000UL)              /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
36889 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO15_Pos (15UL)                   /*!< DSP0N1GPIO15 (Bit 15)                                 */
36890 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO15_Msk (0x8000UL)               /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
36891 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO14_Pos (14UL)                   /*!< DSP0N1GPIO14 (Bit 14)                                 */
36892 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO14_Msk (0x4000UL)               /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
36893 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO13_Pos (13UL)                   /*!< DSP0N1GPIO13 (Bit 13)                                 */
36894 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO13_Msk (0x2000UL)               /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
36895 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO12_Pos (12UL)                   /*!< DSP0N1GPIO12 (Bit 12)                                 */
36896 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO12_Msk (0x1000UL)               /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
36897 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO11_Pos (11UL)                   /*!< DSP0N1GPIO11 (Bit 11)                                 */
36898 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO11_Msk (0x800UL)                /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
36899 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO10_Pos (10UL)                   /*!< DSP0N1GPIO10 (Bit 10)                                 */
36900 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO10_Msk (0x400UL)                /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
36901 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO9_Pos (9UL)                     /*!< DSP0N1GPIO9 (Bit 9)                                   */
36902 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO9_Msk (0x200UL)                 /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
36903 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO8_Pos (8UL)                     /*!< DSP0N1GPIO8 (Bit 8)                                   */
36904 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO8_Msk (0x100UL)                 /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
36905 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO7_Pos (7UL)                     /*!< DSP0N1GPIO7 (Bit 7)                                   */
36906 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO7_Msk (0x80UL)                  /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
36907 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO6_Pos (6UL)                     /*!< DSP0N1GPIO6 (Bit 6)                                   */
36908 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO6_Msk (0x40UL)                  /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
36909 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO5_Pos (5UL)                     /*!< DSP0N1GPIO5 (Bit 5)                                   */
36910 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO5_Msk (0x20UL)                  /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
36911 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO4_Pos (4UL)                     /*!< DSP0N1GPIO4 (Bit 4)                                   */
36912 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO4_Msk (0x10UL)                  /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
36913 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO3_Pos (3UL)                     /*!< DSP0N1GPIO3 (Bit 3)                                   */
36914 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO3_Msk (0x8UL)                   /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
36915 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO2_Pos (2UL)                     /*!< DSP0N1GPIO2 (Bit 2)                                   */
36916 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO2_Msk (0x4UL)                   /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
36917 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO1_Pos (1UL)                     /*!< DSP0N1GPIO1 (Bit 1)                                   */
36918 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO1_Msk (0x2UL)                   /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
36919 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO0_Pos (0UL)                     /*!< DSP0N1GPIO0 (Bit 0)                                   */
36920 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO0_Msk (0x1UL)                   /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
36921 /* ====================================================  DSP0N1INT0STAT  ===================================================== */
36922 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO31_Pos (31UL)                 /*!< DSP0N1GPIO31 (Bit 31)                                 */
36923 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO31_Msk (0x80000000UL)         /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
36924 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO30_Pos (30UL)                 /*!< DSP0N1GPIO30 (Bit 30)                                 */
36925 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO30_Msk (0x40000000UL)         /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
36926 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO29_Pos (29UL)                 /*!< DSP0N1GPIO29 (Bit 29)                                 */
36927 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO29_Msk (0x20000000UL)         /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
36928 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO28_Pos (28UL)                 /*!< DSP0N1GPIO28 (Bit 28)                                 */
36929 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO28_Msk (0x10000000UL)         /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
36930 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO27_Pos (27UL)                 /*!< DSP0N1GPIO27 (Bit 27)                                 */
36931 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO27_Msk (0x8000000UL)          /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
36932 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO26_Pos (26UL)                 /*!< DSP0N1GPIO26 (Bit 26)                                 */
36933 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO26_Msk (0x4000000UL)          /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
36934 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO25_Pos (25UL)                 /*!< DSP0N1GPIO25 (Bit 25)                                 */
36935 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO25_Msk (0x2000000UL)          /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
36936 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO24_Pos (24UL)                 /*!< DSP0N1GPIO24 (Bit 24)                                 */
36937 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO24_Msk (0x1000000UL)          /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
36938 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO23_Pos (23UL)                 /*!< DSP0N1GPIO23 (Bit 23)                                 */
36939 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO23_Msk (0x800000UL)           /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
36940 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO22_Pos (22UL)                 /*!< DSP0N1GPIO22 (Bit 22)                                 */
36941 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO22_Msk (0x400000UL)           /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
36942 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO21_Pos (21UL)                 /*!< DSP0N1GPIO21 (Bit 21)                                 */
36943 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO21_Msk (0x200000UL)           /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
36944 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO20_Pos (20UL)                 /*!< DSP0N1GPIO20 (Bit 20)                                 */
36945 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO20_Msk (0x100000UL)           /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
36946 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO19_Pos (19UL)                 /*!< DSP0N1GPIO19 (Bit 19)                                 */
36947 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO19_Msk (0x80000UL)            /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
36948 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO18_Pos (18UL)                 /*!< DSP0N1GPIO18 (Bit 18)                                 */
36949 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO18_Msk (0x40000UL)            /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
36950 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO17_Pos (17UL)                 /*!< DSP0N1GPIO17 (Bit 17)                                 */
36951 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO17_Msk (0x20000UL)            /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
36952 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO16_Pos (16UL)                 /*!< DSP0N1GPIO16 (Bit 16)                                 */
36953 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO16_Msk (0x10000UL)            /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
36954 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO15_Pos (15UL)                 /*!< DSP0N1GPIO15 (Bit 15)                                 */
36955 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO15_Msk (0x8000UL)             /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
36956 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO14_Pos (14UL)                 /*!< DSP0N1GPIO14 (Bit 14)                                 */
36957 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO14_Msk (0x4000UL)             /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
36958 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO13_Pos (13UL)                 /*!< DSP0N1GPIO13 (Bit 13)                                 */
36959 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO13_Msk (0x2000UL)             /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
36960 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO12_Pos (12UL)                 /*!< DSP0N1GPIO12 (Bit 12)                                 */
36961 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO12_Msk (0x1000UL)             /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
36962 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO11_Pos (11UL)                 /*!< DSP0N1GPIO11 (Bit 11)                                 */
36963 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO11_Msk (0x800UL)              /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
36964 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO10_Pos (10UL)                 /*!< DSP0N1GPIO10 (Bit 10)                                 */
36965 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO10_Msk (0x400UL)              /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
36966 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO9_Pos (9UL)                   /*!< DSP0N1GPIO9 (Bit 9)                                   */
36967 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO9_Msk (0x200UL)               /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
36968 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO8_Pos (8UL)                   /*!< DSP0N1GPIO8 (Bit 8)                                   */
36969 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO8_Msk (0x100UL)               /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
36970 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO7_Pos (7UL)                   /*!< DSP0N1GPIO7 (Bit 7)                                   */
36971 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO7_Msk (0x80UL)                /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
36972 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO6_Pos (6UL)                   /*!< DSP0N1GPIO6 (Bit 6)                                   */
36973 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO6_Msk (0x40UL)                /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
36974 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO5_Pos (5UL)                   /*!< DSP0N1GPIO5 (Bit 5)                                   */
36975 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO5_Msk (0x20UL)                /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
36976 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO4_Pos (4UL)                   /*!< DSP0N1GPIO4 (Bit 4)                                   */
36977 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO4_Msk (0x10UL)                /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
36978 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO3_Pos (3UL)                   /*!< DSP0N1GPIO3 (Bit 3)                                   */
36979 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO3_Msk (0x8UL)                 /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
36980 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO2_Pos (2UL)                   /*!< DSP0N1GPIO2 (Bit 2)                                   */
36981 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO2_Msk (0x4UL)                 /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
36982 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO1_Pos (1UL)                   /*!< DSP0N1GPIO1 (Bit 1)                                   */
36983 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO1_Msk (0x2UL)                 /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
36984 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO0_Pos (0UL)                   /*!< DSP0N1GPIO0 (Bit 0)                                   */
36985 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO0_Msk (0x1UL)                 /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
36986 /* =====================================================  DSP0N1INT0CLR  ===================================================== */
36987 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO31_Pos (31UL)                  /*!< DSP0N1GPIO31 (Bit 31)                                 */
36988 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO31_Msk (0x80000000UL)          /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
36989 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO30_Pos (30UL)                  /*!< DSP0N1GPIO30 (Bit 30)                                 */
36990 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO30_Msk (0x40000000UL)          /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
36991 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO29_Pos (29UL)                  /*!< DSP0N1GPIO29 (Bit 29)                                 */
36992 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO29_Msk (0x20000000UL)          /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
36993 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO28_Pos (28UL)                  /*!< DSP0N1GPIO28 (Bit 28)                                 */
36994 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO28_Msk (0x10000000UL)          /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
36995 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO27_Pos (27UL)                  /*!< DSP0N1GPIO27 (Bit 27)                                 */
36996 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO27_Msk (0x8000000UL)           /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
36997 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO26_Pos (26UL)                  /*!< DSP0N1GPIO26 (Bit 26)                                 */
36998 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO26_Msk (0x4000000UL)           /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
36999 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO25_Pos (25UL)                  /*!< DSP0N1GPIO25 (Bit 25)                                 */
37000 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO25_Msk (0x2000000UL)           /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
37001 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO24_Pos (24UL)                  /*!< DSP0N1GPIO24 (Bit 24)                                 */
37002 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO24_Msk (0x1000000UL)           /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
37003 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO23_Pos (23UL)                  /*!< DSP0N1GPIO23 (Bit 23)                                 */
37004 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO23_Msk (0x800000UL)            /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
37005 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO22_Pos (22UL)                  /*!< DSP0N1GPIO22 (Bit 22)                                 */
37006 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO22_Msk (0x400000UL)            /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
37007 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO21_Pos (21UL)                  /*!< DSP0N1GPIO21 (Bit 21)                                 */
37008 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO21_Msk (0x200000UL)            /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
37009 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO20_Pos (20UL)                  /*!< DSP0N1GPIO20 (Bit 20)                                 */
37010 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO20_Msk (0x100000UL)            /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
37011 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO19_Pos (19UL)                  /*!< DSP0N1GPIO19 (Bit 19)                                 */
37012 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO19_Msk (0x80000UL)             /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
37013 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO18_Pos (18UL)                  /*!< DSP0N1GPIO18 (Bit 18)                                 */
37014 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO18_Msk (0x40000UL)             /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
37015 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO17_Pos (17UL)                  /*!< DSP0N1GPIO17 (Bit 17)                                 */
37016 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO17_Msk (0x20000UL)             /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
37017 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO16_Pos (16UL)                  /*!< DSP0N1GPIO16 (Bit 16)                                 */
37018 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO16_Msk (0x10000UL)             /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
37019 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO15_Pos (15UL)                  /*!< DSP0N1GPIO15 (Bit 15)                                 */
37020 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO15_Msk (0x8000UL)              /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
37021 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO14_Pos (14UL)                  /*!< DSP0N1GPIO14 (Bit 14)                                 */
37022 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO14_Msk (0x4000UL)              /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
37023 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO13_Pos (13UL)                  /*!< DSP0N1GPIO13 (Bit 13)                                 */
37024 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO13_Msk (0x2000UL)              /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
37025 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO12_Pos (12UL)                  /*!< DSP0N1GPIO12 (Bit 12)                                 */
37026 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO12_Msk (0x1000UL)              /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
37027 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO11_Pos (11UL)                  /*!< DSP0N1GPIO11 (Bit 11)                                 */
37028 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO11_Msk (0x800UL)               /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
37029 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO10_Pos (10UL)                  /*!< DSP0N1GPIO10 (Bit 10)                                 */
37030 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO10_Msk (0x400UL)               /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
37031 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO9_Pos (9UL)                    /*!< DSP0N1GPIO9 (Bit 9)                                   */
37032 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO9_Msk (0x200UL)                /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
37033 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO8_Pos (8UL)                    /*!< DSP0N1GPIO8 (Bit 8)                                   */
37034 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO8_Msk (0x100UL)                /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
37035 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO7_Pos (7UL)                    /*!< DSP0N1GPIO7 (Bit 7)                                   */
37036 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO7_Msk (0x80UL)                 /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
37037 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO6_Pos (6UL)                    /*!< DSP0N1GPIO6 (Bit 6)                                   */
37038 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO6_Msk (0x40UL)                 /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
37039 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO5_Pos (5UL)                    /*!< DSP0N1GPIO5 (Bit 5)                                   */
37040 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO5_Msk (0x20UL)                 /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
37041 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO4_Pos (4UL)                    /*!< DSP0N1GPIO4 (Bit 4)                                   */
37042 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO4_Msk (0x10UL)                 /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
37043 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO3_Pos (3UL)                    /*!< DSP0N1GPIO3 (Bit 3)                                   */
37044 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO3_Msk (0x8UL)                  /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
37045 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO2_Pos (2UL)                    /*!< DSP0N1GPIO2 (Bit 2)                                   */
37046 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO2_Msk (0x4UL)                  /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
37047 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO1_Pos (1UL)                    /*!< DSP0N1GPIO1 (Bit 1)                                   */
37048 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO1_Msk (0x2UL)                  /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
37049 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO0_Pos (0UL)                    /*!< DSP0N1GPIO0 (Bit 0)                                   */
37050 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO0_Msk (0x1UL)                  /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
37051 /* =====================================================  DSP0N1INT0SET  ===================================================== */
37052 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO31_Pos (31UL)                  /*!< DSP0N1GPIO31 (Bit 31)                                 */
37053 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO31_Msk (0x80000000UL)          /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
37054 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO30_Pos (30UL)                  /*!< DSP0N1GPIO30 (Bit 30)                                 */
37055 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO30_Msk (0x40000000UL)          /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
37056 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO29_Pos (29UL)                  /*!< DSP0N1GPIO29 (Bit 29)                                 */
37057 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO29_Msk (0x20000000UL)          /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
37058 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO28_Pos (28UL)                  /*!< DSP0N1GPIO28 (Bit 28)                                 */
37059 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO28_Msk (0x10000000UL)          /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
37060 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO27_Pos (27UL)                  /*!< DSP0N1GPIO27 (Bit 27)                                 */
37061 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO27_Msk (0x8000000UL)           /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
37062 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO26_Pos (26UL)                  /*!< DSP0N1GPIO26 (Bit 26)                                 */
37063 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO26_Msk (0x4000000UL)           /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
37064 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO25_Pos (25UL)                  /*!< DSP0N1GPIO25 (Bit 25)                                 */
37065 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO25_Msk (0x2000000UL)           /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
37066 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO24_Pos (24UL)                  /*!< DSP0N1GPIO24 (Bit 24)                                 */
37067 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO24_Msk (0x1000000UL)           /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
37068 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO23_Pos (23UL)                  /*!< DSP0N1GPIO23 (Bit 23)                                 */
37069 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO23_Msk (0x800000UL)            /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
37070 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO22_Pos (22UL)                  /*!< DSP0N1GPIO22 (Bit 22)                                 */
37071 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO22_Msk (0x400000UL)            /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
37072 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO21_Pos (21UL)                  /*!< DSP0N1GPIO21 (Bit 21)                                 */
37073 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO21_Msk (0x200000UL)            /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
37074 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO20_Pos (20UL)                  /*!< DSP0N1GPIO20 (Bit 20)                                 */
37075 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO20_Msk (0x100000UL)            /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
37076 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO19_Pos (19UL)                  /*!< DSP0N1GPIO19 (Bit 19)                                 */
37077 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO19_Msk (0x80000UL)             /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
37078 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO18_Pos (18UL)                  /*!< DSP0N1GPIO18 (Bit 18)                                 */
37079 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO18_Msk (0x40000UL)             /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
37080 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO17_Pos (17UL)                  /*!< DSP0N1GPIO17 (Bit 17)                                 */
37081 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO17_Msk (0x20000UL)             /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
37082 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO16_Pos (16UL)                  /*!< DSP0N1GPIO16 (Bit 16)                                 */
37083 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO16_Msk (0x10000UL)             /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
37084 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO15_Pos (15UL)                  /*!< DSP0N1GPIO15 (Bit 15)                                 */
37085 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO15_Msk (0x8000UL)              /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
37086 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO14_Pos (14UL)                  /*!< DSP0N1GPIO14 (Bit 14)                                 */
37087 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO14_Msk (0x4000UL)              /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
37088 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO13_Pos (13UL)                  /*!< DSP0N1GPIO13 (Bit 13)                                 */
37089 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO13_Msk (0x2000UL)              /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
37090 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO12_Pos (12UL)                  /*!< DSP0N1GPIO12 (Bit 12)                                 */
37091 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO12_Msk (0x1000UL)              /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
37092 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO11_Pos (11UL)                  /*!< DSP0N1GPIO11 (Bit 11)                                 */
37093 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO11_Msk (0x800UL)               /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
37094 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO10_Pos (10UL)                  /*!< DSP0N1GPIO10 (Bit 10)                                 */
37095 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO10_Msk (0x400UL)               /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
37096 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO9_Pos (9UL)                    /*!< DSP0N1GPIO9 (Bit 9)                                   */
37097 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO9_Msk (0x200UL)                /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
37098 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO8_Pos (8UL)                    /*!< DSP0N1GPIO8 (Bit 8)                                   */
37099 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO8_Msk (0x100UL)                /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
37100 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO7_Pos (7UL)                    /*!< DSP0N1GPIO7 (Bit 7)                                   */
37101 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO7_Msk (0x80UL)                 /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
37102 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO6_Pos (6UL)                    /*!< DSP0N1GPIO6 (Bit 6)                                   */
37103 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO6_Msk (0x40UL)                 /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
37104 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO5_Pos (5UL)                    /*!< DSP0N1GPIO5 (Bit 5)                                   */
37105 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO5_Msk (0x20UL)                 /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
37106 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO4_Pos (4UL)                    /*!< DSP0N1GPIO4 (Bit 4)                                   */
37107 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO4_Msk (0x10UL)                 /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
37108 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO3_Pos (3UL)                    /*!< DSP0N1GPIO3 (Bit 3)                                   */
37109 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO3_Msk (0x8UL)                  /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
37110 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO2_Pos (2UL)                    /*!< DSP0N1GPIO2 (Bit 2)                                   */
37111 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO2_Msk (0x4UL)                  /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
37112 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO1_Pos (1UL)                    /*!< DSP0N1GPIO1 (Bit 1)                                   */
37113 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO1_Msk (0x2UL)                  /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
37114 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO0_Pos (0UL)                    /*!< DSP0N1GPIO0 (Bit 0)                                   */
37115 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO0_Msk (0x1UL)                  /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
37116 /* =====================================================  DSP0N1INT1EN  ====================================================== */
37117 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO63_Pos (31UL)                   /*!< DSP0N1GPIO63 (Bit 31)                                 */
37118 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO63_Msk (0x80000000UL)           /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37119 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO62_Pos (30UL)                   /*!< DSP0N1GPIO62 (Bit 30)                                 */
37120 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO62_Msk (0x40000000UL)           /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37121 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO61_Pos (29UL)                   /*!< DSP0N1GPIO61 (Bit 29)                                 */
37122 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO61_Msk (0x20000000UL)           /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37123 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO60_Pos (28UL)                   /*!< DSP0N1GPIO60 (Bit 28)                                 */
37124 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO60_Msk (0x10000000UL)           /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37125 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO59_Pos (27UL)                   /*!< DSP0N1GPIO59 (Bit 27)                                 */
37126 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO59_Msk (0x8000000UL)            /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37127 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO58_Pos (26UL)                   /*!< DSP0N1GPIO58 (Bit 26)                                 */
37128 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO58_Msk (0x4000000UL)            /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37129 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO57_Pos (25UL)                   /*!< DSP0N1GPIO57 (Bit 25)                                 */
37130 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO57_Msk (0x2000000UL)            /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37131 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO56_Pos (24UL)                   /*!< DSP0N1GPIO56 (Bit 24)                                 */
37132 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO56_Msk (0x1000000UL)            /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37133 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO55_Pos (23UL)                   /*!< DSP0N1GPIO55 (Bit 23)                                 */
37134 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO55_Msk (0x800000UL)             /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37135 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO54_Pos (22UL)                   /*!< DSP0N1GPIO54 (Bit 22)                                 */
37136 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO54_Msk (0x400000UL)             /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37137 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO53_Pos (21UL)                   /*!< DSP0N1GPIO53 (Bit 21)                                 */
37138 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO53_Msk (0x200000UL)             /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37139 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO52_Pos (20UL)                   /*!< DSP0N1GPIO52 (Bit 20)                                 */
37140 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO52_Msk (0x100000UL)             /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37141 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO51_Pos (19UL)                   /*!< DSP0N1GPIO51 (Bit 19)                                 */
37142 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO51_Msk (0x80000UL)              /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37143 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO50_Pos (18UL)                   /*!< DSP0N1GPIO50 (Bit 18)                                 */
37144 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO50_Msk (0x40000UL)              /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37145 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO49_Pos (17UL)                   /*!< DSP0N1GPIO49 (Bit 17)                                 */
37146 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO49_Msk (0x20000UL)              /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37147 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO48_Pos (16UL)                   /*!< DSP0N1GPIO48 (Bit 16)                                 */
37148 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO48_Msk (0x10000UL)              /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37149 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO47_Pos (15UL)                   /*!< DSP0N1GPIO47 (Bit 15)                                 */
37150 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO47_Msk (0x8000UL)               /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37151 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO46_Pos (14UL)                   /*!< DSP0N1GPIO46 (Bit 14)                                 */
37152 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO46_Msk (0x4000UL)               /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37153 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO45_Pos (13UL)                   /*!< DSP0N1GPIO45 (Bit 13)                                 */
37154 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO45_Msk (0x2000UL)               /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37155 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO44_Pos (12UL)                   /*!< DSP0N1GPIO44 (Bit 12)                                 */
37156 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO44_Msk (0x1000UL)               /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37157 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO43_Pos (11UL)                   /*!< DSP0N1GPIO43 (Bit 11)                                 */
37158 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO43_Msk (0x800UL)                /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37159 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO42_Pos (10UL)                   /*!< DSP0N1GPIO42 (Bit 10)                                 */
37160 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO42_Msk (0x400UL)                /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37161 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO41_Pos (9UL)                    /*!< DSP0N1GPIO41 (Bit 9)                                  */
37162 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO41_Msk (0x200UL)                /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37163 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO40_Pos (8UL)                    /*!< DSP0N1GPIO40 (Bit 8)                                  */
37164 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO40_Msk (0x100UL)                /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37165 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO39_Pos (7UL)                    /*!< DSP0N1GPIO39 (Bit 7)                                  */
37166 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO39_Msk (0x80UL)                 /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37167 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO38_Pos (6UL)                    /*!< DSP0N1GPIO38 (Bit 6)                                  */
37168 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO38_Msk (0x40UL)                 /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37169 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO37_Pos (5UL)                    /*!< DSP0N1GPIO37 (Bit 5)                                  */
37170 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO37_Msk (0x20UL)                 /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37171 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO36_Pos (4UL)                    /*!< DSP0N1GPIO36 (Bit 4)                                  */
37172 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO36_Msk (0x10UL)                 /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37173 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO35_Pos (3UL)                    /*!< DSP0N1GPIO35 (Bit 3)                                  */
37174 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO35_Msk (0x8UL)                  /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37175 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO34_Pos (2UL)                    /*!< DSP0N1GPIO34 (Bit 2)                                  */
37176 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO34_Msk (0x4UL)                  /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37177 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO33_Pos (1UL)                    /*!< DSP0N1GPIO33 (Bit 1)                                  */
37178 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO33_Msk (0x2UL)                  /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37179 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO32_Pos (0UL)                    /*!< DSP0N1GPIO32 (Bit 0)                                  */
37180 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO32_Msk (0x1UL)                  /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37181 /* ====================================================  DSP0N1INT1STAT  ===================================================== */
37182 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO63_Pos (31UL)                 /*!< DSP0N1GPIO63 (Bit 31)                                 */
37183 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO63_Msk (0x80000000UL)         /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37184 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO62_Pos (30UL)                 /*!< DSP0N1GPIO62 (Bit 30)                                 */
37185 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO62_Msk (0x40000000UL)         /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37186 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO61_Pos (29UL)                 /*!< DSP0N1GPIO61 (Bit 29)                                 */
37187 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO61_Msk (0x20000000UL)         /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37188 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO60_Pos (28UL)                 /*!< DSP0N1GPIO60 (Bit 28)                                 */
37189 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO60_Msk (0x10000000UL)         /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37190 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO59_Pos (27UL)                 /*!< DSP0N1GPIO59 (Bit 27)                                 */
37191 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO59_Msk (0x8000000UL)          /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37192 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO58_Pos (26UL)                 /*!< DSP0N1GPIO58 (Bit 26)                                 */
37193 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO58_Msk (0x4000000UL)          /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37194 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO57_Pos (25UL)                 /*!< DSP0N1GPIO57 (Bit 25)                                 */
37195 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO57_Msk (0x2000000UL)          /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37196 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO56_Pos (24UL)                 /*!< DSP0N1GPIO56 (Bit 24)                                 */
37197 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO56_Msk (0x1000000UL)          /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37198 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO55_Pos (23UL)                 /*!< DSP0N1GPIO55 (Bit 23)                                 */
37199 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO55_Msk (0x800000UL)           /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37200 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO54_Pos (22UL)                 /*!< DSP0N1GPIO54 (Bit 22)                                 */
37201 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO54_Msk (0x400000UL)           /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37202 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO53_Pos (21UL)                 /*!< DSP0N1GPIO53 (Bit 21)                                 */
37203 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO53_Msk (0x200000UL)           /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37204 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO52_Pos (20UL)                 /*!< DSP0N1GPIO52 (Bit 20)                                 */
37205 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO52_Msk (0x100000UL)           /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37206 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO51_Pos (19UL)                 /*!< DSP0N1GPIO51 (Bit 19)                                 */
37207 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO51_Msk (0x80000UL)            /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37208 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO50_Pos (18UL)                 /*!< DSP0N1GPIO50 (Bit 18)                                 */
37209 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO50_Msk (0x40000UL)            /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37210 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO49_Pos (17UL)                 /*!< DSP0N1GPIO49 (Bit 17)                                 */
37211 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO49_Msk (0x20000UL)            /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37212 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO48_Pos (16UL)                 /*!< DSP0N1GPIO48 (Bit 16)                                 */
37213 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO48_Msk (0x10000UL)            /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37214 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO47_Pos (15UL)                 /*!< DSP0N1GPIO47 (Bit 15)                                 */
37215 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO47_Msk (0x8000UL)             /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37216 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO46_Pos (14UL)                 /*!< DSP0N1GPIO46 (Bit 14)                                 */
37217 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO46_Msk (0x4000UL)             /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37218 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO45_Pos (13UL)                 /*!< DSP0N1GPIO45 (Bit 13)                                 */
37219 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO45_Msk (0x2000UL)             /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37220 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO44_Pos (12UL)                 /*!< DSP0N1GPIO44 (Bit 12)                                 */
37221 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO44_Msk (0x1000UL)             /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37222 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO43_Pos (11UL)                 /*!< DSP0N1GPIO43 (Bit 11)                                 */
37223 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO43_Msk (0x800UL)              /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37224 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO42_Pos (10UL)                 /*!< DSP0N1GPIO42 (Bit 10)                                 */
37225 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO42_Msk (0x400UL)              /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37226 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO41_Pos (9UL)                  /*!< DSP0N1GPIO41 (Bit 9)                                  */
37227 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO41_Msk (0x200UL)              /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37228 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO40_Pos (8UL)                  /*!< DSP0N1GPIO40 (Bit 8)                                  */
37229 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO40_Msk (0x100UL)              /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37230 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO39_Pos (7UL)                  /*!< DSP0N1GPIO39 (Bit 7)                                  */
37231 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO39_Msk (0x80UL)               /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37232 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO38_Pos (6UL)                  /*!< DSP0N1GPIO38 (Bit 6)                                  */
37233 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO38_Msk (0x40UL)               /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37234 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO37_Pos (5UL)                  /*!< DSP0N1GPIO37 (Bit 5)                                  */
37235 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO37_Msk (0x20UL)               /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37236 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO36_Pos (4UL)                  /*!< DSP0N1GPIO36 (Bit 4)                                  */
37237 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO36_Msk (0x10UL)               /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37238 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO35_Pos (3UL)                  /*!< DSP0N1GPIO35 (Bit 3)                                  */
37239 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO35_Msk (0x8UL)                /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37240 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO34_Pos (2UL)                  /*!< DSP0N1GPIO34 (Bit 2)                                  */
37241 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO34_Msk (0x4UL)                /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37242 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO33_Pos (1UL)                  /*!< DSP0N1GPIO33 (Bit 1)                                  */
37243 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO33_Msk (0x2UL)                /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37244 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO32_Pos (0UL)                  /*!< DSP0N1GPIO32 (Bit 0)                                  */
37245 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO32_Msk (0x1UL)                /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37246 /* =====================================================  DSP0N1INT1CLR  ===================================================== */
37247 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO63_Pos (31UL)                  /*!< DSP0N1GPIO63 (Bit 31)                                 */
37248 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO63_Msk (0x80000000UL)          /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37249 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO62_Pos (30UL)                  /*!< DSP0N1GPIO62 (Bit 30)                                 */
37250 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO62_Msk (0x40000000UL)          /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37251 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO61_Pos (29UL)                  /*!< DSP0N1GPIO61 (Bit 29)                                 */
37252 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO61_Msk (0x20000000UL)          /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37253 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO60_Pos (28UL)                  /*!< DSP0N1GPIO60 (Bit 28)                                 */
37254 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO60_Msk (0x10000000UL)          /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37255 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO59_Pos (27UL)                  /*!< DSP0N1GPIO59 (Bit 27)                                 */
37256 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO59_Msk (0x8000000UL)           /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37257 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO58_Pos (26UL)                  /*!< DSP0N1GPIO58 (Bit 26)                                 */
37258 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO58_Msk (0x4000000UL)           /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37259 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO57_Pos (25UL)                  /*!< DSP0N1GPIO57 (Bit 25)                                 */
37260 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO57_Msk (0x2000000UL)           /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37261 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO56_Pos (24UL)                  /*!< DSP0N1GPIO56 (Bit 24)                                 */
37262 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO56_Msk (0x1000000UL)           /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37263 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO55_Pos (23UL)                  /*!< DSP0N1GPIO55 (Bit 23)                                 */
37264 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO55_Msk (0x800000UL)            /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37265 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO54_Pos (22UL)                  /*!< DSP0N1GPIO54 (Bit 22)                                 */
37266 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO54_Msk (0x400000UL)            /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37267 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO53_Pos (21UL)                  /*!< DSP0N1GPIO53 (Bit 21)                                 */
37268 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO53_Msk (0x200000UL)            /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37269 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO52_Pos (20UL)                  /*!< DSP0N1GPIO52 (Bit 20)                                 */
37270 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO52_Msk (0x100000UL)            /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37271 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO51_Pos (19UL)                  /*!< DSP0N1GPIO51 (Bit 19)                                 */
37272 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO51_Msk (0x80000UL)             /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37273 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO50_Pos (18UL)                  /*!< DSP0N1GPIO50 (Bit 18)                                 */
37274 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO50_Msk (0x40000UL)             /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37275 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO49_Pos (17UL)                  /*!< DSP0N1GPIO49 (Bit 17)                                 */
37276 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO49_Msk (0x20000UL)             /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37277 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO48_Pos (16UL)                  /*!< DSP0N1GPIO48 (Bit 16)                                 */
37278 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO48_Msk (0x10000UL)             /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37279 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO47_Pos (15UL)                  /*!< DSP0N1GPIO47 (Bit 15)                                 */
37280 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO47_Msk (0x8000UL)              /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37281 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO46_Pos (14UL)                  /*!< DSP0N1GPIO46 (Bit 14)                                 */
37282 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO46_Msk (0x4000UL)              /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37283 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO45_Pos (13UL)                  /*!< DSP0N1GPIO45 (Bit 13)                                 */
37284 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO45_Msk (0x2000UL)              /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37285 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO44_Pos (12UL)                  /*!< DSP0N1GPIO44 (Bit 12)                                 */
37286 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO44_Msk (0x1000UL)              /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37287 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO43_Pos (11UL)                  /*!< DSP0N1GPIO43 (Bit 11)                                 */
37288 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO43_Msk (0x800UL)               /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37289 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO42_Pos (10UL)                  /*!< DSP0N1GPIO42 (Bit 10)                                 */
37290 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO42_Msk (0x400UL)               /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37291 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO41_Pos (9UL)                   /*!< DSP0N1GPIO41 (Bit 9)                                  */
37292 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO41_Msk (0x200UL)               /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37293 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO40_Pos (8UL)                   /*!< DSP0N1GPIO40 (Bit 8)                                  */
37294 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO40_Msk (0x100UL)               /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37295 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO39_Pos (7UL)                   /*!< DSP0N1GPIO39 (Bit 7)                                  */
37296 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO39_Msk (0x80UL)                /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37297 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO38_Pos (6UL)                   /*!< DSP0N1GPIO38 (Bit 6)                                  */
37298 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO38_Msk (0x40UL)                /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37299 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO37_Pos (5UL)                   /*!< DSP0N1GPIO37 (Bit 5)                                  */
37300 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO37_Msk (0x20UL)                /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37301 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO36_Pos (4UL)                   /*!< DSP0N1GPIO36 (Bit 4)                                  */
37302 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO36_Msk (0x10UL)                /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37303 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO35_Pos (3UL)                   /*!< DSP0N1GPIO35 (Bit 3)                                  */
37304 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO35_Msk (0x8UL)                 /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37305 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO34_Pos (2UL)                   /*!< DSP0N1GPIO34 (Bit 2)                                  */
37306 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO34_Msk (0x4UL)                 /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37307 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO33_Pos (1UL)                   /*!< DSP0N1GPIO33 (Bit 1)                                  */
37308 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO33_Msk (0x2UL)                 /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37309 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO32_Pos (0UL)                   /*!< DSP0N1GPIO32 (Bit 0)                                  */
37310 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO32_Msk (0x1UL)                 /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37311 /* =====================================================  DSP0N1INT1SET  ===================================================== */
37312 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO63_Pos (31UL)                  /*!< DSP0N1GPIO63 (Bit 31)                                 */
37313 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO63_Msk (0x80000000UL)          /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37314 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO62_Pos (30UL)                  /*!< DSP0N1GPIO62 (Bit 30)                                 */
37315 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO62_Msk (0x40000000UL)          /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37316 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO61_Pos (29UL)                  /*!< DSP0N1GPIO61 (Bit 29)                                 */
37317 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO61_Msk (0x20000000UL)          /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37318 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO60_Pos (28UL)                  /*!< DSP0N1GPIO60 (Bit 28)                                 */
37319 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO60_Msk (0x10000000UL)          /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37320 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO59_Pos (27UL)                  /*!< DSP0N1GPIO59 (Bit 27)                                 */
37321 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO59_Msk (0x8000000UL)           /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37322 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO58_Pos (26UL)                  /*!< DSP0N1GPIO58 (Bit 26)                                 */
37323 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO58_Msk (0x4000000UL)           /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37324 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO57_Pos (25UL)                  /*!< DSP0N1GPIO57 (Bit 25)                                 */
37325 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO57_Msk (0x2000000UL)           /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37326 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO56_Pos (24UL)                  /*!< DSP0N1GPIO56 (Bit 24)                                 */
37327 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO56_Msk (0x1000000UL)           /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37328 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO55_Pos (23UL)                  /*!< DSP0N1GPIO55 (Bit 23)                                 */
37329 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO55_Msk (0x800000UL)            /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37330 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO54_Pos (22UL)                  /*!< DSP0N1GPIO54 (Bit 22)                                 */
37331 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO54_Msk (0x400000UL)            /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37332 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO53_Pos (21UL)                  /*!< DSP0N1GPIO53 (Bit 21)                                 */
37333 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO53_Msk (0x200000UL)            /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37334 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO52_Pos (20UL)                  /*!< DSP0N1GPIO52 (Bit 20)                                 */
37335 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO52_Msk (0x100000UL)            /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37336 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO51_Pos (19UL)                  /*!< DSP0N1GPIO51 (Bit 19)                                 */
37337 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO51_Msk (0x80000UL)             /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37338 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO50_Pos (18UL)                  /*!< DSP0N1GPIO50 (Bit 18)                                 */
37339 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO50_Msk (0x40000UL)             /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37340 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO49_Pos (17UL)                  /*!< DSP0N1GPIO49 (Bit 17)                                 */
37341 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO49_Msk (0x20000UL)             /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37342 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO48_Pos (16UL)                  /*!< DSP0N1GPIO48 (Bit 16)                                 */
37343 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO48_Msk (0x10000UL)             /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37344 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO47_Pos (15UL)                  /*!< DSP0N1GPIO47 (Bit 15)                                 */
37345 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO47_Msk (0x8000UL)              /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37346 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO46_Pos (14UL)                  /*!< DSP0N1GPIO46 (Bit 14)                                 */
37347 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO46_Msk (0x4000UL)              /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37348 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO45_Pos (13UL)                  /*!< DSP0N1GPIO45 (Bit 13)                                 */
37349 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO45_Msk (0x2000UL)              /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37350 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO44_Pos (12UL)                  /*!< DSP0N1GPIO44 (Bit 12)                                 */
37351 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO44_Msk (0x1000UL)              /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37352 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO43_Pos (11UL)                  /*!< DSP0N1GPIO43 (Bit 11)                                 */
37353 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO43_Msk (0x800UL)               /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37354 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO42_Pos (10UL)                  /*!< DSP0N1GPIO42 (Bit 10)                                 */
37355 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO42_Msk (0x400UL)               /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37356 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO41_Pos (9UL)                   /*!< DSP0N1GPIO41 (Bit 9)                                  */
37357 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO41_Msk (0x200UL)               /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37358 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO40_Pos (8UL)                   /*!< DSP0N1GPIO40 (Bit 8)                                  */
37359 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO40_Msk (0x100UL)               /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37360 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO39_Pos (7UL)                   /*!< DSP0N1GPIO39 (Bit 7)                                  */
37361 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO39_Msk (0x80UL)                /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37362 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO38_Pos (6UL)                   /*!< DSP0N1GPIO38 (Bit 6)                                  */
37363 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO38_Msk (0x40UL)                /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37364 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO37_Pos (5UL)                   /*!< DSP0N1GPIO37 (Bit 5)                                  */
37365 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO37_Msk (0x20UL)                /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37366 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO36_Pos (4UL)                   /*!< DSP0N1GPIO36 (Bit 4)                                  */
37367 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO36_Msk (0x10UL)                /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37368 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO35_Pos (3UL)                   /*!< DSP0N1GPIO35 (Bit 3)                                  */
37369 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO35_Msk (0x8UL)                 /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37370 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO34_Pos (2UL)                   /*!< DSP0N1GPIO34 (Bit 2)                                  */
37371 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO34_Msk (0x4UL)                 /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37372 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO33_Pos (1UL)                   /*!< DSP0N1GPIO33 (Bit 1)                                  */
37373 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO33_Msk (0x2UL)                 /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37374 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO32_Pos (0UL)                   /*!< DSP0N1GPIO32 (Bit 0)                                  */
37375 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO32_Msk (0x1UL)                 /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37376 /* =====================================================  DSP0N1INT2EN  ====================================================== */
37377 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO95_Pos (31UL)                   /*!< DSP0N1GPIO95 (Bit 31)                                 */
37378 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO95_Msk (0x80000000UL)           /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
37379 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO94_Pos (30UL)                   /*!< DSP0N1GPIO94 (Bit 30)                                 */
37380 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO94_Msk (0x40000000UL)           /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
37381 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO93_Pos (29UL)                   /*!< DSP0N1GPIO93 (Bit 29)                                 */
37382 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO93_Msk (0x20000000UL)           /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
37383 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO92_Pos (28UL)                   /*!< DSP0N1GPIO92 (Bit 28)                                 */
37384 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO92_Msk (0x10000000UL)           /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
37385 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO91_Pos (27UL)                   /*!< DSP0N1GPIO91 (Bit 27)                                 */
37386 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO91_Msk (0x8000000UL)            /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
37387 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO90_Pos (26UL)                   /*!< DSP0N1GPIO90 (Bit 26)                                 */
37388 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO90_Msk (0x4000000UL)            /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
37389 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO89_Pos (25UL)                   /*!< DSP0N1GPIO89 (Bit 25)                                 */
37390 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO89_Msk (0x2000000UL)            /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
37391 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO88_Pos (24UL)                   /*!< DSP0N1GPIO88 (Bit 24)                                 */
37392 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO88_Msk (0x1000000UL)            /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
37393 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO87_Pos (23UL)                   /*!< DSP0N1GPIO87 (Bit 23)                                 */
37394 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO87_Msk (0x800000UL)             /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
37395 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO86_Pos (22UL)                   /*!< DSP0N1GPIO86 (Bit 22)                                 */
37396 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO86_Msk (0x400000UL)             /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
37397 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO85_Pos (21UL)                   /*!< DSP0N1GPIO85 (Bit 21)                                 */
37398 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO85_Msk (0x200000UL)             /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
37399 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO84_Pos (20UL)                   /*!< DSP0N1GPIO84 (Bit 20)                                 */
37400 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO84_Msk (0x100000UL)             /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
37401 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO83_Pos (19UL)                   /*!< DSP0N1GPIO83 (Bit 19)                                 */
37402 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO83_Msk (0x80000UL)              /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
37403 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO82_Pos (18UL)                   /*!< DSP0N1GPIO82 (Bit 18)                                 */
37404 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO82_Msk (0x40000UL)              /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
37405 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO81_Pos (17UL)                   /*!< DSP0N1GPIO81 (Bit 17)                                 */
37406 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO81_Msk (0x20000UL)              /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
37407 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO80_Pos (16UL)                   /*!< DSP0N1GPIO80 (Bit 16)                                 */
37408 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO80_Msk (0x10000UL)              /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
37409 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO79_Pos (15UL)                   /*!< DSP0N1GPIO79 (Bit 15)                                 */
37410 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO79_Msk (0x8000UL)               /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
37411 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO78_Pos (14UL)                   /*!< DSP0N1GPIO78 (Bit 14)                                 */
37412 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO78_Msk (0x4000UL)               /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
37413 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO77_Pos (13UL)                   /*!< DSP0N1GPIO77 (Bit 13)                                 */
37414 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO77_Msk (0x2000UL)               /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
37415 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO76_Pos (12UL)                   /*!< DSP0N1GPIO76 (Bit 12)                                 */
37416 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO76_Msk (0x1000UL)               /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
37417 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO75_Pos (11UL)                   /*!< DSP0N1GPIO75 (Bit 11)                                 */
37418 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO75_Msk (0x800UL)                /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
37419 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO74_Pos (10UL)                   /*!< DSP0N1GPIO74 (Bit 10)                                 */
37420 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO74_Msk (0x400UL)                /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
37421 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO73_Pos (9UL)                    /*!< DSP0N1GPIO73 (Bit 9)                                  */
37422 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO73_Msk (0x200UL)                /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
37423 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO72_Pos (8UL)                    /*!< DSP0N1GPIO72 (Bit 8)                                  */
37424 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO72_Msk (0x100UL)                /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
37425 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO71_Pos (7UL)                    /*!< DSP0N1GPIO71 (Bit 7)                                  */
37426 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO71_Msk (0x80UL)                 /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
37427 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO70_Pos (6UL)                    /*!< DSP0N1GPIO70 (Bit 6)                                  */
37428 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO70_Msk (0x40UL)                 /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
37429 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO69_Pos (5UL)                    /*!< DSP0N1GPIO69 (Bit 5)                                  */
37430 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO69_Msk (0x20UL)                 /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
37431 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO68_Pos (4UL)                    /*!< DSP0N1GPIO68 (Bit 4)                                  */
37432 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO68_Msk (0x10UL)                 /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
37433 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO67_Pos (3UL)                    /*!< DSP0N1GPIO67 (Bit 3)                                  */
37434 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO67_Msk (0x8UL)                  /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
37435 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO66_Pos (2UL)                    /*!< DSP0N1GPIO66 (Bit 2)                                  */
37436 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO66_Msk (0x4UL)                  /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
37437 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO65_Pos (1UL)                    /*!< DSP0N1GPIO65 (Bit 1)                                  */
37438 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO65_Msk (0x2UL)                  /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
37439 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO64_Pos (0UL)                    /*!< DSP0N1GPIO64 (Bit 0)                                  */
37440 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO64_Msk (0x1UL)                  /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
37441 /* ====================================================  DSP0N1INT2STAT  ===================================================== */
37442 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO95_Pos (31UL)                 /*!< DSP0N1GPIO95 (Bit 31)                                 */
37443 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO95_Msk (0x80000000UL)         /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
37444 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO94_Pos (30UL)                 /*!< DSP0N1GPIO94 (Bit 30)                                 */
37445 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO94_Msk (0x40000000UL)         /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
37446 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO93_Pos (29UL)                 /*!< DSP0N1GPIO93 (Bit 29)                                 */
37447 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO93_Msk (0x20000000UL)         /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
37448 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO92_Pos (28UL)                 /*!< DSP0N1GPIO92 (Bit 28)                                 */
37449 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO92_Msk (0x10000000UL)         /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
37450 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO91_Pos (27UL)                 /*!< DSP0N1GPIO91 (Bit 27)                                 */
37451 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO91_Msk (0x8000000UL)          /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
37452 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO90_Pos (26UL)                 /*!< DSP0N1GPIO90 (Bit 26)                                 */
37453 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO90_Msk (0x4000000UL)          /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
37454 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO89_Pos (25UL)                 /*!< DSP0N1GPIO89 (Bit 25)                                 */
37455 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO89_Msk (0x2000000UL)          /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
37456 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO88_Pos (24UL)                 /*!< DSP0N1GPIO88 (Bit 24)                                 */
37457 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO88_Msk (0x1000000UL)          /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
37458 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO87_Pos (23UL)                 /*!< DSP0N1GPIO87 (Bit 23)                                 */
37459 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO87_Msk (0x800000UL)           /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
37460 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO86_Pos (22UL)                 /*!< DSP0N1GPIO86 (Bit 22)                                 */
37461 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO86_Msk (0x400000UL)           /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
37462 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO85_Pos (21UL)                 /*!< DSP0N1GPIO85 (Bit 21)                                 */
37463 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO85_Msk (0x200000UL)           /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
37464 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO84_Pos (20UL)                 /*!< DSP0N1GPIO84 (Bit 20)                                 */
37465 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO84_Msk (0x100000UL)           /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
37466 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO83_Pos (19UL)                 /*!< DSP0N1GPIO83 (Bit 19)                                 */
37467 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO83_Msk (0x80000UL)            /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
37468 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO82_Pos (18UL)                 /*!< DSP0N1GPIO82 (Bit 18)                                 */
37469 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO82_Msk (0x40000UL)            /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
37470 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO81_Pos (17UL)                 /*!< DSP0N1GPIO81 (Bit 17)                                 */
37471 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO81_Msk (0x20000UL)            /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
37472 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO80_Pos (16UL)                 /*!< DSP0N1GPIO80 (Bit 16)                                 */
37473 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO80_Msk (0x10000UL)            /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
37474 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO79_Pos (15UL)                 /*!< DSP0N1GPIO79 (Bit 15)                                 */
37475 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO79_Msk (0x8000UL)             /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
37476 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO78_Pos (14UL)                 /*!< DSP0N1GPIO78 (Bit 14)                                 */
37477 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO78_Msk (0x4000UL)             /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
37478 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO77_Pos (13UL)                 /*!< DSP0N1GPIO77 (Bit 13)                                 */
37479 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO77_Msk (0x2000UL)             /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
37480 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO76_Pos (12UL)                 /*!< DSP0N1GPIO76 (Bit 12)                                 */
37481 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO76_Msk (0x1000UL)             /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
37482 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO75_Pos (11UL)                 /*!< DSP0N1GPIO75 (Bit 11)                                 */
37483 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO75_Msk (0x800UL)              /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
37484 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO74_Pos (10UL)                 /*!< DSP0N1GPIO74 (Bit 10)                                 */
37485 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO74_Msk (0x400UL)              /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
37486 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO73_Pos (9UL)                  /*!< DSP0N1GPIO73 (Bit 9)                                  */
37487 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO73_Msk (0x200UL)              /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
37488 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO72_Pos (8UL)                  /*!< DSP0N1GPIO72 (Bit 8)                                  */
37489 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO72_Msk (0x100UL)              /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
37490 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO71_Pos (7UL)                  /*!< DSP0N1GPIO71 (Bit 7)                                  */
37491 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO71_Msk (0x80UL)               /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
37492 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO70_Pos (6UL)                  /*!< DSP0N1GPIO70 (Bit 6)                                  */
37493 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO70_Msk (0x40UL)               /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
37494 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO69_Pos (5UL)                  /*!< DSP0N1GPIO69 (Bit 5)                                  */
37495 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO69_Msk (0x20UL)               /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
37496 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO68_Pos (4UL)                  /*!< DSP0N1GPIO68 (Bit 4)                                  */
37497 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO68_Msk (0x10UL)               /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
37498 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO67_Pos (3UL)                  /*!< DSP0N1GPIO67 (Bit 3)                                  */
37499 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO67_Msk (0x8UL)                /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
37500 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO66_Pos (2UL)                  /*!< DSP0N1GPIO66 (Bit 2)                                  */
37501 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO66_Msk (0x4UL)                /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
37502 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO65_Pos (1UL)                  /*!< DSP0N1GPIO65 (Bit 1)                                  */
37503 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO65_Msk (0x2UL)                /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
37504 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO64_Pos (0UL)                  /*!< DSP0N1GPIO64 (Bit 0)                                  */
37505 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO64_Msk (0x1UL)                /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
37506 /* =====================================================  DSP0N1INT2CLR  ===================================================== */
37507 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO95_Pos (31UL)                  /*!< DSP0N1GPIO95 (Bit 31)                                 */
37508 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO95_Msk (0x80000000UL)          /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
37509 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO94_Pos (30UL)                  /*!< DSP0N1GPIO94 (Bit 30)                                 */
37510 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO94_Msk (0x40000000UL)          /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
37511 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO93_Pos (29UL)                  /*!< DSP0N1GPIO93 (Bit 29)                                 */
37512 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO93_Msk (0x20000000UL)          /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
37513 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO92_Pos (28UL)                  /*!< DSP0N1GPIO92 (Bit 28)                                 */
37514 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO92_Msk (0x10000000UL)          /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
37515 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO91_Pos (27UL)                  /*!< DSP0N1GPIO91 (Bit 27)                                 */
37516 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO91_Msk (0x8000000UL)           /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
37517 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO90_Pos (26UL)                  /*!< DSP0N1GPIO90 (Bit 26)                                 */
37518 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO90_Msk (0x4000000UL)           /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
37519 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO89_Pos (25UL)                  /*!< DSP0N1GPIO89 (Bit 25)                                 */
37520 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO89_Msk (0x2000000UL)           /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
37521 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO88_Pos (24UL)                  /*!< DSP0N1GPIO88 (Bit 24)                                 */
37522 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO88_Msk (0x1000000UL)           /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
37523 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO87_Pos (23UL)                  /*!< DSP0N1GPIO87 (Bit 23)                                 */
37524 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO87_Msk (0x800000UL)            /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
37525 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO86_Pos (22UL)                  /*!< DSP0N1GPIO86 (Bit 22)                                 */
37526 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO86_Msk (0x400000UL)            /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
37527 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO85_Pos (21UL)                  /*!< DSP0N1GPIO85 (Bit 21)                                 */
37528 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO85_Msk (0x200000UL)            /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
37529 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO84_Pos (20UL)                  /*!< DSP0N1GPIO84 (Bit 20)                                 */
37530 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO84_Msk (0x100000UL)            /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
37531 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO83_Pos (19UL)                  /*!< DSP0N1GPIO83 (Bit 19)                                 */
37532 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO83_Msk (0x80000UL)             /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
37533 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO82_Pos (18UL)                  /*!< DSP0N1GPIO82 (Bit 18)                                 */
37534 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO82_Msk (0x40000UL)             /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
37535 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO81_Pos (17UL)                  /*!< DSP0N1GPIO81 (Bit 17)                                 */
37536 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO81_Msk (0x20000UL)             /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
37537 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO80_Pos (16UL)                  /*!< DSP0N1GPIO80 (Bit 16)                                 */
37538 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO80_Msk (0x10000UL)             /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
37539 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO79_Pos (15UL)                  /*!< DSP0N1GPIO79 (Bit 15)                                 */
37540 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO79_Msk (0x8000UL)              /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
37541 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO78_Pos (14UL)                  /*!< DSP0N1GPIO78 (Bit 14)                                 */
37542 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO78_Msk (0x4000UL)              /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
37543 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO77_Pos (13UL)                  /*!< DSP0N1GPIO77 (Bit 13)                                 */
37544 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO77_Msk (0x2000UL)              /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
37545 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO76_Pos (12UL)                  /*!< DSP0N1GPIO76 (Bit 12)                                 */
37546 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO76_Msk (0x1000UL)              /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
37547 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO75_Pos (11UL)                  /*!< DSP0N1GPIO75 (Bit 11)                                 */
37548 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO75_Msk (0x800UL)               /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
37549 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO74_Pos (10UL)                  /*!< DSP0N1GPIO74 (Bit 10)                                 */
37550 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO74_Msk (0x400UL)               /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
37551 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO73_Pos (9UL)                   /*!< DSP0N1GPIO73 (Bit 9)                                  */
37552 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO73_Msk (0x200UL)               /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
37553 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO72_Pos (8UL)                   /*!< DSP0N1GPIO72 (Bit 8)                                  */
37554 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO72_Msk (0x100UL)               /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
37555 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO71_Pos (7UL)                   /*!< DSP0N1GPIO71 (Bit 7)                                  */
37556 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO71_Msk (0x80UL)                /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
37557 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO70_Pos (6UL)                   /*!< DSP0N1GPIO70 (Bit 6)                                  */
37558 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO70_Msk (0x40UL)                /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
37559 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO69_Pos (5UL)                   /*!< DSP0N1GPIO69 (Bit 5)                                  */
37560 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO69_Msk (0x20UL)                /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
37561 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO68_Pos (4UL)                   /*!< DSP0N1GPIO68 (Bit 4)                                  */
37562 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO68_Msk (0x10UL)                /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
37563 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO67_Pos (3UL)                   /*!< DSP0N1GPIO67 (Bit 3)                                  */
37564 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO67_Msk (0x8UL)                 /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
37565 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO66_Pos (2UL)                   /*!< DSP0N1GPIO66 (Bit 2)                                  */
37566 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO66_Msk (0x4UL)                 /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
37567 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO65_Pos (1UL)                   /*!< DSP0N1GPIO65 (Bit 1)                                  */
37568 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO65_Msk (0x2UL)                 /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
37569 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO64_Pos (0UL)                   /*!< DSP0N1GPIO64 (Bit 0)                                  */
37570 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO64_Msk (0x1UL)                 /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
37571 /* =====================================================  DSP0N1INT2SET  ===================================================== */
37572 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO95_Pos (31UL)                  /*!< DSP0N1GPIO95 (Bit 31)                                 */
37573 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO95_Msk (0x80000000UL)          /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
37574 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO94_Pos (30UL)                  /*!< DSP0N1GPIO94 (Bit 30)                                 */
37575 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO94_Msk (0x40000000UL)          /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
37576 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO93_Pos (29UL)                  /*!< DSP0N1GPIO93 (Bit 29)                                 */
37577 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO93_Msk (0x20000000UL)          /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
37578 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO92_Pos (28UL)                  /*!< DSP0N1GPIO92 (Bit 28)                                 */
37579 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO92_Msk (0x10000000UL)          /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
37580 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO91_Pos (27UL)                  /*!< DSP0N1GPIO91 (Bit 27)                                 */
37581 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO91_Msk (0x8000000UL)           /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
37582 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO90_Pos (26UL)                  /*!< DSP0N1GPIO90 (Bit 26)                                 */
37583 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO90_Msk (0x4000000UL)           /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
37584 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO89_Pos (25UL)                  /*!< DSP0N1GPIO89 (Bit 25)                                 */
37585 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO89_Msk (0x2000000UL)           /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
37586 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO88_Pos (24UL)                  /*!< DSP0N1GPIO88 (Bit 24)                                 */
37587 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO88_Msk (0x1000000UL)           /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
37588 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO87_Pos (23UL)                  /*!< DSP0N1GPIO87 (Bit 23)                                 */
37589 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO87_Msk (0x800000UL)            /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
37590 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO86_Pos (22UL)                  /*!< DSP0N1GPIO86 (Bit 22)                                 */
37591 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO86_Msk (0x400000UL)            /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
37592 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO85_Pos (21UL)                  /*!< DSP0N1GPIO85 (Bit 21)                                 */
37593 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO85_Msk (0x200000UL)            /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
37594 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO84_Pos (20UL)                  /*!< DSP0N1GPIO84 (Bit 20)                                 */
37595 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO84_Msk (0x100000UL)            /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
37596 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO83_Pos (19UL)                  /*!< DSP0N1GPIO83 (Bit 19)                                 */
37597 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO83_Msk (0x80000UL)             /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
37598 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO82_Pos (18UL)                  /*!< DSP0N1GPIO82 (Bit 18)                                 */
37599 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO82_Msk (0x40000UL)             /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
37600 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO81_Pos (17UL)                  /*!< DSP0N1GPIO81 (Bit 17)                                 */
37601 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO81_Msk (0x20000UL)             /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
37602 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO80_Pos (16UL)                  /*!< DSP0N1GPIO80 (Bit 16)                                 */
37603 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO80_Msk (0x10000UL)             /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
37604 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO79_Pos (15UL)                  /*!< DSP0N1GPIO79 (Bit 15)                                 */
37605 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO79_Msk (0x8000UL)              /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
37606 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO78_Pos (14UL)                  /*!< DSP0N1GPIO78 (Bit 14)                                 */
37607 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO78_Msk (0x4000UL)              /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
37608 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO77_Pos (13UL)                  /*!< DSP0N1GPIO77 (Bit 13)                                 */
37609 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO77_Msk (0x2000UL)              /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
37610 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO76_Pos (12UL)                  /*!< DSP0N1GPIO76 (Bit 12)                                 */
37611 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO76_Msk (0x1000UL)              /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
37612 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO75_Pos (11UL)                  /*!< DSP0N1GPIO75 (Bit 11)                                 */
37613 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO75_Msk (0x800UL)               /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
37614 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO74_Pos (10UL)                  /*!< DSP0N1GPIO74 (Bit 10)                                 */
37615 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO74_Msk (0x400UL)               /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
37616 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO73_Pos (9UL)                   /*!< DSP0N1GPIO73 (Bit 9)                                  */
37617 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO73_Msk (0x200UL)               /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
37618 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO72_Pos (8UL)                   /*!< DSP0N1GPIO72 (Bit 8)                                  */
37619 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO72_Msk (0x100UL)               /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
37620 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO71_Pos (7UL)                   /*!< DSP0N1GPIO71 (Bit 7)                                  */
37621 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO71_Msk (0x80UL)                /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
37622 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO70_Pos (6UL)                   /*!< DSP0N1GPIO70 (Bit 6)                                  */
37623 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO70_Msk (0x40UL)                /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
37624 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO69_Pos (5UL)                   /*!< DSP0N1GPIO69 (Bit 5)                                  */
37625 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO69_Msk (0x20UL)                /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
37626 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO68_Pos (4UL)                   /*!< DSP0N1GPIO68 (Bit 4)                                  */
37627 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO68_Msk (0x10UL)                /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
37628 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO67_Pos (3UL)                   /*!< DSP0N1GPIO67 (Bit 3)                                  */
37629 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO67_Msk (0x8UL)                 /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
37630 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO66_Pos (2UL)                   /*!< DSP0N1GPIO66 (Bit 2)                                  */
37631 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO66_Msk (0x4UL)                 /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
37632 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO65_Pos (1UL)                   /*!< DSP0N1GPIO65 (Bit 1)                                  */
37633 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO65_Msk (0x2UL)                 /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
37634 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO64_Pos (0UL)                   /*!< DSP0N1GPIO64 (Bit 0)                                  */
37635 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO64_Msk (0x1UL)                 /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
37636 /* =====================================================  DSP0N1INT3EN  ====================================================== */
37637 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO127_Pos (31UL)                  /*!< DSP0N1GPIO127 (Bit 31)                                */
37638 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO127_Msk (0x80000000UL)          /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
37639 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO126_Pos (30UL)                  /*!< DSP0N1GPIO126 (Bit 30)                                */
37640 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO126_Msk (0x40000000UL)          /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
37641 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO125_Pos (29UL)                  /*!< DSP0N1GPIO125 (Bit 29)                                */
37642 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO125_Msk (0x20000000UL)          /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
37643 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO124_Pos (28UL)                  /*!< DSP0N1GPIO124 (Bit 28)                                */
37644 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO124_Msk (0x10000000UL)          /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
37645 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO123_Pos (27UL)                  /*!< DSP0N1GPIO123 (Bit 27)                                */
37646 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO123_Msk (0x8000000UL)           /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
37647 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO122_Pos (26UL)                  /*!< DSP0N1GPIO122 (Bit 26)                                */
37648 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO122_Msk (0x4000000UL)           /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
37649 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO121_Pos (25UL)                  /*!< DSP0N1GPIO121 (Bit 25)                                */
37650 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO121_Msk (0x2000000UL)           /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
37651 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO120_Pos (24UL)                  /*!< DSP0N1GPIO120 (Bit 24)                                */
37652 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO120_Msk (0x1000000UL)           /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
37653 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO119_Pos (23UL)                  /*!< DSP0N1GPIO119 (Bit 23)                                */
37654 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO119_Msk (0x800000UL)            /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
37655 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO118_Pos (22UL)                  /*!< DSP0N1GPIO118 (Bit 22)                                */
37656 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO118_Msk (0x400000UL)            /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
37657 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO117_Pos (21UL)                  /*!< DSP0N1GPIO117 (Bit 21)                                */
37658 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO117_Msk (0x200000UL)            /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
37659 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO116_Pos (20UL)                  /*!< DSP0N1GPIO116 (Bit 20)                                */
37660 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO116_Msk (0x100000UL)            /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
37661 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO115_Pos (19UL)                  /*!< DSP0N1GPIO115 (Bit 19)                                */
37662 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO115_Msk (0x80000UL)             /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
37663 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO114_Pos (18UL)                  /*!< DSP0N1GPIO114 (Bit 18)                                */
37664 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO114_Msk (0x40000UL)             /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
37665 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO113_Pos (17UL)                  /*!< DSP0N1GPIO113 (Bit 17)                                */
37666 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO113_Msk (0x20000UL)             /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
37667 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO112_Pos (16UL)                  /*!< DSP0N1GPIO112 (Bit 16)                                */
37668 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO112_Msk (0x10000UL)             /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
37669 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO111_Pos (15UL)                  /*!< DSP0N1GPIO111 (Bit 15)                                */
37670 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO111_Msk (0x8000UL)              /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
37671 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO110_Pos (14UL)                  /*!< DSP0N1GPIO110 (Bit 14)                                */
37672 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO110_Msk (0x4000UL)              /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
37673 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO109_Pos (13UL)                  /*!< DSP0N1GPIO109 (Bit 13)                                */
37674 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO109_Msk (0x2000UL)              /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
37675 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO108_Pos (12UL)                  /*!< DSP0N1GPIO108 (Bit 12)                                */
37676 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO108_Msk (0x1000UL)              /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
37677 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO107_Pos (11UL)                  /*!< DSP0N1GPIO107 (Bit 11)                                */
37678 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO107_Msk (0x800UL)               /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
37679 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO106_Pos (10UL)                  /*!< DSP0N1GPIO106 (Bit 10)                                */
37680 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO106_Msk (0x400UL)               /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
37681 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO105_Pos (9UL)                   /*!< DSP0N1GPIO105 (Bit 9)                                 */
37682 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO105_Msk (0x200UL)               /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
37683 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO104_Pos (8UL)                   /*!< DSP0N1GPIO104 (Bit 8)                                 */
37684 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO104_Msk (0x100UL)               /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
37685 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO103_Pos (7UL)                   /*!< DSP0N1GPIO103 (Bit 7)                                 */
37686 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO103_Msk (0x80UL)                /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
37687 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO102_Pos (6UL)                   /*!< DSP0N1GPIO102 (Bit 6)                                 */
37688 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO102_Msk (0x40UL)                /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
37689 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO101_Pos (5UL)                   /*!< DSP0N1GPIO101 (Bit 5)                                 */
37690 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO101_Msk (0x20UL)                /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
37691 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO100_Pos (4UL)                   /*!< DSP0N1GPIO100 (Bit 4)                                 */
37692 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO100_Msk (0x10UL)                /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
37693 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO99_Pos (3UL)                    /*!< DSP0N1GPIO99 (Bit 3)                                  */
37694 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO99_Msk (0x8UL)                  /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
37695 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO98_Pos (2UL)                    /*!< DSP0N1GPIO98 (Bit 2)                                  */
37696 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO98_Msk (0x4UL)                  /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
37697 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO97_Pos (1UL)                    /*!< DSP0N1GPIO97 (Bit 1)                                  */
37698 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO97_Msk (0x2UL)                  /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
37699 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO96_Pos (0UL)                    /*!< DSP0N1GPIO96 (Bit 0)                                  */
37700 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO96_Msk (0x1UL)                  /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
37701 /* ====================================================  DSP0N1INT3STAT  ===================================================== */
37702 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO127_Pos (31UL)                /*!< DSP0N1GPIO127 (Bit 31)                                */
37703 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO127_Msk (0x80000000UL)        /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
37704 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO126_Pos (30UL)                /*!< DSP0N1GPIO126 (Bit 30)                                */
37705 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO126_Msk (0x40000000UL)        /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
37706 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO125_Pos (29UL)                /*!< DSP0N1GPIO125 (Bit 29)                                */
37707 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO125_Msk (0x20000000UL)        /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
37708 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO124_Pos (28UL)                /*!< DSP0N1GPIO124 (Bit 28)                                */
37709 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO124_Msk (0x10000000UL)        /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
37710 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO123_Pos (27UL)                /*!< DSP0N1GPIO123 (Bit 27)                                */
37711 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO123_Msk (0x8000000UL)         /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
37712 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO122_Pos (26UL)                /*!< DSP0N1GPIO122 (Bit 26)                                */
37713 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO122_Msk (0x4000000UL)         /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
37714 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO121_Pos (25UL)                /*!< DSP0N1GPIO121 (Bit 25)                                */
37715 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO121_Msk (0x2000000UL)         /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
37716 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO120_Pos (24UL)                /*!< DSP0N1GPIO120 (Bit 24)                                */
37717 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO120_Msk (0x1000000UL)         /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
37718 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO119_Pos (23UL)                /*!< DSP0N1GPIO119 (Bit 23)                                */
37719 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO119_Msk (0x800000UL)          /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
37720 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO118_Pos (22UL)                /*!< DSP0N1GPIO118 (Bit 22)                                */
37721 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO118_Msk (0x400000UL)          /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
37722 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO117_Pos (21UL)                /*!< DSP0N1GPIO117 (Bit 21)                                */
37723 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO117_Msk (0x200000UL)          /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
37724 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO116_Pos (20UL)                /*!< DSP0N1GPIO116 (Bit 20)                                */
37725 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO116_Msk (0x100000UL)          /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
37726 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO115_Pos (19UL)                /*!< DSP0N1GPIO115 (Bit 19)                                */
37727 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO115_Msk (0x80000UL)           /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
37728 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO114_Pos (18UL)                /*!< DSP0N1GPIO114 (Bit 18)                                */
37729 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO114_Msk (0x40000UL)           /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
37730 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO113_Pos (17UL)                /*!< DSP0N1GPIO113 (Bit 17)                                */
37731 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO113_Msk (0x20000UL)           /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
37732 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO112_Pos (16UL)                /*!< DSP0N1GPIO112 (Bit 16)                                */
37733 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO112_Msk (0x10000UL)           /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
37734 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO111_Pos (15UL)                /*!< DSP0N1GPIO111 (Bit 15)                                */
37735 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO111_Msk (0x8000UL)            /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
37736 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO110_Pos (14UL)                /*!< DSP0N1GPIO110 (Bit 14)                                */
37737 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO110_Msk (0x4000UL)            /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
37738 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO109_Pos (13UL)                /*!< DSP0N1GPIO109 (Bit 13)                                */
37739 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO109_Msk (0x2000UL)            /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
37740 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO108_Pos (12UL)                /*!< DSP0N1GPIO108 (Bit 12)                                */
37741 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO108_Msk (0x1000UL)            /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
37742 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO107_Pos (11UL)                /*!< DSP0N1GPIO107 (Bit 11)                                */
37743 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO107_Msk (0x800UL)             /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
37744 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO106_Pos (10UL)                /*!< DSP0N1GPIO106 (Bit 10)                                */
37745 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO106_Msk (0x400UL)             /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
37746 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO105_Pos (9UL)                 /*!< DSP0N1GPIO105 (Bit 9)                                 */
37747 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO105_Msk (0x200UL)             /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
37748 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO104_Pos (8UL)                 /*!< DSP0N1GPIO104 (Bit 8)                                 */
37749 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO104_Msk (0x100UL)             /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
37750 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO103_Pos (7UL)                 /*!< DSP0N1GPIO103 (Bit 7)                                 */
37751 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO103_Msk (0x80UL)              /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
37752 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO102_Pos (6UL)                 /*!< DSP0N1GPIO102 (Bit 6)                                 */
37753 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO102_Msk (0x40UL)              /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
37754 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO101_Pos (5UL)                 /*!< DSP0N1GPIO101 (Bit 5)                                 */
37755 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO101_Msk (0x20UL)              /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
37756 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO100_Pos (4UL)                 /*!< DSP0N1GPIO100 (Bit 4)                                 */
37757 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO100_Msk (0x10UL)              /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
37758 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO99_Pos (3UL)                  /*!< DSP0N1GPIO99 (Bit 3)                                  */
37759 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO99_Msk (0x8UL)                /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
37760 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO98_Pos (2UL)                  /*!< DSP0N1GPIO98 (Bit 2)                                  */
37761 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO98_Msk (0x4UL)                /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
37762 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO97_Pos (1UL)                  /*!< DSP0N1GPIO97 (Bit 1)                                  */
37763 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO97_Msk (0x2UL)                /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
37764 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO96_Pos (0UL)                  /*!< DSP0N1GPIO96 (Bit 0)                                  */
37765 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO96_Msk (0x1UL)                /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
37766 /* =====================================================  DSP0N1INT3CLR  ===================================================== */
37767 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO127_Pos (31UL)                 /*!< DSP0N1GPIO127 (Bit 31)                                */
37768 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO127_Msk (0x80000000UL)         /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
37769 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO126_Pos (30UL)                 /*!< DSP0N1GPIO126 (Bit 30)                                */
37770 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO126_Msk (0x40000000UL)         /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
37771 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO125_Pos (29UL)                 /*!< DSP0N1GPIO125 (Bit 29)                                */
37772 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO125_Msk (0x20000000UL)         /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
37773 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO124_Pos (28UL)                 /*!< DSP0N1GPIO124 (Bit 28)                                */
37774 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO124_Msk (0x10000000UL)         /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
37775 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO123_Pos (27UL)                 /*!< DSP0N1GPIO123 (Bit 27)                                */
37776 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO123_Msk (0x8000000UL)          /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
37777 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO122_Pos (26UL)                 /*!< DSP0N1GPIO122 (Bit 26)                                */
37778 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO122_Msk (0x4000000UL)          /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
37779 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO121_Pos (25UL)                 /*!< DSP0N1GPIO121 (Bit 25)                                */
37780 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO121_Msk (0x2000000UL)          /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
37781 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO120_Pos (24UL)                 /*!< DSP0N1GPIO120 (Bit 24)                                */
37782 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO120_Msk (0x1000000UL)          /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
37783 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO119_Pos (23UL)                 /*!< DSP0N1GPIO119 (Bit 23)                                */
37784 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO119_Msk (0x800000UL)           /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
37785 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO118_Pos (22UL)                 /*!< DSP0N1GPIO118 (Bit 22)                                */
37786 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO118_Msk (0x400000UL)           /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
37787 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO117_Pos (21UL)                 /*!< DSP0N1GPIO117 (Bit 21)                                */
37788 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO117_Msk (0x200000UL)           /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
37789 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO116_Pos (20UL)                 /*!< DSP0N1GPIO116 (Bit 20)                                */
37790 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO116_Msk (0x100000UL)           /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
37791 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO115_Pos (19UL)                 /*!< DSP0N1GPIO115 (Bit 19)                                */
37792 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO115_Msk (0x80000UL)            /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
37793 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO114_Pos (18UL)                 /*!< DSP0N1GPIO114 (Bit 18)                                */
37794 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO114_Msk (0x40000UL)            /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
37795 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO113_Pos (17UL)                 /*!< DSP0N1GPIO113 (Bit 17)                                */
37796 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO113_Msk (0x20000UL)            /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
37797 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO112_Pos (16UL)                 /*!< DSP0N1GPIO112 (Bit 16)                                */
37798 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO112_Msk (0x10000UL)            /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
37799 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO111_Pos (15UL)                 /*!< DSP0N1GPIO111 (Bit 15)                                */
37800 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO111_Msk (0x8000UL)             /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
37801 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO110_Pos (14UL)                 /*!< DSP0N1GPIO110 (Bit 14)                                */
37802 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO110_Msk (0x4000UL)             /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
37803 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO109_Pos (13UL)                 /*!< DSP0N1GPIO109 (Bit 13)                                */
37804 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO109_Msk (0x2000UL)             /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
37805 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO108_Pos (12UL)                 /*!< DSP0N1GPIO108 (Bit 12)                                */
37806 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO108_Msk (0x1000UL)             /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
37807 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO107_Pos (11UL)                 /*!< DSP0N1GPIO107 (Bit 11)                                */
37808 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO107_Msk (0x800UL)              /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
37809 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO106_Pos (10UL)                 /*!< DSP0N1GPIO106 (Bit 10)                                */
37810 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO106_Msk (0x400UL)              /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
37811 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO105_Pos (9UL)                  /*!< DSP0N1GPIO105 (Bit 9)                                 */
37812 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO105_Msk (0x200UL)              /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
37813 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO104_Pos (8UL)                  /*!< DSP0N1GPIO104 (Bit 8)                                 */
37814 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO104_Msk (0x100UL)              /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
37815 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO103_Pos (7UL)                  /*!< DSP0N1GPIO103 (Bit 7)                                 */
37816 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO103_Msk (0x80UL)               /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
37817 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO102_Pos (6UL)                  /*!< DSP0N1GPIO102 (Bit 6)                                 */
37818 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO102_Msk (0x40UL)               /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
37819 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO101_Pos (5UL)                  /*!< DSP0N1GPIO101 (Bit 5)                                 */
37820 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO101_Msk (0x20UL)               /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
37821 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO100_Pos (4UL)                  /*!< DSP0N1GPIO100 (Bit 4)                                 */
37822 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO100_Msk (0x10UL)               /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
37823 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO99_Pos (3UL)                   /*!< DSP0N1GPIO99 (Bit 3)                                  */
37824 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO99_Msk (0x8UL)                 /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
37825 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO98_Pos (2UL)                   /*!< DSP0N1GPIO98 (Bit 2)                                  */
37826 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO98_Msk (0x4UL)                 /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
37827 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO97_Pos (1UL)                   /*!< DSP0N1GPIO97 (Bit 1)                                  */
37828 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO97_Msk (0x2UL)                 /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
37829 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO96_Pos (0UL)                   /*!< DSP0N1GPIO96 (Bit 0)                                  */
37830 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO96_Msk (0x1UL)                 /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
37831 /* =====================================================  DSP0N1INT3SET  ===================================================== */
37832 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO127_Pos (31UL)                 /*!< DSP0N1GPIO127 (Bit 31)                                */
37833 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO127_Msk (0x80000000UL)         /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
37834 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO126_Pos (30UL)                 /*!< DSP0N1GPIO126 (Bit 30)                                */
37835 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO126_Msk (0x40000000UL)         /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
37836 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO125_Pos (29UL)                 /*!< DSP0N1GPIO125 (Bit 29)                                */
37837 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO125_Msk (0x20000000UL)         /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
37838 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO124_Pos (28UL)                 /*!< DSP0N1GPIO124 (Bit 28)                                */
37839 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO124_Msk (0x10000000UL)         /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
37840 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO123_Pos (27UL)                 /*!< DSP0N1GPIO123 (Bit 27)                                */
37841 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO123_Msk (0x8000000UL)          /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
37842 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO122_Pos (26UL)                 /*!< DSP0N1GPIO122 (Bit 26)                                */
37843 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO122_Msk (0x4000000UL)          /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
37844 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO121_Pos (25UL)                 /*!< DSP0N1GPIO121 (Bit 25)                                */
37845 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO121_Msk (0x2000000UL)          /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
37846 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO120_Pos (24UL)                 /*!< DSP0N1GPIO120 (Bit 24)                                */
37847 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO120_Msk (0x1000000UL)          /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
37848 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO119_Pos (23UL)                 /*!< DSP0N1GPIO119 (Bit 23)                                */
37849 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO119_Msk (0x800000UL)           /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
37850 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO118_Pos (22UL)                 /*!< DSP0N1GPIO118 (Bit 22)                                */
37851 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO118_Msk (0x400000UL)           /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
37852 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO117_Pos (21UL)                 /*!< DSP0N1GPIO117 (Bit 21)                                */
37853 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO117_Msk (0x200000UL)           /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
37854 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO116_Pos (20UL)                 /*!< DSP0N1GPIO116 (Bit 20)                                */
37855 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO116_Msk (0x100000UL)           /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
37856 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO115_Pos (19UL)                 /*!< DSP0N1GPIO115 (Bit 19)                                */
37857 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO115_Msk (0x80000UL)            /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
37858 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO114_Pos (18UL)                 /*!< DSP0N1GPIO114 (Bit 18)                                */
37859 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO114_Msk (0x40000UL)            /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
37860 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO113_Pos (17UL)                 /*!< DSP0N1GPIO113 (Bit 17)                                */
37861 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO113_Msk (0x20000UL)            /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
37862 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO112_Pos (16UL)                 /*!< DSP0N1GPIO112 (Bit 16)                                */
37863 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO112_Msk (0x10000UL)            /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
37864 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO111_Pos (15UL)                 /*!< DSP0N1GPIO111 (Bit 15)                                */
37865 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO111_Msk (0x8000UL)             /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
37866 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO110_Pos (14UL)                 /*!< DSP0N1GPIO110 (Bit 14)                                */
37867 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO110_Msk (0x4000UL)             /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
37868 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO109_Pos (13UL)                 /*!< DSP0N1GPIO109 (Bit 13)                                */
37869 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO109_Msk (0x2000UL)             /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
37870 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO108_Pos (12UL)                 /*!< DSP0N1GPIO108 (Bit 12)                                */
37871 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO108_Msk (0x1000UL)             /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
37872 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO107_Pos (11UL)                 /*!< DSP0N1GPIO107 (Bit 11)                                */
37873 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO107_Msk (0x800UL)              /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
37874 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO106_Pos (10UL)                 /*!< DSP0N1GPIO106 (Bit 10)                                */
37875 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO106_Msk (0x400UL)              /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
37876 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO105_Pos (9UL)                  /*!< DSP0N1GPIO105 (Bit 9)                                 */
37877 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO105_Msk (0x200UL)              /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
37878 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO104_Pos (8UL)                  /*!< DSP0N1GPIO104 (Bit 8)                                 */
37879 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO104_Msk (0x100UL)              /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
37880 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO103_Pos (7UL)                  /*!< DSP0N1GPIO103 (Bit 7)                                 */
37881 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO103_Msk (0x80UL)               /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
37882 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO102_Pos (6UL)                  /*!< DSP0N1GPIO102 (Bit 6)                                 */
37883 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO102_Msk (0x40UL)               /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
37884 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO101_Pos (5UL)                  /*!< DSP0N1GPIO101 (Bit 5)                                 */
37885 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO101_Msk (0x20UL)               /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
37886 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO100_Pos (4UL)                  /*!< DSP0N1GPIO100 (Bit 4)                                 */
37887 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO100_Msk (0x10UL)               /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
37888 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO99_Pos (3UL)                   /*!< DSP0N1GPIO99 (Bit 3)                                  */
37889 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO99_Msk (0x8UL)                 /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
37890 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO98_Pos (2UL)                   /*!< DSP0N1GPIO98 (Bit 2)                                  */
37891 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO98_Msk (0x4UL)                 /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
37892 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO97_Pos (1UL)                   /*!< DSP0N1GPIO97 (Bit 1)                                  */
37893 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO97_Msk (0x2UL)                 /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
37894 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO96_Pos (0UL)                   /*!< DSP0N1GPIO96 (Bit 0)                                  */
37895 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO96_Msk (0x1UL)                 /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
37896 /* =====================================================  DSP1N0INT0EN  ====================================================== */
37897 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO31_Pos (31UL)                   /*!< DSP1N0GPIO31 (Bit 31)                                 */
37898 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO31_Msk (0x80000000UL)           /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
37899 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO30_Pos (30UL)                   /*!< DSP1N0GPIO30 (Bit 30)                                 */
37900 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO30_Msk (0x40000000UL)           /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
37901 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO29_Pos (29UL)                   /*!< DSP1N0GPIO29 (Bit 29)                                 */
37902 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO29_Msk (0x20000000UL)           /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
37903 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO28_Pos (28UL)                   /*!< DSP1N0GPIO28 (Bit 28)                                 */
37904 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO28_Msk (0x10000000UL)           /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
37905 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO27_Pos (27UL)                   /*!< DSP1N0GPIO27 (Bit 27)                                 */
37906 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO27_Msk (0x8000000UL)            /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
37907 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO26_Pos (26UL)                   /*!< DSP1N0GPIO26 (Bit 26)                                 */
37908 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO26_Msk (0x4000000UL)            /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
37909 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO25_Pos (25UL)                   /*!< DSP1N0GPIO25 (Bit 25)                                 */
37910 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO25_Msk (0x2000000UL)            /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
37911 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO24_Pos (24UL)                   /*!< DSP1N0GPIO24 (Bit 24)                                 */
37912 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO24_Msk (0x1000000UL)            /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
37913 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO23_Pos (23UL)                   /*!< DSP1N0GPIO23 (Bit 23)                                 */
37914 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO23_Msk (0x800000UL)             /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
37915 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO22_Pos (22UL)                   /*!< DSP1N0GPIO22 (Bit 22)                                 */
37916 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO22_Msk (0x400000UL)             /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
37917 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO21_Pos (21UL)                   /*!< DSP1N0GPIO21 (Bit 21)                                 */
37918 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO21_Msk (0x200000UL)             /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
37919 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO20_Pos (20UL)                   /*!< DSP1N0GPIO20 (Bit 20)                                 */
37920 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO20_Msk (0x100000UL)             /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
37921 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO19_Pos (19UL)                   /*!< DSP1N0GPIO19 (Bit 19)                                 */
37922 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO19_Msk (0x80000UL)              /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
37923 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO18_Pos (18UL)                   /*!< DSP1N0GPIO18 (Bit 18)                                 */
37924 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO18_Msk (0x40000UL)              /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
37925 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO17_Pos (17UL)                   /*!< DSP1N0GPIO17 (Bit 17)                                 */
37926 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO17_Msk (0x20000UL)              /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
37927 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO16_Pos (16UL)                   /*!< DSP1N0GPIO16 (Bit 16)                                 */
37928 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO16_Msk (0x10000UL)              /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
37929 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO15_Pos (15UL)                   /*!< DSP1N0GPIO15 (Bit 15)                                 */
37930 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO15_Msk (0x8000UL)               /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
37931 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO14_Pos (14UL)                   /*!< DSP1N0GPIO14 (Bit 14)                                 */
37932 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO14_Msk (0x4000UL)               /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
37933 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO13_Pos (13UL)                   /*!< DSP1N0GPIO13 (Bit 13)                                 */
37934 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO13_Msk (0x2000UL)               /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
37935 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO12_Pos (12UL)                   /*!< DSP1N0GPIO12 (Bit 12)                                 */
37936 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO12_Msk (0x1000UL)               /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
37937 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO11_Pos (11UL)                   /*!< DSP1N0GPIO11 (Bit 11)                                 */
37938 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO11_Msk (0x800UL)                /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
37939 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO10_Pos (10UL)                   /*!< DSP1N0GPIO10 (Bit 10)                                 */
37940 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO10_Msk (0x400UL)                /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
37941 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO9_Pos (9UL)                     /*!< DSP1N0GPIO9 (Bit 9)                                   */
37942 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO9_Msk (0x200UL)                 /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
37943 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO8_Pos (8UL)                     /*!< DSP1N0GPIO8 (Bit 8)                                   */
37944 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO8_Msk (0x100UL)                 /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
37945 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO7_Pos (7UL)                     /*!< DSP1N0GPIO7 (Bit 7)                                   */
37946 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO7_Msk (0x80UL)                  /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
37947 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO6_Pos (6UL)                     /*!< DSP1N0GPIO6 (Bit 6)                                   */
37948 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO6_Msk (0x40UL)                  /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
37949 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO5_Pos (5UL)                     /*!< DSP1N0GPIO5 (Bit 5)                                   */
37950 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO5_Msk (0x20UL)                  /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
37951 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO4_Pos (4UL)                     /*!< DSP1N0GPIO4 (Bit 4)                                   */
37952 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO4_Msk (0x10UL)                  /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
37953 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO3_Pos (3UL)                     /*!< DSP1N0GPIO3 (Bit 3)                                   */
37954 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO3_Msk (0x8UL)                   /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
37955 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO2_Pos (2UL)                     /*!< DSP1N0GPIO2 (Bit 2)                                   */
37956 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO2_Msk (0x4UL)                   /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
37957 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO1_Pos (1UL)                     /*!< DSP1N0GPIO1 (Bit 1)                                   */
37958 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO1_Msk (0x2UL)                   /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
37959 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO0_Pos (0UL)                     /*!< DSP1N0GPIO0 (Bit 0)                                   */
37960 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO0_Msk (0x1UL)                   /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
37961 /* ====================================================  DSP1N0INT0STAT  ===================================================== */
37962 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO31_Pos (31UL)                 /*!< DSP1N0GPIO31 (Bit 31)                                 */
37963 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO31_Msk (0x80000000UL)         /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
37964 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO30_Pos (30UL)                 /*!< DSP1N0GPIO30 (Bit 30)                                 */
37965 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO30_Msk (0x40000000UL)         /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
37966 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO29_Pos (29UL)                 /*!< DSP1N0GPIO29 (Bit 29)                                 */
37967 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO29_Msk (0x20000000UL)         /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
37968 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO28_Pos (28UL)                 /*!< DSP1N0GPIO28 (Bit 28)                                 */
37969 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO28_Msk (0x10000000UL)         /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
37970 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO27_Pos (27UL)                 /*!< DSP1N0GPIO27 (Bit 27)                                 */
37971 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO27_Msk (0x8000000UL)          /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
37972 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO26_Pos (26UL)                 /*!< DSP1N0GPIO26 (Bit 26)                                 */
37973 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO26_Msk (0x4000000UL)          /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
37974 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO25_Pos (25UL)                 /*!< DSP1N0GPIO25 (Bit 25)                                 */
37975 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO25_Msk (0x2000000UL)          /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
37976 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO24_Pos (24UL)                 /*!< DSP1N0GPIO24 (Bit 24)                                 */
37977 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO24_Msk (0x1000000UL)          /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
37978 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO23_Pos (23UL)                 /*!< DSP1N0GPIO23 (Bit 23)                                 */
37979 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO23_Msk (0x800000UL)           /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
37980 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO22_Pos (22UL)                 /*!< DSP1N0GPIO22 (Bit 22)                                 */
37981 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO22_Msk (0x400000UL)           /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
37982 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO21_Pos (21UL)                 /*!< DSP1N0GPIO21 (Bit 21)                                 */
37983 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO21_Msk (0x200000UL)           /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
37984 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO20_Pos (20UL)                 /*!< DSP1N0GPIO20 (Bit 20)                                 */
37985 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO20_Msk (0x100000UL)           /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
37986 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO19_Pos (19UL)                 /*!< DSP1N0GPIO19 (Bit 19)                                 */
37987 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO19_Msk (0x80000UL)            /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
37988 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO18_Pos (18UL)                 /*!< DSP1N0GPIO18 (Bit 18)                                 */
37989 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO18_Msk (0x40000UL)            /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
37990 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO17_Pos (17UL)                 /*!< DSP1N0GPIO17 (Bit 17)                                 */
37991 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO17_Msk (0x20000UL)            /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
37992 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO16_Pos (16UL)                 /*!< DSP1N0GPIO16 (Bit 16)                                 */
37993 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO16_Msk (0x10000UL)            /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
37994 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO15_Pos (15UL)                 /*!< DSP1N0GPIO15 (Bit 15)                                 */
37995 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO15_Msk (0x8000UL)             /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
37996 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO14_Pos (14UL)                 /*!< DSP1N0GPIO14 (Bit 14)                                 */
37997 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO14_Msk (0x4000UL)             /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
37998 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO13_Pos (13UL)                 /*!< DSP1N0GPIO13 (Bit 13)                                 */
37999 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO13_Msk (0x2000UL)             /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
38000 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO12_Pos (12UL)                 /*!< DSP1N0GPIO12 (Bit 12)                                 */
38001 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO12_Msk (0x1000UL)             /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
38002 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO11_Pos (11UL)                 /*!< DSP1N0GPIO11 (Bit 11)                                 */
38003 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO11_Msk (0x800UL)              /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
38004 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO10_Pos (10UL)                 /*!< DSP1N0GPIO10 (Bit 10)                                 */
38005 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO10_Msk (0x400UL)              /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
38006 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO9_Pos (9UL)                   /*!< DSP1N0GPIO9 (Bit 9)                                   */
38007 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO9_Msk (0x200UL)               /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
38008 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO8_Pos (8UL)                   /*!< DSP1N0GPIO8 (Bit 8)                                   */
38009 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO8_Msk (0x100UL)               /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
38010 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO7_Pos (7UL)                   /*!< DSP1N0GPIO7 (Bit 7)                                   */
38011 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO7_Msk (0x80UL)                /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
38012 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO6_Pos (6UL)                   /*!< DSP1N0GPIO6 (Bit 6)                                   */
38013 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO6_Msk (0x40UL)                /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
38014 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO5_Pos (5UL)                   /*!< DSP1N0GPIO5 (Bit 5)                                   */
38015 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO5_Msk (0x20UL)                /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
38016 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO4_Pos (4UL)                   /*!< DSP1N0GPIO4 (Bit 4)                                   */
38017 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO4_Msk (0x10UL)                /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
38018 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO3_Pos (3UL)                   /*!< DSP1N0GPIO3 (Bit 3)                                   */
38019 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO3_Msk (0x8UL)                 /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
38020 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO2_Pos (2UL)                   /*!< DSP1N0GPIO2 (Bit 2)                                   */
38021 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO2_Msk (0x4UL)                 /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
38022 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO1_Pos (1UL)                   /*!< DSP1N0GPIO1 (Bit 1)                                   */
38023 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO1_Msk (0x2UL)                 /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
38024 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO0_Pos (0UL)                   /*!< DSP1N0GPIO0 (Bit 0)                                   */
38025 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO0_Msk (0x1UL)                 /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
38026 /* =====================================================  DSP1N0INT0CLR  ===================================================== */
38027 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO31_Pos (31UL)                  /*!< DSP1N0GPIO31 (Bit 31)                                 */
38028 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO31_Msk (0x80000000UL)          /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
38029 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO30_Pos (30UL)                  /*!< DSP1N0GPIO30 (Bit 30)                                 */
38030 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO30_Msk (0x40000000UL)          /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
38031 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO29_Pos (29UL)                  /*!< DSP1N0GPIO29 (Bit 29)                                 */
38032 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO29_Msk (0x20000000UL)          /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
38033 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO28_Pos (28UL)                  /*!< DSP1N0GPIO28 (Bit 28)                                 */
38034 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO28_Msk (0x10000000UL)          /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
38035 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO27_Pos (27UL)                  /*!< DSP1N0GPIO27 (Bit 27)                                 */
38036 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO27_Msk (0x8000000UL)           /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
38037 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO26_Pos (26UL)                  /*!< DSP1N0GPIO26 (Bit 26)                                 */
38038 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO26_Msk (0x4000000UL)           /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
38039 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO25_Pos (25UL)                  /*!< DSP1N0GPIO25 (Bit 25)                                 */
38040 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO25_Msk (0x2000000UL)           /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
38041 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO24_Pos (24UL)                  /*!< DSP1N0GPIO24 (Bit 24)                                 */
38042 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO24_Msk (0x1000000UL)           /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
38043 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO23_Pos (23UL)                  /*!< DSP1N0GPIO23 (Bit 23)                                 */
38044 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO23_Msk (0x800000UL)            /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
38045 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO22_Pos (22UL)                  /*!< DSP1N0GPIO22 (Bit 22)                                 */
38046 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO22_Msk (0x400000UL)            /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
38047 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO21_Pos (21UL)                  /*!< DSP1N0GPIO21 (Bit 21)                                 */
38048 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO21_Msk (0x200000UL)            /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
38049 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO20_Pos (20UL)                  /*!< DSP1N0GPIO20 (Bit 20)                                 */
38050 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO20_Msk (0x100000UL)            /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
38051 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO19_Pos (19UL)                  /*!< DSP1N0GPIO19 (Bit 19)                                 */
38052 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO19_Msk (0x80000UL)             /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
38053 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO18_Pos (18UL)                  /*!< DSP1N0GPIO18 (Bit 18)                                 */
38054 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO18_Msk (0x40000UL)             /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
38055 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO17_Pos (17UL)                  /*!< DSP1N0GPIO17 (Bit 17)                                 */
38056 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO17_Msk (0x20000UL)             /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
38057 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO16_Pos (16UL)                  /*!< DSP1N0GPIO16 (Bit 16)                                 */
38058 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO16_Msk (0x10000UL)             /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
38059 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO15_Pos (15UL)                  /*!< DSP1N0GPIO15 (Bit 15)                                 */
38060 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO15_Msk (0x8000UL)              /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
38061 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO14_Pos (14UL)                  /*!< DSP1N0GPIO14 (Bit 14)                                 */
38062 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO14_Msk (0x4000UL)              /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
38063 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO13_Pos (13UL)                  /*!< DSP1N0GPIO13 (Bit 13)                                 */
38064 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO13_Msk (0x2000UL)              /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
38065 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO12_Pos (12UL)                  /*!< DSP1N0GPIO12 (Bit 12)                                 */
38066 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO12_Msk (0x1000UL)              /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
38067 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO11_Pos (11UL)                  /*!< DSP1N0GPIO11 (Bit 11)                                 */
38068 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO11_Msk (0x800UL)               /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
38069 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO10_Pos (10UL)                  /*!< DSP1N0GPIO10 (Bit 10)                                 */
38070 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO10_Msk (0x400UL)               /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
38071 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO9_Pos (9UL)                    /*!< DSP1N0GPIO9 (Bit 9)                                   */
38072 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO9_Msk (0x200UL)                /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
38073 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO8_Pos (8UL)                    /*!< DSP1N0GPIO8 (Bit 8)                                   */
38074 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO8_Msk (0x100UL)                /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
38075 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO7_Pos (7UL)                    /*!< DSP1N0GPIO7 (Bit 7)                                   */
38076 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO7_Msk (0x80UL)                 /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
38077 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO6_Pos (6UL)                    /*!< DSP1N0GPIO6 (Bit 6)                                   */
38078 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO6_Msk (0x40UL)                 /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
38079 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO5_Pos (5UL)                    /*!< DSP1N0GPIO5 (Bit 5)                                   */
38080 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO5_Msk (0x20UL)                 /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
38081 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO4_Pos (4UL)                    /*!< DSP1N0GPIO4 (Bit 4)                                   */
38082 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO4_Msk (0x10UL)                 /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
38083 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO3_Pos (3UL)                    /*!< DSP1N0GPIO3 (Bit 3)                                   */
38084 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO3_Msk (0x8UL)                  /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
38085 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO2_Pos (2UL)                    /*!< DSP1N0GPIO2 (Bit 2)                                   */
38086 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO2_Msk (0x4UL)                  /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
38087 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO1_Pos (1UL)                    /*!< DSP1N0GPIO1 (Bit 1)                                   */
38088 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO1_Msk (0x2UL)                  /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
38089 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO0_Pos (0UL)                    /*!< DSP1N0GPIO0 (Bit 0)                                   */
38090 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO0_Msk (0x1UL)                  /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
38091 /* =====================================================  DSP1N0INT0SET  ===================================================== */
38092 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO31_Pos (31UL)                  /*!< DSP1N0GPIO31 (Bit 31)                                 */
38093 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO31_Msk (0x80000000UL)          /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
38094 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO30_Pos (30UL)                  /*!< DSP1N0GPIO30 (Bit 30)                                 */
38095 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO30_Msk (0x40000000UL)          /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
38096 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO29_Pos (29UL)                  /*!< DSP1N0GPIO29 (Bit 29)                                 */
38097 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO29_Msk (0x20000000UL)          /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
38098 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO28_Pos (28UL)                  /*!< DSP1N0GPIO28 (Bit 28)                                 */
38099 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO28_Msk (0x10000000UL)          /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
38100 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO27_Pos (27UL)                  /*!< DSP1N0GPIO27 (Bit 27)                                 */
38101 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO27_Msk (0x8000000UL)           /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
38102 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO26_Pos (26UL)                  /*!< DSP1N0GPIO26 (Bit 26)                                 */
38103 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO26_Msk (0x4000000UL)           /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
38104 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO25_Pos (25UL)                  /*!< DSP1N0GPIO25 (Bit 25)                                 */
38105 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO25_Msk (0x2000000UL)           /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
38106 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO24_Pos (24UL)                  /*!< DSP1N0GPIO24 (Bit 24)                                 */
38107 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO24_Msk (0x1000000UL)           /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
38108 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO23_Pos (23UL)                  /*!< DSP1N0GPIO23 (Bit 23)                                 */
38109 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO23_Msk (0x800000UL)            /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
38110 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO22_Pos (22UL)                  /*!< DSP1N0GPIO22 (Bit 22)                                 */
38111 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO22_Msk (0x400000UL)            /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
38112 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO21_Pos (21UL)                  /*!< DSP1N0GPIO21 (Bit 21)                                 */
38113 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO21_Msk (0x200000UL)            /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
38114 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO20_Pos (20UL)                  /*!< DSP1N0GPIO20 (Bit 20)                                 */
38115 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO20_Msk (0x100000UL)            /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
38116 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO19_Pos (19UL)                  /*!< DSP1N0GPIO19 (Bit 19)                                 */
38117 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO19_Msk (0x80000UL)             /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
38118 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO18_Pos (18UL)                  /*!< DSP1N0GPIO18 (Bit 18)                                 */
38119 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO18_Msk (0x40000UL)             /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
38120 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO17_Pos (17UL)                  /*!< DSP1N0GPIO17 (Bit 17)                                 */
38121 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO17_Msk (0x20000UL)             /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
38122 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO16_Pos (16UL)                  /*!< DSP1N0GPIO16 (Bit 16)                                 */
38123 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO16_Msk (0x10000UL)             /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
38124 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO15_Pos (15UL)                  /*!< DSP1N0GPIO15 (Bit 15)                                 */
38125 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO15_Msk (0x8000UL)              /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
38126 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO14_Pos (14UL)                  /*!< DSP1N0GPIO14 (Bit 14)                                 */
38127 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO14_Msk (0x4000UL)              /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
38128 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO13_Pos (13UL)                  /*!< DSP1N0GPIO13 (Bit 13)                                 */
38129 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO13_Msk (0x2000UL)              /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
38130 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO12_Pos (12UL)                  /*!< DSP1N0GPIO12 (Bit 12)                                 */
38131 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO12_Msk (0x1000UL)              /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
38132 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO11_Pos (11UL)                  /*!< DSP1N0GPIO11 (Bit 11)                                 */
38133 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO11_Msk (0x800UL)               /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
38134 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO10_Pos (10UL)                  /*!< DSP1N0GPIO10 (Bit 10)                                 */
38135 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO10_Msk (0x400UL)               /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
38136 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO9_Pos (9UL)                    /*!< DSP1N0GPIO9 (Bit 9)                                   */
38137 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO9_Msk (0x200UL)                /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
38138 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO8_Pos (8UL)                    /*!< DSP1N0GPIO8 (Bit 8)                                   */
38139 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO8_Msk (0x100UL)                /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
38140 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO7_Pos (7UL)                    /*!< DSP1N0GPIO7 (Bit 7)                                   */
38141 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO7_Msk (0x80UL)                 /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
38142 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO6_Pos (6UL)                    /*!< DSP1N0GPIO6 (Bit 6)                                   */
38143 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO6_Msk (0x40UL)                 /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
38144 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO5_Pos (5UL)                    /*!< DSP1N0GPIO5 (Bit 5)                                   */
38145 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO5_Msk (0x20UL)                 /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
38146 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO4_Pos (4UL)                    /*!< DSP1N0GPIO4 (Bit 4)                                   */
38147 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO4_Msk (0x10UL)                 /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
38148 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO3_Pos (3UL)                    /*!< DSP1N0GPIO3 (Bit 3)                                   */
38149 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO3_Msk (0x8UL)                  /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
38150 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO2_Pos (2UL)                    /*!< DSP1N0GPIO2 (Bit 2)                                   */
38151 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO2_Msk (0x4UL)                  /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
38152 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO1_Pos (1UL)                    /*!< DSP1N0GPIO1 (Bit 1)                                   */
38153 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO1_Msk (0x2UL)                  /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
38154 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO0_Pos (0UL)                    /*!< DSP1N0GPIO0 (Bit 0)                                   */
38155 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO0_Msk (0x1UL)                  /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
38156 /* =====================================================  DSP1N0INT1EN  ====================================================== */
38157 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO63_Pos (31UL)                   /*!< DSP1N0GPIO63 (Bit 31)                                 */
38158 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO63_Msk (0x80000000UL)           /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38159 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO62_Pos (30UL)                   /*!< DSP1N0GPIO62 (Bit 30)                                 */
38160 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO62_Msk (0x40000000UL)           /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38161 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO61_Pos (29UL)                   /*!< DSP1N0GPIO61 (Bit 29)                                 */
38162 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO61_Msk (0x20000000UL)           /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38163 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO60_Pos (28UL)                   /*!< DSP1N0GPIO60 (Bit 28)                                 */
38164 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO60_Msk (0x10000000UL)           /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38165 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO59_Pos (27UL)                   /*!< DSP1N0GPIO59 (Bit 27)                                 */
38166 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO59_Msk (0x8000000UL)            /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38167 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO58_Pos (26UL)                   /*!< DSP1N0GPIO58 (Bit 26)                                 */
38168 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO58_Msk (0x4000000UL)            /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38169 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO57_Pos (25UL)                   /*!< DSP1N0GPIO57 (Bit 25)                                 */
38170 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO57_Msk (0x2000000UL)            /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38171 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO56_Pos (24UL)                   /*!< DSP1N0GPIO56 (Bit 24)                                 */
38172 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO56_Msk (0x1000000UL)            /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38173 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO55_Pos (23UL)                   /*!< DSP1N0GPIO55 (Bit 23)                                 */
38174 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO55_Msk (0x800000UL)             /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38175 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO54_Pos (22UL)                   /*!< DSP1N0GPIO54 (Bit 22)                                 */
38176 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO54_Msk (0x400000UL)             /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38177 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO53_Pos (21UL)                   /*!< DSP1N0GPIO53 (Bit 21)                                 */
38178 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO53_Msk (0x200000UL)             /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38179 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO52_Pos (20UL)                   /*!< DSP1N0GPIO52 (Bit 20)                                 */
38180 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO52_Msk (0x100000UL)             /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38181 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO51_Pos (19UL)                   /*!< DSP1N0GPIO51 (Bit 19)                                 */
38182 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO51_Msk (0x80000UL)              /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38183 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO50_Pos (18UL)                   /*!< DSP1N0GPIO50 (Bit 18)                                 */
38184 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO50_Msk (0x40000UL)              /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38185 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO49_Pos (17UL)                   /*!< DSP1N0GPIO49 (Bit 17)                                 */
38186 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO49_Msk (0x20000UL)              /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38187 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO48_Pos (16UL)                   /*!< DSP1N0GPIO48 (Bit 16)                                 */
38188 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO48_Msk (0x10000UL)              /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38189 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO47_Pos (15UL)                   /*!< DSP1N0GPIO47 (Bit 15)                                 */
38190 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO47_Msk (0x8000UL)               /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38191 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO46_Pos (14UL)                   /*!< DSP1N0GPIO46 (Bit 14)                                 */
38192 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO46_Msk (0x4000UL)               /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38193 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO45_Pos (13UL)                   /*!< DSP1N0GPIO45 (Bit 13)                                 */
38194 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO45_Msk (0x2000UL)               /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38195 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO44_Pos (12UL)                   /*!< DSP1N0GPIO44 (Bit 12)                                 */
38196 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO44_Msk (0x1000UL)               /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38197 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO43_Pos (11UL)                   /*!< DSP1N0GPIO43 (Bit 11)                                 */
38198 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO43_Msk (0x800UL)                /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
38199 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO42_Pos (10UL)                   /*!< DSP1N0GPIO42 (Bit 10)                                 */
38200 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO42_Msk (0x400UL)                /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
38201 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO41_Pos (9UL)                    /*!< DSP1N0GPIO41 (Bit 9)                                  */
38202 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO41_Msk (0x200UL)                /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
38203 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO40_Pos (8UL)                    /*!< DSP1N0GPIO40 (Bit 8)                                  */
38204 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO40_Msk (0x100UL)                /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
38205 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO39_Pos (7UL)                    /*!< DSP1N0GPIO39 (Bit 7)                                  */
38206 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO39_Msk (0x80UL)                 /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
38207 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO38_Pos (6UL)                    /*!< DSP1N0GPIO38 (Bit 6)                                  */
38208 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO38_Msk (0x40UL)                 /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
38209 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO37_Pos (5UL)                    /*!< DSP1N0GPIO37 (Bit 5)                                  */
38210 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO37_Msk (0x20UL)                 /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
38211 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO36_Pos (4UL)                    /*!< DSP1N0GPIO36 (Bit 4)                                  */
38212 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO36_Msk (0x10UL)                 /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
38213 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO35_Pos (3UL)                    /*!< DSP1N0GPIO35 (Bit 3)                                  */
38214 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO35_Msk (0x8UL)                  /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
38215 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO34_Pos (2UL)                    /*!< DSP1N0GPIO34 (Bit 2)                                  */
38216 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO34_Msk (0x4UL)                  /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
38217 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO33_Pos (1UL)                    /*!< DSP1N0GPIO33 (Bit 1)                                  */
38218 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO33_Msk (0x2UL)                  /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
38219 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO32_Pos (0UL)                    /*!< DSP1N0GPIO32 (Bit 0)                                  */
38220 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO32_Msk (0x1UL)                  /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
38221 /* ====================================================  DSP1N0INT1STAT  ===================================================== */
38222 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO63_Pos (31UL)                 /*!< DSP1N0GPIO63 (Bit 31)                                 */
38223 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO63_Msk (0x80000000UL)         /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38224 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO62_Pos (30UL)                 /*!< DSP1N0GPIO62 (Bit 30)                                 */
38225 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO62_Msk (0x40000000UL)         /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38226 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO61_Pos (29UL)                 /*!< DSP1N0GPIO61 (Bit 29)                                 */
38227 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO61_Msk (0x20000000UL)         /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38228 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO60_Pos (28UL)                 /*!< DSP1N0GPIO60 (Bit 28)                                 */
38229 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO60_Msk (0x10000000UL)         /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38230 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO59_Pos (27UL)                 /*!< DSP1N0GPIO59 (Bit 27)                                 */
38231 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO59_Msk (0x8000000UL)          /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38232 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO58_Pos (26UL)                 /*!< DSP1N0GPIO58 (Bit 26)                                 */
38233 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO58_Msk (0x4000000UL)          /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38234 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO57_Pos (25UL)                 /*!< DSP1N0GPIO57 (Bit 25)                                 */
38235 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO57_Msk (0x2000000UL)          /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38236 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO56_Pos (24UL)                 /*!< DSP1N0GPIO56 (Bit 24)                                 */
38237 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO56_Msk (0x1000000UL)          /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38238 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO55_Pos (23UL)                 /*!< DSP1N0GPIO55 (Bit 23)                                 */
38239 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO55_Msk (0x800000UL)           /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38240 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO54_Pos (22UL)                 /*!< DSP1N0GPIO54 (Bit 22)                                 */
38241 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO54_Msk (0x400000UL)           /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38242 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO53_Pos (21UL)                 /*!< DSP1N0GPIO53 (Bit 21)                                 */
38243 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO53_Msk (0x200000UL)           /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38244 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO52_Pos (20UL)                 /*!< DSP1N0GPIO52 (Bit 20)                                 */
38245 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO52_Msk (0x100000UL)           /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38246 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO51_Pos (19UL)                 /*!< DSP1N0GPIO51 (Bit 19)                                 */
38247 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO51_Msk (0x80000UL)            /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38248 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO50_Pos (18UL)                 /*!< DSP1N0GPIO50 (Bit 18)                                 */
38249 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO50_Msk (0x40000UL)            /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38250 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO49_Pos (17UL)                 /*!< DSP1N0GPIO49 (Bit 17)                                 */
38251 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO49_Msk (0x20000UL)            /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38252 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO48_Pos (16UL)                 /*!< DSP1N0GPIO48 (Bit 16)                                 */
38253 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO48_Msk (0x10000UL)            /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38254 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO47_Pos (15UL)                 /*!< DSP1N0GPIO47 (Bit 15)                                 */
38255 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO47_Msk (0x8000UL)             /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38256 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO46_Pos (14UL)                 /*!< DSP1N0GPIO46 (Bit 14)                                 */
38257 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO46_Msk (0x4000UL)             /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38258 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO45_Pos (13UL)                 /*!< DSP1N0GPIO45 (Bit 13)                                 */
38259 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO45_Msk (0x2000UL)             /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38260 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO44_Pos (12UL)                 /*!< DSP1N0GPIO44 (Bit 12)                                 */
38261 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO44_Msk (0x1000UL)             /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38262 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO43_Pos (11UL)                 /*!< DSP1N0GPIO43 (Bit 11)                                 */
38263 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO43_Msk (0x800UL)              /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
38264 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO42_Pos (10UL)                 /*!< DSP1N0GPIO42 (Bit 10)                                 */
38265 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO42_Msk (0x400UL)              /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
38266 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO41_Pos (9UL)                  /*!< DSP1N0GPIO41 (Bit 9)                                  */
38267 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO41_Msk (0x200UL)              /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
38268 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO40_Pos (8UL)                  /*!< DSP1N0GPIO40 (Bit 8)                                  */
38269 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO40_Msk (0x100UL)              /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
38270 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO39_Pos (7UL)                  /*!< DSP1N0GPIO39 (Bit 7)                                  */
38271 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO39_Msk (0x80UL)               /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
38272 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO38_Pos (6UL)                  /*!< DSP1N0GPIO38 (Bit 6)                                  */
38273 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO38_Msk (0x40UL)               /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
38274 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO37_Pos (5UL)                  /*!< DSP1N0GPIO37 (Bit 5)                                  */
38275 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO37_Msk (0x20UL)               /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
38276 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO36_Pos (4UL)                  /*!< DSP1N0GPIO36 (Bit 4)                                  */
38277 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO36_Msk (0x10UL)               /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
38278 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO35_Pos (3UL)                  /*!< DSP1N0GPIO35 (Bit 3)                                  */
38279 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO35_Msk (0x8UL)                /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
38280 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO34_Pos (2UL)                  /*!< DSP1N0GPIO34 (Bit 2)                                  */
38281 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO34_Msk (0x4UL)                /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
38282 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO33_Pos (1UL)                  /*!< DSP1N0GPIO33 (Bit 1)                                  */
38283 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO33_Msk (0x2UL)                /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
38284 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO32_Pos (0UL)                  /*!< DSP1N0GPIO32 (Bit 0)                                  */
38285 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO32_Msk (0x1UL)                /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
38286 /* =====================================================  DSP1N0INT1CLR  ===================================================== */
38287 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO63_Pos (31UL)                  /*!< DSP1N0GPIO63 (Bit 31)                                 */
38288 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO63_Msk (0x80000000UL)          /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38289 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO62_Pos (30UL)                  /*!< DSP1N0GPIO62 (Bit 30)                                 */
38290 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO62_Msk (0x40000000UL)          /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38291 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO61_Pos (29UL)                  /*!< DSP1N0GPIO61 (Bit 29)                                 */
38292 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO61_Msk (0x20000000UL)          /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38293 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO60_Pos (28UL)                  /*!< DSP1N0GPIO60 (Bit 28)                                 */
38294 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO60_Msk (0x10000000UL)          /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38295 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO59_Pos (27UL)                  /*!< DSP1N0GPIO59 (Bit 27)                                 */
38296 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO59_Msk (0x8000000UL)           /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38297 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO58_Pos (26UL)                  /*!< DSP1N0GPIO58 (Bit 26)                                 */
38298 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO58_Msk (0x4000000UL)           /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38299 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO57_Pos (25UL)                  /*!< DSP1N0GPIO57 (Bit 25)                                 */
38300 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO57_Msk (0x2000000UL)           /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38301 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO56_Pos (24UL)                  /*!< DSP1N0GPIO56 (Bit 24)                                 */
38302 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO56_Msk (0x1000000UL)           /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38303 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO55_Pos (23UL)                  /*!< DSP1N0GPIO55 (Bit 23)                                 */
38304 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO55_Msk (0x800000UL)            /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38305 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO54_Pos (22UL)                  /*!< DSP1N0GPIO54 (Bit 22)                                 */
38306 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO54_Msk (0x400000UL)            /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38307 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO53_Pos (21UL)                  /*!< DSP1N0GPIO53 (Bit 21)                                 */
38308 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO53_Msk (0x200000UL)            /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38309 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO52_Pos (20UL)                  /*!< DSP1N0GPIO52 (Bit 20)                                 */
38310 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO52_Msk (0x100000UL)            /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38311 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO51_Pos (19UL)                  /*!< DSP1N0GPIO51 (Bit 19)                                 */
38312 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO51_Msk (0x80000UL)             /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38313 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO50_Pos (18UL)                  /*!< DSP1N0GPIO50 (Bit 18)                                 */
38314 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO50_Msk (0x40000UL)             /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38315 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO49_Pos (17UL)                  /*!< DSP1N0GPIO49 (Bit 17)                                 */
38316 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO49_Msk (0x20000UL)             /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38317 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO48_Pos (16UL)                  /*!< DSP1N0GPIO48 (Bit 16)                                 */
38318 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO48_Msk (0x10000UL)             /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38319 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO47_Pos (15UL)                  /*!< DSP1N0GPIO47 (Bit 15)                                 */
38320 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO47_Msk (0x8000UL)              /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38321 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO46_Pos (14UL)                  /*!< DSP1N0GPIO46 (Bit 14)                                 */
38322 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO46_Msk (0x4000UL)              /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38323 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO45_Pos (13UL)                  /*!< DSP1N0GPIO45 (Bit 13)                                 */
38324 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO45_Msk (0x2000UL)              /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38325 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO44_Pos (12UL)                  /*!< DSP1N0GPIO44 (Bit 12)                                 */
38326 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO44_Msk (0x1000UL)              /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38327 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO43_Pos (11UL)                  /*!< DSP1N0GPIO43 (Bit 11)                                 */
38328 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO43_Msk (0x800UL)               /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
38329 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO42_Pos (10UL)                  /*!< DSP1N0GPIO42 (Bit 10)                                 */
38330 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO42_Msk (0x400UL)               /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
38331 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO41_Pos (9UL)                   /*!< DSP1N0GPIO41 (Bit 9)                                  */
38332 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO41_Msk (0x200UL)               /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
38333 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO40_Pos (8UL)                   /*!< DSP1N0GPIO40 (Bit 8)                                  */
38334 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO40_Msk (0x100UL)               /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
38335 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO39_Pos (7UL)                   /*!< DSP1N0GPIO39 (Bit 7)                                  */
38336 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO39_Msk (0x80UL)                /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
38337 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO38_Pos (6UL)                   /*!< DSP1N0GPIO38 (Bit 6)                                  */
38338 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO38_Msk (0x40UL)                /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
38339 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO37_Pos (5UL)                   /*!< DSP1N0GPIO37 (Bit 5)                                  */
38340 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO37_Msk (0x20UL)                /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
38341 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO36_Pos (4UL)                   /*!< DSP1N0GPIO36 (Bit 4)                                  */
38342 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO36_Msk (0x10UL)                /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
38343 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO35_Pos (3UL)                   /*!< DSP1N0GPIO35 (Bit 3)                                  */
38344 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO35_Msk (0x8UL)                 /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
38345 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO34_Pos (2UL)                   /*!< DSP1N0GPIO34 (Bit 2)                                  */
38346 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO34_Msk (0x4UL)                 /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
38347 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO33_Pos (1UL)                   /*!< DSP1N0GPIO33 (Bit 1)                                  */
38348 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO33_Msk (0x2UL)                 /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
38349 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO32_Pos (0UL)                   /*!< DSP1N0GPIO32 (Bit 0)                                  */
38350 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO32_Msk (0x1UL)                 /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
38351 /* =====================================================  DSP1N0INT1SET  ===================================================== */
38352 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO63_Pos (31UL)                  /*!< DSP1N0GPIO63 (Bit 31)                                 */
38353 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO63_Msk (0x80000000UL)          /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38354 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO62_Pos (30UL)                  /*!< DSP1N0GPIO62 (Bit 30)                                 */
38355 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO62_Msk (0x40000000UL)          /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38356 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO61_Pos (29UL)                  /*!< DSP1N0GPIO61 (Bit 29)                                 */
38357 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO61_Msk (0x20000000UL)          /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38358 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO60_Pos (28UL)                  /*!< DSP1N0GPIO60 (Bit 28)                                 */
38359 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO60_Msk (0x10000000UL)          /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38360 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO59_Pos (27UL)                  /*!< DSP1N0GPIO59 (Bit 27)                                 */
38361 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO59_Msk (0x8000000UL)           /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38362 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO58_Pos (26UL)                  /*!< DSP1N0GPIO58 (Bit 26)                                 */
38363 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO58_Msk (0x4000000UL)           /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38364 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO57_Pos (25UL)                  /*!< DSP1N0GPIO57 (Bit 25)                                 */
38365 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO57_Msk (0x2000000UL)           /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38366 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO56_Pos (24UL)                  /*!< DSP1N0GPIO56 (Bit 24)                                 */
38367 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO56_Msk (0x1000000UL)           /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38368 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO55_Pos (23UL)                  /*!< DSP1N0GPIO55 (Bit 23)                                 */
38369 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO55_Msk (0x800000UL)            /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38370 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO54_Pos (22UL)                  /*!< DSP1N0GPIO54 (Bit 22)                                 */
38371 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO54_Msk (0x400000UL)            /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38372 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO53_Pos (21UL)                  /*!< DSP1N0GPIO53 (Bit 21)                                 */
38373 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO53_Msk (0x200000UL)            /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38374 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO52_Pos (20UL)                  /*!< DSP1N0GPIO52 (Bit 20)                                 */
38375 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO52_Msk (0x100000UL)            /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38376 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO51_Pos (19UL)                  /*!< DSP1N0GPIO51 (Bit 19)                                 */
38377 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO51_Msk (0x80000UL)             /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38378 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO50_Pos (18UL)                  /*!< DSP1N0GPIO50 (Bit 18)                                 */
38379 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO50_Msk (0x40000UL)             /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38380 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO49_Pos (17UL)                  /*!< DSP1N0GPIO49 (Bit 17)                                 */
38381 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO49_Msk (0x20000UL)             /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38382 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO48_Pos (16UL)                  /*!< DSP1N0GPIO48 (Bit 16)                                 */
38383 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO48_Msk (0x10000UL)             /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38384 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO47_Pos (15UL)                  /*!< DSP1N0GPIO47 (Bit 15)                                 */
38385 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO47_Msk (0x8000UL)              /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38386 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO46_Pos (14UL)                  /*!< DSP1N0GPIO46 (Bit 14)                                 */
38387 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO46_Msk (0x4000UL)              /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38388 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO45_Pos (13UL)                  /*!< DSP1N0GPIO45 (Bit 13)                                 */
38389 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO45_Msk (0x2000UL)              /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38390 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO44_Pos (12UL)                  /*!< DSP1N0GPIO44 (Bit 12)                                 */
38391 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO44_Msk (0x1000UL)              /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38392 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO43_Pos (11UL)                  /*!< DSP1N0GPIO43 (Bit 11)                                 */
38393 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO43_Msk (0x800UL)               /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
38394 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO42_Pos (10UL)                  /*!< DSP1N0GPIO42 (Bit 10)                                 */
38395 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO42_Msk (0x400UL)               /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
38396 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO41_Pos (9UL)                   /*!< DSP1N0GPIO41 (Bit 9)                                  */
38397 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO41_Msk (0x200UL)               /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
38398 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO40_Pos (8UL)                   /*!< DSP1N0GPIO40 (Bit 8)                                  */
38399 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO40_Msk (0x100UL)               /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
38400 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO39_Pos (7UL)                   /*!< DSP1N0GPIO39 (Bit 7)                                  */
38401 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO39_Msk (0x80UL)                /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
38402 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO38_Pos (6UL)                   /*!< DSP1N0GPIO38 (Bit 6)                                  */
38403 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO38_Msk (0x40UL)                /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
38404 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO37_Pos (5UL)                   /*!< DSP1N0GPIO37 (Bit 5)                                  */
38405 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO37_Msk (0x20UL)                /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
38406 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO36_Pos (4UL)                   /*!< DSP1N0GPIO36 (Bit 4)                                  */
38407 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO36_Msk (0x10UL)                /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
38408 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO35_Pos (3UL)                   /*!< DSP1N0GPIO35 (Bit 3)                                  */
38409 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO35_Msk (0x8UL)                 /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
38410 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO34_Pos (2UL)                   /*!< DSP1N0GPIO34 (Bit 2)                                  */
38411 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO34_Msk (0x4UL)                 /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
38412 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO33_Pos (1UL)                   /*!< DSP1N0GPIO33 (Bit 1)                                  */
38413 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO33_Msk (0x2UL)                 /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
38414 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO32_Pos (0UL)                   /*!< DSP1N0GPIO32 (Bit 0)                                  */
38415 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO32_Msk (0x1UL)                 /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
38416 /* =====================================================  DSP1N0INT2EN  ====================================================== */
38417 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO95_Pos (31UL)                   /*!< DSP1N0GPIO95 (Bit 31)                                 */
38418 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO95_Msk (0x80000000UL)           /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
38419 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO94_Pos (30UL)                   /*!< DSP1N0GPIO94 (Bit 30)                                 */
38420 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO94_Msk (0x40000000UL)           /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
38421 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO93_Pos (29UL)                   /*!< DSP1N0GPIO93 (Bit 29)                                 */
38422 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO93_Msk (0x20000000UL)           /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
38423 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO92_Pos (28UL)                   /*!< DSP1N0GPIO92 (Bit 28)                                 */
38424 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO92_Msk (0x10000000UL)           /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
38425 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO91_Pos (27UL)                   /*!< DSP1N0GPIO91 (Bit 27)                                 */
38426 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO91_Msk (0x8000000UL)            /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
38427 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO90_Pos (26UL)                   /*!< DSP1N0GPIO90 (Bit 26)                                 */
38428 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO90_Msk (0x4000000UL)            /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
38429 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO89_Pos (25UL)                   /*!< DSP1N0GPIO89 (Bit 25)                                 */
38430 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO89_Msk (0x2000000UL)            /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
38431 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO88_Pos (24UL)                   /*!< DSP1N0GPIO88 (Bit 24)                                 */
38432 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO88_Msk (0x1000000UL)            /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
38433 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO87_Pos (23UL)                   /*!< DSP1N0GPIO87 (Bit 23)                                 */
38434 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO87_Msk (0x800000UL)             /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
38435 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO86_Pos (22UL)                   /*!< DSP1N0GPIO86 (Bit 22)                                 */
38436 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO86_Msk (0x400000UL)             /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
38437 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO85_Pos (21UL)                   /*!< DSP1N0GPIO85 (Bit 21)                                 */
38438 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO85_Msk (0x200000UL)             /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
38439 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO84_Pos (20UL)                   /*!< DSP1N0GPIO84 (Bit 20)                                 */
38440 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO84_Msk (0x100000UL)             /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
38441 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO83_Pos (19UL)                   /*!< DSP1N0GPIO83 (Bit 19)                                 */
38442 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO83_Msk (0x80000UL)              /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
38443 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO82_Pos (18UL)                   /*!< DSP1N0GPIO82 (Bit 18)                                 */
38444 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO82_Msk (0x40000UL)              /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
38445 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO81_Pos (17UL)                   /*!< DSP1N0GPIO81 (Bit 17)                                 */
38446 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO81_Msk (0x20000UL)              /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
38447 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO80_Pos (16UL)                   /*!< DSP1N0GPIO80 (Bit 16)                                 */
38448 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO80_Msk (0x10000UL)              /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
38449 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO79_Pos (15UL)                   /*!< DSP1N0GPIO79 (Bit 15)                                 */
38450 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO79_Msk (0x8000UL)               /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
38451 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO78_Pos (14UL)                   /*!< DSP1N0GPIO78 (Bit 14)                                 */
38452 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO78_Msk (0x4000UL)               /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
38453 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO77_Pos (13UL)                   /*!< DSP1N0GPIO77 (Bit 13)                                 */
38454 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO77_Msk (0x2000UL)               /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
38455 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO76_Pos (12UL)                   /*!< DSP1N0GPIO76 (Bit 12)                                 */
38456 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO76_Msk (0x1000UL)               /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
38457 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO75_Pos (11UL)                   /*!< DSP1N0GPIO75 (Bit 11)                                 */
38458 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO75_Msk (0x800UL)                /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
38459 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO74_Pos (10UL)                   /*!< DSP1N0GPIO74 (Bit 10)                                 */
38460 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO74_Msk (0x400UL)                /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
38461 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO73_Pos (9UL)                    /*!< DSP1N0GPIO73 (Bit 9)                                  */
38462 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO73_Msk (0x200UL)                /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
38463 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO72_Pos (8UL)                    /*!< DSP1N0GPIO72 (Bit 8)                                  */
38464 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO72_Msk (0x100UL)                /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
38465 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO71_Pos (7UL)                    /*!< DSP1N0GPIO71 (Bit 7)                                  */
38466 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO71_Msk (0x80UL)                 /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
38467 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO70_Pos (6UL)                    /*!< DSP1N0GPIO70 (Bit 6)                                  */
38468 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO70_Msk (0x40UL)                 /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
38469 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO69_Pos (5UL)                    /*!< DSP1N0GPIO69 (Bit 5)                                  */
38470 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO69_Msk (0x20UL)                 /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
38471 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO68_Pos (4UL)                    /*!< DSP1N0GPIO68 (Bit 4)                                  */
38472 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO68_Msk (0x10UL)                 /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
38473 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO67_Pos (3UL)                    /*!< DSP1N0GPIO67 (Bit 3)                                  */
38474 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO67_Msk (0x8UL)                  /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
38475 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO66_Pos (2UL)                    /*!< DSP1N0GPIO66 (Bit 2)                                  */
38476 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO66_Msk (0x4UL)                  /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
38477 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO65_Pos (1UL)                    /*!< DSP1N0GPIO65 (Bit 1)                                  */
38478 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO65_Msk (0x2UL)                  /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
38479 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO64_Pos (0UL)                    /*!< DSP1N0GPIO64 (Bit 0)                                  */
38480 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO64_Msk (0x1UL)                  /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
38481 /* ====================================================  DSP1N0INT2STAT  ===================================================== */
38482 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO95_Pos (31UL)                 /*!< DSP1N0GPIO95 (Bit 31)                                 */
38483 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO95_Msk (0x80000000UL)         /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
38484 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO94_Pos (30UL)                 /*!< DSP1N0GPIO94 (Bit 30)                                 */
38485 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO94_Msk (0x40000000UL)         /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
38486 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO93_Pos (29UL)                 /*!< DSP1N0GPIO93 (Bit 29)                                 */
38487 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO93_Msk (0x20000000UL)         /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
38488 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO92_Pos (28UL)                 /*!< DSP1N0GPIO92 (Bit 28)                                 */
38489 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO92_Msk (0x10000000UL)         /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
38490 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO91_Pos (27UL)                 /*!< DSP1N0GPIO91 (Bit 27)                                 */
38491 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO91_Msk (0x8000000UL)          /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
38492 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO90_Pos (26UL)                 /*!< DSP1N0GPIO90 (Bit 26)                                 */
38493 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO90_Msk (0x4000000UL)          /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
38494 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO89_Pos (25UL)                 /*!< DSP1N0GPIO89 (Bit 25)                                 */
38495 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO89_Msk (0x2000000UL)          /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
38496 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO88_Pos (24UL)                 /*!< DSP1N0GPIO88 (Bit 24)                                 */
38497 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO88_Msk (0x1000000UL)          /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
38498 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO87_Pos (23UL)                 /*!< DSP1N0GPIO87 (Bit 23)                                 */
38499 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO87_Msk (0x800000UL)           /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
38500 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO86_Pos (22UL)                 /*!< DSP1N0GPIO86 (Bit 22)                                 */
38501 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO86_Msk (0x400000UL)           /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
38502 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO85_Pos (21UL)                 /*!< DSP1N0GPIO85 (Bit 21)                                 */
38503 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO85_Msk (0x200000UL)           /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
38504 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO84_Pos (20UL)                 /*!< DSP1N0GPIO84 (Bit 20)                                 */
38505 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO84_Msk (0x100000UL)           /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
38506 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO83_Pos (19UL)                 /*!< DSP1N0GPIO83 (Bit 19)                                 */
38507 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO83_Msk (0x80000UL)            /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
38508 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO82_Pos (18UL)                 /*!< DSP1N0GPIO82 (Bit 18)                                 */
38509 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO82_Msk (0x40000UL)            /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
38510 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO81_Pos (17UL)                 /*!< DSP1N0GPIO81 (Bit 17)                                 */
38511 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO81_Msk (0x20000UL)            /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
38512 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO80_Pos (16UL)                 /*!< DSP1N0GPIO80 (Bit 16)                                 */
38513 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO80_Msk (0x10000UL)            /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
38514 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO79_Pos (15UL)                 /*!< DSP1N0GPIO79 (Bit 15)                                 */
38515 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO79_Msk (0x8000UL)             /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
38516 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO78_Pos (14UL)                 /*!< DSP1N0GPIO78 (Bit 14)                                 */
38517 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO78_Msk (0x4000UL)             /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
38518 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO77_Pos (13UL)                 /*!< DSP1N0GPIO77 (Bit 13)                                 */
38519 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO77_Msk (0x2000UL)             /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
38520 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO76_Pos (12UL)                 /*!< DSP1N0GPIO76 (Bit 12)                                 */
38521 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO76_Msk (0x1000UL)             /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
38522 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO75_Pos (11UL)                 /*!< DSP1N0GPIO75 (Bit 11)                                 */
38523 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO75_Msk (0x800UL)              /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
38524 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO74_Pos (10UL)                 /*!< DSP1N0GPIO74 (Bit 10)                                 */
38525 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO74_Msk (0x400UL)              /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
38526 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO73_Pos (9UL)                  /*!< DSP1N0GPIO73 (Bit 9)                                  */
38527 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO73_Msk (0x200UL)              /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
38528 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO72_Pos (8UL)                  /*!< DSP1N0GPIO72 (Bit 8)                                  */
38529 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO72_Msk (0x100UL)              /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
38530 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO71_Pos (7UL)                  /*!< DSP1N0GPIO71 (Bit 7)                                  */
38531 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO71_Msk (0x80UL)               /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
38532 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO70_Pos (6UL)                  /*!< DSP1N0GPIO70 (Bit 6)                                  */
38533 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO70_Msk (0x40UL)               /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
38534 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO69_Pos (5UL)                  /*!< DSP1N0GPIO69 (Bit 5)                                  */
38535 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO69_Msk (0x20UL)               /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
38536 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO68_Pos (4UL)                  /*!< DSP1N0GPIO68 (Bit 4)                                  */
38537 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO68_Msk (0x10UL)               /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
38538 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO67_Pos (3UL)                  /*!< DSP1N0GPIO67 (Bit 3)                                  */
38539 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO67_Msk (0x8UL)                /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
38540 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO66_Pos (2UL)                  /*!< DSP1N0GPIO66 (Bit 2)                                  */
38541 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO66_Msk (0x4UL)                /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
38542 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO65_Pos (1UL)                  /*!< DSP1N0GPIO65 (Bit 1)                                  */
38543 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO65_Msk (0x2UL)                /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
38544 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO64_Pos (0UL)                  /*!< DSP1N0GPIO64 (Bit 0)                                  */
38545 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO64_Msk (0x1UL)                /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
38546 /* =====================================================  DSP1N0INT2CLR  ===================================================== */
38547 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO95_Pos (31UL)                  /*!< DSP1N0GPIO95 (Bit 31)                                 */
38548 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO95_Msk (0x80000000UL)          /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
38549 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO94_Pos (30UL)                  /*!< DSP1N0GPIO94 (Bit 30)                                 */
38550 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO94_Msk (0x40000000UL)          /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
38551 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO93_Pos (29UL)                  /*!< DSP1N0GPIO93 (Bit 29)                                 */
38552 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO93_Msk (0x20000000UL)          /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
38553 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO92_Pos (28UL)                  /*!< DSP1N0GPIO92 (Bit 28)                                 */
38554 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO92_Msk (0x10000000UL)          /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
38555 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO91_Pos (27UL)                  /*!< DSP1N0GPIO91 (Bit 27)                                 */
38556 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO91_Msk (0x8000000UL)           /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
38557 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO90_Pos (26UL)                  /*!< DSP1N0GPIO90 (Bit 26)                                 */
38558 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO90_Msk (0x4000000UL)           /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
38559 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO89_Pos (25UL)                  /*!< DSP1N0GPIO89 (Bit 25)                                 */
38560 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO89_Msk (0x2000000UL)           /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
38561 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO88_Pos (24UL)                  /*!< DSP1N0GPIO88 (Bit 24)                                 */
38562 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO88_Msk (0x1000000UL)           /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
38563 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO87_Pos (23UL)                  /*!< DSP1N0GPIO87 (Bit 23)                                 */
38564 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO87_Msk (0x800000UL)            /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
38565 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO86_Pos (22UL)                  /*!< DSP1N0GPIO86 (Bit 22)                                 */
38566 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO86_Msk (0x400000UL)            /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
38567 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO85_Pos (21UL)                  /*!< DSP1N0GPIO85 (Bit 21)                                 */
38568 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO85_Msk (0x200000UL)            /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
38569 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO84_Pos (20UL)                  /*!< DSP1N0GPIO84 (Bit 20)                                 */
38570 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO84_Msk (0x100000UL)            /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
38571 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO83_Pos (19UL)                  /*!< DSP1N0GPIO83 (Bit 19)                                 */
38572 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO83_Msk (0x80000UL)             /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
38573 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO82_Pos (18UL)                  /*!< DSP1N0GPIO82 (Bit 18)                                 */
38574 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO82_Msk (0x40000UL)             /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
38575 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO81_Pos (17UL)                  /*!< DSP1N0GPIO81 (Bit 17)                                 */
38576 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO81_Msk (0x20000UL)             /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
38577 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO80_Pos (16UL)                  /*!< DSP1N0GPIO80 (Bit 16)                                 */
38578 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO80_Msk (0x10000UL)             /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
38579 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO79_Pos (15UL)                  /*!< DSP1N0GPIO79 (Bit 15)                                 */
38580 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO79_Msk (0x8000UL)              /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
38581 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO78_Pos (14UL)                  /*!< DSP1N0GPIO78 (Bit 14)                                 */
38582 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO78_Msk (0x4000UL)              /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
38583 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO77_Pos (13UL)                  /*!< DSP1N0GPIO77 (Bit 13)                                 */
38584 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO77_Msk (0x2000UL)              /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
38585 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO76_Pos (12UL)                  /*!< DSP1N0GPIO76 (Bit 12)                                 */
38586 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO76_Msk (0x1000UL)              /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
38587 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO75_Pos (11UL)                  /*!< DSP1N0GPIO75 (Bit 11)                                 */
38588 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO75_Msk (0x800UL)               /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
38589 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO74_Pos (10UL)                  /*!< DSP1N0GPIO74 (Bit 10)                                 */
38590 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO74_Msk (0x400UL)               /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
38591 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO73_Pos (9UL)                   /*!< DSP1N0GPIO73 (Bit 9)                                  */
38592 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO73_Msk (0x200UL)               /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
38593 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO72_Pos (8UL)                   /*!< DSP1N0GPIO72 (Bit 8)                                  */
38594 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO72_Msk (0x100UL)               /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
38595 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO71_Pos (7UL)                   /*!< DSP1N0GPIO71 (Bit 7)                                  */
38596 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO71_Msk (0x80UL)                /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
38597 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO70_Pos (6UL)                   /*!< DSP1N0GPIO70 (Bit 6)                                  */
38598 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO70_Msk (0x40UL)                /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
38599 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO69_Pos (5UL)                   /*!< DSP1N0GPIO69 (Bit 5)                                  */
38600 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO69_Msk (0x20UL)                /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
38601 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO68_Pos (4UL)                   /*!< DSP1N0GPIO68 (Bit 4)                                  */
38602 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO68_Msk (0x10UL)                /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
38603 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO67_Pos (3UL)                   /*!< DSP1N0GPIO67 (Bit 3)                                  */
38604 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO67_Msk (0x8UL)                 /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
38605 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO66_Pos (2UL)                   /*!< DSP1N0GPIO66 (Bit 2)                                  */
38606 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO66_Msk (0x4UL)                 /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
38607 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO65_Pos (1UL)                   /*!< DSP1N0GPIO65 (Bit 1)                                  */
38608 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO65_Msk (0x2UL)                 /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
38609 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO64_Pos (0UL)                   /*!< DSP1N0GPIO64 (Bit 0)                                  */
38610 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO64_Msk (0x1UL)                 /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
38611 /* =====================================================  DSP1N0INT2SET  ===================================================== */
38612 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO95_Pos (31UL)                  /*!< DSP1N0GPIO95 (Bit 31)                                 */
38613 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO95_Msk (0x80000000UL)          /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
38614 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO94_Pos (30UL)                  /*!< DSP1N0GPIO94 (Bit 30)                                 */
38615 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO94_Msk (0x40000000UL)          /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
38616 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO93_Pos (29UL)                  /*!< DSP1N0GPIO93 (Bit 29)                                 */
38617 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO93_Msk (0x20000000UL)          /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
38618 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO92_Pos (28UL)                  /*!< DSP1N0GPIO92 (Bit 28)                                 */
38619 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO92_Msk (0x10000000UL)          /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
38620 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO91_Pos (27UL)                  /*!< DSP1N0GPIO91 (Bit 27)                                 */
38621 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO91_Msk (0x8000000UL)           /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
38622 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO90_Pos (26UL)                  /*!< DSP1N0GPIO90 (Bit 26)                                 */
38623 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO90_Msk (0x4000000UL)           /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
38624 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO89_Pos (25UL)                  /*!< DSP1N0GPIO89 (Bit 25)                                 */
38625 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO89_Msk (0x2000000UL)           /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
38626 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO88_Pos (24UL)                  /*!< DSP1N0GPIO88 (Bit 24)                                 */
38627 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO88_Msk (0x1000000UL)           /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
38628 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO87_Pos (23UL)                  /*!< DSP1N0GPIO87 (Bit 23)                                 */
38629 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO87_Msk (0x800000UL)            /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
38630 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO86_Pos (22UL)                  /*!< DSP1N0GPIO86 (Bit 22)                                 */
38631 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO86_Msk (0x400000UL)            /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
38632 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO85_Pos (21UL)                  /*!< DSP1N0GPIO85 (Bit 21)                                 */
38633 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO85_Msk (0x200000UL)            /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
38634 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO84_Pos (20UL)                  /*!< DSP1N0GPIO84 (Bit 20)                                 */
38635 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO84_Msk (0x100000UL)            /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
38636 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO83_Pos (19UL)                  /*!< DSP1N0GPIO83 (Bit 19)                                 */
38637 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO83_Msk (0x80000UL)             /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
38638 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO82_Pos (18UL)                  /*!< DSP1N0GPIO82 (Bit 18)                                 */
38639 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO82_Msk (0x40000UL)             /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
38640 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO81_Pos (17UL)                  /*!< DSP1N0GPIO81 (Bit 17)                                 */
38641 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO81_Msk (0x20000UL)             /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
38642 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO80_Pos (16UL)                  /*!< DSP1N0GPIO80 (Bit 16)                                 */
38643 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO80_Msk (0x10000UL)             /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
38644 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO79_Pos (15UL)                  /*!< DSP1N0GPIO79 (Bit 15)                                 */
38645 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO79_Msk (0x8000UL)              /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
38646 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO78_Pos (14UL)                  /*!< DSP1N0GPIO78 (Bit 14)                                 */
38647 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO78_Msk (0x4000UL)              /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
38648 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO77_Pos (13UL)                  /*!< DSP1N0GPIO77 (Bit 13)                                 */
38649 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO77_Msk (0x2000UL)              /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
38650 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO76_Pos (12UL)                  /*!< DSP1N0GPIO76 (Bit 12)                                 */
38651 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO76_Msk (0x1000UL)              /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
38652 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO75_Pos (11UL)                  /*!< DSP1N0GPIO75 (Bit 11)                                 */
38653 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO75_Msk (0x800UL)               /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
38654 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO74_Pos (10UL)                  /*!< DSP1N0GPIO74 (Bit 10)                                 */
38655 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO74_Msk (0x400UL)               /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
38656 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO73_Pos (9UL)                   /*!< DSP1N0GPIO73 (Bit 9)                                  */
38657 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO73_Msk (0x200UL)               /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
38658 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO72_Pos (8UL)                   /*!< DSP1N0GPIO72 (Bit 8)                                  */
38659 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO72_Msk (0x100UL)               /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
38660 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO71_Pos (7UL)                   /*!< DSP1N0GPIO71 (Bit 7)                                  */
38661 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO71_Msk (0x80UL)                /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
38662 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO70_Pos (6UL)                   /*!< DSP1N0GPIO70 (Bit 6)                                  */
38663 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO70_Msk (0x40UL)                /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
38664 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO69_Pos (5UL)                   /*!< DSP1N0GPIO69 (Bit 5)                                  */
38665 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO69_Msk (0x20UL)                /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
38666 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO68_Pos (4UL)                   /*!< DSP1N0GPIO68 (Bit 4)                                  */
38667 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO68_Msk (0x10UL)                /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
38668 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO67_Pos (3UL)                   /*!< DSP1N0GPIO67 (Bit 3)                                  */
38669 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO67_Msk (0x8UL)                 /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
38670 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO66_Pos (2UL)                   /*!< DSP1N0GPIO66 (Bit 2)                                  */
38671 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO66_Msk (0x4UL)                 /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
38672 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO65_Pos (1UL)                   /*!< DSP1N0GPIO65 (Bit 1)                                  */
38673 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO65_Msk (0x2UL)                 /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
38674 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO64_Pos (0UL)                   /*!< DSP1N0GPIO64 (Bit 0)                                  */
38675 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO64_Msk (0x1UL)                 /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
38676 /* =====================================================  DSP1N0INT3EN  ====================================================== */
38677 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO127_Pos (31UL)                  /*!< DSP1N0GPIO127 (Bit 31)                                */
38678 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO127_Msk (0x80000000UL)          /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
38679 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO126_Pos (30UL)                  /*!< DSP1N0GPIO126 (Bit 30)                                */
38680 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO126_Msk (0x40000000UL)          /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
38681 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO125_Pos (29UL)                  /*!< DSP1N0GPIO125 (Bit 29)                                */
38682 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO125_Msk (0x20000000UL)          /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
38683 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO124_Pos (28UL)                  /*!< DSP1N0GPIO124 (Bit 28)                                */
38684 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO124_Msk (0x10000000UL)          /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
38685 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO123_Pos (27UL)                  /*!< DSP1N0GPIO123 (Bit 27)                                */
38686 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO123_Msk (0x8000000UL)           /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
38687 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO122_Pos (26UL)                  /*!< DSP1N0GPIO122 (Bit 26)                                */
38688 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO122_Msk (0x4000000UL)           /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
38689 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO121_Pos (25UL)                  /*!< DSP1N0GPIO121 (Bit 25)                                */
38690 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO121_Msk (0x2000000UL)           /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
38691 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO120_Pos (24UL)                  /*!< DSP1N0GPIO120 (Bit 24)                                */
38692 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO120_Msk (0x1000000UL)           /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
38693 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO119_Pos (23UL)                  /*!< DSP1N0GPIO119 (Bit 23)                                */
38694 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO119_Msk (0x800000UL)            /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
38695 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO118_Pos (22UL)                  /*!< DSP1N0GPIO118 (Bit 22)                                */
38696 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO118_Msk (0x400000UL)            /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
38697 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO117_Pos (21UL)                  /*!< DSP1N0GPIO117 (Bit 21)                                */
38698 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO117_Msk (0x200000UL)            /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
38699 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO116_Pos (20UL)                  /*!< DSP1N0GPIO116 (Bit 20)                                */
38700 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO116_Msk (0x100000UL)            /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
38701 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO115_Pos (19UL)                  /*!< DSP1N0GPIO115 (Bit 19)                                */
38702 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO115_Msk (0x80000UL)             /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
38703 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO114_Pos (18UL)                  /*!< DSP1N0GPIO114 (Bit 18)                                */
38704 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO114_Msk (0x40000UL)             /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
38705 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO113_Pos (17UL)                  /*!< DSP1N0GPIO113 (Bit 17)                                */
38706 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO113_Msk (0x20000UL)             /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
38707 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO112_Pos (16UL)                  /*!< DSP1N0GPIO112 (Bit 16)                                */
38708 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO112_Msk (0x10000UL)             /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
38709 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO111_Pos (15UL)                  /*!< DSP1N0GPIO111 (Bit 15)                                */
38710 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO111_Msk (0x8000UL)              /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
38711 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO110_Pos (14UL)                  /*!< DSP1N0GPIO110 (Bit 14)                                */
38712 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO110_Msk (0x4000UL)              /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
38713 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO109_Pos (13UL)                  /*!< DSP1N0GPIO109 (Bit 13)                                */
38714 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO109_Msk (0x2000UL)              /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
38715 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO108_Pos (12UL)                  /*!< DSP1N0GPIO108 (Bit 12)                                */
38716 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO108_Msk (0x1000UL)              /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
38717 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO107_Pos (11UL)                  /*!< DSP1N0GPIO107 (Bit 11)                                */
38718 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO107_Msk (0x800UL)               /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
38719 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO106_Pos (10UL)                  /*!< DSP1N0GPIO106 (Bit 10)                                */
38720 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO106_Msk (0x400UL)               /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
38721 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO105_Pos (9UL)                   /*!< DSP1N0GPIO105 (Bit 9)                                 */
38722 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO105_Msk (0x200UL)               /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
38723 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO104_Pos (8UL)                   /*!< DSP1N0GPIO104 (Bit 8)                                 */
38724 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO104_Msk (0x100UL)               /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
38725 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO103_Pos (7UL)                   /*!< DSP1N0GPIO103 (Bit 7)                                 */
38726 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO103_Msk (0x80UL)                /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
38727 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO102_Pos (6UL)                   /*!< DSP1N0GPIO102 (Bit 6)                                 */
38728 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO102_Msk (0x40UL)                /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
38729 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO101_Pos (5UL)                   /*!< DSP1N0GPIO101 (Bit 5)                                 */
38730 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO101_Msk (0x20UL)                /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
38731 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO100_Pos (4UL)                   /*!< DSP1N0GPIO100 (Bit 4)                                 */
38732 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO100_Msk (0x10UL)                /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
38733 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO99_Pos (3UL)                    /*!< DSP1N0GPIO99 (Bit 3)                                  */
38734 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO99_Msk (0x8UL)                  /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
38735 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO98_Pos (2UL)                    /*!< DSP1N0GPIO98 (Bit 2)                                  */
38736 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO98_Msk (0x4UL)                  /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
38737 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO97_Pos (1UL)                    /*!< DSP1N0GPIO97 (Bit 1)                                  */
38738 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO97_Msk (0x2UL)                  /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
38739 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO96_Pos (0UL)                    /*!< DSP1N0GPIO96 (Bit 0)                                  */
38740 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO96_Msk (0x1UL)                  /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
38741 /* ====================================================  DSP1N0INT3STAT  ===================================================== */
38742 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO127_Pos (31UL)                /*!< DSP1N0GPIO127 (Bit 31)                                */
38743 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO127_Msk (0x80000000UL)        /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
38744 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO126_Pos (30UL)                /*!< DSP1N0GPIO126 (Bit 30)                                */
38745 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO126_Msk (0x40000000UL)        /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
38746 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO125_Pos (29UL)                /*!< DSP1N0GPIO125 (Bit 29)                                */
38747 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO125_Msk (0x20000000UL)        /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
38748 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO124_Pos (28UL)                /*!< DSP1N0GPIO124 (Bit 28)                                */
38749 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO124_Msk (0x10000000UL)        /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
38750 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO123_Pos (27UL)                /*!< DSP1N0GPIO123 (Bit 27)                                */
38751 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO123_Msk (0x8000000UL)         /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
38752 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO122_Pos (26UL)                /*!< DSP1N0GPIO122 (Bit 26)                                */
38753 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO122_Msk (0x4000000UL)         /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
38754 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO121_Pos (25UL)                /*!< DSP1N0GPIO121 (Bit 25)                                */
38755 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO121_Msk (0x2000000UL)         /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
38756 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO120_Pos (24UL)                /*!< DSP1N0GPIO120 (Bit 24)                                */
38757 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO120_Msk (0x1000000UL)         /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
38758 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO119_Pos (23UL)                /*!< DSP1N0GPIO119 (Bit 23)                                */
38759 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO119_Msk (0x800000UL)          /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
38760 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO118_Pos (22UL)                /*!< DSP1N0GPIO118 (Bit 22)                                */
38761 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO118_Msk (0x400000UL)          /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
38762 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO117_Pos (21UL)                /*!< DSP1N0GPIO117 (Bit 21)                                */
38763 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO117_Msk (0x200000UL)          /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
38764 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO116_Pos (20UL)                /*!< DSP1N0GPIO116 (Bit 20)                                */
38765 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO116_Msk (0x100000UL)          /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
38766 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO115_Pos (19UL)                /*!< DSP1N0GPIO115 (Bit 19)                                */
38767 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO115_Msk (0x80000UL)           /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
38768 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO114_Pos (18UL)                /*!< DSP1N0GPIO114 (Bit 18)                                */
38769 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO114_Msk (0x40000UL)           /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
38770 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO113_Pos (17UL)                /*!< DSP1N0GPIO113 (Bit 17)                                */
38771 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO113_Msk (0x20000UL)           /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
38772 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO112_Pos (16UL)                /*!< DSP1N0GPIO112 (Bit 16)                                */
38773 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO112_Msk (0x10000UL)           /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
38774 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO111_Pos (15UL)                /*!< DSP1N0GPIO111 (Bit 15)                                */
38775 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO111_Msk (0x8000UL)            /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
38776 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO110_Pos (14UL)                /*!< DSP1N0GPIO110 (Bit 14)                                */
38777 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO110_Msk (0x4000UL)            /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
38778 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO109_Pos (13UL)                /*!< DSP1N0GPIO109 (Bit 13)                                */
38779 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO109_Msk (0x2000UL)            /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
38780 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO108_Pos (12UL)                /*!< DSP1N0GPIO108 (Bit 12)                                */
38781 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO108_Msk (0x1000UL)            /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
38782 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO107_Pos (11UL)                /*!< DSP1N0GPIO107 (Bit 11)                                */
38783 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO107_Msk (0x800UL)             /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
38784 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO106_Pos (10UL)                /*!< DSP1N0GPIO106 (Bit 10)                                */
38785 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO106_Msk (0x400UL)             /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
38786 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO105_Pos (9UL)                 /*!< DSP1N0GPIO105 (Bit 9)                                 */
38787 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO105_Msk (0x200UL)             /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
38788 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO104_Pos (8UL)                 /*!< DSP1N0GPIO104 (Bit 8)                                 */
38789 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO104_Msk (0x100UL)             /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
38790 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO103_Pos (7UL)                 /*!< DSP1N0GPIO103 (Bit 7)                                 */
38791 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO103_Msk (0x80UL)              /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
38792 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO102_Pos (6UL)                 /*!< DSP1N0GPIO102 (Bit 6)                                 */
38793 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO102_Msk (0x40UL)              /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
38794 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO101_Pos (5UL)                 /*!< DSP1N0GPIO101 (Bit 5)                                 */
38795 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO101_Msk (0x20UL)              /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
38796 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO100_Pos (4UL)                 /*!< DSP1N0GPIO100 (Bit 4)                                 */
38797 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO100_Msk (0x10UL)              /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
38798 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO99_Pos (3UL)                  /*!< DSP1N0GPIO99 (Bit 3)                                  */
38799 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO99_Msk (0x8UL)                /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
38800 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO98_Pos (2UL)                  /*!< DSP1N0GPIO98 (Bit 2)                                  */
38801 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO98_Msk (0x4UL)                /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
38802 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO97_Pos (1UL)                  /*!< DSP1N0GPIO97 (Bit 1)                                  */
38803 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO97_Msk (0x2UL)                /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
38804 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO96_Pos (0UL)                  /*!< DSP1N0GPIO96 (Bit 0)                                  */
38805 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO96_Msk (0x1UL)                /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
38806 /* =====================================================  DSP1N0INT3CLR  ===================================================== */
38807 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO127_Pos (31UL)                 /*!< DSP1N0GPIO127 (Bit 31)                                */
38808 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO127_Msk (0x80000000UL)         /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
38809 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO126_Pos (30UL)                 /*!< DSP1N0GPIO126 (Bit 30)                                */
38810 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO126_Msk (0x40000000UL)         /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
38811 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO125_Pos (29UL)                 /*!< DSP1N0GPIO125 (Bit 29)                                */
38812 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO125_Msk (0x20000000UL)         /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
38813 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO124_Pos (28UL)                 /*!< DSP1N0GPIO124 (Bit 28)                                */
38814 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO124_Msk (0x10000000UL)         /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
38815 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO123_Pos (27UL)                 /*!< DSP1N0GPIO123 (Bit 27)                                */
38816 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO123_Msk (0x8000000UL)          /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
38817 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO122_Pos (26UL)                 /*!< DSP1N0GPIO122 (Bit 26)                                */
38818 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO122_Msk (0x4000000UL)          /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
38819 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO121_Pos (25UL)                 /*!< DSP1N0GPIO121 (Bit 25)                                */
38820 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO121_Msk (0x2000000UL)          /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
38821 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO120_Pos (24UL)                 /*!< DSP1N0GPIO120 (Bit 24)                                */
38822 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO120_Msk (0x1000000UL)          /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
38823 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO119_Pos (23UL)                 /*!< DSP1N0GPIO119 (Bit 23)                                */
38824 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO119_Msk (0x800000UL)           /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
38825 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO118_Pos (22UL)                 /*!< DSP1N0GPIO118 (Bit 22)                                */
38826 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO118_Msk (0x400000UL)           /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
38827 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO117_Pos (21UL)                 /*!< DSP1N0GPIO117 (Bit 21)                                */
38828 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO117_Msk (0x200000UL)           /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
38829 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO116_Pos (20UL)                 /*!< DSP1N0GPIO116 (Bit 20)                                */
38830 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO116_Msk (0x100000UL)           /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
38831 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO115_Pos (19UL)                 /*!< DSP1N0GPIO115 (Bit 19)                                */
38832 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO115_Msk (0x80000UL)            /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
38833 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO114_Pos (18UL)                 /*!< DSP1N0GPIO114 (Bit 18)                                */
38834 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO114_Msk (0x40000UL)            /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
38835 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO113_Pos (17UL)                 /*!< DSP1N0GPIO113 (Bit 17)                                */
38836 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO113_Msk (0x20000UL)            /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
38837 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO112_Pos (16UL)                 /*!< DSP1N0GPIO112 (Bit 16)                                */
38838 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO112_Msk (0x10000UL)            /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
38839 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO111_Pos (15UL)                 /*!< DSP1N0GPIO111 (Bit 15)                                */
38840 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO111_Msk (0x8000UL)             /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
38841 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO110_Pos (14UL)                 /*!< DSP1N0GPIO110 (Bit 14)                                */
38842 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO110_Msk (0x4000UL)             /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
38843 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO109_Pos (13UL)                 /*!< DSP1N0GPIO109 (Bit 13)                                */
38844 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO109_Msk (0x2000UL)             /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
38845 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO108_Pos (12UL)                 /*!< DSP1N0GPIO108 (Bit 12)                                */
38846 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO108_Msk (0x1000UL)             /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
38847 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO107_Pos (11UL)                 /*!< DSP1N0GPIO107 (Bit 11)                                */
38848 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO107_Msk (0x800UL)              /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
38849 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO106_Pos (10UL)                 /*!< DSP1N0GPIO106 (Bit 10)                                */
38850 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO106_Msk (0x400UL)              /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
38851 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO105_Pos (9UL)                  /*!< DSP1N0GPIO105 (Bit 9)                                 */
38852 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO105_Msk (0x200UL)              /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
38853 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO104_Pos (8UL)                  /*!< DSP1N0GPIO104 (Bit 8)                                 */
38854 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO104_Msk (0x100UL)              /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
38855 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO103_Pos (7UL)                  /*!< DSP1N0GPIO103 (Bit 7)                                 */
38856 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO103_Msk (0x80UL)               /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
38857 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO102_Pos (6UL)                  /*!< DSP1N0GPIO102 (Bit 6)                                 */
38858 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO102_Msk (0x40UL)               /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
38859 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO101_Pos (5UL)                  /*!< DSP1N0GPIO101 (Bit 5)                                 */
38860 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO101_Msk (0x20UL)               /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
38861 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO100_Pos (4UL)                  /*!< DSP1N0GPIO100 (Bit 4)                                 */
38862 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO100_Msk (0x10UL)               /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
38863 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO99_Pos (3UL)                   /*!< DSP1N0GPIO99 (Bit 3)                                  */
38864 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO99_Msk (0x8UL)                 /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
38865 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO98_Pos (2UL)                   /*!< DSP1N0GPIO98 (Bit 2)                                  */
38866 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO98_Msk (0x4UL)                 /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
38867 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO97_Pos (1UL)                   /*!< DSP1N0GPIO97 (Bit 1)                                  */
38868 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO97_Msk (0x2UL)                 /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
38869 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO96_Pos (0UL)                   /*!< DSP1N0GPIO96 (Bit 0)                                  */
38870 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO96_Msk (0x1UL)                 /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
38871 /* =====================================================  DSP1N0INT3SET  ===================================================== */
38872 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO127_Pos (31UL)                 /*!< DSP1N0GPIO127 (Bit 31)                                */
38873 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO127_Msk (0x80000000UL)         /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
38874 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO126_Pos (30UL)                 /*!< DSP1N0GPIO126 (Bit 30)                                */
38875 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO126_Msk (0x40000000UL)         /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
38876 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO125_Pos (29UL)                 /*!< DSP1N0GPIO125 (Bit 29)                                */
38877 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO125_Msk (0x20000000UL)         /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
38878 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO124_Pos (28UL)                 /*!< DSP1N0GPIO124 (Bit 28)                                */
38879 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO124_Msk (0x10000000UL)         /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
38880 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO123_Pos (27UL)                 /*!< DSP1N0GPIO123 (Bit 27)                                */
38881 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO123_Msk (0x8000000UL)          /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
38882 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO122_Pos (26UL)                 /*!< DSP1N0GPIO122 (Bit 26)                                */
38883 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO122_Msk (0x4000000UL)          /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
38884 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO121_Pos (25UL)                 /*!< DSP1N0GPIO121 (Bit 25)                                */
38885 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO121_Msk (0x2000000UL)          /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
38886 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO120_Pos (24UL)                 /*!< DSP1N0GPIO120 (Bit 24)                                */
38887 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO120_Msk (0x1000000UL)          /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
38888 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO119_Pos (23UL)                 /*!< DSP1N0GPIO119 (Bit 23)                                */
38889 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO119_Msk (0x800000UL)           /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
38890 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO118_Pos (22UL)                 /*!< DSP1N0GPIO118 (Bit 22)                                */
38891 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO118_Msk (0x400000UL)           /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
38892 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO117_Pos (21UL)                 /*!< DSP1N0GPIO117 (Bit 21)                                */
38893 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO117_Msk (0x200000UL)           /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
38894 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO116_Pos (20UL)                 /*!< DSP1N0GPIO116 (Bit 20)                                */
38895 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO116_Msk (0x100000UL)           /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
38896 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO115_Pos (19UL)                 /*!< DSP1N0GPIO115 (Bit 19)                                */
38897 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO115_Msk (0x80000UL)            /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
38898 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO114_Pos (18UL)                 /*!< DSP1N0GPIO114 (Bit 18)                                */
38899 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO114_Msk (0x40000UL)            /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
38900 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO113_Pos (17UL)                 /*!< DSP1N0GPIO113 (Bit 17)                                */
38901 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO113_Msk (0x20000UL)            /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
38902 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO112_Pos (16UL)                 /*!< DSP1N0GPIO112 (Bit 16)                                */
38903 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO112_Msk (0x10000UL)            /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
38904 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO111_Pos (15UL)                 /*!< DSP1N0GPIO111 (Bit 15)                                */
38905 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO111_Msk (0x8000UL)             /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
38906 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO110_Pos (14UL)                 /*!< DSP1N0GPIO110 (Bit 14)                                */
38907 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO110_Msk (0x4000UL)             /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
38908 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO109_Pos (13UL)                 /*!< DSP1N0GPIO109 (Bit 13)                                */
38909 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO109_Msk (0x2000UL)             /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
38910 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO108_Pos (12UL)                 /*!< DSP1N0GPIO108 (Bit 12)                                */
38911 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO108_Msk (0x1000UL)             /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
38912 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO107_Pos (11UL)                 /*!< DSP1N0GPIO107 (Bit 11)                                */
38913 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO107_Msk (0x800UL)              /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
38914 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO106_Pos (10UL)                 /*!< DSP1N0GPIO106 (Bit 10)                                */
38915 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO106_Msk (0x400UL)              /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
38916 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO105_Pos (9UL)                  /*!< DSP1N0GPIO105 (Bit 9)                                 */
38917 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO105_Msk (0x200UL)              /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
38918 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO104_Pos (8UL)                  /*!< DSP1N0GPIO104 (Bit 8)                                 */
38919 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO104_Msk (0x100UL)              /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
38920 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO103_Pos (7UL)                  /*!< DSP1N0GPIO103 (Bit 7)                                 */
38921 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO103_Msk (0x80UL)               /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
38922 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO102_Pos (6UL)                  /*!< DSP1N0GPIO102 (Bit 6)                                 */
38923 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO102_Msk (0x40UL)               /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
38924 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO101_Pos (5UL)                  /*!< DSP1N0GPIO101 (Bit 5)                                 */
38925 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO101_Msk (0x20UL)               /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
38926 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO100_Pos (4UL)                  /*!< DSP1N0GPIO100 (Bit 4)                                 */
38927 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO100_Msk (0x10UL)               /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
38928 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO99_Pos (3UL)                   /*!< DSP1N0GPIO99 (Bit 3)                                  */
38929 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO99_Msk (0x8UL)                 /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
38930 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO98_Pos (2UL)                   /*!< DSP1N0GPIO98 (Bit 2)                                  */
38931 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO98_Msk (0x4UL)                 /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
38932 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO97_Pos (1UL)                   /*!< DSP1N0GPIO97 (Bit 1)                                  */
38933 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO97_Msk (0x2UL)                 /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
38934 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO96_Pos (0UL)                   /*!< DSP1N0GPIO96 (Bit 0)                                  */
38935 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO96_Msk (0x1UL)                 /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
38936 /* =====================================================  DSP1N1INT0EN  ====================================================== */
38937 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO31_Pos (31UL)                   /*!< DSP1N1GPIO31 (Bit 31)                                 */
38938 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO31_Msk (0x80000000UL)           /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
38939 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO30_Pos (30UL)                   /*!< DSP1N1GPIO30 (Bit 30)                                 */
38940 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO30_Msk (0x40000000UL)           /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
38941 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO29_Pos (29UL)                   /*!< DSP1N1GPIO29 (Bit 29)                                 */
38942 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO29_Msk (0x20000000UL)           /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
38943 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO28_Pos (28UL)                   /*!< DSP1N1GPIO28 (Bit 28)                                 */
38944 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO28_Msk (0x10000000UL)           /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
38945 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO27_Pos (27UL)                   /*!< DSP1N1GPIO27 (Bit 27)                                 */
38946 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO27_Msk (0x8000000UL)            /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
38947 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO26_Pos (26UL)                   /*!< DSP1N1GPIO26 (Bit 26)                                 */
38948 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO26_Msk (0x4000000UL)            /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
38949 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO25_Pos (25UL)                   /*!< DSP1N1GPIO25 (Bit 25)                                 */
38950 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO25_Msk (0x2000000UL)            /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
38951 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO24_Pos (24UL)                   /*!< DSP1N1GPIO24 (Bit 24)                                 */
38952 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO24_Msk (0x1000000UL)            /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
38953 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO23_Pos (23UL)                   /*!< DSP1N1GPIO23 (Bit 23)                                 */
38954 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO23_Msk (0x800000UL)             /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
38955 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO22_Pos (22UL)                   /*!< DSP1N1GPIO22 (Bit 22)                                 */
38956 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO22_Msk (0x400000UL)             /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
38957 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO21_Pos (21UL)                   /*!< DSP1N1GPIO21 (Bit 21)                                 */
38958 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO21_Msk (0x200000UL)             /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
38959 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO20_Pos (20UL)                   /*!< DSP1N1GPIO20 (Bit 20)                                 */
38960 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO20_Msk (0x100000UL)             /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
38961 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO19_Pos (19UL)                   /*!< DSP1N1GPIO19 (Bit 19)                                 */
38962 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO19_Msk (0x80000UL)              /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
38963 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO18_Pos (18UL)                   /*!< DSP1N1GPIO18 (Bit 18)                                 */
38964 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO18_Msk (0x40000UL)              /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
38965 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO17_Pos (17UL)                   /*!< DSP1N1GPIO17 (Bit 17)                                 */
38966 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO17_Msk (0x20000UL)              /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
38967 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO16_Pos (16UL)                   /*!< DSP1N1GPIO16 (Bit 16)                                 */
38968 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO16_Msk (0x10000UL)              /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
38969 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO15_Pos (15UL)                   /*!< DSP1N1GPIO15 (Bit 15)                                 */
38970 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO15_Msk (0x8000UL)               /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
38971 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO14_Pos (14UL)                   /*!< DSP1N1GPIO14 (Bit 14)                                 */
38972 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO14_Msk (0x4000UL)               /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
38973 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO13_Pos (13UL)                   /*!< DSP1N1GPIO13 (Bit 13)                                 */
38974 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO13_Msk (0x2000UL)               /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
38975 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO12_Pos (12UL)                   /*!< DSP1N1GPIO12 (Bit 12)                                 */
38976 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO12_Msk (0x1000UL)               /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
38977 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO11_Pos (11UL)                   /*!< DSP1N1GPIO11 (Bit 11)                                 */
38978 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO11_Msk (0x800UL)                /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
38979 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO10_Pos (10UL)                   /*!< DSP1N1GPIO10 (Bit 10)                                 */
38980 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO10_Msk (0x400UL)                /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
38981 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO9_Pos (9UL)                     /*!< DSP1N1GPIO9 (Bit 9)                                   */
38982 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO9_Msk (0x200UL)                 /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
38983 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO8_Pos (8UL)                     /*!< DSP1N1GPIO8 (Bit 8)                                   */
38984 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO8_Msk (0x100UL)                 /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
38985 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO7_Pos (7UL)                     /*!< DSP1N1GPIO7 (Bit 7)                                   */
38986 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO7_Msk (0x80UL)                  /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
38987 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO6_Pos (6UL)                     /*!< DSP1N1GPIO6 (Bit 6)                                   */
38988 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO6_Msk (0x40UL)                  /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
38989 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO5_Pos (5UL)                     /*!< DSP1N1GPIO5 (Bit 5)                                   */
38990 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO5_Msk (0x20UL)                  /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
38991 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO4_Pos (4UL)                     /*!< DSP1N1GPIO4 (Bit 4)                                   */
38992 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO4_Msk (0x10UL)                  /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
38993 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO3_Pos (3UL)                     /*!< DSP1N1GPIO3 (Bit 3)                                   */
38994 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO3_Msk (0x8UL)                   /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
38995 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO2_Pos (2UL)                     /*!< DSP1N1GPIO2 (Bit 2)                                   */
38996 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO2_Msk (0x4UL)                   /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
38997 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO1_Pos (1UL)                     /*!< DSP1N1GPIO1 (Bit 1)                                   */
38998 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO1_Msk (0x2UL)                   /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
38999 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO0_Pos (0UL)                     /*!< DSP1N1GPIO0 (Bit 0)                                   */
39000 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO0_Msk (0x1UL)                   /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39001 /* ====================================================  DSP1N1INT0STAT  ===================================================== */
39002 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO31_Pos (31UL)                 /*!< DSP1N1GPIO31 (Bit 31)                                 */
39003 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO31_Msk (0x80000000UL)         /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
39004 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO30_Pos (30UL)                 /*!< DSP1N1GPIO30 (Bit 30)                                 */
39005 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO30_Msk (0x40000000UL)         /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
39006 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO29_Pos (29UL)                 /*!< DSP1N1GPIO29 (Bit 29)                                 */
39007 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO29_Msk (0x20000000UL)         /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
39008 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO28_Pos (28UL)                 /*!< DSP1N1GPIO28 (Bit 28)                                 */
39009 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO28_Msk (0x10000000UL)         /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
39010 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO27_Pos (27UL)                 /*!< DSP1N1GPIO27 (Bit 27)                                 */
39011 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO27_Msk (0x8000000UL)          /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
39012 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO26_Pos (26UL)                 /*!< DSP1N1GPIO26 (Bit 26)                                 */
39013 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO26_Msk (0x4000000UL)          /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
39014 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO25_Pos (25UL)                 /*!< DSP1N1GPIO25 (Bit 25)                                 */
39015 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO25_Msk (0x2000000UL)          /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
39016 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO24_Pos (24UL)                 /*!< DSP1N1GPIO24 (Bit 24)                                 */
39017 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO24_Msk (0x1000000UL)          /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
39018 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO23_Pos (23UL)                 /*!< DSP1N1GPIO23 (Bit 23)                                 */
39019 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO23_Msk (0x800000UL)           /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
39020 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO22_Pos (22UL)                 /*!< DSP1N1GPIO22 (Bit 22)                                 */
39021 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO22_Msk (0x400000UL)           /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
39022 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO21_Pos (21UL)                 /*!< DSP1N1GPIO21 (Bit 21)                                 */
39023 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO21_Msk (0x200000UL)           /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
39024 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO20_Pos (20UL)                 /*!< DSP1N1GPIO20 (Bit 20)                                 */
39025 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO20_Msk (0x100000UL)           /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
39026 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO19_Pos (19UL)                 /*!< DSP1N1GPIO19 (Bit 19)                                 */
39027 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO19_Msk (0x80000UL)            /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
39028 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO18_Pos (18UL)                 /*!< DSP1N1GPIO18 (Bit 18)                                 */
39029 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO18_Msk (0x40000UL)            /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
39030 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO17_Pos (17UL)                 /*!< DSP1N1GPIO17 (Bit 17)                                 */
39031 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO17_Msk (0x20000UL)            /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
39032 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO16_Pos (16UL)                 /*!< DSP1N1GPIO16 (Bit 16)                                 */
39033 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO16_Msk (0x10000UL)            /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
39034 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO15_Pos (15UL)                 /*!< DSP1N1GPIO15 (Bit 15)                                 */
39035 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO15_Msk (0x8000UL)             /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
39036 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO14_Pos (14UL)                 /*!< DSP1N1GPIO14 (Bit 14)                                 */
39037 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO14_Msk (0x4000UL)             /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
39038 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO13_Pos (13UL)                 /*!< DSP1N1GPIO13 (Bit 13)                                 */
39039 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO13_Msk (0x2000UL)             /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
39040 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO12_Pos (12UL)                 /*!< DSP1N1GPIO12 (Bit 12)                                 */
39041 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO12_Msk (0x1000UL)             /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
39042 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO11_Pos (11UL)                 /*!< DSP1N1GPIO11 (Bit 11)                                 */
39043 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO11_Msk (0x800UL)              /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
39044 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO10_Pos (10UL)                 /*!< DSP1N1GPIO10 (Bit 10)                                 */
39045 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO10_Msk (0x400UL)              /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
39046 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO9_Pos (9UL)                   /*!< DSP1N1GPIO9 (Bit 9)                                   */
39047 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO9_Msk (0x200UL)               /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
39048 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO8_Pos (8UL)                   /*!< DSP1N1GPIO8 (Bit 8)                                   */
39049 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO8_Msk (0x100UL)               /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
39050 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO7_Pos (7UL)                   /*!< DSP1N1GPIO7 (Bit 7)                                   */
39051 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO7_Msk (0x80UL)                /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
39052 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO6_Pos (6UL)                   /*!< DSP1N1GPIO6 (Bit 6)                                   */
39053 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO6_Msk (0x40UL)                /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
39054 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO5_Pos (5UL)                   /*!< DSP1N1GPIO5 (Bit 5)                                   */
39055 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO5_Msk (0x20UL)                /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
39056 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO4_Pos (4UL)                   /*!< DSP1N1GPIO4 (Bit 4)                                   */
39057 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO4_Msk (0x10UL)                /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
39058 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO3_Pos (3UL)                   /*!< DSP1N1GPIO3 (Bit 3)                                   */
39059 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO3_Msk (0x8UL)                 /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
39060 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO2_Pos (2UL)                   /*!< DSP1N1GPIO2 (Bit 2)                                   */
39061 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO2_Msk (0x4UL)                 /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
39062 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO1_Pos (1UL)                   /*!< DSP1N1GPIO1 (Bit 1)                                   */
39063 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO1_Msk (0x2UL)                 /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
39064 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO0_Pos (0UL)                   /*!< DSP1N1GPIO0 (Bit 0)                                   */
39065 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO0_Msk (0x1UL)                 /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39066 /* =====================================================  DSP1N1INT0CLR  ===================================================== */
39067 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO31_Pos (31UL)                  /*!< DSP1N1GPIO31 (Bit 31)                                 */
39068 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO31_Msk (0x80000000UL)          /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
39069 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO30_Pos (30UL)                  /*!< DSP1N1GPIO30 (Bit 30)                                 */
39070 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO30_Msk (0x40000000UL)          /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
39071 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO29_Pos (29UL)                  /*!< DSP1N1GPIO29 (Bit 29)                                 */
39072 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO29_Msk (0x20000000UL)          /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
39073 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO28_Pos (28UL)                  /*!< DSP1N1GPIO28 (Bit 28)                                 */
39074 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO28_Msk (0x10000000UL)          /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
39075 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO27_Pos (27UL)                  /*!< DSP1N1GPIO27 (Bit 27)                                 */
39076 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO27_Msk (0x8000000UL)           /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
39077 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO26_Pos (26UL)                  /*!< DSP1N1GPIO26 (Bit 26)                                 */
39078 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO26_Msk (0x4000000UL)           /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
39079 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO25_Pos (25UL)                  /*!< DSP1N1GPIO25 (Bit 25)                                 */
39080 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO25_Msk (0x2000000UL)           /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
39081 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO24_Pos (24UL)                  /*!< DSP1N1GPIO24 (Bit 24)                                 */
39082 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO24_Msk (0x1000000UL)           /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
39083 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO23_Pos (23UL)                  /*!< DSP1N1GPIO23 (Bit 23)                                 */
39084 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO23_Msk (0x800000UL)            /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
39085 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO22_Pos (22UL)                  /*!< DSP1N1GPIO22 (Bit 22)                                 */
39086 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO22_Msk (0x400000UL)            /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
39087 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO21_Pos (21UL)                  /*!< DSP1N1GPIO21 (Bit 21)                                 */
39088 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO21_Msk (0x200000UL)            /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
39089 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO20_Pos (20UL)                  /*!< DSP1N1GPIO20 (Bit 20)                                 */
39090 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO20_Msk (0x100000UL)            /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
39091 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO19_Pos (19UL)                  /*!< DSP1N1GPIO19 (Bit 19)                                 */
39092 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO19_Msk (0x80000UL)             /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
39093 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO18_Pos (18UL)                  /*!< DSP1N1GPIO18 (Bit 18)                                 */
39094 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO18_Msk (0x40000UL)             /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
39095 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO17_Pos (17UL)                  /*!< DSP1N1GPIO17 (Bit 17)                                 */
39096 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO17_Msk (0x20000UL)             /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
39097 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO16_Pos (16UL)                  /*!< DSP1N1GPIO16 (Bit 16)                                 */
39098 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO16_Msk (0x10000UL)             /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
39099 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO15_Pos (15UL)                  /*!< DSP1N1GPIO15 (Bit 15)                                 */
39100 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO15_Msk (0x8000UL)              /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
39101 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO14_Pos (14UL)                  /*!< DSP1N1GPIO14 (Bit 14)                                 */
39102 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO14_Msk (0x4000UL)              /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
39103 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO13_Pos (13UL)                  /*!< DSP1N1GPIO13 (Bit 13)                                 */
39104 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO13_Msk (0x2000UL)              /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
39105 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO12_Pos (12UL)                  /*!< DSP1N1GPIO12 (Bit 12)                                 */
39106 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO12_Msk (0x1000UL)              /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
39107 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO11_Pos (11UL)                  /*!< DSP1N1GPIO11 (Bit 11)                                 */
39108 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO11_Msk (0x800UL)               /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
39109 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO10_Pos (10UL)                  /*!< DSP1N1GPIO10 (Bit 10)                                 */
39110 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO10_Msk (0x400UL)               /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
39111 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO9_Pos (9UL)                    /*!< DSP1N1GPIO9 (Bit 9)                                   */
39112 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO9_Msk (0x200UL)                /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
39113 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO8_Pos (8UL)                    /*!< DSP1N1GPIO8 (Bit 8)                                   */
39114 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO8_Msk (0x100UL)                /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
39115 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO7_Pos (7UL)                    /*!< DSP1N1GPIO7 (Bit 7)                                   */
39116 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO7_Msk (0x80UL)                 /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
39117 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO6_Pos (6UL)                    /*!< DSP1N1GPIO6 (Bit 6)                                   */
39118 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO6_Msk (0x40UL)                 /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
39119 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO5_Pos (5UL)                    /*!< DSP1N1GPIO5 (Bit 5)                                   */
39120 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO5_Msk (0x20UL)                 /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
39121 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO4_Pos (4UL)                    /*!< DSP1N1GPIO4 (Bit 4)                                   */
39122 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO4_Msk (0x10UL)                 /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
39123 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO3_Pos (3UL)                    /*!< DSP1N1GPIO3 (Bit 3)                                   */
39124 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO3_Msk (0x8UL)                  /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
39125 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO2_Pos (2UL)                    /*!< DSP1N1GPIO2 (Bit 2)                                   */
39126 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO2_Msk (0x4UL)                  /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
39127 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO1_Pos (1UL)                    /*!< DSP1N1GPIO1 (Bit 1)                                   */
39128 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO1_Msk (0x2UL)                  /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
39129 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO0_Pos (0UL)                    /*!< DSP1N1GPIO0 (Bit 0)                                   */
39130 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO0_Msk (0x1UL)                  /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39131 /* =====================================================  DSP1N1INT0SET  ===================================================== */
39132 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO31_Pos (31UL)                  /*!< DSP1N1GPIO31 (Bit 31)                                 */
39133 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO31_Msk (0x80000000UL)          /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
39134 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO30_Pos (30UL)                  /*!< DSP1N1GPIO30 (Bit 30)                                 */
39135 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO30_Msk (0x40000000UL)          /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
39136 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO29_Pos (29UL)                  /*!< DSP1N1GPIO29 (Bit 29)                                 */
39137 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO29_Msk (0x20000000UL)          /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
39138 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO28_Pos (28UL)                  /*!< DSP1N1GPIO28 (Bit 28)                                 */
39139 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO28_Msk (0x10000000UL)          /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
39140 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO27_Pos (27UL)                  /*!< DSP1N1GPIO27 (Bit 27)                                 */
39141 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO27_Msk (0x8000000UL)           /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
39142 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO26_Pos (26UL)                  /*!< DSP1N1GPIO26 (Bit 26)                                 */
39143 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO26_Msk (0x4000000UL)           /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
39144 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO25_Pos (25UL)                  /*!< DSP1N1GPIO25 (Bit 25)                                 */
39145 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO25_Msk (0x2000000UL)           /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
39146 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO24_Pos (24UL)                  /*!< DSP1N1GPIO24 (Bit 24)                                 */
39147 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO24_Msk (0x1000000UL)           /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
39148 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO23_Pos (23UL)                  /*!< DSP1N1GPIO23 (Bit 23)                                 */
39149 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO23_Msk (0x800000UL)            /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
39150 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO22_Pos (22UL)                  /*!< DSP1N1GPIO22 (Bit 22)                                 */
39151 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO22_Msk (0x400000UL)            /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
39152 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO21_Pos (21UL)                  /*!< DSP1N1GPIO21 (Bit 21)                                 */
39153 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO21_Msk (0x200000UL)            /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
39154 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO20_Pos (20UL)                  /*!< DSP1N1GPIO20 (Bit 20)                                 */
39155 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO20_Msk (0x100000UL)            /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
39156 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO19_Pos (19UL)                  /*!< DSP1N1GPIO19 (Bit 19)                                 */
39157 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO19_Msk (0x80000UL)             /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
39158 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO18_Pos (18UL)                  /*!< DSP1N1GPIO18 (Bit 18)                                 */
39159 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO18_Msk (0x40000UL)             /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
39160 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO17_Pos (17UL)                  /*!< DSP1N1GPIO17 (Bit 17)                                 */
39161 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO17_Msk (0x20000UL)             /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
39162 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO16_Pos (16UL)                  /*!< DSP1N1GPIO16 (Bit 16)                                 */
39163 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO16_Msk (0x10000UL)             /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
39164 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO15_Pos (15UL)                  /*!< DSP1N1GPIO15 (Bit 15)                                 */
39165 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO15_Msk (0x8000UL)              /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
39166 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO14_Pos (14UL)                  /*!< DSP1N1GPIO14 (Bit 14)                                 */
39167 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO14_Msk (0x4000UL)              /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
39168 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO13_Pos (13UL)                  /*!< DSP1N1GPIO13 (Bit 13)                                 */
39169 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO13_Msk (0x2000UL)              /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
39170 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO12_Pos (12UL)                  /*!< DSP1N1GPIO12 (Bit 12)                                 */
39171 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO12_Msk (0x1000UL)              /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
39172 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO11_Pos (11UL)                  /*!< DSP1N1GPIO11 (Bit 11)                                 */
39173 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO11_Msk (0x800UL)               /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
39174 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO10_Pos (10UL)                  /*!< DSP1N1GPIO10 (Bit 10)                                 */
39175 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO10_Msk (0x400UL)               /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
39176 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO9_Pos (9UL)                    /*!< DSP1N1GPIO9 (Bit 9)                                   */
39177 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO9_Msk (0x200UL)                /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
39178 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO8_Pos (8UL)                    /*!< DSP1N1GPIO8 (Bit 8)                                   */
39179 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO8_Msk (0x100UL)                /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
39180 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO7_Pos (7UL)                    /*!< DSP1N1GPIO7 (Bit 7)                                   */
39181 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO7_Msk (0x80UL)                 /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
39182 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO6_Pos (6UL)                    /*!< DSP1N1GPIO6 (Bit 6)                                   */
39183 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO6_Msk (0x40UL)                 /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
39184 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO5_Pos (5UL)                    /*!< DSP1N1GPIO5 (Bit 5)                                   */
39185 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO5_Msk (0x20UL)                 /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
39186 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO4_Pos (4UL)                    /*!< DSP1N1GPIO4 (Bit 4)                                   */
39187 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO4_Msk (0x10UL)                 /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
39188 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO3_Pos (3UL)                    /*!< DSP1N1GPIO3 (Bit 3)                                   */
39189 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO3_Msk (0x8UL)                  /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
39190 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO2_Pos (2UL)                    /*!< DSP1N1GPIO2 (Bit 2)                                   */
39191 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO2_Msk (0x4UL)                  /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
39192 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO1_Pos (1UL)                    /*!< DSP1N1GPIO1 (Bit 1)                                   */
39193 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO1_Msk (0x2UL)                  /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
39194 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO0_Pos (0UL)                    /*!< DSP1N1GPIO0 (Bit 0)                                   */
39195 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO0_Msk (0x1UL)                  /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39196 /* =====================================================  DSP1N1INT1EN  ====================================================== */
39197 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO63_Pos (31UL)                   /*!< DSP1N1GPIO63 (Bit 31)                                 */
39198 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO63_Msk (0x80000000UL)           /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
39199 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO62_Pos (30UL)                   /*!< DSP1N1GPIO62 (Bit 30)                                 */
39200 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO62_Msk (0x40000000UL)           /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
39201 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO61_Pos (29UL)                   /*!< DSP1N1GPIO61 (Bit 29)                                 */
39202 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO61_Msk (0x20000000UL)           /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
39203 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO60_Pos (28UL)                   /*!< DSP1N1GPIO60 (Bit 28)                                 */
39204 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO60_Msk (0x10000000UL)           /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
39205 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO59_Pos (27UL)                   /*!< DSP1N1GPIO59 (Bit 27)                                 */
39206 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO59_Msk (0x8000000UL)            /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
39207 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO58_Pos (26UL)                   /*!< DSP1N1GPIO58 (Bit 26)                                 */
39208 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO58_Msk (0x4000000UL)            /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
39209 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO57_Pos (25UL)                   /*!< DSP1N1GPIO57 (Bit 25)                                 */
39210 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO57_Msk (0x2000000UL)            /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
39211 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO56_Pos (24UL)                   /*!< DSP1N1GPIO56 (Bit 24)                                 */
39212 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO56_Msk (0x1000000UL)            /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
39213 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO55_Pos (23UL)                   /*!< DSP1N1GPIO55 (Bit 23)                                 */
39214 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO55_Msk (0x800000UL)             /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
39215 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO54_Pos (22UL)                   /*!< DSP1N1GPIO54 (Bit 22)                                 */
39216 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO54_Msk (0x400000UL)             /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
39217 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO53_Pos (21UL)                   /*!< DSP1N1GPIO53 (Bit 21)                                 */
39218 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO53_Msk (0x200000UL)             /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
39219 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO52_Pos (20UL)                   /*!< DSP1N1GPIO52 (Bit 20)                                 */
39220 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO52_Msk (0x100000UL)             /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
39221 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO51_Pos (19UL)                   /*!< DSP1N1GPIO51 (Bit 19)                                 */
39222 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO51_Msk (0x80000UL)              /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
39223 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO50_Pos (18UL)                   /*!< DSP1N1GPIO50 (Bit 18)                                 */
39224 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO50_Msk (0x40000UL)              /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
39225 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO49_Pos (17UL)                   /*!< DSP1N1GPIO49 (Bit 17)                                 */
39226 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO49_Msk (0x20000UL)              /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
39227 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO48_Pos (16UL)                   /*!< DSP1N1GPIO48 (Bit 16)                                 */
39228 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO48_Msk (0x10000UL)              /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
39229 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO47_Pos (15UL)                   /*!< DSP1N1GPIO47 (Bit 15)                                 */
39230 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO47_Msk (0x8000UL)               /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
39231 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO46_Pos (14UL)                   /*!< DSP1N1GPIO46 (Bit 14)                                 */
39232 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO46_Msk (0x4000UL)               /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
39233 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO45_Pos (13UL)                   /*!< DSP1N1GPIO45 (Bit 13)                                 */
39234 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO45_Msk (0x2000UL)               /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
39235 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO44_Pos (12UL)                   /*!< DSP1N1GPIO44 (Bit 12)                                 */
39236 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO44_Msk (0x1000UL)               /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
39237 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO43_Pos (11UL)                   /*!< DSP1N1GPIO43 (Bit 11)                                 */
39238 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO43_Msk (0x800UL)                /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
39239 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO42_Pos (10UL)                   /*!< DSP1N1GPIO42 (Bit 10)                                 */
39240 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO42_Msk (0x400UL)                /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
39241 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO41_Pos (9UL)                    /*!< DSP1N1GPIO41 (Bit 9)                                  */
39242 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO41_Msk (0x200UL)                /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
39243 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO40_Pos (8UL)                    /*!< DSP1N1GPIO40 (Bit 8)                                  */
39244 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO40_Msk (0x100UL)                /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
39245 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO39_Pos (7UL)                    /*!< DSP1N1GPIO39 (Bit 7)                                  */
39246 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO39_Msk (0x80UL)                 /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
39247 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO38_Pos (6UL)                    /*!< DSP1N1GPIO38 (Bit 6)                                  */
39248 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO38_Msk (0x40UL)                 /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
39249 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO37_Pos (5UL)                    /*!< DSP1N1GPIO37 (Bit 5)                                  */
39250 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO37_Msk (0x20UL)                 /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
39251 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO36_Pos (4UL)                    /*!< DSP1N1GPIO36 (Bit 4)                                  */
39252 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO36_Msk (0x10UL)                 /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
39253 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO35_Pos (3UL)                    /*!< DSP1N1GPIO35 (Bit 3)                                  */
39254 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO35_Msk (0x8UL)                  /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
39255 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO34_Pos (2UL)                    /*!< DSP1N1GPIO34 (Bit 2)                                  */
39256 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO34_Msk (0x4UL)                  /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
39257 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO33_Pos (1UL)                    /*!< DSP1N1GPIO33 (Bit 1)                                  */
39258 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO33_Msk (0x2UL)                  /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
39259 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO32_Pos (0UL)                    /*!< DSP1N1GPIO32 (Bit 0)                                  */
39260 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO32_Msk (0x1UL)                  /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
39261 /* ====================================================  DSP1N1INT1STAT  ===================================================== */
39262 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO63_Pos (31UL)                 /*!< DSP1N1GPIO63 (Bit 31)                                 */
39263 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO63_Msk (0x80000000UL)         /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
39264 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO62_Pos (30UL)                 /*!< DSP1N1GPIO62 (Bit 30)                                 */
39265 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO62_Msk (0x40000000UL)         /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
39266 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO61_Pos (29UL)                 /*!< DSP1N1GPIO61 (Bit 29)                                 */
39267 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO61_Msk (0x20000000UL)         /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
39268 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO60_Pos (28UL)                 /*!< DSP1N1GPIO60 (Bit 28)                                 */
39269 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO60_Msk (0x10000000UL)         /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
39270 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO59_Pos (27UL)                 /*!< DSP1N1GPIO59 (Bit 27)                                 */
39271 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO59_Msk (0x8000000UL)          /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
39272 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO58_Pos (26UL)                 /*!< DSP1N1GPIO58 (Bit 26)                                 */
39273 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO58_Msk (0x4000000UL)          /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
39274 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO57_Pos (25UL)                 /*!< DSP1N1GPIO57 (Bit 25)                                 */
39275 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO57_Msk (0x2000000UL)          /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
39276 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO56_Pos (24UL)                 /*!< DSP1N1GPIO56 (Bit 24)                                 */
39277 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO56_Msk (0x1000000UL)          /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
39278 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO55_Pos (23UL)                 /*!< DSP1N1GPIO55 (Bit 23)                                 */
39279 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO55_Msk (0x800000UL)           /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
39280 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO54_Pos (22UL)                 /*!< DSP1N1GPIO54 (Bit 22)                                 */
39281 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO54_Msk (0x400000UL)           /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
39282 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO53_Pos (21UL)                 /*!< DSP1N1GPIO53 (Bit 21)                                 */
39283 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO53_Msk (0x200000UL)           /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
39284 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO52_Pos (20UL)                 /*!< DSP1N1GPIO52 (Bit 20)                                 */
39285 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO52_Msk (0x100000UL)           /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
39286 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO51_Pos (19UL)                 /*!< DSP1N1GPIO51 (Bit 19)                                 */
39287 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO51_Msk (0x80000UL)            /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
39288 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO50_Pos (18UL)                 /*!< DSP1N1GPIO50 (Bit 18)                                 */
39289 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO50_Msk (0x40000UL)            /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
39290 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO49_Pos (17UL)                 /*!< DSP1N1GPIO49 (Bit 17)                                 */
39291 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO49_Msk (0x20000UL)            /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
39292 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO48_Pos (16UL)                 /*!< DSP1N1GPIO48 (Bit 16)                                 */
39293 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO48_Msk (0x10000UL)            /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
39294 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO47_Pos (15UL)                 /*!< DSP1N1GPIO47 (Bit 15)                                 */
39295 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO47_Msk (0x8000UL)             /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
39296 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO46_Pos (14UL)                 /*!< DSP1N1GPIO46 (Bit 14)                                 */
39297 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO46_Msk (0x4000UL)             /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
39298 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO45_Pos (13UL)                 /*!< DSP1N1GPIO45 (Bit 13)                                 */
39299 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO45_Msk (0x2000UL)             /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
39300 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO44_Pos (12UL)                 /*!< DSP1N1GPIO44 (Bit 12)                                 */
39301 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO44_Msk (0x1000UL)             /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
39302 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO43_Pos (11UL)                 /*!< DSP1N1GPIO43 (Bit 11)                                 */
39303 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO43_Msk (0x800UL)              /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
39304 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO42_Pos (10UL)                 /*!< DSP1N1GPIO42 (Bit 10)                                 */
39305 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO42_Msk (0x400UL)              /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
39306 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO41_Pos (9UL)                  /*!< DSP1N1GPIO41 (Bit 9)                                  */
39307 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO41_Msk (0x200UL)              /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
39308 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO40_Pos (8UL)                  /*!< DSP1N1GPIO40 (Bit 8)                                  */
39309 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO40_Msk (0x100UL)              /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
39310 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO39_Pos (7UL)                  /*!< DSP1N1GPIO39 (Bit 7)                                  */
39311 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO39_Msk (0x80UL)               /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
39312 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO38_Pos (6UL)                  /*!< DSP1N1GPIO38 (Bit 6)                                  */
39313 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO38_Msk (0x40UL)               /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
39314 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO37_Pos (5UL)                  /*!< DSP1N1GPIO37 (Bit 5)                                  */
39315 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO37_Msk (0x20UL)               /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
39316 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO36_Pos (4UL)                  /*!< DSP1N1GPIO36 (Bit 4)                                  */
39317 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO36_Msk (0x10UL)               /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
39318 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO35_Pos (3UL)                  /*!< DSP1N1GPIO35 (Bit 3)                                  */
39319 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO35_Msk (0x8UL)                /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
39320 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO34_Pos (2UL)                  /*!< DSP1N1GPIO34 (Bit 2)                                  */
39321 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO34_Msk (0x4UL)                /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
39322 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO33_Pos (1UL)                  /*!< DSP1N1GPIO33 (Bit 1)                                  */
39323 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO33_Msk (0x2UL)                /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
39324 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO32_Pos (0UL)                  /*!< DSP1N1GPIO32 (Bit 0)                                  */
39325 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO32_Msk (0x1UL)                /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
39326 /* =====================================================  DSP1N1INT1CLR  ===================================================== */
39327 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO63_Pos (31UL)                  /*!< DSP1N1GPIO63 (Bit 31)                                 */
39328 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO63_Msk (0x80000000UL)          /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
39329 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO62_Pos (30UL)                  /*!< DSP1N1GPIO62 (Bit 30)                                 */
39330 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO62_Msk (0x40000000UL)          /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
39331 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO61_Pos (29UL)                  /*!< DSP1N1GPIO61 (Bit 29)                                 */
39332 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO61_Msk (0x20000000UL)          /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
39333 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO60_Pos (28UL)                  /*!< DSP1N1GPIO60 (Bit 28)                                 */
39334 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO60_Msk (0x10000000UL)          /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
39335 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO59_Pos (27UL)                  /*!< DSP1N1GPIO59 (Bit 27)                                 */
39336 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO59_Msk (0x8000000UL)           /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
39337 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO58_Pos (26UL)                  /*!< DSP1N1GPIO58 (Bit 26)                                 */
39338 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO58_Msk (0x4000000UL)           /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
39339 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO57_Pos (25UL)                  /*!< DSP1N1GPIO57 (Bit 25)                                 */
39340 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO57_Msk (0x2000000UL)           /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
39341 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO56_Pos (24UL)                  /*!< DSP1N1GPIO56 (Bit 24)                                 */
39342 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO56_Msk (0x1000000UL)           /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
39343 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO55_Pos (23UL)                  /*!< DSP1N1GPIO55 (Bit 23)                                 */
39344 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO55_Msk (0x800000UL)            /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
39345 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO54_Pos (22UL)                  /*!< DSP1N1GPIO54 (Bit 22)                                 */
39346 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO54_Msk (0x400000UL)            /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
39347 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO53_Pos (21UL)                  /*!< DSP1N1GPIO53 (Bit 21)                                 */
39348 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO53_Msk (0x200000UL)            /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
39349 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO52_Pos (20UL)                  /*!< DSP1N1GPIO52 (Bit 20)                                 */
39350 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO52_Msk (0x100000UL)            /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
39351 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO51_Pos (19UL)                  /*!< DSP1N1GPIO51 (Bit 19)                                 */
39352 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO51_Msk (0x80000UL)             /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
39353 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO50_Pos (18UL)                  /*!< DSP1N1GPIO50 (Bit 18)                                 */
39354 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO50_Msk (0x40000UL)             /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
39355 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO49_Pos (17UL)                  /*!< DSP1N1GPIO49 (Bit 17)                                 */
39356 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO49_Msk (0x20000UL)             /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
39357 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO48_Pos (16UL)                  /*!< DSP1N1GPIO48 (Bit 16)                                 */
39358 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO48_Msk (0x10000UL)             /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
39359 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO47_Pos (15UL)                  /*!< DSP1N1GPIO47 (Bit 15)                                 */
39360 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO47_Msk (0x8000UL)              /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
39361 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO46_Pos (14UL)                  /*!< DSP1N1GPIO46 (Bit 14)                                 */
39362 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO46_Msk (0x4000UL)              /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
39363 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO45_Pos (13UL)                  /*!< DSP1N1GPIO45 (Bit 13)                                 */
39364 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO45_Msk (0x2000UL)              /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
39365 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO44_Pos (12UL)                  /*!< DSP1N1GPIO44 (Bit 12)                                 */
39366 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO44_Msk (0x1000UL)              /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
39367 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO43_Pos (11UL)                  /*!< DSP1N1GPIO43 (Bit 11)                                 */
39368 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO43_Msk (0x800UL)               /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
39369 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO42_Pos (10UL)                  /*!< DSP1N1GPIO42 (Bit 10)                                 */
39370 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO42_Msk (0x400UL)               /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
39371 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO41_Pos (9UL)                   /*!< DSP1N1GPIO41 (Bit 9)                                  */
39372 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO41_Msk (0x200UL)               /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
39373 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO40_Pos (8UL)                   /*!< DSP1N1GPIO40 (Bit 8)                                  */
39374 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO40_Msk (0x100UL)               /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
39375 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO39_Pos (7UL)                   /*!< DSP1N1GPIO39 (Bit 7)                                  */
39376 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO39_Msk (0x80UL)                /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
39377 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO38_Pos (6UL)                   /*!< DSP1N1GPIO38 (Bit 6)                                  */
39378 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO38_Msk (0x40UL)                /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
39379 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO37_Pos (5UL)                   /*!< DSP1N1GPIO37 (Bit 5)                                  */
39380 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO37_Msk (0x20UL)                /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
39381 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO36_Pos (4UL)                   /*!< DSP1N1GPIO36 (Bit 4)                                  */
39382 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO36_Msk (0x10UL)                /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
39383 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO35_Pos (3UL)                   /*!< DSP1N1GPIO35 (Bit 3)                                  */
39384 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO35_Msk (0x8UL)                 /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
39385 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO34_Pos (2UL)                   /*!< DSP1N1GPIO34 (Bit 2)                                  */
39386 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO34_Msk (0x4UL)                 /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
39387 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO33_Pos (1UL)                   /*!< DSP1N1GPIO33 (Bit 1)                                  */
39388 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO33_Msk (0x2UL)                 /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
39389 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO32_Pos (0UL)                   /*!< DSP1N1GPIO32 (Bit 0)                                  */
39390 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO32_Msk (0x1UL)                 /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
39391 /* =====================================================  DSP1N1INT1SET  ===================================================== */
39392 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO63_Pos (31UL)                  /*!< DSP1N1GPIO63 (Bit 31)                                 */
39393 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO63_Msk (0x80000000UL)          /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
39394 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO62_Pos (30UL)                  /*!< DSP1N1GPIO62 (Bit 30)                                 */
39395 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO62_Msk (0x40000000UL)          /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
39396 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO61_Pos (29UL)                  /*!< DSP1N1GPIO61 (Bit 29)                                 */
39397 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO61_Msk (0x20000000UL)          /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
39398 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO60_Pos (28UL)                  /*!< DSP1N1GPIO60 (Bit 28)                                 */
39399 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO60_Msk (0x10000000UL)          /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
39400 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO59_Pos (27UL)                  /*!< DSP1N1GPIO59 (Bit 27)                                 */
39401 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO59_Msk (0x8000000UL)           /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
39402 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO58_Pos (26UL)                  /*!< DSP1N1GPIO58 (Bit 26)                                 */
39403 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO58_Msk (0x4000000UL)           /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
39404 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO57_Pos (25UL)                  /*!< DSP1N1GPIO57 (Bit 25)                                 */
39405 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO57_Msk (0x2000000UL)           /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
39406 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO56_Pos (24UL)                  /*!< DSP1N1GPIO56 (Bit 24)                                 */
39407 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO56_Msk (0x1000000UL)           /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
39408 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO55_Pos (23UL)                  /*!< DSP1N1GPIO55 (Bit 23)                                 */
39409 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO55_Msk (0x800000UL)            /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
39410 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO54_Pos (22UL)                  /*!< DSP1N1GPIO54 (Bit 22)                                 */
39411 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO54_Msk (0x400000UL)            /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
39412 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO53_Pos (21UL)                  /*!< DSP1N1GPIO53 (Bit 21)                                 */
39413 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO53_Msk (0x200000UL)            /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
39414 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO52_Pos (20UL)                  /*!< DSP1N1GPIO52 (Bit 20)                                 */
39415 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO52_Msk (0x100000UL)            /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
39416 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO51_Pos (19UL)                  /*!< DSP1N1GPIO51 (Bit 19)                                 */
39417 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO51_Msk (0x80000UL)             /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
39418 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO50_Pos (18UL)                  /*!< DSP1N1GPIO50 (Bit 18)                                 */
39419 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO50_Msk (0x40000UL)             /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
39420 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO49_Pos (17UL)                  /*!< DSP1N1GPIO49 (Bit 17)                                 */
39421 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO49_Msk (0x20000UL)             /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
39422 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO48_Pos (16UL)                  /*!< DSP1N1GPIO48 (Bit 16)                                 */
39423 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO48_Msk (0x10000UL)             /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
39424 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO47_Pos (15UL)                  /*!< DSP1N1GPIO47 (Bit 15)                                 */
39425 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO47_Msk (0x8000UL)              /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
39426 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO46_Pos (14UL)                  /*!< DSP1N1GPIO46 (Bit 14)                                 */
39427 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO46_Msk (0x4000UL)              /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
39428 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO45_Pos (13UL)                  /*!< DSP1N1GPIO45 (Bit 13)                                 */
39429 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO45_Msk (0x2000UL)              /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
39430 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO44_Pos (12UL)                  /*!< DSP1N1GPIO44 (Bit 12)                                 */
39431 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO44_Msk (0x1000UL)              /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
39432 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO43_Pos (11UL)                  /*!< DSP1N1GPIO43 (Bit 11)                                 */
39433 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO43_Msk (0x800UL)               /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
39434 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO42_Pos (10UL)                  /*!< DSP1N1GPIO42 (Bit 10)                                 */
39435 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO42_Msk (0x400UL)               /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
39436 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO41_Pos (9UL)                   /*!< DSP1N1GPIO41 (Bit 9)                                  */
39437 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO41_Msk (0x200UL)               /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
39438 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO40_Pos (8UL)                   /*!< DSP1N1GPIO40 (Bit 8)                                  */
39439 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO40_Msk (0x100UL)               /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
39440 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO39_Pos (7UL)                   /*!< DSP1N1GPIO39 (Bit 7)                                  */
39441 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO39_Msk (0x80UL)                /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
39442 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO38_Pos (6UL)                   /*!< DSP1N1GPIO38 (Bit 6)                                  */
39443 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO38_Msk (0x40UL)                /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
39444 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO37_Pos (5UL)                   /*!< DSP1N1GPIO37 (Bit 5)                                  */
39445 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO37_Msk (0x20UL)                /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
39446 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO36_Pos (4UL)                   /*!< DSP1N1GPIO36 (Bit 4)                                  */
39447 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO36_Msk (0x10UL)                /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
39448 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO35_Pos (3UL)                   /*!< DSP1N1GPIO35 (Bit 3)                                  */
39449 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO35_Msk (0x8UL)                 /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
39450 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO34_Pos (2UL)                   /*!< DSP1N1GPIO34 (Bit 2)                                  */
39451 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO34_Msk (0x4UL)                 /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
39452 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO33_Pos (1UL)                   /*!< DSP1N1GPIO33 (Bit 1)                                  */
39453 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO33_Msk (0x2UL)                 /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
39454 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO32_Pos (0UL)                   /*!< DSP1N1GPIO32 (Bit 0)                                  */
39455 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO32_Msk (0x1UL)                 /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
39456 /* =====================================================  DSP1N1INT2EN  ====================================================== */
39457 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO95_Pos (31UL)                   /*!< DSP1N1GPIO95 (Bit 31)                                 */
39458 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO95_Msk (0x80000000UL)           /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
39459 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO94_Pos (30UL)                   /*!< DSP1N1GPIO94 (Bit 30)                                 */
39460 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO94_Msk (0x40000000UL)           /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
39461 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO93_Pos (29UL)                   /*!< DSP1N1GPIO93 (Bit 29)                                 */
39462 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO93_Msk (0x20000000UL)           /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
39463 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO92_Pos (28UL)                   /*!< DSP1N1GPIO92 (Bit 28)                                 */
39464 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO92_Msk (0x10000000UL)           /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
39465 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO91_Pos (27UL)                   /*!< DSP1N1GPIO91 (Bit 27)                                 */
39466 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO91_Msk (0x8000000UL)            /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
39467 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO90_Pos (26UL)                   /*!< DSP1N1GPIO90 (Bit 26)                                 */
39468 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO90_Msk (0x4000000UL)            /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
39469 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO89_Pos (25UL)                   /*!< DSP1N1GPIO89 (Bit 25)                                 */
39470 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO89_Msk (0x2000000UL)            /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
39471 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO88_Pos (24UL)                   /*!< DSP1N1GPIO88 (Bit 24)                                 */
39472 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO88_Msk (0x1000000UL)            /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
39473 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO87_Pos (23UL)                   /*!< DSP1N1GPIO87 (Bit 23)                                 */
39474 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO87_Msk (0x800000UL)             /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
39475 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO86_Pos (22UL)                   /*!< DSP1N1GPIO86 (Bit 22)                                 */
39476 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO86_Msk (0x400000UL)             /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
39477 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO85_Pos (21UL)                   /*!< DSP1N1GPIO85 (Bit 21)                                 */
39478 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO85_Msk (0x200000UL)             /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
39479 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO84_Pos (20UL)                   /*!< DSP1N1GPIO84 (Bit 20)                                 */
39480 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO84_Msk (0x100000UL)             /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
39481 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO83_Pos (19UL)                   /*!< DSP1N1GPIO83 (Bit 19)                                 */
39482 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO83_Msk (0x80000UL)              /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
39483 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO82_Pos (18UL)                   /*!< DSP1N1GPIO82 (Bit 18)                                 */
39484 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO82_Msk (0x40000UL)              /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
39485 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO81_Pos (17UL)                   /*!< DSP1N1GPIO81 (Bit 17)                                 */
39486 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO81_Msk (0x20000UL)              /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
39487 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO80_Pos (16UL)                   /*!< DSP1N1GPIO80 (Bit 16)                                 */
39488 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO80_Msk (0x10000UL)              /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
39489 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO79_Pos (15UL)                   /*!< DSP1N1GPIO79 (Bit 15)                                 */
39490 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO79_Msk (0x8000UL)               /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
39491 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO78_Pos (14UL)                   /*!< DSP1N1GPIO78 (Bit 14)                                 */
39492 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO78_Msk (0x4000UL)               /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
39493 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO77_Pos (13UL)                   /*!< DSP1N1GPIO77 (Bit 13)                                 */
39494 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO77_Msk (0x2000UL)               /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
39495 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO76_Pos (12UL)                   /*!< DSP1N1GPIO76 (Bit 12)                                 */
39496 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO76_Msk (0x1000UL)               /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
39497 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO75_Pos (11UL)                   /*!< DSP1N1GPIO75 (Bit 11)                                 */
39498 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO75_Msk (0x800UL)                /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
39499 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO74_Pos (10UL)                   /*!< DSP1N1GPIO74 (Bit 10)                                 */
39500 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO74_Msk (0x400UL)                /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
39501 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO73_Pos (9UL)                    /*!< DSP1N1GPIO73 (Bit 9)                                  */
39502 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO73_Msk (0x200UL)                /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
39503 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO72_Pos (8UL)                    /*!< DSP1N1GPIO72 (Bit 8)                                  */
39504 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO72_Msk (0x100UL)                /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
39505 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO71_Pos (7UL)                    /*!< DSP1N1GPIO71 (Bit 7)                                  */
39506 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO71_Msk (0x80UL)                 /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
39507 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO70_Pos (6UL)                    /*!< DSP1N1GPIO70 (Bit 6)                                  */
39508 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO70_Msk (0x40UL)                 /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
39509 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO69_Pos (5UL)                    /*!< DSP1N1GPIO69 (Bit 5)                                  */
39510 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO69_Msk (0x20UL)                 /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
39511 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO68_Pos (4UL)                    /*!< DSP1N1GPIO68 (Bit 4)                                  */
39512 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO68_Msk (0x10UL)                 /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
39513 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO67_Pos (3UL)                    /*!< DSP1N1GPIO67 (Bit 3)                                  */
39514 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO67_Msk (0x8UL)                  /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
39515 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO66_Pos (2UL)                    /*!< DSP1N1GPIO66 (Bit 2)                                  */
39516 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO66_Msk (0x4UL)                  /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
39517 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO65_Pos (1UL)                    /*!< DSP1N1GPIO65 (Bit 1)                                  */
39518 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO65_Msk (0x2UL)                  /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
39519 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO64_Pos (0UL)                    /*!< DSP1N1GPIO64 (Bit 0)                                  */
39520 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO64_Msk (0x1UL)                  /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
39521 /* ====================================================  DSP1N1INT2STAT  ===================================================== */
39522 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO95_Pos (31UL)                 /*!< DSP1N1GPIO95 (Bit 31)                                 */
39523 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO95_Msk (0x80000000UL)         /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
39524 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO94_Pos (30UL)                 /*!< DSP1N1GPIO94 (Bit 30)                                 */
39525 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO94_Msk (0x40000000UL)         /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
39526 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO93_Pos (29UL)                 /*!< DSP1N1GPIO93 (Bit 29)                                 */
39527 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO93_Msk (0x20000000UL)         /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
39528 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO92_Pos (28UL)                 /*!< DSP1N1GPIO92 (Bit 28)                                 */
39529 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO92_Msk (0x10000000UL)         /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
39530 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO91_Pos (27UL)                 /*!< DSP1N1GPIO91 (Bit 27)                                 */
39531 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO91_Msk (0x8000000UL)          /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
39532 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO90_Pos (26UL)                 /*!< DSP1N1GPIO90 (Bit 26)                                 */
39533 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO90_Msk (0x4000000UL)          /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
39534 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO89_Pos (25UL)                 /*!< DSP1N1GPIO89 (Bit 25)                                 */
39535 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO89_Msk (0x2000000UL)          /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
39536 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO88_Pos (24UL)                 /*!< DSP1N1GPIO88 (Bit 24)                                 */
39537 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO88_Msk (0x1000000UL)          /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
39538 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO87_Pos (23UL)                 /*!< DSP1N1GPIO87 (Bit 23)                                 */
39539 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO87_Msk (0x800000UL)           /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
39540 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO86_Pos (22UL)                 /*!< DSP1N1GPIO86 (Bit 22)                                 */
39541 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO86_Msk (0x400000UL)           /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
39542 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO85_Pos (21UL)                 /*!< DSP1N1GPIO85 (Bit 21)                                 */
39543 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO85_Msk (0x200000UL)           /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
39544 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO84_Pos (20UL)                 /*!< DSP1N1GPIO84 (Bit 20)                                 */
39545 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO84_Msk (0x100000UL)           /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
39546 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO83_Pos (19UL)                 /*!< DSP1N1GPIO83 (Bit 19)                                 */
39547 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO83_Msk (0x80000UL)            /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
39548 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO82_Pos (18UL)                 /*!< DSP1N1GPIO82 (Bit 18)                                 */
39549 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO82_Msk (0x40000UL)            /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
39550 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO81_Pos (17UL)                 /*!< DSP1N1GPIO81 (Bit 17)                                 */
39551 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO81_Msk (0x20000UL)            /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
39552 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO80_Pos (16UL)                 /*!< DSP1N1GPIO80 (Bit 16)                                 */
39553 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO80_Msk (0x10000UL)            /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
39554 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO79_Pos (15UL)                 /*!< DSP1N1GPIO79 (Bit 15)                                 */
39555 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO79_Msk (0x8000UL)             /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
39556 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO78_Pos (14UL)                 /*!< DSP1N1GPIO78 (Bit 14)                                 */
39557 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO78_Msk (0x4000UL)             /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
39558 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO77_Pos (13UL)                 /*!< DSP1N1GPIO77 (Bit 13)                                 */
39559 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO77_Msk (0x2000UL)             /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
39560 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO76_Pos (12UL)                 /*!< DSP1N1GPIO76 (Bit 12)                                 */
39561 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO76_Msk (0x1000UL)             /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
39562 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO75_Pos (11UL)                 /*!< DSP1N1GPIO75 (Bit 11)                                 */
39563 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO75_Msk (0x800UL)              /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
39564 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO74_Pos (10UL)                 /*!< DSP1N1GPIO74 (Bit 10)                                 */
39565 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO74_Msk (0x400UL)              /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
39566 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO73_Pos (9UL)                  /*!< DSP1N1GPIO73 (Bit 9)                                  */
39567 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO73_Msk (0x200UL)              /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
39568 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO72_Pos (8UL)                  /*!< DSP1N1GPIO72 (Bit 8)                                  */
39569 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO72_Msk (0x100UL)              /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
39570 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO71_Pos (7UL)                  /*!< DSP1N1GPIO71 (Bit 7)                                  */
39571 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO71_Msk (0x80UL)               /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
39572 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO70_Pos (6UL)                  /*!< DSP1N1GPIO70 (Bit 6)                                  */
39573 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO70_Msk (0x40UL)               /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
39574 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO69_Pos (5UL)                  /*!< DSP1N1GPIO69 (Bit 5)                                  */
39575 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO69_Msk (0x20UL)               /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
39576 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO68_Pos (4UL)                  /*!< DSP1N1GPIO68 (Bit 4)                                  */
39577 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO68_Msk (0x10UL)               /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
39578 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO67_Pos (3UL)                  /*!< DSP1N1GPIO67 (Bit 3)                                  */
39579 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO67_Msk (0x8UL)                /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
39580 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO66_Pos (2UL)                  /*!< DSP1N1GPIO66 (Bit 2)                                  */
39581 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO66_Msk (0x4UL)                /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
39582 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO65_Pos (1UL)                  /*!< DSP1N1GPIO65 (Bit 1)                                  */
39583 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO65_Msk (0x2UL)                /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
39584 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO64_Pos (0UL)                  /*!< DSP1N1GPIO64 (Bit 0)                                  */
39585 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO64_Msk (0x1UL)                /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
39586 /* =====================================================  DSP1N1INT2CLR  ===================================================== */
39587 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO95_Pos (31UL)                  /*!< DSP1N1GPIO95 (Bit 31)                                 */
39588 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO95_Msk (0x80000000UL)          /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
39589 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO94_Pos (30UL)                  /*!< DSP1N1GPIO94 (Bit 30)                                 */
39590 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO94_Msk (0x40000000UL)          /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
39591 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO93_Pos (29UL)                  /*!< DSP1N1GPIO93 (Bit 29)                                 */
39592 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO93_Msk (0x20000000UL)          /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
39593 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO92_Pos (28UL)                  /*!< DSP1N1GPIO92 (Bit 28)                                 */
39594 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO92_Msk (0x10000000UL)          /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
39595 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO91_Pos (27UL)                  /*!< DSP1N1GPIO91 (Bit 27)                                 */
39596 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO91_Msk (0x8000000UL)           /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
39597 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO90_Pos (26UL)                  /*!< DSP1N1GPIO90 (Bit 26)                                 */
39598 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO90_Msk (0x4000000UL)           /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
39599 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO89_Pos (25UL)                  /*!< DSP1N1GPIO89 (Bit 25)                                 */
39600 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO89_Msk (0x2000000UL)           /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
39601 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO88_Pos (24UL)                  /*!< DSP1N1GPIO88 (Bit 24)                                 */
39602 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO88_Msk (0x1000000UL)           /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
39603 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO87_Pos (23UL)                  /*!< DSP1N1GPIO87 (Bit 23)                                 */
39604 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO87_Msk (0x800000UL)            /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
39605 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO86_Pos (22UL)                  /*!< DSP1N1GPIO86 (Bit 22)                                 */
39606 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO86_Msk (0x400000UL)            /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
39607 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO85_Pos (21UL)                  /*!< DSP1N1GPIO85 (Bit 21)                                 */
39608 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO85_Msk (0x200000UL)            /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
39609 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO84_Pos (20UL)                  /*!< DSP1N1GPIO84 (Bit 20)                                 */
39610 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO84_Msk (0x100000UL)            /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
39611 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO83_Pos (19UL)                  /*!< DSP1N1GPIO83 (Bit 19)                                 */
39612 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO83_Msk (0x80000UL)             /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
39613 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO82_Pos (18UL)                  /*!< DSP1N1GPIO82 (Bit 18)                                 */
39614 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO82_Msk (0x40000UL)             /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
39615 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO81_Pos (17UL)                  /*!< DSP1N1GPIO81 (Bit 17)                                 */
39616 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO81_Msk (0x20000UL)             /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
39617 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO80_Pos (16UL)                  /*!< DSP1N1GPIO80 (Bit 16)                                 */
39618 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO80_Msk (0x10000UL)             /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
39619 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO79_Pos (15UL)                  /*!< DSP1N1GPIO79 (Bit 15)                                 */
39620 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO79_Msk (0x8000UL)              /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
39621 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO78_Pos (14UL)                  /*!< DSP1N1GPIO78 (Bit 14)                                 */
39622 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO78_Msk (0x4000UL)              /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
39623 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO77_Pos (13UL)                  /*!< DSP1N1GPIO77 (Bit 13)                                 */
39624 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO77_Msk (0x2000UL)              /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
39625 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO76_Pos (12UL)                  /*!< DSP1N1GPIO76 (Bit 12)                                 */
39626 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO76_Msk (0x1000UL)              /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
39627 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO75_Pos (11UL)                  /*!< DSP1N1GPIO75 (Bit 11)                                 */
39628 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO75_Msk (0x800UL)               /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
39629 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO74_Pos (10UL)                  /*!< DSP1N1GPIO74 (Bit 10)                                 */
39630 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO74_Msk (0x400UL)               /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
39631 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO73_Pos (9UL)                   /*!< DSP1N1GPIO73 (Bit 9)                                  */
39632 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO73_Msk (0x200UL)               /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
39633 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO72_Pos (8UL)                   /*!< DSP1N1GPIO72 (Bit 8)                                  */
39634 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO72_Msk (0x100UL)               /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
39635 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO71_Pos (7UL)                   /*!< DSP1N1GPIO71 (Bit 7)                                  */
39636 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO71_Msk (0x80UL)                /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
39637 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO70_Pos (6UL)                   /*!< DSP1N1GPIO70 (Bit 6)                                  */
39638 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO70_Msk (0x40UL)                /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
39639 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO69_Pos (5UL)                   /*!< DSP1N1GPIO69 (Bit 5)                                  */
39640 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO69_Msk (0x20UL)                /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
39641 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO68_Pos (4UL)                   /*!< DSP1N1GPIO68 (Bit 4)                                  */
39642 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO68_Msk (0x10UL)                /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
39643 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO67_Pos (3UL)                   /*!< DSP1N1GPIO67 (Bit 3)                                  */
39644 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO67_Msk (0x8UL)                 /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
39645 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO66_Pos (2UL)                   /*!< DSP1N1GPIO66 (Bit 2)                                  */
39646 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO66_Msk (0x4UL)                 /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
39647 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO65_Pos (1UL)                   /*!< DSP1N1GPIO65 (Bit 1)                                  */
39648 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO65_Msk (0x2UL)                 /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
39649 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO64_Pos (0UL)                   /*!< DSP1N1GPIO64 (Bit 0)                                  */
39650 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO64_Msk (0x1UL)                 /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
39651 /* =====================================================  DSP1N1INT2SET  ===================================================== */
39652 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO95_Pos (31UL)                  /*!< DSP1N1GPIO95 (Bit 31)                                 */
39653 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO95_Msk (0x80000000UL)          /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
39654 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO94_Pos (30UL)                  /*!< DSP1N1GPIO94 (Bit 30)                                 */
39655 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO94_Msk (0x40000000UL)          /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
39656 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO93_Pos (29UL)                  /*!< DSP1N1GPIO93 (Bit 29)                                 */
39657 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO93_Msk (0x20000000UL)          /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
39658 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO92_Pos (28UL)                  /*!< DSP1N1GPIO92 (Bit 28)                                 */
39659 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO92_Msk (0x10000000UL)          /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
39660 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO91_Pos (27UL)                  /*!< DSP1N1GPIO91 (Bit 27)                                 */
39661 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO91_Msk (0x8000000UL)           /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
39662 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO90_Pos (26UL)                  /*!< DSP1N1GPIO90 (Bit 26)                                 */
39663 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO90_Msk (0x4000000UL)           /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
39664 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO89_Pos (25UL)                  /*!< DSP1N1GPIO89 (Bit 25)                                 */
39665 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO89_Msk (0x2000000UL)           /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
39666 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO88_Pos (24UL)                  /*!< DSP1N1GPIO88 (Bit 24)                                 */
39667 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO88_Msk (0x1000000UL)           /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
39668 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO87_Pos (23UL)                  /*!< DSP1N1GPIO87 (Bit 23)                                 */
39669 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO87_Msk (0x800000UL)            /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
39670 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO86_Pos (22UL)                  /*!< DSP1N1GPIO86 (Bit 22)                                 */
39671 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO86_Msk (0x400000UL)            /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
39672 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO85_Pos (21UL)                  /*!< DSP1N1GPIO85 (Bit 21)                                 */
39673 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO85_Msk (0x200000UL)            /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
39674 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO84_Pos (20UL)                  /*!< DSP1N1GPIO84 (Bit 20)                                 */
39675 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO84_Msk (0x100000UL)            /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
39676 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO83_Pos (19UL)                  /*!< DSP1N1GPIO83 (Bit 19)                                 */
39677 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO83_Msk (0x80000UL)             /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
39678 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO82_Pos (18UL)                  /*!< DSP1N1GPIO82 (Bit 18)                                 */
39679 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO82_Msk (0x40000UL)             /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
39680 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO81_Pos (17UL)                  /*!< DSP1N1GPIO81 (Bit 17)                                 */
39681 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO81_Msk (0x20000UL)             /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
39682 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO80_Pos (16UL)                  /*!< DSP1N1GPIO80 (Bit 16)                                 */
39683 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO80_Msk (0x10000UL)             /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
39684 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO79_Pos (15UL)                  /*!< DSP1N1GPIO79 (Bit 15)                                 */
39685 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO79_Msk (0x8000UL)              /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
39686 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO78_Pos (14UL)                  /*!< DSP1N1GPIO78 (Bit 14)                                 */
39687 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO78_Msk (0x4000UL)              /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
39688 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO77_Pos (13UL)                  /*!< DSP1N1GPIO77 (Bit 13)                                 */
39689 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO77_Msk (0x2000UL)              /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
39690 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO76_Pos (12UL)                  /*!< DSP1N1GPIO76 (Bit 12)                                 */
39691 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO76_Msk (0x1000UL)              /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
39692 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO75_Pos (11UL)                  /*!< DSP1N1GPIO75 (Bit 11)                                 */
39693 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO75_Msk (0x800UL)               /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
39694 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO74_Pos (10UL)                  /*!< DSP1N1GPIO74 (Bit 10)                                 */
39695 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO74_Msk (0x400UL)               /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
39696 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO73_Pos (9UL)                   /*!< DSP1N1GPIO73 (Bit 9)                                  */
39697 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO73_Msk (0x200UL)               /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
39698 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO72_Pos (8UL)                   /*!< DSP1N1GPIO72 (Bit 8)                                  */
39699 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO72_Msk (0x100UL)               /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
39700 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO71_Pos (7UL)                   /*!< DSP1N1GPIO71 (Bit 7)                                  */
39701 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO71_Msk (0x80UL)                /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
39702 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO70_Pos (6UL)                   /*!< DSP1N1GPIO70 (Bit 6)                                  */
39703 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO70_Msk (0x40UL)                /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
39704 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO69_Pos (5UL)                   /*!< DSP1N1GPIO69 (Bit 5)                                  */
39705 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO69_Msk (0x20UL)                /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
39706 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO68_Pos (4UL)                   /*!< DSP1N1GPIO68 (Bit 4)                                  */
39707 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO68_Msk (0x10UL)                /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
39708 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO67_Pos (3UL)                   /*!< DSP1N1GPIO67 (Bit 3)                                  */
39709 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO67_Msk (0x8UL)                 /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
39710 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO66_Pos (2UL)                   /*!< DSP1N1GPIO66 (Bit 2)                                  */
39711 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO66_Msk (0x4UL)                 /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
39712 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO65_Pos (1UL)                   /*!< DSP1N1GPIO65 (Bit 1)                                  */
39713 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO65_Msk (0x2UL)                 /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
39714 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO64_Pos (0UL)                   /*!< DSP1N1GPIO64 (Bit 0)                                  */
39715 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO64_Msk (0x1UL)                 /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
39716 /* =====================================================  DSP1N1INT3EN  ====================================================== */
39717 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO127_Pos (31UL)                  /*!< DSP1N1GPIO127 (Bit 31)                                */
39718 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO127_Msk (0x80000000UL)          /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
39719 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO126_Pos (30UL)                  /*!< DSP1N1GPIO126 (Bit 30)                                */
39720 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO126_Msk (0x40000000UL)          /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
39721 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO125_Pos (29UL)                  /*!< DSP1N1GPIO125 (Bit 29)                                */
39722 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO125_Msk (0x20000000UL)          /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
39723 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO124_Pos (28UL)                  /*!< DSP1N1GPIO124 (Bit 28)                                */
39724 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO124_Msk (0x10000000UL)          /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
39725 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO123_Pos (27UL)                  /*!< DSP1N1GPIO123 (Bit 27)                                */
39726 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO123_Msk (0x8000000UL)           /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
39727 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO122_Pos (26UL)                  /*!< DSP1N1GPIO122 (Bit 26)                                */
39728 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO122_Msk (0x4000000UL)           /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
39729 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO121_Pos (25UL)                  /*!< DSP1N1GPIO121 (Bit 25)                                */
39730 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO121_Msk (0x2000000UL)           /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
39731 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO120_Pos (24UL)                  /*!< DSP1N1GPIO120 (Bit 24)                                */
39732 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO120_Msk (0x1000000UL)           /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
39733 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO119_Pos (23UL)                  /*!< DSP1N1GPIO119 (Bit 23)                                */
39734 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO119_Msk (0x800000UL)            /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
39735 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO118_Pos (22UL)                  /*!< DSP1N1GPIO118 (Bit 22)                                */
39736 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO118_Msk (0x400000UL)            /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
39737 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO117_Pos (21UL)                  /*!< DSP1N1GPIO117 (Bit 21)                                */
39738 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO117_Msk (0x200000UL)            /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
39739 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO116_Pos (20UL)                  /*!< DSP1N1GPIO116 (Bit 20)                                */
39740 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO116_Msk (0x100000UL)            /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
39741 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO115_Pos (19UL)                  /*!< DSP1N1GPIO115 (Bit 19)                                */
39742 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO115_Msk (0x80000UL)             /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
39743 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO114_Pos (18UL)                  /*!< DSP1N1GPIO114 (Bit 18)                                */
39744 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO114_Msk (0x40000UL)             /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
39745 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO113_Pos (17UL)                  /*!< DSP1N1GPIO113 (Bit 17)                                */
39746 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO113_Msk (0x20000UL)             /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
39747 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO112_Pos (16UL)                  /*!< DSP1N1GPIO112 (Bit 16)                                */
39748 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO112_Msk (0x10000UL)             /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
39749 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO111_Pos (15UL)                  /*!< DSP1N1GPIO111 (Bit 15)                                */
39750 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO111_Msk (0x8000UL)              /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
39751 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO110_Pos (14UL)                  /*!< DSP1N1GPIO110 (Bit 14)                                */
39752 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO110_Msk (0x4000UL)              /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
39753 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO109_Pos (13UL)                  /*!< DSP1N1GPIO109 (Bit 13)                                */
39754 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO109_Msk (0x2000UL)              /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
39755 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO108_Pos (12UL)                  /*!< DSP1N1GPIO108 (Bit 12)                                */
39756 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO108_Msk (0x1000UL)              /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
39757 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO107_Pos (11UL)                  /*!< DSP1N1GPIO107 (Bit 11)                                */
39758 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO107_Msk (0x800UL)               /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
39759 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO106_Pos (10UL)                  /*!< DSP1N1GPIO106 (Bit 10)                                */
39760 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO106_Msk (0x400UL)               /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
39761 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO105_Pos (9UL)                   /*!< DSP1N1GPIO105 (Bit 9)                                 */
39762 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO105_Msk (0x200UL)               /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
39763 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO104_Pos (8UL)                   /*!< DSP1N1GPIO104 (Bit 8)                                 */
39764 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO104_Msk (0x100UL)               /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
39765 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO103_Pos (7UL)                   /*!< DSP1N1GPIO103 (Bit 7)                                 */
39766 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO103_Msk (0x80UL)                /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
39767 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO102_Pos (6UL)                   /*!< DSP1N1GPIO102 (Bit 6)                                 */
39768 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO102_Msk (0x40UL)                /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
39769 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO101_Pos (5UL)                   /*!< DSP1N1GPIO101 (Bit 5)                                 */
39770 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO101_Msk (0x20UL)                /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
39771 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO100_Pos (4UL)                   /*!< DSP1N1GPIO100 (Bit 4)                                 */
39772 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO100_Msk (0x10UL)                /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
39773 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO99_Pos (3UL)                    /*!< DSP1N1GPIO99 (Bit 3)                                  */
39774 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO99_Msk (0x8UL)                  /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
39775 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO98_Pos (2UL)                    /*!< DSP1N1GPIO98 (Bit 2)                                  */
39776 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO98_Msk (0x4UL)                  /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
39777 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO97_Pos (1UL)                    /*!< DSP1N1GPIO97 (Bit 1)                                  */
39778 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO97_Msk (0x2UL)                  /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
39779 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO96_Pos (0UL)                    /*!< DSP1N1GPIO96 (Bit 0)                                  */
39780 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO96_Msk (0x1UL)                  /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
39781 /* ====================================================  DSP1N1INT3STAT  ===================================================== */
39782 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO127_Pos (31UL)                /*!< DSP1N1GPIO127 (Bit 31)                                */
39783 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO127_Msk (0x80000000UL)        /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
39784 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO126_Pos (30UL)                /*!< DSP1N1GPIO126 (Bit 30)                                */
39785 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO126_Msk (0x40000000UL)        /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
39786 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO125_Pos (29UL)                /*!< DSP1N1GPIO125 (Bit 29)                                */
39787 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO125_Msk (0x20000000UL)        /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
39788 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO124_Pos (28UL)                /*!< DSP1N1GPIO124 (Bit 28)                                */
39789 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO124_Msk (0x10000000UL)        /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
39790 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO123_Pos (27UL)                /*!< DSP1N1GPIO123 (Bit 27)                                */
39791 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO123_Msk (0x8000000UL)         /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
39792 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO122_Pos (26UL)                /*!< DSP1N1GPIO122 (Bit 26)                                */
39793 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO122_Msk (0x4000000UL)         /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
39794 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO121_Pos (25UL)                /*!< DSP1N1GPIO121 (Bit 25)                                */
39795 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO121_Msk (0x2000000UL)         /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
39796 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO120_Pos (24UL)                /*!< DSP1N1GPIO120 (Bit 24)                                */
39797 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO120_Msk (0x1000000UL)         /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
39798 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO119_Pos (23UL)                /*!< DSP1N1GPIO119 (Bit 23)                                */
39799 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO119_Msk (0x800000UL)          /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
39800 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO118_Pos (22UL)                /*!< DSP1N1GPIO118 (Bit 22)                                */
39801 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO118_Msk (0x400000UL)          /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
39802 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO117_Pos (21UL)                /*!< DSP1N1GPIO117 (Bit 21)                                */
39803 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO117_Msk (0x200000UL)          /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
39804 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO116_Pos (20UL)                /*!< DSP1N1GPIO116 (Bit 20)                                */
39805 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO116_Msk (0x100000UL)          /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
39806 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO115_Pos (19UL)                /*!< DSP1N1GPIO115 (Bit 19)                                */
39807 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO115_Msk (0x80000UL)           /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
39808 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO114_Pos (18UL)                /*!< DSP1N1GPIO114 (Bit 18)                                */
39809 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO114_Msk (0x40000UL)           /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
39810 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO113_Pos (17UL)                /*!< DSP1N1GPIO113 (Bit 17)                                */
39811 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO113_Msk (0x20000UL)           /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
39812 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO112_Pos (16UL)                /*!< DSP1N1GPIO112 (Bit 16)                                */
39813 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO112_Msk (0x10000UL)           /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
39814 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO111_Pos (15UL)                /*!< DSP1N1GPIO111 (Bit 15)                                */
39815 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO111_Msk (0x8000UL)            /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
39816 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO110_Pos (14UL)                /*!< DSP1N1GPIO110 (Bit 14)                                */
39817 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO110_Msk (0x4000UL)            /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
39818 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO109_Pos (13UL)                /*!< DSP1N1GPIO109 (Bit 13)                                */
39819 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO109_Msk (0x2000UL)            /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
39820 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO108_Pos (12UL)                /*!< DSP1N1GPIO108 (Bit 12)                                */
39821 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO108_Msk (0x1000UL)            /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
39822 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO107_Pos (11UL)                /*!< DSP1N1GPIO107 (Bit 11)                                */
39823 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO107_Msk (0x800UL)             /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
39824 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO106_Pos (10UL)                /*!< DSP1N1GPIO106 (Bit 10)                                */
39825 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO106_Msk (0x400UL)             /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
39826 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO105_Pos (9UL)                 /*!< DSP1N1GPIO105 (Bit 9)                                 */
39827 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO105_Msk (0x200UL)             /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
39828 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO104_Pos (8UL)                 /*!< DSP1N1GPIO104 (Bit 8)                                 */
39829 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO104_Msk (0x100UL)             /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
39830 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO103_Pos (7UL)                 /*!< DSP1N1GPIO103 (Bit 7)                                 */
39831 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO103_Msk (0x80UL)              /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
39832 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO102_Pos (6UL)                 /*!< DSP1N1GPIO102 (Bit 6)                                 */
39833 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO102_Msk (0x40UL)              /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
39834 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO101_Pos (5UL)                 /*!< DSP1N1GPIO101 (Bit 5)                                 */
39835 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO101_Msk (0x20UL)              /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
39836 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO100_Pos (4UL)                 /*!< DSP1N1GPIO100 (Bit 4)                                 */
39837 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO100_Msk (0x10UL)              /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
39838 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO99_Pos (3UL)                  /*!< DSP1N1GPIO99 (Bit 3)                                  */
39839 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO99_Msk (0x8UL)                /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
39840 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO98_Pos (2UL)                  /*!< DSP1N1GPIO98 (Bit 2)                                  */
39841 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO98_Msk (0x4UL)                /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
39842 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO97_Pos (1UL)                  /*!< DSP1N1GPIO97 (Bit 1)                                  */
39843 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO97_Msk (0x2UL)                /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
39844 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO96_Pos (0UL)                  /*!< DSP1N1GPIO96 (Bit 0)                                  */
39845 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO96_Msk (0x1UL)                /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
39846 /* =====================================================  DSP1N1INT3CLR  ===================================================== */
39847 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO127_Pos (31UL)                 /*!< DSP1N1GPIO127 (Bit 31)                                */
39848 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO127_Msk (0x80000000UL)         /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
39849 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO126_Pos (30UL)                 /*!< DSP1N1GPIO126 (Bit 30)                                */
39850 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO126_Msk (0x40000000UL)         /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
39851 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO125_Pos (29UL)                 /*!< DSP1N1GPIO125 (Bit 29)                                */
39852 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO125_Msk (0x20000000UL)         /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
39853 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO124_Pos (28UL)                 /*!< DSP1N1GPIO124 (Bit 28)                                */
39854 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO124_Msk (0x10000000UL)         /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
39855 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO123_Pos (27UL)                 /*!< DSP1N1GPIO123 (Bit 27)                                */
39856 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO123_Msk (0x8000000UL)          /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
39857 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO122_Pos (26UL)                 /*!< DSP1N1GPIO122 (Bit 26)                                */
39858 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO122_Msk (0x4000000UL)          /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
39859 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO121_Pos (25UL)                 /*!< DSP1N1GPIO121 (Bit 25)                                */
39860 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO121_Msk (0x2000000UL)          /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
39861 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO120_Pos (24UL)                 /*!< DSP1N1GPIO120 (Bit 24)                                */
39862 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO120_Msk (0x1000000UL)          /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
39863 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO119_Pos (23UL)                 /*!< DSP1N1GPIO119 (Bit 23)                                */
39864 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO119_Msk (0x800000UL)           /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
39865 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO118_Pos (22UL)                 /*!< DSP1N1GPIO118 (Bit 22)                                */
39866 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO118_Msk (0x400000UL)           /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
39867 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO117_Pos (21UL)                 /*!< DSP1N1GPIO117 (Bit 21)                                */
39868 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO117_Msk (0x200000UL)           /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
39869 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO116_Pos (20UL)                 /*!< DSP1N1GPIO116 (Bit 20)                                */
39870 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO116_Msk (0x100000UL)           /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
39871 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO115_Pos (19UL)                 /*!< DSP1N1GPIO115 (Bit 19)                                */
39872 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO115_Msk (0x80000UL)            /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
39873 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO114_Pos (18UL)                 /*!< DSP1N1GPIO114 (Bit 18)                                */
39874 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO114_Msk (0x40000UL)            /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
39875 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO113_Pos (17UL)                 /*!< DSP1N1GPIO113 (Bit 17)                                */
39876 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO113_Msk (0x20000UL)            /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
39877 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO112_Pos (16UL)                 /*!< DSP1N1GPIO112 (Bit 16)                                */
39878 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO112_Msk (0x10000UL)            /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
39879 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO111_Pos (15UL)                 /*!< DSP1N1GPIO111 (Bit 15)                                */
39880 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO111_Msk (0x8000UL)             /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
39881 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO110_Pos (14UL)                 /*!< DSP1N1GPIO110 (Bit 14)                                */
39882 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO110_Msk (0x4000UL)             /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
39883 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO109_Pos (13UL)                 /*!< DSP1N1GPIO109 (Bit 13)                                */
39884 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO109_Msk (0x2000UL)             /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
39885 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO108_Pos (12UL)                 /*!< DSP1N1GPIO108 (Bit 12)                                */
39886 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO108_Msk (0x1000UL)             /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
39887 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO107_Pos (11UL)                 /*!< DSP1N1GPIO107 (Bit 11)                                */
39888 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO107_Msk (0x800UL)              /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
39889 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO106_Pos (10UL)                 /*!< DSP1N1GPIO106 (Bit 10)                                */
39890 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO106_Msk (0x400UL)              /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
39891 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO105_Pos (9UL)                  /*!< DSP1N1GPIO105 (Bit 9)                                 */
39892 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO105_Msk (0x200UL)              /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
39893 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO104_Pos (8UL)                  /*!< DSP1N1GPIO104 (Bit 8)                                 */
39894 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO104_Msk (0x100UL)              /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
39895 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO103_Pos (7UL)                  /*!< DSP1N1GPIO103 (Bit 7)                                 */
39896 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO103_Msk (0x80UL)               /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
39897 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO102_Pos (6UL)                  /*!< DSP1N1GPIO102 (Bit 6)                                 */
39898 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO102_Msk (0x40UL)               /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
39899 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO101_Pos (5UL)                  /*!< DSP1N1GPIO101 (Bit 5)                                 */
39900 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO101_Msk (0x20UL)               /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
39901 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO100_Pos (4UL)                  /*!< DSP1N1GPIO100 (Bit 4)                                 */
39902 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO100_Msk (0x10UL)               /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
39903 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO99_Pos (3UL)                   /*!< DSP1N1GPIO99 (Bit 3)                                  */
39904 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO99_Msk (0x8UL)                 /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
39905 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO98_Pos (2UL)                   /*!< DSP1N1GPIO98 (Bit 2)                                  */
39906 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO98_Msk (0x4UL)                 /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
39907 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO97_Pos (1UL)                   /*!< DSP1N1GPIO97 (Bit 1)                                  */
39908 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO97_Msk (0x2UL)                 /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
39909 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO96_Pos (0UL)                   /*!< DSP1N1GPIO96 (Bit 0)                                  */
39910 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO96_Msk (0x1UL)                 /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
39911 /* =====================================================  DSP1N1INT3SET  ===================================================== */
39912 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO127_Pos (31UL)                 /*!< DSP1N1GPIO127 (Bit 31)                                */
39913 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO127_Msk (0x80000000UL)         /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
39914 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO126_Pos (30UL)                 /*!< DSP1N1GPIO126 (Bit 30)                                */
39915 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO126_Msk (0x40000000UL)         /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
39916 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO125_Pos (29UL)                 /*!< DSP1N1GPIO125 (Bit 29)                                */
39917 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO125_Msk (0x20000000UL)         /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
39918 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO124_Pos (28UL)                 /*!< DSP1N1GPIO124 (Bit 28)                                */
39919 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO124_Msk (0x10000000UL)         /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
39920 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO123_Pos (27UL)                 /*!< DSP1N1GPIO123 (Bit 27)                                */
39921 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO123_Msk (0x8000000UL)          /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
39922 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO122_Pos (26UL)                 /*!< DSP1N1GPIO122 (Bit 26)                                */
39923 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO122_Msk (0x4000000UL)          /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
39924 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO121_Pos (25UL)                 /*!< DSP1N1GPIO121 (Bit 25)                                */
39925 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO121_Msk (0x2000000UL)          /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
39926 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO120_Pos (24UL)                 /*!< DSP1N1GPIO120 (Bit 24)                                */
39927 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO120_Msk (0x1000000UL)          /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
39928 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO119_Pos (23UL)                 /*!< DSP1N1GPIO119 (Bit 23)                                */
39929 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO119_Msk (0x800000UL)           /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
39930 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO118_Pos (22UL)                 /*!< DSP1N1GPIO118 (Bit 22)                                */
39931 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO118_Msk (0x400000UL)           /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
39932 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO117_Pos (21UL)                 /*!< DSP1N1GPIO117 (Bit 21)                                */
39933 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO117_Msk (0x200000UL)           /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
39934 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO116_Pos (20UL)                 /*!< DSP1N1GPIO116 (Bit 20)                                */
39935 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO116_Msk (0x100000UL)           /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
39936 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO115_Pos (19UL)                 /*!< DSP1N1GPIO115 (Bit 19)                                */
39937 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO115_Msk (0x80000UL)            /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
39938 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO114_Pos (18UL)                 /*!< DSP1N1GPIO114 (Bit 18)                                */
39939 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO114_Msk (0x40000UL)            /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
39940 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO113_Pos (17UL)                 /*!< DSP1N1GPIO113 (Bit 17)                                */
39941 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO113_Msk (0x20000UL)            /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
39942 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO112_Pos (16UL)                 /*!< DSP1N1GPIO112 (Bit 16)                                */
39943 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO112_Msk (0x10000UL)            /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
39944 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO111_Pos (15UL)                 /*!< DSP1N1GPIO111 (Bit 15)                                */
39945 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO111_Msk (0x8000UL)             /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
39946 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO110_Pos (14UL)                 /*!< DSP1N1GPIO110 (Bit 14)                                */
39947 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO110_Msk (0x4000UL)             /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
39948 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO109_Pos (13UL)                 /*!< DSP1N1GPIO109 (Bit 13)                                */
39949 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO109_Msk (0x2000UL)             /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
39950 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO108_Pos (12UL)                 /*!< DSP1N1GPIO108 (Bit 12)                                */
39951 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO108_Msk (0x1000UL)             /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
39952 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO107_Pos (11UL)                 /*!< DSP1N1GPIO107 (Bit 11)                                */
39953 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO107_Msk (0x800UL)              /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
39954 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO106_Pos (10UL)                 /*!< DSP1N1GPIO106 (Bit 10)                                */
39955 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO106_Msk (0x400UL)              /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
39956 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO105_Pos (9UL)                  /*!< DSP1N1GPIO105 (Bit 9)                                 */
39957 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO105_Msk (0x200UL)              /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
39958 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO104_Pos (8UL)                  /*!< DSP1N1GPIO104 (Bit 8)                                 */
39959 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO104_Msk (0x100UL)              /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
39960 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO103_Pos (7UL)                  /*!< DSP1N1GPIO103 (Bit 7)                                 */
39961 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO103_Msk (0x80UL)               /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
39962 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO102_Pos (6UL)                  /*!< DSP1N1GPIO102 (Bit 6)                                 */
39963 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO102_Msk (0x40UL)               /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
39964 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO101_Pos (5UL)                  /*!< DSP1N1GPIO101 (Bit 5)                                 */
39965 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO101_Msk (0x20UL)               /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
39966 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO100_Pos (4UL)                  /*!< DSP1N1GPIO100 (Bit 4)                                 */
39967 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO100_Msk (0x10UL)               /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
39968 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO99_Pos (3UL)                   /*!< DSP1N1GPIO99 (Bit 3)                                  */
39969 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO99_Msk (0x8UL)                 /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
39970 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO98_Pos (2UL)                   /*!< DSP1N1GPIO98 (Bit 2)                                  */
39971 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO98_Msk (0x4UL)                 /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
39972 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO97_Pos (1UL)                   /*!< DSP1N1GPIO97 (Bit 1)                                  */
39973 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO97_Msk (0x2UL)                 /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
39974 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO96_Pos (0UL)                   /*!< DSP1N1GPIO96 (Bit 0)                                  */
39975 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO96_Msk (0x1UL)                 /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
39976 
39977 
39978 /* =========================================================================================================================== */
39979 /* ================                                            GPU                                            ================ */
39980 /* =========================================================================================================================== */
39981 
39982 /* =======================================================  TEX0BASE  ======================================================== */
39983 #define GPU_TEX0BASE_Base_Pos             (0UL)                     /*!< Base (Bit 0)                                          */
39984 #define GPU_TEX0BASE_Base_Msk             (0xffffffffUL)            /*!< Base (Bitfield-Mask: 0xffffffff)                      */
39985 /* ======================================================  TEX0STRIDE  ======================================================= */
39986 #define GPU_TEX0STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
39987 #define GPU_TEX0STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
39988 #define GPU_TEX0STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
39989 #define GPU_TEX0STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
39990 #define GPU_TEX0STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
39991 #define GPU_TEX0STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
39992 /* ========================================================  TEX0RES  ======================================================== */
39993 #define GPU_TEX0RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
39994 #define GPU_TEX0RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
39995 #define GPU_TEX0RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
39996 #define GPU_TEX0RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
39997 /* =======================================================  TEX1BASE  ======================================================== */
39998 #define GPU_TEX1BASE_Base_Pos             (0UL)                     /*!< Base (Bit 0)                                          */
39999 #define GPU_TEX1BASE_Base_Msk             (0xffffffffUL)            /*!< Base (Bitfield-Mask: 0xffffffff)                      */
40000 /* ======================================================  TEX1STRIDE  ======================================================= */
40001 #define GPU_TEX1STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
40002 #define GPU_TEX1STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
40003 #define GPU_TEX1STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
40004 #define GPU_TEX1STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
40005 #define GPU_TEX1STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
40006 #define GPU_TEX1STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
40007 /* ========================================================  TEX1RES  ======================================================== */
40008 #define GPU_TEX1RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
40009 #define GPU_TEX1RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
40010 #define GPU_TEX1RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
40011 #define GPU_TEX1RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
40012 /* =======================================================  TEX1COLOR  ======================================================= */
40013 #define GPU_TEX1COLOR_ALPHA_Pos           (24UL)                    /*!< ALPHA (Bit 24)                                        */
40014 #define GPU_TEX1COLOR_ALPHA_Msk           (0xff000000UL)            /*!< ALPHA (Bitfield-Mask: 0xff)                           */
40015 #define GPU_TEX1COLOR_BLUE_Pos            (16UL)                    /*!< BLUE (Bit 16)                                         */
40016 #define GPU_TEX1COLOR_BLUE_Msk            (0xff0000UL)              /*!< BLUE (Bitfield-Mask: 0xff)                            */
40017 #define GPU_TEX1COLOR_GREEN_Pos           (8UL)                     /*!< GREEN (Bit 8)                                         */
40018 #define GPU_TEX1COLOR_GREEN_Msk           (0xff00UL)                /*!< GREEN (Bitfield-Mask: 0xff)                           */
40019 #define GPU_TEX1COLOR_RED_Pos             (0UL)                     /*!< RED (Bit 0)                                           */
40020 #define GPU_TEX1COLOR_RED_Msk             (0xffUL)                  /*!< RED (Bitfield-Mask: 0xff)                             */
40021 /* =======================================================  TEX2BASE  ======================================================== */
40022 #define GPU_TEX2BASE_Drawing_Pos          (0UL)                     /*!< Drawing (Bit 0)                                       */
40023 #define GPU_TEX2BASE_Drawing_Msk          (0xffffffffUL)            /*!< Drawing (Bitfield-Mask: 0xffffffff)                   */
40024 /* ======================================================  TEX2STRIDE  ======================================================= */
40025 #define GPU_TEX2STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
40026 #define GPU_TEX2STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
40027 #define GPU_TEX2STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
40028 #define GPU_TEX2STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
40029 #define GPU_TEX2STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
40030 #define GPU_TEX2STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
40031 /* ========================================================  TEX2RES  ======================================================== */
40032 #define GPU_TEX2RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
40033 #define GPU_TEX2RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
40034 #define GPU_TEX2RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
40035 #define GPU_TEX2RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
40036 /* =======================================================  TEX3BASE  ======================================================== */
40037 #define GPU_TEX3BASE_Image_Pos            (0UL)                     /*!< Image (Bit 0)                                         */
40038 #define GPU_TEX3BASE_Image_Msk            (0xffffffffUL)            /*!< Image (Bitfield-Mask: 0xffffffff)                     */
40039 /* ======================================================  TEX3STRIDE  ======================================================= */
40040 #define GPU_TEX3STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
40041 #define GPU_TEX3STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
40042 #define GPU_TEX3STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
40043 #define GPU_TEX3STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
40044 #define GPU_TEX3STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
40045 #define GPU_TEX3STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
40046 /* ========================================================  TEX3RES  ======================================================== */
40047 #define GPU_TEX3RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
40048 #define GPU_TEX3RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
40049 #define GPU_TEX3RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
40050 #define GPU_TEX3RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
40051 /* =========================================================  CGCMD  ========================================================= */
40052 #define GPU_CGCMD_START_Pos               (1UL)                     /*!< START (Bit 1)                                         */
40053 #define GPU_CGCMD_START_Msk               (0x2UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
40054 #define GPU_CGCMD_STOP_Pos                (0UL)                     /*!< STOP (Bit 0)                                          */
40055 #define GPU_CGCMD_STOP_Msk                (0x1UL)                   /*!< STOP (Bitfield-Mask: 0x01)                            */
40056 /* ========================================================  CGCTRL  ========================================================= */
40057 #define GPU_CGCTRL_DISCLKMOD_Pos          (30UL)                    /*!< DISCLKMOD (Bit 30)                                    */
40058 #define GPU_CGCTRL_DISCLKMOD_Msk          (0xc0000000UL)            /*!< DISCLKMOD (Bitfield-Mask: 0x03)                       */
40059 #define GPU_CGCTRL_RSVD1_Pos              (24UL)                    /*!< RSVD1 (Bit 24)                                        */
40060 #define GPU_CGCTRL_RSVD1_Msk              (0x3f000000UL)            /*!< RSVD1 (Bitfield-Mask: 0x3f)                           */
40061 #define GPU_CGCTRL_DISCLKCORE_Pos         (23UL)                    /*!< DISCLKCORE (Bit 23)                                   */
40062 #define GPU_CGCTRL_DISCLKCORE_Msk         (0x800000UL)              /*!< DISCLKCORE (Bitfield-Mask: 0x01)                      */
40063 #define GPU_CGCTRL_RSVD0_Pos              (4UL)                     /*!< RSVD0 (Bit 4)                                         */
40064 #define GPU_CGCTRL_RSVD0_Msk              (0x7ffff0UL)              /*!< RSVD0 (Bitfield-Mask: 0x7ffff)                        */
40065 #define GPU_CGCTRL_DISCLKFRAME_Pos        (2UL)                     /*!< DISCLKFRAME (Bit 2)                                   */
40066 #define GPU_CGCTRL_DISCLKFRAME_Msk        (0xcUL)                   /*!< DISCLKFRAME (Bitfield-Mask: 0x03)                     */
40067 #define GPU_CGCTRL_DISCLKCFG_Pos          (1UL)                     /*!< DISCLKCFG (Bit 1)                                     */
40068 #define GPU_CGCTRL_DISCLKCFG_Msk          (0x2UL)                   /*!< DISCLKCFG (Bitfield-Mask: 0x01)                       */
40069 #define GPU_CGCTRL_DISCLKPROC_Pos         (0UL)                     /*!< DISCLKPROC (Bit 0)                                    */
40070 #define GPU_CGCTRL_DISCLKPROC_Msk         (0x1UL)                   /*!< DISCLKPROC (Bitfield-Mask: 0x01)                      */
40071 /* =====================================================  DIRTYTRIGMIN  ====================================================== */
40072 #define GPU_DIRTYTRIGMIN_DRTYREG_Pos      (0UL)                     /*!< DRTYREG (Bit 0)                                       */
40073 #define GPU_DIRTYTRIGMIN_DRTYREG_Msk      (0xffffffffUL)            /*!< DRTYREG (Bitfield-Mask: 0xffffffff)                   */
40074 /* =====================================================  DIRTYTRIGMAX  ====================================================== */
40075 #define GPU_DIRTYTRIGMAX_DRTYREG_Pos      (0UL)                     /*!< DRTYREG (Bit 0)                                       */
40076 #define GPU_DIRTYTRIGMAX_DRTYREG_Msk      (0xffffffffUL)            /*!< DRTYREG (Bitfield-Mask: 0xffffffff)                   */
40077 /* ========================================================  STATUS  ========================================================= */
40078 #define GPU_STATUS_SYSBSY_Pos             (31UL)                    /*!< SYSBSY (Bit 31)                                       */
40079 #define GPU_STATUS_SYSBSY_Msk             (0x80000000UL)            /*!< SYSBSY (Bitfield-Mask: 0x01)                          */
40080 #define GPU_STATUS_MEMBSY_Pos             (30UL)                    /*!< MEMBSY (Bit 30)                                       */
40081 #define GPU_STATUS_MEMBSY_Msk             (0x40000000UL)            /*!< MEMBSY (Bitfield-Mask: 0x01)                          */
40082 #define GPU_STATUS_CLBSY_Pos              (29UL)                    /*!< CLBSY (Bit 29)                                        */
40083 #define GPU_STATUS_CLBSY_Msk              (0x20000000UL)            /*!< CLBSY (Bitfield-Mask: 0x01)                           */
40084 #define GPU_STATUS_CLPBSY_Pos             (28UL)                    /*!< CLPBSY (Bit 28)                                       */
40085 #define GPU_STATUS_CLPBSY_Msk             (0x10000000UL)            /*!< CLPBSY (Bitfield-Mask: 0x01)                          */
40086 #define GPU_STATUS_RASTBSY_Pos            (24UL)                    /*!< RASTBSY (Bit 24)                                      */
40087 #define GPU_STATUS_RASTBSY_Msk            (0xf000000UL)             /*!< RASTBSY (Bitfield-Mask: 0x0f)                         */
40088 #define GPU_STATUS_DEPTHFIFOBSY_Pos       (16UL)                    /*!< DEPTHFIFOBSY (Bit 16)                                 */
40089 #define GPU_STATUS_DEPTHFIFOBSY_Msk       (0xf0000UL)               /*!< DEPTHFIFOBSY (Bitfield-Mask: 0x0f)                    */
40090 #define GPU_STATUS_RENDERBSY_Pos          (12UL)                    /*!< RENDERBSY (Bit 12)                                    */
40091 #define GPU_STATUS_RENDERBSY_Msk          (0xf000UL)                /*!< RENDERBSY (Bitfield-Mask: 0x0f)                       */
40092 #define GPU_STATUS_TEXTMAPBSY_Pos         (8UL)                     /*!< TEXTMAPBSY (Bit 8)                                    */
40093 #define GPU_STATUS_TEXTMAPBSY_Msk         (0xf00UL)                 /*!< TEXTMAPBSY (Bitfield-Mask: 0x0f)                      */
40094 #define GPU_STATUS_PIPEBSY_Pos            (4UL)                     /*!< PIPEBSY (Bit 4)                                       */
40095 #define GPU_STATUS_PIPEBSY_Msk            (0xf0UL)                  /*!< PIPEBSY (Bitfield-Mask: 0x0f)                         */
40096 #define GPU_STATUS_COREBSY_Pos            (0UL)                     /*!< COREBSY (Bit 0)                                       */
40097 #define GPU_STATUS_COREBSY_Msk            (0xfUL)                   /*!< COREBSY (Bitfield-Mask: 0x0f)                         */
40098 /* ========================================================  BUSCTRL  ======================================================== */
40099 #define GPU_BUSCTRL_BUSCTRL_Pos           (0UL)                     /*!< BUSCTRL (Bit 0)                                       */
40100 #define GPU_BUSCTRL_BUSCTRL_Msk           (0xffffffffUL)            /*!< BUSCTRL (Bitfield-Mask: 0xffffffff)                   */
40101 /* ======================================================  IMEMLDIADDR  ====================================================== */
40102 #define GPU_IMEMLDIADDR_IMEM_Pos          (0UL)                     /*!< IMEM (Bit 0)                                          */
40103 #define GPU_IMEMLDIADDR_IMEM_Msk          (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
40104 /* =====================================================  IMEMLDIDATAHL  ===================================================== */
40105 #define GPU_IMEMLDIDATAHL_IMEM_Pos        (0UL)                     /*!< IMEM (Bit 0)                                          */
40106 #define GPU_IMEMLDIDATAHL_IMEM_Msk        (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
40107 /* =====================================================  IMEMLDIDATAHH  ===================================================== */
40108 #define GPU_IMEMLDIDATAHH_IMEM_Pos        (0UL)                     /*!< IMEM (Bit 0)                                          */
40109 #define GPU_IMEMLDIDATAHH_IMEM_Msk        (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
40110 /* =====================================================  CMDLISTSTATUS  ===================================================== */
40111 #define GPU_CMDLISTSTATUS_LIST_Pos        (0UL)                     /*!< LIST (Bit 0)                                          */
40112 #define GPU_CMDLISTSTATUS_LIST_Msk        (0x1UL)                   /*!< LIST (Bitfield-Mask: 0x01)                            */
40113 /* ====================================================  CMDLISTRINGSTOP  ==================================================== */
40114 #define GPU_CMDLISTRINGSTOP_UPDATEPRT_Pos (0UL)                     /*!< UPDATEPRT (Bit 0)                                     */
40115 #define GPU_CMDLISTRINGSTOP_UPDATEPRT_Msk (0xffffffffUL)            /*!< UPDATEPRT (Bitfield-Mask: 0xffffffff)                 */
40116 /* ======================================================  CMDLISTADDR  ====================================================== */
40117 #define GPU_CMDLISTADDR_BASEPTR_Pos       (0UL)                     /*!< BASEPTR (Bit 0)                                       */
40118 #define GPU_CMDLISTADDR_BASEPTR_Msk       (0xffffffffUL)            /*!< BASEPTR (Bitfield-Mask: 0xffffffff)                   */
40119 /* ======================================================  CMDLISTSIZE  ====================================================== */
40120 #define GPU_CMDLISTSIZE_LISTWORDS_Pos     (0UL)                     /*!< LISTWORDS (Bit 0)                                     */
40121 #define GPU_CMDLISTSIZE_LISTWORDS_Msk     (0xffffffffUL)            /*!< LISTWORDS (Bitfield-Mask: 0xffffffff)                 */
40122 /* =====================================================  INTERRUPTCTRL  ===================================================== */
40123 #define GPU_INTERRUPTCTRL_CHANGEFREQ_Pos  (30UL)                    /*!< CHANGEFREQ (Bit 30)                                   */
40124 #define GPU_INTERRUPTCTRL_CHANGEFREQ_Msk  (0xc0000000UL)            /*!< CHANGEFREQ (Bitfield-Mask: 0x03)                      */
40125 #define GPU_INTERRUPTCTRL_RSVD_Pos        (4UL)                     /*!< RSVD (Bit 4)                                          */
40126 #define GPU_INTERRUPTCTRL_RSVD_Msk        (0x3ffffff0UL)            /*!< RSVD (Bitfield-Mask: 0x3ffffff)                       */
40127 #define GPU_INTERRUPTCTRL_AUTOCLR_Pos     (3UL)                     /*!< AUTOCLR (Bit 3)                                       */
40128 #define GPU_INTERRUPTCTRL_AUTOCLR_Msk     (0x8UL)                   /*!< AUTOCLR (Bitfield-Mask: 0x01)                         */
40129 #define GPU_INTERRUPTCTRL_INTDRAWEND_Pos  (2UL)                     /*!< INTDRAWEND (Bit 2)                                    */
40130 #define GPU_INTERRUPTCTRL_INTDRAWEND_Msk  (0x4UL)                   /*!< INTDRAWEND (Bitfield-Mask: 0x01)                      */
40131 #define GPU_INTERRUPTCTRL_INTCMDEND_Pos   (1UL)                     /*!< INTCMDEND (Bit 1)                                     */
40132 #define GPU_INTERRUPTCTRL_INTCMDEND_Msk   (0x2UL)                   /*!< INTCMDEND (Bitfield-Mask: 0x01)                       */
40133 #define GPU_INTERRUPTCTRL_IRQACTIVE_Pos   (0UL)                     /*!< IRQACTIVE (Bit 0)                                     */
40134 #define GPU_INTERRUPTCTRL_IRQACTIVE_Msk   (0x1UL)                   /*!< IRQACTIVE (Bitfield-Mask: 0x01)                       */
40135 /* =======================================================  SYSCLEAR  ======================================================== */
40136 #define GPU_SYSCLEAR_RESETGPU_Pos         (0UL)                     /*!< RESETGPU (Bit 0)                                      */
40137 #define GPU_SYSCLEAR_RESETGPU_Msk         (0xffffffffUL)            /*!< RESETGPU (Bitfield-Mask: 0xffffffff)                  */
40138 /* ========================================================  DRAWCMD  ======================================================== */
40139 #define GPU_DRAWCMD_RSVD_Pos              (3UL)                     /*!< RSVD (Bit 3)                                          */
40140 #define GPU_DRAWCMD_RSVD_Msk              (0xfffffff8UL)            /*!< RSVD (Bitfield-Mask: 0x1fffffff)                      */
40141 #define GPU_DRAWCMD_START_Pos             (0UL)                     /*!< START (Bit 0)                                         */
40142 #define GPU_DRAWCMD_START_Msk             (0x7UL)                   /*!< START (Bitfield-Mask: 0x07)                           */
40143 /* ========================================================  DRAWPT0  ======================================================== */
40144 #define GPU_DRAWPT0_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40145 #define GPU_DRAWPT0_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40146 #define GPU_DRAWPT0_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40147 #define GPU_DRAWPT0_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40148 /* ========================================================  DRAWPT1  ======================================================== */
40149 #define GPU_DRAWPT1_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40150 #define GPU_DRAWPT1_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40151 #define GPU_DRAWPT1_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40152 #define GPU_DRAWPT1_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40153 /* ========================================================  CLIPMIN  ======================================================== */
40154 #define GPU_CLIPMIN_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40155 #define GPU_CLIPMIN_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40156 #define GPU_CLIPMIN_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40157 #define GPU_CLIPMIN_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40158 /* ========================================================  CLIPMAX  ======================================================== */
40159 #define GPU_CLIPMAX_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40160 #define GPU_CLIPMAX_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40161 #define GPU_CLIPMAX_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40162 #define GPU_CLIPMAX_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40163 /* =======================================================  RASTCTRL  ======================================================== */
40164 #define GPU_RASTCTRL_PERSP_Pos            (30UL)                    /*!< PERSP (Bit 30)                                        */
40165 #define GPU_RASTCTRL_PERSP_Msk            (0xc0000000UL)            /*!< PERSP (Bitfield-Mask: 0x03)                           */
40166 #define GPU_RASTCTRL_ADD_Pos              (29UL)                    /*!< ADD (Bit 29)                                          */
40167 #define GPU_RASTCTRL_ADD_Msk              (0x20000000UL)            /*!< ADD (Bitfield-Mask: 0x01)                             */
40168 #define GPU_RASTCTRL_BYPASS_Pos           (28UL)                    /*!< BYPASS (Bit 28)                                       */
40169 #define GPU_RASTCTRL_BYPASS_Msk           (0x10000000UL)            /*!< BYPASS (Bitfield-Mask: 0x01)                          */
40170 #define GPU_RASTCTRL_RSVD_Pos             (0UL)                     /*!< RSVD (Bit 0)                                          */
40171 #define GPU_RASTCTRL_RSVD_Msk             (0xfffffffUL)             /*!< RSVD (Bitfield-Mask: 0xfffffff)                       */
40172 /* ======================================================  DRAWCODEPTR  ====================================================== */
40173 #define GPU_DRAWCODEPTR_BKGND_Pos         (16UL)                    /*!< BKGND (Bit 16)                                        */
40174 #define GPU_DRAWCODEPTR_BKGND_Msk         (0xffff0000UL)            /*!< BKGND (Bitfield-Mask: 0xffff)                         */
40175 #define GPU_DRAWCODEPTR_FRGND_Pos         (0UL)                     /*!< FRGND (Bit 0)                                         */
40176 #define GPU_DRAWCODEPTR_FRGND_Msk         (0xffffUL)                /*!< FRGND (Bitfield-Mask: 0xffff)                         */
40177 /* =======================================================  DRAWPT0X  ======================================================== */
40178 #define GPU_DRAWPT0X_DRAW0X_Pos           (0UL)                     /*!< DRAW0X (Bit 0)                                        */
40179 #define GPU_DRAWPT0X_DRAW0X_Msk           (0xffffffffUL)            /*!< DRAW0X (Bitfield-Mask: 0xffffffff)                    */
40180 /* =======================================================  DRAWPT0Y  ======================================================== */
40181 #define GPU_DRAWPT0Y_DRAW0Y_Pos           (0UL)                     /*!< DRAW0Y (Bit 0)                                        */
40182 #define GPU_DRAWPT0Y_DRAW0Y_Msk           (0xffffffffUL)            /*!< DRAW0Y (Bitfield-Mask: 0xffffffff)                    */
40183 /* =======================================================  DRAWPT0Z  ======================================================== */
40184 #define GPU_DRAWPT0Z_DRAW0Z_Pos           (0UL)                     /*!< DRAW0Z (Bit 0)                                        */
40185 #define GPU_DRAWPT0Z_DRAW0Z_Msk           (0xffffffffUL)            /*!< DRAW0Z (Bitfield-Mask: 0xffffffff)                    */
40186 /* =======================================================  DRAWCOLOR  ======================================================= */
40187 #define GPU_DRAWCOLOR_RASTPRIM_Pos        (0UL)                     /*!< RASTPRIM (Bit 0)                                      */
40188 #define GPU_DRAWCOLOR_RASTPRIM_Msk        (0xffffffffUL)            /*!< RASTPRIM (Bitfield-Mask: 0xffffffff)                  */
40189 /* =======================================================  DRAWPT1X  ======================================================== */
40190 #define GPU_DRAWPT1X_DRAW1X_Pos           (0UL)                     /*!< DRAW1X (Bit 0)                                        */
40191 #define GPU_DRAWPT1X_DRAW1X_Msk           (0xffffffffUL)            /*!< DRAW1X (Bitfield-Mask: 0xffffffff)                    */
40192 /* =======================================================  DRAWPT1Y  ======================================================== */
40193 #define GPU_DRAWPT1Y_DRAW1Y_Pos           (0UL)                     /*!< DRAW1Y (Bit 0)                                        */
40194 #define GPU_DRAWPT1Y_DRAW1Y_Msk           (0xffffffffUL)            /*!< DRAW1Y (Bitfield-Mask: 0xffffffff)                    */
40195 /* =======================================================  DRAWPT1Z  ======================================================== */
40196 #define GPU_DRAWPT1Z_DRAW1Z_Pos           (0UL)                     /*!< DRAW1Z (Bit 0)                                        */
40197 #define GPU_DRAWPT1Z_DRAW1Z_Msk           (0xffffffffUL)            /*!< DRAW1Z (Bitfield-Mask: 0xffffffff)                    */
40198 /* =======================================================  DRAWPT2X  ======================================================== */
40199 #define GPU_DRAWPT2X_DRAW2X_Pos           (0UL)                     /*!< DRAW2X (Bit 0)                                        */
40200 #define GPU_DRAWPT2X_DRAW2X_Msk           (0xffffffffUL)            /*!< DRAW2X (Bitfield-Mask: 0xffffffff)                    */
40201 /* =======================================================  DRAWPT2Y  ======================================================== */
40202 #define GPU_DRAWPT2Y_DRAW2Y_Pos           (0UL)                     /*!< DRAW2Y (Bit 0)                                        */
40203 #define GPU_DRAWPT2Y_DRAW2Y_Msk           (0xffffffffUL)            /*!< DRAW2Y (Bitfield-Mask: 0xffffffff)                    */
40204 /* =======================================================  DRAWPT2Z  ======================================================== */
40205 #define GPU_DRAWPT2Z_RSVD_Pos             (0UL)                     /*!< RSVD (Bit 0)                                          */
40206 #define GPU_DRAWPT2Z_RSVD_Msk             (0xffffffffUL)            /*!< RSVD (Bitfield-Mask: 0xffffffff)                      */
40207 /* =======================================================  DRAWPT3X  ======================================================== */
40208 #define GPU_DRAWPT3X_DRAW3X_Pos           (0UL)                     /*!< DRAW3X (Bit 0)                                        */
40209 #define GPU_DRAWPT3X_DRAW3X_Msk           (0xffffffffUL)            /*!< DRAW3X (Bitfield-Mask: 0xffffffff)                    */
40210 /* =======================================================  DRAWPT3Y  ======================================================== */
40211 #define GPU_DRAWPT3Y_DRAW3Y_Pos           (0UL)                     /*!< DRAW3Y (Bit 0)                                        */
40212 #define GPU_DRAWPT3Y_DRAW3Y_Msk           (0xffffffffUL)            /*!< DRAW3Y (Bitfield-Mask: 0xffffffff)                    */
40213 /* =======================================================  DRAWPT3Z  ======================================================== */
40214 #define GPU_DRAWPT3Z_DRAW3Z_Pos           (0UL)                     /*!< DRAW3Z (Bit 0)                                        */
40215 #define GPU_DRAWPT3Z_DRAW3Z_Msk           (0xffffffffUL)            /*!< DRAW3Z (Bitfield-Mask: 0xffffffff)                    */
40216 /* =========================================================  MM00  ========================================================== */
40217 #define GPU_MM00_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40218 #define GPU_MM00_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40219 /* =========================================================  MM01  ========================================================== */
40220 #define GPU_MM01_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40221 #define GPU_MM01_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40222 /* =========================================================  MM02  ========================================================== */
40223 #define GPU_MM02_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40224 #define GPU_MM02_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40225 /* =========================================================  MM10  ========================================================== */
40226 #define GPU_MM10_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40227 #define GPU_MM10_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40228 /* =========================================================  MM11  ========================================================== */
40229 #define GPU_MM11_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40230 #define GPU_MM11_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40231 /* =========================================================  MM12  ========================================================== */
40232 #define GPU_MM12_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40233 #define GPU_MM12_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40234 /* =========================================================  MM20  ========================================================== */
40235 #define GPU_MM20_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40236 #define GPU_MM20_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40237 /* =========================================================  MM21  ========================================================== */
40238 #define GPU_MM21_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40239 #define GPU_MM21_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40240 /* =========================================================  MM22  ========================================================== */
40241 #define GPU_MM22_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40242 #define GPU_MM22_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40243 /* ======================================================  DEPTHSTARTL  ====================================================== */
40244 #define GPU_DEPTHSTARTL_DEPTH32LO_Pos     (0UL)                     /*!< DEPTH32LO (Bit 0)                                     */
40245 #define GPU_DEPTHSTARTL_DEPTH32LO_Msk     (0xffffffffUL)            /*!< DEPTH32LO (Bitfield-Mask: 0xffffffff)                 */
40246 /* ======================================================  DEPTHSTARTH  ====================================================== */
40247 #define GPU_DEPTHSTARTH_DEPTH32HI_Pos     (0UL)                     /*!< DEPTH32HI (Bit 0)                                     */
40248 #define GPU_DEPTHSTARTH_DEPTH32HI_Msk     (0xffffffffUL)            /*!< DEPTH32HI (Bitfield-Mask: 0xffffffff)                 */
40249 /* =======================================================  DEPTHDXL  ======================================================== */
40250 #define GPU_DEPTHDXL_XAXISLO_Pos          (0UL)                     /*!< XAXISLO (Bit 0)                                       */
40251 #define GPU_DEPTHDXL_XAXISLO_Msk          (0xffffffffUL)            /*!< XAXISLO (Bitfield-Mask: 0xffffffff)                   */
40252 /* =======================================================  DEPTHDXH  ======================================================== */
40253 #define GPU_DEPTHDXH_XAXISHI_Pos          (0UL)                     /*!< XAXISHI (Bit 0)                                       */
40254 #define GPU_DEPTHDXH_XAXISHI_Msk          (0xffffffffUL)            /*!< XAXISHI (Bitfield-Mask: 0xffffffff)                   */
40255 /* =======================================================  DEPTHDYL  ======================================================== */
40256 #define GPU_DEPTHDYL_YAXISLO_Pos          (0UL)                     /*!< YAXISLO (Bit 0)                                       */
40257 #define GPU_DEPTHDYL_YAXISLO_Msk          (0xffffffffUL)            /*!< YAXISLO (Bitfield-Mask: 0xffffffff)                   */
40258 /* =======================================================  DEPTHDYH  ======================================================== */
40259 #define GPU_DEPTHDYH_YAXISHI_Pos          (0UL)                     /*!< YAXISHI (Bit 0)                                       */
40260 #define GPU_DEPTHDYH_YAXISHI_Msk          (0xffffffffUL)            /*!< YAXISHI (Bitfield-Mask: 0xffffffff)                   */
40261 /* =========================================================  REDX  ========================================================== */
40262 #define GPU_REDX_REDX_Pos                 (0UL)                     /*!< REDX (Bit 0)                                          */
40263 #define GPU_REDX_REDX_Msk                 (0xffffffffUL)            /*!< REDX (Bitfield-Mask: 0xffffffff)                      */
40264 /* =========================================================  REDY  ========================================================== */
40265 #define GPU_REDY_REDY_Pos                 (0UL)                     /*!< REDY (Bit 0)                                          */
40266 #define GPU_REDY_REDY_Msk                 (0xffffffffUL)            /*!< REDY (Bitfield-Mask: 0xffffffff)                      */
40267 /* ========================================================  GREENX  ========================================================= */
40268 #define GPU_GREENX_GREENX_Pos             (0UL)                     /*!< GREENX (Bit 0)                                        */
40269 #define GPU_GREENX_GREENX_Msk             (0xffffffffUL)            /*!< GREENX (Bitfield-Mask: 0xffffffff)                    */
40270 /* ========================================================  GREENY  ========================================================= */
40271 #define GPU_GREENY_GREENY_Pos             (0UL)                     /*!< GREENY (Bit 0)                                        */
40272 #define GPU_GREENY_GREENY_Msk             (0xffffffffUL)            /*!< GREENY (Bitfield-Mask: 0xffffffff)                    */
40273 /* =========================================================  BLUEX  ========================================================= */
40274 #define GPU_BLUEX_BLUEX_Pos               (0UL)                     /*!< BLUEX (Bit 0)                                         */
40275 #define GPU_BLUEX_BLUEX_Msk               (0xffffffffUL)            /*!< BLUEX (Bitfield-Mask: 0xffffffff)                     */
40276 /* =========================================================  BLUEY  ========================================================= */
40277 #define GPU_BLUEY_BLUEY_Pos               (0UL)                     /*!< BLUEY (Bit 0)                                         */
40278 #define GPU_BLUEY_BLUEY_Msk               (0xffffffffUL)            /*!< BLUEY (Bitfield-Mask: 0xffffffff)                     */
40279 /* =========================================================  ALFX  ========================================================== */
40280 #define GPU_ALFX_ALFX_Pos                 (0UL)                     /*!< ALFX (Bit 0)                                          */
40281 #define GPU_ALFX_ALFX_Msk                 (0xffffffffUL)            /*!< ALFX (Bitfield-Mask: 0xffffffff)                      */
40282 /* =========================================================  ALFY  ========================================================== */
40283 #define GPU_ALFY_ALFY_Pos                 (0UL)                     /*!< ALFY (Bit 0)                                          */
40284 #define GPU_ALFY_ALFY_Msk                 (0xffffffffUL)            /*!< ALFY (Bitfield-Mask: 0xffffffff)                      */
40285 /* ========================================================  REDINIT  ======================================================== */
40286 #define GPU_REDINIT_REDXY_Pos             (0UL)                     /*!< REDXY (Bit 0)                                         */
40287 #define GPU_REDINIT_REDXY_Msk             (0xffffffffUL)            /*!< REDXY (Bitfield-Mask: 0xffffffff)                     */
40288 /* ========================================================  GREINIT  ======================================================== */
40289 #define GPU_GREINIT_GREENXY_Pos           (0UL)                     /*!< GREENXY (Bit 0)                                       */
40290 #define GPU_GREINIT_GREENXY_Msk           (0xffffffffUL)            /*!< GREENXY (Bitfield-Mask: 0xffffffff)                   */
40291 /* ========================================================  BLUINIT  ======================================================== */
40292 #define GPU_BLUINIT_BLUEXY_Pos            (0UL)                     /*!< BLUEXY (Bit 0)                                        */
40293 #define GPU_BLUINIT_BLUEXY_Msk            (0xffffffffUL)            /*!< BLUEXY (Bitfield-Mask: 0xffffffff)                    */
40294 /* ========================================================  ALFINIT  ======================================================== */
40295 #define GPU_ALFINIT_ALFXY_Pos             (0UL)                     /*!< ALFXY (Bit 0)                                         */
40296 #define GPU_ALFINIT_ALFXY_Msk             (0xffffffffUL)            /*!< ALFXY (Bitfield-Mask: 0xffffffff)                     */
40297 /* =========================================================  IDREG  ========================================================= */
40298 #define GPU_IDREG_GPUID_Pos               (0UL)                     /*!< GPUID (Bit 0)                                         */
40299 #define GPU_IDREG_GPUID_Msk               (0xffffffffUL)            /*!< GPUID (Bitfield-Mask: 0xffffffff)                     */
40300 /* =======================================================  LOADCTRL  ======================================================== */
40301 #define GPU_LOADCTRL_LOADCTRL_Pos         (0UL)                     /*!< LOADCTRL (Bit 0)                                      */
40302 #define GPU_LOADCTRL_LOADCTRL_Msk         (0xffffffffUL)            /*!< LOADCTRL (Bitfield-Mask: 0xffffffff)                  */
40303 /* =========================================================  C0REG  ========================================================= */
40304 #define GPU_C0REG_C0SHADER_Pos            (0UL)                     /*!< C0SHADER (Bit 0)                                      */
40305 #define GPU_C0REG_C0SHADER_Msk            (0xffffffffUL)            /*!< C0SHADER (Bitfield-Mask: 0xffffffff)                  */
40306 /* =========================================================  C1REG  ========================================================= */
40307 #define GPU_C1REG_C1SHADER_Pos            (0UL)                     /*!< C1SHADER (Bit 0)                                      */
40308 #define GPU_C1REG_C1SHADER_Msk            (0xffffffffUL)            /*!< C1SHADER (Bitfield-Mask: 0xffffffff)                  */
40309 /* =========================================================  C2REG  ========================================================= */
40310 #define GPU_C2REG_C2SHADER_Pos            (0UL)                     /*!< C2SHADER (Bit 0)                                      */
40311 #define GPU_C2REG_C2SHADER_Msk            (0xffffffffUL)            /*!< C2SHADER (Bitfield-Mask: 0xffffffff)                  */
40312 /* =========================================================  C3REG  ========================================================= */
40313 #define GPU_C3REG_C3SHADER_Pos            (0UL)                     /*!< C3SHADER (Bit 0)                                      */
40314 #define GPU_C3REG_C3SHADER_Msk            (0xffffffffUL)            /*!< C3SHADER (Bitfield-Mask: 0xffffffff)                  */
40315 /* =========================================================  IRQID  ========================================================= */
40316 #define GPU_IRQID_IRQID_Pos               (0UL)                     /*!< IRQID (Bit 0)                                         */
40317 #define GPU_IRQID_IRQID_Msk               (0xffffffffUL)            /*!< IRQID (Bitfield-Mask: 0xffffffff)                     */
40318 
40319 
40320 /* =========================================================================================================================== */
40321 /* ================                                           I2S0                                            ================ */
40322 /* =========================================================================================================================== */
40323 
40324 /* ========================================================  RXDATA  ========================================================= */
40325 #define I2S0_RXDATA_RXSAMPLE_Pos          (0UL)                     /*!< RXSAMPLE (Bit 0)                                      */
40326 #define I2S0_RXDATA_RXSAMPLE_Msk          (0xffffffffUL)            /*!< RXSAMPLE (Bitfield-Mask: 0xffffffff)                  */
40327 /* =======================================================  RXCHANID  ======================================================== */
40328 #define I2S0_RXCHANID_RXCHANID_Pos        (0UL)                     /*!< RXCHANID (Bit 0)                                      */
40329 #define I2S0_RXCHANID_RXCHANID_Msk        (0xffUL)                  /*!< RXCHANID (Bitfield-Mask: 0xff)                        */
40330 /* =====================================================  RXFIFOSTATUS  ====================================================== */
40331 #define I2S0_RXFIFOSTATUS_RXEMPTY_Pos     (28UL)                    /*!< RXEMPTY (Bit 28)                                      */
40332 #define I2S0_RXFIFOSTATUS_RXEMPTY_Msk     (0x10000000UL)            /*!< RXEMPTY (Bitfield-Mask: 0x01)                         */
40333 #define I2S0_RXFIFOSTATUS_RXSAMPLECNT_Pos (0UL)                     /*!< RXSAMPLECNT (Bit 0)                                   */
40334 #define I2S0_RXFIFOSTATUS_RXSAMPLECNT_Msk (0xfffffffUL)             /*!< RXSAMPLECNT (Bitfield-Mask: 0xfffffff)                */
40335 /* ======================================================  RXFIFOSIZE  ======================================================= */
40336 #define I2S0_RXFIFOSIZE_SIZE_Pos          (0UL)                     /*!< SIZE (Bit 0)                                          */
40337 #define I2S0_RXFIFOSIZE_SIZE_Msk          (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40338 /* =====================================================  RXUPPERLIMIT  ====================================================== */
40339 #define I2S0_RXUPPERLIMIT_SIZE_Pos        (0UL)                     /*!< SIZE (Bit 0)                                          */
40340 #define I2S0_RXUPPERLIMIT_SIZE_Msk        (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40341 /* ========================================================  TXDATA  ========================================================= */
40342 #define I2S0_TXDATA_TXSAMPLE_Pos          (0UL)                     /*!< TXSAMPLE (Bit 0)                                      */
40343 #define I2S0_TXDATA_TXSAMPLE_Msk          (0xffffffffUL)            /*!< TXSAMPLE (Bitfield-Mask: 0xffffffff)                  */
40344 /* =======================================================  TXCHANID  ======================================================== */
40345 #define I2S0_TXCHANID_TXCHANID_Pos        (0UL)                     /*!< TXCHANID (Bit 0)                                      */
40346 #define I2S0_TXCHANID_TXCHANID_Msk        (0xffUL)                  /*!< TXCHANID (Bitfield-Mask: 0xff)                        */
40347 /* =====================================================  TXFIFOSTATUS  ====================================================== */
40348 #define I2S0_TXFIFOSTATUS_TXFIFOFULL_Pos  (28UL)                    /*!< TXFIFOFULL (Bit 28)                                   */
40349 #define I2S0_TXFIFOSTATUS_TXFIFOFULL_Msk  (0x10000000UL)            /*!< TXFIFOFULL (Bitfield-Mask: 0x01)                      */
40350 #define I2S0_TXFIFOSTATUS_TXFIFOCNT_Pos   (0UL)                     /*!< TXFIFOCNT (Bit 0)                                     */
40351 #define I2S0_TXFIFOSTATUS_TXFIFOCNT_Msk   (0xfffffffUL)             /*!< TXFIFOCNT (Bitfield-Mask: 0xfffffff)                  */
40352 /* ======================================================  TXFIFOSIZE  ======================================================= */
40353 #define I2S0_TXFIFOSIZE_SIZE_Pos          (0UL)                     /*!< SIZE (Bit 0)                                          */
40354 #define I2S0_TXFIFOSIZE_SIZE_Msk          (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40355 /* =====================================================  TXLOWERLIMIT  ====================================================== */
40356 #define I2S0_TXLOWERLIMIT_SIZE_Pos        (0UL)                     /*!< SIZE (Bit 0)                                          */
40357 #define I2S0_TXLOWERLIMIT_SIZE_Msk        (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40358 /* ======================================================  I2SDATACFG  ======================================================= */
40359 #define I2S0_I2SDATACFG_PH_Pos            (31UL)                    /*!< PH (Bit 31)                                           */
40360 #define I2S0_I2SDATACFG_PH_Msk            (0x80000000UL)            /*!< PH (Bitfield-Mask: 0x01)                              */
40361 #define I2S0_I2SDATACFG_FRLEN2_Pos        (24UL)                    /*!< FRLEN2 (Bit 24)                                       */
40362 #define I2S0_I2SDATACFG_FRLEN2_Msk        (0x7f000000UL)            /*!< FRLEN2 (Bitfield-Mask: 0x7f)                          */
40363 #define I2S0_I2SDATACFG_WDLEN2_Pos        (21UL)                    /*!< WDLEN2 (Bit 21)                                       */
40364 #define I2S0_I2SDATACFG_WDLEN2_Msk        (0xe00000UL)              /*!< WDLEN2 (Bitfield-Mask: 0x07)                          */
40365 #define I2S0_I2SDATACFG_DATADLY_Pos       (19UL)                    /*!< DATADLY (Bit 19)                                      */
40366 #define I2S0_I2SDATACFG_DATADLY_Msk       (0x180000UL)              /*!< DATADLY (Bitfield-Mask: 0x03)                         */
40367 #define I2S0_I2SDATACFG_SSZ2_Pos          (16UL)                    /*!< SSZ2 (Bit 16)                                         */
40368 #define I2S0_I2SDATACFG_SSZ2_Msk          (0x70000UL)               /*!< SSZ2 (Bitfield-Mask: 0x07)                            */
40369 #define I2S0_I2SDATACFG_FRLEN1_Pos        (8UL)                     /*!< FRLEN1 (Bit 8)                                        */
40370 #define I2S0_I2SDATACFG_FRLEN1_Msk        (0x7f00UL)                /*!< FRLEN1 (Bitfield-Mask: 0x7f)                          */
40371 #define I2S0_I2SDATACFG_WDLEN1_Pos        (5UL)                     /*!< WDLEN1 (Bit 5)                                        */
40372 #define I2S0_I2SDATACFG_WDLEN1_Msk        (0xe0UL)                  /*!< WDLEN1 (Bitfield-Mask: 0x07)                          */
40373 #define I2S0_I2SDATACFG_JUST_Pos          (3UL)                     /*!< JUST (Bit 3)                                          */
40374 #define I2S0_I2SDATACFG_JUST_Msk          (0x8UL)                   /*!< JUST (Bitfield-Mask: 0x01)                            */
40375 #define I2S0_I2SDATACFG_SSZ1_Pos          (0UL)                     /*!< SSZ1 (Bit 0)                                          */
40376 #define I2S0_I2SDATACFG_SSZ1_Msk          (0x7UL)                   /*!< SSZ1 (Bitfield-Mask: 0x07)                            */
40377 /* =======================================================  I2SIOCFG  ======================================================== */
40378 #define I2S0_I2SIOCFG_FWID_Pos            (20UL)                    /*!< FWID (Bit 20)                                         */
40379 #define I2S0_I2SIOCFG_FWID_Msk            (0xff00000UL)             /*!< FWID (Bitfield-Mask: 0xff)                            */
40380 #define I2S0_I2SIOCFG_PRx_Pos             (19UL)                    /*!< PRx (Bit 19)                                          */
40381 #define I2S0_I2SIOCFG_PRx_Msk             (0x80000UL)               /*!< PRx (Bitfield-Mask: 0x01)                             */
40382 #define I2S0_I2SIOCFG_MSL_Pos             (18UL)                    /*!< MSL (Bit 18)                                          */
40383 #define I2S0_I2SIOCFG_MSL_Msk             (0x40000UL)               /*!< MSL (Bitfield-Mask: 0x01)                             */
40384 #define I2S0_I2SIOCFG_PRTX_Pos            (17UL)                    /*!< PRTX (Bit 17)                                         */
40385 #define I2S0_I2SIOCFG_PRTX_Msk            (0x20000UL)               /*!< PRTX (Bitfield-Mask: 0x01)                            */
40386 #define I2S0_I2SIOCFG_FSP_Pos             (16UL)                    /*!< FSP (Bit 16)                                          */
40387 #define I2S0_I2SIOCFG_FSP_Msk             (0x10000UL)               /*!< FSP (Bitfield-Mask: 0x01)                             */
40388 #define I2S0_I2SIOCFG_FPER_Pos            (4UL)                     /*!< FPER (Bit 4)                                          */
40389 #define I2S0_I2SIOCFG_FPER_Msk            (0xfff0UL)                /*!< FPER (Bitfield-Mask: 0xfff)                           */
40390 #define I2S0_I2SIOCFG_OEN_Pos             (0UL)                     /*!< OEN (Bit 0)                                           */
40391 #define I2S0_I2SIOCFG_OEN_Msk             (0x1UL)                   /*!< OEN (Bitfield-Mask: 0x01)                             */
40392 /* ========================================================  I2SCTL  ========================================================= */
40393 #define I2S0_I2SCTL_I2SVAL_Pos            (31UL)                    /*!< I2SVAL (Bit 31)                                       */
40394 #define I2S0_I2SCTL_I2SVAL_Msk            (0x80000000UL)            /*!< I2SVAL (Bitfield-Mask: 0x01)                          */
40395 #define I2S0_I2SCTL_RXRST_Pos             (5UL)                     /*!< RXRST (Bit 5)                                         */
40396 #define I2S0_I2SCTL_RXRST_Msk             (0x20UL)                  /*!< RXRST (Bitfield-Mask: 0x01)                           */
40397 #define I2S0_I2SCTL_RXEN_Pos              (4UL)                     /*!< RXEN (Bit 4)                                          */
40398 #define I2S0_I2SCTL_RXEN_Msk              (0x10UL)                  /*!< RXEN (Bitfield-Mask: 0x01)                            */
40399 #define I2S0_I2SCTL_TXRST_Pos             (1UL)                     /*!< TXRST (Bit 1)                                         */
40400 #define I2S0_I2SCTL_TXRST_Msk             (0x2UL)                   /*!< TXRST (Bitfield-Mask: 0x01)                           */
40401 #define I2S0_I2SCTL_TXEN_Pos              (0UL)                     /*!< TXEN (Bit 0)                                          */
40402 #define I2S0_I2SCTL_TXEN_Msk              (0x1UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
40403 /* ========================================================  IPBIRPT  ======================================================== */
40404 #define I2S0_IPBIRPT_TXDMAI_Pos           (21UL)                    /*!< TXDMAI (Bit 21)                                       */
40405 #define I2S0_IPBIRPT_TXDMAI_Msk           (0x200000UL)              /*!< TXDMAI (Bitfield-Mask: 0x01)                          */
40406 #define I2S0_IPBIRPT_RXDMAI_Pos           (20UL)                    /*!< RXDMAI (Bit 20)                                       */
40407 #define I2S0_IPBIRPT_RXDMAI_Msk           (0x100000UL)              /*!< RXDMAI (Bitfield-Mask: 0x01)                          */
40408 #define I2S0_IPBIRPT_TXEI_Pos             (19UL)                    /*!< TXEI (Bit 19)                                         */
40409 #define I2S0_IPBIRPT_TXEI_Msk             (0x80000UL)               /*!< TXEI (Bitfield-Mask: 0x01)                            */
40410 #define I2S0_IPBIRPT_RXFI_Pos             (18UL)                    /*!< RXFI (Bit 18)                                         */
40411 #define I2S0_IPBIRPT_RXFI_Msk             (0x40000UL)               /*!< RXFI (Bitfield-Mask: 0x01)                            */
40412 #define I2S0_IPBIRPT_TXFFI_Pos            (17UL)                    /*!< TXFFI (Bit 17)                                        */
40413 #define I2S0_IPBIRPT_TXFFI_Msk            (0x20000UL)               /*!< TXFFI (Bitfield-Mask: 0x01)                           */
40414 #define I2S0_IPBIRPT_RXFFI_Pos            (16UL)                    /*!< RXFFI (Bit 16)                                        */
40415 #define I2S0_IPBIRPT_RXFFI_Msk            (0x10000UL)               /*!< RXFFI (Bitfield-Mask: 0x01)                           */
40416 #define I2S0_IPBIRPT_TXDMAM_Pos           (5UL)                     /*!< TXDMAM (Bit 5)                                        */
40417 #define I2S0_IPBIRPT_TXDMAM_Msk           (0x20UL)                  /*!< TXDMAM (Bitfield-Mask: 0x01)                          */
40418 #define I2S0_IPBIRPT_RXDMAM_Pos           (4UL)                     /*!< RXDMAM (Bit 4)                                        */
40419 #define I2S0_IPBIRPT_RXDMAM_Msk           (0x10UL)                  /*!< RXDMAM (Bitfield-Mask: 0x01)                          */
40420 #define I2S0_IPBIRPT_TXEM_Pos             (3UL)                     /*!< TXEM (Bit 3)                                          */
40421 #define I2S0_IPBIRPT_TXEM_Msk             (0x8UL)                   /*!< TXEM (Bitfield-Mask: 0x01)                            */
40422 #define I2S0_IPBIRPT_RXFM_Pos             (2UL)                     /*!< RXFM (Bit 2)                                          */
40423 #define I2S0_IPBIRPT_RXFM_Msk             (0x4UL)                   /*!< RXFM (Bitfield-Mask: 0x01)                            */
40424 #define I2S0_IPBIRPT_TXFFM_Pos            (1UL)                     /*!< TXFFM (Bit 1)                                         */
40425 #define I2S0_IPBIRPT_TXFFM_Msk            (0x2UL)                   /*!< TXFFM (Bitfield-Mask: 0x01)                           */
40426 #define I2S0_IPBIRPT_RXFFM_Pos            (0UL)                     /*!< RXFFM (Bit 0)                                         */
40427 #define I2S0_IPBIRPT_RXFFM_Msk            (0x1UL)                   /*!< RXFFM (Bitfield-Mask: 0x01)                           */
40428 /* =======================================================  IPCOREID  ======================================================== */
40429 #define I2S0_IPCOREID_COREFAM_Pos         (24UL)                    /*!< COREFAM (Bit 24)                                      */
40430 #define I2S0_IPCOREID_COREFAM_Msk         (0xff000000UL)            /*!< COREFAM (Bitfield-Mask: 0xff)                         */
40431 #define I2S0_IPCOREID_COREID_Pos          (16UL)                    /*!< COREID (Bit 16)                                       */
40432 #define I2S0_IPCOREID_COREID_Msk          (0xff0000UL)              /*!< COREID (Bitfield-Mask: 0xff)                          */
40433 /* ========================================================  AMQCFG  ========================================================= */
40434 #define I2S0_AMQCFG_ASRCEN_Pos            (1UL)                     /*!< ASRCEN (Bit 1)                                        */
40435 #define I2S0_AMQCFG_ASRCEN_Msk            (0x2UL)                   /*!< ASRCEN (Bitfield-Mask: 0x01)                          */
40436 #define I2S0_AMQCFG_MCLKSRC_Pos           (0UL)                     /*!< MCLKSRC (Bit 0)                                       */
40437 #define I2S0_AMQCFG_MCLKSRC_Msk           (0x1UL)                   /*!< MCLKSRC (Bitfield-Mask: 0x01)                         */
40438 /* ========================================================  INTDIV  ========================================================= */
40439 #define I2S0_INTDIV_INTDIV_Pos            (0UL)                     /*!< INTDIV (Bit 0)                                        */
40440 #define I2S0_INTDIV_INTDIV_Msk            (0xffffffffUL)            /*!< INTDIV (Bitfield-Mask: 0xffffffff)                    */
40441 /* ========================================================  FRACDIV  ======================================================== */
40442 #define I2S0_FRACDIV_FRACDIV_Pos          (0UL)                     /*!< FRACDIV (Bit 0)                                       */
40443 #define I2S0_FRACDIV_FRACDIV_Msk          (0xffffffffUL)            /*!< FRACDIV (Bitfield-Mask: 0xffffffff)                   */
40444 /* ========================================================  CLKCFG  ========================================================= */
40445 #define I2S0_CLKCFG_DIV3_Pos              (20UL)                    /*!< DIV3 (Bit 20)                                         */
40446 #define I2S0_CLKCFG_DIV3_Msk              (0x100000UL)              /*!< DIV3 (Bitfield-Mask: 0x01)                            */
40447 #define I2S0_CLKCFG_REFFSEL_Pos           (16UL)                    /*!< REFFSEL (Bit 16)                                      */
40448 #define I2S0_CLKCFG_REFFSEL_Msk           (0x30000UL)               /*!< REFFSEL (Bitfield-Mask: 0x03)                         */
40449 #define I2S0_CLKCFG_REFCLKEN_Pos          (12UL)                    /*!< REFCLKEN (Bit 12)                                     */
40450 #define I2S0_CLKCFG_REFCLKEN_Msk          (0x1000UL)                /*!< REFCLKEN (Bitfield-Mask: 0x01)                        */
40451 #define I2S0_CLKCFG_FSEL_Pos              (4UL)                     /*!< FSEL (Bit 4)                                          */
40452 #define I2S0_CLKCFG_FSEL_Msk              (0x1f0UL)                 /*!< FSEL (Bitfield-Mask: 0x1f)                            */
40453 #define I2S0_CLKCFG_MCLKEN_Pos            (0UL)                     /*!< MCLKEN (Bit 0)                                        */
40454 #define I2S0_CLKCFG_MCLKEN_Msk            (0x1UL)                   /*!< MCLKEN (Bitfield-Mask: 0x01)                          */
40455 /* ========================================================  DMACFG  ========================================================= */
40456 #define I2S0_DMACFG_RXREQCNT_Pos          (16UL)                    /*!< RXREQCNT (Bit 16)                                     */
40457 #define I2S0_DMACFG_RXREQCNT_Msk          (0xff0000UL)              /*!< RXREQCNT (Bitfield-Mask: 0xff)                        */
40458 #define I2S0_DMACFG_TXREQCNT_Pos          (8UL)                     /*!< TXREQCNT (Bit 8)                                      */
40459 #define I2S0_DMACFG_TXREQCNT_Msk          (0xff00UL)                /*!< TXREQCNT (Bitfield-Mask: 0xff)                        */
40460 #define I2S0_DMACFG_TXDMAPRI_Pos          (5UL)                     /*!< TXDMAPRI (Bit 5)                                      */
40461 #define I2S0_DMACFG_TXDMAPRI_Msk          (0x20UL)                  /*!< TXDMAPRI (Bitfield-Mask: 0x01)                        */
40462 #define I2S0_DMACFG_TXDMAEN_Pos           (4UL)                     /*!< TXDMAEN (Bit 4)                                       */
40463 #define I2S0_DMACFG_TXDMAEN_Msk           (0x10UL)                  /*!< TXDMAEN (Bitfield-Mask: 0x01)                         */
40464 #define I2S0_DMACFG_RXDMAPRI_Pos          (1UL)                     /*!< RXDMAPRI (Bit 1)                                      */
40465 #define I2S0_DMACFG_RXDMAPRI_Msk          (0x2UL)                   /*!< RXDMAPRI (Bitfield-Mask: 0x01)                        */
40466 #define I2S0_DMACFG_RXDMAEN_Pos           (0UL)                     /*!< RXDMAEN (Bit 0)                                       */
40467 #define I2S0_DMACFG_RXDMAEN_Msk           (0x1UL)                   /*!< RXDMAEN (Bitfield-Mask: 0x01)                         */
40468 /* ======================================================  RXDMATOTCNT  ====================================================== */
40469 #define I2S0_RXDMATOTCNT_RXTOTCNT_Pos     (0UL)                     /*!< RXTOTCNT (Bit 0)                                      */
40470 #define I2S0_RXDMATOTCNT_RXTOTCNT_Msk     (0xfffUL)                 /*!< RXTOTCNT (Bitfield-Mask: 0xfff)                       */
40471 /* =======================================================  RXDMAADDR  ======================================================= */
40472 #define I2S0_RXDMAADDR_RXTARGADDR_Pos     (0UL)                     /*!< RXTARGADDR (Bit 0)                                    */
40473 #define I2S0_RXDMAADDR_RXTARGADDR_Msk     (0xffffffffUL)            /*!< RXTARGADDR (Bitfield-Mask: 0xffffffff)                */
40474 /* =======================================================  RXDMASTAT  ======================================================= */
40475 #define I2S0_RXDMASTAT_RXDMAERR_Pos       (2UL)                     /*!< RXDMAERR (Bit 2)                                      */
40476 #define I2S0_RXDMASTAT_RXDMAERR_Msk       (0x4UL)                   /*!< RXDMAERR (Bitfield-Mask: 0x01)                        */
40477 #define I2S0_RXDMASTAT_RXDMACPL_Pos       (1UL)                     /*!< RXDMACPL (Bit 1)                                      */
40478 #define I2S0_RXDMASTAT_RXDMACPL_Msk       (0x2UL)                   /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
40479 #define I2S0_RXDMASTAT_RXDMATIP_Pos       (0UL)                     /*!< RXDMATIP (Bit 0)                                      */
40480 #define I2S0_RXDMASTAT_RXDMATIP_Msk       (0x1UL)                   /*!< RXDMATIP (Bitfield-Mask: 0x01)                        */
40481 /* ======================================================  TXDMATOTCNT  ====================================================== */
40482 #define I2S0_TXDMATOTCNT_TXTOTCNT_Pos     (0UL)                     /*!< TXTOTCNT (Bit 0)                                      */
40483 #define I2S0_TXDMATOTCNT_TXTOTCNT_Msk     (0xfffUL)                 /*!< TXTOTCNT (Bitfield-Mask: 0xfff)                       */
40484 /* =======================================================  TXDMAADDR  ======================================================= */
40485 #define I2S0_TXDMAADDR_TXTARGADDR_Pos     (0UL)                     /*!< TXTARGADDR (Bit 0)                                    */
40486 #define I2S0_TXDMAADDR_TXTARGADDR_Msk     (0xffffffffUL)            /*!< TXTARGADDR (Bitfield-Mask: 0xffffffff)                */
40487 /* =======================================================  TXDMASTAT  ======================================================= */
40488 #define I2S0_TXDMASTAT_TXDMAERR_Pos       (2UL)                     /*!< TXDMAERR (Bit 2)                                      */
40489 #define I2S0_TXDMASTAT_TXDMAERR_Msk       (0x4UL)                   /*!< TXDMAERR (Bitfield-Mask: 0x01)                        */
40490 #define I2S0_TXDMASTAT_TXDMACPL_Pos       (1UL)                     /*!< TXDMACPL (Bit 1)                                      */
40491 #define I2S0_TXDMASTAT_TXDMACPL_Msk       (0x2UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
40492 #define I2S0_TXDMASTAT_TXDMATIP_Pos       (0UL)                     /*!< TXDMATIP (Bit 0)                                      */
40493 #define I2S0_TXDMASTAT_TXDMATIP_Msk       (0x1UL)                   /*!< TXDMATIP (Bitfield-Mask: 0x01)                        */
40494 /* ========================================================  STATUS  ========================================================= */
40495 #define I2S0_STATUS_TBD_Pos               (0UL)                     /*!< TBD (Bit 0)                                           */
40496 #define I2S0_STATUS_TBD_Msk               (0x1UL)                   /*!< TBD (Bitfield-Mask: 0x01)                             */
40497 /* =========================================================  INTEN  ========================================================= */
40498 #define I2S0_INTEN_RXDMACPL_Pos           (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
40499 #define I2S0_INTEN_RXDMACPL_Msk           (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
40500 #define I2S0_INTEN_TXDMACPL_Pos           (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
40501 #define I2S0_INTEN_TXDMACPL_Msk           (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
40502 #define I2S0_INTEN_TXREQCNT_Pos           (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
40503 #define I2S0_INTEN_TXREQCNT_Msk           (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
40504 #define I2S0_INTEN_RXREQCNT_Pos           (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
40505 #define I2S0_INTEN_RXREQCNT_Msk           (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
40506 #define I2S0_INTEN_IPB_Pos                (0UL)                     /*!< IPB (Bit 0)                                           */
40507 #define I2S0_INTEN_IPB_Msk                (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
40508 /* ========================================================  INTSTAT  ======================================================== */
40509 #define I2S0_INTSTAT_RXDMACPL_Pos         (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
40510 #define I2S0_INTSTAT_RXDMACPL_Msk         (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
40511 #define I2S0_INTSTAT_TXDMACPL_Pos         (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
40512 #define I2S0_INTSTAT_TXDMACPL_Msk         (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
40513 #define I2S0_INTSTAT_TXREQCNT_Pos         (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
40514 #define I2S0_INTSTAT_TXREQCNT_Msk         (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
40515 #define I2S0_INTSTAT_RXREQCNT_Pos         (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
40516 #define I2S0_INTSTAT_RXREQCNT_Msk         (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
40517 #define I2S0_INTSTAT_IPB_Pos              (0UL)                     /*!< IPB (Bit 0)                                           */
40518 #define I2S0_INTSTAT_IPB_Msk              (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
40519 /* ========================================================  INTCLR  ========================================================= */
40520 #define I2S0_INTCLR_RXDMACPL_Pos          (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
40521 #define I2S0_INTCLR_RXDMACPL_Msk          (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
40522 #define I2S0_INTCLR_TXDMACPL_Pos          (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
40523 #define I2S0_INTCLR_TXDMACPL_Msk          (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
40524 #define I2S0_INTCLR_TXREQCNT_Pos          (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
40525 #define I2S0_INTCLR_TXREQCNT_Msk          (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
40526 #define I2S0_INTCLR_RXREQCNT_Pos          (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
40527 #define I2S0_INTCLR_RXREQCNT_Msk          (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
40528 #define I2S0_INTCLR_IPB_Pos               (0UL)                     /*!< IPB (Bit 0)                                           */
40529 #define I2S0_INTCLR_IPB_Msk               (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
40530 /* ========================================================  INTSET  ========================================================= */
40531 #define I2S0_INTSET_RXDMACPL_Pos          (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
40532 #define I2S0_INTSET_RXDMACPL_Msk          (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
40533 #define I2S0_INTSET_TXDMACPL_Pos          (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
40534 #define I2S0_INTSET_TXDMACPL_Msk          (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
40535 #define I2S0_INTSET_TXREQCNT_Pos          (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
40536 #define I2S0_INTSET_TXREQCNT_Msk          (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
40537 #define I2S0_INTSET_RXREQCNT_Pos          (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
40538 #define I2S0_INTSET_RXREQCNT_Msk          (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
40539 #define I2S0_INTSET_IPB_Pos               (0UL)                     /*!< IPB (Bit 0)                                           */
40540 #define I2S0_INTSET_IPB_Msk               (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
40541 /* ========================================================  I2SDBG  ========================================================= */
40542 #define I2S0_I2SDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
40543 #define I2S0_I2SDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
40544 #define I2S0_I2SDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
40545 #define I2S0_I2SDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
40546 #define I2S0_I2SDBG_MCLKON_Pos            (1UL)                     /*!< MCLKON (Bit 1)                                        */
40547 #define I2S0_I2SDBG_MCLKON_Msk            (0x2UL)                   /*!< MCLKON (Bitfield-Mask: 0x01)                          */
40548 #define I2S0_I2SDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
40549 #define I2S0_I2SDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
40550 
40551 
40552 /* =========================================================================================================================== */
40553 /* ================                                           IOM0                                            ================ */
40554 /* =========================================================================================================================== */
40555 
40556 /* =========================================================  FIFO  ========================================================== */
40557 #define IOM0_FIFO_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
40558 #define IOM0_FIFO_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
40559 /* ========================================================  FIFOPTR  ======================================================== */
40560 #define IOM0_FIFOPTR_FIFO1REM_Pos         (24UL)                    /*!< FIFO1REM (Bit 24)                                     */
40561 #define IOM0_FIFOPTR_FIFO1REM_Msk         (0xff000000UL)            /*!< FIFO1REM (Bitfield-Mask: 0xff)                        */
40562 #define IOM0_FIFOPTR_FIFO1SIZ_Pos         (16UL)                    /*!< FIFO1SIZ (Bit 16)                                     */
40563 #define IOM0_FIFOPTR_FIFO1SIZ_Msk         (0xff0000UL)              /*!< FIFO1SIZ (Bitfield-Mask: 0xff)                        */
40564 #define IOM0_FIFOPTR_FIFO0REM_Pos         (8UL)                     /*!< FIFO0REM (Bit 8)                                      */
40565 #define IOM0_FIFOPTR_FIFO0REM_Msk         (0xff00UL)                /*!< FIFO0REM (Bitfield-Mask: 0xff)                        */
40566 #define IOM0_FIFOPTR_FIFO0SIZ_Pos         (0UL)                     /*!< FIFO0SIZ (Bit 0)                                      */
40567 #define IOM0_FIFOPTR_FIFO0SIZ_Msk         (0xffUL)                  /*!< FIFO0SIZ (Bitfield-Mask: 0xff)                        */
40568 /* ========================================================  FIFOTHR  ======================================================== */
40569 #define IOM0_FIFOTHR_FIFOWTHR_Pos         (8UL)                     /*!< FIFOWTHR (Bit 8)                                      */
40570 #define IOM0_FIFOTHR_FIFOWTHR_Msk         (0x3f00UL)                /*!< FIFOWTHR (Bitfield-Mask: 0x3f)                        */
40571 #define IOM0_FIFOTHR_FIFORTHR_Pos         (0UL)                     /*!< FIFORTHR (Bit 0)                                      */
40572 #define IOM0_FIFOTHR_FIFORTHR_Msk         (0x3fUL)                  /*!< FIFORTHR (Bitfield-Mask: 0x3f)                        */
40573 /* ========================================================  FIFOPOP  ======================================================== */
40574 #define IOM0_FIFOPOP_FIFODOUT_Pos         (0UL)                     /*!< FIFODOUT (Bit 0)                                      */
40575 #define IOM0_FIFOPOP_FIFODOUT_Msk         (0xffffffffUL)            /*!< FIFODOUT (Bitfield-Mask: 0xffffffff)                  */
40576 /* =======================================================  FIFOPUSH  ======================================================== */
40577 #define IOM0_FIFOPUSH_FIFODIN_Pos         (0UL)                     /*!< FIFODIN (Bit 0)                                       */
40578 #define IOM0_FIFOPUSH_FIFODIN_Msk         (0xffffffffUL)            /*!< FIFODIN (Bitfield-Mask: 0xffffffff)                   */
40579 /* =======================================================  FIFOCTRL  ======================================================== */
40580 #define IOM0_FIFOCTRL_FIFORSTN_Pos        (1UL)                     /*!< FIFORSTN (Bit 1)                                      */
40581 #define IOM0_FIFOCTRL_FIFORSTN_Msk        (0x2UL)                   /*!< FIFORSTN (Bitfield-Mask: 0x01)                        */
40582 #define IOM0_FIFOCTRL_POPWR_Pos           (0UL)                     /*!< POPWR (Bit 0)                                         */
40583 #define IOM0_FIFOCTRL_POPWR_Msk           (0x1UL)                   /*!< POPWR (Bitfield-Mask: 0x01)                           */
40584 /* ========================================================  FIFOLOC  ======================================================== */
40585 #define IOM0_FIFOLOC_FIFORPTR_Pos         (8UL)                     /*!< FIFORPTR (Bit 8)                                      */
40586 #define IOM0_FIFOLOC_FIFORPTR_Msk         (0xf00UL)                 /*!< FIFORPTR (Bitfield-Mask: 0x0f)                        */
40587 #define IOM0_FIFOLOC_FIFOWPTR_Pos         (0UL)                     /*!< FIFOWPTR (Bit 0)                                      */
40588 #define IOM0_FIFOLOC_FIFOWPTR_Msk         (0xfUL)                   /*!< FIFOWPTR (Bitfield-Mask: 0x0f)                        */
40589 /* ========================================================  CLKCFG  ========================================================= */
40590 #define IOM0_CLKCFG_TOTPER_Pos            (24UL)                    /*!< TOTPER (Bit 24)                                       */
40591 #define IOM0_CLKCFG_TOTPER_Msk            (0xff000000UL)            /*!< TOTPER (Bitfield-Mask: 0xff)                          */
40592 #define IOM0_CLKCFG_LOWPER_Pos            (16UL)                    /*!< LOWPER (Bit 16)                                       */
40593 #define IOM0_CLKCFG_LOWPER_Msk            (0xff0000UL)              /*!< LOWPER (Bitfield-Mask: 0xff)                          */
40594 #define IOM0_CLKCFG_DIVEN_Pos             (12UL)                    /*!< DIVEN (Bit 12)                                        */
40595 #define IOM0_CLKCFG_DIVEN_Msk             (0x1000UL)                /*!< DIVEN (Bitfield-Mask: 0x01)                           */
40596 #define IOM0_CLKCFG_DIV3_Pos              (11UL)                    /*!< DIV3 (Bit 11)                                         */
40597 #define IOM0_CLKCFG_DIV3_Msk              (0x800UL)                 /*!< DIV3 (Bitfield-Mask: 0x01)                            */
40598 #define IOM0_CLKCFG_FSEL_Pos              (8UL)                     /*!< FSEL (Bit 8)                                          */
40599 #define IOM0_CLKCFG_FSEL_Msk              (0x700UL)                 /*!< FSEL (Bitfield-Mask: 0x07)                            */
40600 #define IOM0_CLKCFG_IOCLKEN_Pos           (0UL)                     /*!< IOCLKEN (Bit 0)                                       */
40601 #define IOM0_CLKCFG_IOCLKEN_Msk           (0x1UL)                   /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
40602 /* ======================================================  SUBMODCTRL  ======================================================= */
40603 #define IOM0_SUBMODCTRL_SMOD2TYPE_Pos     (9UL)                     /*!< SMOD2TYPE (Bit 9)                                     */
40604 #define IOM0_SUBMODCTRL_SMOD2TYPE_Msk     (0xe00UL)                 /*!< SMOD2TYPE (Bitfield-Mask: 0x07)                       */
40605 #define IOM0_SUBMODCTRL_SMOD2EN_Pos       (8UL)                     /*!< SMOD2EN (Bit 8)                                       */
40606 #define IOM0_SUBMODCTRL_SMOD2EN_Msk       (0x100UL)                 /*!< SMOD2EN (Bitfield-Mask: 0x01)                         */
40607 #define IOM0_SUBMODCTRL_SMOD1TYPE_Pos     (5UL)                     /*!< SMOD1TYPE (Bit 5)                                     */
40608 #define IOM0_SUBMODCTRL_SMOD1TYPE_Msk     (0xe0UL)                  /*!< SMOD1TYPE (Bitfield-Mask: 0x07)                       */
40609 #define IOM0_SUBMODCTRL_SMOD1EN_Pos       (4UL)                     /*!< SMOD1EN (Bit 4)                                       */
40610 #define IOM0_SUBMODCTRL_SMOD1EN_Msk       (0x10UL)                  /*!< SMOD1EN (Bitfield-Mask: 0x01)                         */
40611 #define IOM0_SUBMODCTRL_SMOD0TYPE_Pos     (1UL)                     /*!< SMOD0TYPE (Bit 1)                                     */
40612 #define IOM0_SUBMODCTRL_SMOD0TYPE_Msk     (0xeUL)                   /*!< SMOD0TYPE (Bitfield-Mask: 0x07)                       */
40613 #define IOM0_SUBMODCTRL_SMOD0EN_Pos       (0UL)                     /*!< SMOD0EN (Bit 0)                                       */
40614 #define IOM0_SUBMODCTRL_SMOD0EN_Msk       (0x1UL)                   /*!< SMOD0EN (Bitfield-Mask: 0x01)                         */
40615 /* ==========================================================  CMD  ========================================================== */
40616 #define IOM0_CMD_OFFSETLO_Pos             (24UL)                    /*!< OFFSETLO (Bit 24)                                     */
40617 #define IOM0_CMD_OFFSETLO_Msk             (0xff000000UL)            /*!< OFFSETLO (Bitfield-Mask: 0xff)                        */
40618 #define IOM0_CMD_CMDSEL_Pos               (20UL)                    /*!< CMDSEL (Bit 20)                                       */
40619 #define IOM0_CMD_CMDSEL_Msk               (0x300000UL)              /*!< CMDSEL (Bitfield-Mask: 0x03)                          */
40620 #define IOM0_CMD_TSIZE_Pos                (8UL)                     /*!< TSIZE (Bit 8)                                         */
40621 #define IOM0_CMD_TSIZE_Msk                (0xfff00UL)               /*!< TSIZE (Bitfield-Mask: 0xfff)                          */
40622 #define IOM0_CMD_CONT_Pos                 (7UL)                     /*!< CONT (Bit 7)                                          */
40623 #define IOM0_CMD_CONT_Msk                 (0x80UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
40624 #define IOM0_CMD_OFFSETCNT_Pos            (4UL)                     /*!< OFFSETCNT (Bit 4)                                     */
40625 #define IOM0_CMD_OFFSETCNT_Msk            (0x70UL)                  /*!< OFFSETCNT (Bitfield-Mask: 0x07)                       */
40626 #define IOM0_CMD_CMD_Pos                  (0UL)                     /*!< CMD (Bit 0)                                           */
40627 #define IOM0_CMD_CMD_Msk                  (0xfUL)                   /*!< CMD (Bitfield-Mask: 0x0f)                             */
40628 /* ========================================================  DCXCTRL  ======================================================== */
40629 #define IOM0_DCXCTRL_DCXEN_Pos            (4UL)                     /*!< DCXEN (Bit 4)                                         */
40630 #define IOM0_DCXCTRL_DCXEN_Msk            (0x10UL)                  /*!< DCXEN (Bitfield-Mask: 0x01)                           */
40631 #define IOM0_DCXCTRL_DCXSEL_Pos           (0UL)                     /*!< DCXSEL (Bit 0)                                        */
40632 #define IOM0_DCXCTRL_DCXSEL_Msk           (0xfUL)                   /*!< DCXSEL (Bitfield-Mask: 0x0f)                          */
40633 /* =======================================================  OFFSETHI  ======================================================== */
40634 #define IOM0_OFFSETHI_OFFSETHI_Pos        (0UL)                     /*!< OFFSETHI (Bit 0)                                      */
40635 #define IOM0_OFFSETHI_OFFSETHI_Msk        (0xffffffffUL)            /*!< OFFSETHI (Bitfield-Mask: 0xffffffff)                  */
40636 /* ========================================================  CMDSTAT  ======================================================== */
40637 #define IOM0_CMDSTAT_CTSIZE_Pos           (8UL)                     /*!< CTSIZE (Bit 8)                                        */
40638 #define IOM0_CMDSTAT_CTSIZE_Msk           (0xfff00UL)               /*!< CTSIZE (Bitfield-Mask: 0xfff)                         */
40639 #define IOM0_CMDSTAT_CMDSTAT_Pos          (5UL)                     /*!< CMDSTAT (Bit 5)                                       */
40640 #define IOM0_CMDSTAT_CMDSTAT_Msk          (0xe0UL)                  /*!< CMDSTAT (Bitfield-Mask: 0x07)                         */
40641 #define IOM0_CMDSTAT_CCMD_Pos             (0UL)                     /*!< CCMD (Bit 0)                                          */
40642 #define IOM0_CMDSTAT_CCMD_Msk             (0x1fUL)                  /*!< CCMD (Bitfield-Mask: 0x1f)                            */
40643 /* =========================================================  INTEN  ========================================================= */
40644 #define IOM0_INTEN_CQERR_Pos              (14UL)                    /*!< CQERR (Bit 14)                                        */
40645 #define IOM0_INTEN_CQERR_Msk              (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
40646 #define IOM0_INTEN_CQUPD_Pos              (13UL)                    /*!< CQUPD (Bit 13)                                        */
40647 #define IOM0_INTEN_CQUPD_Msk              (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
40648 #define IOM0_INTEN_CQPAUSED_Pos           (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
40649 #define IOM0_INTEN_CQPAUSED_Msk           (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
40650 #define IOM0_INTEN_DERR_Pos               (11UL)                    /*!< DERR (Bit 11)                                         */
40651 #define IOM0_INTEN_DERR_Msk               (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
40652 #define IOM0_INTEN_DCMP_Pos               (10UL)                    /*!< DCMP (Bit 10)                                         */
40653 #define IOM0_INTEN_DCMP_Msk               (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
40654 #define IOM0_INTEN_ARB_Pos                (9UL)                     /*!< ARB (Bit 9)                                           */
40655 #define IOM0_INTEN_ARB_Msk                (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
40656 #define IOM0_INTEN_STOP_Pos               (8UL)                     /*!< STOP (Bit 8)                                          */
40657 #define IOM0_INTEN_STOP_Msk               (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
40658 #define IOM0_INTEN_START_Pos              (7UL)                     /*!< START (Bit 7)                                         */
40659 #define IOM0_INTEN_START_Msk              (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
40660 #define IOM0_INTEN_ICMD_Pos               (6UL)                     /*!< ICMD (Bit 6)                                          */
40661 #define IOM0_INTEN_ICMD_Msk               (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
40662 #define IOM0_INTEN_IACC_Pos               (5UL)                     /*!< IACC (Bit 5)                                          */
40663 #define IOM0_INTEN_IACC_Msk               (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
40664 #define IOM0_INTEN_NAK_Pos                (4UL)                     /*!< NAK (Bit 4)                                           */
40665 #define IOM0_INTEN_NAK_Msk                (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
40666 #define IOM0_INTEN_FOVFL_Pos              (3UL)                     /*!< FOVFL (Bit 3)                                         */
40667 #define IOM0_INTEN_FOVFL_Msk              (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
40668 #define IOM0_INTEN_FUNDFL_Pos             (2UL)                     /*!< FUNDFL (Bit 2)                                        */
40669 #define IOM0_INTEN_FUNDFL_Msk             (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
40670 #define IOM0_INTEN_THR_Pos                (1UL)                     /*!< THR (Bit 1)                                           */
40671 #define IOM0_INTEN_THR_Msk                (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
40672 #define IOM0_INTEN_CMDCMP_Pos             (0UL)                     /*!< CMDCMP (Bit 0)                                        */
40673 #define IOM0_INTEN_CMDCMP_Msk             (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
40674 /* ========================================================  INTSTAT  ======================================================== */
40675 #define IOM0_INTSTAT_CQERR_Pos            (14UL)                    /*!< CQERR (Bit 14)                                        */
40676 #define IOM0_INTSTAT_CQERR_Msk            (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
40677 #define IOM0_INTSTAT_CQUPD_Pos            (13UL)                    /*!< CQUPD (Bit 13)                                        */
40678 #define IOM0_INTSTAT_CQUPD_Msk            (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
40679 #define IOM0_INTSTAT_CQPAUSED_Pos         (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
40680 #define IOM0_INTSTAT_CQPAUSED_Msk         (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
40681 #define IOM0_INTSTAT_DERR_Pos             (11UL)                    /*!< DERR (Bit 11)                                         */
40682 #define IOM0_INTSTAT_DERR_Msk             (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
40683 #define IOM0_INTSTAT_DCMP_Pos             (10UL)                    /*!< DCMP (Bit 10)                                         */
40684 #define IOM0_INTSTAT_DCMP_Msk             (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
40685 #define IOM0_INTSTAT_ARB_Pos              (9UL)                     /*!< ARB (Bit 9)                                           */
40686 #define IOM0_INTSTAT_ARB_Msk              (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
40687 #define IOM0_INTSTAT_STOP_Pos             (8UL)                     /*!< STOP (Bit 8)                                          */
40688 #define IOM0_INTSTAT_STOP_Msk             (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
40689 #define IOM0_INTSTAT_START_Pos            (7UL)                     /*!< START (Bit 7)                                         */
40690 #define IOM0_INTSTAT_START_Msk            (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
40691 #define IOM0_INTSTAT_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
40692 #define IOM0_INTSTAT_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
40693 #define IOM0_INTSTAT_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
40694 #define IOM0_INTSTAT_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
40695 #define IOM0_INTSTAT_NAK_Pos              (4UL)                     /*!< NAK (Bit 4)                                           */
40696 #define IOM0_INTSTAT_NAK_Msk              (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
40697 #define IOM0_INTSTAT_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
40698 #define IOM0_INTSTAT_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
40699 #define IOM0_INTSTAT_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
40700 #define IOM0_INTSTAT_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
40701 #define IOM0_INTSTAT_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
40702 #define IOM0_INTSTAT_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
40703 #define IOM0_INTSTAT_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
40704 #define IOM0_INTSTAT_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
40705 /* ========================================================  INTCLR  ========================================================= */
40706 #define IOM0_INTCLR_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
40707 #define IOM0_INTCLR_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
40708 #define IOM0_INTCLR_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
40709 #define IOM0_INTCLR_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
40710 #define IOM0_INTCLR_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
40711 #define IOM0_INTCLR_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
40712 #define IOM0_INTCLR_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
40713 #define IOM0_INTCLR_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
40714 #define IOM0_INTCLR_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
40715 #define IOM0_INTCLR_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
40716 #define IOM0_INTCLR_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
40717 #define IOM0_INTCLR_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
40718 #define IOM0_INTCLR_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
40719 #define IOM0_INTCLR_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
40720 #define IOM0_INTCLR_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
40721 #define IOM0_INTCLR_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
40722 #define IOM0_INTCLR_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
40723 #define IOM0_INTCLR_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
40724 #define IOM0_INTCLR_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
40725 #define IOM0_INTCLR_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
40726 #define IOM0_INTCLR_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
40727 #define IOM0_INTCLR_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
40728 #define IOM0_INTCLR_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
40729 #define IOM0_INTCLR_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
40730 #define IOM0_INTCLR_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
40731 #define IOM0_INTCLR_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
40732 #define IOM0_INTCLR_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
40733 #define IOM0_INTCLR_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
40734 #define IOM0_INTCLR_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
40735 #define IOM0_INTCLR_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
40736 /* ========================================================  INTSET  ========================================================= */
40737 #define IOM0_INTSET_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
40738 #define IOM0_INTSET_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
40739 #define IOM0_INTSET_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
40740 #define IOM0_INTSET_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
40741 #define IOM0_INTSET_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
40742 #define IOM0_INTSET_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
40743 #define IOM0_INTSET_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
40744 #define IOM0_INTSET_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
40745 #define IOM0_INTSET_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
40746 #define IOM0_INTSET_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
40747 #define IOM0_INTSET_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
40748 #define IOM0_INTSET_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
40749 #define IOM0_INTSET_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
40750 #define IOM0_INTSET_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
40751 #define IOM0_INTSET_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
40752 #define IOM0_INTSET_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
40753 #define IOM0_INTSET_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
40754 #define IOM0_INTSET_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
40755 #define IOM0_INTSET_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
40756 #define IOM0_INTSET_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
40757 #define IOM0_INTSET_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
40758 #define IOM0_INTSET_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
40759 #define IOM0_INTSET_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
40760 #define IOM0_INTSET_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
40761 #define IOM0_INTSET_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
40762 #define IOM0_INTSET_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
40763 #define IOM0_INTSET_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
40764 #define IOM0_INTSET_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
40765 #define IOM0_INTSET_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
40766 #define IOM0_INTSET_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
40767 /* =======================================================  DMATRIGEN  ======================================================= */
40768 #define IOM0_DMATRIGEN_DTHREN_Pos         (1UL)                     /*!< DTHREN (Bit 1)                                        */
40769 #define IOM0_DMATRIGEN_DTHREN_Msk         (0x2UL)                   /*!< DTHREN (Bitfield-Mask: 0x01)                          */
40770 #define IOM0_DMATRIGEN_DCMDCMPEN_Pos      (0UL)                     /*!< DCMDCMPEN (Bit 0)                                     */
40771 #define IOM0_DMATRIGEN_DCMDCMPEN_Msk      (0x1UL)                   /*!< DCMDCMPEN (Bitfield-Mask: 0x01)                       */
40772 /* ======================================================  DMATRIGSTAT  ====================================================== */
40773 #define IOM0_DMATRIGSTAT_DTOTCMP_Pos      (2UL)                     /*!< DTOTCMP (Bit 2)                                       */
40774 #define IOM0_DMATRIGSTAT_DTOTCMP_Msk      (0x4UL)                   /*!< DTOTCMP (Bitfield-Mask: 0x01)                         */
40775 #define IOM0_DMATRIGSTAT_DTHR_Pos         (1UL)                     /*!< DTHR (Bit 1)                                          */
40776 #define IOM0_DMATRIGSTAT_DTHR_Msk         (0x2UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
40777 #define IOM0_DMATRIGSTAT_DCMDCMP_Pos      (0UL)                     /*!< DCMDCMP (Bit 0)                                       */
40778 #define IOM0_DMATRIGSTAT_DCMDCMP_Msk      (0x1UL)                   /*!< DCMDCMP (Bitfield-Mask: 0x01)                         */
40779 /* ========================================================  DMACFG  ========================================================= */
40780 #define IOM0_DMACFG_DPWROFF_Pos           (9UL)                     /*!< DPWROFF (Bit 9)                                       */
40781 #define IOM0_DMACFG_DPWROFF_Msk           (0x200UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
40782 #define IOM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
40783 #define IOM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
40784 #define IOM0_DMACFG_DMADIR_Pos            (1UL)                     /*!< DMADIR (Bit 1)                                        */
40785 #define IOM0_DMACFG_DMADIR_Msk            (0x2UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
40786 #define IOM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
40787 #define IOM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
40788 /* ======================================================  DMATOTCOUNT  ====================================================== */
40789 #define IOM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
40790 #define IOM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffUL)                 /*!< TOTCOUNT (Bitfield-Mask: 0xfff)                       */
40791 /* ======================================================  DMATARGADDR  ====================================================== */
40792 #define IOM0_DMATARGADDR_TARGADDR_Pos     (0UL)                     /*!< TARGADDR (Bit 0)                                      */
40793 #define IOM0_DMATARGADDR_TARGADDR_Msk     (0x1fffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0x1fffffff)                  */
40794 /* ========================================================  DMASTAT  ======================================================== */
40795 #define IOM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
40796 #define IOM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
40797 #define IOM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
40798 #define IOM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
40799 #define IOM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
40800 #define IOM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
40801 /* =========================================================  CQCFG  ========================================================= */
40802 #define IOM0_CQCFG_MSPIFLGSEL_Pos         (2UL)                     /*!< MSPIFLGSEL (Bit 2)                                    */
40803 #define IOM0_CQCFG_MSPIFLGSEL_Msk         (0xcUL)                   /*!< MSPIFLGSEL (Bitfield-Mask: 0x03)                      */
40804 #define IOM0_CQCFG_CQPRI_Pos              (1UL)                     /*!< CQPRI (Bit 1)                                         */
40805 #define IOM0_CQCFG_CQPRI_Msk              (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
40806 #define IOM0_CQCFG_CQEN_Pos               (0UL)                     /*!< CQEN (Bit 0)                                          */
40807 #define IOM0_CQCFG_CQEN_Msk               (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
40808 /* ========================================================  CQADDR  ========================================================= */
40809 #define IOM0_CQADDR_CQADDR_Pos            (2UL)                     /*!< CQADDR (Bit 2)                                        */
40810 #define IOM0_CQADDR_CQADDR_Msk            (0x1ffffffcUL)            /*!< CQADDR (Bitfield-Mask: 0x7ffffff)                     */
40811 /* ========================================================  CQSTAT  ========================================================= */
40812 #define IOM0_CQSTAT_CQERR_Pos             (2UL)                     /*!< CQERR (Bit 2)                                         */
40813 #define IOM0_CQSTAT_CQERR_Msk             (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
40814 #define IOM0_CQSTAT_CQPAUSED_Pos          (1UL)                     /*!< CQPAUSED (Bit 1)                                      */
40815 #define IOM0_CQSTAT_CQPAUSED_Msk          (0x2UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
40816 #define IOM0_CQSTAT_CQTIP_Pos             (0UL)                     /*!< CQTIP (Bit 0)                                         */
40817 #define IOM0_CQSTAT_CQTIP_Msk             (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
40818 /* ========================================================  CQFLAGS  ======================================================== */
40819 #define IOM0_CQFLAGS_CQIRQMASK_Pos        (16UL)                    /*!< CQIRQMASK (Bit 16)                                    */
40820 #define IOM0_CQFLAGS_CQIRQMASK_Msk        (0xffff0000UL)            /*!< CQIRQMASK (Bitfield-Mask: 0xffff)                     */
40821 #define IOM0_CQFLAGS_CQFLAGS_Pos          (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
40822 #define IOM0_CQFLAGS_CQFLAGS_Msk          (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
40823 /* ======================================================  CQSETCLEAR  ======================================================= */
40824 #define IOM0_CQSETCLEAR_CQFCLR_Pos        (16UL)                    /*!< CQFCLR (Bit 16)                                       */
40825 #define IOM0_CQSETCLEAR_CQFCLR_Msk        (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
40826 #define IOM0_CQSETCLEAR_CQFTGL_Pos        (8UL)                     /*!< CQFTGL (Bit 8)                                        */
40827 #define IOM0_CQSETCLEAR_CQFTGL_Msk        (0xff00UL)                /*!< CQFTGL (Bitfield-Mask: 0xff)                          */
40828 #define IOM0_CQSETCLEAR_CQFSET_Pos        (0UL)                     /*!< CQFSET (Bit 0)                                        */
40829 #define IOM0_CQSETCLEAR_CQFSET_Msk        (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
40830 /* =======================================================  CQPAUSEEN  ======================================================= */
40831 #define IOM0_CQPAUSEEN_CQPEN_Pos          (0UL)                     /*!< CQPEN (Bit 0)                                         */
40832 #define IOM0_CQPAUSEEN_CQPEN_Msk          (0xffffUL)                /*!< CQPEN (Bitfield-Mask: 0xffff)                         */
40833 /* =======================================================  CQCURIDX  ======================================================== */
40834 #define IOM0_CQCURIDX_CQCURIDX_Pos        (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
40835 #define IOM0_CQCURIDX_CQCURIDX_Msk        (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
40836 /* =======================================================  CQENDIDX  ======================================================== */
40837 #define IOM0_CQENDIDX_CQENDIDX_Pos        (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
40838 #define IOM0_CQENDIDX_CQENDIDX_Msk        (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
40839 /* ========================================================  STATUS  ========================================================= */
40840 #define IOM0_STATUS_IDLEST_Pos            (2UL)                     /*!< IDLEST (Bit 2)                                        */
40841 #define IOM0_STATUS_IDLEST_Msk            (0x4UL)                   /*!< IDLEST (Bitfield-Mask: 0x01)                          */
40842 #define IOM0_STATUS_CMDACT_Pos            (1UL)                     /*!< CMDACT (Bit 1)                                        */
40843 #define IOM0_STATUS_CMDACT_Msk            (0x2UL)                   /*!< CMDACT (Bitfield-Mask: 0x01)                          */
40844 #define IOM0_STATUS_ERR_Pos               (0UL)                     /*!< ERR (Bit 0)                                           */
40845 #define IOM0_STATUS_ERR_Msk               (0x1UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */
40846 /* ========================================================  MSPICFG  ======================================================== */
40847 #define IOM0_MSPICFG_MSPIRST_Pos          (30UL)                    /*!< MSPIRST (Bit 30)                                      */
40848 #define IOM0_MSPICFG_MSPIRST_Msk          (0x40000000UL)            /*!< MSPIRST (Bitfield-Mask: 0x01)                         */
40849 #define IOM0_MSPICFG_DOUTDLY_Pos          (27UL)                    /*!< DOUTDLY (Bit 27)                                      */
40850 #define IOM0_MSPICFG_DOUTDLY_Msk          (0x38000000UL)            /*!< DOUTDLY (Bitfield-Mask: 0x07)                         */
40851 #define IOM0_MSPICFG_DINDLY_Pos           (24UL)                    /*!< DINDLY (Bit 24)                                       */
40852 #define IOM0_MSPICFG_DINDLY_Msk           (0x7000000UL)             /*!< DINDLY (Bitfield-Mask: 0x07)                          */
40853 #define IOM0_MSPICFG_SPILSB_Pos           (23UL)                    /*!< SPILSB (Bit 23)                                       */
40854 #define IOM0_MSPICFG_SPILSB_Msk           (0x800000UL)              /*!< SPILSB (Bitfield-Mask: 0x01)                          */
40855 #define IOM0_MSPICFG_RDFCPOL_Pos          (22UL)                    /*!< RDFCPOL (Bit 22)                                      */
40856 #define IOM0_MSPICFG_RDFCPOL_Msk          (0x400000UL)              /*!< RDFCPOL (Bitfield-Mask: 0x01)                         */
40857 #define IOM0_MSPICFG_WTFCPOL_Pos          (21UL)                    /*!< WTFCPOL (Bit 21)                                      */
40858 #define IOM0_MSPICFG_WTFCPOL_Msk          (0x200000UL)              /*!< WTFCPOL (Bitfield-Mask: 0x01)                         */
40859 #define IOM0_MSPICFG_WTFCIRQ_Pos          (20UL)                    /*!< WTFCIRQ (Bit 20)                                      */
40860 #define IOM0_MSPICFG_WTFCIRQ_Msk          (0x100000UL)              /*!< WTFCIRQ (Bitfield-Mask: 0x01)                         */
40861 #define IOM0_MSPICFG_MOSIINV_Pos          (18UL)                    /*!< MOSIINV (Bit 18)                                      */
40862 #define IOM0_MSPICFG_MOSIINV_Msk          (0x40000UL)               /*!< MOSIINV (Bitfield-Mask: 0x01)                         */
40863 #define IOM0_MSPICFG_RDFC_Pos             (17UL)                    /*!< RDFC (Bit 17)                                         */
40864 #define IOM0_MSPICFG_RDFC_Msk             (0x20000UL)               /*!< RDFC (Bitfield-Mask: 0x01)                            */
40865 #define IOM0_MSPICFG_WTFC_Pos             (16UL)                    /*!< WTFC (Bit 16)                                         */
40866 #define IOM0_MSPICFG_WTFC_Msk             (0x10000UL)               /*!< WTFC (Bitfield-Mask: 0x01)                            */
40867 #define IOM0_MSPICFG_FULLDUP_Pos          (2UL)                     /*!< FULLDUP (Bit 2)                                       */
40868 #define IOM0_MSPICFG_FULLDUP_Msk          (0x4UL)                   /*!< FULLDUP (Bitfield-Mask: 0x01)                         */
40869 #define IOM0_MSPICFG_SPHA_Pos             (1UL)                     /*!< SPHA (Bit 1)                                          */
40870 #define IOM0_MSPICFG_SPHA_Msk             (0x2UL)                   /*!< SPHA (Bitfield-Mask: 0x01)                            */
40871 #define IOM0_MSPICFG_SPOL_Pos             (0UL)                     /*!< SPOL (Bit 0)                                          */
40872 #define IOM0_MSPICFG_SPOL_Msk             (0x1UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
40873 /* ========================================================  MI2CCFG  ======================================================== */
40874 #define IOM0_MI2CCFG_STRDIS_Pos           (24UL)                    /*!< STRDIS (Bit 24)                                       */
40875 #define IOM0_MI2CCFG_STRDIS_Msk           (0x1000000UL)             /*!< STRDIS (Bitfield-Mask: 0x01)                          */
40876 #define IOM0_MI2CCFG_SMPCNT_Pos           (16UL)                    /*!< SMPCNT (Bit 16)                                       */
40877 #define IOM0_MI2CCFG_SMPCNT_Msk           (0xff0000UL)              /*!< SMPCNT (Bitfield-Mask: 0xff)                          */
40878 #define IOM0_MI2CCFG_SDAENDLY_Pos         (12UL)                    /*!< SDAENDLY (Bit 12)                                     */
40879 #define IOM0_MI2CCFG_SDAENDLY_Msk         (0xf000UL)                /*!< SDAENDLY (Bitfield-Mask: 0x0f)                        */
40880 #define IOM0_MI2CCFG_SCLENDLY_Pos         (8UL)                     /*!< SCLENDLY (Bit 8)                                      */
40881 #define IOM0_MI2CCFG_SCLENDLY_Msk         (0xf00UL)                 /*!< SCLENDLY (Bitfield-Mask: 0x0f)                        */
40882 #define IOM0_MI2CCFG_MI2CRST_Pos          (6UL)                     /*!< MI2CRST (Bit 6)                                       */
40883 #define IOM0_MI2CCFG_MI2CRST_Msk          (0x40UL)                  /*!< MI2CRST (Bitfield-Mask: 0x01)                         */
40884 #define IOM0_MI2CCFG_SDADLY_Pos           (4UL)                     /*!< SDADLY (Bit 4)                                        */
40885 #define IOM0_MI2CCFG_SDADLY_Msk           (0x30UL)                  /*!< SDADLY (Bitfield-Mask: 0x03)                          */
40886 #define IOM0_MI2CCFG_ARBEN_Pos            (2UL)                     /*!< ARBEN (Bit 2)                                         */
40887 #define IOM0_MI2CCFG_ARBEN_Msk            (0x4UL)                   /*!< ARBEN (Bitfield-Mask: 0x01)                           */
40888 #define IOM0_MI2CCFG_I2CLSB_Pos           (1UL)                     /*!< I2CLSB (Bit 1)                                        */
40889 #define IOM0_MI2CCFG_I2CLSB_Msk           (0x2UL)                   /*!< I2CLSB (Bitfield-Mask: 0x01)                          */
40890 #define IOM0_MI2CCFG_ADDRSZ_Pos           (0UL)                     /*!< ADDRSZ (Bit 0)                                        */
40891 #define IOM0_MI2CCFG_ADDRSZ_Msk           (0x1UL)                   /*!< ADDRSZ (Bitfield-Mask: 0x01)                          */
40892 /* ========================================================  DEVCFG  ========================================================= */
40893 #define IOM0_DEVCFG_DEVADDR_Pos           (0UL)                     /*!< DEVADDR (Bit 0)                                       */
40894 #define IOM0_DEVCFG_DEVADDR_Msk           (0x3ffUL)                 /*!< DEVADDR (Bitfield-Mask: 0x3ff)                        */
40895 /* ========================================================  IOMDBG  ========================================================= */
40896 #define IOM0_IOMDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
40897 #define IOM0_IOMDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
40898 #define IOM0_IOMDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
40899 #define IOM0_IOMDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
40900 #define IOM0_IOMDBG_IOCLKON_Pos           (1UL)                     /*!< IOCLKON (Bit 1)                                       */
40901 #define IOM0_IOMDBG_IOCLKON_Msk           (0x2UL)                   /*!< IOCLKON (Bitfield-Mask: 0x01)                         */
40902 #define IOM0_IOMDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
40903 #define IOM0_IOMDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
40904 
40905 
40906 /* =========================================================================================================================== */
40907 /* ================                                          IOSLAVE                                          ================ */
40908 /* =========================================================================================================================== */
40909 
40910 /* ========================================================  FIFOPTR  ======================================================== */
40911 #define IOSLAVE_FIFOPTR_FIFOSIZ_Pos       (8UL)                     /*!< FIFOSIZ (Bit 8)                                       */
40912 #define IOSLAVE_FIFOPTR_FIFOSIZ_Msk       (0xff00UL)                /*!< FIFOSIZ (Bitfield-Mask: 0xff)                         */
40913 #define IOSLAVE_FIFOPTR_FIFOPTR_Pos       (0UL)                     /*!< FIFOPTR (Bit 0)                                       */
40914 #define IOSLAVE_FIFOPTR_FIFOPTR_Msk       (0xffUL)                  /*!< FIFOPTR (Bitfield-Mask: 0xff)                         */
40915 /* ========================================================  FIFOCFG  ======================================================== */
40916 #define IOSLAVE_FIFOCFG_ROBASE_Pos        (24UL)                    /*!< ROBASE (Bit 24)                                       */
40917 #define IOSLAVE_FIFOCFG_ROBASE_Msk        (0x3f000000UL)            /*!< ROBASE (Bitfield-Mask: 0x3f)                          */
40918 #define IOSLAVE_FIFOCFG_FIFOMAX_Pos       (8UL)                     /*!< FIFOMAX (Bit 8)                                       */
40919 #define IOSLAVE_FIFOCFG_FIFOMAX_Msk       (0x3f00UL)                /*!< FIFOMAX (Bitfield-Mask: 0x3f)                         */
40920 #define IOSLAVE_FIFOCFG_FIFOBASE_Pos      (0UL)                     /*!< FIFOBASE (Bit 0)                                      */
40921 #define IOSLAVE_FIFOCFG_FIFOBASE_Msk      (0x1fUL)                  /*!< FIFOBASE (Bitfield-Mask: 0x1f)                        */
40922 /* ========================================================  FIFOTHR  ======================================================== */
40923 #define IOSLAVE_FIFOTHR_FIFOTHR_Pos       (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
40924 #define IOSLAVE_FIFOTHR_FIFOTHR_Msk       (0xffUL)                  /*!< FIFOTHR (Bitfield-Mask: 0xff)                         */
40925 /* =========================================================  FUPD  ========================================================== */
40926 #define IOSLAVE_FUPD_IOREAD_Pos           (1UL)                     /*!< IOREAD (Bit 1)                                        */
40927 #define IOSLAVE_FUPD_IOREAD_Msk           (0x2UL)                   /*!< IOREAD (Bitfield-Mask: 0x01)                          */
40928 #define IOSLAVE_FUPD_FIFOUPD_Pos          (0UL)                     /*!< FIFOUPD (Bit 0)                                       */
40929 #define IOSLAVE_FUPD_FIFOUPD_Msk          (0x1UL)                   /*!< FIFOUPD (Bitfield-Mask: 0x01)                         */
40930 /* ========================================================  FIFOCTR  ======================================================== */
40931 #define IOSLAVE_FIFOCTR_FIFOCTR_Pos       (0UL)                     /*!< FIFOCTR (Bit 0)                                       */
40932 #define IOSLAVE_FIFOCTR_FIFOCTR_Msk       (0x3ffUL)                 /*!< FIFOCTR (Bitfield-Mask: 0x3ff)                        */
40933 /* ========================================================  FIFOINC  ======================================================== */
40934 #define IOSLAVE_FIFOINC_FIFOINC_Pos       (0UL)                     /*!< FIFOINC (Bit 0)                                       */
40935 #define IOSLAVE_FIFOINC_FIFOINC_Msk       (0x3ffUL)                 /*!< FIFOINC (Bitfield-Mask: 0x3ff)                        */
40936 /* ==========================================================  CFG  ========================================================== */
40937 #define IOSLAVE_CFG_IFCEN_Pos             (31UL)                    /*!< IFCEN (Bit 31)                                        */
40938 #define IOSLAVE_CFG_IFCEN_Msk             (0x80000000UL)            /*!< IFCEN (Bitfield-Mask: 0x01)                           */
40939 #define IOSLAVE_CFG_WRAPPTR_Pos           (20UL)                    /*!< WRAPPTR (Bit 20)                                      */
40940 #define IOSLAVE_CFG_WRAPPTR_Msk           (0x100000UL)              /*!< WRAPPTR (Bitfield-Mask: 0x01)                         */
40941 #define IOSLAVE_CFG_I2CADDR_Pos           (8UL)                     /*!< I2CADDR (Bit 8)                                       */
40942 #define IOSLAVE_CFG_I2CADDR_Msk           (0xfff00UL)               /*!< I2CADDR (Bitfield-Mask: 0xfff)                        */
40943 #define IOSLAVE_CFG_STARTRD_Pos           (4UL)                     /*!< STARTRD (Bit 4)                                       */
40944 #define IOSLAVE_CFG_STARTRD_Msk           (0x10UL)                  /*!< STARTRD (Bitfield-Mask: 0x01)                         */
40945 #define IOSLAVE_CFG_LSB_Pos               (2UL)                     /*!< LSB (Bit 2)                                           */
40946 #define IOSLAVE_CFG_LSB_Msk               (0x4UL)                   /*!< LSB (Bitfield-Mask: 0x01)                             */
40947 #define IOSLAVE_CFG_SPOL_Pos              (1UL)                     /*!< SPOL (Bit 1)                                          */
40948 #define IOSLAVE_CFG_SPOL_Msk              (0x2UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
40949 #define IOSLAVE_CFG_IFCSEL_Pos            (0UL)                     /*!< IFCSEL (Bit 0)                                        */
40950 #define IOSLAVE_CFG_IFCSEL_Msk            (0x1UL)                   /*!< IFCSEL (Bitfield-Mask: 0x01)                          */
40951 /* =========================================================  PRENC  ========================================================= */
40952 #define IOSLAVE_PRENC_PRENC_Pos           (0UL)                     /*!< PRENC (Bit 0)                                         */
40953 #define IOSLAVE_PRENC_PRENC_Msk           (0x1fUL)                  /*!< PRENC (Bitfield-Mask: 0x1f)                           */
40954 /* =======================================================  IOINTCTL  ======================================================== */
40955 #define IOSLAVE_IOINTCTL_IOINTSET_Pos     (24UL)                    /*!< IOINTSET (Bit 24)                                     */
40956 #define IOSLAVE_IOINTCTL_IOINTSET_Msk     (0xff000000UL)            /*!< IOINTSET (Bitfield-Mask: 0xff)                        */
40957 #define IOSLAVE_IOINTCTL_IOINTCLR_Pos     (16UL)                    /*!< IOINTCLR (Bit 16)                                     */
40958 #define IOSLAVE_IOINTCTL_IOINTCLR_Msk     (0x10000UL)               /*!< IOINTCLR (Bitfield-Mask: 0x01)                        */
40959 #define IOSLAVE_IOINTCTL_IOINT_Pos        (8UL)                     /*!< IOINT (Bit 8)                                         */
40960 #define IOSLAVE_IOINTCTL_IOINT_Msk        (0xff00UL)                /*!< IOINT (Bitfield-Mask: 0xff)                           */
40961 #define IOSLAVE_IOINTCTL_IOINTEN_Pos      (0UL)                     /*!< IOINTEN (Bit 0)                                       */
40962 #define IOSLAVE_IOINTCTL_IOINTEN_Msk      (0xffUL)                  /*!< IOINTEN (Bitfield-Mask: 0xff)                         */
40963 /* ========================================================  GENADD  ========================================================= */
40964 #define IOSLAVE_GENADD_GADATA_Pos         (0UL)                     /*!< GADATA (Bit 0)                                        */
40965 #define IOSLAVE_GENADD_GADATA_Msk         (0xffUL)                  /*!< GADATA (Bitfield-Mask: 0xff)                          */
40966 /* ========================================================  ADDPTR  ========================================================= */
40967 #define IOSLAVE_ADDPTR_ADDPTR_Pos         (0UL)                     /*!< ADDPTR (Bit 0)                                        */
40968 #define IOSLAVE_ADDPTR_ADDPTR_Msk         (0xffUL)                  /*!< ADDPTR (Bitfield-Mask: 0xff)                          */
40969 /* =========================================================  INTEN  ========================================================= */
40970 #define IOSLAVE_INTEN_XCMPWR_Pos          (9UL)                     /*!< XCMPWR (Bit 9)                                        */
40971 #define IOSLAVE_INTEN_XCMPWR_Msk          (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
40972 #define IOSLAVE_INTEN_XCMPWF_Pos          (8UL)                     /*!< XCMPWF (Bit 8)                                        */
40973 #define IOSLAVE_INTEN_XCMPWF_Msk          (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
40974 #define IOSLAVE_INTEN_XCMPRR_Pos          (7UL)                     /*!< XCMPRR (Bit 7)                                        */
40975 #define IOSLAVE_INTEN_XCMPRR_Msk          (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
40976 #define IOSLAVE_INTEN_XCMPRF_Pos          (6UL)                     /*!< XCMPRF (Bit 6)                                        */
40977 #define IOSLAVE_INTEN_XCMPRF_Msk          (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
40978 #define IOSLAVE_INTEN_IOINTW_Pos          (5UL)                     /*!< IOINTW (Bit 5)                                        */
40979 #define IOSLAVE_INTEN_IOINTW_Msk          (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
40980 #define IOSLAVE_INTEN_GENAD_Pos           (4UL)                     /*!< GENAD (Bit 4)                                         */
40981 #define IOSLAVE_INTEN_GENAD_Msk           (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
40982 #define IOSLAVE_INTEN_FRDERR_Pos          (3UL)                     /*!< FRDERR (Bit 3)                                        */
40983 #define IOSLAVE_INTEN_FRDERR_Msk          (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
40984 #define IOSLAVE_INTEN_FUNDFL_Pos          (2UL)                     /*!< FUNDFL (Bit 2)                                        */
40985 #define IOSLAVE_INTEN_FUNDFL_Msk          (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
40986 #define IOSLAVE_INTEN_FOVFL_Pos           (1UL)                     /*!< FOVFL (Bit 1)                                         */
40987 #define IOSLAVE_INTEN_FOVFL_Msk           (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
40988 #define IOSLAVE_INTEN_FSIZE_Pos           (0UL)                     /*!< FSIZE (Bit 0)                                         */
40989 #define IOSLAVE_INTEN_FSIZE_Msk           (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
40990 /* ========================================================  INTSTAT  ======================================================== */
40991 #define IOSLAVE_INTSTAT_XCMPWR_Pos        (9UL)                     /*!< XCMPWR (Bit 9)                                        */
40992 #define IOSLAVE_INTSTAT_XCMPWR_Msk        (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
40993 #define IOSLAVE_INTSTAT_XCMPWF_Pos        (8UL)                     /*!< XCMPWF (Bit 8)                                        */
40994 #define IOSLAVE_INTSTAT_XCMPWF_Msk        (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
40995 #define IOSLAVE_INTSTAT_XCMPRR_Pos        (7UL)                     /*!< XCMPRR (Bit 7)                                        */
40996 #define IOSLAVE_INTSTAT_XCMPRR_Msk        (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
40997 #define IOSLAVE_INTSTAT_XCMPRF_Pos        (6UL)                     /*!< XCMPRF (Bit 6)                                        */
40998 #define IOSLAVE_INTSTAT_XCMPRF_Msk        (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
40999 #define IOSLAVE_INTSTAT_IOINTW_Pos        (5UL)                     /*!< IOINTW (Bit 5)                                        */
41000 #define IOSLAVE_INTSTAT_IOINTW_Msk        (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
41001 #define IOSLAVE_INTSTAT_GENAD_Pos         (4UL)                     /*!< GENAD (Bit 4)                                         */
41002 #define IOSLAVE_INTSTAT_GENAD_Msk         (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
41003 #define IOSLAVE_INTSTAT_FRDERR_Pos        (3UL)                     /*!< FRDERR (Bit 3)                                        */
41004 #define IOSLAVE_INTSTAT_FRDERR_Msk        (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
41005 #define IOSLAVE_INTSTAT_FUNDFL_Pos        (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41006 #define IOSLAVE_INTSTAT_FUNDFL_Msk        (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41007 #define IOSLAVE_INTSTAT_FOVFL_Pos         (1UL)                     /*!< FOVFL (Bit 1)                                         */
41008 #define IOSLAVE_INTSTAT_FOVFL_Msk         (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41009 #define IOSLAVE_INTSTAT_FSIZE_Pos         (0UL)                     /*!< FSIZE (Bit 0)                                         */
41010 #define IOSLAVE_INTSTAT_FSIZE_Msk         (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
41011 /* ========================================================  INTCLR  ========================================================= */
41012 #define IOSLAVE_INTCLR_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
41013 #define IOSLAVE_INTCLR_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
41014 #define IOSLAVE_INTCLR_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
41015 #define IOSLAVE_INTCLR_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
41016 #define IOSLAVE_INTCLR_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
41017 #define IOSLAVE_INTCLR_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
41018 #define IOSLAVE_INTCLR_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
41019 #define IOSLAVE_INTCLR_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
41020 #define IOSLAVE_INTCLR_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
41021 #define IOSLAVE_INTCLR_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
41022 #define IOSLAVE_INTCLR_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
41023 #define IOSLAVE_INTCLR_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
41024 #define IOSLAVE_INTCLR_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
41025 #define IOSLAVE_INTCLR_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
41026 #define IOSLAVE_INTCLR_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41027 #define IOSLAVE_INTCLR_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41028 #define IOSLAVE_INTCLR_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
41029 #define IOSLAVE_INTCLR_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41030 #define IOSLAVE_INTCLR_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
41031 #define IOSLAVE_INTCLR_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
41032 /* ========================================================  INTSET  ========================================================= */
41033 #define IOSLAVE_INTSET_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
41034 #define IOSLAVE_INTSET_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
41035 #define IOSLAVE_INTSET_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
41036 #define IOSLAVE_INTSET_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
41037 #define IOSLAVE_INTSET_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
41038 #define IOSLAVE_INTSET_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
41039 #define IOSLAVE_INTSET_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
41040 #define IOSLAVE_INTSET_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
41041 #define IOSLAVE_INTSET_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
41042 #define IOSLAVE_INTSET_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
41043 #define IOSLAVE_INTSET_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
41044 #define IOSLAVE_INTSET_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
41045 #define IOSLAVE_INTSET_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
41046 #define IOSLAVE_INTSET_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
41047 #define IOSLAVE_INTSET_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41048 #define IOSLAVE_INTSET_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41049 #define IOSLAVE_INTSET_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
41050 #define IOSLAVE_INTSET_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41051 #define IOSLAVE_INTSET_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
41052 #define IOSLAVE_INTSET_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
41053 /* ======================================================  REGACCINTEN  ====================================================== */
41054 #define IOSLAVE_REGACCINTEN_REGACC_Pos    (0UL)                     /*!< REGACC (Bit 0)                                        */
41055 #define IOSLAVE_REGACCINTEN_REGACC_Msk    (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41056 /* =====================================================  REGACCINTSTAT  ===================================================== */
41057 #define IOSLAVE_REGACCINTSTAT_REGACC_Pos  (0UL)                     /*!< REGACC (Bit 0)                                        */
41058 #define IOSLAVE_REGACCINTSTAT_REGACC_Msk  (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41059 /* =====================================================  REGACCINTCLR  ====================================================== */
41060 #define IOSLAVE_REGACCINTCLR_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
41061 #define IOSLAVE_REGACCINTCLR_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41062 /* =====================================================  REGACCINTSET  ====================================================== */
41063 #define IOSLAVE_REGACCINTSET_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
41064 #define IOSLAVE_REGACCINTSET_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41065 
41066 
41067 /* =========================================================================================================================== */
41068 /* ================                                          MCUCTRL                                          ================ */
41069 /* =========================================================================================================================== */
41070 
41071 /* ========================================================  CHIPPN  ========================================================= */
41072 #define MCUCTRL_CHIPPN_PARTNUM_Pos        (0UL)                     /*!< PARTNUM (Bit 0)                                       */
41073 #define MCUCTRL_CHIPPN_PARTNUM_Msk        (0xffffffffUL)            /*!< PARTNUM (Bitfield-Mask: 0xffffffff)                   */
41074 /* ========================================================  CHIPID0  ======================================================== */
41075 #define MCUCTRL_CHIPID0_CHIPID0_Pos       (0UL)                     /*!< CHIPID0 (Bit 0)                                       */
41076 #define MCUCTRL_CHIPID0_CHIPID0_Msk       (0xffffffffUL)            /*!< CHIPID0 (Bitfield-Mask: 0xffffffff)                   */
41077 /* ========================================================  CHIPID1  ======================================================== */
41078 #define MCUCTRL_CHIPID1_CHIPID1_Pos       (0UL)                     /*!< CHIPID1 (Bit 0)                                       */
41079 #define MCUCTRL_CHIPID1_CHIPID1_Msk       (0xffffffffUL)            /*!< CHIPID1 (Bitfield-Mask: 0xffffffff)                   */
41080 /* ========================================================  CHIPREV  ======================================================== */
41081 #define MCUCTRL_CHIPREV_SIPART_Pos        (8UL)                     /*!< SIPART (Bit 8)                                        */
41082 #define MCUCTRL_CHIPREV_SIPART_Msk        (0xfff00UL)               /*!< SIPART (Bitfield-Mask: 0xfff)                         */
41083 #define MCUCTRL_CHIPREV_REVMAJ_Pos        (4UL)                     /*!< REVMAJ (Bit 4)                                        */
41084 #define MCUCTRL_CHIPREV_REVMAJ_Msk        (0xf0UL)                  /*!< REVMAJ (Bitfield-Mask: 0x0f)                          */
41085 #define MCUCTRL_CHIPREV_REVMIN_Pos        (0UL)                     /*!< REVMIN (Bit 0)                                        */
41086 #define MCUCTRL_CHIPREV_REVMIN_Msk        (0xfUL)                   /*!< REVMIN (Bitfield-Mask: 0x0f)                          */
41087 /* =======================================================  VENDORID  ======================================================== */
41088 #define MCUCTRL_VENDORID_VENDORID_Pos     (0UL)                     /*!< VENDORID (Bit 0)                                      */
41089 #define MCUCTRL_VENDORID_VENDORID_Msk     (0xffffffffUL)            /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
41090 /* ==========================================================  SKU  ========================================================== */
41091 #define MCUCTRL_SKU_SKUSECURESPOT_Pos     (10UL)                    /*!< SKUSECURESPOT (Bit 10)                                */
41092 #define MCUCTRL_SKU_SKUSECURESPOT_Msk     (0x400UL)                 /*!< SKUSECURESPOT (Bitfield-Mask: 0x01)                   */
41093 #define MCUCTRL_SKU_SKUUSB_Pos            (9UL)                     /*!< SKUUSB (Bit 9)                                        */
41094 #define MCUCTRL_SKU_SKUUSB_Msk            (0x200UL)                 /*!< SKUUSB (Bitfield-Mask: 0x01)                          */
41095 #define MCUCTRL_SKU_SKUGFX_Pos            (8UL)                     /*!< SKUGFX (Bit 8)                                        */
41096 #define MCUCTRL_SKU_SKUGFX_Msk            (0x100UL)                 /*!< SKUGFX (Bitfield-Mask: 0x01)                          */
41097 #define MCUCTRL_SKU_SKUMIPIDSI_Pos        (7UL)                     /*!< SKUMIPIDSI (Bit 7)                                    */
41098 #define MCUCTRL_SKU_SKUMIPIDSI_Msk        (0x80UL)                  /*!< SKUMIPIDSI (Bitfield-Mask: 0x01)                      */
41099 #define MCUCTRL_SKU_SKUTURBOSPOT_Pos      (6UL)                     /*!< SKUTURBOSPOT (Bit 6)                                  */
41100 #define MCUCTRL_SKU_SKUTURBOSPOT_Msk      (0x40UL)                  /*!< SKUTURBOSPOT (Bitfield-Mask: 0x01)                    */
41101 #define MCUCTRL_SKU_SKUDSP_Pos            (4UL)                     /*!< SKUDSP (Bit 4)                                        */
41102 #define MCUCTRL_SKU_SKUDSP_Msk            (0x30UL)                  /*!< SKUDSP (Bitfield-Mask: 0x03)                          */
41103 #define MCUCTRL_SKU_SKUMRAMSIZE_Pos       (2UL)                     /*!< SKUMRAMSIZE (Bit 2)                                   */
41104 #define MCUCTRL_SKU_SKUMRAMSIZE_Msk       (0xcUL)                   /*!< SKUMRAMSIZE (Bitfield-Mask: 0x03)                     */
41105 #define MCUCTRL_SKU_SKUSRAMSIZE_Pos       (0UL)                     /*!< SKUSRAMSIZE (Bit 0)                                   */
41106 #define MCUCTRL_SKU_SKUSRAMSIZE_Msk       (0x3UL)                   /*!< SKUSRAMSIZE (Bitfield-Mask: 0x03)                     */
41107 /* =======================================================  DEBUGGER  ======================================================== */
41108 #define MCUCTRL_DEBUGGER_LOCKOUT_Pos      (0UL)                     /*!< LOCKOUT (Bit 0)                                       */
41109 #define MCUCTRL_DEBUGGER_LOCKOUT_Msk      (0xffffffffUL)            /*!< LOCKOUT (Bitfield-Mask: 0xffffffff)                   */
41110 /* =========================================================  ACRG  ========================================================== */
41111 #define MCUCTRL_ACRG_ACRGTRIM_Pos         (3UL)                     /*!< ACRGTRIM (Bit 3)                                      */
41112 #define MCUCTRL_ACRG_ACRGTRIM_Msk         (0xf8UL)                  /*!< ACRGTRIM (Bitfield-Mask: 0x1f)                        */
41113 #define MCUCTRL_ACRG_ACRGIBIASSEL_Pos     (2UL)                     /*!< ACRGIBIASSEL (Bit 2)                                  */
41114 #define MCUCTRL_ACRG_ACRGIBIASSEL_Msk     (0x4UL)                   /*!< ACRGIBIASSEL (Bitfield-Mask: 0x01)                    */
41115 #define MCUCTRL_ACRG_ACRGPWD_Pos          (1UL)                     /*!< ACRGPWD (Bit 1)                                       */
41116 #define MCUCTRL_ACRG_ACRGPWD_Msk          (0x2UL)                   /*!< ACRGPWD (Bitfield-Mask: 0x01)                         */
41117 #define MCUCTRL_ACRG_ACRGSWE_Pos          (0UL)                     /*!< ACRGSWE (Bit 0)                                       */
41118 #define MCUCTRL_ACRG_ACRGSWE_Msk          (0x1UL)                   /*!< ACRGSWE (Bitfield-Mask: 0x01)                         */
41119 /* =======================================================  VREFGEN2  ======================================================== */
41120 #define MCUCTRL_VREFGEN2_TVRG2SELVREF_Pos (29UL)                    /*!< TVRG2SELVREF (Bit 29)                                 */
41121 #define MCUCTRL_VREFGEN2_TVRG2SELVREF_Msk (0x20000000UL)            /*!< TVRG2SELVREF (Bitfield-Mask: 0x01)                    */
41122 #define MCUCTRL_VREFGEN2_TVRGSELVREF_Pos  (28UL)                    /*!< TVRGSELVREF (Bit 28)                                  */
41123 #define MCUCTRL_VREFGEN2_TVRGSELVREF_Msk  (0x10000000UL)            /*!< TVRGSELVREF (Bitfield-Mask: 0x01)                     */
41124 #define MCUCTRL_VREFGEN2_TVRG2VREFTRIM_Pos (21UL)                   /*!< TVRG2VREFTRIM (Bit 21)                                */
41125 #define MCUCTRL_VREFGEN2_TVRG2VREFTRIM_Msk (0xfe00000UL)            /*!< TVRG2VREFTRIM (Bitfield-Mask: 0x7f)                   */
41126 #define MCUCTRL_VREFGEN2_TVRG2CURRENTTRIM_Pos (20UL)                /*!< TVRG2CURRENTTRIM (Bit 20)                             */
41127 #define MCUCTRL_VREFGEN2_TVRG2CURRENTTRIM_Msk (0x100000UL)          /*!< TVRG2CURRENTTRIM (Bitfield-Mask: 0x01)                */
41128 #define MCUCTRL_VREFGEN2_TVRG2PWD_Pos     (19UL)                    /*!< TVRG2PWD (Bit 19)                                     */
41129 #define MCUCTRL_VREFGEN2_TVRG2PWD_Msk     (0x80000UL)               /*!< TVRG2PWD (Bitfield-Mask: 0x01)                        */
41130 #define MCUCTRL_VREFGEN2_TVRG2TEMPCOTRIM_Pos (14UL)                 /*!< TVRG2TEMPCOTRIM (Bit 14)                              */
41131 #define MCUCTRL_VREFGEN2_TVRG2TEMPCOTRIM_Msk (0x7c000UL)            /*!< TVRG2TEMPCOTRIM (Bitfield-Mask: 0x1f)                 */
41132 #define MCUCTRL_VREFGEN2_TVRGVREFTRIM_Pos (7UL)                     /*!< TVRGVREFTRIM (Bit 7)                                  */
41133 #define MCUCTRL_VREFGEN2_TVRGVREFTRIM_Msk (0x3f80UL)                /*!< TVRGVREFTRIM (Bitfield-Mask: 0x7f)                    */
41134 #define MCUCTRL_VREFGEN2_TVRGCURRENTTRIM_Pos (6UL)                  /*!< TVRGCURRENTTRIM (Bit 6)                               */
41135 #define MCUCTRL_VREFGEN2_TVRGCURRENTTRIM_Msk (0x40UL)               /*!< TVRGCURRENTTRIM (Bitfield-Mask: 0x01)                 */
41136 #define MCUCTRL_VREFGEN2_TVRGPWD_Pos      (5UL)                     /*!< TVRGPWD (Bit 5)                                       */
41137 #define MCUCTRL_VREFGEN2_TVRGPWD_Msk      (0x20UL)                  /*!< TVRGPWD (Bitfield-Mask: 0x01)                         */
41138 #define MCUCTRL_VREFGEN2_TVRGTEMPCOTRIM_Pos (0UL)                   /*!< TVRGTEMPCOTRIM (Bit 0)                                */
41139 #define MCUCTRL_VREFGEN2_TVRGTEMPCOTRIM_Msk (0x1fUL)                /*!< TVRGTEMPCOTRIM (Bitfield-Mask: 0x1f)                  */
41140 /* ========================================================  VRCTRL  ========================================================= */
41141 #define MCUCTRL_VRCTRL_SIMOBUCKACTIVE_Pos (19UL)                    /*!< SIMOBUCKACTIVE (Bit 19)                               */
41142 #define MCUCTRL_VRCTRL_SIMOBUCKACTIVE_Msk (0x80000UL)               /*!< SIMOBUCKACTIVE (Bitfield-Mask: 0x01)                  */
41143 #define MCUCTRL_VRCTRL_SIMOBUCKRSTB_Pos   (18UL)                    /*!< SIMOBUCKRSTB (Bit 18)                                 */
41144 #define MCUCTRL_VRCTRL_SIMOBUCKRSTB_Msk   (0x40000UL)               /*!< SIMOBUCKRSTB (Bitfield-Mask: 0x01)                    */
41145 #define MCUCTRL_VRCTRL_SIMOBUCKPDNB_Pos   (17UL)                    /*!< SIMOBUCKPDNB (Bit 17)                                 */
41146 #define MCUCTRL_VRCTRL_SIMOBUCKPDNB_Msk   (0x20000UL)               /*!< SIMOBUCKPDNB (Bitfield-Mask: 0x01)                    */
41147 #define MCUCTRL_VRCTRL_SIMOBUCKOVER_Pos   (16UL)                    /*!< SIMOBUCKOVER (Bit 16)                                 */
41148 #define MCUCTRL_VRCTRL_SIMOBUCKOVER_Msk   (0x10000UL)               /*!< SIMOBUCKOVER (Bitfield-Mask: 0x01)                    */
41149 #define MCUCTRL_VRCTRL_ANALDOACTIVE_Pos   (15UL)                    /*!< ANALDOACTIVE (Bit 15)                                 */
41150 #define MCUCTRL_VRCTRL_ANALDOACTIVE_Msk   (0x8000UL)                /*!< ANALDOACTIVE (Bitfield-Mask: 0x01)                    */
41151 #define MCUCTRL_VRCTRL_ANALDOPDNB_Pos     (14UL)                    /*!< ANALDOPDNB (Bit 14)                                   */
41152 #define MCUCTRL_VRCTRL_ANALDOPDNB_Msk     (0x4000UL)                /*!< ANALDOPDNB (Bitfield-Mask: 0x01)                      */
41153 #define MCUCTRL_VRCTRL_ANALDOOVER_Pos     (13UL)                    /*!< ANALDOOVER (Bit 13)                                   */
41154 #define MCUCTRL_VRCTRL_ANALDOOVER_Msk     (0x2000UL)                /*!< ANALDOOVER (Bitfield-Mask: 0x01)                      */
41155 #define MCUCTRL_VRCTRL_MEMLPLDOACTIVE_Pos (12UL)                    /*!< MEMLPLDOACTIVE (Bit 12)                               */
41156 #define MCUCTRL_VRCTRL_MEMLPLDOACTIVE_Msk (0x1000UL)                /*!< MEMLPLDOACTIVE (Bitfield-Mask: 0x01)                  */
41157 #define MCUCTRL_VRCTRL_MEMLPLDOPDNB_Pos   (11UL)                    /*!< MEMLPLDOPDNB (Bit 11)                                 */
41158 #define MCUCTRL_VRCTRL_MEMLPLDOPDNB_Msk   (0x800UL)                 /*!< MEMLPLDOPDNB (Bitfield-Mask: 0x01)                    */
41159 #define MCUCTRL_VRCTRL_MEMLPLDOOVER_Pos   (10UL)                    /*!< MEMLPLDOOVER (Bit 10)                                 */
41160 #define MCUCTRL_VRCTRL_MEMLPLDOOVER_Msk   (0x400UL)                 /*!< MEMLPLDOOVER (Bitfield-Mask: 0x01)                    */
41161 #define MCUCTRL_VRCTRL_MEMLDOCOLDSTARTEN_Pos (9UL)                  /*!< MEMLDOCOLDSTARTEN (Bit 9)                             */
41162 #define MCUCTRL_VRCTRL_MEMLDOCOLDSTARTEN_Msk (0x200UL)              /*!< MEMLDOCOLDSTARTEN (Bitfield-Mask: 0x01)               */
41163 #define MCUCTRL_VRCTRL_MEMLDOACTIVE_Pos   (8UL)                     /*!< MEMLDOACTIVE (Bit 8)                                  */
41164 #define MCUCTRL_VRCTRL_MEMLDOACTIVE_Msk   (0x100UL)                 /*!< MEMLDOACTIVE (Bitfield-Mask: 0x01)                    */
41165 #define MCUCTRL_VRCTRL_MEMLDOACTIVEEARLY_Pos (7UL)                  /*!< MEMLDOACTIVEEARLY (Bit 7)                             */
41166 #define MCUCTRL_VRCTRL_MEMLDOACTIVEEARLY_Msk (0x80UL)               /*!< MEMLDOACTIVEEARLY (Bitfield-Mask: 0x01)               */
41167 #define MCUCTRL_VRCTRL_MEMLDOPDNB_Pos     (6UL)                     /*!< MEMLDOPDNB (Bit 6)                                    */
41168 #define MCUCTRL_VRCTRL_MEMLDOPDNB_Msk     (0x40UL)                  /*!< MEMLDOPDNB (Bitfield-Mask: 0x01)                      */
41169 #define MCUCTRL_VRCTRL_MEMLDOOVER_Pos     (5UL)                     /*!< MEMLDOOVER (Bit 5)                                    */
41170 #define MCUCTRL_VRCTRL_MEMLDOOVER_Msk     (0x20UL)                  /*!< MEMLDOOVER (Bitfield-Mask: 0x01)                      */
41171 #define MCUCTRL_VRCTRL_CORELDOCOLDSTARTEN_Pos (4UL)                 /*!< CORELDOCOLDSTARTEN (Bit 4)                            */
41172 #define MCUCTRL_VRCTRL_CORELDOCOLDSTARTEN_Msk (0x10UL)              /*!< CORELDOCOLDSTARTEN (Bitfield-Mask: 0x01)              */
41173 #define MCUCTRL_VRCTRL_CORELDOACTIVE_Pos  (3UL)                     /*!< CORELDOACTIVE (Bit 3)                                 */
41174 #define MCUCTRL_VRCTRL_CORELDOACTIVE_Msk  (0x8UL)                   /*!< CORELDOACTIVE (Bitfield-Mask: 0x01)                   */
41175 #define MCUCTRL_VRCTRL_CORELDOACTIVEEARLY_Pos (2UL)                 /*!< CORELDOACTIVEEARLY (Bit 2)                            */
41176 #define MCUCTRL_VRCTRL_CORELDOACTIVEEARLY_Msk (0x4UL)               /*!< CORELDOACTIVEEARLY (Bitfield-Mask: 0x01)              */
41177 #define MCUCTRL_VRCTRL_CORELDOPDNB_Pos    (1UL)                     /*!< CORELDOPDNB (Bit 1)                                   */
41178 #define MCUCTRL_VRCTRL_CORELDOPDNB_Msk    (0x2UL)                   /*!< CORELDOPDNB (Bitfield-Mask: 0x01)                     */
41179 #define MCUCTRL_VRCTRL_CORELDOOVER_Pos    (0UL)                     /*!< CORELDOOVER (Bit 0)                                   */
41180 #define MCUCTRL_VRCTRL_CORELDOOVER_Msk    (0x1UL)                   /*!< CORELDOOVER (Bitfield-Mask: 0x01)                     */
41181 /* ========================================================  LDOREG1  ======================================================== */
41182 #define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Pos (21UL)                  /*!< CORELDOIBIASSEL (Bit 21)                              */
41183 #define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Msk (0x200000UL)            /*!< CORELDOIBIASSEL (Bitfield-Mask: 0x01)                 */
41184 #define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Pos (20UL)                 /*!< CORELDOIBIASTRIM (Bit 20)                             */
41185 #define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Msk (0x100000UL)           /*!< CORELDOIBIASTRIM (Bitfield-Mask: 0x01)                */
41186 #define MCUCTRL_LDOREG1_CORELDOLPTRIM_Pos (14UL)                    /*!< CORELDOLPTRIM (Bit 14)                                */
41187 #define MCUCTRL_LDOREG1_CORELDOLPTRIM_Msk (0xfc000UL)               /*!< CORELDOLPTRIM (Bitfield-Mask: 0x3f)                   */
41188 #define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Pos (10UL)                /*!< CORELDOTEMPCOTRIM (Bit 10)                            */
41189 #define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Msk (0x3c00UL)            /*!< CORELDOTEMPCOTRIM (Bitfield-Mask: 0x0f)               */
41190 #define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Pos (0UL)                 /*!< CORELDOACTIVETRIM (Bit 0)                             */
41191 #define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Msk (0x3ffUL)             /*!< CORELDOACTIVETRIM (Bitfield-Mask: 0x3ff)              */
41192 /* ========================================================  LDOREG2  ======================================================== */
41193 #define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Pos  (18UL)                    /*!< MEMLPLDOTRIM (Bit 18)                                 */
41194 #define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Msk  (0xfc0000UL)              /*!< MEMLPLDOTRIM (Bitfield-Mask: 0x3f)                    */
41195 #define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Pos (0UL)                  /*!< MEMLDOACTIVETRIM (Bit 0)                              */
41196 #define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Msk (0x3fUL)               /*!< MEMLDOACTIVETRIM (Bitfield-Mask: 0x3f)                */
41197 /* =========================================================  LFRC  ========================================================== */
41198 #define MCUCTRL_LFRC_LFRCSIMOCLKDIV_Pos   (10UL)                    /*!< LFRCSIMOCLKDIV (Bit 10)                               */
41199 #define MCUCTRL_LFRC_LFRCSIMOCLKDIV_Msk   (0x1c00UL)                /*!< LFRCSIMOCLKDIV (Bitfield-Mask: 0x07)                  */
41200 #define MCUCTRL_LFRC_LFRCITAILTRIM_Pos    (8UL)                     /*!< LFRCITAILTRIM (Bit 8)                                 */
41201 #define MCUCTRL_LFRC_LFRCITAILTRIM_Msk    (0x300UL)                 /*!< LFRCITAILTRIM (Bitfield-Mask: 0x03)                   */
41202 #define MCUCTRL_LFRC_RESETLFRC_Pos        (7UL)                     /*!< RESETLFRC (Bit 7)                                     */
41203 #define MCUCTRL_LFRC_RESETLFRC_Msk        (0x80UL)                  /*!< RESETLFRC (Bitfield-Mask: 0x01)                       */
41204 #define MCUCTRL_LFRC_PWDLFRC_Pos          (6UL)                     /*!< PWDLFRC (Bit 6)                                       */
41205 #define MCUCTRL_LFRC_PWDLFRC_Msk          (0x40UL)                  /*!< PWDLFRC (Bitfield-Mask: 0x01)                         */
41206 #define MCUCTRL_LFRC_TRIMTUNELFRC_Pos     (1UL)                     /*!< TRIMTUNELFRC (Bit 1)                                  */
41207 #define MCUCTRL_LFRC_TRIMTUNELFRC_Msk     (0x3eUL)                  /*!< TRIMTUNELFRC (Bitfield-Mask: 0x1f)                    */
41208 #define MCUCTRL_LFRC_LFRCSWE_Pos          (0UL)                     /*!< LFRCSWE (Bit 0)                                       */
41209 #define MCUCTRL_LFRC_LFRCSWE_Msk          (0x1UL)                   /*!< LFRCSWE (Bitfield-Mask: 0x01)                         */
41210 /* ========================================================  BODCTRL  ======================================================== */
41211 #define MCUCTRL_BODCTRL_BODHVREFSEL_Pos   (7UL)                     /*!< BODHVREFSEL (Bit 7)                                   */
41212 #define MCUCTRL_BODCTRL_BODHVREFSEL_Msk   (0x80UL)                  /*!< BODHVREFSEL (Bitfield-Mask: 0x01)                     */
41213 #define MCUCTRL_BODCTRL_BODLVREFSEL_Pos   (6UL)                     /*!< BODLVREFSEL (Bit 6)                                   */
41214 #define MCUCTRL_BODCTRL_BODLVREFSEL_Msk   (0x40UL)                  /*!< BODLVREFSEL (Bitfield-Mask: 0x01)                     */
41215 #define MCUCTRL_BODCTRL_BODCLVPWD_Pos     (5UL)                     /*!< BODCLVPWD (Bit 5)                                     */
41216 #define MCUCTRL_BODCTRL_BODCLVPWD_Msk     (0x20UL)                  /*!< BODCLVPWD (Bitfield-Mask: 0x01)                       */
41217 #define MCUCTRL_BODCTRL_BODSPWD_Pos       (4UL)                     /*!< BODSPWD (Bit 4)                                       */
41218 #define MCUCTRL_BODCTRL_BODSPWD_Msk       (0x10UL)                  /*!< BODSPWD (Bitfield-Mask: 0x01)                         */
41219 #define MCUCTRL_BODCTRL_BODFPWD_Pos       (3UL)                     /*!< BODFPWD (Bit 3)                                       */
41220 #define MCUCTRL_BODCTRL_BODFPWD_Msk       (0x8UL)                   /*!< BODFPWD (Bitfield-Mask: 0x01)                         */
41221 #define MCUCTRL_BODCTRL_BODCPWD_Pos       (2UL)                     /*!< BODCPWD (Bit 2)                                       */
41222 #define MCUCTRL_BODCTRL_BODCPWD_Msk       (0x4UL)                   /*!< BODCPWD (Bitfield-Mask: 0x01)                         */
41223 #define MCUCTRL_BODCTRL_BODHPWD_Pos       (1UL)                     /*!< BODHPWD (Bit 1)                                       */
41224 #define MCUCTRL_BODCTRL_BODHPWD_Msk       (0x2UL)                   /*!< BODHPWD (Bitfield-Mask: 0x01)                         */
41225 #define MCUCTRL_BODCTRL_BODLPWD_Pos       (0UL)                     /*!< BODLPWD (Bit 0)                                       */
41226 #define MCUCTRL_BODCTRL_BODLPWD_Msk       (0x1UL)                   /*!< BODLPWD (Bitfield-Mask: 0x01)                         */
41227 /* =======================================================  ADCPWRDLY  ======================================================= */
41228 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos     (8UL)                     /*!< ADCPWR1 (Bit 8)                                       */
41229 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk     (0xff00UL)                /*!< ADCPWR1 (Bitfield-Mask: 0xff)                         */
41230 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos     (0UL)                     /*!< ADCPWR0 (Bit 0)                                       */
41231 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk     (0xffUL)                  /*!< ADCPWR0 (Bitfield-Mask: 0xff)                         */
41232 /* ======================================================  ADCPWRCTRL  ======================================================= */
41233 #define MCUCTRL_ADCPWRCTRL_ADCKEEPOUTEN_Pos (16UL)                  /*!< ADCKEEPOUTEN (Bit 16)                                 */
41234 #define MCUCTRL_ADCPWRCTRL_ADCKEEPOUTEN_Msk (0x10000UL)             /*!< ADCKEEPOUTEN (Bitfield-Mask: 0x01)                    */
41235 #define MCUCTRL_ADCPWRCTRL_ADCRFBUFSLWEN_Pos (15UL)                 /*!< ADCRFBUFSLWEN (Bit 15)                                */
41236 #define MCUCTRL_ADCPWRCTRL_ADCRFBUFSLWEN_Msk (0x8000UL)             /*!< ADCRFBUFSLWEN (Bitfield-Mask: 0x01)                   */
41237 #define MCUCTRL_ADCPWRCTRL_ADCINBUFEN_Pos (14UL)                    /*!< ADCINBUFEN (Bit 14)                                   */
41238 #define MCUCTRL_ADCPWRCTRL_ADCINBUFEN_Msk (0x4000UL)                /*!< ADCINBUFEN (Bitfield-Mask: 0x01)                      */
41239 #define MCUCTRL_ADCPWRCTRL_ADCINBUFSEL_Pos (12UL)                   /*!< ADCINBUFSEL (Bit 12)                                  */
41240 #define MCUCTRL_ADCPWRCTRL_ADCINBUFSEL_Msk (0x3000UL)               /*!< ADCINBUFSEL (Bitfield-Mask: 0x03)                     */
41241 #define MCUCTRL_ADCPWRCTRL_ADCVBATDIVEN_Pos (11UL)                  /*!< ADCVBATDIVEN (Bit 11)                                 */
41242 #define MCUCTRL_ADCPWRCTRL_ADCVBATDIVEN_Msk (0x800UL)               /*!< ADCVBATDIVEN (Bitfield-Mask: 0x01)                    */
41243 #define MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Pos (9UL)                   /*!< VDDADCRESETN (Bit 9)                                  */
41244 #define MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Msk (0x200UL)               /*!< VDDADCRESETN (Bitfield-Mask: 0x01)                    */
41245 #define MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Pos (8UL)               /*!< VDDADCDIGISOLATE (Bit 8)                              */
41246 #define MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Msk (0x100UL)           /*!< VDDADCDIGISOLATE (Bitfield-Mask: 0x01)                */
41247 #define MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Pos (7UL)               /*!< VDDADCSARISOLATE (Bit 7)                              */
41248 #define MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Msk (0x80UL)            /*!< VDDADCSARISOLATE (Bitfield-Mask: 0x01)                */
41249 #define MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Pos (6UL)                     /*!< REFKEEPPEN (Bit 6)                                    */
41250 #define MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Msk (0x40UL)                  /*!< REFKEEPPEN (Bitfield-Mask: 0x01)                      */
41251 #define MCUCTRL_ADCPWRCTRL_REFBUFPEN_Pos  (5UL)                     /*!< REFBUFPEN (Bit 5)                                     */
41252 #define MCUCTRL_ADCPWRCTRL_REFBUFPEN_Msk  (0x20UL)                  /*!< REFBUFPEN (Bitfield-Mask: 0x01)                       */
41253 #define MCUCTRL_ADCPWRCTRL_BGTLPPEN_Pos   (4UL)                     /*!< BGTLPPEN (Bit 4)                                      */
41254 #define MCUCTRL_ADCPWRCTRL_BGTLPPEN_Msk   (0x10UL)                  /*!< BGTLPPEN (Bitfield-Mask: 0x01)                        */
41255 #define MCUCTRL_ADCPWRCTRL_BGTPEN_Pos     (3UL)                     /*!< BGTPEN (Bit 3)                                        */
41256 #define MCUCTRL_ADCPWRCTRL_BGTPEN_Msk     (0x8UL)                   /*!< BGTPEN (Bitfield-Mask: 0x01)                          */
41257 #define MCUCTRL_ADCPWRCTRL_ADCBPSEN_Pos   (2UL)                     /*!< ADCBPSEN (Bit 2)                                      */
41258 #define MCUCTRL_ADCPWRCTRL_ADCBPSEN_Msk   (0x4UL)                   /*!< ADCBPSEN (Bitfield-Mask: 0x01)                        */
41259 #define MCUCTRL_ADCPWRCTRL_ADCAPSEN_Pos   (1UL)                     /*!< ADCAPSEN (Bit 1)                                      */
41260 #define MCUCTRL_ADCPWRCTRL_ADCAPSEN_Msk   (0x2UL)                   /*!< ADCAPSEN (Bitfield-Mask: 0x01)                        */
41261 #define MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Pos (0UL)                  /*!< ADCPWRCTRLSWE (Bit 0)                                 */
41262 #define MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Msk (0x1UL)                /*!< ADCPWRCTRLSWE (Bitfield-Mask: 0x01)                   */
41263 /* ========================================================  ADCCAL  ========================================================= */
41264 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos  (1UL)                     /*!< ADCCALIBRATED (Bit 1)                                 */
41265 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk  (0x2UL)                   /*!< ADCCALIBRATED (Bitfield-Mask: 0x01)                   */
41266 #define MCUCTRL_ADCCAL_CALONPWRUP_Pos     (0UL)                     /*!< CALONPWRUP (Bit 0)                                    */
41267 #define MCUCTRL_ADCCAL_CALONPWRUP_Msk     (0x1UL)                   /*!< CALONPWRUP (Bitfield-Mask: 0x01)                      */
41268 /* ======================================================  ADCBATTLOAD  ====================================================== */
41269 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos  (0UL)                     /*!< BATTLOAD (Bit 0)                                      */
41270 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk  (0x1UL)                   /*!< BATTLOAD (Bitfield-Mask: 0x01)                        */
41271 /* =======================================================  XTALCTRL  ======================================================== */
41272 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (7UL)                    /*!< XTALICOMPTRIM (Bit 7)                                 */
41273 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x180UL)                /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03)                   */
41274 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (5UL)                     /*!< XTALIBUFTRIM (Bit 5)                                  */
41275 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0x60UL)                  /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03)                    */
41276 #define MCUCTRL_XTALCTRL_XTALCOMPPDNB_Pos (4UL)                     /*!< XTALCOMPPDNB (Bit 4)                                  */
41277 #define MCUCTRL_XTALCTRL_XTALCOMPPDNB_Msk (0x10UL)                  /*!< XTALCOMPPDNB (Bitfield-Mask: 0x01)                    */
41278 #define MCUCTRL_XTALCTRL_XTALPDNB_Pos     (3UL)                     /*!< XTALPDNB (Bit 3)                                      */
41279 #define MCUCTRL_XTALCTRL_XTALPDNB_Msk     (0x8UL)                   /*!< XTALPDNB (Bitfield-Mask: 0x01)                        */
41280 #define MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Pos (2UL)                   /*!< XTALCOMPBYPASS (Bit 2)                                */
41281 #define MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Msk (0x4UL)                 /*!< XTALCOMPBYPASS (Bitfield-Mask: 0x01)                  */
41282 #define MCUCTRL_XTALCTRL_XTALCOREDISFB_Pos (1UL)                    /*!< XTALCOREDISFB (Bit 1)                                 */
41283 #define MCUCTRL_XTALCTRL_XTALCOREDISFB_Msk (0x2UL)                  /*!< XTALCOREDISFB (Bitfield-Mask: 0x01)                   */
41284 #define MCUCTRL_XTALCTRL_XTALSWE_Pos      (0UL)                     /*!< XTALSWE (Bit 0)                                       */
41285 #define MCUCTRL_XTALCTRL_XTALSWE_Msk      (0x1UL)                   /*!< XTALSWE (Bitfield-Mask: 0x01)                         */
41286 /* ======================================================  XTALGENCTRL  ====================================================== */
41287 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL)                /*!< XTALKSBIASTRIM (Bit 8)                                */
41288 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL)           /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f)                  */
41289 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL)                  /*!< XTALBIASTRIM (Bit 2)                                  */
41290 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL)               /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f)                    */
41291 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos  (0UL)                     /*!< ACWARMUP (Bit 0)                                      */
41292 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk  (0x3UL)                   /*!< ACWARMUP (Bitfield-Mask: 0x03)                        */
41293 /* ======================================================  XTALHSTRIMS  ====================================================== */
41294 #define MCUCTRL_XTALHSTRIMS_XTALHSSPARE_Pos (29UL)                  /*!< XTALHSSPARE (Bit 29)                                  */
41295 #define MCUCTRL_XTALHSTRIMS_XTALHSSPARE_Msk (0x20000000UL)          /*!< XTALHSSPARE (Bitfield-Mask: 0x01)                     */
41296 #define MCUCTRL_XTALHSTRIMS_XTALHSRSTRIM_Pos (28UL)                 /*!< XTALHSRSTRIM (Bit 28)                                 */
41297 #define MCUCTRL_XTALHSTRIMS_XTALHSRSTRIM_Msk (0x10000000UL)         /*!< XTALHSRSTRIM (Bitfield-Mask: 0x01)                    */
41298 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASTRIM_Pos (21UL)              /*!< XTALHSIBIASTRIM (Bit 21)                              */
41299 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASTRIM_Msk (0xfe00000UL)       /*!< XTALHSIBIASTRIM (Bitfield-Mask: 0x7f)                 */
41300 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMPTRIM_Pos (17UL)          /*!< XTALHSIBIASCOMPTRIM (Bit 17)                          */
41301 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMPTRIM_Msk (0x1e0000UL)    /*!< XTALHSIBIASCOMPTRIM (Bitfield-Mask: 0x0f)             */
41302 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMP2TRIM_Pos (15UL)         /*!< XTALHSIBIASCOMP2TRIM (Bit 15)                         */
41303 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMP2TRIM_Msk (0x18000UL)    /*!< XTALHSIBIASCOMP2TRIM (Bitfield-Mask: 0x03)            */
41304 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVERSTRENGTH_Pos (12UL)         /*!< XTALHSDRIVERSTRENGTH (Bit 12)                         */
41305 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVERSTRENGTH_Msk (0x7000UL)     /*!< XTALHSDRIVERSTRENGTH (Bitfield-Mask: 0x07)            */
41306 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVETRIM_Pos (10UL)              /*!< XTALHSDRIVETRIM (Bit 10)                              */
41307 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVETRIM_Msk (0xc00UL)           /*!< XTALHSDRIVETRIM (Bitfield-Mask: 0x03)                 */
41308 #define MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Pos (6UL)                 /*!< XTALHSCAPTRIM (Bit 6)                                 */
41309 #define MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Msk (0x3c0UL)             /*!< XTALHSCAPTRIM (Bitfield-Mask: 0x0f)                   */
41310 #define MCUCTRL_XTALHSTRIMS_XTALHSCAP2TRIM_Pos (0UL)                /*!< XTALHSCAP2TRIM (Bit 0)                                */
41311 #define MCUCTRL_XTALHSTRIMS_XTALHSCAP2TRIM_Msk (0x3fUL)             /*!< XTALHSCAP2TRIM (Bitfield-Mask: 0x3f)                  */
41312 /* ======================================================  XTALHSCTRL  ======================================================= */
41313 #define MCUCTRL_XTALHSCTRL_XTALHSEXTERNALCLOCK_Pos (8UL)            /*!< XTALHSEXTERNALCLOCK (Bit 8)                           */
41314 #define MCUCTRL_XTALHSCTRL_XTALHSEXTERNALCLOCK_Msk (0x100UL)        /*!< XTALHSEXTERNALCLOCK (Bitfield-Mask: 0x01)             */
41315 #define MCUCTRL_XTALHSCTRL_XTALHSPADOUTEN_Pos (7UL)                 /*!< XTALHSPADOUTEN (Bit 7)                                */
41316 #define MCUCTRL_XTALHSCTRL_XTALHSPADOUTEN_Msk (0x80UL)              /*!< XTALHSPADOUTEN (Bitfield-Mask: 0x01)                  */
41317 #define MCUCTRL_XTALHSCTRL_XTALHSSELRCOM_Pos (6UL)                  /*!< XTALHSSELRCOM (Bit 6)                                 */
41318 #define MCUCTRL_XTALHSCTRL_XTALHSSELRCOM_Msk (0x40UL)               /*!< XTALHSSELRCOM (Bitfield-Mask: 0x01)                   */
41319 #define MCUCTRL_XTALHSCTRL_XTALHSPDNPNIMPROVE_Pos (5UL)             /*!< XTALHSPDNPNIMPROVE (Bit 5)                            */
41320 #define MCUCTRL_XTALHSCTRL_XTALHSPDNPNIMPROVE_Msk (0x20UL)          /*!< XTALHSPDNPNIMPROVE (Bitfield-Mask: 0x01)              */
41321 #define MCUCTRL_XTALHSCTRL_XTALHSINJECTIONENABLE_Pos (4UL)          /*!< XTALHSINJECTIONENABLE (Bit 4)                         */
41322 #define MCUCTRL_XTALHSCTRL_XTALHSINJECTIONENABLE_Msk (0x10UL)       /*!< XTALHSINJECTIONENABLE (Bitfield-Mask: 0x01)           */
41323 #define MCUCTRL_XTALHSCTRL_XTALHSIBSTENABLE_Pos (3UL)               /*!< XTALHSIBSTENABLE (Bit 3)                              */
41324 #define MCUCTRL_XTALHSCTRL_XTALHSIBSTENABLE_Msk (0x8UL)             /*!< XTALHSIBSTENABLE (Bitfield-Mask: 0x01)                */
41325 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPSEL_Pos (2UL)                  /*!< XTALHSCOMPSEL (Bit 2)                                 */
41326 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPSEL_Msk (0x4UL)                /*!< XTALHSCOMPSEL (Bitfield-Mask: 0x01)                   */
41327 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPPDNB_Pos (1UL)                 /*!< XTALHSCOMPPDNB (Bit 1)                                */
41328 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPPDNB_Msk (0x2UL)               /*!< XTALHSCOMPPDNB (Bitfield-Mask: 0x01)                  */
41329 #define MCUCTRL_XTALHSCTRL_XTALHSPDNB_Pos (0UL)                     /*!< XTALHSPDNB (Bit 0)                                    */
41330 #define MCUCTRL_XTALHSCTRL_XTALHSPDNB_Msk (0x1UL)                   /*!< XTALHSPDNB (Bitfield-Mask: 0x01)                      */
41331 /* ======================================================  MRAMPWRCTRL  ====================================================== */
41332 #define MCUCTRL_MRAMPWRCTRL_MRAMPWRCTRL_Pos (2UL)                   /*!< MRAMPWRCTRL (Bit 2)                                   */
41333 #define MCUCTRL_MRAMPWRCTRL_MRAMPWRCTRL_Msk (0x4UL)                 /*!< MRAMPWRCTRL (Bitfield-Mask: 0x01)                     */
41334 #define MCUCTRL_MRAMPWRCTRL_MRAMSLPEN_Pos (1UL)                     /*!< MRAMSLPEN (Bit 1)                                     */
41335 #define MCUCTRL_MRAMPWRCTRL_MRAMSLPEN_Msk (0x2UL)                   /*!< MRAMSLPEN (Bitfield-Mask: 0x01)                       */
41336 #define MCUCTRL_MRAMPWRCTRL_MRAMLPREN_Pos (0UL)                     /*!< MRAMLPREN (Bit 0)                                     */
41337 #define MCUCTRL_MRAMPWRCTRL_MRAMLPREN_Msk (0x1UL)                   /*!< MRAMLPREN (Bitfield-Mask: 0x01)                       */
41338 /* =======================================================  BODISABLE  ======================================================= */
41339 #define MCUCTRL_BODISABLE_BODCLVREN_Pos   (4UL)                     /*!< BODCLVREN (Bit 4)                                     */
41340 #define MCUCTRL_BODISABLE_BODCLVREN_Msk   (0x10UL)                  /*!< BODCLVREN (Bitfield-Mask: 0x01)                       */
41341 #define MCUCTRL_BODISABLE_BODSREN_Pos     (3UL)                     /*!< BODSREN (Bit 3)                                       */
41342 #define MCUCTRL_BODISABLE_BODSREN_Msk     (0x8UL)                   /*!< BODSREN (Bitfield-Mask: 0x01)                         */
41343 #define MCUCTRL_BODISABLE_BODFREN_Pos     (2UL)                     /*!< BODFREN (Bit 2)                                       */
41344 #define MCUCTRL_BODISABLE_BODFREN_Msk     (0x4UL)                   /*!< BODFREN (Bitfield-Mask: 0x01)                         */
41345 #define MCUCTRL_BODISABLE_BODCREN_Pos     (1UL)                     /*!< BODCREN (Bit 1)                                       */
41346 #define MCUCTRL_BODISABLE_BODCREN_Msk     (0x2UL)                   /*!< BODCREN (Bitfield-Mask: 0x01)                         */
41347 #define MCUCTRL_BODISABLE_BODLRDE_Pos     (0UL)                     /*!< BODLRDE (Bit 0)                                       */
41348 #define MCUCTRL_BODISABLE_BODLRDE_Msk     (0x1UL)                   /*!< BODLRDE (Bitfield-Mask: 0x01)                         */
41349 /* ======================================================  BOOTLOADER  ======================================================= */
41350 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL)                  /*!< SECBOOTONRST (Bit 30)                                 */
41351 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL)          /*!< SECBOOTONRST (Bitfield-Mask: 0x03)                    */
41352 #define MCUCTRL_BOOTLOADER_SECBOOT_Pos    (28UL)                    /*!< SECBOOT (Bit 28)                                      */
41353 #define MCUCTRL_BOOTLOADER_SECBOOT_Msk    (0x30000000UL)            /*!< SECBOOT (Bitfield-Mask: 0x03)                         */
41354 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL)                /*!< SECBOOTFEATURE (Bit 26)                               */
41355 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL)         /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03)                  */
41356 #define MCUCTRL_BOOTLOADER_SBLLOCK_Pos    (3UL)                     /*!< SBLLOCK (Bit 3)                                       */
41357 #define MCUCTRL_BOOTLOADER_SBLLOCK_Msk    (0x8UL)                   /*!< SBLLOCK (Bitfield-Mask: 0x01)                         */
41358 #define MCUCTRL_BOOTLOADER_PROTLOCK_Pos   (2UL)                     /*!< PROTLOCK (Bit 2)                                      */
41359 #define MCUCTRL_BOOTLOADER_PROTLOCK_Msk   (0x4UL)                   /*!< PROTLOCK (Bitfield-Mask: 0x01)                        */
41360 #define MCUCTRL_BOOTLOADER_SBRLOCK_Pos    (1UL)                     /*!< SBRLOCK (Bit 1)                                       */
41361 #define MCUCTRL_BOOTLOADER_SBRLOCK_Msk    (0x2UL)                   /*!< SBRLOCK (Bitfield-Mask: 0x01)                         */
41362 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL)                  /*!< BOOTLOADERLOW (Bit 0)                                 */
41363 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL)                /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01)                   */
41364 /* ======================================================  SHADOWVALID  ====================================================== */
41365 #define MCUCTRL_SHADOWVALID_INFO0VALID_Pos (2UL)                    /*!< INFO0VALID (Bit 2)                                    */
41366 #define MCUCTRL_SHADOWVALID_INFO0VALID_Msk (0x4UL)                  /*!< INFO0VALID (Bitfield-Mask: 0x01)                      */
41367 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos  (1UL)                     /*!< BLDSLEEP (Bit 1)                                      */
41368 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk  (0x2UL)                   /*!< BLDSLEEP (Bitfield-Mask: 0x01)                        */
41369 #define MCUCTRL_SHADOWVALID_VALID_Pos     (0UL)                     /*!< VALID (Bit 0)                                         */
41370 #define MCUCTRL_SHADOWVALID_VALID_Msk     (0x1UL)                   /*!< VALID (Bitfield-Mask: 0x01)                           */
41371 /* =======================================================  SCRATCH0  ======================================================== */
41372 #define MCUCTRL_SCRATCH0_HALTREQ_Pos      (0UL)                     /*!< HALTREQ (Bit 0)                                       */
41373 #define MCUCTRL_SCRATCH0_HALTREQ_Msk      (0x1UL)                   /*!< HALTREQ (Bitfield-Mask: 0x01)                         */
41374 /* =========================================================  DBGR1  ========================================================= */
41375 #define MCUCTRL_DBGR1_ONETO8_Pos          (0UL)                     /*!< ONETO8 (Bit 0)                                        */
41376 #define MCUCTRL_DBGR1_ONETO8_Msk          (0xffffffffUL)            /*!< ONETO8 (Bitfield-Mask: 0xffffffff)                    */
41377 /* =========================================================  DBGR2  ========================================================= */
41378 #define MCUCTRL_DBGR2_COOLCODE_Pos        (0UL)                     /*!< COOLCODE (Bit 0)                                      */
41379 #define MCUCTRL_DBGR2_COOLCODE_Msk        (0xffffffffUL)            /*!< COOLCODE (Bitfield-Mask: 0xffffffff)                  */
41380 /* =======================================================  PMUENABLE  ======================================================= */
41381 #define MCUCTRL_PMUENABLE_ENABLE_Pos      (0UL)                     /*!< ENABLE (Bit 0)                                        */
41382 #define MCUCTRL_PMUENABLE_ENABLE_Msk      (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
41383 /* ========================================================  DBGCTRL  ======================================================== */
41384 #define MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Pos (17UL)              /*!< DBGDSP1OCDHALTONRST (Bit 17)                          */
41385 #define MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Msk (0x20000UL)         /*!< DBGDSP1OCDHALTONRST (Bitfield-Mask: 0x01)             */
41386 #define MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Pos (16UL)              /*!< DBGDSP0OCDHALTONRST (Bit 16)                          */
41387 #define MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Msk (0x10000UL)         /*!< DBGDSP0OCDHALTONRST (Bitfield-Mask: 0x01)             */
41388 #define MCUCTRL_DBGCTRL_DBGTSCLKSEL_Pos   (12UL)                    /*!< DBGTSCLKSEL (Bit 12)                                  */
41389 #define MCUCTRL_DBGCTRL_DBGTSCLKSEL_Msk   (0x7000UL)                /*!< DBGTSCLKSEL (Bitfield-Mask: 0x07)                     */
41390 #define MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Pos (11UL)                   /*!< DBGDSP1TRACEEN (Bit 11)                               */
41391 #define MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Msk (0x800UL)                /*!< DBGDSP1TRACEEN (Bitfield-Mask: 0x01)                  */
41392 #define MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Pos (10UL)                   /*!< DBGDSP0TRACEEN (Bit 10)                               */
41393 #define MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Msk (0x400UL)                /*!< DBGDSP0TRACEEN (Bitfield-Mask: 0x01)                  */
41394 #define MCUCTRL_DBGCTRL_DBGETMTRACEEN_Pos (9UL)                     /*!< DBGETMTRACEEN (Bit 9)                                 */
41395 #define MCUCTRL_DBGCTRL_DBGETMTRACEEN_Msk (0x200UL)                 /*!< DBGETMTRACEEN (Bitfield-Mask: 0x01)                   */
41396 #define MCUCTRL_DBGCTRL_DBGETBENABLE_Pos  (8UL)                     /*!< DBGETBENABLE (Bit 8)                                  */
41397 #define MCUCTRL_DBGCTRL_DBGETBENABLE_Msk  (0x100UL)                 /*!< DBGETBENABLE (Bitfield-Mask: 0x01)                    */
41398 #define MCUCTRL_DBGCTRL_DBGCLKSEL_Pos     (5UL)                     /*!< DBGCLKSEL (Bit 5)                                     */
41399 #define MCUCTRL_DBGCTRL_DBGCLKSEL_Msk     (0xe0UL)                  /*!< DBGCLKSEL (Bitfield-Mask: 0x07)                       */
41400 #define MCUCTRL_DBGCTRL_DBGTPIUENABLE_Pos (4UL)                     /*!< DBGTPIUENABLE (Bit 4)                                 */
41401 #define MCUCTRL_DBGCTRL_DBGTPIUENABLE_Msk (0x10UL)                  /*!< DBGTPIUENABLE (Bitfield-Mask: 0x01)                   */
41402 #define MCUCTRL_DBGCTRL_CM4CLKSEL_Pos     (1UL)                     /*!< CM4CLKSEL (Bit 1)                                     */
41403 #define MCUCTRL_DBGCTRL_CM4CLKSEL_Msk     (0xeUL)                   /*!< CM4CLKSEL (Bitfield-Mask: 0x07)                       */
41404 #define MCUCTRL_DBGCTRL_CM4TPIUENABLE_Pos (0UL)                     /*!< CM4TPIUENABLE (Bit 0)                                 */
41405 #define MCUCTRL_DBGCTRL_CM4TPIUENABLE_Msk (0x1UL)                   /*!< CM4TPIUENABLE (Bitfield-Mask: 0x01)                   */
41406 /* ======================================================  OTAPOINTER  ======================================================= */
41407 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL)                     /*!< OTAPOINTER (Bit 2)                                    */
41408 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL)            /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff)                */
41409 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL)                   /*!< OTASBLUPDATE (Bit 1)                                  */
41410 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL)                 /*!< OTASBLUPDATE (Bitfield-Mask: 0x01)                    */
41411 #define MCUCTRL_OTAPOINTER_OTAVALID_Pos   (0UL)                     /*!< OTAVALID (Bit 0)                                      */
41412 #define MCUCTRL_OTAPOINTER_OTAVALID_Msk   (0x1UL)                   /*!< OTAVALID (Bitfield-Mask: 0x01)                        */
41413 /* ======================================================  APBDMACTRL  ======================================================= */
41414 #define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL)                     /*!< HYSTERESIS (Bit 8)                                    */
41415 #define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL)                /*!< HYSTERESIS (Bitfield-Mask: 0xff)                      */
41416 #define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL)                    /*!< DECODEABORT (Bit 1)                                   */
41417 #define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL)                  /*!< DECODEABORT (Bitfield-Mask: 0x01)                     */
41418 #define MCUCTRL_APBDMACTRL_DMAENABLE_Pos  (0UL)                     /*!< DMAENABLE (Bit 0)                                     */
41419 #define MCUCTRL_APBDMACTRL_DMAENABLE_Msk  (0x1UL)                   /*!< DMAENABLE (Bitfield-Mask: 0x01)                       */
41420 /* ======================================================  KEXTCLKSEL  ======================================================= */
41421 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL)                     /*!< KEXTCLKSEL (Bit 0)                                    */
41422 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL)            /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff)                */
41423 /* =======================================================  SIMOBUCK0  ======================================================= */
41424 #define MCUCTRL_SIMOBUCK0_TONTOFFNODEGLITCH_Pos (4UL)               /*!< TONTOFFNODEGLITCH (Bit 4)                             */
41425 #define MCUCTRL_SIMOBUCK0_TONTOFFNODEGLITCH_Msk (0x10UL)            /*!< TONTOFFNODEGLITCH (Bitfield-Mask: 0x01)               */
41426 #define MCUCTRL_SIMOBUCK0_VDDCLVRXCOMPEN_Pos (3UL)                  /*!< VDDCLVRXCOMPEN (Bit 3)                                */
41427 #define MCUCTRL_SIMOBUCK0_VDDCLVRXCOMPEN_Msk (0x8UL)                /*!< VDDCLVRXCOMPEN (Bitfield-Mask: 0x01)                  */
41428 #define MCUCTRL_SIMOBUCK0_VDDSRXCOMPEN_Pos (2UL)                    /*!< VDDSRXCOMPEN (Bit 2)                                  */
41429 #define MCUCTRL_SIMOBUCK0_VDDSRXCOMPEN_Msk (0x4UL)                  /*!< VDDSRXCOMPEN (Bitfield-Mask: 0x01)                    */
41430 #define MCUCTRL_SIMOBUCK0_VDDFRXCOMPEN_Pos (1UL)                    /*!< VDDFRXCOMPEN (Bit 1)                                  */
41431 #define MCUCTRL_SIMOBUCK0_VDDFRXCOMPEN_Msk (0x2UL)                  /*!< VDDFRXCOMPEN (Bitfield-Mask: 0x01)                    */
41432 #define MCUCTRL_SIMOBUCK0_VDDCRXCOMPEN_Pos (0UL)                    /*!< VDDCRXCOMPEN (Bit 0)                                  */
41433 #define MCUCTRL_SIMOBUCK0_VDDCRXCOMPEN_Msk (0x1UL)                  /*!< VDDCRXCOMPEN (Bitfield-Mask: 0x01)                    */
41434 /* =======================================================  SIMOBUCK1  ======================================================= */
41435 #define MCUCTRL_SIMOBUCK1_SIMOBUCKTONCLKTRIM_Pos (22UL)             /*!< SIMOBUCKTONCLKTRIM (Bit 22)                           */
41436 #define MCUCTRL_SIMOBUCK1_SIMOBUCKTONCLKTRIM_Msk (0x3c00000UL)      /*!< SIMOBUCKTONCLKTRIM (Bitfield-Mask: 0x0f)              */
41437 #define MCUCTRL_SIMOBUCK1_SIMOBUCKRXCLKACTTRIM_Pos (6UL)            /*!< SIMOBUCKRXCLKACTTRIM (Bit 6)                          */
41438 #define MCUCTRL_SIMOBUCK1_SIMOBUCKRXCLKACTTRIM_Msk (0x7c0UL)        /*!< SIMOBUCKRXCLKACTTRIM (Bitfield-Mask: 0x1f)            */
41439 /* =======================================================  SIMOBUCK2  ======================================================= */
41440 #define MCUCTRL_SIMOBUCK2_SIMOBUCKVDDCACTLOWTONTRIM_Pos (24UL)      /*!< SIMOBUCKVDDCACTLOWTONTRIM (Bit 24)                    */
41441 #define MCUCTRL_SIMOBUCK2_SIMOBUCKVDDCACTLOWTONTRIM_Msk (0xf000000UL) /*!< SIMOBUCKVDDCACTLOWTONTRIM (Bitfield-Mask: 0x0f)     */
41442 #define MCUCTRL_SIMOBUCK2_SIMOBUCKVDDCACTHIGHTONTRIM_Pos (11UL)     /*!< SIMOBUCKVDDCACTHIGHTONTRIM (Bit 11)                   */
41443 #define MCUCTRL_SIMOBUCK2_SIMOBUCKVDDCACTHIGHTONTRIM_Msk (0x7800UL) /*!< SIMOBUCKVDDCACTHIGHTONTRIM (Bitfield-Mask: 0x0f)      */
41444 /* =======================================================  SIMOBUCK3  ======================================================= */
41445 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPLOWTONTRIM_Pos (26UL)       /*!< SIMOBUCKVDDCLPLOWTONTRIM (Bit 26)                     */
41446 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPLOWTONTRIM_Msk (0x3c000000UL) /*!< SIMOBUCKVDDCLPLOWTONTRIM (Bitfield-Mask: 0x0f)      */
41447 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPLOWTOFFTRIM_Pos (21UL)      /*!< SIMOBUCKVDDCLPLOWTOFFTRIM (Bit 21)                    */
41448 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPLOWTOFFTRIM_Msk (0x3e00000UL) /*!< SIMOBUCKVDDCLPLOWTOFFTRIM (Bitfield-Mask: 0x1f)     */
41449 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPHIGHTONTRIM_Pos (13UL)      /*!< SIMOBUCKVDDCLPHIGHTONTRIM (Bit 13)                    */
41450 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPHIGHTONTRIM_Msk (0x1e000UL) /*!< SIMOBUCKVDDCLPHIGHTONTRIM (Bitfield-Mask: 0x0f)       */
41451 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPHIGHTOFFTRIM_Pos (8UL)      /*!< SIMOBUCKVDDCLPHIGHTOFFTRIM (Bit 8)                    */
41452 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPHIGHTOFFTRIM_Msk (0x1f00UL) /*!< SIMOBUCKVDDCLPHIGHTOFFTRIM (Bitfield-Mask: 0x1f)      */
41453 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPDRVSTRTRIM_Pos (2UL)        /*!< SIMOBUCKVDDCLPDRVSTRTRIM (Bit 2)                      */
41454 #define MCUCTRL_SIMOBUCK3_SIMOBUCKVDDCLPDRVSTRTRIM_Msk (0xcUL)      /*!< SIMOBUCKVDDCLPDRVSTRTRIM (Bitfield-Mask: 0x03)        */
41455 /* =======================================================  SIMOBUCK4  ======================================================= */
41456 #define MCUCTRL_SIMOBUCK4_VDDCLVACTLOWTONTRIM_Pos (24UL)            /*!< VDDCLVACTLOWTONTRIM (Bit 24)                          */
41457 #define MCUCTRL_SIMOBUCK4_VDDCLVACTLOWTONTRIM_Msk (0xf000000UL)     /*!< VDDCLVACTLOWTONTRIM (Bitfield-Mask: 0x0f)             */
41458 #define MCUCTRL_SIMOBUCK4_VDDCLVACTLOWTOFFTRIM_Pos (19UL)           /*!< VDDCLVACTLOWTOFFTRIM (Bit 19)                         */
41459 #define MCUCTRL_SIMOBUCK4_VDDCLVACTLOWTOFFTRIM_Msk (0xf80000UL)     /*!< VDDCLVACTLOWTOFFTRIM (Bitfield-Mask: 0x1f)            */
41460 #define MCUCTRL_SIMOBUCK4_VDDCLVACTHIGHTONTRIM_Pos (11UL)           /*!< VDDCLVACTHIGHTONTRIM (Bit 11)                         */
41461 #define MCUCTRL_SIMOBUCK4_VDDCLVACTHIGHTONTRIM_Msk (0x7800UL)       /*!< VDDCLVACTHIGHTONTRIM (Bitfield-Mask: 0x0f)            */
41462 #define MCUCTRL_SIMOBUCK4_VDDCLVACTHIGHTOFFTRIM_Pos (6UL)           /*!< VDDCLVACTHIGHTOFFTRIM (Bit 6)                         */
41463 #define MCUCTRL_SIMOBUCK4_VDDCLVACTHIGHTOFFTRIM_Msk (0x7c0UL)       /*!< VDDCLVACTHIGHTOFFTRIM (Bitfield-Mask: 0x1f)           */
41464 #define MCUCTRL_SIMOBUCK4_VDDCLVACTDRVSTRTRIM_Pos (0UL)             /*!< VDDCLVACTDRVSTRTRIM (Bit 0)                           */
41465 #define MCUCTRL_SIMOBUCK4_VDDCLVACTDRVSTRTRIM_Msk (0x3UL)           /*!< VDDCLVACTDRVSTRTRIM (Bitfield-Mask: 0x03)             */
41466 /* =======================================================  SIMOBUCK6  ======================================================= */
41467 #define MCUCTRL_SIMOBUCK6_SIMOBUCKVDDFACTHIGHTONTRIM_Pos (17UL)     /*!< SIMOBUCKVDDFACTHIGHTONTRIM (Bit 17)                   */
41468 #define MCUCTRL_SIMOBUCK6_SIMOBUCKVDDFACTHIGHTONTRIM_Msk (0x1e0000UL) /*!< SIMOBUCKVDDFACTHIGHTONTRIM (Bitfield-Mask: 0x0f)    */
41469 /* =======================================================  SIMOBUCK7  ======================================================= */
41470 #define MCUCTRL_SIMOBUCK7_ZXCOMPZXTRIM_Pos (18UL)                   /*!< ZXCOMPZXTRIM (Bit 18)                                 */
41471 #define MCUCTRL_SIMOBUCK7_ZXCOMPZXTRIM_Msk (0x7c0000UL)             /*!< ZXCOMPZXTRIM (Bitfield-Mask: 0x1f)                    */
41472 #define MCUCTRL_SIMOBUCK7_VDDFLPDRVSTRTRIM_Pos (13UL)               /*!< VDDFLPDRVSTRTRIM (Bit 13)                             */
41473 #define MCUCTRL_SIMOBUCK7_VDDFLPDRVSTRTRIM_Msk (0x6000UL)           /*!< VDDFLPDRVSTRTRIM (Bitfield-Mask: 0x03)                */
41474 #define MCUCTRL_SIMOBUCK7_VDDFACTLOWTONTRIM_Pos (9UL)               /*!< VDDFACTLOWTONTRIM (Bit 9)                             */
41475 #define MCUCTRL_SIMOBUCK7_VDDFACTLOWTONTRIM_Msk (0x1e00UL)          /*!< VDDFACTLOWTONTRIM (Bitfield-Mask: 0x0f)               */
41476 #define MCUCTRL_SIMOBUCK7_VDDFACTLOWTOFFTRIM_Pos (4UL)              /*!< VDDFACTLOWTOFFTRIM (Bit 4)                            */
41477 #define MCUCTRL_SIMOBUCK7_VDDFACTLOWTOFFTRIM_Msk (0x1f0UL)          /*!< VDDFACTLOWTOFFTRIM (Bitfield-Mask: 0x1f)              */
41478 /* =======================================================  SIMOBUCK8  ======================================================= */
41479 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPLOWTONTRIM_Pos (22UL)       /*!< SIMOBUCKVDDFLPLOWTONTRIM (Bit 22)                     */
41480 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPLOWTONTRIM_Msk (0x3c00000UL) /*!< SIMOBUCKVDDFLPLOWTONTRIM (Bitfield-Mask: 0x0f)       */
41481 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPLOWTOFFTRIM_Pos (17UL)      /*!< SIMOBUCKVDDFLPLOWTOFFTRIM (Bit 17)                    */
41482 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPLOWTOFFTRIM_Msk (0x3e0000UL) /*!< SIMOBUCKVDDFLPLOWTOFFTRIM (Bitfield-Mask: 0x1f)      */
41483 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPHIGHTONTRIM_Pos (9UL)       /*!< SIMOBUCKVDDFLPHIGHTONTRIM (Bit 9)                     */
41484 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPHIGHTONTRIM_Msk (0x1e00UL)  /*!< SIMOBUCKVDDFLPHIGHTONTRIM (Bitfield-Mask: 0x0f)       */
41485 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPHIGHTOFFTRIM_Pos (4UL)      /*!< SIMOBUCKVDDFLPHIGHTOFFTRIM (Bit 4)                    */
41486 #define MCUCTRL_SIMOBUCK8_SIMOBUCKVDDFLPHIGHTOFFTRIM_Msk (0x1f0UL)  /*!< SIMOBUCKVDDFLPHIGHTOFFTRIM (Bitfield-Mask: 0x1f)      */
41487 /* =======================================================  SIMOBUCK9  ======================================================= */
41488 #define MCUCTRL_SIMOBUCK9_SIMOBUCKVDDSACTLOWTONTRIM_Pos (22UL)      /*!< SIMOBUCKVDDSACTLOWTONTRIM (Bit 22)                    */
41489 #define MCUCTRL_SIMOBUCK9_SIMOBUCKVDDSACTLOWTONTRIM_Msk (0x3c00000UL) /*!< SIMOBUCKVDDSACTLOWTONTRIM (Bitfield-Mask: 0x0f)     */
41490 #define MCUCTRL_SIMOBUCK9_SIMOBUCKVDDSACTHIGHTONTRIM_Pos (17UL)     /*!< SIMOBUCKVDDSACTHIGHTONTRIM (Bit 17)                   */
41491 #define MCUCTRL_SIMOBUCK9_SIMOBUCKVDDSACTHIGHTONTRIM_Msk (0x1e0000UL) /*!< SIMOBUCKVDDSACTHIGHTONTRIM (Bitfield-Mask: 0x0f)    */
41492 /* ======================================================  SIMOBUCK12  ======================================================= */
41493 #define MCUCTRL_SIMOBUCK12_LPTRIMVDDF_Pos (26UL)                    /*!< LPTRIMVDDF (Bit 26)                                   */
41494 #define MCUCTRL_SIMOBUCK12_LPTRIMVDDF_Msk (0xfc000000UL)            /*!< LPTRIMVDDF (Bitfield-Mask: 0x3f)                      */
41495 #define MCUCTRL_SIMOBUCK12_ACTTRIMVDDF_Pos (20UL)                   /*!< ACTTRIMVDDF (Bit 20)                                  */
41496 #define MCUCTRL_SIMOBUCK12_ACTTRIMVDDF_Msk (0x3f00000UL)            /*!< ACTTRIMVDDF (Bitfield-Mask: 0x3f)                     */
41497 #define MCUCTRL_SIMOBUCK12_VDDCLVBRNOUTTRIM_Pos (10UL)              /*!< VDDCLVBRNOUTTRIM (Bit 10)                             */
41498 #define MCUCTRL_SIMOBUCK12_VDDCLVBRNOUTTRIM_Msk (0xffc00UL)         /*!< VDDCLVBRNOUTTRIM (Bitfield-Mask: 0x3ff)               */
41499 #define MCUCTRL_SIMOBUCK12_VDDCLVCOMPTRIMPLUS_Pos (5UL)             /*!< VDDCLVCOMPTRIMPLUS (Bit 5)                            */
41500 #define MCUCTRL_SIMOBUCK12_VDDCLVCOMPTRIMPLUS_Msk (0x3e0UL)         /*!< VDDCLVCOMPTRIMPLUS (Bitfield-Mask: 0x1f)              */
41501 #define MCUCTRL_SIMOBUCK12_VDDCLVCOMPTRIMMINUS_Pos (0UL)            /*!< VDDCLVCOMPTRIMMINUS (Bit 0)                           */
41502 #define MCUCTRL_SIMOBUCK12_VDDCLVCOMPTRIMMINUS_Msk (0x1fUL)         /*!< VDDCLVCOMPTRIMMINUS (Bitfield-Mask: 0x1f)             */
41503 /* ======================================================  SIMOBUCK13  ======================================================= */
41504 #define MCUCTRL_SIMOBUCK13_SIMOBUCKLPTRIMVDDS_Pos (26UL)            /*!< SIMOBUCKLPTRIMVDDS (Bit 26)                           */
41505 #define MCUCTRL_SIMOBUCK13_SIMOBUCKLPTRIMVDDS_Msk (0xfc000000UL)    /*!< SIMOBUCKLPTRIMVDDS (Bitfield-Mask: 0x3f)              */
41506 #define MCUCTRL_SIMOBUCK13_SIMOBUCKACTTRIMVDDS_Pos (20UL)           /*!< SIMOBUCKACTTRIMVDDS (Bit 20)                          */
41507 #define MCUCTRL_SIMOBUCK13_SIMOBUCKACTTRIMVDDS_Msk (0x3f00000UL)    /*!< SIMOBUCKACTTRIMVDDS (Bitfield-Mask: 0x3f)             */
41508 /* ======================================================  SIMOBUCK15  ======================================================= */
41509 #define MCUCTRL_SIMOBUCK15_TRIMLATCHOVER_Pos (31UL)                 /*!< TRIMLATCHOVER (Bit 31)                                */
41510 #define MCUCTRL_SIMOBUCK15_TRIMLATCHOVER_Msk (0x80000000UL)         /*!< TRIMLATCHOVER (Bitfield-Mask: 0x01)                   */
41511 #define MCUCTRL_SIMOBUCK15_ZXCOMPOFFSETTRIM_Pos (24UL)              /*!< ZXCOMPOFFSETTRIM (Bit 24)                             */
41512 #define MCUCTRL_SIMOBUCK15_ZXCOMPOFFSETTRIM_Msk (0x1f000000UL)      /*!< ZXCOMPOFFSETTRIM (Bitfield-Mask: 0x1f)                */
41513 #define MCUCTRL_SIMOBUCK15_VDDCRXCOMPTRIMEN_Pos (23UL)              /*!< VDDCRXCOMPTRIMEN (Bit 23)                             */
41514 #define MCUCTRL_SIMOBUCK15_VDDCRXCOMPTRIMEN_Msk (0x800000UL)        /*!< VDDCRXCOMPTRIMEN (Bitfield-Mask: 0x01)                */
41515 #define MCUCTRL_SIMOBUCK15_VDDFRXCOMPTRIMEN_Pos (22UL)              /*!< VDDFRXCOMPTRIMEN (Bit 22)                             */
41516 #define MCUCTRL_SIMOBUCK15_VDDFRXCOMPTRIMEN_Msk (0x400000UL)        /*!< VDDFRXCOMPTRIMEN (Bitfield-Mask: 0x01)                */
41517 #define MCUCTRL_SIMOBUCK15_VDDSRXCOMPTRIMEN_Pos (21UL)              /*!< VDDSRXCOMPTRIMEN (Bit 21)                             */
41518 #define MCUCTRL_SIMOBUCK15_VDDSRXCOMPTRIMEN_Msk (0x200000UL)        /*!< VDDSRXCOMPTRIMEN (Bitfield-Mask: 0x01)                */
41519 #define MCUCTRL_SIMOBUCK15_VDDCLVRXCOMPTRIMEN_Pos (20UL)            /*!< VDDCLVRXCOMPTRIMEN (Bit 20)                           */
41520 #define MCUCTRL_SIMOBUCK15_VDDCLVRXCOMPTRIMEN_Msk (0x100000UL)      /*!< VDDCLVRXCOMPTRIMEN (Bitfield-Mask: 0x01)              */
41521 #define MCUCTRL_SIMOBUCK15_VDDCBRNOUTTRIM_Pos (10UL)                /*!< VDDCBRNOUTTRIM (Bit 10)                               */
41522 #define MCUCTRL_SIMOBUCK15_VDDCBRNOUTTRIM_Msk (0xffc00UL)           /*!< VDDCBRNOUTTRIM (Bitfield-Mask: 0x3ff)                 */
41523 #define MCUCTRL_SIMOBUCK15_VDDCCOMPTRIMPLUS_Pos (5UL)               /*!< VDDCCOMPTRIMPLUS (Bit 5)                              */
41524 #define MCUCTRL_SIMOBUCK15_VDDCCOMPTRIMPLUS_Msk (0x3e0UL)           /*!< VDDCCOMPTRIMPLUS (Bitfield-Mask: 0x1f)                */
41525 #define MCUCTRL_SIMOBUCK15_VDDCCOMPTRIMMINUS_Pos (0UL)              /*!< VDDCCOMPTRIMMINUS (Bit 0)                             */
41526 #define MCUCTRL_SIMOBUCK15_VDDCCOMPTRIMMINUS_Msk (0x1fUL)           /*!< VDDCCOMPTRIMMINUS (Bitfield-Mask: 0x1f)               */
41527 /* ========================================================  PWRSW0  ========================================================= */
41528 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUOVERRIDE_Pos (31UL)              /*!< PWRSWVDDRCPUOVERRIDE (Bit 31)                         */
41529 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUOVERRIDE_Msk (0x80000000UL)      /*!< PWRSWVDDRCPUOVERRIDE (Bitfield-Mask: 0x01)            */
41530 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Pos (30UL)               /*!< PWRSWVDDRCPUSTATSEL (Bit 30)                          */
41531 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Msk (0x40000000UL)       /*!< PWRSWVDDRCPUSTATSEL (Bitfield-Mask: 0x01)             */
41532 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUDYNSEL_Pos (27UL)                /*!< PWRSWVDDRCPUDYNSEL (Bit 27)                           */
41533 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUDYNSEL_Msk (0x18000000UL)        /*!< PWRSWVDDRCPUDYNSEL (Bitfield-Mask: 0x03)              */
41534 #define MCUCTRL_PWRSW0_PWRSWVDDMLOVERRIDE_Pos (26UL)                /*!< PWRSWVDDMLOVERRIDE (Bit 26)                           */
41535 #define MCUCTRL_PWRSW0_PWRSWVDDMLOVERRIDE_Msk (0x4000000UL)         /*!< PWRSWVDDMLOVERRIDE (Bitfield-Mask: 0x01)              */
41536 #define MCUCTRL_PWRSW0_PWRSWVDDMLDYNSEL_Pos (24UL)                  /*!< PWRSWVDDMLDYNSEL (Bit 24)                             */
41537 #define MCUCTRL_PWRSW0_PWRSWVDDMLDYNSEL_Msk (0x1000000UL)           /*!< PWRSWVDDMLDYNSEL (Bitfield-Mask: 0x01)                */
41538 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1OVERRIDE_Pos (23UL)             /*!< PWRSWVDDMDSP1OVERRIDE (Bit 23)                        */
41539 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1OVERRIDE_Msk (0x800000UL)       /*!< PWRSWVDDMDSP1OVERRIDE (Bitfield-Mask: 0x01)           */
41540 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Pos (22UL)              /*!< PWRSWVDDMDSP1STATSEL (Bit 22)                         */
41541 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Msk (0x400000UL)        /*!< PWRSWVDDMDSP1STATSEL (Bitfield-Mask: 0x01)            */
41542 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1DYNSEL_Pos (21UL)               /*!< PWRSWVDDMDSP1DYNSEL (Bit 21)                          */
41543 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1DYNSEL_Msk (0x200000UL)         /*!< PWRSWVDDMDSP1DYNSEL (Bitfield-Mask: 0x01)             */
41544 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0OVERRIDE_Pos (20UL)             /*!< PWRSWVDDMDSP0OVERRIDE (Bit 20)                        */
41545 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0OVERRIDE_Msk (0x100000UL)       /*!< PWRSWVDDMDSP0OVERRIDE (Bitfield-Mask: 0x01)           */
41546 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Pos (19UL)              /*!< PWRSWVDDMDSP0STATSEL (Bit 19)                         */
41547 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Msk (0x80000UL)         /*!< PWRSWVDDMDSP0STATSEL (Bitfield-Mask: 0x01)            */
41548 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0DYNSEL_Pos (18UL)               /*!< PWRSWVDDMDSP0DYNSEL (Bit 18)                          */
41549 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0DYNSEL_Msk (0x40000UL)          /*!< PWRSWVDDMDSP0DYNSEL (Bitfield-Mask: 0x01)             */
41550 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUOVERRIDE_Pos (17UL)              /*!< PWRSWVDDMCPUOVERRIDE (Bit 17)                         */
41551 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUOVERRIDE_Msk (0x20000UL)         /*!< PWRSWVDDMCPUOVERRIDE (Bitfield-Mask: 0x01)            */
41552 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Pos (16UL)               /*!< PWRSWVDDMCPUSTATSEL (Bit 16)                          */
41553 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Msk (0x10000UL)          /*!< PWRSWVDDMCPUSTATSEL (Bitfield-Mask: 0x01)             */
41554 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUDYNSEL_Pos (15UL)                /*!< PWRSWVDDMCPUDYNSEL (Bit 15)                           */
41555 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUDYNSEL_Msk (0x8000UL)            /*!< PWRSWVDDMCPUDYNSEL (Bitfield-Mask: 0x01)              */
41556 #define MCUCTRL_PWRSW0_PWRSWVDDCAOROVERRIDE_Pos (6UL)               /*!< PWRSWVDDCAOROVERRIDE (Bit 6)                          */
41557 #define MCUCTRL_PWRSW0_PWRSWVDDCAOROVERRIDE_Msk (0x40UL)            /*!< PWRSWVDDCAOROVERRIDE (Bitfield-Mask: 0x01)            */
41558 #define MCUCTRL_PWRSW0_PWRSWVDDCAORDYNSEL_Pos (4UL)                 /*!< PWRSWVDDCAORDYNSEL (Bit 4)                            */
41559 #define MCUCTRL_PWRSW0_PWRSWVDDCAORDYNSEL_Msk (0x30UL)              /*!< PWRSWVDDCAORDYNSEL (Bitfield-Mask: 0x03)              */
41560 #define MCUCTRL_PWRSW0_PWRSWVDDCPUOVERRIDE_Pos (3UL)                /*!< PWRSWVDDCPUOVERRIDE (Bit 3)                           */
41561 #define MCUCTRL_PWRSW0_PWRSWVDDCPUOVERRIDE_Msk (0x8UL)              /*!< PWRSWVDDCPUOVERRIDE (Bitfield-Mask: 0x01)             */
41562 #define MCUCTRL_PWRSW0_PWRSWVDDCPUDYNSEL_Pos (0UL)                  /*!< PWRSWVDDCPUDYNSEL (Bit 0)                             */
41563 #define MCUCTRL_PWRSW0_PWRSWVDDCPUDYNSEL_Msk (0x3UL)                /*!< PWRSWVDDCPUDYNSEL (Bitfield-Mask: 0x03)               */
41564 /* ========================================================  PWRSW1  ========================================================= */
41565 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSORVAL_Pos (31UL)                /*!< SHORTVDDFVDDSORVAL (Bit 31)                           */
41566 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSORVAL_Msk (0x80000000UL)        /*!< SHORTVDDFVDDSORVAL (Bitfield-Mask: 0x01)              */
41567 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSOREN_Pos (30UL)                 /*!< SHORTVDDFVDDSOREN (Bit 30)                            */
41568 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSOREN_Msk (0x40000000UL)         /*!< SHORTVDDFVDDSOREN (Bitfield-Mask: 0x01)               */
41569 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVORVAL_Pos (29UL)              /*!< SHORTVDDCVDDCLVORVAL (Bit 29)                         */
41570 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVORVAL_Msk (0x20000000UL)      /*!< SHORTVDDCVDDCLVORVAL (Bitfield-Mask: 0x01)            */
41571 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVOREN_Pos (28UL)               /*!< SHORTVDDCVDDCLVOREN (Bit 28)                          */
41572 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVOREN_Msk (0x10000000UL)       /*!< SHORTVDDCVDDCLVOREN (Bitfield-Mask: 0x01)             */
41573 #define MCUCTRL_PWRSW1_USEVDDF4VDDRCPUINHP_Pos (25UL)               /*!< USEVDDF4VDDRCPUINHP (Bit 25)                          */
41574 #define MCUCTRL_PWRSW1_USEVDDF4VDDRCPUINHP_Msk (0x2000000UL)        /*!< USEVDDF4VDDRCPUINHP (Bitfield-Mask: 0x01)             */
41575 /* ======================================================  FLASHWPROT0  ====================================================== */
41576 #define MCUCTRL_FLASHWPROT0_FW0BITS_Pos   (0UL)                     /*!< FW0BITS (Bit 0)                                       */
41577 #define MCUCTRL_FLASHWPROT0_FW0BITS_Msk   (0xffffffffUL)            /*!< FW0BITS (Bitfield-Mask: 0xffffffff)                   */
41578 /* ======================================================  FLASHWPROT1  ====================================================== */
41579 #define MCUCTRL_FLASHWPROT1_FW1BITS_Pos   (0UL)                     /*!< FW1BITS (Bit 0)                                       */
41580 #define MCUCTRL_FLASHWPROT1_FW1BITS_Msk   (0xffffffffUL)            /*!< FW1BITS (Bitfield-Mask: 0xffffffff)                   */
41581 /* ======================================================  FLASHWPROT2  ====================================================== */
41582 #define MCUCTRL_FLASHWPROT2_FW2BITS_Pos   (0UL)                     /*!< FW2BITS (Bit 0)                                       */
41583 #define MCUCTRL_FLASHWPROT2_FW2BITS_Msk   (0xffffffffUL)            /*!< FW2BITS (Bitfield-Mask: 0xffffffff)                   */
41584 /* ======================================================  FLASHWPROT3  ====================================================== */
41585 #define MCUCTRL_FLASHWPROT3_FW3BITS_Pos   (0UL)                     /*!< FW3BITS (Bit 0)                                       */
41586 #define MCUCTRL_FLASHWPROT3_FW3BITS_Msk   (0xffffffffUL)            /*!< FW3BITS (Bitfield-Mask: 0xffffffff)                   */
41587 /* ======================================================  FLASHRPROT0  ====================================================== */
41588 #define MCUCTRL_FLASHRPROT0_FR0BITS_Pos   (0UL)                     /*!< FR0BITS (Bit 0)                                       */
41589 #define MCUCTRL_FLASHRPROT0_FR0BITS_Msk   (0xffffffffUL)            /*!< FR0BITS (Bitfield-Mask: 0xffffffff)                   */
41590 /* ======================================================  FLASHRPROT1  ====================================================== */
41591 #define MCUCTRL_FLASHRPROT1_FR1BITS_Pos   (0UL)                     /*!< FR1BITS (Bit 0)                                       */
41592 #define MCUCTRL_FLASHRPROT1_FR1BITS_Msk   (0xffffffffUL)            /*!< FR1BITS (Bitfield-Mask: 0xffffffff)                   */
41593 /* ======================================================  FLASHRPROT2  ====================================================== */
41594 #define MCUCTRL_FLASHRPROT2_FR2BITS_Pos   (0UL)                     /*!< FR2BITS (Bit 0)                                       */
41595 #define MCUCTRL_FLASHRPROT2_FR2BITS_Msk   (0xffffffffUL)            /*!< FR2BITS (Bitfield-Mask: 0xffffffff)                   */
41596 /* ======================================================  FLASHRPROT3  ====================================================== */
41597 #define MCUCTRL_FLASHRPROT3_FR3BITS_Pos   (0UL)                     /*!< FR3BITS (Bit 0)                                       */
41598 #define MCUCTRL_FLASHRPROT3_FR3BITS_Msk   (0xffffffffUL)            /*!< FR3BITS (Bitfield-Mask: 0xffffffff)                   */
41599 /* =====================================================  DMASRAMWPROT0  ===================================================== */
41600 #define MCUCTRL_DMASRAMWPROT0_DMAWPROT0_Pos (0UL)                   /*!< DMAWPROT0 (Bit 0)                                     */
41601 #define MCUCTRL_DMASRAMWPROT0_DMAWPROT0_Msk (0xffffffffUL)          /*!< DMAWPROT0 (Bitfield-Mask: 0xffffffff)                 */
41602 /* =====================================================  DMASRAMWPROT1  ===================================================== */
41603 #define MCUCTRL_DMASRAMWPROT1_DMAWPROT1_Pos (0UL)                   /*!< DMAWPROT1 (Bit 0)                                     */
41604 #define MCUCTRL_DMASRAMWPROT1_DMAWPROT1_Msk (0xffffUL)              /*!< DMAWPROT1 (Bitfield-Mask: 0xffff)                     */
41605 /* =====================================================  DMASRAMRPROT0  ===================================================== */
41606 #define MCUCTRL_DMASRAMRPROT0_DMARPROT0_Pos (0UL)                   /*!< DMARPROT0 (Bit 0)                                     */
41607 #define MCUCTRL_DMASRAMRPROT0_DMARPROT0_Msk (0xffffffffUL)          /*!< DMARPROT0 (Bitfield-Mask: 0xffffffff)                 */
41608 /* =====================================================  DMASRAMRPROT1  ===================================================== */
41609 #define MCUCTRL_DMASRAMRPROT1_DMARPROT1_Pos (0UL)                   /*!< DMARPROT1 (Bit 0)                                     */
41610 #define MCUCTRL_DMASRAMRPROT1_DMARPROT1_Msk (0xffffUL)              /*!< DMARPROT1 (Bitfield-Mask: 0xffff)                     */
41611 /* ======================================================  USBPHYRESET  ====================================================== */
41612 #define MCUCTRL_USBPHYRESET_USBPHYUTMIRSTDIS_Pos (1UL)              /*!< USBPHYUTMIRSTDIS (Bit 1)                              */
41613 #define MCUCTRL_USBPHYRESET_USBPHYUTMIRSTDIS_Msk (0x2UL)            /*!< USBPHYUTMIRSTDIS (Bitfield-Mask: 0x01)                */
41614 #define MCUCTRL_USBPHYRESET_USBPHYPORRSTDIS_Pos (0UL)               /*!< USBPHYPORRSTDIS (Bit 0)                               */
41615 #define MCUCTRL_USBPHYRESET_USBPHYPORRSTDIS_Msk (0x1UL)             /*!< USBPHYPORRSTDIS (Bitfield-Mask: 0x01)                 */
41616 /* =====================================================  AUDADCPWRCTRL  ===================================================== */
41617 #define MCUCTRL_AUDADCPWRCTRL_AUDADCKEEPOUTEN_Pos (18UL)            /*!< AUDADCKEEPOUTEN (Bit 18)                              */
41618 #define MCUCTRL_AUDADCPWRCTRL_AUDADCKEEPOUTEN_Msk (0x40000UL)       /*!< AUDADCKEEPOUTEN (Bitfield-Mask: 0x01)                 */
41619 #define MCUCTRL_AUDADCPWRCTRL_AUDADCRFBUFSLWEN_Pos (17UL)           /*!< AUDADCRFBUFSLWEN (Bit 17)                             */
41620 #define MCUCTRL_AUDADCPWRCTRL_AUDADCRFBUFSLWEN_Msk (0x20000UL)      /*!< AUDADCRFBUFSLWEN (Bitfield-Mask: 0x01)                */
41621 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFEN_Pos (16UL)              /*!< AUDADCINBUFEN (Bit 16)                                */
41622 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFEN_Msk (0x10000UL)         /*!< AUDADCINBUFEN (Bitfield-Mask: 0x01)                   */
41623 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFSEL_Pos (14UL)             /*!< AUDADCINBUFSEL (Bit 14)                               */
41624 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFSEL_Msk (0xc000UL)         /*!< AUDADCINBUFSEL (Bitfield-Mask: 0x03)                  */
41625 #define MCUCTRL_AUDADCPWRCTRL_AUDADCVBATDIVEN_Pos (12UL)            /*!< AUDADCVBATDIVEN (Bit 12)                              */
41626 #define MCUCTRL_AUDADCPWRCTRL_AUDADCVBATDIVEN_Msk (0x1000UL)        /*!< AUDADCVBATDIVEN (Bitfield-Mask: 0x01)                 */
41627 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Pos (10UL)            /*!< VDDAUDADCRESETN (Bit 10)                              */
41628 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Msk (0x400UL)         /*!< VDDAUDADCRESETN (Bitfield-Mask: 0x01)                 */
41629 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Pos (9UL)         /*!< VDDAUDADCDIGISOLATE (Bit 9)                           */
41630 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Msk (0x200UL)     /*!< VDDAUDADCDIGISOLATE (Bitfield-Mask: 0x01)             */
41631 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Pos (8UL)         /*!< VDDAUDADCSARISOLATE (Bit 8)                           */
41632 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Msk (0x100UL)     /*!< VDDAUDADCSARISOLATE (Bitfield-Mask: 0x01)             */
41633 #define MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Pos (5UL)               /*!< AUDREFKEEPPEN (Bit 5)                                 */
41634 #define MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Msk (0x20UL)            /*!< AUDREFKEEPPEN (Bitfield-Mask: 0x01)                   */
41635 #define MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Pos (4UL)                /*!< AUDREFBUFPEN (Bit 4)                                  */
41636 #define MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Msk (0x10UL)             /*!< AUDREFBUFPEN (Bitfield-Mask: 0x01)                    */
41637 #define MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Pos (3UL)                   /*!< AUDBGTPEN (Bit 3)                                     */
41638 #define MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Msk (0x8UL)                 /*!< AUDBGTPEN (Bitfield-Mask: 0x01)                       */
41639 #define MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Pos (2UL)                 /*!< AUDADCBPSEN (Bit 2)                                   */
41640 #define MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Msk (0x4UL)               /*!< AUDADCBPSEN (Bitfield-Mask: 0x01)                     */
41641 #define MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Pos (1UL)                 /*!< AUDADCAPSEN (Bit 1)                                   */
41642 #define MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Msk (0x2UL)               /*!< AUDADCAPSEN (Bitfield-Mask: 0x01)                     */
41643 #define MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Pos (0UL)            /*!< AUDADCPWRCTRLSWE (Bit 0)                              */
41644 #define MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Msk (0x1UL)          /*!< AUDADCPWRCTRLSWE (Bitfield-Mask: 0x01)                */
41645 /* ========================================================  AUDIO1  ========================================================= */
41646 #define MCUCTRL_AUDIO1_MICBIASPDNB_Pos    (12UL)                    /*!< MICBIASPDNB (Bit 12)                                  */
41647 #define MCUCTRL_AUDIO1_MICBIASPDNB_Msk    (0x1000UL)                /*!< MICBIASPDNB (Bitfield-Mask: 0x01)                     */
41648 #define MCUCTRL_AUDIO1_MICBIASVOLTAGETRIM_Pos (6UL)                 /*!< MICBIASVOLTAGETRIM (Bit 6)                            */
41649 #define MCUCTRL_AUDIO1_MICBIASVOLTAGETRIM_Msk (0xfc0UL)             /*!< MICBIASVOLTAGETRIM (Bitfield-Mask: 0x3f)              */
41650 /* =====================================================  PGAADCIFCTRL  ====================================================== */
41651 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPSEL_Pos (13UL)            /*!< PGAADCIFVCOMPSEL (Bit 13)                             */
41652 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPSEL_Msk (0x6000UL)        /*!< PGAADCIFVCOMPSEL (Bitfield-Mask: 0x03)                */
41653 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPEN_Pos (12UL)             /*!< PGAADCIFVCOMPEN (Bit 12)                              */
41654 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPEN_Msk (0x1000UL)         /*!< PGAADCIFVCOMPEN (Bitfield-Mask: 0x01)                 */
41655 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBPDNB_Pos (6UL)              /*!< PGAADCIFCHBPDNB (Bit 6)                               */
41656 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBPDNB_Msk (0xc0UL)           /*!< PGAADCIFCHBPDNB (Bitfield-Mask: 0x03)                 */
41657 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBACTIVE_Pos (4UL)            /*!< PGAADCIFCHBACTIVE (Bit 4)                             */
41658 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBACTIVE_Msk (0x30UL)         /*!< PGAADCIFCHBACTIVE (Bitfield-Mask: 0x03)               */
41659 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAPDNB_Pos (2UL)              /*!< PGAADCIFCHAPDNB (Bit 2)                               */
41660 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAPDNB_Msk (0xcUL)            /*!< PGAADCIFCHAPDNB (Bitfield-Mask: 0x03)                 */
41661 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAACTIVE_Pos (0UL)            /*!< PGAADCIFCHAACTIVE (Bit 0)                             */
41662 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAACTIVE_Msk (0x3UL)          /*!< PGAADCIFCHAACTIVE (Bitfield-Mask: 0x03)               */
41663 /* =======================================================  PGACTRL1  ======================================================== */
41664 #define MCUCTRL_PGACTRL1_PGAGAINAOVRD_Pos (31UL)                    /*!< PGAGAINAOVRD (Bit 31)                                 */
41665 #define MCUCTRL_PGACTRL1_PGAGAINAOVRD_Msk (0x80000000UL)            /*!< PGAGAINAOVRD (Bitfield-Mask: 0x01)                    */
41666 #define MCUCTRL_PGACTRL1_VCOMPSELPGA_Pos  (29UL)                    /*!< VCOMPSELPGA (Bit 29)                                  */
41667 #define MCUCTRL_PGACTRL1_VCOMPSELPGA_Msk  (0x20000000UL)            /*!< VCOMPSELPGA (Bitfield-Mask: 0x01)                     */
41668 #define MCUCTRL_PGACTRL1_PGAVREFGENQUICKSTARTEN_Pos (28UL)          /*!< PGAVREFGENQUICKSTARTEN (Bit 28)                       */
41669 #define MCUCTRL_PGACTRL1_PGAVREFGENQUICKSTARTEN_Msk (0x10000000UL)  /*!< PGAVREFGENQUICKSTARTEN (Bitfield-Mask: 0x01)          */
41670 #define MCUCTRL_PGACTRL1_PGAVREFGENPDNB_Pos (27UL)                  /*!< PGAVREFGENPDNB (Bit 27)                               */
41671 #define MCUCTRL_PGACTRL1_PGAVREFGENPDNB_Msk (0x8000000UL)           /*!< PGAVREFGENPDNB (Bitfield-Mask: 0x01)                  */
41672 #define MCUCTRL_PGACTRL1_PGAIREFGENPDNB_Pos (26UL)                  /*!< PGAIREFGENPDNB (Bit 26)                               */
41673 #define MCUCTRL_PGACTRL1_PGAIREFGENPDNB_Msk (0x4000000UL)           /*!< PGAIREFGENPDNB (Bitfield-Mask: 0x01)                  */
41674 #define MCUCTRL_PGACTRL1_PGACHAVCMGENQCHARGEEN_Pos (25UL)           /*!< PGACHAVCMGENQCHARGEEN (Bit 25)                        */
41675 #define MCUCTRL_PGACTRL1_PGACHAVCMGENQCHARGEEN_Msk (0x2000000UL)    /*!< PGACHAVCMGENQCHARGEEN (Bitfield-Mask: 0x01)           */
41676 #define MCUCTRL_PGACTRL1_PGACHAVCMGENPDNB_Pos (24UL)                /*!< PGACHAVCMGENPDNB (Bit 24)                             */
41677 #define MCUCTRL_PGACTRL1_PGACHAVCMGENPDNB_Msk (0x1000000UL)         /*!< PGACHAVCMGENPDNB (Bitfield-Mask: 0x01)                */
41678 #define MCUCTRL_PGACTRL1_PGACHAOPAMPOUTPDNB_Pos (22UL)              /*!< PGACHAOPAMPOUTPDNB (Bit 22)                           */
41679 #define MCUCTRL_PGACTRL1_PGACHAOPAMPOUTPDNB_Msk (0xc00000UL)        /*!< PGACHAOPAMPOUTPDNB (Bitfield-Mask: 0x03)              */
41680 #define MCUCTRL_PGACTRL1_PGACHAOPAMPINPDNB_Pos (20UL)               /*!< PGACHAOPAMPINPDNB (Bit 20)                            */
41681 #define MCUCTRL_PGACTRL1_PGACHAOPAMPINPDNB_Msk (0x300000UL)         /*!< PGACHAOPAMPINPDNB (Bitfield-Mask: 0x03)               */
41682 #define MCUCTRL_PGACTRL1_PGACHABYPASSEN_Pos (18UL)                  /*!< PGACHABYPASSEN (Bit 18)                               */
41683 #define MCUCTRL_PGACTRL1_PGACHABYPASSEN_Msk (0xc0000UL)             /*!< PGACHABYPASSEN (Bitfield-Mask: 0x03)                  */
41684 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2SEL_Pos (13UL)                 /*!< PGACHA1GAIN2SEL (Bit 13)                              */
41685 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2SEL_Msk (0x3e000UL)            /*!< PGACHA1GAIN2SEL (Bitfield-Mask: 0x1f)                 */
41686 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2DIV2SEL_Pos (12UL)             /*!< PGACHA1GAIN2DIV2SEL (Bit 12)                          */
41687 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2DIV2SEL_Msk (0x1000UL)         /*!< PGACHA1GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
41688 #define MCUCTRL_PGACTRL1_PGACHA1GAIN1SEL_Pos (9UL)                  /*!< PGACHA1GAIN1SEL (Bit 9)                               */
41689 #define MCUCTRL_PGACTRL1_PGACHA1GAIN1SEL_Msk (0xe00UL)              /*!< PGACHA1GAIN1SEL (Bitfield-Mask: 0x07)                 */
41690 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2SEL_Pos (4UL)                  /*!< PGACHA0GAIN2SEL (Bit 4)                               */
41691 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2SEL_Msk (0x1f0UL)              /*!< PGACHA0GAIN2SEL (Bitfield-Mask: 0x1f)                 */
41692 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2DIV2SEL_Pos (3UL)              /*!< PGACHA0GAIN2DIV2SEL (Bit 3)                           */
41693 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2DIV2SEL_Msk (0x8UL)            /*!< PGACHA0GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
41694 #define MCUCTRL_PGACTRL1_PGACHA0GAIN1SEL_Pos (0UL)                  /*!< PGACHA0GAIN1SEL (Bit 0)                               */
41695 #define MCUCTRL_PGACTRL1_PGACHA0GAIN1SEL_Msk (0x7UL)                /*!< PGACHA0GAIN1SEL (Bitfield-Mask: 0x07)                 */
41696 /* =======================================================  PGACTRL2  ======================================================== */
41697 #define MCUCTRL_PGACTRL2_PGAGAINBOVRD_Pos (31UL)                    /*!< PGAGAINBOVRD (Bit 31)                                 */
41698 #define MCUCTRL_PGACTRL2_PGAGAINBOVRD_Msk (0x80000000UL)            /*!< PGAGAINBOVRD (Bitfield-Mask: 0x01)                    */
41699 #define MCUCTRL_PGACTRL2_PGACHBVCMGENQCHARGEEN_Pos (25UL)           /*!< PGACHBVCMGENQCHARGEEN (Bit 25)                        */
41700 #define MCUCTRL_PGACTRL2_PGACHBVCMGENQCHARGEEN_Msk (0x2000000UL)    /*!< PGACHBVCMGENQCHARGEEN (Bitfield-Mask: 0x01)           */
41701 #define MCUCTRL_PGACTRL2_PGACHBVCMGENPDNB_Pos (24UL)                /*!< PGACHBVCMGENPDNB (Bit 24)                             */
41702 #define MCUCTRL_PGACTRL2_PGACHBVCMGENPDNB_Msk (0x1000000UL)         /*!< PGACHBVCMGENPDNB (Bitfield-Mask: 0x01)                */
41703 #define MCUCTRL_PGACTRL2_PGACHBOPAMPOUTPDNB_Pos (22UL)              /*!< PGACHBOPAMPOUTPDNB (Bit 22)                           */
41704 #define MCUCTRL_PGACTRL2_PGACHBOPAMPOUTPDNB_Msk (0xc00000UL)        /*!< PGACHBOPAMPOUTPDNB (Bitfield-Mask: 0x03)              */
41705 #define MCUCTRL_PGACTRL2_PGACHBOPAMPINPDNB_Pos (20UL)               /*!< PGACHBOPAMPINPDNB (Bit 20)                            */
41706 #define MCUCTRL_PGACTRL2_PGACHBOPAMPINPDNB_Msk (0x300000UL)         /*!< PGACHBOPAMPINPDNB (Bitfield-Mask: 0x03)               */
41707 #define MCUCTRL_PGACTRL2_PGACHBBYPASSEN_Pos (18UL)                  /*!< PGACHBBYPASSEN (Bit 18)                               */
41708 #define MCUCTRL_PGACTRL2_PGACHBBYPASSEN_Msk (0xc0000UL)             /*!< PGACHBBYPASSEN (Bitfield-Mask: 0x03)                  */
41709 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2SEL_Pos (13UL)                 /*!< PGACHB1GAIN2SEL (Bit 13)                              */
41710 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2SEL_Msk (0x3e000UL)            /*!< PGACHB1GAIN2SEL (Bitfield-Mask: 0x1f)                 */
41711 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2DIV2SEL_Pos (12UL)             /*!< PGACHB1GAIN2DIV2SEL (Bit 12)                          */
41712 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2DIV2SEL_Msk (0x1000UL)         /*!< PGACHB1GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
41713 #define MCUCTRL_PGACTRL2_PGACHB1GAIN1SEL_Pos (9UL)                  /*!< PGACHB1GAIN1SEL (Bit 9)                               */
41714 #define MCUCTRL_PGACTRL2_PGACHB1GAIN1SEL_Msk (0xe00UL)              /*!< PGACHB1GAIN1SEL (Bitfield-Mask: 0x07)                 */
41715 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2SEL_Pos (4UL)                  /*!< PGACHB0GAIN2SEL (Bit 4)                               */
41716 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2SEL_Msk (0x1f0UL)              /*!< PGACHB0GAIN2SEL (Bitfield-Mask: 0x1f)                 */
41717 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2DIV2SEL_Pos (3UL)              /*!< PGACHB0GAIN2DIV2SEL (Bit 3)                           */
41718 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2DIV2SEL_Msk (0x8UL)            /*!< PGACHB0GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
41719 #define MCUCTRL_PGACTRL2_PGACHB0GAIN1SEL_Pos (0UL)                  /*!< PGACHB0GAIN1SEL (Bit 0)                               */
41720 #define MCUCTRL_PGACTRL2_PGACHB0GAIN1SEL_Msk (0x7UL)                /*!< PGACHB0GAIN1SEL (Bitfield-Mask: 0x07)                 */
41721 /* =====================================================  AUDADCPWRDLY  ====================================================== */
41722 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR1_Pos (8UL)                   /*!< AUDADCPWR1 (Bit 8)                                    */
41723 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR1_Msk (0xff00UL)              /*!< AUDADCPWR1 (Bitfield-Mask: 0xff)                      */
41724 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR0_Pos (0UL)                   /*!< AUDADCPWR0 (Bit 0)                                    */
41725 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR0_Msk (0xffUL)                /*!< AUDADCPWR0 (Bitfield-Mask: 0xff)                      */
41726 /* =======================================================  SDIOCTRL  ======================================================== */
41727 #define MCUCTRL_SDIOCTRL_SDIODATOPENDRAINEN_Pos (18UL)              /*!< SDIODATOPENDRAINEN (Bit 18)                           */
41728 #define MCUCTRL_SDIOCTRL_SDIODATOPENDRAINEN_Msk (0x40000UL)         /*!< SDIODATOPENDRAINEN (Bitfield-Mask: 0x01)              */
41729 #define MCUCTRL_SDIOCTRL_SDIOCMDOPENDRAINEN_Pos (17UL)              /*!< SDIOCMDOPENDRAINEN (Bit 17)                           */
41730 #define MCUCTRL_SDIOCTRL_SDIOCMDOPENDRAINEN_Msk (0x20000UL)         /*!< SDIOCMDOPENDRAINEN (Bitfield-Mask: 0x01)              */
41731 #define MCUCTRL_SDIOCTRL_SDIOXINCLKSEL_Pos (15UL)                   /*!< SDIOXINCLKSEL (Bit 15)                                */
41732 #define MCUCTRL_SDIOCTRL_SDIOXINCLKSEL_Msk (0x18000UL)              /*!< SDIOXINCLKSEL (Bitfield-Mask: 0x03)                   */
41733 #define MCUCTRL_SDIOCTRL_SDIOASYNCWKUPENA_Pos (14UL)                /*!< SDIOASYNCWKUPENA (Bit 14)                             */
41734 #define MCUCTRL_SDIOCTRL_SDIOASYNCWKUPENA_Msk (0x4000UL)            /*!< SDIOASYNCWKUPENA (Bitfield-Mask: 0x01)                */
41735 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYSEL_Pos (10UL)                  /*!< SDIOOTAPDLYSEL (Bit 10)                               */
41736 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYSEL_Msk (0x3c00UL)              /*!< SDIOOTAPDLYSEL (Bitfield-Mask: 0x0f)                  */
41737 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYENA_Pos (9UL)                   /*!< SDIOOTAPDLYENA (Bit 9)                                */
41738 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYENA_Msk (0x200UL)               /*!< SDIOOTAPDLYENA (Bitfield-Mask: 0x01)                  */
41739 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYSEL_Pos (4UL)                   /*!< SDIOITAPDLYSEL (Bit 4)                                */
41740 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYSEL_Msk (0x1f0UL)               /*!< SDIOITAPDLYSEL (Bitfield-Mask: 0x1f)                  */
41741 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYENA_Pos (3UL)                   /*!< SDIOITAPDLYENA (Bit 3)                                */
41742 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYENA_Msk (0x8UL)                 /*!< SDIOITAPDLYENA (Bitfield-Mask: 0x01)                  */
41743 #define MCUCTRL_SDIOCTRL_SDIOITAPCHGWIN_Pos (2UL)                   /*!< SDIOITAPCHGWIN (Bit 2)                                */
41744 #define MCUCTRL_SDIOCTRL_SDIOITAPCHGWIN_Msk (0x4UL)                 /*!< SDIOITAPCHGWIN (Bitfield-Mask: 0x01)                  */
41745 #define MCUCTRL_SDIOCTRL_SDIOXINCLKEN_Pos (1UL)                     /*!< SDIOXINCLKEN (Bit 1)                                  */
41746 #define MCUCTRL_SDIOCTRL_SDIOXINCLKEN_Msk (0x2UL)                   /*!< SDIOXINCLKEN (Bitfield-Mask: 0x01)                    */
41747 #define MCUCTRL_SDIOCTRL_SDIOSYSCLKEN_Pos (0UL)                     /*!< SDIOSYSCLKEN (Bit 0)                                  */
41748 #define MCUCTRL_SDIOCTRL_SDIOSYSCLKEN_Msk (0x1UL)                   /*!< SDIOSYSCLKEN (Bitfield-Mask: 0x01)                    */
41749 /* ========================================================  PDMCTRL  ======================================================== */
41750 #define MCUCTRL_PDMCTRL_PDMGLOBALEN_Pos   (0UL)                     /*!< PDMGLOBALEN (Bit 0)                                   */
41751 #define MCUCTRL_PDMCTRL_PDMGLOBALEN_Msk   (0x1UL)                   /*!< PDMGLOBALEN (Bitfield-Mask: 0x01)                     */
41752 
41753 
41754 /* =========================================================================================================================== */
41755 /* ================                                           MSPI0                                           ================ */
41756 /* =========================================================================================================================== */
41757 
41758 /* =========================================================  CTRL  ========================================================== */
41759 #define MSPI0_CTRL_XFERBYTES_Pos          (16UL)                    /*!< XFERBYTES (Bit 16)                                    */
41760 #define MSPI0_CTRL_XFERBYTES_Msk          (0xffff0000UL)            /*!< XFERBYTES (Bitfield-Mask: 0xffff)                     */
41761 #define MSPI0_CTRL_PIOMIXED_Pos           (13UL)                    /*!< PIOMIXED (Bit 13)                                     */
41762 #define MSPI0_CTRL_PIOMIXED_Msk           (0xe000UL)                /*!< PIOMIXED (Bitfield-Mask: 0x07)                        */
41763 #define MSPI0_CTRL_ENWLAT_Pos             (12UL)                    /*!< ENWLAT (Bit 12)                                       */
41764 #define MSPI0_CTRL_ENWLAT_Msk             (0x1000UL)                /*!< ENWLAT (Bitfield-Mask: 0x01)                          */
41765 #define MSPI0_CTRL_ENDCX_Pos              (11UL)                    /*!< ENDCX (Bit 11)                                        */
41766 #define MSPI0_CTRL_ENDCX_Msk              (0x800UL)                 /*!< ENDCX (Bitfield-Mask: 0x01)                           */
41767 #define MSPI0_CTRL_ENTURN_Pos             (10UL)                    /*!< ENTURN (Bit 10)                                       */
41768 #define MSPI0_CTRL_ENTURN_Msk             (0x400UL)                 /*!< ENTURN (Bitfield-Mask: 0x01)                          */
41769 #define MSPI0_CTRL_PIOSCRAMBLE_Pos        (9UL)                     /*!< PIOSCRAMBLE (Bit 9)                                   */
41770 #define MSPI0_CTRL_PIOSCRAMBLE_Msk        (0x200UL)                 /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01)                     */
41771 #define MSPI0_CTRL_BIGENDIAN_Pos          (8UL)                     /*!< BIGENDIAN (Bit 8)                                     */
41772 #define MSPI0_CTRL_BIGENDIAN_Msk          (0x100UL)                 /*!< BIGENDIAN (Bitfield-Mask: 0x01)                       */
41773 #define MSPI0_CTRL_TXRX_Pos               (7UL)                     /*!< TXRX (Bit 7)                                          */
41774 #define MSPI0_CTRL_TXRX_Msk               (0x80UL)                  /*!< TXRX (Bitfield-Mask: 0x01)                            */
41775 #define MSPI0_CTRL_SENDI_Pos              (6UL)                     /*!< SENDI (Bit 6)                                         */
41776 #define MSPI0_CTRL_SENDI_Msk              (0x40UL)                  /*!< SENDI (Bitfield-Mask: 0x01)                           */
41777 #define MSPI0_CTRL_SENDA_Pos              (5UL)                     /*!< SENDA (Bit 5)                                         */
41778 #define MSPI0_CTRL_SENDA_Msk              (0x20UL)                  /*!< SENDA (Bitfield-Mask: 0x01)                           */
41779 #define MSPI0_CTRL_PIODEV_Pos             (4UL)                     /*!< PIODEV (Bit 4)                                        */
41780 #define MSPI0_CTRL_PIODEV_Msk             (0x10UL)                  /*!< PIODEV (Bitfield-Mask: 0x01)                          */
41781 #define MSPI0_CTRL_BUSY_Pos               (2UL)                     /*!< BUSY (Bit 2)                                          */
41782 #define MSPI0_CTRL_BUSY_Msk               (0x4UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
41783 #define MSPI0_CTRL_STATUS_Pos             (1UL)                     /*!< STATUS (Bit 1)                                        */
41784 #define MSPI0_CTRL_STATUS_Msk             (0x2UL)                   /*!< STATUS (Bitfield-Mask: 0x01)                          */
41785 #define MSPI0_CTRL_START_Pos              (0UL)                     /*!< START (Bit 0)                                         */
41786 #define MSPI0_CTRL_START_Msk              (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
41787 /* =========================================================  ADDR  ========================================================== */
41788 #define MSPI0_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
41789 #define MSPI0_ADDR_ADDR_Msk               (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
41790 /* =========================================================  INSTR  ========================================================= */
41791 #define MSPI0_INSTR_INSTR_Pos             (0UL)                     /*!< INSTR (Bit 0)                                         */
41792 #define MSPI0_INSTR_INSTR_Msk             (0xffffUL)                /*!< INSTR (Bitfield-Mask: 0xffff)                         */
41793 /* ========================================================  TXFIFO  ========================================================= */
41794 #define MSPI0_TXFIFO_TXFIFO_Pos           (0UL)                     /*!< TXFIFO (Bit 0)                                        */
41795 #define MSPI0_TXFIFO_TXFIFO_Msk           (0xffffffffUL)            /*!< TXFIFO (Bitfield-Mask: 0xffffffff)                    */
41796 /* ========================================================  RXFIFO  ========================================================= */
41797 #define MSPI0_RXFIFO_RXFIFO_Pos           (0UL)                     /*!< RXFIFO (Bit 0)                                        */
41798 #define MSPI0_RXFIFO_RXFIFO_Msk           (0xffffffffUL)            /*!< RXFIFO (Bitfield-Mask: 0xffffffff)                    */
41799 /* =======================================================  TXENTRIES  ======================================================= */
41800 #define MSPI0_TXENTRIES_TXENTRIES_Pos     (0UL)                     /*!< TXENTRIES (Bit 0)                                     */
41801 #define MSPI0_TXENTRIES_TXENTRIES_Msk     (0x3fUL)                  /*!< TXENTRIES (Bitfield-Mask: 0x3f)                       */
41802 /* =======================================================  RXENTRIES  ======================================================= */
41803 #define MSPI0_RXENTRIES_RXENTRIES_Pos     (0UL)                     /*!< RXENTRIES (Bit 0)                                     */
41804 #define MSPI0_RXENTRIES_RXENTRIES_Msk     (0x3fUL)                  /*!< RXENTRIES (Bitfield-Mask: 0x3f)                       */
41805 /* =======================================================  THRESHOLD  ======================================================= */
41806 #define MSPI0_THRESHOLD_RXTHRESH_Pos      (8UL)                     /*!< RXTHRESH (Bit 8)                                      */
41807 #define MSPI0_THRESHOLD_RXTHRESH_Msk      (0x3f00UL)                /*!< RXTHRESH (Bitfield-Mask: 0x3f)                        */
41808 #define MSPI0_THRESHOLD_TXTHRESH_Pos      (0UL)                     /*!< TXTHRESH (Bit 0)                                      */
41809 #define MSPI0_THRESHOLD_TXTHRESH_Msk      (0x3fUL)                  /*!< TXTHRESH (Bitfield-Mask: 0x3f)                        */
41810 /* ========================================================  MSPICFG  ======================================================== */
41811 #define MSPI0_MSPICFG_PRSTN_Pos           (31UL)                    /*!< PRSTN (Bit 31)                                        */
41812 #define MSPI0_MSPICFG_PRSTN_Msk           (0x80000000UL)            /*!< PRSTN (Bitfield-Mask: 0x01)                           */
41813 #define MSPI0_MSPICFG_IPRSTN_Pos          (30UL)                    /*!< IPRSTN (Bit 30)                                       */
41814 #define MSPI0_MSPICFG_IPRSTN_Msk          (0x40000000UL)            /*!< IPRSTN (Bitfield-Mask: 0x01)                          */
41815 #define MSPI0_MSPICFG_FIFORESET_Pos       (29UL)                    /*!< FIFORESET (Bit 29)                                    */
41816 #define MSPI0_MSPICFG_FIFORESET_Msk       (0x20000000UL)            /*!< FIFORESET (Bitfield-Mask: 0x01)                       */
41817 #define MSPI0_MSPICFG_IOMSEL_Pos          (4UL)                     /*!< IOMSEL (Bit 4)                                        */
41818 #define MSPI0_MSPICFG_IOMSEL_Msk          (0xf0UL)                  /*!< IOMSEL (Bitfield-Mask: 0x0f)                          */
41819 #define MSPI0_MSPICFG_APBCLK_Pos          (0UL)                     /*!< APBCLK (Bit 0)                                        */
41820 #define MSPI0_MSPICFG_APBCLK_Msk          (0x1UL)                   /*!< APBCLK (Bitfield-Mask: 0x01)                          */
41821 /* =======================================================  PADOUTEN  ======================================================== */
41822 #define MSPI0_PADOUTEN_CLKOND4_Pos        (12UL)                    /*!< CLKOND4 (Bit 12)                                      */
41823 #define MSPI0_PADOUTEN_CLKOND4_Msk        (0x1000UL)                /*!< CLKOND4 (Bitfield-Mask: 0x01)                         */
41824 #define MSPI0_PADOUTEN_OUTEN_Pos          (0UL)                     /*!< OUTEN (Bit 0)                                         */
41825 #define MSPI0_PADOUTEN_OUTEN_Msk          (0x3ffUL)                 /*!< OUTEN (Bitfield-Mask: 0x3ff)                          */
41826 /* =======================================================  PADOVEREN  ======================================================= */
41827 #define MSPI0_PADOVEREN_OVERRIDEEN_Pos    (0UL)                     /*!< OVERRIDEEN (Bit 0)                                    */
41828 #define MSPI0_PADOVEREN_OVERRIDEEN_Msk    (0x3ffUL)                 /*!< OVERRIDEEN (Bitfield-Mask: 0x3ff)                     */
41829 /* ========================================================  PADOVER  ======================================================== */
41830 #define MSPI0_PADOVER_OVERRIDE_Pos        (0UL)                     /*!< OVERRIDE (Bit 0)                                      */
41831 #define MSPI0_PADOVER_OVERRIDE_Msk        (0x3ffUL)                 /*!< OVERRIDE (Bitfield-Mask: 0x3ff)                       */
41832 /* ========================================================  DEV0AXI  ======================================================== */
41833 #define MSPI0_DEV0AXI_BASE0_Pos           (16UL)                    /*!< BASE0 (Bit 16)                                        */
41834 #define MSPI0_DEV0AXI_BASE0_Msk           (0x3ff0000UL)             /*!< BASE0 (Bitfield-Mask: 0x3ff)                          */
41835 #define MSPI0_DEV0AXI_READONLY0_Pos       (4UL)                     /*!< READONLY0 (Bit 4)                                     */
41836 #define MSPI0_DEV0AXI_READONLY0_Msk       (0x10UL)                  /*!< READONLY0 (Bitfield-Mask: 0x01)                       */
41837 #define MSPI0_DEV0AXI_SIZE0_Pos           (0UL)                     /*!< SIZE0 (Bit 0)                                         */
41838 #define MSPI0_DEV0AXI_SIZE0_Msk           (0xfUL)                   /*!< SIZE0 (Bitfield-Mask: 0x0f)                           */
41839 /* ========================================================  DEV0CFG  ======================================================== */
41840 #define MSPI0_DEV0CFG_WRITELATENCY0_Pos   (26UL)                    /*!< WRITELATENCY0 (Bit 26)                                */
41841 #define MSPI0_DEV0CFG_WRITELATENCY0_Msk   (0xfc000000UL)            /*!< WRITELATENCY0 (Bitfield-Mask: 0x3f)                   */
41842 #define MSPI0_DEV0CFG_TXNEG0_Pos          (24UL)                    /*!< TXNEG0 (Bit 24)                                       */
41843 #define MSPI0_DEV0CFG_TXNEG0_Msk          (0x1000000UL)             /*!< TXNEG0 (Bitfield-Mask: 0x01)                          */
41844 #define MSPI0_DEV0CFG_RXNEG0_Pos          (23UL)                    /*!< RXNEG0 (Bit 23)                                       */
41845 #define MSPI0_DEV0CFG_RXNEG0_Msk          (0x800000UL)              /*!< RXNEG0 (Bitfield-Mask: 0x01)                          */
41846 #define MSPI0_DEV0CFG_RXCAP0_Pos          (22UL)                    /*!< RXCAP0 (Bit 22)                                       */
41847 #define MSPI0_DEV0CFG_RXCAP0_Msk          (0x400000UL)              /*!< RXCAP0 (Bitfield-Mask: 0x01)                          */
41848 #define MSPI0_DEV0CFG_CLKDIV0_Pos         (16UL)                    /*!< CLKDIV0 (Bit 16)                                      */
41849 #define MSPI0_DEV0CFG_CLKDIV0_Msk         (0x3f0000UL)              /*!< CLKDIV0 (Bitfield-Mask: 0x3f)                         */
41850 #define MSPI0_DEV0CFG_CPOL0_Pos           (15UL)                    /*!< CPOL0 (Bit 15)                                        */
41851 #define MSPI0_DEV0CFG_CPOL0_Msk           (0x8000UL)                /*!< CPOL0 (Bitfield-Mask: 0x01)                           */
41852 #define MSPI0_DEV0CFG_CPHA0_Pos           (14UL)                    /*!< CPHA0 (Bit 14)                                        */
41853 #define MSPI0_DEV0CFG_CPHA0_Msk           (0x4000UL)                /*!< CPHA0 (Bitfield-Mask: 0x01)                           */
41854 #define MSPI0_DEV0CFG_TURNAROUND0_Pos     (8UL)                     /*!< TURNAROUND0 (Bit 8)                                   */
41855 #define MSPI0_DEV0CFG_TURNAROUND0_Msk     (0x3f00UL)                /*!< TURNAROUND0 (Bitfield-Mask: 0x3f)                     */
41856 #define MSPI0_DEV0CFG_SEPIO0_Pos          (7UL)                     /*!< SEPIO0 (Bit 7)                                        */
41857 #define MSPI0_DEV0CFG_SEPIO0_Msk          (0x80UL)                  /*!< SEPIO0 (Bitfield-Mask: 0x01)                          */
41858 #define MSPI0_DEV0CFG_ISIZE0_Pos          (6UL)                     /*!< ISIZE0 (Bit 6)                                        */
41859 #define MSPI0_DEV0CFG_ISIZE0_Msk          (0x40UL)                  /*!< ISIZE0 (Bitfield-Mask: 0x01)                          */
41860 #define MSPI0_DEV0CFG_ASIZE0_Pos          (4UL)                     /*!< ASIZE0 (Bit 4)                                        */
41861 #define MSPI0_DEV0CFG_ASIZE0_Msk          (0x30UL)                  /*!< ASIZE0 (Bitfield-Mask: 0x03)                          */
41862 #define MSPI0_DEV0CFG_DEVCFG0_Pos         (0UL)                     /*!< DEVCFG0 (Bit 0)                                       */
41863 #define MSPI0_DEV0CFG_DEVCFG0_Msk         (0xfUL)                   /*!< DEVCFG0 (Bitfield-Mask: 0x0f)                         */
41864 /* ========================================================  DEV0DDR  ======================================================== */
41865 #define MSPI0_DEV0DDR_TXDQSDELAY0_Pos     (16UL)                    /*!< TXDQSDELAY0 (Bit 16)                                  */
41866 #define MSPI0_DEV0DDR_TXDQSDELAY0_Msk     (0x1f0000UL)              /*!< TXDQSDELAY0 (Bitfield-Mask: 0x1f)                     */
41867 #define MSPI0_DEV0DDR_RXDQSDELAY0_Pos     (8UL)                     /*!< RXDQSDELAY0 (Bit 8)                                   */
41868 #define MSPI0_DEV0DDR_RXDQSDELAY0_Msk     (0x1f00UL)                /*!< RXDQSDELAY0 (Bitfield-Mask: 0x1f)                     */
41869 #define MSPI0_DEV0DDR_ENABLEFINEDELAY0_Pos (6UL)                    /*!< ENABLEFINEDELAY0 (Bit 6)                              */
41870 #define MSPI0_DEV0DDR_ENABLEFINEDELAY0_Msk (0x40UL)                 /*!< ENABLEFINEDELAY0 (Bitfield-Mask: 0x01)                */
41871 #define MSPI0_DEV0DDR_OVERRIDEDDRCLKOUTDELAY0_Pos (5UL)             /*!< OVERRIDEDDRCLKOUTDELAY0 (Bit 5)                       */
41872 #define MSPI0_DEV0DDR_OVERRIDEDDRCLKOUTDELAY0_Msk (0x20UL)          /*!< OVERRIDEDDRCLKOUTDELAY0 (Bitfield-Mask: 0x01)         */
41873 #define MSPI0_DEV0DDR_OVERRIDERXDQSDELAY0_Pos (4UL)                 /*!< OVERRIDERXDQSDELAY0 (Bit 4)                           */
41874 #define MSPI0_DEV0DDR_OVERRIDERXDQSDELAY0_Msk (0x10UL)              /*!< OVERRIDERXDQSDELAY0 (Bitfield-Mask: 0x01)             */
41875 #define MSPI0_DEV0DDR_DQSSYNCNEG0_Pos     (3UL)                     /*!< DQSSYNCNEG0 (Bit 3)                                   */
41876 #define MSPI0_DEV0DDR_DQSSYNCNEG0_Msk     (0x8UL)                   /*!< DQSSYNCNEG0 (Bitfield-Mask: 0x01)                     */
41877 #define MSPI0_DEV0DDR_ENABLEDQS0_Pos      (2UL)                     /*!< ENABLEDQS0 (Bit 2)                                    */
41878 #define MSPI0_DEV0DDR_ENABLEDQS0_Msk      (0x4UL)                   /*!< ENABLEDQS0 (Bitfield-Mask: 0x01)                      */
41879 #define MSPI0_DEV0DDR_QUADDDR0_Pos        (1UL)                     /*!< QUADDDR0 (Bit 1)                                      */
41880 #define MSPI0_DEV0DDR_QUADDDR0_Msk        (0x2UL)                   /*!< QUADDDR0 (Bitfield-Mask: 0x01)                        */
41881 #define MSPI0_DEV0DDR_EMULATEDDR0_Pos     (0UL)                     /*!< EMULATEDDR0 (Bit 0)                                   */
41882 #define MSPI0_DEV0DDR_EMULATEDDR0_Msk     (0x1UL)                   /*!< EMULATEDDR0 (Bitfield-Mask: 0x01)                     */
41883 /* ========================================================  DEV0XIP  ======================================================== */
41884 #define MSPI0_DEV0XIP_XIPWRITELATENCY0_Pos (19UL)                   /*!< XIPWRITELATENCY0 (Bit 19)                             */
41885 #define MSPI0_DEV0XIP_XIPWRITELATENCY0_Msk (0x1f80000UL)            /*!< XIPWRITELATENCY0 (Bitfield-Mask: 0x3f)                */
41886 #define MSPI0_DEV0XIP_XIPTURNAROUND0_Pos  (13UL)                    /*!< XIPTURNAROUND0 (Bit 13)                               */
41887 #define MSPI0_DEV0XIP_XIPTURNAROUND0_Msk  (0x7e000UL)               /*!< XIPTURNAROUND0 (Bitfield-Mask: 0x3f)                  */
41888 #define MSPI0_DEV0XIP_XIPENWLAT0_Pos      (12UL)                    /*!< XIPENWLAT0 (Bit 12)                                   */
41889 #define MSPI0_DEV0XIP_XIPENWLAT0_Msk      (0x1000UL)                /*!< XIPENWLAT0 (Bitfield-Mask: 0x01)                      */
41890 #define MSPI0_DEV0XIP_XIPENDCX0_Pos       (11UL)                    /*!< XIPENDCX0 (Bit 11)                                    */
41891 #define MSPI0_DEV0XIP_XIPENDCX0_Msk       (0x800UL)                 /*!< XIPENDCX0 (Bitfield-Mask: 0x01)                       */
41892 #define MSPI0_DEV0XIP_XIPMIXED0_Pos       (8UL)                     /*!< XIPMIXED0 (Bit 8)                                     */
41893 #define MSPI0_DEV0XIP_XIPMIXED0_Msk       (0x700UL)                 /*!< XIPMIXED0 (Bitfield-Mask: 0x07)                       */
41894 #define MSPI0_DEV0XIP_XIPSENDI0_Pos       (7UL)                     /*!< XIPSENDI0 (Bit 7)                                     */
41895 #define MSPI0_DEV0XIP_XIPSENDI0_Msk       (0x80UL)                  /*!< XIPSENDI0 (Bitfield-Mask: 0x01)                       */
41896 #define MSPI0_DEV0XIP_XIPSENDA0_Pos       (6UL)                     /*!< XIPSENDA0 (Bit 6)                                     */
41897 #define MSPI0_DEV0XIP_XIPSENDA0_Msk       (0x40UL)                  /*!< XIPSENDA0 (Bitfield-Mask: 0x01)                       */
41898 #define MSPI0_DEV0XIP_XIPENTURN0_Pos      (5UL)                     /*!< XIPENTURN0 (Bit 5)                                    */
41899 #define MSPI0_DEV0XIP_XIPENTURN0_Msk      (0x20UL)                  /*!< XIPENTURN0 (Bitfield-Mask: 0x01)                      */
41900 #define MSPI0_DEV0XIP_XIPBIGENDIAN0_Pos   (4UL)                     /*!< XIPBIGENDIAN0 (Bit 4)                                 */
41901 #define MSPI0_DEV0XIP_XIPBIGENDIAN0_Msk   (0x10UL)                  /*!< XIPBIGENDIAN0 (Bitfield-Mask: 0x01)                   */
41902 #define MSPI0_DEV0XIP_XIPACK0_Pos         (2UL)                     /*!< XIPACK0 (Bit 2)                                       */
41903 #define MSPI0_DEV0XIP_XIPACK0_Msk         (0xcUL)                   /*!< XIPACK0 (Bitfield-Mask: 0x03)                         */
41904 #define MSPI0_DEV0XIP_XIPEN0_Pos          (0UL)                     /*!< XIPEN0 (Bit 0)                                        */
41905 #define MSPI0_DEV0XIP_XIPEN0_Msk          (0x1UL)                   /*!< XIPEN0 (Bitfield-Mask: 0x01)                          */
41906 /* =======================================================  DEV0INSTR  ======================================================= */
41907 #define MSPI0_DEV0INSTR_READINSTR0_Pos    (16UL)                    /*!< READINSTR0 (Bit 16)                                   */
41908 #define MSPI0_DEV0INSTR_READINSTR0_Msk    (0xffff0000UL)            /*!< READINSTR0 (Bitfield-Mask: 0xffff)                    */
41909 #define MSPI0_DEV0INSTR_WRITEINSTR0_Pos   (0UL)                     /*!< WRITEINSTR0 (Bit 0)                                   */
41910 #define MSPI0_DEV0INSTR_WRITEINSTR0_Msk   (0xffffUL)                /*!< WRITEINSTR0 (Bitfield-Mask: 0xffff)                   */
41911 /* =====================================================  DEV0BOUNDARY  ====================================================== */
41912 #define MSPI0_DEV0BOUNDARY_DMABOUND0_Pos  (12UL)                    /*!< DMABOUND0 (Bit 12)                                    */
41913 #define MSPI0_DEV0BOUNDARY_DMABOUND0_Msk  (0xf000UL)                /*!< DMABOUND0 (Bitfield-Mask: 0x0f)                       */
41914 #define MSPI0_DEV0BOUNDARY_DMATIMELIMIT0_Pos (0UL)                  /*!< DMATIMELIMIT0 (Bit 0)                                 */
41915 #define MSPI0_DEV0BOUNDARY_DMATIMELIMIT0_Msk (0xfffUL)              /*!< DMATIMELIMIT0 (Bitfield-Mask: 0xfff)                  */
41916 /* ====================================================  DEV0SCRAMBLING  ===================================================== */
41917 #define MSPI0_DEV0SCRAMBLING_SCRENABLE0_Pos (31UL)                  /*!< SCRENABLE0 (Bit 31)                                   */
41918 #define MSPI0_DEV0SCRAMBLING_SCRENABLE0_Msk (0x80000000UL)          /*!< SCRENABLE0 (Bitfield-Mask: 0x01)                      */
41919 #define MSPI0_DEV0SCRAMBLING_SCREND0_Pos  (16UL)                    /*!< SCREND0 (Bit 16)                                      */
41920 #define MSPI0_DEV0SCRAMBLING_SCREND0_Msk  (0x3ff0000UL)             /*!< SCREND0 (Bitfield-Mask: 0x3ff)                        */
41921 #define MSPI0_DEV0SCRAMBLING_SCRSTART0_Pos (0UL)                    /*!< SCRSTART0 (Bit 0)                                     */
41922 #define MSPI0_DEV0SCRAMBLING_SCRSTART0_Msk (0x3ffUL)                /*!< SCRSTART0 (Bitfield-Mask: 0x3ff)                      */
41923 /* ======================================================  DEV0XIPMISC  ====================================================== */
41924 #define MSPI0_DEV0XIPMISC_APNDODD0_Pos    (21UL)                    /*!< APNDODD0 (Bit 21)                                     */
41925 #define MSPI0_DEV0XIPMISC_APNDODD0_Msk    (0x200000UL)              /*!< APNDODD0 (Bitfield-Mask: 0x01)                        */
41926 #define MSPI0_DEV0XIPMISC_AFIFOLVL0_Pos   (16UL)                    /*!< AFIFOLVL0 (Bit 16)                                    */
41927 #define MSPI0_DEV0XIPMISC_AFIFOLVL0_Msk   (0x1f0000UL)              /*!< AFIFOLVL0 (Bitfield-Mask: 0x1f)                       */
41928 #define MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Pos (15UL)                   /*!< XIPBOUNDARY0 (Bit 15)                                 */
41929 #define MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Msk (0x8000UL)               /*!< XIPBOUNDARY0 (Bitfield-Mask: 0x01)                    */
41930 #define MSPI0_DEV0XIPMISC_BEON0_Pos       (14UL)                    /*!< BEON0 (Bit 14)                                        */
41931 #define MSPI0_DEV0XIPMISC_BEON0_Msk       (0x4000UL)                /*!< BEON0 (Bitfield-Mask: 0x01)                           */
41932 #define MSPI0_DEV0XIPMISC_BEPOL0_Pos      (13UL)                    /*!< BEPOL0 (Bit 13)                                       */
41933 #define MSPI0_DEV0XIPMISC_BEPOL0_Msk      (0x2000UL)                /*!< BEPOL0 (Bitfield-Mask: 0x01)                          */
41934 #define MSPI0_DEV0XIPMISC_XIPODD0_Pos     (12UL)                    /*!< XIPODD0 (Bit 12)                                      */
41935 #define MSPI0_DEV0XIPMISC_XIPODD0_Msk     (0x1000UL)                /*!< XIPODD0 (Bitfield-Mask: 0x01)                         */
41936 #define MSPI0_DEV0XIPMISC_CEBREAK0_Pos    (0UL)                     /*!< CEBREAK0 (Bit 0)                                      */
41937 #define MSPI0_DEV0XIPMISC_CEBREAK0_Msk    (0xfffUL)                 /*!< CEBREAK0 (Bitfield-Mask: 0xfff)                       */
41938 /* ========================================================  DMACFG  ========================================================= */
41939 #define MSPI0_DMACFG_DMAPWROFF_Pos        (18UL)                    /*!< DMAPWROFF (Bit 18)                                    */
41940 #define MSPI0_DMACFG_DMAPWROFF_Msk        (0x40000UL)               /*!< DMAPWROFF (Bitfield-Mask: 0x01)                       */
41941 #define MSPI0_DMACFG_DMAPRI_Pos           (4UL)                     /*!< DMAPRI (Bit 4)                                        */
41942 #define MSPI0_DMACFG_DMAPRI_Msk           (0x30UL)                  /*!< DMAPRI (Bitfield-Mask: 0x03)                          */
41943 #define MSPI0_DMACFG_DMADEV_Pos           (3UL)                     /*!< DMADEV (Bit 3)                                        */
41944 #define MSPI0_DMACFG_DMADEV_Msk           (0x8UL)                   /*!< DMADEV (Bitfield-Mask: 0x01)                          */
41945 #define MSPI0_DMACFG_DMADIR_Pos           (2UL)                     /*!< DMADIR (Bit 2)                                        */
41946 #define MSPI0_DMACFG_DMADIR_Msk           (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
41947 #define MSPI0_DMACFG_DMAEN_Pos            (0UL)                     /*!< DMAEN (Bit 0)                                         */
41948 #define MSPI0_DMACFG_DMAEN_Msk            (0x3UL)                   /*!< DMAEN (Bitfield-Mask: 0x03)                           */
41949 /* ========================================================  DMASTAT  ======================================================== */
41950 #define MSPI0_DMASTAT_SCRERR_Pos          (3UL)                     /*!< SCRERR (Bit 3)                                        */
41951 #define MSPI0_DMASTAT_SCRERR_Msk          (0x8UL)                   /*!< SCRERR (Bitfield-Mask: 0x01)                          */
41952 #define MSPI0_DMASTAT_DMAERR_Pos          (2UL)                     /*!< DMAERR (Bit 2)                                        */
41953 #define MSPI0_DMASTAT_DMAERR_Msk          (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
41954 #define MSPI0_DMASTAT_DMACPL_Pos          (1UL)                     /*!< DMACPL (Bit 1)                                        */
41955 #define MSPI0_DMASTAT_DMACPL_Msk          (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
41956 #define MSPI0_DMASTAT_DMATIP_Pos          (0UL)                     /*!< DMATIP (Bit 0)                                        */
41957 #define MSPI0_DMASTAT_DMATIP_Msk          (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
41958 /* ======================================================  DMATARGADDR  ====================================================== */
41959 #define MSPI0_DMATARGADDR_TARGADDR_Pos    (0UL)                     /*!< TARGADDR (Bit 0)                                      */
41960 #define MSPI0_DMATARGADDR_TARGADDR_Msk    (0xffffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0xffffffff)                  */
41961 /* ======================================================  DMADEVADDR  ======================================================= */
41962 #define MSPI0_DMADEVADDR_DEVADDR_Pos      (0UL)                     /*!< DEVADDR (Bit 0)                                       */
41963 #define MSPI0_DMADEVADDR_DEVADDR_Msk      (0xffffffffUL)            /*!< DEVADDR (Bitfield-Mask: 0xffffffff)                   */
41964 /* ======================================================  DMATOTCOUNT  ====================================================== */
41965 #define MSPI0_DMATOTCOUNT_TOTCOUNT_Pos    (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
41966 #define MSPI0_DMATOTCOUNT_TOTCOUNT_Msk    (0xffffffUL)              /*!< TOTCOUNT (Bitfield-Mask: 0xffffff)                    */
41967 /* =======================================================  DMABCOUNT  ======================================================= */
41968 #define MSPI0_DMABCOUNT_BCOUNT_Pos        (0UL)                     /*!< BCOUNT (Bit 0)                                        */
41969 #define MSPI0_DMABCOUNT_BCOUNT_Msk        (0xffUL)                  /*!< BCOUNT (Bitfield-Mask: 0xff)                          */
41970 /* =======================================================  DMATHRESH  ======================================================= */
41971 #define MSPI0_DMATHRESH_DMARXTHRESH_Pos   (8UL)                     /*!< DMARXTHRESH (Bit 8)                                   */
41972 #define MSPI0_DMATHRESH_DMARXTHRESH_Msk   (0x1f00UL)                /*!< DMARXTHRESH (Bitfield-Mask: 0x1f)                     */
41973 #define MSPI0_DMATHRESH_DMATXTHRESH_Pos   (0UL)                     /*!< DMATXTHRESH (Bit 0)                                   */
41974 #define MSPI0_DMATHRESH_DMATXTHRESH_Msk   (0x1fUL)                  /*!< DMATXTHRESH (Bitfield-Mask: 0x1f)                     */
41975 /* =========================================================  INTEN  ========================================================= */
41976 #define MSPI0_INTEN_SCRERR_Pos            (12UL)                    /*!< SCRERR (Bit 12)                                       */
41977 #define MSPI0_INTEN_SCRERR_Msk            (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
41978 #define MSPI0_INTEN_CQERR_Pos             (11UL)                    /*!< CQERR (Bit 11)                                        */
41979 #define MSPI0_INTEN_CQERR_Msk             (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
41980 #define MSPI0_INTEN_CQPAUSED_Pos          (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
41981 #define MSPI0_INTEN_CQPAUSED_Msk          (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
41982 #define MSPI0_INTEN_CQUPD_Pos             (9UL)                     /*!< CQUPD (Bit 9)                                         */
41983 #define MSPI0_INTEN_CQUPD_Msk             (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
41984 #define MSPI0_INTEN_CQCMP_Pos             (8UL)                     /*!< CQCMP (Bit 8)                                         */
41985 #define MSPI0_INTEN_CQCMP_Msk             (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
41986 #define MSPI0_INTEN_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
41987 #define MSPI0_INTEN_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
41988 #define MSPI0_INTEN_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
41989 #define MSPI0_INTEN_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
41990 #define MSPI0_INTEN_RXF_Pos               (5UL)                     /*!< RXF (Bit 5)                                           */
41991 #define MSPI0_INTEN_RXF_Msk               (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
41992 #define MSPI0_INTEN_RXO_Pos               (4UL)                     /*!< RXO (Bit 4)                                           */
41993 #define MSPI0_INTEN_RXO_Msk               (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
41994 #define MSPI0_INTEN_RXU_Pos               (3UL)                     /*!< RXU (Bit 3)                                           */
41995 #define MSPI0_INTEN_RXU_Msk               (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
41996 #define MSPI0_INTEN_TXO_Pos               (2UL)                     /*!< TXO (Bit 2)                                           */
41997 #define MSPI0_INTEN_TXO_Msk               (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
41998 #define MSPI0_INTEN_TXE_Pos               (1UL)                     /*!< TXE (Bit 1)                                           */
41999 #define MSPI0_INTEN_TXE_Msk               (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42000 #define MSPI0_INTEN_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42001 #define MSPI0_INTEN_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42002 /* ========================================================  INTSTAT  ======================================================== */
42003 #define MSPI0_INTSTAT_SCRERR_Pos          (12UL)                    /*!< SCRERR (Bit 12)                                       */
42004 #define MSPI0_INTSTAT_SCRERR_Msk          (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42005 #define MSPI0_INTSTAT_CQERR_Pos           (11UL)                    /*!< CQERR (Bit 11)                                        */
42006 #define MSPI0_INTSTAT_CQERR_Msk           (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
42007 #define MSPI0_INTSTAT_CQPAUSED_Pos        (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
42008 #define MSPI0_INTSTAT_CQPAUSED_Msk        (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42009 #define MSPI0_INTSTAT_CQUPD_Pos           (9UL)                     /*!< CQUPD (Bit 9)                                         */
42010 #define MSPI0_INTSTAT_CQUPD_Msk           (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
42011 #define MSPI0_INTSTAT_CQCMP_Pos           (8UL)                     /*!< CQCMP (Bit 8)                                         */
42012 #define MSPI0_INTSTAT_CQCMP_Msk           (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
42013 #define MSPI0_INTSTAT_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
42014 #define MSPI0_INTSTAT_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42015 #define MSPI0_INTSTAT_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
42016 #define MSPI0_INTSTAT_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
42017 #define MSPI0_INTSTAT_RXF_Pos             (5UL)                     /*!< RXF (Bit 5)                                           */
42018 #define MSPI0_INTSTAT_RXF_Msk             (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
42019 #define MSPI0_INTSTAT_RXO_Pos             (4UL)                     /*!< RXO (Bit 4)                                           */
42020 #define MSPI0_INTSTAT_RXO_Msk             (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
42021 #define MSPI0_INTSTAT_RXU_Pos             (3UL)                     /*!< RXU (Bit 3)                                           */
42022 #define MSPI0_INTSTAT_RXU_Msk             (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
42023 #define MSPI0_INTSTAT_TXO_Pos             (2UL)                     /*!< TXO (Bit 2)                                           */
42024 #define MSPI0_INTSTAT_TXO_Msk             (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
42025 #define MSPI0_INTSTAT_TXE_Pos             (1UL)                     /*!< TXE (Bit 1)                                           */
42026 #define MSPI0_INTSTAT_TXE_Msk             (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42027 #define MSPI0_INTSTAT_CMDCMP_Pos          (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42028 #define MSPI0_INTSTAT_CMDCMP_Msk          (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42029 /* ========================================================  INTCLR  ========================================================= */
42030 #define MSPI0_INTCLR_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
42031 #define MSPI0_INTCLR_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42032 #define MSPI0_INTCLR_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
42033 #define MSPI0_INTCLR_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
42034 #define MSPI0_INTCLR_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
42035 #define MSPI0_INTCLR_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42036 #define MSPI0_INTCLR_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
42037 #define MSPI0_INTCLR_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
42038 #define MSPI0_INTCLR_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
42039 #define MSPI0_INTCLR_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
42040 #define MSPI0_INTCLR_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
42041 #define MSPI0_INTCLR_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42042 #define MSPI0_INTCLR_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
42043 #define MSPI0_INTCLR_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
42044 #define MSPI0_INTCLR_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
42045 #define MSPI0_INTCLR_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
42046 #define MSPI0_INTCLR_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
42047 #define MSPI0_INTCLR_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
42048 #define MSPI0_INTCLR_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
42049 #define MSPI0_INTCLR_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
42050 #define MSPI0_INTCLR_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
42051 #define MSPI0_INTCLR_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
42052 #define MSPI0_INTCLR_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
42053 #define MSPI0_INTCLR_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42054 #define MSPI0_INTCLR_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42055 #define MSPI0_INTCLR_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42056 /* ========================================================  INTSET  ========================================================= */
42057 #define MSPI0_INTSET_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
42058 #define MSPI0_INTSET_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42059 #define MSPI0_INTSET_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
42060 #define MSPI0_INTSET_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
42061 #define MSPI0_INTSET_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
42062 #define MSPI0_INTSET_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42063 #define MSPI0_INTSET_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
42064 #define MSPI0_INTSET_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
42065 #define MSPI0_INTSET_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
42066 #define MSPI0_INTSET_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
42067 #define MSPI0_INTSET_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
42068 #define MSPI0_INTSET_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42069 #define MSPI0_INTSET_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
42070 #define MSPI0_INTSET_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
42071 #define MSPI0_INTSET_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
42072 #define MSPI0_INTSET_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
42073 #define MSPI0_INTSET_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
42074 #define MSPI0_INTSET_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
42075 #define MSPI0_INTSET_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
42076 #define MSPI0_INTSET_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
42077 #define MSPI0_INTSET_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
42078 #define MSPI0_INTSET_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
42079 #define MSPI0_INTSET_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
42080 #define MSPI0_INTSET_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42081 #define MSPI0_INTSET_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42082 #define MSPI0_INTSET_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42083 /* =========================================================  CQCFG  ========================================================= */
42084 #define MSPI0_CQCFG_CQAUTOCLEARMASK_Pos   (3UL)                     /*!< CQAUTOCLEARMASK (Bit 3)                               */
42085 #define MSPI0_CQCFG_CQAUTOCLEARMASK_Msk   (0x8UL)                   /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01)                 */
42086 #define MSPI0_CQCFG_CQPWROFF_Pos          (2UL)                     /*!< CQPWROFF (Bit 2)                                      */
42087 #define MSPI0_CQCFG_CQPWROFF_Msk          (0x4UL)                   /*!< CQPWROFF (Bitfield-Mask: 0x01)                        */
42088 #define MSPI0_CQCFG_CQPRI_Pos             (1UL)                     /*!< CQPRI (Bit 1)                                         */
42089 #define MSPI0_CQCFG_CQPRI_Msk             (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
42090 #define MSPI0_CQCFG_CQEN_Pos              (0UL)                     /*!< CQEN (Bit 0)                                          */
42091 #define MSPI0_CQCFG_CQEN_Msk              (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
42092 /* ========================================================  CQADDR  ========================================================= */
42093 #define MSPI0_CQADDR_CQADDR_Pos           (0UL)                     /*!< CQADDR (Bit 0)                                        */
42094 #define MSPI0_CQADDR_CQADDR_Msk           (0x1fffffffUL)            /*!< CQADDR (Bitfield-Mask: 0x1fffffff)                    */
42095 /* ========================================================  CQSTAT  ========================================================= */
42096 #define MSPI0_CQSTAT_CQPAUSED_Pos         (3UL)                     /*!< CQPAUSED (Bit 3)                                      */
42097 #define MSPI0_CQSTAT_CQPAUSED_Msk         (0x8UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42098 #define MSPI0_CQSTAT_CQERR_Pos            (2UL)                     /*!< CQERR (Bit 2)                                         */
42099 #define MSPI0_CQSTAT_CQERR_Msk            (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
42100 #define MSPI0_CQSTAT_CQCPL_Pos            (1UL)                     /*!< CQCPL (Bit 1)                                         */
42101 #define MSPI0_CQSTAT_CQCPL_Msk            (0x2UL)                   /*!< CQCPL (Bitfield-Mask: 0x01)                           */
42102 #define MSPI0_CQSTAT_CQTIP_Pos            (0UL)                     /*!< CQTIP (Bit 0)                                         */
42103 #define MSPI0_CQSTAT_CQTIP_Msk            (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
42104 /* ========================================================  CQFLAGS  ======================================================== */
42105 #define MSPI0_CQFLAGS_CQFLAGS_Pos         (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
42106 #define MSPI0_CQFLAGS_CQFLAGS_Msk         (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
42107 /* ======================================================  CQSETCLEAR  ======================================================= */
42108 #define MSPI0_CQSETCLEAR_CQFCLR_Pos       (16UL)                    /*!< CQFCLR (Bit 16)                                       */
42109 #define MSPI0_CQSETCLEAR_CQFCLR_Msk       (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
42110 #define MSPI0_CQSETCLEAR_CQFTOGGLE_Pos    (8UL)                     /*!< CQFTOGGLE (Bit 8)                                     */
42111 #define MSPI0_CQSETCLEAR_CQFTOGGLE_Msk    (0xff00UL)                /*!< CQFTOGGLE (Bitfield-Mask: 0xff)                       */
42112 #define MSPI0_CQSETCLEAR_CQFSET_Pos       (0UL)                     /*!< CQFSET (Bit 0)                                        */
42113 #define MSPI0_CQSETCLEAR_CQFSET_Msk       (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
42114 /* ========================================================  CQPAUSE  ======================================================== */
42115 #define MSPI0_CQPAUSE_CQMASK_Pos          (0UL)                     /*!< CQMASK (Bit 0)                                        */
42116 #define MSPI0_CQPAUSE_CQMASK_Msk          (0xffffUL)                /*!< CQMASK (Bitfield-Mask: 0xffff)                        */
42117 /* =======================================================  CQCURIDX  ======================================================== */
42118 #define MSPI0_CQCURIDX_CQCURIDX_Pos       (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
42119 #define MSPI0_CQCURIDX_CQCURIDX_Msk       (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
42120 /* =======================================================  CQENDIDX  ======================================================== */
42121 #define MSPI0_CQENDIDX_CQENDIDX_Pos       (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
42122 #define MSPI0_CQENDIDX_CQENDIDX_Msk       (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
42123 
42124 
42125 /* =========================================================================================================================== */
42126 /* ================                                           PDM0                                            ================ */
42127 /* =========================================================================================================================== */
42128 
42129 /* =========================================================  CTRL  ========================================================== */
42130 #define PDM0_CTRL_EN_Pos                  (6UL)                     /*!< EN (Bit 6)                                            */
42131 #define PDM0_CTRL_EN_Msk                  (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
42132 #define PDM0_CTRL_PCMPACK_Pos             (5UL)                     /*!< PCMPACK (Bit 5)                                       */
42133 #define PDM0_CTRL_PCMPACK_Msk             (0x20UL)                  /*!< PCMPACK (Bitfield-Mask: 0x01)                         */
42134 #define PDM0_CTRL_RSTB_Pos                (4UL)                     /*!< RSTB (Bit 4)                                          */
42135 #define PDM0_CTRL_RSTB_Msk                (0x10UL)                  /*!< RSTB (Bitfield-Mask: 0x01)                            */
42136 #define PDM0_CTRL_CLKSEL_Pos              (1UL)                     /*!< CLKSEL (Bit 1)                                        */
42137 #define PDM0_CTRL_CLKSEL_Msk              (0x6UL)                   /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
42138 #define PDM0_CTRL_CLKEN_Pos               (0UL)                     /*!< CLKEN (Bit 0)                                         */
42139 #define PDM0_CTRL_CLKEN_Msk               (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
42140 /* =======================================================  CORECFG0  ======================================================== */
42141 #define PDM0_CORECFG0_PGAR_Pos            (26UL)                    /*!< PGAR (Bit 26)                                         */
42142 #define PDM0_CORECFG0_PGAR_Msk            (0x7c000000UL)            /*!< PGAR (Bitfield-Mask: 0x1f)                            */
42143 #define PDM0_CORECFG0_PGAL_Pos            (21UL)                    /*!< PGAL (Bit 21)                                         */
42144 #define PDM0_CORECFG0_PGAL_Msk            (0x3e00000UL)             /*!< PGAL (Bitfield-Mask: 0x1f)                            */
42145 #define PDM0_CORECFG0_SINCRATE_Pos        (14UL)                    /*!< SINCRATE (Bit 14)                                     */
42146 #define PDM0_CORECFG0_SINCRATE_Msk        (0x1fc000UL)              /*!< SINCRATE (Bitfield-Mask: 0x7f)                        */
42147 #define PDM0_CORECFG0_MCLKDIV_Pos         (10UL)                    /*!< MCLKDIV (Bit 10)                                      */
42148 #define PDM0_CORECFG0_MCLKDIV_Msk         (0x3c00UL)                /*!< MCLKDIV (Bitfield-Mask: 0x0f)                         */
42149 #define PDM0_CORECFG0_ADCHPD_Pos          (9UL)                     /*!< ADCHPD (Bit 9)                                        */
42150 #define PDM0_CORECFG0_ADCHPD_Msk          (0x200UL)                 /*!< ADCHPD (Bitfield-Mask: 0x01)                          */
42151 #define PDM0_CORECFG0_HPGAIN_Pos          (5UL)                     /*!< HPGAIN (Bit 5)                                        */
42152 #define PDM0_CORECFG0_HPGAIN_Msk          (0x1e0UL)                 /*!< HPGAIN (Bitfield-Mask: 0x0f)                          */
42153 #define PDM0_CORECFG0_SCYCLES_Pos         (2UL)                     /*!< SCYCLES (Bit 2)                                       */
42154 #define PDM0_CORECFG0_SCYCLES_Msk         (0x1cUL)                  /*!< SCYCLES (Bitfield-Mask: 0x07)                         */
42155 #define PDM0_CORECFG0_SOFTMUTE_Pos        (1UL)                     /*!< SOFTMUTE (Bit 1)                                      */
42156 #define PDM0_CORECFG0_SOFTMUTE_Msk        (0x2UL)                   /*!< SOFTMUTE (Bitfield-Mask: 0x01)                        */
42157 #define PDM0_CORECFG0_LRSWAP_Pos          (0UL)                     /*!< LRSWAP (Bit 0)                                        */
42158 #define PDM0_CORECFG0_LRSWAP_Msk          (0x1UL)                   /*!< LRSWAP (Bitfield-Mask: 0x01)                          */
42159 /* =======================================================  CORECFG1  ======================================================== */
42160 #define PDM0_CORECFG1_SELSTEP_Pos         (7UL)                     /*!< SELSTEP (Bit 7)                                       */
42161 #define PDM0_CORECFG1_SELSTEP_Msk         (0x80UL)                  /*!< SELSTEP (Bitfield-Mask: 0x01)                         */
42162 #define PDM0_CORECFG1_CKODLY_Pos          (4UL)                     /*!< CKODLY (Bit 4)                                        */
42163 #define PDM0_CORECFG1_CKODLY_Msk          (0x70UL)                  /*!< CKODLY (Bitfield-Mask: 0x07)                          */
42164 #define PDM0_CORECFG1_DIVMCLKQ_Pos        (2UL)                     /*!< DIVMCLKQ (Bit 2)                                      */
42165 #define PDM0_CORECFG1_DIVMCLKQ_Msk        (0xcUL)                   /*!< DIVMCLKQ (Bitfield-Mask: 0x03)                        */
42166 #define PDM0_CORECFG1_PCMCHSET_Pos        (0UL)                     /*!< PCMCHSET (Bit 0)                                      */
42167 #define PDM0_CORECFG1_PCMCHSET_Msk        (0x3UL)                   /*!< PCMCHSET (Bitfield-Mask: 0x03)                        */
42168 /* =======================================================  CORECTRL  ======================================================== */
42169 #define PDM0_CORECTRL_CORECTRL_Pos        (0UL)                     /*!< CORECTRL (Bit 0)                                      */
42170 #define PDM0_CORECTRL_CORECTRL_Msk        (0xffffffffUL)            /*!< CORECTRL (Bitfield-Mask: 0xffffffff)                  */
42171 /* ========================================================  FIFOCNT  ======================================================== */
42172 #define PDM0_FIFOCNT_FIFOCNT_Pos          (0UL)                     /*!< FIFOCNT (Bit 0)                                       */
42173 #define PDM0_FIFOCNT_FIFOCNT_Msk          (0x3fUL)                  /*!< FIFOCNT (Bitfield-Mask: 0x3f)                         */
42174 /* =======================================================  FIFOREAD  ======================================================== */
42175 #define PDM0_FIFOREAD_FIFOREAD_Pos        (0UL)                     /*!< FIFOREAD (Bit 0)                                      */
42176 #define PDM0_FIFOREAD_FIFOREAD_Msk        (0xffffffffUL)            /*!< FIFOREAD (Bitfield-Mask: 0xffffffff)                  */
42177 /* =======================================================  FIFOFLUSH  ======================================================= */
42178 #define PDM0_FIFOFLUSH_FIFOFLUSH_Pos      (0UL)                     /*!< FIFOFLUSH (Bit 0)                                     */
42179 #define PDM0_FIFOFLUSH_FIFOFLUSH_Msk      (0x1UL)                   /*!< FIFOFLUSH (Bitfield-Mask: 0x01)                       */
42180 /* ========================================================  FIFOTHR  ======================================================== */
42181 #define PDM0_FIFOTHR_FIFOTHR_Pos          (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
42182 #define PDM0_FIFOTHR_FIFOTHR_Msk          (0x1fUL)                  /*!< FIFOTHR (Bitfield-Mask: 0x1f)                         */
42183 /* =========================================================  INTEN  ========================================================= */
42184 #define PDM0_INTEN_DERR_Pos               (4UL)                     /*!< DERR (Bit 4)                                          */
42185 #define PDM0_INTEN_DERR_Msk               (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42186 #define PDM0_INTEN_DCMP_Pos               (3UL)                     /*!< DCMP (Bit 3)                                          */
42187 #define PDM0_INTEN_DCMP_Msk               (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42188 #define PDM0_INTEN_UNDFL_Pos              (2UL)                     /*!< UNDFL (Bit 2)                                         */
42189 #define PDM0_INTEN_UNDFL_Msk              (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42190 #define PDM0_INTEN_OVF_Pos                (1UL)                     /*!< OVF (Bit 1)                                           */
42191 #define PDM0_INTEN_OVF_Msk                (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42192 #define PDM0_INTEN_THR_Pos                (0UL)                     /*!< THR (Bit 0)                                           */
42193 #define PDM0_INTEN_THR_Msk                (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42194 /* ========================================================  INTSTAT  ======================================================== */
42195 #define PDM0_INTSTAT_DERR_Pos             (4UL)                     /*!< DERR (Bit 4)                                          */
42196 #define PDM0_INTSTAT_DERR_Msk             (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42197 #define PDM0_INTSTAT_DCMP_Pos             (3UL)                     /*!< DCMP (Bit 3)                                          */
42198 #define PDM0_INTSTAT_DCMP_Msk             (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42199 #define PDM0_INTSTAT_UNDFL_Pos            (2UL)                     /*!< UNDFL (Bit 2)                                         */
42200 #define PDM0_INTSTAT_UNDFL_Msk            (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42201 #define PDM0_INTSTAT_OVF_Pos              (1UL)                     /*!< OVF (Bit 1)                                           */
42202 #define PDM0_INTSTAT_OVF_Msk              (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42203 #define PDM0_INTSTAT_THR_Pos              (0UL)                     /*!< THR (Bit 0)                                           */
42204 #define PDM0_INTSTAT_THR_Msk              (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42205 /* ========================================================  INTCLR  ========================================================= */
42206 #define PDM0_INTCLR_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
42207 #define PDM0_INTCLR_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42208 #define PDM0_INTCLR_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
42209 #define PDM0_INTCLR_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42210 #define PDM0_INTCLR_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
42211 #define PDM0_INTCLR_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42212 #define PDM0_INTCLR_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
42213 #define PDM0_INTCLR_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42214 #define PDM0_INTCLR_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
42215 #define PDM0_INTCLR_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42216 /* ========================================================  INTSET  ========================================================= */
42217 #define PDM0_INTSET_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
42218 #define PDM0_INTSET_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42219 #define PDM0_INTSET_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
42220 #define PDM0_INTSET_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42221 #define PDM0_INTSET_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
42222 #define PDM0_INTSET_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42223 #define PDM0_INTSET_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
42224 #define PDM0_INTSET_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42225 #define PDM0_INTSET_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
42226 #define PDM0_INTSET_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42227 /* =======================================================  DMATRIGEN  ======================================================= */
42228 #define PDM0_DMATRIGEN_DTHR90_Pos         (1UL)                     /*!< DTHR90 (Bit 1)                                        */
42229 #define PDM0_DMATRIGEN_DTHR90_Msk         (0x2UL)                   /*!< DTHR90 (Bitfield-Mask: 0x01)                          */
42230 #define PDM0_DMATRIGEN_DTHR_Pos           (0UL)                     /*!< DTHR (Bit 0)                                          */
42231 #define PDM0_DMATRIGEN_DTHR_Msk           (0x1UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
42232 /* ======================================================  DMATRIGSTAT  ====================================================== */
42233 #define PDM0_DMATRIGSTAT_DTHR90STAT_Pos   (1UL)                     /*!< DTHR90STAT (Bit 1)                                    */
42234 #define PDM0_DMATRIGSTAT_DTHR90STAT_Msk   (0x2UL)                   /*!< DTHR90STAT (Bitfield-Mask: 0x01)                      */
42235 #define PDM0_DMATRIGSTAT_DTHRSTAT_Pos     (0UL)                     /*!< DTHRSTAT (Bit 0)                                      */
42236 #define PDM0_DMATRIGSTAT_DTHRSTAT_Msk     (0x1UL)                   /*!< DTHRSTAT (Bitfield-Mask: 0x01)                        */
42237 /* ========================================================  DMACFG  ========================================================= */
42238 #define PDM0_DMACFG_DPWROFF_Pos           (10UL)                    /*!< DPWROFF (Bit 10)                                      */
42239 #define PDM0_DMACFG_DPWROFF_Msk           (0x400UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
42240 #define PDM0_DMACFG_DAUTOHIP_Pos          (9UL)                     /*!< DAUTOHIP (Bit 9)                                      */
42241 #define PDM0_DMACFG_DAUTOHIP_Msk          (0x200UL)                 /*!< DAUTOHIP (Bitfield-Mask: 0x01)                        */
42242 #define PDM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
42243 #define PDM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
42244 #define PDM0_DMACFG_DMADIR_Pos            (2UL)                     /*!< DMADIR (Bit 2)                                        */
42245 #define PDM0_DMACFG_DMADIR_Msk            (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
42246 #define PDM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
42247 #define PDM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
42248 /* ======================================================  DMATARGADDR  ====================================================== */
42249 #define PDM0_DMATARGADDR_UTARGADDR_Pos    (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
42250 #define PDM0_DMATARGADDR_UTARGADDR_Msk    (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
42251 #define PDM0_DMATARGADDR_LTARGADDR_Pos    (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
42252 #define PDM0_DMATARGADDR_LTARGADDR_Msk    (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
42253 /* ========================================================  DMASTAT  ======================================================== */
42254 #define PDM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
42255 #define PDM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
42256 #define PDM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
42257 #define PDM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
42258 #define PDM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
42259 #define PDM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
42260 /* ======================================================  DMATOTCOUNT  ====================================================== */
42261 #define PDM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
42262 #define PDM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffffUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xfffff)                     */
42263 
42264 
42265 /* =========================================================================================================================== */
42266 /* ================                                          PWRCTRL                                          ================ */
42267 /* =========================================================================================================================== */
42268 
42269 /* ======================================================  MCUPERFREQ  ======================================================= */
42270 #define PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Pos (3UL)                  /*!< MCUPERFSTATUS (Bit 3)                                 */
42271 #define PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Msk (0x18UL)               /*!< MCUPERFSTATUS (Bitfield-Mask: 0x03)                   */
42272 #define PWRCTRL_MCUPERFREQ_MCUPERFACK_Pos (2UL)                     /*!< MCUPERFACK (Bit 2)                                    */
42273 #define PWRCTRL_MCUPERFREQ_MCUPERFACK_Msk (0x4UL)                   /*!< MCUPERFACK (Bitfield-Mask: 0x01)                      */
42274 #define PWRCTRL_MCUPERFREQ_MCUPERFREQ_Pos (0UL)                     /*!< MCUPERFREQ (Bit 0)                                    */
42275 #define PWRCTRL_MCUPERFREQ_MCUPERFREQ_Msk (0x3UL)                   /*!< MCUPERFREQ (Bitfield-Mask: 0x03)                      */
42276 /* =======================================================  DEVPWREN  ======================================================== */
42277 #define PWRCTRL_DEVPWREN_PWRENDBG_Pos     (24UL)                    /*!< PWRENDBG (Bit 24)                                     */
42278 #define PWRCTRL_DEVPWREN_PWRENDBG_Msk     (0x1000000UL)             /*!< PWRENDBG (Bitfield-Mask: 0x01)                        */
42279 #define PWRCTRL_DEVPWREN_PWRENUSBPHY_Pos  (23UL)                    /*!< PWRENUSBPHY (Bit 23)                                  */
42280 #define PWRCTRL_DEVPWREN_PWRENUSBPHY_Msk  (0x800000UL)              /*!< PWRENUSBPHY (Bitfield-Mask: 0x01)                     */
42281 #define PWRCTRL_DEVPWREN_PWRENUSB_Pos     (22UL)                    /*!< PWRENUSB (Bit 22)                                     */
42282 #define PWRCTRL_DEVPWREN_PWRENUSB_Msk     (0x400000UL)              /*!< PWRENUSB (Bitfield-Mask: 0x01)                        */
42283 #define PWRCTRL_DEVPWREN_PWRENSDIO_Pos    (21UL)                    /*!< PWRENSDIO (Bit 21)                                    */
42284 #define PWRCTRL_DEVPWREN_PWRENSDIO_Msk    (0x200000UL)              /*!< PWRENSDIO (Bitfield-Mask: 0x01)                       */
42285 #define PWRCTRL_DEVPWREN_PWRENCRYPTO_Pos  (20UL)                    /*!< PWRENCRYPTO (Bit 20)                                  */
42286 #define PWRCTRL_DEVPWREN_PWRENCRYPTO_Msk  (0x100000UL)              /*!< PWRENCRYPTO (Bitfield-Mask: 0x01)                     */
42287 #define PWRCTRL_DEVPWREN_PWRENDISPPHY_Pos (19UL)                    /*!< PWRENDISPPHY (Bit 19)                                 */
42288 #define PWRCTRL_DEVPWREN_PWRENDISPPHY_Msk (0x80000UL)               /*!< PWRENDISPPHY (Bitfield-Mask: 0x01)                    */
42289 #define PWRCTRL_DEVPWREN_PWRENDISP_Pos    (18UL)                    /*!< PWRENDISP (Bit 18)                                    */
42290 #define PWRCTRL_DEVPWREN_PWRENDISP_Msk    (0x40000UL)               /*!< PWRENDISP (Bitfield-Mask: 0x01)                       */
42291 #define PWRCTRL_DEVPWREN_PWRENGFX_Pos     (17UL)                    /*!< PWRENGFX (Bit 17)                                     */
42292 #define PWRCTRL_DEVPWREN_PWRENGFX_Msk     (0x20000UL)               /*!< PWRENGFX (Bitfield-Mask: 0x01)                        */
42293 #define PWRCTRL_DEVPWREN_PWRENMSPI2_Pos   (16UL)                    /*!< PWRENMSPI2 (Bit 16)                                   */
42294 #define PWRCTRL_DEVPWREN_PWRENMSPI2_Msk   (0x10000UL)               /*!< PWRENMSPI2 (Bitfield-Mask: 0x01)                      */
42295 #define PWRCTRL_DEVPWREN_PWRENMSPI1_Pos   (15UL)                    /*!< PWRENMSPI1 (Bit 15)                                   */
42296 #define PWRCTRL_DEVPWREN_PWRENMSPI1_Msk   (0x8000UL)                /*!< PWRENMSPI1 (Bitfield-Mask: 0x01)                      */
42297 #define PWRCTRL_DEVPWREN_PWRENMSPI0_Pos   (14UL)                    /*!< PWRENMSPI0 (Bit 14)                                   */
42298 #define PWRCTRL_DEVPWREN_PWRENMSPI0_Msk   (0x4000UL)                /*!< PWRENMSPI0 (Bitfield-Mask: 0x01)                      */
42299 #define PWRCTRL_DEVPWREN_PWRENADC_Pos     (13UL)                    /*!< PWRENADC (Bit 13)                                     */
42300 #define PWRCTRL_DEVPWREN_PWRENADC_Msk     (0x2000UL)                /*!< PWRENADC (Bitfield-Mask: 0x01)                        */
42301 #define PWRCTRL_DEVPWREN_PWRENUART3_Pos   (12UL)                    /*!< PWRENUART3 (Bit 12)                                   */
42302 #define PWRCTRL_DEVPWREN_PWRENUART3_Msk   (0x1000UL)                /*!< PWRENUART3 (Bitfield-Mask: 0x01)                      */
42303 #define PWRCTRL_DEVPWREN_PWRENUART2_Pos   (11UL)                    /*!< PWRENUART2 (Bit 11)                                   */
42304 #define PWRCTRL_DEVPWREN_PWRENUART2_Msk   (0x800UL)                 /*!< PWRENUART2 (Bitfield-Mask: 0x01)                      */
42305 #define PWRCTRL_DEVPWREN_PWRENUART1_Pos   (10UL)                    /*!< PWRENUART1 (Bit 10)                                   */
42306 #define PWRCTRL_DEVPWREN_PWRENUART1_Msk   (0x400UL)                 /*!< PWRENUART1 (Bitfield-Mask: 0x01)                      */
42307 #define PWRCTRL_DEVPWREN_PWRENUART0_Pos   (9UL)                     /*!< PWRENUART0 (Bit 9)                                    */
42308 #define PWRCTRL_DEVPWREN_PWRENUART0_Msk   (0x200UL)                 /*!< PWRENUART0 (Bitfield-Mask: 0x01)                      */
42309 #define PWRCTRL_DEVPWREN_PWRENIOM7_Pos    (8UL)                     /*!< PWRENIOM7 (Bit 8)                                     */
42310 #define PWRCTRL_DEVPWREN_PWRENIOM7_Msk    (0x100UL)                 /*!< PWRENIOM7 (Bitfield-Mask: 0x01)                       */
42311 #define PWRCTRL_DEVPWREN_PWRENIOM6_Pos    (7UL)                     /*!< PWRENIOM6 (Bit 7)                                     */
42312 #define PWRCTRL_DEVPWREN_PWRENIOM6_Msk    (0x80UL)                  /*!< PWRENIOM6 (Bitfield-Mask: 0x01)                       */
42313 #define PWRCTRL_DEVPWREN_PWRENIOM5_Pos    (6UL)                     /*!< PWRENIOM5 (Bit 6)                                     */
42314 #define PWRCTRL_DEVPWREN_PWRENIOM5_Msk    (0x40UL)                  /*!< PWRENIOM5 (Bitfield-Mask: 0x01)                       */
42315 #define PWRCTRL_DEVPWREN_PWRENIOM4_Pos    (5UL)                     /*!< PWRENIOM4 (Bit 5)                                     */
42316 #define PWRCTRL_DEVPWREN_PWRENIOM4_Msk    (0x20UL)                  /*!< PWRENIOM4 (Bitfield-Mask: 0x01)                       */
42317 #define PWRCTRL_DEVPWREN_PWRENIOM3_Pos    (4UL)                     /*!< PWRENIOM3 (Bit 4)                                     */
42318 #define PWRCTRL_DEVPWREN_PWRENIOM3_Msk    (0x10UL)                  /*!< PWRENIOM3 (Bitfield-Mask: 0x01)                       */
42319 #define PWRCTRL_DEVPWREN_PWRENIOM2_Pos    (3UL)                     /*!< PWRENIOM2 (Bit 3)                                     */
42320 #define PWRCTRL_DEVPWREN_PWRENIOM2_Msk    (0x8UL)                   /*!< PWRENIOM2 (Bitfield-Mask: 0x01)                       */
42321 #define PWRCTRL_DEVPWREN_PWRENIOM1_Pos    (2UL)                     /*!< PWRENIOM1 (Bit 2)                                     */
42322 #define PWRCTRL_DEVPWREN_PWRENIOM1_Msk    (0x4UL)                   /*!< PWRENIOM1 (Bitfield-Mask: 0x01)                       */
42323 #define PWRCTRL_DEVPWREN_PWRENIOM0_Pos    (1UL)                     /*!< PWRENIOM0 (Bit 1)                                     */
42324 #define PWRCTRL_DEVPWREN_PWRENIOM0_Msk    (0x2UL)                   /*!< PWRENIOM0 (Bitfield-Mask: 0x01)                       */
42325 #define PWRCTRL_DEVPWREN_PWRENIOS_Pos     (0UL)                     /*!< PWRENIOS (Bit 0)                                      */
42326 #define PWRCTRL_DEVPWREN_PWRENIOS_Msk     (0x1UL)                   /*!< PWRENIOS (Bitfield-Mask: 0x01)                        */
42327 /* =====================================================  DEVPWRSTATUS  ====================================================== */
42328 #define PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Pos (24UL)                    /*!< PWRSTDBG (Bit 24)                                     */
42329 #define PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Msk (0x1000000UL)             /*!< PWRSTDBG (Bitfield-Mask: 0x01)                        */
42330 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_Pos (23UL)                 /*!< PWRSTUSBPHY (Bit 23)                                  */
42331 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_Msk (0x800000UL)           /*!< PWRSTUSBPHY (Bitfield-Mask: 0x01)                     */
42332 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSB_Pos (22UL)                    /*!< PWRSTUSB (Bit 22)                                     */
42333 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSB_Msk (0x400000UL)              /*!< PWRSTUSB (Bitfield-Mask: 0x01)                        */
42334 #define PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Pos (21UL)                   /*!< PWRSTSDIO (Bit 21)                                    */
42335 #define PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Msk (0x200000UL)             /*!< PWRSTSDIO (Bitfield-Mask: 0x01)                       */
42336 #define PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Pos (20UL)                 /*!< PWRSTCRYPTO (Bit 20)                                  */
42337 #define PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Msk (0x100000UL)           /*!< PWRSTCRYPTO (Bitfield-Mask: 0x01)                     */
42338 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_Pos (19UL)                /*!< PWRSTDISPPHY (Bit 19)                                 */
42339 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_Msk (0x80000UL)           /*!< PWRSTDISPPHY (Bitfield-Mask: 0x01)                    */
42340 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISP_Pos (18UL)                   /*!< PWRSTDISP (Bit 18)                                    */
42341 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISP_Msk (0x40000UL)              /*!< PWRSTDISP (Bitfield-Mask: 0x01)                       */
42342 #define PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Pos (17UL)                    /*!< PWRSTGFX (Bit 17)                                     */
42343 #define PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Msk (0x20000UL)               /*!< PWRSTGFX (Bitfield-Mask: 0x01)                        */
42344 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Pos (16UL)                  /*!< PWRSTMSPI2 (Bit 16)                                   */
42345 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Msk (0x10000UL)             /*!< PWRSTMSPI2 (Bitfield-Mask: 0x01)                      */
42346 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Pos (15UL)                  /*!< PWRSTMSPI1 (Bit 15)                                   */
42347 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Msk (0x8000UL)              /*!< PWRSTMSPI1 (Bitfield-Mask: 0x01)                      */
42348 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Pos (14UL)                  /*!< PWRSTMSPI0 (Bit 14)                                   */
42349 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Msk (0x4000UL)              /*!< PWRSTMSPI0 (Bitfield-Mask: 0x01)                      */
42350 #define PWRCTRL_DEVPWRSTATUS_PWRSTADC_Pos (13UL)                    /*!< PWRSTADC (Bit 13)                                     */
42351 #define PWRCTRL_DEVPWRSTATUS_PWRSTADC_Msk (0x2000UL)                /*!< PWRSTADC (Bitfield-Mask: 0x01)                        */
42352 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Pos (12UL)                  /*!< PWRSTUART3 (Bit 12)                                   */
42353 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Msk (0x1000UL)              /*!< PWRSTUART3 (Bitfield-Mask: 0x01)                      */
42354 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Pos (11UL)                  /*!< PWRSTUART2 (Bit 11)                                   */
42355 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Msk (0x800UL)               /*!< PWRSTUART2 (Bitfield-Mask: 0x01)                      */
42356 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Pos (10UL)                  /*!< PWRSTUART1 (Bit 10)                                   */
42357 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Msk (0x400UL)               /*!< PWRSTUART1 (Bitfield-Mask: 0x01)                      */
42358 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Pos (9UL)                   /*!< PWRSTUART0 (Bit 9)                                    */
42359 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Msk (0x200UL)               /*!< PWRSTUART0 (Bitfield-Mask: 0x01)                      */
42360 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Pos (8UL)                    /*!< PWRSTIOM7 (Bit 8)                                     */
42361 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Msk (0x100UL)                /*!< PWRSTIOM7 (Bitfield-Mask: 0x01)                       */
42362 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Pos (7UL)                    /*!< PWRSTIOM6 (Bit 7)                                     */
42363 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Msk (0x80UL)                 /*!< PWRSTIOM6 (Bitfield-Mask: 0x01)                       */
42364 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Pos (6UL)                    /*!< PWRSTIOM5 (Bit 6)                                     */
42365 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Msk (0x40UL)                 /*!< PWRSTIOM5 (Bitfield-Mask: 0x01)                       */
42366 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Pos (5UL)                    /*!< PWRSTIOM4 (Bit 5)                                     */
42367 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Msk (0x20UL)                 /*!< PWRSTIOM4 (Bitfield-Mask: 0x01)                       */
42368 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Pos (4UL)                    /*!< PWRSTIOM3 (Bit 4)                                     */
42369 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Msk (0x10UL)                 /*!< PWRSTIOM3 (Bitfield-Mask: 0x01)                       */
42370 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Pos (3UL)                    /*!< PWRSTIOM2 (Bit 3)                                     */
42371 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Msk (0x8UL)                  /*!< PWRSTIOM2 (Bitfield-Mask: 0x01)                       */
42372 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Pos (2UL)                    /*!< PWRSTIOM1 (Bit 2)                                     */
42373 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Msk (0x4UL)                  /*!< PWRSTIOM1 (Bitfield-Mask: 0x01)                       */
42374 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Pos (1UL)                    /*!< PWRSTIOM0 (Bit 1)                                     */
42375 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Msk (0x2UL)                  /*!< PWRSTIOM0 (Bitfield-Mask: 0x01)                       */
42376 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Pos (0UL)                     /*!< PWRSTIOS (Bit 0)                                      */
42377 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Msk (0x1UL)                   /*!< PWRSTIOS (Bitfield-Mask: 0x01)                        */
42378 /* ======================================================  AUDSSPWREN  ======================================================= */
42379 #define PWRCTRL_AUDSSPWREN_PWRENDSPA_Pos  (11UL)                    /*!< PWRENDSPA (Bit 11)                                    */
42380 #define PWRCTRL_AUDSSPWREN_PWRENDSPA_Msk  (0x800UL)                 /*!< PWRENDSPA (Bitfield-Mask: 0x01)                       */
42381 #define PWRCTRL_AUDSSPWREN_PWRENAUDADC_Pos (10UL)                   /*!< PWRENAUDADC (Bit 10)                                  */
42382 #define PWRCTRL_AUDSSPWREN_PWRENAUDADC_Msk (0x400UL)                /*!< PWRENAUDADC (Bitfield-Mask: 0x01)                     */
42383 #define PWRCTRL_AUDSSPWREN_PWRENI2S1_Pos  (7UL)                     /*!< PWRENI2S1 (Bit 7)                                     */
42384 #define PWRCTRL_AUDSSPWREN_PWRENI2S1_Msk  (0x80UL)                  /*!< PWRENI2S1 (Bitfield-Mask: 0x01)                       */
42385 #define PWRCTRL_AUDSSPWREN_PWRENI2S0_Pos  (6UL)                     /*!< PWRENI2S0 (Bit 6)                                     */
42386 #define PWRCTRL_AUDSSPWREN_PWRENI2S0_Msk  (0x40UL)                  /*!< PWRENI2S0 (Bitfield-Mask: 0x01)                       */
42387 #define PWRCTRL_AUDSSPWREN_PWRENPDM3_Pos  (5UL)                     /*!< PWRENPDM3 (Bit 5)                                     */
42388 #define PWRCTRL_AUDSSPWREN_PWRENPDM3_Msk  (0x20UL)                  /*!< PWRENPDM3 (Bitfield-Mask: 0x01)                       */
42389 #define PWRCTRL_AUDSSPWREN_PWRENPDM2_Pos  (4UL)                     /*!< PWRENPDM2 (Bit 4)                                     */
42390 #define PWRCTRL_AUDSSPWREN_PWRENPDM2_Msk  (0x10UL)                  /*!< PWRENPDM2 (Bitfield-Mask: 0x01)                       */
42391 #define PWRCTRL_AUDSSPWREN_PWRENPDM1_Pos  (3UL)                     /*!< PWRENPDM1 (Bit 3)                                     */
42392 #define PWRCTRL_AUDSSPWREN_PWRENPDM1_Msk  (0x8UL)                   /*!< PWRENPDM1 (Bitfield-Mask: 0x01)                       */
42393 #define PWRCTRL_AUDSSPWREN_PWRENPDM0_Pos  (2UL)                     /*!< PWRENPDM0 (Bit 2)                                     */
42394 #define PWRCTRL_AUDSSPWREN_PWRENPDM0_Msk  (0x4UL)                   /*!< PWRENPDM0 (Bitfield-Mask: 0x01)                       */
42395 #define PWRCTRL_AUDSSPWREN_PWRENAUDPB_Pos (1UL)                     /*!< PWRENAUDPB (Bit 1)                                    */
42396 #define PWRCTRL_AUDSSPWREN_PWRENAUDPB_Msk (0x2UL)                   /*!< PWRENAUDPB (Bitfield-Mask: 0x01)                      */
42397 #define PWRCTRL_AUDSSPWREN_PWRENAUDREC_Pos (0UL)                    /*!< PWRENAUDREC (Bit 0)                                   */
42398 #define PWRCTRL_AUDSSPWREN_PWRENAUDREC_Msk (0x1UL)                  /*!< PWRENAUDREC (Bitfield-Mask: 0x01)                     */
42399 /* ====================================================  AUDSSPWRSTATUS  ===================================================== */
42400 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_Pos (11UL)                 /*!< PWRSTDSPA (Bit 11)                                    */
42401 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_Msk (0x800UL)              /*!< PWRSTDSPA (Bitfield-Mask: 0x01)                       */
42402 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_Pos (10UL)               /*!< PWRSTAUDADC (Bit 10)                                  */
42403 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_Msk (0x400UL)            /*!< PWRSTAUDADC (Bitfield-Mask: 0x01)                     */
42404 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Pos (7UL)                  /*!< PWRSTI2S1 (Bit 7)                                     */
42405 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Msk (0x80UL)               /*!< PWRSTI2S1 (Bitfield-Mask: 0x01)                       */
42406 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Pos (6UL)                  /*!< PWRSTI2S0 (Bit 6)                                     */
42407 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Msk (0x40UL)               /*!< PWRSTI2S0 (Bitfield-Mask: 0x01)                       */
42408 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_Pos (5UL)                  /*!< PWRSTPDM3 (Bit 5)                                     */
42409 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_Msk (0x20UL)               /*!< PWRSTPDM3 (Bitfield-Mask: 0x01)                       */
42410 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_Pos (4UL)                  /*!< PWRSTPDM2 (Bit 4)                                     */
42411 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_Msk (0x10UL)               /*!< PWRSTPDM2 (Bitfield-Mask: 0x01)                       */
42412 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_Pos (3UL)                  /*!< PWRSTPDM1 (Bit 3)                                     */
42413 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_Msk (0x8UL)                /*!< PWRSTPDM1 (Bitfield-Mask: 0x01)                       */
42414 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Pos (2UL)                  /*!< PWRSTPDM0 (Bit 2)                                     */
42415 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Msk (0x4UL)                /*!< PWRSTPDM0 (Bitfield-Mask: 0x01)                       */
42416 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Pos (1UL)                 /*!< PWRSTAUDPB (Bit 1)                                    */
42417 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Msk (0x2UL)               /*!< PWRSTAUDPB (Bitfield-Mask: 0x01)                      */
42418 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Pos (0UL)                /*!< PWRSTAUDREC (Bit 0)                                   */
42419 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Msk (0x1UL)              /*!< PWRSTAUDREC (Bitfield-Mask: 0x01)                     */
42420 /* =======================================================  MEMPWREN  ======================================================== */
42421 #define PWRCTRL_MEMPWREN_PWRENCACHEB2_Pos (5UL)                     /*!< PWRENCACHEB2 (Bit 5)                                  */
42422 #define PWRCTRL_MEMPWREN_PWRENCACHEB2_Msk (0x20UL)                  /*!< PWRENCACHEB2 (Bitfield-Mask: 0x01)                    */
42423 #define PWRCTRL_MEMPWREN_PWRENCACHEB0_Pos (4UL)                     /*!< PWRENCACHEB0 (Bit 4)                                  */
42424 #define PWRCTRL_MEMPWREN_PWRENCACHEB0_Msk (0x10UL)                  /*!< PWRENCACHEB0 (Bitfield-Mask: 0x01)                    */
42425 #define PWRCTRL_MEMPWREN_PWRENNVM0_Pos    (3UL)                     /*!< PWRENNVM0 (Bit 3)                                     */
42426 #define PWRCTRL_MEMPWREN_PWRENNVM0_Msk    (0x8UL)                   /*!< PWRENNVM0 (Bitfield-Mask: 0x01)                       */
42427 #define PWRCTRL_MEMPWREN_PWRENDTCM_Pos    (0UL)                     /*!< PWRENDTCM (Bit 0)                                     */
42428 #define PWRCTRL_MEMPWREN_PWRENDTCM_Msk    (0x7UL)                   /*!< PWRENDTCM (Bitfield-Mask: 0x07)                       */
42429 /* =====================================================  MEMPWRSTATUS  ====================================================== */
42430 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB2_Pos (5UL)                 /*!< PWRSTCACHEB2 (Bit 5)                                  */
42431 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB2_Msk (0x20UL)              /*!< PWRSTCACHEB2 (Bitfield-Mask: 0x01)                    */
42432 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB0_Pos (4UL)                 /*!< PWRSTCACHEB0 (Bit 4)                                  */
42433 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB0_Msk (0x10UL)              /*!< PWRSTCACHEB0 (Bitfield-Mask: 0x01)                    */
42434 #define PWRCTRL_MEMPWRSTATUS_PWRSTNVM0_Pos (3UL)                    /*!< PWRSTNVM0 (Bit 3)                                     */
42435 #define PWRCTRL_MEMPWRSTATUS_PWRSTNVM0_Msk (0x8UL)                  /*!< PWRSTNVM0 (Bitfield-Mask: 0x01)                       */
42436 #define PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Pos (0UL)                    /*!< PWRSTDTCM (Bit 0)                                     */
42437 #define PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Msk (0x7UL)                  /*!< PWRSTDTCM (Bitfield-Mask: 0x07)                       */
42438 /* =======================================================  MEMRETCFG  ======================================================= */
42439 #define PWRCTRL_MEMRETCFG_CACHEPWDSLP_Pos (4UL)                     /*!< CACHEPWDSLP (Bit 4)                                   */
42440 #define PWRCTRL_MEMRETCFG_CACHEPWDSLP_Msk (0x10UL)                  /*!< CACHEPWDSLP (Bitfield-Mask: 0x01)                     */
42441 #define PWRCTRL_MEMRETCFG_NVM0PWDSLP_Pos  (3UL)                     /*!< NVM0PWDSLP (Bit 3)                                    */
42442 #define PWRCTRL_MEMRETCFG_NVM0PWDSLP_Msk  (0x8UL)                   /*!< NVM0PWDSLP (Bitfield-Mask: 0x01)                      */
42443 #define PWRCTRL_MEMRETCFG_DTCMPWDSLP_Pos  (0UL)                     /*!< DTCMPWDSLP (Bit 0)                                    */
42444 #define PWRCTRL_MEMRETCFG_DTCMPWDSLP_Msk  (0x7UL)                   /*!< DTCMPWDSLP (Bitfield-Mask: 0x07)                      */
42445 /* =====================================================  SYSPWRSTATUS  ====================================================== */
42446 #define PWRCTRL_SYSPWRSTATUS_SYSDEEPSLEEP_Pos (31UL)                /*!< SYSDEEPSLEEP (Bit 31)                                 */
42447 #define PWRCTRL_SYSPWRSTATUS_SYSDEEPSLEEP_Msk (0x80000000UL)        /*!< SYSDEEPSLEEP (Bitfield-Mask: 0x01)                    */
42448 #define PWRCTRL_SYSPWRSTATUS_COREDEEPSLEEP_Pos (30UL)               /*!< COREDEEPSLEEP (Bit 30)                                */
42449 #define PWRCTRL_SYSPWRSTATUS_COREDEEPSLEEP_Msk (0x40000000UL)       /*!< COREDEEPSLEEP (Bitfield-Mask: 0x01)                   */
42450 #define PWRCTRL_SYSPWRSTATUS_CORESLEEP_Pos (29UL)                   /*!< CORESLEEP (Bit 29)                                    */
42451 #define PWRCTRL_SYSPWRSTATUS_CORESLEEP_Msk (0x20000000UL)           /*!< CORESLEEP (Bitfield-Mask: 0x01)                       */
42452 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP1H_Pos (3UL)                   /*!< PWRSTDSP1H (Bit 3)                                    */
42453 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP1H_Msk (0x8UL)                 /*!< PWRSTDSP1H (Bitfield-Mask: 0x01)                      */
42454 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP0H_Pos (2UL)                   /*!< PWRSTDSP0H (Bit 2)                                    */
42455 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP0H_Msk (0x4UL)                 /*!< PWRSTDSP0H (Bitfield-Mask: 0x01)                      */
42456 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUH_Pos (1UL)                    /*!< PWRSTMCUH (Bit 1)                                     */
42457 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUH_Msk (0x2UL)                  /*!< PWRSTMCUH (Bitfield-Mask: 0x01)                       */
42458 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUL_Pos (0UL)                    /*!< PWRSTMCUL (Bit 0)                                     */
42459 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUL_Msk (0x1UL)                  /*!< PWRSTMCUL (Bitfield-Mask: 0x01)                       */
42460 /* ======================================================  SSRAMPWREN  ======================================================= */
42461 #define PWRCTRL_SSRAMPWREN_PWRENSSRAM_Pos (0UL)                     /*!< PWRENSSRAM (Bit 0)                                    */
42462 #define PWRCTRL_SSRAMPWREN_PWRENSSRAM_Msk (0x3UL)                   /*!< PWRENSSRAM (Bitfield-Mask: 0x03)                      */
42463 /* ======================================================  SSRAMPWRST  ======================================================= */
42464 #define PWRCTRL_SSRAMPWRST_SSRAMPWRST_Pos (0UL)                     /*!< SSRAMPWRST (Bit 0)                                    */
42465 #define PWRCTRL_SSRAMPWRST_SSRAMPWRST_Msk (0x3UL)                   /*!< SSRAMPWRST (Bitfield-Mask: 0x03)                      */
42466 /* ======================================================  SSRAMRETCFG  ====================================================== */
42467 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDISP_Pos (8UL)                  /*!< SSRAMACTDISP (Bit 8)                                  */
42468 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDISP_Msk (0x300UL)              /*!< SSRAMACTDISP (Bitfield-Mask: 0x03)                    */
42469 #define PWRCTRL_SSRAMRETCFG_SSRAMACTGFX_Pos (6UL)                   /*!< SSRAMACTGFX (Bit 6)                                   */
42470 #define PWRCTRL_SSRAMRETCFG_SSRAMACTGFX_Msk (0xc0UL)                /*!< SSRAMACTGFX (Bitfield-Mask: 0x03)                     */
42471 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDSP_Pos (4UL)                   /*!< SSRAMACTDSP (Bit 4)                                   */
42472 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDSP_Msk (0x30UL)                /*!< SSRAMACTDSP (Bitfield-Mask: 0x03)                     */
42473 #define PWRCTRL_SSRAMRETCFG_SSRAMACTMCU_Pos (2UL)                   /*!< SSRAMACTMCU (Bit 2)                                   */
42474 #define PWRCTRL_SSRAMRETCFG_SSRAMACTMCU_Msk (0xcUL)                 /*!< SSRAMACTMCU (Bitfield-Mask: 0x03)                     */
42475 #define PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Pos (0UL)                   /*!< SSRAMPWDSLP (Bit 0)                                   */
42476 #define PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Msk (0x3UL)                 /*!< SSRAMPWDSLP (Bitfield-Mask: 0x03)                     */
42477 /* =====================================================  DEVPWREVENTEN  ===================================================== */
42478 #define PWRCTRL_DEVPWREVENTEN_AUDEVEN_Pos (7UL)                     /*!< AUDEVEN (Bit 7)                                       */
42479 #define PWRCTRL_DEVPWREVENTEN_AUDEVEN_Msk (0x80UL)                  /*!< AUDEVEN (Bitfield-Mask: 0x01)                         */
42480 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL)                    /*!< MSPIEVEN (Bit 6)                                      */
42481 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL)                 /*!< MSPIEVEN (Bitfield-Mask: 0x01)                        */
42482 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL)                     /*!< ADCEVEN (Bit 5)                                       */
42483 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL)                  /*!< ADCEVEN (Bitfield-Mask: 0x01)                         */
42484 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL)                    /*!< HCPCEVEN (Bit 4)                                      */
42485 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL)                 /*!< HCPCEVEN (Bitfield-Mask: 0x01)                        */
42486 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL)                    /*!< HCPBEVEN (Bit 3)                                      */
42487 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL)                  /*!< HCPBEVEN (Bitfield-Mask: 0x01)                        */
42488 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL)                    /*!< HCPAEVEN (Bit 2)                                      */
42489 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL)                  /*!< HCPAEVEN (Bitfield-Mask: 0x01)                        */
42490 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL)                    /*!< MCUHEVEN (Bit 1)                                      */
42491 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL)                  /*!< MCUHEVEN (Bitfield-Mask: 0x01)                        */
42492 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL)                    /*!< MCULEVEN (Bit 0)                                      */
42493 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL)                  /*!< MCULEVEN (Bitfield-Mask: 0x01)                        */
42494 /* =====================================================  MEMPWREVENTEN  ===================================================== */
42495 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (5UL)                   /*!< CACHEB2EN (Bit 5)                                     */
42496 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x20UL)                /*!< CACHEB2EN (Bitfield-Mask: 0x01)                       */
42497 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (4UL)                   /*!< CACHEB0EN (Bit 4)                                     */
42498 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x10UL)                /*!< CACHEB0EN (Bitfield-Mask: 0x01)                       */
42499 #define PWRCTRL_MEMPWREVENTEN_NVM0EN_Pos  (3UL)                     /*!< NVM0EN (Bit 3)                                        */
42500 #define PWRCTRL_MEMPWREVENTEN_NVM0EN_Msk  (0x8UL)                   /*!< NVM0EN (Bitfield-Mask: 0x01)                          */
42501 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos  (0UL)                     /*!< DTCMEN (Bit 0)                                        */
42502 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk  (0x7UL)                   /*!< DTCMEN (Bitfield-Mask: 0x07)                          */
42503 /* ======================================================  MMSOVERRIDE  ====================================================== */
42504 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Pos (10UL)            /*!< MMSOVRSSRAMRETGFX (Bit 10)                            */
42505 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Msk (0xc00UL)         /*!< MMSOVRSSRAMRETGFX (Bitfield-Mask: 0x03)               */
42506 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Pos (8UL)            /*!< MMSOVRSSRAMRETDISP (Bit 8)                            */
42507 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Msk (0x300UL)        /*!< MMSOVRSSRAMRETDISP (Bitfield-Mask: 0x03)              */
42508 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Pos (6UL)            /*!< MMSOVRDSPRAMRETGFX (Bit 6)                            */
42509 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Msk (0xc0UL)         /*!< MMSOVRDSPRAMRETGFX (Bitfield-Mask: 0x03)              */
42510 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Pos (4UL)           /*!< MMSOVRDSPRAMRETDISP (Bit 4)                           */
42511 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Msk (0x30UL)        /*!< MMSOVRDSPRAMRETDISP (Bitfield-Mask: 0x03)             */
42512 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Pos (3UL)                /*!< MMSOVRSSRAMGFX (Bit 3)                                */
42513 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Msk (0x8UL)              /*!< MMSOVRSSRAMGFX (Bitfield-Mask: 0x01)                  */
42514 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Pos (2UL)               /*!< MMSOVRSSRAMDISP (Bit 2)                               */
42515 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Msk (0x4UL)             /*!< MMSOVRSSRAMDISP (Bitfield-Mask: 0x01)                 */
42516 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Pos (1UL)                 /*!< MMSOVRMCULGFX (Bit 1)                                 */
42517 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Msk (0x2UL)               /*!< MMSOVRMCULGFX (Bitfield-Mask: 0x01)                   */
42518 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Pos (0UL)                /*!< MMSOVRMCULDISP (Bit 0)                                */
42519 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Msk (0x1UL)              /*!< MMSOVRMCULDISP (Bitfield-Mask: 0x01)                  */
42520 /* ======================================================  DSP0PWRCTRL  ====================================================== */
42521 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Pos (4UL)                  /*!< DSP0PCMRSTOR (Bit 4)                                  */
42522 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Msk (0x10UL)               /*!< DSP0PCMRSTOR (Bitfield-Mask: 0x01)                    */
42523 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTDLY_Pos (0UL)                 /*!< DSP0PCMRSTDLY (Bit 0)                                 */
42524 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTDLY_Msk (0xfUL)               /*!< DSP0PCMRSTDLY (Bitfield-Mask: 0x0f)                   */
42525 /* ======================================================  DSP0PERFREQ  ====================================================== */
42526 #define PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Pos (3UL)                /*!< DSP0PERFSTATUS (Bit 3)                                */
42527 #define PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Msk (0x18UL)             /*!< DSP0PERFSTATUS (Bitfield-Mask: 0x03)                  */
42528 #define PWRCTRL_DSP0PERFREQ_DSP0PERFACK_Pos (2UL)                   /*!< DSP0PERFACK (Bit 2)                                   */
42529 #define PWRCTRL_DSP0PERFREQ_DSP0PERFACK_Msk (0x4UL)                 /*!< DSP0PERFACK (Bitfield-Mask: 0x01)                     */
42530 #define PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Pos (0UL)                   /*!< DSP0PERFREQ (Bit 0)                                   */
42531 #define PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Msk (0x3UL)                 /*!< DSP0PERFREQ (Bitfield-Mask: 0x03)                     */
42532 /* =====================================================  DSP0MEMPWREN  ====================================================== */
42533 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Pos (1UL)              /*!< PWRENDSP0ICACHE (Bit 1)                               */
42534 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Msk (0x2UL)            /*!< PWRENDSP0ICACHE (Bitfield-Mask: 0x01)                 */
42535 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Pos (0UL)                 /*!< PWRENDSP0RAM (Bit 0)                                  */
42536 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Msk (0x1UL)               /*!< PWRENDSP0RAM (Bitfield-Mask: 0x01)                    */
42537 /* =====================================================  DSP0MEMPWRST  ====================================================== */
42538 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0ICACHE_Pos (1UL)              /*!< PWRSTDSP0ICACHE (Bit 1)                               */
42539 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0ICACHE_Msk (0x2UL)            /*!< PWRSTDSP0ICACHE (Bitfield-Mask: 0x01)                 */
42540 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0RAM_Pos (0UL)                 /*!< PWRSTDSP0RAM (Bit 0)                                  */
42541 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0RAM_Msk (0x1UL)               /*!< PWRSTDSP0RAM (Bitfield-Mask: 0x01)                    */
42542 /* =====================================================  DSP0MEMRETCFG  ===================================================== */
42543 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Pos (4UL)               /*!< DSP0RAMACTGFX (Bit 4)                                 */
42544 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Msk (0x10UL)            /*!< DSP0RAMACTGFX (Bitfield-Mask: 0x01)                   */
42545 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Pos (3UL)              /*!< DSP0RAMACTDISP (Bit 3)                                */
42546 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Msk (0x8UL)            /*!< DSP0RAMACTDISP (Bitfield-Mask: 0x01)                  */
42547 #define PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Pos (2UL)            /*!< ICACHEPWDDSP0OFF (Bit 2)                              */
42548 #define PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Msk (0x4UL)          /*!< ICACHEPWDDSP0OFF (Bitfield-Mask: 0x01)                */
42549 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Pos (1UL)               /*!< DSP0RAMACTMCU (Bit 1)                                 */
42550 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Msk (0x2UL)             /*!< DSP0RAMACTMCU (Bitfield-Mask: 0x01)                   */
42551 #define PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Pos (0UL)               /*!< RAMPWDDSP0OFF (Bit 0)                                 */
42552 #define PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Msk (0x1UL)             /*!< RAMPWDDSP0OFF (Bitfield-Mask: 0x01)                   */
42553 /* ======================================================  DSP1PWRCTRL  ====================================================== */
42554 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Pos (4UL)                  /*!< DSP1PCMRSTOR (Bit 4)                                  */
42555 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Msk (0x10UL)               /*!< DSP1PCMRSTOR (Bitfield-Mask: 0x01)                    */
42556 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTDLY_Pos (0UL)                 /*!< DSP1PCMRSTDLY (Bit 0)                                 */
42557 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTDLY_Msk (0xfUL)               /*!< DSP1PCMRSTDLY (Bitfield-Mask: 0x0f)                   */
42558 /* ======================================================  DSP1PERFREQ  ====================================================== */
42559 #define PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Pos (3UL)                /*!< DSP1PERFSTATUS (Bit 3)                                */
42560 #define PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Msk (0x18UL)             /*!< DSP1PERFSTATUS (Bitfield-Mask: 0x03)                  */
42561 #define PWRCTRL_DSP1PERFREQ_DSP1PERFACK_Pos (2UL)                   /*!< DSP1PERFACK (Bit 2)                                   */
42562 #define PWRCTRL_DSP1PERFREQ_DSP1PERFACK_Msk (0x4UL)                 /*!< DSP1PERFACK (Bitfield-Mask: 0x01)                     */
42563 #define PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Pos (0UL)                   /*!< DSP1PERFREQ (Bit 0)                                   */
42564 #define PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Msk (0x3UL)                 /*!< DSP1PERFREQ (Bitfield-Mask: 0x03)                     */
42565 /* =====================================================  DSP1MEMPWREN  ====================================================== */
42566 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Pos (1UL)              /*!< PWRENDSP1ICACHE (Bit 1)                               */
42567 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Msk (0x2UL)            /*!< PWRENDSP1ICACHE (Bitfield-Mask: 0x01)                 */
42568 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Pos (0UL)                 /*!< PWRENDSP1RAM (Bit 0)                                  */
42569 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Msk (0x1UL)               /*!< PWRENDSP1RAM (Bitfield-Mask: 0x01)                    */
42570 /* =====================================================  DSP1MEMPWRST  ====================================================== */
42571 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1ICACHE_Pos (1UL)              /*!< PWRSTDSP1ICACHE (Bit 1)                               */
42572 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1ICACHE_Msk (0x2UL)            /*!< PWRSTDSP1ICACHE (Bitfield-Mask: 0x01)                 */
42573 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1RAM_Pos (0UL)                 /*!< PWRSTDSP1RAM (Bit 0)                                  */
42574 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1RAM_Msk (0x1UL)               /*!< PWRSTDSP1RAM (Bitfield-Mask: 0x01)                    */
42575 /* =====================================================  DSP1MEMRETCFG  ===================================================== */
42576 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Pos (4UL)               /*!< DSP1RAMACTGFX (Bit 4)                                 */
42577 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Msk (0x10UL)            /*!< DSP1RAMACTGFX (Bitfield-Mask: 0x01)                   */
42578 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Pos (3UL)              /*!< DSP1RAMACTDISP (Bit 3)                                */
42579 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Msk (0x8UL)            /*!< DSP1RAMACTDISP (Bitfield-Mask: 0x01)                  */
42580 #define PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Pos (2UL)            /*!< ICACHEPWDDSP1OFF (Bit 2)                              */
42581 #define PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Msk (0x4UL)          /*!< ICACHEPWDDSP1OFF (Bitfield-Mask: 0x01)                */
42582 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Pos (1UL)               /*!< DSP1RAMACTMCU (Bit 1)                                 */
42583 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Msk (0x2UL)             /*!< DSP1RAMACTMCU (Bitfield-Mask: 0x01)                   */
42584 #define PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Pos (0UL)               /*!< RAMPWDDSP1OFF (Bit 0)                                 */
42585 #define PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Msk (0x1UL)             /*!< RAMPWDDSP1OFF (Bitfield-Mask: 0x01)                   */
42586 /* ========================================================  VRCTRL  ========================================================= */
42587 #define PWRCTRL_VRCTRL_SIMOBUCKEN_Pos     (0UL)                     /*!< SIMOBUCKEN (Bit 0)                                    */
42588 #define PWRCTRL_VRCTRL_SIMOBUCKEN_Msk     (0x1UL)                   /*!< SIMOBUCKEN (Bitfield-Mask: 0x01)                      */
42589 /* =====================================================  LEGACYVRLPOVR  ===================================================== */
42590 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDBG_Pos (18UL)                  /*!< IGNOREDBG (Bit 18)                                    */
42591 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDBG_Msk (0x40000UL)             /*!< IGNOREDBG (Bitfield-Mask: 0x01)                       */
42592 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP1H_Pos (17UL)                /*!< IGNOREDSP1H (Bit 17)                                  */
42593 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP1H_Msk (0x20000UL)           /*!< IGNOREDSP1H (Bitfield-Mask: 0x01)                     */
42594 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP0H_Pos (16UL)                /*!< IGNOREDSP0H (Bit 16)                                  */
42595 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP0H_Msk (0x10000UL)           /*!< IGNOREDSP0H (Bitfield-Mask: 0x01)                     */
42596 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSPA_Pos (15UL)                 /*!< IGNOREDSPA (Bit 15)                                   */
42597 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSPA_Msk (0x8000UL)             /*!< IGNOREDSPA (Bitfield-Mask: 0x01)                      */
42598 #define PWRCTRL_LEGACYVRLPOVR_IGNOREAUD_Pos (14UL)                  /*!< IGNOREAUD (Bit 14)                                    */
42599 #define PWRCTRL_LEGACYVRLPOVR_IGNOREAUD_Msk (0x4000UL)              /*!< IGNOREAUD (Bitfield-Mask: 0x01)                       */
42600 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSBPHY_Pos (13UL)               /*!< IGNOREUSBPHY (Bit 13)                                 */
42601 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSBPHY_Msk (0x2000UL)           /*!< IGNOREUSBPHY (Bitfield-Mask: 0x01)                    */
42602 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSB_Pos (12UL)                  /*!< IGNOREUSB (Bit 12)                                    */
42603 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSB_Msk (0x1000UL)              /*!< IGNOREUSB (Bitfield-Mask: 0x01)                       */
42604 #define PWRCTRL_LEGACYVRLPOVR_IGNORESDIO_Pos (11UL)                 /*!< IGNORESDIO (Bit 11)                                   */
42605 #define PWRCTRL_LEGACYVRLPOVR_IGNORESDIO_Msk (0x800UL)              /*!< IGNORESDIO (Bitfield-Mask: 0x01)                      */
42606 #define PWRCTRL_LEGACYVRLPOVR_IGNORECRYPTO_Pos (10UL)               /*!< IGNORECRYPTO (Bit 10)                                 */
42607 #define PWRCTRL_LEGACYVRLPOVR_IGNORECRYPTO_Msk (0x400UL)            /*!< IGNORECRYPTO (Bitfield-Mask: 0x01)                    */
42608 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISPPHY_Pos (9UL)               /*!< IGNOREDISPPHY (Bit 9)                                 */
42609 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISPPHY_Msk (0x200UL)           /*!< IGNOREDISPPHY (Bitfield-Mask: 0x01)                   */
42610 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISP_Pos (8UL)                  /*!< IGNOREDISP (Bit 8)                                    */
42611 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISP_Msk (0x100UL)              /*!< IGNOREDISP (Bitfield-Mask: 0x01)                      */
42612 #define PWRCTRL_LEGACYVRLPOVR_IGNOREGFX_Pos (7UL)                   /*!< IGNOREGFX (Bit 7)                                     */
42613 #define PWRCTRL_LEGACYVRLPOVR_IGNOREGFX_Msk (0x80UL)                /*!< IGNOREGFX (Bitfield-Mask: 0x01)                       */
42614 #define PWRCTRL_LEGACYVRLPOVR_IGNOREMSPI_Pos (6UL)                  /*!< IGNOREMSPI (Bit 6)                                    */
42615 #define PWRCTRL_LEGACYVRLPOVR_IGNOREMSPI_Msk (0x40UL)               /*!< IGNOREMSPI (Bitfield-Mask: 0x01)                      */
42616 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPE_Pos (5UL)                  /*!< IGNOREHCPE (Bit 5)                                    */
42617 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPE_Msk (0x20UL)               /*!< IGNOREHCPE (Bitfield-Mask: 0x01)                      */
42618 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPD_Pos (4UL)                  /*!< IGNOREHCPD (Bit 4)                                    */
42619 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPD_Msk (0x10UL)               /*!< IGNOREHCPD (Bitfield-Mask: 0x01)                      */
42620 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPC_Pos (3UL)                  /*!< IGNOREHCPC (Bit 3)                                    */
42621 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPC_Msk (0x8UL)                /*!< IGNOREHCPC (Bitfield-Mask: 0x01)                      */
42622 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPB_Pos (2UL)                  /*!< IGNOREHCPB (Bit 2)                                    */
42623 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPB_Msk (0x4UL)                /*!< IGNOREHCPB (Bitfield-Mask: 0x01)                      */
42624 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPA_Pos (1UL)                  /*!< IGNOREHCPA (Bit 1)                                    */
42625 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPA_Msk (0x2UL)                /*!< IGNOREHCPA (Bitfield-Mask: 0x01)                      */
42626 #define PWRCTRL_LEGACYVRLPOVR_IGNOREIOS_Pos (0UL)                   /*!< IGNOREIOS (Bit 0)                                     */
42627 #define PWRCTRL_LEGACYVRLPOVR_IGNOREIOS_Msk (0x1UL)                 /*!< IGNOREIOS (Bitfield-Mask: 0x01)                       */
42628 /* =======================================================  VRSTATUS  ======================================================== */
42629 #define PWRCTRL_VRSTATUS_SIMOBUCKST_Pos   (4UL)                     /*!< SIMOBUCKST (Bit 4)                                    */
42630 #define PWRCTRL_VRSTATUS_SIMOBUCKST_Msk   (0x30UL)                  /*!< SIMOBUCKST (Bitfield-Mask: 0x03)                      */
42631 #define PWRCTRL_VRSTATUS_MEMLDOST_Pos     (2UL)                     /*!< MEMLDOST (Bit 2)                                      */
42632 #define PWRCTRL_VRSTATUS_MEMLDOST_Msk     (0xcUL)                   /*!< MEMLDOST (Bitfield-Mask: 0x03)                        */
42633 #define PWRCTRL_VRSTATUS_CORELDOST_Pos    (0UL)                     /*!< CORELDOST (Bit 0)                                     */
42634 #define PWRCTRL_VRSTATUS_CORELDOST_Msk    (0x3UL)                   /*!< CORELDOST (Bitfield-Mask: 0x03)                       */
42635 /* =====================================================  PWRWEIGHTULP0  ===================================================== */
42636 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART3_Pos (28UL)                 /*!< WTULPUART3 (Bit 28)                                   */
42637 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART3_Msk (0xf0000000UL)         /*!< WTULPUART3 (Bitfield-Mask: 0x0f)                      */
42638 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART2_Pos (24UL)                 /*!< WTULPUART2 (Bit 24)                                   */
42639 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART2_Msk (0xf000000UL)          /*!< WTULPUART2 (Bitfield-Mask: 0x0f)                      */
42640 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART1_Pos (20UL)                 /*!< WTULPUART1 (Bit 20)                                   */
42641 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART1_Msk (0xf00000UL)           /*!< WTULPUART1 (Bitfield-Mask: 0x0f)                      */
42642 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART0_Pos (16UL)                 /*!< WTULPUART0 (Bit 16)                                   */
42643 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART0_Msk (0xf0000UL)            /*!< WTULPUART0 (Bitfield-Mask: 0x0f)                      */
42644 #define PWRCTRL_PWRWEIGHTULP0_WTULPIOS_Pos (12UL)                   /*!< WTULPIOS (Bit 12)                                     */
42645 #define PWRCTRL_PWRWEIGHTULP0_WTULPIOS_Msk (0xf000UL)               /*!< WTULPIOS (Bitfield-Mask: 0x0f)                        */
42646 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP1_Pos (8UL)                   /*!< WTULPDSP1 (Bit 8)                                     */
42647 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP1_Msk (0xf00UL)               /*!< WTULPDSP1 (Bitfield-Mask: 0x0f)                       */
42648 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP0_Pos (4UL)                   /*!< WTULPDSP0 (Bit 4)                                     */
42649 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP0_Msk (0xf0UL)                /*!< WTULPDSP0 (Bitfield-Mask: 0x0f)                       */
42650 #define PWRCTRL_PWRWEIGHTULP0_WTULPMCU_Pos (0UL)                    /*!< WTULPMCU (Bit 0)                                      */
42651 #define PWRCTRL_PWRWEIGHTULP0_WTULPMCU_Msk (0xfUL)                  /*!< WTULPMCU (Bitfield-Mask: 0x0f)                        */
42652 /* =====================================================  PWRWEIGHTULP1  ===================================================== */
42653 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM7_Pos (28UL)                  /*!< WTULPIOM7 (Bit 28)                                    */
42654 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM7_Msk (0xf0000000UL)          /*!< WTULPIOM7 (Bitfield-Mask: 0x0f)                       */
42655 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM6_Pos (24UL)                  /*!< WTULPIOM6 (Bit 24)                                    */
42656 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM6_Msk (0xf000000UL)           /*!< WTULPIOM6 (Bitfield-Mask: 0x0f)                       */
42657 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM5_Pos (20UL)                  /*!< WTULPIOM5 (Bit 20)                                    */
42658 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM5_Msk (0xf00000UL)            /*!< WTULPIOM5 (Bitfield-Mask: 0x0f)                       */
42659 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM4_Pos (16UL)                  /*!< WTULPIOM4 (Bit 16)                                    */
42660 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM4_Msk (0xf0000UL)             /*!< WTULPIOM4 (Bitfield-Mask: 0x0f)                       */
42661 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM3_Pos (12UL)                  /*!< WTULPIOM3 (Bit 12)                                    */
42662 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM3_Msk (0xf000UL)              /*!< WTULPIOM3 (Bitfield-Mask: 0x0f)                       */
42663 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM2_Pos (8UL)                   /*!< WTULPIOM2 (Bit 8)                                     */
42664 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM2_Msk (0xf00UL)               /*!< WTULPIOM2 (Bitfield-Mask: 0x0f)                       */
42665 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM1_Pos (4UL)                   /*!< WTULPIOM1 (Bit 4)                                     */
42666 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM1_Msk (0xf0UL)                /*!< WTULPIOM1 (Bitfield-Mask: 0x0f)                       */
42667 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM0_Pos (0UL)                   /*!< WTULPIOM0 (Bit 0)                                     */
42668 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM0_Msk (0xfUL)                 /*!< WTULPIOM0 (Bitfield-Mask: 0x0f)                       */
42669 /* =====================================================  PWRWEIGHTULP2  ===================================================== */
42670 #define PWRCTRL_PWRWEIGHTULP2_WTULPUSB_Pos (28UL)                   /*!< WTULPUSB (Bit 28)                                     */
42671 #define PWRCTRL_PWRWEIGHTULP2_WTULPUSB_Msk (0xf0000000UL)           /*!< WTULPUSB (Bitfield-Mask: 0x0f)                        */
42672 #define PWRCTRL_PWRWEIGHTULP2_WTULPSDIO_Pos (24UL)                  /*!< WTULPSDIO (Bit 24)                                    */
42673 #define PWRCTRL_PWRWEIGHTULP2_WTULPSDIO_Msk (0xf000000UL)           /*!< WTULPSDIO (Bitfield-Mask: 0x0f)                       */
42674 #define PWRCTRL_PWRWEIGHTULP2_WTULPCRYPTO_Pos (20UL)                /*!< WTULPCRYPTO (Bit 20)                                  */
42675 #define PWRCTRL_PWRWEIGHTULP2_WTULPCRYPTO_Msk (0xf00000UL)          /*!< WTULPCRYPTO (Bitfield-Mask: 0x0f)                     */
42676 #define PWRCTRL_PWRWEIGHTULP2_WTULPDISP_Pos (16UL)                  /*!< WTULPDISP (Bit 16)                                    */
42677 #define PWRCTRL_PWRWEIGHTULP2_WTULPDISP_Msk (0xf0000UL)             /*!< WTULPDISP (Bitfield-Mask: 0x0f)                       */
42678 #define PWRCTRL_PWRWEIGHTULP2_WTULPGFX_Pos (12UL)                   /*!< WTULPGFX (Bit 12)                                     */
42679 #define PWRCTRL_PWRWEIGHTULP2_WTULPGFX_Msk (0xf000UL)               /*!< WTULPGFX (Bitfield-Mask: 0x0f)                        */
42680 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI1_Pos (8UL)                  /*!< WTULPMSPI1 (Bit 8)                                    */
42681 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI1_Msk (0xf00UL)              /*!< WTULPMSPI1 (Bitfield-Mask: 0x0f)                      */
42682 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI0_Pos (4UL)                  /*!< WTULPMSPI0 (Bit 4)                                    */
42683 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI0_Msk (0xf0UL)               /*!< WTULPMSPI0 (Bitfield-Mask: 0x0f)                      */
42684 #define PWRCTRL_PWRWEIGHTULP2_WTULPADC_Pos (0UL)                    /*!< WTULPADC (Bit 0)                                      */
42685 #define PWRCTRL_PWRWEIGHTULP2_WTULPADC_Msk (0xfUL)                  /*!< WTULPADC (Bitfield-Mask: 0x0f)                        */
42686 /* =====================================================  PWRWEIGHTULP3  ===================================================== */
42687 #define PWRCTRL_PWRWEIGHTULP3_WTULPMSPI2_Pos (28UL)                 /*!< WTULPMSPI2 (Bit 28)                                   */
42688 #define PWRCTRL_PWRWEIGHTULP3_WTULPMSPI2_Msk (0xf0000000UL)         /*!< WTULPMSPI2 (Bitfield-Mask: 0x0f)                      */
42689 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDADC_Pos (16UL)                /*!< WTULPAUDADC (Bit 16)                                  */
42690 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDADC_Msk (0xf0000UL)           /*!< WTULPAUDADC (Bitfield-Mask: 0x0f)                     */
42691 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDPB_Pos (12UL)                 /*!< WTULPAUDPB (Bit 12)                                   */
42692 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDPB_Msk (0xf000UL)             /*!< WTULPAUDPB (Bitfield-Mask: 0x0f)                      */
42693 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDREC_Pos (8UL)                 /*!< WTULPAUDREC (Bit 8)                                   */
42694 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDREC_Msk (0xf00UL)             /*!< WTULPAUDREC (Bitfield-Mask: 0x0f)                     */
42695 #define PWRCTRL_PWRWEIGHTULP3_WTULPDBG_Pos (4UL)                    /*!< WTULPDBG (Bit 4)                                      */
42696 #define PWRCTRL_PWRWEIGHTULP3_WTULPDBG_Msk (0xf0UL)                 /*!< WTULPDBG (Bitfield-Mask: 0x0f)                        */
42697 #define PWRCTRL_PWRWEIGHTULP3_WTULPDSPA_Pos (0UL)                   /*!< WTULPDSPA (Bit 0)                                     */
42698 #define PWRCTRL_PWRWEIGHTULP3_WTULPDSPA_Msk (0xfUL)                 /*!< WTULPDSPA (Bitfield-Mask: 0x0f)                       */
42699 /* =====================================================  PWRWEIGHTULP4  ===================================================== */
42700 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM3_Pos (28UL)                  /*!< WTULPPDM3 (Bit 28)                                    */
42701 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM3_Msk (0xf0000000UL)          /*!< WTULPPDM3 (Bitfield-Mask: 0x0f)                       */
42702 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM2_Pos (24UL)                  /*!< WTULPPDM2 (Bit 24)                                    */
42703 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM2_Msk (0xf000000UL)           /*!< WTULPPDM2 (Bitfield-Mask: 0x0f)                       */
42704 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM1_Pos (20UL)                  /*!< WTULPPDM1 (Bit 20)                                    */
42705 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM1_Msk (0xf00000UL)            /*!< WTULPPDM1 (Bitfield-Mask: 0x0f)                       */
42706 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM0_Pos (16UL)                  /*!< WTULPPDM0 (Bit 16)                                    */
42707 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM0_Msk (0xf0000UL)             /*!< WTULPPDM0 (Bitfield-Mask: 0x0f)                       */
42708 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S1_Pos (4UL)                   /*!< WTULPI2S1 (Bit 4)                                     */
42709 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S1_Msk (0xf0UL)                /*!< WTULPI2S1 (Bitfield-Mask: 0x0f)                       */
42710 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S0_Pos (0UL)                   /*!< WTULPI2S0 (Bit 0)                                     */
42711 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S0_Msk (0xfUL)                 /*!< WTULPI2S0 (Bitfield-Mask: 0x0f)                       */
42712 /* =====================================================  PWRWEIGHTULP5  ===================================================== */
42713 #define PWRCTRL_PWRWEIGHTULP5_WTULPUSBPHY_Pos (4UL)                 /*!< WTULPUSBPHY (Bit 4)                                   */
42714 #define PWRCTRL_PWRWEIGHTULP5_WTULPUSBPHY_Msk (0xf0UL)              /*!< WTULPUSBPHY (Bitfield-Mask: 0x0f)                     */
42715 #define PWRCTRL_PWRWEIGHTULP5_WTULPDISPPHY_Pos (0UL)                /*!< WTULPDISPPHY (Bit 0)                                  */
42716 #define PWRCTRL_PWRWEIGHTULP5_WTULPDISPPHY_Msk (0xfUL)              /*!< WTULPDISPPHY (Bitfield-Mask: 0x0f)                    */
42717 /* =====================================================  PWRWEIGHTLP0  ====================================================== */
42718 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART3_Pos (28UL)                   /*!< WTLPUART3 (Bit 28)                                    */
42719 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART3_Msk (0xf0000000UL)           /*!< WTLPUART3 (Bitfield-Mask: 0x0f)                       */
42720 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART2_Pos (24UL)                   /*!< WTLPUART2 (Bit 24)                                    */
42721 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART2_Msk (0xf000000UL)            /*!< WTLPUART2 (Bitfield-Mask: 0x0f)                       */
42722 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART1_Pos (20UL)                   /*!< WTLPUART1 (Bit 20)                                    */
42723 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART1_Msk (0xf00000UL)             /*!< WTLPUART1 (Bitfield-Mask: 0x0f)                       */
42724 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART0_Pos (16UL)                   /*!< WTLPUART0 (Bit 16)                                    */
42725 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART0_Msk (0xf0000UL)              /*!< WTLPUART0 (Bitfield-Mask: 0x0f)                       */
42726 #define PWRCTRL_PWRWEIGHTLP0_WTLPIOS_Pos  (12UL)                    /*!< WTLPIOS (Bit 12)                                      */
42727 #define PWRCTRL_PWRWEIGHTLP0_WTLPIOS_Msk  (0xf000UL)                /*!< WTLPIOS (Bitfield-Mask: 0x0f)                         */
42728 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP1_Pos (8UL)                     /*!< WTLPDSP1 (Bit 8)                                      */
42729 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP1_Msk (0xf00UL)                 /*!< WTLPDSP1 (Bitfield-Mask: 0x0f)                        */
42730 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP0_Pos (4UL)                     /*!< WTLPDSP0 (Bit 4)                                      */
42731 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP0_Msk (0xf0UL)                  /*!< WTLPDSP0 (Bitfield-Mask: 0x0f)                        */
42732 #define PWRCTRL_PWRWEIGHTLP0_WTLPMCU_Pos  (0UL)                     /*!< WTLPMCU (Bit 0)                                       */
42733 #define PWRCTRL_PWRWEIGHTLP0_WTLPMCU_Msk  (0xfUL)                   /*!< WTLPMCU (Bitfield-Mask: 0x0f)                         */
42734 /* =====================================================  PWRWEIGHTLP1  ====================================================== */
42735 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM7_Pos (28UL)                    /*!< WTLPIOM7 (Bit 28)                                     */
42736 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM7_Msk (0xf0000000UL)            /*!< WTLPIOM7 (Bitfield-Mask: 0x0f)                        */
42737 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM6_Pos (24UL)                    /*!< WTLPIOM6 (Bit 24)                                     */
42738 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM6_Msk (0xf000000UL)             /*!< WTLPIOM6 (Bitfield-Mask: 0x0f)                        */
42739 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM5_Pos (20UL)                    /*!< WTLPIOM5 (Bit 20)                                     */
42740 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM5_Msk (0xf00000UL)              /*!< WTLPIOM5 (Bitfield-Mask: 0x0f)                        */
42741 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM4_Pos (16UL)                    /*!< WTLPIOM4 (Bit 16)                                     */
42742 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM4_Msk (0xf0000UL)               /*!< WTLPIOM4 (Bitfield-Mask: 0x0f)                        */
42743 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM3_Pos (12UL)                    /*!< WTLPIOM3 (Bit 12)                                     */
42744 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM3_Msk (0xf000UL)                /*!< WTLPIOM3 (Bitfield-Mask: 0x0f)                        */
42745 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM2_Pos (8UL)                     /*!< WTLPIOM2 (Bit 8)                                      */
42746 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM2_Msk (0xf00UL)                 /*!< WTLPIOM2 (Bitfield-Mask: 0x0f)                        */
42747 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM1_Pos (4UL)                     /*!< WTLPIOM1 (Bit 4)                                      */
42748 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM1_Msk (0xf0UL)                  /*!< WTLPIOM1 (Bitfield-Mask: 0x0f)                        */
42749 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM0_Pos (0UL)                     /*!< WTLPIOM0 (Bit 0)                                      */
42750 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM0_Msk (0xfUL)                   /*!< WTLPIOM0 (Bitfield-Mask: 0x0f)                        */
42751 /* =====================================================  PWRWEIGHTLP2  ====================================================== */
42752 #define PWRCTRL_PWRWEIGHTLP2_WTLPUSB_Pos  (28UL)                    /*!< WTLPUSB (Bit 28)                                      */
42753 #define PWRCTRL_PWRWEIGHTLP2_WTLPUSB_Msk  (0xf0000000UL)            /*!< WTLPUSB (Bitfield-Mask: 0x0f)                         */
42754 #define PWRCTRL_PWRWEIGHTLP2_WTLPSDIO_Pos (24UL)                    /*!< WTLPSDIO (Bit 24)                                     */
42755 #define PWRCTRL_PWRWEIGHTLP2_WTLPSDIO_Msk (0xf000000UL)             /*!< WTLPSDIO (Bitfield-Mask: 0x0f)                        */
42756 #define PWRCTRL_PWRWEIGHTLP2_WTLPCRYPTO_Pos (20UL)                  /*!< WTLPCRYPTO (Bit 20)                                   */
42757 #define PWRCTRL_PWRWEIGHTLP2_WTLPCRYPTO_Msk (0xf00000UL)            /*!< WTLPCRYPTO (Bitfield-Mask: 0x0f)                      */
42758 #define PWRCTRL_PWRWEIGHTLP2_WTLPDISP_Pos (16UL)                    /*!< WTLPDISP (Bit 16)                                     */
42759 #define PWRCTRL_PWRWEIGHTLP2_WTLPDISP_Msk (0xf0000UL)               /*!< WTLPDISP (Bitfield-Mask: 0x0f)                        */
42760 #define PWRCTRL_PWRWEIGHTLP2_WTLPGFX_Pos  (12UL)                    /*!< WTLPGFX (Bit 12)                                      */
42761 #define PWRCTRL_PWRWEIGHTLP2_WTLPGFX_Msk  (0xf000UL)                /*!< WTLPGFX (Bitfield-Mask: 0x0f)                         */
42762 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI1_Pos (8UL)                    /*!< WTLPMSPI1 (Bit 8)                                     */
42763 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI1_Msk (0xf00UL)                /*!< WTLPMSPI1 (Bitfield-Mask: 0x0f)                       */
42764 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI0_Pos (4UL)                    /*!< WTLPMSPI0 (Bit 4)                                     */
42765 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI0_Msk (0xf0UL)                 /*!< WTLPMSPI0 (Bitfield-Mask: 0x0f)                       */
42766 #define PWRCTRL_PWRWEIGHTLP2_WTLPADC_Pos  (0UL)                     /*!< WTLPADC (Bit 0)                                       */
42767 #define PWRCTRL_PWRWEIGHTLP2_WTLPADC_Msk  (0xfUL)                   /*!< WTLPADC (Bitfield-Mask: 0x0f)                         */
42768 /* =====================================================  PWRWEIGHTLP3  ====================================================== */
42769 #define PWRCTRL_PWRWEIGHTLP3_WTLPMSPI2_Pos (28UL)                   /*!< WTLPMSPI2 (Bit 28)                                    */
42770 #define PWRCTRL_PWRWEIGHTLP3_WTLPMSPI2_Msk (0xf0000000UL)           /*!< WTLPMSPI2 (Bitfield-Mask: 0x0f)                       */
42771 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDADC_Pos (16UL)                  /*!< WTLPAUDADC (Bit 16)                                   */
42772 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDADC_Msk (0xf0000UL)             /*!< WTLPAUDADC (Bitfield-Mask: 0x0f)                      */
42773 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDPB_Pos (12UL)                   /*!< WTLPAUDPB (Bit 12)                                    */
42774 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDPB_Msk (0xf000UL)               /*!< WTLPAUDPB (Bitfield-Mask: 0x0f)                       */
42775 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDREC_Pos (8UL)                   /*!< WTLPAUDREC (Bit 8)                                    */
42776 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDREC_Msk (0xf00UL)               /*!< WTLPAUDREC (Bitfield-Mask: 0x0f)                      */
42777 #define PWRCTRL_PWRWEIGHTLP3_WTLPDBG_Pos  (4UL)                     /*!< WTLPDBG (Bit 4)                                       */
42778 #define PWRCTRL_PWRWEIGHTLP3_WTLPDBG_Msk  (0xf0UL)                  /*!< WTLPDBG (Bitfield-Mask: 0x0f)                         */
42779 #define PWRCTRL_PWRWEIGHTLP3_WTLPDSPA_Pos (0UL)                     /*!< WTLPDSPA (Bit 0)                                      */
42780 #define PWRCTRL_PWRWEIGHTLP3_WTLPDSPA_Msk (0xfUL)                   /*!< WTLPDSPA (Bitfield-Mask: 0x0f)                        */
42781 /* =====================================================  PWRWEIGHTLP4  ====================================================== */
42782 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM3_Pos (28UL)                    /*!< WTLPPDM3 (Bit 28)                                     */
42783 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM3_Msk (0xf0000000UL)            /*!< WTLPPDM3 (Bitfield-Mask: 0x0f)                        */
42784 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM2_Pos (24UL)                    /*!< WTLPPDM2 (Bit 24)                                     */
42785 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM2_Msk (0xf000000UL)             /*!< WTLPPDM2 (Bitfield-Mask: 0x0f)                        */
42786 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM1_Pos (20UL)                    /*!< WTLPPDM1 (Bit 20)                                     */
42787 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM1_Msk (0xf00000UL)              /*!< WTLPPDM1 (Bitfield-Mask: 0x0f)                        */
42788 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM0_Pos (16UL)                    /*!< WTLPPDM0 (Bit 16)                                     */
42789 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM0_Msk (0xf0000UL)               /*!< WTLPPDM0 (Bitfield-Mask: 0x0f)                        */
42790 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S1_Pos (4UL)                     /*!< WTLPI2S1 (Bit 4)                                      */
42791 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S1_Msk (0xf0UL)                  /*!< WTLPI2S1 (Bitfield-Mask: 0x0f)                        */
42792 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S0_Pos (0UL)                     /*!< WTLPI2S0 (Bit 0)                                      */
42793 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S0_Msk (0xfUL)                   /*!< WTLPI2S0 (Bitfield-Mask: 0x0f)                        */
42794 /* =====================================================  PWRWEIGHTLP5  ====================================================== */
42795 #define PWRCTRL_PWRWEIGHTLP5_WTLPUSBPHY_Pos (4UL)                   /*!< WTLPUSBPHY (Bit 4)                                    */
42796 #define PWRCTRL_PWRWEIGHTLP5_WTLPUSBPHY_Msk (0xf0UL)                /*!< WTLPUSBPHY (Bitfield-Mask: 0x0f)                      */
42797 #define PWRCTRL_PWRWEIGHTLP5_WTLPDISPPHY_Pos (0UL)                  /*!< WTLPDISPPHY (Bit 0)                                   */
42798 #define PWRCTRL_PWRWEIGHTLP5_WTLPDISPPHY_Msk (0xfUL)                /*!< WTLPDISPPHY (Bitfield-Mask: 0x0f)                     */
42799 /* =====================================================  PWRWEIGHTHP0  ====================================================== */
42800 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART3_Pos (28UL)                   /*!< WTHPUART3 (Bit 28)                                    */
42801 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART3_Msk (0xf0000000UL)           /*!< WTHPUART3 (Bitfield-Mask: 0x0f)                       */
42802 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART2_Pos (24UL)                   /*!< WTHPUART2 (Bit 24)                                    */
42803 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART2_Msk (0xf000000UL)            /*!< WTHPUART2 (Bitfield-Mask: 0x0f)                       */
42804 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART1_Pos (20UL)                   /*!< WTHPUART1 (Bit 20)                                    */
42805 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART1_Msk (0xf00000UL)             /*!< WTHPUART1 (Bitfield-Mask: 0x0f)                       */
42806 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART0_Pos (16UL)                   /*!< WTHPUART0 (Bit 16)                                    */
42807 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART0_Msk (0xf0000UL)              /*!< WTHPUART0 (Bitfield-Mask: 0x0f)                       */
42808 #define PWRCTRL_PWRWEIGHTHP0_WTHPIOS_Pos  (12UL)                    /*!< WTHPIOS (Bit 12)                                      */
42809 #define PWRCTRL_PWRWEIGHTHP0_WTHPIOS_Msk  (0xf000UL)                /*!< WTHPIOS (Bitfield-Mask: 0x0f)                         */
42810 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP1_Pos (8UL)                     /*!< WTHPDSP1 (Bit 8)                                      */
42811 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP1_Msk (0xf00UL)                 /*!< WTHPDSP1 (Bitfield-Mask: 0x0f)                        */
42812 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP0_Pos (4UL)                     /*!< WTHPDSP0 (Bit 4)                                      */
42813 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP0_Msk (0xf0UL)                  /*!< WTHPDSP0 (Bitfield-Mask: 0x0f)                        */
42814 #define PWRCTRL_PWRWEIGHTHP0_WTHPMCU_Pos  (0UL)                     /*!< WTHPMCU (Bit 0)                                       */
42815 #define PWRCTRL_PWRWEIGHTHP0_WTHPMCU_Msk  (0xfUL)                   /*!< WTHPMCU (Bitfield-Mask: 0x0f)                         */
42816 /* =====================================================  PWRWEIGHTHP1  ====================================================== */
42817 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM7_Pos (28UL)                    /*!< WTHPIOM7 (Bit 28)                                     */
42818 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM7_Msk (0xf0000000UL)            /*!< WTHPIOM7 (Bitfield-Mask: 0x0f)                        */
42819 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM6_Pos (24UL)                    /*!< WTHPIOM6 (Bit 24)                                     */
42820 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM6_Msk (0xf000000UL)             /*!< WTHPIOM6 (Bitfield-Mask: 0x0f)                        */
42821 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM5_Pos (20UL)                    /*!< WTHPIOM5 (Bit 20)                                     */
42822 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM5_Msk (0xf00000UL)              /*!< WTHPIOM5 (Bitfield-Mask: 0x0f)                        */
42823 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM4_Pos (16UL)                    /*!< WTHPIOM4 (Bit 16)                                     */
42824 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM4_Msk (0xf0000UL)               /*!< WTHPIOM4 (Bitfield-Mask: 0x0f)                        */
42825 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM3_Pos (12UL)                    /*!< WTHPIOM3 (Bit 12)                                     */
42826 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM3_Msk (0xf000UL)                /*!< WTHPIOM3 (Bitfield-Mask: 0x0f)                        */
42827 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM2_Pos (8UL)                     /*!< WTHPIOM2 (Bit 8)                                      */
42828 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM2_Msk (0xf00UL)                 /*!< WTHPIOM2 (Bitfield-Mask: 0x0f)                        */
42829 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM1_Pos (4UL)                     /*!< WTHPIOM1 (Bit 4)                                      */
42830 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM1_Msk (0xf0UL)                  /*!< WTHPIOM1 (Bitfield-Mask: 0x0f)                        */
42831 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM0_Pos (0UL)                     /*!< WTHPIOM0 (Bit 0)                                      */
42832 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM0_Msk (0xfUL)                   /*!< WTHPIOM0 (Bitfield-Mask: 0x0f)                        */
42833 /* =====================================================  PWRWEIGHTHP2  ====================================================== */
42834 #define PWRCTRL_PWRWEIGHTHP2_WTHPUSB_Pos  (28UL)                    /*!< WTHPUSB (Bit 28)                                      */
42835 #define PWRCTRL_PWRWEIGHTHP2_WTHPUSB_Msk  (0xf0000000UL)            /*!< WTHPUSB (Bitfield-Mask: 0x0f)                         */
42836 #define PWRCTRL_PWRWEIGHTHP2_WTHPSDIO_Pos (24UL)                    /*!< WTHPSDIO (Bit 24)                                     */
42837 #define PWRCTRL_PWRWEIGHTHP2_WTHPSDIO_Msk (0xf000000UL)             /*!< WTHPSDIO (Bitfield-Mask: 0x0f)                        */
42838 #define PWRCTRL_PWRWEIGHTHP2_WTHPCRYPTO_Pos (20UL)                  /*!< WTHPCRYPTO (Bit 20)                                   */
42839 #define PWRCTRL_PWRWEIGHTHP2_WTHPCRYPTO_Msk (0xf00000UL)            /*!< WTHPCRYPTO (Bitfield-Mask: 0x0f)                      */
42840 #define PWRCTRL_PWRWEIGHTHP2_WTHPDISP_Pos (16UL)                    /*!< WTHPDISP (Bit 16)                                     */
42841 #define PWRCTRL_PWRWEIGHTHP2_WTHPDISP_Msk (0xf0000UL)               /*!< WTHPDISP (Bitfield-Mask: 0x0f)                        */
42842 #define PWRCTRL_PWRWEIGHTHP2_WTHPGFX_Pos  (12UL)                    /*!< WTHPGFX (Bit 12)                                      */
42843 #define PWRCTRL_PWRWEIGHTHP2_WTHPGFX_Msk  (0xf000UL)                /*!< WTHPGFX (Bitfield-Mask: 0x0f)                         */
42844 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI1_Pos (8UL)                    /*!< WTHPMSPI1 (Bit 8)                                     */
42845 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI1_Msk (0xf00UL)                /*!< WTHPMSPI1 (Bitfield-Mask: 0x0f)                       */
42846 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI0_Pos (4UL)                    /*!< WTHPMSPI0 (Bit 4)                                     */
42847 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI0_Msk (0xf0UL)                 /*!< WTHPMSPI0 (Bitfield-Mask: 0x0f)                       */
42848 #define PWRCTRL_PWRWEIGHTHP2_WTHPADC_Pos  (0UL)                     /*!< WTHPADC (Bit 0)                                       */
42849 #define PWRCTRL_PWRWEIGHTHP2_WTHPADC_Msk  (0xfUL)                   /*!< WTHPADC (Bitfield-Mask: 0x0f)                         */
42850 /* =====================================================  PWRWEIGHTHP3  ====================================================== */
42851 #define PWRCTRL_PWRWEIGHTHP3_WTHPMSPI2_Pos (28UL)                   /*!< WTHPMSPI2 (Bit 28)                                    */
42852 #define PWRCTRL_PWRWEIGHTHP3_WTHPMSPI2_Msk (0xf0000000UL)           /*!< WTHPMSPI2 (Bitfield-Mask: 0x0f)                       */
42853 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDADC_Pos (16UL)                  /*!< WTHPAUDADC (Bit 16)                                   */
42854 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDADC_Msk (0xf0000UL)             /*!< WTHPAUDADC (Bitfield-Mask: 0x0f)                      */
42855 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDPB_Pos (12UL)                   /*!< WTHPAUDPB (Bit 12)                                    */
42856 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDPB_Msk (0xf000UL)               /*!< WTHPAUDPB (Bitfield-Mask: 0x0f)                       */
42857 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDREC_Pos (8UL)                   /*!< WTHPAUDREC (Bit 8)                                    */
42858 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDREC_Msk (0xf00UL)               /*!< WTHPAUDREC (Bitfield-Mask: 0x0f)                      */
42859 #define PWRCTRL_PWRWEIGHTHP3_WTHPDBG_Pos  (4UL)                     /*!< WTHPDBG (Bit 4)                                       */
42860 #define PWRCTRL_PWRWEIGHTHP3_WTHPDBG_Msk  (0xf0UL)                  /*!< WTHPDBG (Bitfield-Mask: 0x0f)                         */
42861 #define PWRCTRL_PWRWEIGHTHP3_WTHPDSPA_Pos (0UL)                     /*!< WTHPDSPA (Bit 0)                                      */
42862 #define PWRCTRL_PWRWEIGHTHP3_WTHPDSPA_Msk (0xfUL)                   /*!< WTHPDSPA (Bitfield-Mask: 0x0f)                        */
42863 /* =====================================================  PWRWEIGHTHP4  ====================================================== */
42864 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM3_Pos (28UL)                    /*!< WTHPPDM3 (Bit 28)                                     */
42865 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM3_Msk (0xf0000000UL)            /*!< WTHPPDM3 (Bitfield-Mask: 0x0f)                        */
42866 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM2_Pos (24UL)                    /*!< WTHPPDM2 (Bit 24)                                     */
42867 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM2_Msk (0xf000000UL)             /*!< WTHPPDM2 (Bitfield-Mask: 0x0f)                        */
42868 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM1_Pos (20UL)                    /*!< WTHPPDM1 (Bit 20)                                     */
42869 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM1_Msk (0xf00000UL)              /*!< WTHPPDM1 (Bitfield-Mask: 0x0f)                        */
42870 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM0_Pos (16UL)                    /*!< WTHPPDM0 (Bit 16)                                     */
42871 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM0_Msk (0xf0000UL)               /*!< WTHPPDM0 (Bitfield-Mask: 0x0f)                        */
42872 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S1_Pos (4UL)                     /*!< WTHPI2S1 (Bit 4)                                      */
42873 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S1_Msk (0xf0UL)                  /*!< WTHPI2S1 (Bitfield-Mask: 0x0f)                        */
42874 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S0_Pos (0UL)                     /*!< WTHPI2S0 (Bit 0)                                      */
42875 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S0_Msk (0xfUL)                   /*!< WTHPI2S0 (Bitfield-Mask: 0x0f)                        */
42876 /* =====================================================  PWRWEIGHTHP5  ====================================================== */
42877 #define PWRCTRL_PWRWEIGHTHP5_WTHPUSBPHY_Pos (4UL)                   /*!< WTHPUSBPHY (Bit 4)                                    */
42878 #define PWRCTRL_PWRWEIGHTHP5_WTHPUSBPHY_Msk (0xf0UL)                /*!< WTHPUSBPHY (Bitfield-Mask: 0x0f)                      */
42879 #define PWRCTRL_PWRWEIGHTHP5_WTHPDISPPHY_Pos (0UL)                  /*!< WTHPDISPPHY (Bit 0)                                   */
42880 #define PWRCTRL_PWRWEIGHTHP5_WTHPDISPPHY_Msk (0xfUL)                /*!< WTHPDISPPHY (Bitfield-Mask: 0x0f)                     */
42881 /* =====================================================  PWRWEIGHTSLP  ====================================================== */
42882 #define PWRCTRL_PWRWEIGHTSLP_WTDSMCU_Pos  (0UL)                     /*!< WTDSMCU (Bit 0)                                       */
42883 #define PWRCTRL_PWRWEIGHTSLP_WTDSMCU_Msk  (0xfUL)                   /*!< WTDSMCU (Bitfield-Mask: 0x0f)                         */
42884 /* =====================================================  VRDEMOTIONTHR  ===================================================== */
42885 #define PWRCTRL_VRDEMOTIONTHR_VRDEMOTIONTHR_Pos (0UL)               /*!< VRDEMOTIONTHR (Bit 0)                                 */
42886 #define PWRCTRL_VRDEMOTIONTHR_VRDEMOTIONTHR_Msk (0xffffffffUL)      /*!< VRDEMOTIONTHR (Bitfield-Mask: 0xffffffff)             */
42887 /* =======================================================  SRAMCTRL  ======================================================== */
42888 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL)                   /*!< SRAMLIGHTSLEEP (Bit 8)                                */
42889 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL)             /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff)                 */
42890 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL)                /*!< SRAMMASTERCLKGATE (Bit 2)                             */
42891 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL)              /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01)               */
42892 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos  (1UL)                     /*!< SRAMCLKGATE (Bit 1)                                   */
42893 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk  (0x2UL)                   /*!< SRAMCLKGATE (Bitfield-Mask: 0x01)                     */
42894 /* =======================================================  ADCSTATUS  ======================================================= */
42895 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos   (5UL)                     /*!< REFBUFPWD (Bit 5)                                     */
42896 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk   (0x20UL)                  /*!< REFBUFPWD (Bitfield-Mask: 0x01)                       */
42897 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos  (4UL)                     /*!< REFKEEPPWD (Bit 4)                                    */
42898 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk  (0x10UL)                  /*!< REFKEEPPWD (Bitfield-Mask: 0x01)                      */
42899 #define PWRCTRL_ADCSTATUS_VBATPWD_Pos     (3UL)                     /*!< VBATPWD (Bit 3)                                       */
42900 #define PWRCTRL_ADCSTATUS_VBATPWD_Msk     (0x8UL)                   /*!< VBATPWD (Bitfield-Mask: 0x01)                         */
42901 #define PWRCTRL_ADCSTATUS_VPTATPWD_Pos    (2UL)                     /*!< VPTATPWD (Bit 2)                                      */
42902 #define PWRCTRL_ADCSTATUS_VPTATPWD_Msk    (0x4UL)                   /*!< VPTATPWD (Bitfield-Mask: 0x01)                        */
42903 #define PWRCTRL_ADCSTATUS_BGTPWD_Pos      (1UL)                     /*!< BGTPWD (Bit 1)                                        */
42904 #define PWRCTRL_ADCSTATUS_BGTPWD_Msk      (0x2UL)                   /*!< BGTPWD (Bitfield-Mask: 0x01)                          */
42905 #define PWRCTRL_ADCSTATUS_ADCPWD_Pos      (0UL)                     /*!< ADCPWD (Bit 0)                                        */
42906 #define PWRCTRL_ADCSTATUS_ADCPWD_Msk      (0x1UL)                   /*!< ADCPWD (Bitfield-Mask: 0x01)                          */
42907 /* =====================================================  AUDADCSTATUS  ====================================================== */
42908 #define PWRCTRL_AUDADCSTATUS_AUDREFBUFPWD_Pos (5UL)                 /*!< AUDREFBUFPWD (Bit 5)                                  */
42909 #define PWRCTRL_AUDADCSTATUS_AUDREFBUFPWD_Msk (0x20UL)              /*!< AUDREFBUFPWD (Bitfield-Mask: 0x01)                    */
42910 #define PWRCTRL_AUDADCSTATUS_AUDREFKEEPPWD_Pos (4UL)                /*!< AUDREFKEEPPWD (Bit 4)                                 */
42911 #define PWRCTRL_AUDADCSTATUS_AUDREFKEEPPWD_Msk (0x10UL)             /*!< AUDREFKEEPPWD (Bitfield-Mask: 0x01)                   */
42912 #define PWRCTRL_AUDADCSTATUS_AUDVBATPWD_Pos (3UL)                   /*!< AUDVBATPWD (Bit 3)                                    */
42913 #define PWRCTRL_AUDADCSTATUS_AUDVBATPWD_Msk (0x8UL)                 /*!< AUDVBATPWD (Bitfield-Mask: 0x01)                      */
42914 #define PWRCTRL_AUDADCSTATUS_AUDVPTATPWD_Pos (2UL)                  /*!< AUDVPTATPWD (Bit 2)                                   */
42915 #define PWRCTRL_AUDADCSTATUS_AUDVPTATPWD_Msk (0x4UL)                /*!< AUDVPTATPWD (Bitfield-Mask: 0x01)                     */
42916 #define PWRCTRL_AUDADCSTATUS_AUDBGTPWD_Pos (1UL)                    /*!< AUDBGTPWD (Bit 1)                                     */
42917 #define PWRCTRL_AUDADCSTATUS_AUDBGTPWD_Msk (0x2UL)                  /*!< AUDBGTPWD (Bitfield-Mask: 0x01)                       */
42918 #define PWRCTRL_AUDADCSTATUS_AUDADCPWD_Pos (0UL)                    /*!< AUDADCPWD (Bit 0)                                     */
42919 #define PWRCTRL_AUDADCSTATUS_AUDADCPWD_Msk (0x1UL)                  /*!< AUDADCPWD (Bitfield-Mask: 0x01)                       */
42920 /* =======================================================  EMONCTRL  ======================================================== */
42921 #define PWRCTRL_EMONCTRL_CLEAR_Pos        (8UL)                     /*!< CLEAR (Bit 8)                                         */
42922 #define PWRCTRL_EMONCTRL_CLEAR_Msk        (0xff00UL)                /*!< CLEAR (Bitfield-Mask: 0xff)                           */
42923 #define PWRCTRL_EMONCTRL_FREEZE_Pos       (0UL)                     /*!< FREEZE (Bit 0)                                        */
42924 #define PWRCTRL_EMONCTRL_FREEZE_Msk       (0xffUL)                  /*!< FREEZE (Bitfield-Mask: 0xff)                          */
42925 /* =======================================================  EMONCFG0  ======================================================== */
42926 #define PWRCTRL_EMONCFG0_EMONSEL0_Pos     (0UL)                     /*!< EMONSEL0 (Bit 0)                                      */
42927 #define PWRCTRL_EMONCFG0_EMONSEL0_Msk     (0xffUL)                  /*!< EMONSEL0 (Bitfield-Mask: 0xff)                        */
42928 /* =======================================================  EMONCFG1  ======================================================== */
42929 #define PWRCTRL_EMONCFG1_EMONSEL1_Pos     (0UL)                     /*!< EMONSEL1 (Bit 0)                                      */
42930 #define PWRCTRL_EMONCFG1_EMONSEL1_Msk     (0xffUL)                  /*!< EMONSEL1 (Bitfield-Mask: 0xff)                        */
42931 /* =======================================================  EMONCFG2  ======================================================== */
42932 #define PWRCTRL_EMONCFG2_EMONSEL2_Pos     (0UL)                     /*!< EMONSEL2 (Bit 0)                                      */
42933 #define PWRCTRL_EMONCFG2_EMONSEL2_Msk     (0xffUL)                  /*!< EMONSEL2 (Bitfield-Mask: 0xff)                        */
42934 /* =======================================================  EMONCFG3  ======================================================== */
42935 #define PWRCTRL_EMONCFG3_EMONSEL3_Pos     (0UL)                     /*!< EMONSEL3 (Bit 0)                                      */
42936 #define PWRCTRL_EMONCFG3_EMONSEL3_Msk     (0xffUL)                  /*!< EMONSEL3 (Bitfield-Mask: 0xff)                        */
42937 /* =======================================================  EMONCFG4  ======================================================== */
42938 #define PWRCTRL_EMONCFG4_EMONSEL4_Pos     (0UL)                     /*!< EMONSEL4 (Bit 0)                                      */
42939 #define PWRCTRL_EMONCFG4_EMONSEL4_Msk     (0xffUL)                  /*!< EMONSEL4 (Bitfield-Mask: 0xff)                        */
42940 /* =======================================================  EMONCFG5  ======================================================== */
42941 #define PWRCTRL_EMONCFG5_EMONSEL5_Pos     (0UL)                     /*!< EMONSEL5 (Bit 0)                                      */
42942 #define PWRCTRL_EMONCFG5_EMONSEL5_Msk     (0xffUL)                  /*!< EMONSEL5 (Bitfield-Mask: 0xff)                        */
42943 /* =======================================================  EMONCFG6  ======================================================== */
42944 #define PWRCTRL_EMONCFG6_EMONSEL6_Pos     (0UL)                     /*!< EMONSEL6 (Bit 0)                                      */
42945 #define PWRCTRL_EMONCFG6_EMONSEL6_Msk     (0xffUL)                  /*!< EMONSEL6 (Bitfield-Mask: 0xff)                        */
42946 /* =======================================================  EMONCFG7  ======================================================== */
42947 #define PWRCTRL_EMONCFG7_EMONSEL7_Pos     (0UL)                     /*!< EMONSEL7 (Bit 0)                                      */
42948 #define PWRCTRL_EMONCFG7_EMONSEL7_Msk     (0xffUL)                  /*!< EMONSEL7 (Bitfield-Mask: 0xff)                        */
42949 /* ======================================================  EMONCOUNT0  ======================================================= */
42950 #define PWRCTRL_EMONCOUNT0_EMONCOUNT0_Pos (0UL)                     /*!< EMONCOUNT0 (Bit 0)                                    */
42951 #define PWRCTRL_EMONCOUNT0_EMONCOUNT0_Msk (0xffffffffUL)            /*!< EMONCOUNT0 (Bitfield-Mask: 0xffffffff)                */
42952 /* ======================================================  EMONCOUNT1  ======================================================= */
42953 #define PWRCTRL_EMONCOUNT1_EMONCOUNT1_Pos (0UL)                     /*!< EMONCOUNT1 (Bit 0)                                    */
42954 #define PWRCTRL_EMONCOUNT1_EMONCOUNT1_Msk (0xffffffffUL)            /*!< EMONCOUNT1 (Bitfield-Mask: 0xffffffff)                */
42955 /* ======================================================  EMONCOUNT2  ======================================================= */
42956 #define PWRCTRL_EMONCOUNT2_EMONCOUNT2_Pos (0UL)                     /*!< EMONCOUNT2 (Bit 0)                                    */
42957 #define PWRCTRL_EMONCOUNT2_EMONCOUNT2_Msk (0xffffffffUL)            /*!< EMONCOUNT2 (Bitfield-Mask: 0xffffffff)                */
42958 /* ======================================================  EMONCOUNT3  ======================================================= */
42959 #define PWRCTRL_EMONCOUNT3_EMONCOUNT3_Pos (0UL)                     /*!< EMONCOUNT3 (Bit 0)                                    */
42960 #define PWRCTRL_EMONCOUNT3_EMONCOUNT3_Msk (0xffffffffUL)            /*!< EMONCOUNT3 (Bitfield-Mask: 0xffffffff)                */
42961 /* ======================================================  EMONCOUNT4  ======================================================= */
42962 #define PWRCTRL_EMONCOUNT4_EMONCOUNT4_Pos (0UL)                     /*!< EMONCOUNT4 (Bit 0)                                    */
42963 #define PWRCTRL_EMONCOUNT4_EMONCOUNT4_Msk (0xffffffffUL)            /*!< EMONCOUNT4 (Bitfield-Mask: 0xffffffff)                */
42964 /* ======================================================  EMONCOUNT5  ======================================================= */
42965 #define PWRCTRL_EMONCOUNT5_EMONCOUNT5_Pos (0UL)                     /*!< EMONCOUNT5 (Bit 0)                                    */
42966 #define PWRCTRL_EMONCOUNT5_EMONCOUNT5_Msk (0xffffffffUL)            /*!< EMONCOUNT5 (Bitfield-Mask: 0xffffffff)                */
42967 /* ======================================================  EMONCOUNT6  ======================================================= */
42968 #define PWRCTRL_EMONCOUNT6_EMONCOUNT6_Pos (0UL)                     /*!< EMONCOUNT6 (Bit 0)                                    */
42969 #define PWRCTRL_EMONCOUNT6_EMONCOUNT6_Msk (0xffffffffUL)            /*!< EMONCOUNT6 (Bitfield-Mask: 0xffffffff)                */
42970 /* ======================================================  EMONCOUNT7  ======================================================= */
42971 #define PWRCTRL_EMONCOUNT7_EMONCOUNT7_Pos (0UL)                     /*!< EMONCOUNT7 (Bit 0)                                    */
42972 #define PWRCTRL_EMONCOUNT7_EMONCOUNT7_Msk (0xffffffffUL)            /*!< EMONCOUNT7 (Bitfield-Mask: 0xffffffff)                */
42973 /* ======================================================  EMONSTATUS  ======================================================= */
42974 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW7_Pos (7UL)                  /*!< EMONOVERFLOW7 (Bit 7)                                 */
42975 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW7_Msk (0x80UL)               /*!< EMONOVERFLOW7 (Bitfield-Mask: 0x01)                   */
42976 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW6_Pos (6UL)                  /*!< EMONOVERFLOW6 (Bit 6)                                 */
42977 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW6_Msk (0x40UL)               /*!< EMONOVERFLOW6 (Bitfield-Mask: 0x01)                   */
42978 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW5_Pos (5UL)                  /*!< EMONOVERFLOW5 (Bit 5)                                 */
42979 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW5_Msk (0x20UL)               /*!< EMONOVERFLOW5 (Bitfield-Mask: 0x01)                   */
42980 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW4_Pos (4UL)                  /*!< EMONOVERFLOW4 (Bit 4)                                 */
42981 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW4_Msk (0x10UL)               /*!< EMONOVERFLOW4 (Bitfield-Mask: 0x01)                   */
42982 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW3_Pos (3UL)                  /*!< EMONOVERFLOW3 (Bit 3)                                 */
42983 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW3_Msk (0x8UL)                /*!< EMONOVERFLOW3 (Bitfield-Mask: 0x01)                   */
42984 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW2_Pos (2UL)                  /*!< EMONOVERFLOW2 (Bit 2)                                 */
42985 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW2_Msk (0x4UL)                /*!< EMONOVERFLOW2 (Bitfield-Mask: 0x01)                   */
42986 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW1_Pos (1UL)                  /*!< EMONOVERFLOW1 (Bit 1)                                 */
42987 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW1_Msk (0x2UL)                /*!< EMONOVERFLOW1 (Bitfield-Mask: 0x01)                   */
42988 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW0_Pos (0UL)                  /*!< EMONOVERFLOW0 (Bit 0)                                 */
42989 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW0_Msk (0x1UL)                /*!< EMONOVERFLOW0 (Bitfield-Mask: 0x01)                   */
42990 
42991 
42992 /* =========================================================================================================================== */
42993 /* ================                                          RSTGEN                                           ================ */
42994 /* =========================================================================================================================== */
42995 
42996 /* ==========================================================  CFG  ========================================================== */
42997 #define RSTGEN_CFG_WDREN_Pos              (1UL)                     /*!< WDREN (Bit 1)                                         */
42998 #define RSTGEN_CFG_WDREN_Msk              (0x2UL)                   /*!< WDREN (Bitfield-Mask: 0x01)                           */
42999 #define RSTGEN_CFG_BODHREN_Pos            (0UL)                     /*!< BODHREN (Bit 0)                                       */
43000 #define RSTGEN_CFG_BODHREN_Msk            (0x1UL)                   /*!< BODHREN (Bitfield-Mask: 0x01)                         */
43001 /* =========================================================  SWPOI  ========================================================= */
43002 #define RSTGEN_SWPOI_SWPOIKEY_Pos         (0UL)                     /*!< SWPOIKEY (Bit 0)                                      */
43003 #define RSTGEN_SWPOI_SWPOIKEY_Msk         (0xffUL)                  /*!< SWPOIKEY (Bitfield-Mask: 0xff)                        */
43004 /* =========================================================  SWPOR  ========================================================= */
43005 #define RSTGEN_SWPOR_SWPORKEY_Pos         (0UL)                     /*!< SWPORKEY (Bit 0)                                      */
43006 #define RSTGEN_SWPOR_SWPORKEY_Msk         (0xffUL)                  /*!< SWPORKEY (Bitfield-Mask: 0xff)                        */
43007 /* =======================================================  SIMOBODM  ======================================================== */
43008 #define RSTGEN_SIMOBODM_DIGBOECLV_Pos     (3UL)                     /*!< DIGBOECLV (Bit 3)                                     */
43009 #define RSTGEN_SIMOBODM_DIGBOECLV_Msk     (0x8UL)                   /*!< DIGBOECLV (Bitfield-Mask: 0x01)                       */
43010 #define RSTGEN_SIMOBODM_DIGBOES_Pos       (2UL)                     /*!< DIGBOES (Bit 2)                                       */
43011 #define RSTGEN_SIMOBODM_DIGBOES_Msk       (0x4UL)                   /*!< DIGBOES (Bitfield-Mask: 0x01)                         */
43012 #define RSTGEN_SIMOBODM_DIGBOEF_Pos       (1UL)                     /*!< DIGBOEF (Bit 1)                                       */
43013 #define RSTGEN_SIMOBODM_DIGBOEF_Msk       (0x2UL)                   /*!< DIGBOEF (Bitfield-Mask: 0x01)                         */
43014 #define RSTGEN_SIMOBODM_DIGBOEC_Pos       (0UL)                     /*!< DIGBOEC (Bit 0)                                       */
43015 #define RSTGEN_SIMOBODM_DIGBOEC_Msk       (0x1UL)                   /*!< DIGBOEC (Bitfield-Mask: 0x01)                         */
43016 /* =========================================================  INTEN  ========================================================= */
43017 #define RSTGEN_INTEN_BODDIGCLV_Pos        (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43018 #define RSTGEN_INTEN_BODDIGCLV_Msk        (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43019 #define RSTGEN_INTEN_BODDIGS_Pos          (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43020 #define RSTGEN_INTEN_BODDIGS_Msk          (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43021 #define RSTGEN_INTEN_BODDIGF_Pos          (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43022 #define RSTGEN_INTEN_BODDIGF_Msk          (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43023 #define RSTGEN_INTEN_BODDIGC_Pos          (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43024 #define RSTGEN_INTEN_BODDIGC_Msk          (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43025 #define RSTGEN_INTEN_BODH_Pos             (0UL)                     /*!< BODH (Bit 0)                                          */
43026 #define RSTGEN_INTEN_BODH_Msk             (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43027 /* ========================================================  INTSTAT  ======================================================== */
43028 #define RSTGEN_INTSTAT_BODDIGCLV_Pos      (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43029 #define RSTGEN_INTSTAT_BODDIGCLV_Msk      (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43030 #define RSTGEN_INTSTAT_BODDIGS_Pos        (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43031 #define RSTGEN_INTSTAT_BODDIGS_Msk        (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43032 #define RSTGEN_INTSTAT_BODDIGF_Pos        (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43033 #define RSTGEN_INTSTAT_BODDIGF_Msk        (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43034 #define RSTGEN_INTSTAT_BODDIGC_Pos        (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43035 #define RSTGEN_INTSTAT_BODDIGC_Msk        (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43036 #define RSTGEN_INTSTAT_BODH_Pos           (0UL)                     /*!< BODH (Bit 0)                                          */
43037 #define RSTGEN_INTSTAT_BODH_Msk           (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43038 /* ========================================================  INTCLR  ========================================================= */
43039 #define RSTGEN_INTCLR_BODDIGCLV_Pos       (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43040 #define RSTGEN_INTCLR_BODDIGCLV_Msk       (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43041 #define RSTGEN_INTCLR_BODDIGS_Pos         (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43042 #define RSTGEN_INTCLR_BODDIGS_Msk         (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43043 #define RSTGEN_INTCLR_BODDIGF_Pos         (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43044 #define RSTGEN_INTCLR_BODDIGF_Msk         (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43045 #define RSTGEN_INTCLR_BODDIGC_Pos         (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43046 #define RSTGEN_INTCLR_BODDIGC_Msk         (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43047 #define RSTGEN_INTCLR_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
43048 #define RSTGEN_INTCLR_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43049 /* ========================================================  INTSET  ========================================================= */
43050 #define RSTGEN_INTSET_BODDIGCLV_Pos       (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43051 #define RSTGEN_INTSET_BODDIGCLV_Msk       (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43052 #define RSTGEN_INTSET_BODDIGS_Pos         (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43053 #define RSTGEN_INTSET_BODDIGS_Msk         (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43054 #define RSTGEN_INTSET_BODDIGF_Pos         (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43055 #define RSTGEN_INTSET_BODDIGF_Msk         (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43056 #define RSTGEN_INTSET_BODDIGC_Pos         (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43057 #define RSTGEN_INTSET_BODDIGC_Msk         (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43058 #define RSTGEN_INTSET_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
43059 #define RSTGEN_INTSET_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43060 /* =========================================================  STAT  ========================================================== */
43061 #define RSTGEN_STAT_BOSSTAT_Pos           (10UL)                    /*!< BOSSTAT (Bit 10)                                      */
43062 #define RSTGEN_STAT_BOSSTAT_Msk           (0x400UL)                 /*!< BOSSTAT (Bitfield-Mask: 0x01)                         */
43063 #define RSTGEN_STAT_BOFSTAT_Pos           (9UL)                     /*!< BOFSTAT (Bit 9)                                       */
43064 #define RSTGEN_STAT_BOFSTAT_Msk           (0x200UL)                 /*!< BOFSTAT (Bitfield-Mask: 0x01)                         */
43065 #define RSTGEN_STAT_BOCSTAT_Pos           (8UL)                     /*!< BOCSTAT (Bit 8)                                       */
43066 #define RSTGEN_STAT_BOCSTAT_Msk           (0x100UL)                 /*!< BOCSTAT (Bitfield-Mask: 0x01)                         */
43067 #define RSTGEN_STAT_BOUSTAT_Pos           (7UL)                     /*!< BOUSTAT (Bit 7)                                       */
43068 #define RSTGEN_STAT_BOUSTAT_Msk           (0x80UL)                  /*!< BOUSTAT (Bitfield-Mask: 0x01)                         */
43069 #define RSTGEN_STAT_WDRSTAT_Pos           (6UL)                     /*!< WDRSTAT (Bit 6)                                       */
43070 #define RSTGEN_STAT_WDRSTAT_Msk           (0x40UL)                  /*!< WDRSTAT (Bitfield-Mask: 0x01)                         */
43071 #define RSTGEN_STAT_DBGRSTAT_Pos          (5UL)                     /*!< DBGRSTAT (Bit 5)                                      */
43072 #define RSTGEN_STAT_DBGRSTAT_Msk          (0x20UL)                  /*!< DBGRSTAT (Bitfield-Mask: 0x01)                        */
43073 #define RSTGEN_STAT_POIRSTAT_Pos          (4UL)                     /*!< POIRSTAT (Bit 4)                                      */
43074 #define RSTGEN_STAT_POIRSTAT_Msk          (0x10UL)                  /*!< POIRSTAT (Bitfield-Mask: 0x01)                        */
43075 #define RSTGEN_STAT_SWRSTAT_Pos           (3UL)                     /*!< SWRSTAT (Bit 3)                                       */
43076 #define RSTGEN_STAT_SWRSTAT_Msk           (0x8UL)                   /*!< SWRSTAT (Bitfield-Mask: 0x01)                         */
43077 #define RSTGEN_STAT_BORSTAT_Pos           (2UL)                     /*!< BORSTAT (Bit 2)                                       */
43078 #define RSTGEN_STAT_BORSTAT_Msk           (0x4UL)                   /*!< BORSTAT (Bitfield-Mask: 0x01)                         */
43079 #define RSTGEN_STAT_PORSTAT_Pos           (1UL)                     /*!< PORSTAT (Bit 1)                                       */
43080 #define RSTGEN_STAT_PORSTAT_Msk           (0x2UL)                   /*!< PORSTAT (Bitfield-Mask: 0x01)                         */
43081 #define RSTGEN_STAT_EXRSTAT_Pos           (0UL)                     /*!< EXRSTAT (Bit 0)                                       */
43082 #define RSTGEN_STAT_EXRSTAT_Msk           (0x1UL)                   /*!< EXRSTAT (Bitfield-Mask: 0x01)                         */
43083 
43084 
43085 /* =========================================================================================================================== */
43086 /* ================                                            RTC                                            ================ */
43087 /* =========================================================================================================================== */
43088 
43089 /* ========================================================  RTCCTL  ========================================================= */
43090 #define RTC_RTCCTL_RSTOP_Pos              (4UL)                     /*!< RSTOP (Bit 4)                                         */
43091 #define RTC_RTCCTL_RSTOP_Msk              (0x10UL)                  /*!< RSTOP (Bitfield-Mask: 0x01)                           */
43092 #define RTC_RTCCTL_RPT_Pos                (1UL)                     /*!< RPT (Bit 1)                                           */
43093 #define RTC_RTCCTL_RPT_Msk                (0xeUL)                   /*!< RPT (Bitfield-Mask: 0x07)                             */
43094 #define RTC_RTCCTL_WRTC_Pos               (0UL)                     /*!< WRTC (Bit 0)                                          */
43095 #define RTC_RTCCTL_WRTC_Msk               (0x1UL)                   /*!< WRTC (Bitfield-Mask: 0x01)                            */
43096 /* ========================================================  RTCSTAT  ======================================================== */
43097 #define RTC_RTCSTAT_WRITEBUSY_Pos         (0UL)                     /*!< WRITEBUSY (Bit 0)                                     */
43098 #define RTC_RTCSTAT_WRITEBUSY_Msk         (0x1UL)                   /*!< WRITEBUSY (Bitfield-Mask: 0x01)                       */
43099 /* ========================================================  CTRLOW  ========================================================= */
43100 #define RTC_CTRLOW_CTRHR_Pos              (24UL)                    /*!< CTRHR (Bit 24)                                        */
43101 #define RTC_CTRLOW_CTRHR_Msk              (0x3f000000UL)            /*!< CTRHR (Bitfield-Mask: 0x3f)                           */
43102 #define RTC_CTRLOW_CTRMIN_Pos             (16UL)                    /*!< CTRMIN (Bit 16)                                       */
43103 #define RTC_CTRLOW_CTRMIN_Msk             (0x7f0000UL)              /*!< CTRMIN (Bitfield-Mask: 0x7f)                          */
43104 #define RTC_CTRLOW_CTRSEC_Pos             (8UL)                     /*!< CTRSEC (Bit 8)                                        */
43105 #define RTC_CTRLOW_CTRSEC_Msk             (0x7f00UL)                /*!< CTRSEC (Bitfield-Mask: 0x7f)                          */
43106 #define RTC_CTRLOW_CTR100_Pos             (0UL)                     /*!< CTR100 (Bit 0)                                        */
43107 #define RTC_CTRLOW_CTR100_Msk             (0xffUL)                  /*!< CTR100 (Bitfield-Mask: 0xff)                          */
43108 /* =========================================================  CTRUP  ========================================================= */
43109 #define RTC_CTRUP_CTERR_Pos               (31UL)                    /*!< CTERR (Bit 31)                                        */
43110 #define RTC_CTRUP_CTERR_Msk               (0x80000000UL)            /*!< CTERR (Bitfield-Mask: 0x01)                           */
43111 #define RTC_CTRUP_CEB_Pos                 (29UL)                    /*!< CEB (Bit 29)                                          */
43112 #define RTC_CTRUP_CEB_Msk                 (0x20000000UL)            /*!< CEB (Bitfield-Mask: 0x01)                             */
43113 #define RTC_CTRUP_CB_Pos                  (28UL)                    /*!< CB (Bit 28)                                           */
43114 #define RTC_CTRUP_CB_Msk                  (0x10000000UL)            /*!< CB (Bitfield-Mask: 0x01)                              */
43115 #define RTC_CTRUP_CTRWKDY_Pos             (24UL)                    /*!< CTRWKDY (Bit 24)                                      */
43116 #define RTC_CTRUP_CTRWKDY_Msk             (0x7000000UL)             /*!< CTRWKDY (Bitfield-Mask: 0x07)                         */
43117 #define RTC_CTRUP_CTRYR_Pos               (16UL)                    /*!< CTRYR (Bit 16)                                        */
43118 #define RTC_CTRUP_CTRYR_Msk               (0xff0000UL)              /*!< CTRYR (Bitfield-Mask: 0xff)                           */
43119 #define RTC_CTRUP_CTRMO_Pos               (8UL)                     /*!< CTRMO (Bit 8)                                         */
43120 #define RTC_CTRUP_CTRMO_Msk               (0x1f00UL)                /*!< CTRMO (Bitfield-Mask: 0x1f)                           */
43121 #define RTC_CTRUP_CTRDATE_Pos             (0UL)                     /*!< CTRDATE (Bit 0)                                       */
43122 #define RTC_CTRUP_CTRDATE_Msk             (0x3fUL)                  /*!< CTRDATE (Bitfield-Mask: 0x3f)                         */
43123 /* ========================================================  ALMLOW  ========================================================= */
43124 #define RTC_ALMLOW_ALMHR_Pos              (24UL)                    /*!< ALMHR (Bit 24)                                        */
43125 #define RTC_ALMLOW_ALMHR_Msk              (0x3f000000UL)            /*!< ALMHR (Bitfield-Mask: 0x3f)                           */
43126 #define RTC_ALMLOW_ALMMIN_Pos             (16UL)                    /*!< ALMMIN (Bit 16)                                       */
43127 #define RTC_ALMLOW_ALMMIN_Msk             (0x7f0000UL)              /*!< ALMMIN (Bitfield-Mask: 0x7f)                          */
43128 #define RTC_ALMLOW_ALMSEC_Pos             (8UL)                     /*!< ALMSEC (Bit 8)                                        */
43129 #define RTC_ALMLOW_ALMSEC_Msk             (0x7f00UL)                /*!< ALMSEC (Bitfield-Mask: 0x7f)                          */
43130 #define RTC_ALMLOW_ALM100_Pos             (0UL)                     /*!< ALM100 (Bit 0)                                        */
43131 #define RTC_ALMLOW_ALM100_Msk             (0xffUL)                  /*!< ALM100 (Bitfield-Mask: 0xff)                          */
43132 /* =========================================================  ALMUP  ========================================================= */
43133 #define RTC_ALMUP_ALMWKDY_Pos             (16UL)                    /*!< ALMWKDY (Bit 16)                                      */
43134 #define RTC_ALMUP_ALMWKDY_Msk             (0x70000UL)               /*!< ALMWKDY (Bitfield-Mask: 0x07)                         */
43135 #define RTC_ALMUP_ALMMO_Pos               (8UL)                     /*!< ALMMO (Bit 8)                                         */
43136 #define RTC_ALMUP_ALMMO_Msk               (0x1f00UL)                /*!< ALMMO (Bitfield-Mask: 0x1f)                           */
43137 #define RTC_ALMUP_ALMDATE_Pos             (0UL)                     /*!< ALMDATE (Bit 0)                                       */
43138 #define RTC_ALMUP_ALMDATE_Msk             (0x3fUL)                  /*!< ALMDATE (Bitfield-Mask: 0x3f)                         */
43139 /* =========================================================  INTEN  ========================================================= */
43140 #define RTC_INTEN_ALM_Pos                 (0UL)                     /*!< ALM (Bit 0)                                           */
43141 #define RTC_INTEN_ALM_Msk                 (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43142 /* ========================================================  INTSTAT  ======================================================== */
43143 #define RTC_INTSTAT_ALM_Pos               (0UL)                     /*!< ALM (Bit 0)                                           */
43144 #define RTC_INTSTAT_ALM_Msk               (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43145 /* ========================================================  INTCLR  ========================================================= */
43146 #define RTC_INTCLR_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
43147 #define RTC_INTCLR_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43148 /* ========================================================  INTSET  ========================================================= */
43149 #define RTC_INTSET_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
43150 #define RTC_INTSET_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43151 
43152 
43153 /* =========================================================================================================================== */
43154 /* ================                                           SDIO                                            ================ */
43155 /* =========================================================================================================================== */
43156 
43157 /* =========================================================  SDMA  ========================================================== */
43158 #define SDIO_SDMA_SDMASYSTEMADDRESS_Pos   (0UL)                     /*!< SDMASYSTEMADDRESS (Bit 0)                             */
43159 #define SDIO_SDMA_SDMASYSTEMADDRESS_Msk   (0xffffffffUL)            /*!< SDMASYSTEMADDRESS (Bitfield-Mask: 0xffffffff)         */
43160 /* =========================================================  BLOCK  ========================================================= */
43161 #define SDIO_BLOCK_BLKCNT_Pos             (16UL)                    /*!< BLKCNT (Bit 16)                                       */
43162 #define SDIO_BLOCK_BLKCNT_Msk             (0xffff0000UL)            /*!< BLKCNT (Bitfield-Mask: 0xffff)                        */
43163 #define SDIO_BLOCK_HOSTSDMABUFSZ_Pos      (12UL)                    /*!< HOSTSDMABUFSZ (Bit 12)                                */
43164 #define SDIO_BLOCK_HOSTSDMABUFSZ_Msk      (0x7000UL)                /*!< HOSTSDMABUFSZ (Bitfield-Mask: 0x07)                   */
43165 #define SDIO_BLOCK_TRANSFERBLOCKSIZE_Pos  (0UL)                     /*!< TRANSFERBLOCKSIZE (Bit 0)                             */
43166 #define SDIO_BLOCK_TRANSFERBLOCKSIZE_Msk  (0xfffUL)                 /*!< TRANSFERBLOCKSIZE (Bitfield-Mask: 0xfff)              */
43167 /* =======================================================  ARGUMENT1  ======================================================= */
43168 #define SDIO_ARGUMENT1_CMDARG1_Pos        (0UL)                     /*!< CMDARG1 (Bit 0)                                       */
43169 #define SDIO_ARGUMENT1_CMDARG1_Msk        (0xffffffffUL)            /*!< CMDARG1 (Bitfield-Mask: 0xffffffff)                   */
43170 /* =======================================================  TRANSFER  ======================================================== */
43171 #define SDIO_TRANSFER_CMDIDX_Pos          (24UL)                    /*!< CMDIDX (Bit 24)                                       */
43172 #define SDIO_TRANSFER_CMDIDX_Msk          (0x3f000000UL)            /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
43173 #define SDIO_TRANSFER_CMDTYPE_Pos         (22UL)                    /*!< CMDTYPE (Bit 22)                                      */
43174 #define SDIO_TRANSFER_CMDTYPE_Msk         (0xc00000UL)              /*!< CMDTYPE (Bitfield-Mask: 0x03)                         */
43175 #define SDIO_TRANSFER_DATAPRSNTSEL_Pos    (21UL)                    /*!< DATAPRSNTSEL (Bit 21)                                 */
43176 #define SDIO_TRANSFER_DATAPRSNTSEL_Msk    (0x200000UL)              /*!< DATAPRSNTSEL (Bitfield-Mask: 0x01)                    */
43177 #define SDIO_TRANSFER_CMDIDXCHKEN_Pos     (20UL)                    /*!< CMDIDXCHKEN (Bit 20)                                  */
43178 #define SDIO_TRANSFER_CMDIDXCHKEN_Msk     (0x100000UL)              /*!< CMDIDXCHKEN (Bitfield-Mask: 0x01)                     */
43179 #define SDIO_TRANSFER_CMDCRCCHKEN_Pos     (19UL)                    /*!< CMDCRCCHKEN (Bit 19)                                  */
43180 #define SDIO_TRANSFER_CMDCRCCHKEN_Msk     (0x80000UL)               /*!< CMDCRCCHKEN (Bitfield-Mask: 0x01)                     */
43181 #define SDIO_TRANSFER_RESPTYPESEL_Pos     (16UL)                    /*!< RESPTYPESEL (Bit 16)                                  */
43182 #define SDIO_TRANSFER_RESPTYPESEL_Msk     (0x30000UL)               /*!< RESPTYPESEL (Bitfield-Mask: 0x03)                     */
43183 #define SDIO_TRANSFER_BLKSEL_Pos          (5UL)                     /*!< BLKSEL (Bit 5)                                        */
43184 #define SDIO_TRANSFER_BLKSEL_Msk          (0x20UL)                  /*!< BLKSEL (Bitfield-Mask: 0x01)                          */
43185 #define SDIO_TRANSFER_DXFERDIRSEL_Pos     (4UL)                     /*!< DXFERDIRSEL (Bit 4)                                   */
43186 #define SDIO_TRANSFER_DXFERDIRSEL_Msk     (0x10UL)                  /*!< DXFERDIRSEL (Bitfield-Mask: 0x01)                     */
43187 #define SDIO_TRANSFER_ACMDEN_Pos          (2UL)                     /*!< ACMDEN (Bit 2)                                        */
43188 #define SDIO_TRANSFER_ACMDEN_Msk          (0xcUL)                   /*!< ACMDEN (Bitfield-Mask: 0x03)                          */
43189 #define SDIO_TRANSFER_BLKCNTEN_Pos        (1UL)                     /*!< BLKCNTEN (Bit 1)                                      */
43190 #define SDIO_TRANSFER_BLKCNTEN_Msk        (0x2UL)                   /*!< BLKCNTEN (Bitfield-Mask: 0x01)                        */
43191 #define SDIO_TRANSFER_DMAEN_Pos           (0UL)                     /*!< DMAEN (Bit 0)                                         */
43192 #define SDIO_TRANSFER_DMAEN_Msk           (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
43193 /* =======================================================  RESPONSE0  ======================================================= */
43194 #define SDIO_RESPONSE0_CMDRESP0_Pos       (0UL)                     /*!< CMDRESP0 (Bit 0)                                      */
43195 #define SDIO_RESPONSE0_CMDRESP0_Msk       (0xffffffffUL)            /*!< CMDRESP0 (Bitfield-Mask: 0xffffffff)                  */
43196 /* =======================================================  RESPONSE1  ======================================================= */
43197 #define SDIO_RESPONSE1_CMDRESP1_Pos       (0UL)                     /*!< CMDRESP1 (Bit 0)                                      */
43198 #define SDIO_RESPONSE1_CMDRESP1_Msk       (0xffffffffUL)            /*!< CMDRESP1 (Bitfield-Mask: 0xffffffff)                  */
43199 /* =======================================================  RESPONSE2  ======================================================= */
43200 #define SDIO_RESPONSE2_CMDRESP2_Pos       (0UL)                     /*!< CMDRESP2 (Bit 0)                                      */
43201 #define SDIO_RESPONSE2_CMDRESP2_Msk       (0xffffffffUL)            /*!< CMDRESP2 (Bitfield-Mask: 0xffffffff)                  */
43202 /* =======================================================  RESPONSE3  ======================================================= */
43203 #define SDIO_RESPONSE3_CMDRESP3_Pos       (0UL)                     /*!< CMDRESP3 (Bit 0)                                      */
43204 #define SDIO_RESPONSE3_CMDRESP3_Msk       (0xffffffffUL)            /*!< CMDRESP3 (Bitfield-Mask: 0xffffffff)                  */
43205 /* ========================================================  BUFFER  ========================================================= */
43206 #define SDIO_BUFFER_BUFFERDATA_Pos        (0UL)                     /*!< BUFFERDATA (Bit 0)                                    */
43207 #define SDIO_BUFFER_BUFFERDATA_Msk        (0xffffffffUL)            /*!< BUFFERDATA (Bitfield-Mask: 0xffffffff)                */
43208 /* ========================================================  PRESENT  ======================================================== */
43209 #define SDIO_PRESENT_DAT74LINE_Pos        (25UL)                    /*!< DAT74LINE (Bit 25)                                    */
43210 #define SDIO_PRESENT_DAT74LINE_Msk        (0x1e000000UL)            /*!< DAT74LINE (Bitfield-Mask: 0x0f)                       */
43211 #define SDIO_PRESENT_CMDLINE_Pos          (24UL)                    /*!< CMDLINE (Bit 24)                                      */
43212 #define SDIO_PRESENT_CMDLINE_Msk          (0x1000000UL)             /*!< CMDLINE (Bitfield-Mask: 0x01)                         */
43213 #define SDIO_PRESENT_DAT30LINE_Pos        (20UL)                    /*!< DAT30LINE (Bit 20)                                    */
43214 #define SDIO_PRESENT_DAT30LINE_Msk        (0xf00000UL)              /*!< DAT30LINE (Bitfield-Mask: 0x0f)                       */
43215 #define SDIO_PRESENT_WRPROTSW_Pos         (19UL)                    /*!< WRPROTSW (Bit 19)                                     */
43216 #define SDIO_PRESENT_WRPROTSW_Msk         (0x80000UL)               /*!< WRPROTSW (Bitfield-Mask: 0x01)                        */
43217 #define SDIO_PRESENT_CARDDET_Pos          (18UL)                    /*!< CARDDET (Bit 18)                                      */
43218 #define SDIO_PRESENT_CARDDET_Msk          (0x40000UL)               /*!< CARDDET (Bitfield-Mask: 0x01)                         */
43219 #define SDIO_PRESENT_CARDSTABLE_Pos       (17UL)                    /*!< CARDSTABLE (Bit 17)                                   */
43220 #define SDIO_PRESENT_CARDSTABLE_Msk       (0x20000UL)               /*!< CARDSTABLE (Bitfield-Mask: 0x01)                      */
43221 #define SDIO_PRESENT_CARDINSERTED_Pos     (16UL)                    /*!< CARDINSERTED (Bit 16)                                 */
43222 #define SDIO_PRESENT_CARDINSERTED_Msk     (0x10000UL)               /*!< CARDINSERTED (Bitfield-Mask: 0x01)                    */
43223 #define SDIO_PRESENT_BUFRDEN_Pos          (11UL)                    /*!< BUFRDEN (Bit 11)                                      */
43224 #define SDIO_PRESENT_BUFRDEN_Msk          (0x800UL)                 /*!< BUFRDEN (Bitfield-Mask: 0x01)                         */
43225 #define SDIO_PRESENT_BUFWREN_Pos          (10UL)                    /*!< BUFWREN (Bit 10)                                      */
43226 #define SDIO_PRESENT_BUFWREN_Msk          (0x400UL)                 /*!< BUFWREN (Bitfield-Mask: 0x01)                         */
43227 #define SDIO_PRESENT_RDXFERACT_Pos        (9UL)                     /*!< RDXFERACT (Bit 9)                                     */
43228 #define SDIO_PRESENT_RDXFERACT_Msk        (0x200UL)                 /*!< RDXFERACT (Bitfield-Mask: 0x01)                       */
43229 #define SDIO_PRESENT_WRXFERACT_Pos        (8UL)                     /*!< WRXFERACT (Bit 8)                                     */
43230 #define SDIO_PRESENT_WRXFERACT_Msk        (0x100UL)                 /*!< WRXFERACT (Bitfield-Mask: 0x01)                       */
43231 #define SDIO_PRESENT_RETUNINGREQUEST_Pos  (3UL)                     /*!< RETUNINGREQUEST (Bit 3)                               */
43232 #define SDIO_PRESENT_RETUNINGREQUEST_Msk  (0x8UL)                   /*!< RETUNINGREQUEST (Bitfield-Mask: 0x01)                 */
43233 #define SDIO_PRESENT_DLINEACT_Pos         (2UL)                     /*!< DLINEACT (Bit 2)                                      */
43234 #define SDIO_PRESENT_DLINEACT_Msk         (0x4UL)                   /*!< DLINEACT (Bitfield-Mask: 0x01)                        */
43235 #define SDIO_PRESENT_CMDINHDAT_Pos        (1UL)                     /*!< CMDINHDAT (Bit 1)                                     */
43236 #define SDIO_PRESENT_CMDINHDAT_Msk        (0x2UL)                   /*!< CMDINHDAT (Bitfield-Mask: 0x01)                       */
43237 #define SDIO_PRESENT_CMDINHCMD_Pos        (0UL)                     /*!< CMDINHCMD (Bit 0)                                     */
43238 #define SDIO_PRESENT_CMDINHCMD_Msk        (0x1UL)                   /*!< CMDINHCMD (Bitfield-Mask: 0x01)                       */
43239 /* =======================================================  HOSTCTRL1  ======================================================= */
43240 #define SDIO_HOSTCTRL1_WUENCARDREMOVL_Pos (26UL)                    /*!< WUENCARDREMOVL (Bit 26)                               */
43241 #define SDIO_HOSTCTRL1_WUENCARDREMOVL_Msk (0x4000000UL)             /*!< WUENCARDREMOVL (Bitfield-Mask: 0x01)                  */
43242 #define SDIO_HOSTCTRL1_WUENCARDINSERT_Pos (25UL)                    /*!< WUENCARDINSERT (Bit 25)                               */
43243 #define SDIO_HOSTCTRL1_WUENCARDINSERT_Msk (0x2000000UL)             /*!< WUENCARDINSERT (Bitfield-Mask: 0x01)                  */
43244 #define SDIO_HOSTCTRL1_WUENCARDINT_Pos    (24UL)                    /*!< WUENCARDINT (Bit 24)                                  */
43245 #define SDIO_HOSTCTRL1_WUENCARDINT_Msk    (0x1000000UL)             /*!< WUENCARDINT (Bitfield-Mask: 0x01)                     */
43246 #define SDIO_HOSTCTRL1_BOOTACKCHK_Pos     (23UL)                    /*!< BOOTACKCHK (Bit 23)                                   */
43247 #define SDIO_HOSTCTRL1_BOOTACKCHK_Msk     (0x800000UL)              /*!< BOOTACKCHK (Bitfield-Mask: 0x01)                      */
43248 #define SDIO_HOSTCTRL1_ALTBOOTEN_Pos      (22UL)                    /*!< ALTBOOTEN (Bit 22)                                    */
43249 #define SDIO_HOSTCTRL1_ALTBOOTEN_Msk      (0x400000UL)              /*!< ALTBOOTEN (Bitfield-Mask: 0x01)                       */
43250 #define SDIO_HOSTCTRL1_BOOTEN_Pos         (21UL)                    /*!< BOOTEN (Bit 21)                                       */
43251 #define SDIO_HOSTCTRL1_BOOTEN_Msk         (0x200000UL)              /*!< BOOTEN (Bitfield-Mask: 0x01)                          */
43252 #define SDIO_HOSTCTRL1_SPIMODE_Pos        (20UL)                    /*!< SPIMODE (Bit 20)                                      */
43253 #define SDIO_HOSTCTRL1_SPIMODE_Msk        (0x100000UL)              /*!< SPIMODE (Bitfield-Mask: 0x01)                         */
43254 #define SDIO_HOSTCTRL1_GAP_Pos            (19UL)                    /*!< GAP (Bit 19)                                          */
43255 #define SDIO_HOSTCTRL1_GAP_Msk            (0x80000UL)               /*!< GAP (Bitfield-Mask: 0x01)                             */
43256 #define SDIO_HOSTCTRL1_READWAITCTRL_Pos   (18UL)                    /*!< READWAITCTRL (Bit 18)                                 */
43257 #define SDIO_HOSTCTRL1_READWAITCTRL_Msk   (0x40000UL)               /*!< READWAITCTRL (Bitfield-Mask: 0x01)                    */
43258 #define SDIO_HOSTCTRL1_CONTREQ_Pos        (17UL)                    /*!< CONTREQ (Bit 17)                                      */
43259 #define SDIO_HOSTCTRL1_CONTREQ_Msk        (0x20000UL)               /*!< CONTREQ (Bitfield-Mask: 0x01)                         */
43260 #define SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Pos (16UL)             /*!< STOPATBLOCKGAPREQUEST (Bit 16)                        */
43261 #define SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Msk (0x10000UL)        /*!< STOPATBLOCKGAPREQUEST (Bitfield-Mask: 0x01)           */
43262 #define SDIO_HOSTCTRL1_HWRESET_Pos        (12UL)                    /*!< HWRESET (Bit 12)                                      */
43263 #define SDIO_HOSTCTRL1_HWRESET_Msk        (0x1000UL)                /*!< HWRESET (Bitfield-Mask: 0x01)                         */
43264 #define SDIO_HOSTCTRL1_VOLTSELECT_Pos     (9UL)                     /*!< VOLTSELECT (Bit 9)                                    */
43265 #define SDIO_HOSTCTRL1_VOLTSELECT_Msk     (0xe00UL)                 /*!< VOLTSELECT (Bitfield-Mask: 0x07)                      */
43266 #define SDIO_HOSTCTRL1_SDBUSPOWER_Pos     (8UL)                     /*!< SDBUSPOWER (Bit 8)                                    */
43267 #define SDIO_HOSTCTRL1_SDBUSPOWER_Msk     (0x100UL)                 /*!< SDBUSPOWER (Bitfield-Mask: 0x01)                      */
43268 #define SDIO_HOSTCTRL1_CARDSRC_Pos        (7UL)                     /*!< CARDSRC (Bit 7)                                       */
43269 #define SDIO_HOSTCTRL1_CARDSRC_Msk        (0x80UL)                  /*!< CARDSRC (Bitfield-Mask: 0x01)                         */
43270 #define SDIO_HOSTCTRL1_TESTLEVEL_Pos      (6UL)                     /*!< TESTLEVEL (Bit 6)                                     */
43271 #define SDIO_HOSTCTRL1_TESTLEVEL_Msk      (0x40UL)                  /*!< TESTLEVEL (Bitfield-Mask: 0x01)                       */
43272 #define SDIO_HOSTCTRL1_XFERWIDTH_Pos      (5UL)                     /*!< XFERWIDTH (Bit 5)                                     */
43273 #define SDIO_HOSTCTRL1_XFERWIDTH_Msk      (0x20UL)                  /*!< XFERWIDTH (Bitfield-Mask: 0x01)                       */
43274 #define SDIO_HOSTCTRL1_DMASELECT_Pos      (3UL)                     /*!< DMASELECT (Bit 3)                                     */
43275 #define SDIO_HOSTCTRL1_DMASELECT_Msk      (0x18UL)                  /*!< DMASELECT (Bitfield-Mask: 0x03)                       */
43276 #define SDIO_HOSTCTRL1_HISPEEDEN_Pos      (2UL)                     /*!< HISPEEDEN (Bit 2)                                     */
43277 #define SDIO_HOSTCTRL1_HISPEEDEN_Msk      (0x4UL)                   /*!< HISPEEDEN (Bitfield-Mask: 0x01)                       */
43278 #define SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Pos (1UL)                  /*!< DATATRANSFERWIDTH (Bit 1)                             */
43279 #define SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Msk (0x2UL)                /*!< DATATRANSFERWIDTH (Bitfield-Mask: 0x01)               */
43280 #define SDIO_HOSTCTRL1_LEDCONTROL_Pos     (0UL)                     /*!< LEDCONTROL (Bit 0)                                    */
43281 #define SDIO_HOSTCTRL1_LEDCONTROL_Msk     (0x1UL)                   /*!< LEDCONTROL (Bitfield-Mask: 0x01)                      */
43282 /* =======================================================  CLOCKCTRL  ======================================================= */
43283 #define SDIO_CLOCKCTRL_SWRSTDAT_Pos       (26UL)                    /*!< SWRSTDAT (Bit 26)                                     */
43284 #define SDIO_CLOCKCTRL_SWRSTDAT_Msk       (0x4000000UL)             /*!< SWRSTDAT (Bitfield-Mask: 0x01)                        */
43285 #define SDIO_CLOCKCTRL_SWRSTCMD_Pos       (25UL)                    /*!< SWRSTCMD (Bit 25)                                     */
43286 #define SDIO_CLOCKCTRL_SWRSTCMD_Msk       (0x2000000UL)             /*!< SWRSTCMD (Bitfield-Mask: 0x01)                        */
43287 #define SDIO_CLOCKCTRL_SWRSTALL_Pos       (24UL)                    /*!< SWRSTALL (Bit 24)                                     */
43288 #define SDIO_CLOCKCTRL_SWRSTALL_Msk       (0x1000000UL)             /*!< SWRSTALL (Bitfield-Mask: 0x01)                        */
43289 #define SDIO_CLOCKCTRL_TIMEOUTCNT_Pos     (16UL)                    /*!< TIMEOUTCNT (Bit 16)                                   */
43290 #define SDIO_CLOCKCTRL_TIMEOUTCNT_Msk     (0xf0000UL)               /*!< TIMEOUTCNT (Bitfield-Mask: 0x0f)                      */
43291 #define SDIO_CLOCKCTRL_FREQSEL_Pos        (8UL)                     /*!< FREQSEL (Bit 8)                                       */
43292 #define SDIO_CLOCKCTRL_FREQSEL_Msk        (0xff00UL)                /*!< FREQSEL (Bitfield-Mask: 0xff)                         */
43293 #define SDIO_CLOCKCTRL_UPRCLKDIV_Pos      (6UL)                     /*!< UPRCLKDIV (Bit 6)                                     */
43294 #define SDIO_CLOCKCTRL_UPRCLKDIV_Msk      (0xc0UL)                  /*!< UPRCLKDIV (Bitfield-Mask: 0x03)                       */
43295 #define SDIO_CLOCKCTRL_CLKGENSEL_Pos      (5UL)                     /*!< CLKGENSEL (Bit 5)                                     */
43296 #define SDIO_CLOCKCTRL_CLKGENSEL_Msk      (0x20UL)                  /*!< CLKGENSEL (Bitfield-Mask: 0x01)                       */
43297 #define SDIO_CLOCKCTRL_SDCLKEN_Pos        (2UL)                     /*!< SDCLKEN (Bit 2)                                       */
43298 #define SDIO_CLOCKCTRL_SDCLKEN_Msk        (0x4UL)                   /*!< SDCLKEN (Bitfield-Mask: 0x01)                         */
43299 #define SDIO_CLOCKCTRL_CLKSTABLE_Pos      (1UL)                     /*!< CLKSTABLE (Bit 1)                                     */
43300 #define SDIO_CLOCKCTRL_CLKSTABLE_Msk      (0x2UL)                   /*!< CLKSTABLE (Bitfield-Mask: 0x01)                       */
43301 #define SDIO_CLOCKCTRL_CLKEN_Pos          (0UL)                     /*!< CLKEN (Bit 0)                                         */
43302 #define SDIO_CLOCKCTRL_CLKEN_Msk          (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
43303 /* ========================================================  INTSTAT  ======================================================== */
43304 #define SDIO_INTSTAT_VNDERRSTAT_Pos       (29UL)                    /*!< VNDERRSTAT (Bit 29)                                   */
43305 #define SDIO_INTSTAT_VNDERRSTAT_Msk       (0xe0000000UL)            /*!< VNDERRSTAT (Bitfield-Mask: 0x07)                      */
43306 #define SDIO_INTSTAT_TGTRESPERR_Pos       (28UL)                    /*!< TGTRESPERR (Bit 28)                                   */
43307 #define SDIO_INTSTAT_TGTRESPERR_Msk       (0x10000000UL)            /*!< TGTRESPERR (Bitfield-Mask: 0x01)                      */
43308 #define SDIO_INTSTAT_ADMAERROR_Pos        (25UL)                    /*!< ADMAERROR (Bit 25)                                    */
43309 #define SDIO_INTSTAT_ADMAERROR_Msk        (0x2000000UL)             /*!< ADMAERROR (Bitfield-Mask: 0x01)                       */
43310 #define SDIO_INTSTAT_AUTOCMDERROR_Pos     (24UL)                    /*!< AUTOCMDERROR (Bit 24)                                 */
43311 #define SDIO_INTSTAT_AUTOCMDERROR_Msk     (0x1000000UL)             /*!< AUTOCMDERROR (Bitfield-Mask: 0x01)                    */
43312 #define SDIO_INTSTAT_CURRENTLIMITERROR_Pos (23UL)                   /*!< CURRENTLIMITERROR (Bit 23)                            */
43313 #define SDIO_INTSTAT_CURRENTLIMITERROR_Msk (0x800000UL)             /*!< CURRENTLIMITERROR (Bitfield-Mask: 0x01)               */
43314 #define SDIO_INTSTAT_DATAENDBITERROR_Pos  (22UL)                    /*!< DATAENDBITERROR (Bit 22)                              */
43315 #define SDIO_INTSTAT_DATAENDBITERROR_Msk  (0x400000UL)              /*!< DATAENDBITERROR (Bitfield-Mask: 0x01)                 */
43316 #define SDIO_INTSTAT_DATACRCERROR_Pos     (21UL)                    /*!< DATACRCERROR (Bit 21)                                 */
43317 #define SDIO_INTSTAT_DATACRCERROR_Msk     (0x200000UL)              /*!< DATACRCERROR (Bitfield-Mask: 0x01)                    */
43318 #define SDIO_INTSTAT_DATATIMEOUTERROR_Pos (20UL)                    /*!< DATATIMEOUTERROR (Bit 20)                             */
43319 #define SDIO_INTSTAT_DATATIMEOUTERROR_Msk (0x100000UL)              /*!< DATATIMEOUTERROR (Bitfield-Mask: 0x01)                */
43320 #define SDIO_INTSTAT_COMMANDINDEXERROR_Pos (19UL)                   /*!< COMMANDINDEXERROR (Bit 19)                            */
43321 #define SDIO_INTSTAT_COMMANDINDEXERROR_Msk (0x80000UL)              /*!< COMMANDINDEXERROR (Bitfield-Mask: 0x01)               */
43322 #define SDIO_INTSTAT_COMMANDENDBITERROR_Pos (18UL)                  /*!< COMMANDENDBITERROR (Bit 18)                           */
43323 #define SDIO_INTSTAT_COMMANDENDBITERROR_Msk (0x40000UL)             /*!< COMMANDENDBITERROR (Bitfield-Mask: 0x01)              */
43324 #define SDIO_INTSTAT_COMMANDCRCERROR_Pos  (17UL)                    /*!< COMMANDCRCERROR (Bit 17)                              */
43325 #define SDIO_INTSTAT_COMMANDCRCERROR_Msk  (0x20000UL)               /*!< COMMANDCRCERROR (Bitfield-Mask: 0x01)                 */
43326 #define SDIO_INTSTAT_COMMANDTIMEOUTERROR_Pos (16UL)                 /*!< COMMANDTIMEOUTERROR (Bit 16)                          */
43327 #define SDIO_INTSTAT_COMMANDTIMEOUTERROR_Msk (0x10000UL)            /*!< COMMANDTIMEOUTERROR (Bitfield-Mask: 0x01)             */
43328 #define SDIO_INTSTAT_ERRORINTERRUPT_Pos   (15UL)                    /*!< ERRORINTERRUPT (Bit 15)                               */
43329 #define SDIO_INTSTAT_ERRORINTERRUPT_Msk   (0x8000UL)                /*!< ERRORINTERRUPT (Bitfield-Mask: 0x01)                  */
43330 #define SDIO_INTSTAT_BOOTTERMINATE_Pos    (14UL)                    /*!< BOOTTERMINATE (Bit 14)                                */
43331 #define SDIO_INTSTAT_BOOTTERMINATE_Msk    (0x4000UL)                /*!< BOOTTERMINATE (Bitfield-Mask: 0x01)                   */
43332 #define SDIO_INTSTAT_BOOTACKRCV_Pos       (13UL)                    /*!< BOOTACKRCV (Bit 13)                                   */
43333 #define SDIO_INTSTAT_BOOTACKRCV_Msk       (0x2000UL)                /*!< BOOTACKRCV (Bitfield-Mask: 0x01)                      */
43334 #define SDIO_INTSTAT_RETUNINGEVENT_Pos    (12UL)                    /*!< RETUNINGEVENT (Bit 12)                                */
43335 #define SDIO_INTSTAT_RETUNINGEVENT_Msk    (0x1000UL)                /*!< RETUNINGEVENT (Bitfield-Mask: 0x01)                   */
43336 #define SDIO_INTSTAT_INTC_Pos             (11UL)                    /*!< INTC (Bit 11)                                         */
43337 #define SDIO_INTSTAT_INTC_Msk             (0x800UL)                 /*!< INTC (Bitfield-Mask: 0x01)                            */
43338 #define SDIO_INTSTAT_INTB_Pos             (10UL)                    /*!< INTB (Bit 10)                                         */
43339 #define SDIO_INTSTAT_INTB_Msk             (0x400UL)                 /*!< INTB (Bitfield-Mask: 0x01)                            */
43340 #define SDIO_INTSTAT_INTA_Pos             (9UL)                     /*!< INTA (Bit 9)                                          */
43341 #define SDIO_INTSTAT_INTA_Msk             (0x200UL)                 /*!< INTA (Bitfield-Mask: 0x01)                            */
43342 #define SDIO_INTSTAT_CARDINTERRUPT_Pos    (8UL)                     /*!< CARDINTERRUPT (Bit 8)                                 */
43343 #define SDIO_INTSTAT_CARDINTERRUPT_Msk    (0x100UL)                 /*!< CARDINTERRUPT (Bitfield-Mask: 0x01)                   */
43344 #define SDIO_INTSTAT_CARDREMOVAL_Pos      (7UL)                     /*!< CARDREMOVAL (Bit 7)                                   */
43345 #define SDIO_INTSTAT_CARDREMOVAL_Msk      (0x80UL)                  /*!< CARDREMOVAL (Bitfield-Mask: 0x01)                     */
43346 #define SDIO_INTSTAT_CARDINSERTION_Pos    (6UL)                     /*!< CARDINSERTION (Bit 6)                                 */
43347 #define SDIO_INTSTAT_CARDINSERTION_Msk    (0x40UL)                  /*!< CARDINSERTION (Bitfield-Mask: 0x01)                   */
43348 #define SDIO_INTSTAT_BUFFERREADREADY_Pos  (5UL)                     /*!< BUFFERREADREADY (Bit 5)                               */
43349 #define SDIO_INTSTAT_BUFFERREADREADY_Msk  (0x20UL)                  /*!< BUFFERREADREADY (Bitfield-Mask: 0x01)                 */
43350 #define SDIO_INTSTAT_BUFFERWRITEREADY_Pos (4UL)                     /*!< BUFFERWRITEREADY (Bit 4)                              */
43351 #define SDIO_INTSTAT_BUFFERWRITEREADY_Msk (0x10UL)                  /*!< BUFFERWRITEREADY (Bitfield-Mask: 0x01)                */
43352 #define SDIO_INTSTAT_DMAINTERRUPT_Pos     (3UL)                     /*!< DMAINTERRUPT (Bit 3)                                  */
43353 #define SDIO_INTSTAT_DMAINTERRUPT_Msk     (0x8UL)                   /*!< DMAINTERRUPT (Bitfield-Mask: 0x01)                    */
43354 #define SDIO_INTSTAT_BLOCKGAPEVENT_Pos    (2UL)                     /*!< BLOCKGAPEVENT (Bit 2)                                 */
43355 #define SDIO_INTSTAT_BLOCKGAPEVENT_Msk    (0x4UL)                   /*!< BLOCKGAPEVENT (Bitfield-Mask: 0x01)                   */
43356 #define SDIO_INTSTAT_TRANSFERCOMPLETE_Pos (1UL)                     /*!< TRANSFERCOMPLETE (Bit 1)                              */
43357 #define SDIO_INTSTAT_TRANSFERCOMPLETE_Msk (0x2UL)                   /*!< TRANSFERCOMPLETE (Bitfield-Mask: 0x01)                */
43358 #define SDIO_INTSTAT_COMMANDCOMPLETE_Pos  (0UL)                     /*!< COMMANDCOMPLETE (Bit 0)                               */
43359 #define SDIO_INTSTAT_COMMANDCOMPLETE_Msk  (0x1UL)                   /*!< COMMANDCOMPLETE (Bitfield-Mask: 0x01)                 */
43360 /* =======================================================  INTENABLE  ======================================================= */
43361 #define SDIO_INTENABLE_VENDORSPECIFICERRORSTATUSENABLE_Pos (29UL)   /*!< VENDORSPECIFICERRORSTATUSENABLE (Bit 29)              */
43362 #define SDIO_INTENABLE_VENDORSPECIFICERRORSTATUSENABLE_Msk (0xe0000000UL) /*!< VENDORSPECIFICERRORSTATUSENABLE (Bitfield-Mask: 0x07) */
43363 #define SDIO_INTENABLE_TGTRESPERRHOSTERRSTATEN_Pos (28UL)           /*!< TGTRESPERRHOSTERRSTATEN (Bit 28)                      */
43364 #define SDIO_INTENABLE_TGTRESPERRHOSTERRSTATEN_Msk (0x10000000UL)   /*!< TGTRESPERRHOSTERRSTATEN (Bitfield-Mask: 0x01)         */
43365 #define SDIO_INTENABLE_TUNINGERRORSTATUS_Pos (26UL)                 /*!< TUNINGERRORSTATUS (Bit 26)                            */
43366 #define SDIO_INTENABLE_TUNINGERRORSTATUS_Msk (0x4000000UL)          /*!< TUNINGERRORSTATUS (Bitfield-Mask: 0x01)               */
43367 #define SDIO_INTENABLE_ADMAERRORSTATUSENABLE_Pos (25UL)             /*!< ADMAERRORSTATUSENABLE (Bit 25)                        */
43368 #define SDIO_INTENABLE_ADMAERRORSTATUSENABLE_Msk (0x2000000UL)      /*!< ADMAERRORSTATUSENABLE (Bitfield-Mask: 0x01)           */
43369 #define SDIO_INTENABLE_AUTOCMD12ERRORSTATUSENABLE_Pos (24UL)        /*!< AUTOCMD12ERRORSTATUSENABLE (Bit 24)                   */
43370 #define SDIO_INTENABLE_AUTOCMD12ERRORSTATUSENABLE_Msk (0x1000000UL) /*!< AUTOCMD12ERRORSTATUSENABLE (Bitfield-Mask: 0x01)      */
43371 #define SDIO_INTENABLE_CURRENTLIMITERRORSTATUSENABLE_Pos (23UL)     /*!< CURRENTLIMITERRORSTATUSENABLE (Bit 23)                */
43372 #define SDIO_INTENABLE_CURRENTLIMITERRORSTATUSENABLE_Msk (0x800000UL) /*!< CURRENTLIMITERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
43373 #define SDIO_INTENABLE_DATAENDBITERRORSTATUSENABLE_Pos (22UL)       /*!< DATAENDBITERRORSTATUSENABLE (Bit 22)                  */
43374 #define SDIO_INTENABLE_DATAENDBITERRORSTATUSENABLE_Msk (0x400000UL) /*!< DATAENDBITERRORSTATUSENABLE (Bitfield-Mask: 0x01)     */
43375 #define SDIO_INTENABLE_DATACRCERRORSTATUSENABLE_Pos (21UL)          /*!< DATACRCERRORSTATUSENABLE (Bit 21)                     */
43376 #define SDIO_INTENABLE_DATACRCERRORSTATUSENABLE_Msk (0x200000UL)    /*!< DATACRCERRORSTATUSENABLE (Bitfield-Mask: 0x01)        */
43377 #define SDIO_INTENABLE_DATATIMEOUTERRORSTATUSENABLE_Pos (20UL)      /*!< DATATIMEOUTERRORSTATUSENABLE (Bit 20)                 */
43378 #define SDIO_INTENABLE_DATATIMEOUTERRORSTATUSENABLE_Msk (0x100000UL) /*!< DATATIMEOUTERRORSTATUSENABLE (Bitfield-Mask: 0x01)   */
43379 #define SDIO_INTENABLE_COMMANDINDEXERRORSTATUSENABLE_Pos (19UL)     /*!< COMMANDINDEXERRORSTATUSENABLE (Bit 19)                */
43380 #define SDIO_INTENABLE_COMMANDINDEXERRORSTATUSENABLE_Msk (0x80000UL) /*!< COMMANDINDEXERRORSTATUSENABLE (Bitfield-Mask: 0x01)  */
43381 #define SDIO_INTENABLE_COMMANDENDBITERRORSTATUSENABLE_Pos (18UL)    /*!< COMMANDENDBITERRORSTATUSENABLE (Bit 18)               */
43382 #define SDIO_INTENABLE_COMMANDENDBITERRORSTATUSENABLE_Msk (0x40000UL) /*!< COMMANDENDBITERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
43383 #define SDIO_INTENABLE_COMMANDCRCERRORSTATUSENABLE_Pos (17UL)       /*!< COMMANDCRCERRORSTATUSENABLE (Bit 17)                  */
43384 #define SDIO_INTENABLE_COMMANDCRCERRORSTATUSENABLE_Msk (0x20000UL)  /*!< COMMANDCRCERRORSTATUSENABLE (Bitfield-Mask: 0x01)     */
43385 #define SDIO_INTENABLE_COMMANDTIMEOUTERRORSTATUSENABLE_Pos (16UL)   /*!< COMMANDTIMEOUTERRORSTATUSENABLE (Bit 16)              */
43386 #define SDIO_INTENABLE_COMMANDTIMEOUTERRORSTATUSENABLE_Msk (0x10000UL) /*!< COMMANDTIMEOUTERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
43387 #define SDIO_INTENABLE_FIXEDTO0_Pos       (15UL)                    /*!< FIXEDTO0 (Bit 15)                                     */
43388 #define SDIO_INTENABLE_FIXEDTO0_Msk       (0x8000UL)                /*!< FIXEDTO0 (Bitfield-Mask: 0x01)                        */
43389 #define SDIO_INTENABLE_BOOTTERMINATE_Pos  (14UL)                    /*!< BOOTTERMINATE (Bit 14)                                */
43390 #define SDIO_INTENABLE_BOOTTERMINATE_Msk  (0x4000UL)                /*!< BOOTTERMINATE (Bitfield-Mask: 0x01)                   */
43391 #define SDIO_INTENABLE_BOOTACKRCVENABLE_Pos (13UL)                  /*!< BOOTACKRCVENABLE (Bit 13)                             */
43392 #define SDIO_INTENABLE_BOOTACKRCVENABLE_Msk (0x2000UL)              /*!< BOOTACKRCVENABLE (Bitfield-Mask: 0x01)                */
43393 #define SDIO_INTENABLE_RETUNINGEVENTSTATUSENABLE_Pos (12UL)         /*!< RETUNINGEVENTSTATUSENABLE (Bit 12)                    */
43394 #define SDIO_INTENABLE_RETUNINGEVENTSTATUSENABLE_Msk (0x1000UL)     /*!< RETUNINGEVENTSTATUSENABLE (Bitfield-Mask: 0x01)       */
43395 #define SDIO_INTENABLE_INTCSTATUSENABLE_Pos (11UL)                  /*!< INTCSTATUSENABLE (Bit 11)                             */
43396 #define SDIO_INTENABLE_INTCSTATUSENABLE_Msk (0x800UL)               /*!< INTCSTATUSENABLE (Bitfield-Mask: 0x01)                */
43397 #define SDIO_INTENABLE_INTBSTATUSENABLE_Pos (10UL)                  /*!< INTBSTATUSENABLE (Bit 10)                             */
43398 #define SDIO_INTENABLE_INTBSTATUSENABLE_Msk (0x400UL)               /*!< INTBSTATUSENABLE (Bitfield-Mask: 0x01)                */
43399 #define SDIO_INTENABLE_INTASTATUSENABLE_Pos (9UL)                   /*!< INTASTATUSENABLE (Bit 9)                              */
43400 #define SDIO_INTENABLE_INTASTATUSENABLE_Msk (0x200UL)               /*!< INTASTATUSENABLE (Bitfield-Mask: 0x01)                */
43401 #define SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Pos (8UL)          /*!< CARDINTERRUPTSTATUSENABLE (Bit 8)                     */
43402 #define SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Msk (0x100UL)      /*!< CARDINTERRUPTSTATUSENABLE (Bitfield-Mask: 0x01)       */
43403 #define SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Pos (7UL)            /*!< CARDREMOVALSTATUSENABLE (Bit 7)                       */
43404 #define SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Msk (0x80UL)         /*!< CARDREMOVALSTATUSENABLE (Bitfield-Mask: 0x01)         */
43405 #define SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Pos (6UL)          /*!< CARDINSERTIONSTATUSENABLE (Bit 6)                     */
43406 #define SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Msk (0x40UL)       /*!< CARDINSERTIONSTATUSENABLE (Bitfield-Mask: 0x01)       */
43407 #define SDIO_INTENABLE_BUFFERREADREADYSTATUSENABLE_Pos (5UL)        /*!< BUFFERREADREADYSTATUSENABLE (Bit 5)                   */
43408 #define SDIO_INTENABLE_BUFFERREADREADYSTATUSENABLE_Msk (0x20UL)     /*!< BUFFERREADREADYSTATUSENABLE (Bitfield-Mask: 0x01)     */
43409 #define SDIO_INTENABLE_BUFFERWRITEREADYSTATUSENABLE_Pos (4UL)       /*!< BUFFERWRITEREADYSTATUSENABLE (Bit 4)                  */
43410 #define SDIO_INTENABLE_BUFFERWRITEREADYSTATUSENABLE_Msk (0x10UL)    /*!< BUFFERWRITEREADYSTATUSENABLE (Bitfield-Mask: 0x01)    */
43411 #define SDIO_INTENABLE_DMAINTERRUPTSTATUSENABLE_Pos (3UL)           /*!< DMAINTERRUPTSTATUSENABLE (Bit 3)                      */
43412 #define SDIO_INTENABLE_DMAINTERRUPTSTATUSENABLE_Msk (0x8UL)         /*!< DMAINTERRUPTSTATUSENABLE (Bitfield-Mask: 0x01)        */
43413 #define SDIO_INTENABLE_BLOCKGAPEVENTSTATUSENABLE_Pos (2UL)          /*!< BLOCKGAPEVENTSTATUSENABLE (Bit 2)                     */
43414 #define SDIO_INTENABLE_BLOCKGAPEVENTSTATUSENABLE_Msk (0x4UL)        /*!< BLOCKGAPEVENTSTATUSENABLE (Bitfield-Mask: 0x01)       */
43415 #define SDIO_INTENABLE_TRANSFERCOMPLETESTATUSENABLE_Pos (1UL)       /*!< TRANSFERCOMPLETESTATUSENABLE (Bit 1)                  */
43416 #define SDIO_INTENABLE_TRANSFERCOMPLETESTATUSENABLE_Msk (0x2UL)     /*!< TRANSFERCOMPLETESTATUSENABLE (Bitfield-Mask: 0x01)    */
43417 #define SDIO_INTENABLE_COMMANDCOMPLETESTATUSENABLE_Pos (0UL)        /*!< COMMANDCOMPLETESTATUSENABLE (Bit 0)                   */
43418 #define SDIO_INTENABLE_COMMANDCOMPLETESTATUSENABLE_Msk (0x1UL)      /*!< COMMANDCOMPLETESTATUSENABLE (Bitfield-Mask: 0x01)     */
43419 /* ========================================================  INTSIG  ========================================================= */
43420 #define SDIO_INTSIG_VNDERREN_Pos          (29UL)                    /*!< VNDERREN (Bit 29)                                     */
43421 #define SDIO_INTSIG_VNDERREN_Msk          (0xe0000000UL)            /*!< VNDERREN (Bitfield-Mask: 0x07)                        */
43422 #define SDIO_INTSIG_TGTRESPEN_Pos         (28UL)                    /*!< TGTRESPEN (Bit 28)                                    */
43423 #define SDIO_INTSIG_TGTRESPEN_Msk         (0x10000000UL)            /*!< TGTRESPEN (Bitfield-Mask: 0x01)                       */
43424 #define SDIO_INTSIG_TUNINGERREN_Pos       (26UL)                    /*!< TUNINGERREN (Bit 26)                                  */
43425 #define SDIO_INTSIG_TUNINGERREN_Msk       (0x4000000UL)             /*!< TUNINGERREN (Bitfield-Mask: 0x01)                     */
43426 #define SDIO_INTSIG_ADMAERREN_Pos         (25UL)                    /*!< ADMAERREN (Bit 25)                                    */
43427 #define SDIO_INTSIG_ADMAERREN_Msk         (0x2000000UL)             /*!< ADMAERREN (Bitfield-Mask: 0x01)                       */
43428 #define SDIO_INTSIG_AUTOCMD12ERREN_Pos    (24UL)                    /*!< AUTOCMD12ERREN (Bit 24)                               */
43429 #define SDIO_INTSIG_AUTOCMD12ERREN_Msk    (0x1000000UL)             /*!< AUTOCMD12ERREN (Bitfield-Mask: 0x01)                  */
43430 #define SDIO_INTSIG_CURRLMTERREN_Pos      (23UL)                    /*!< CURRLMTERREN (Bit 23)                                 */
43431 #define SDIO_INTSIG_CURRLMTERREN_Msk      (0x800000UL)              /*!< CURRLMTERREN (Bitfield-Mask: 0x01)                    */
43432 #define SDIO_INTSIG_DATAENDERREN_Pos      (22UL)                    /*!< DATAENDERREN (Bit 22)                                 */
43433 #define SDIO_INTSIG_DATAENDERREN_Msk      (0x400000UL)              /*!< DATAENDERREN (Bitfield-Mask: 0x01)                    */
43434 #define SDIO_INTSIG_DATACRCERREN_Pos      (21UL)                    /*!< DATACRCERREN (Bit 21)                                 */
43435 #define SDIO_INTSIG_DATACRCERREN_Msk      (0x200000UL)              /*!< DATACRCERREN (Bitfield-Mask: 0x01)                    */
43436 #define SDIO_INTSIG_DATATOERROREN_Pos     (20UL)                    /*!< DATATOERROREN (Bit 20)                                */
43437 #define SDIO_INTSIG_DATATOERROREN_Msk     (0x100000UL)              /*!< DATATOERROREN (Bitfield-Mask: 0x01)                   */
43438 #define SDIO_INTSIG_CMDIDXERREN_Pos       (19UL)                    /*!< CMDIDXERREN (Bit 19)                                  */
43439 #define SDIO_INTSIG_CMDIDXERREN_Msk       (0x80000UL)               /*!< CMDIDXERREN (Bitfield-Mask: 0x01)                     */
43440 #define SDIO_INTSIG_CMDENDBITERREN_Pos    (18UL)                    /*!< CMDENDBITERREN (Bit 18)                               */
43441 #define SDIO_INTSIG_CMDENDBITERREN_Msk    (0x40000UL)               /*!< CMDENDBITERREN (Bitfield-Mask: 0x01)                  */
43442 #define SDIO_INTSIG_CMDCRCERREN_Pos       (17UL)                    /*!< CMDCRCERREN (Bit 17)                                  */
43443 #define SDIO_INTSIG_CMDCRCERREN_Msk       (0x20000UL)               /*!< CMDCRCERREN (Bitfield-Mask: 0x01)                     */
43444 #define SDIO_INTSIG_CMDTOERREN_Pos        (16UL)                    /*!< CMDTOERREN (Bit 16)                                   */
43445 #define SDIO_INTSIG_CMDTOERREN_Msk        (0x10000UL)               /*!< CMDTOERREN (Bitfield-Mask: 0x01)                      */
43446 #define SDIO_INTSIG_FIXED0_Pos            (15UL)                    /*!< FIXED0 (Bit 15)                                       */
43447 #define SDIO_INTSIG_FIXED0_Msk            (0x8000UL)                /*!< FIXED0 (Bitfield-Mask: 0x01)                          */
43448 #define SDIO_INTSIG_BOOTTERM_Pos          (14UL)                    /*!< BOOTTERM (Bit 14)                                     */
43449 #define SDIO_INTSIG_BOOTTERM_Msk          (0x4000UL)                /*!< BOOTTERM (Bitfield-Mask: 0x01)                        */
43450 #define SDIO_INTSIG_BOOTACKEN_Pos         (13UL)                    /*!< BOOTACKEN (Bit 13)                                    */
43451 #define SDIO_INTSIG_BOOTACKEN_Msk         (0x2000UL)                /*!< BOOTACKEN (Bitfield-Mask: 0x01)                       */
43452 #define SDIO_INTSIG_RETUNEEVENTEN_Pos     (12UL)                    /*!< RETUNEEVENTEN (Bit 12)                                */
43453 #define SDIO_INTSIG_RETUNEEVENTEN_Msk     (0x1000UL)                /*!< RETUNEEVENTEN (Bitfield-Mask: 0x01)                   */
43454 #define SDIO_INTSIG_INTCEN_Pos            (11UL)                    /*!< INTCEN (Bit 11)                                       */
43455 #define SDIO_INTSIG_INTCEN_Msk            (0x800UL)                 /*!< INTCEN (Bitfield-Mask: 0x01)                          */
43456 #define SDIO_INTSIG_INTBEN_Pos            (10UL)                    /*!< INTBEN (Bit 10)                                       */
43457 #define SDIO_INTSIG_INTBEN_Msk            (0x400UL)                 /*!< INTBEN (Bitfield-Mask: 0x01)                          */
43458 #define SDIO_INTSIG_INTAEN_Pos            (9UL)                     /*!< INTAEN (Bit 9)                                        */
43459 #define SDIO_INTSIG_INTAEN_Msk            (0x200UL)                 /*!< INTAEN (Bitfield-Mask: 0x01)                          */
43460 #define SDIO_INTSIG_CARDINTEN_Pos         (8UL)                     /*!< CARDINTEN (Bit 8)                                     */
43461 #define SDIO_INTSIG_CARDINTEN_Msk         (0x100UL)                 /*!< CARDINTEN (Bitfield-Mask: 0x01)                       */
43462 #define SDIO_INTSIG_CARDREMOVALEN_Pos     (7UL)                     /*!< CARDREMOVALEN (Bit 7)                                 */
43463 #define SDIO_INTSIG_CARDREMOVALEN_Msk     (0x80UL)                  /*!< CARDREMOVALEN (Bitfield-Mask: 0x01)                   */
43464 #define SDIO_INTSIG_CARDINSERTEN_Pos      (6UL)                     /*!< CARDINSERTEN (Bit 6)                                  */
43465 #define SDIO_INTSIG_CARDINSERTEN_Msk      (0x40UL)                  /*!< CARDINSERTEN (Bitfield-Mask: 0x01)                    */
43466 #define SDIO_INTSIG_BUFFERRDEN_Pos        (5UL)                     /*!< BUFFERRDEN (Bit 5)                                    */
43467 #define SDIO_INTSIG_BUFFERRDEN_Msk        (0x20UL)                  /*!< BUFFERRDEN (Bitfield-Mask: 0x01)                      */
43468 #define SDIO_INTSIG_BUFFERWREN_Pos        (4UL)                     /*!< BUFFERWREN (Bit 4)                                    */
43469 #define SDIO_INTSIG_BUFFERWREN_Msk        (0x10UL)                  /*!< BUFFERWREN (Bitfield-Mask: 0x01)                      */
43470 #define SDIO_INTSIG_DMAINTEN_Pos          (3UL)                     /*!< DMAINTEN (Bit 3)                                      */
43471 #define SDIO_INTSIG_DMAINTEN_Msk          (0x8UL)                   /*!< DMAINTEN (Bitfield-Mask: 0x01)                        */
43472 #define SDIO_INTSIG_BLOCKGAPEN_Pos        (2UL)                     /*!< BLOCKGAPEN (Bit 2)                                    */
43473 #define SDIO_INTSIG_BLOCKGAPEN_Msk        (0x4UL)                   /*!< BLOCKGAPEN (Bitfield-Mask: 0x01)                      */
43474 #define SDIO_INTSIG_XFERCMPEN_Pos         (1UL)                     /*!< XFERCMPEN (Bit 1)                                     */
43475 #define SDIO_INTSIG_XFERCMPEN_Msk         (0x2UL)                   /*!< XFERCMPEN (Bitfield-Mask: 0x01)                       */
43476 #define SDIO_INTSIG_CMDCMPEN_Pos          (0UL)                     /*!< CMDCMPEN (Bit 0)                                      */
43477 #define SDIO_INTSIG_CMDCMPEN_Msk          (0x1UL)                   /*!< CMDCMPEN (Bitfield-Mask: 0x01)                        */
43478 /* =========================================================  AUTO  ========================================================== */
43479 #define SDIO_AUTO_PRESETEN_Pos            (31UL)                    /*!< PRESETEN (Bit 31)                                     */
43480 #define SDIO_AUTO_PRESETEN_Msk            (0x80000000UL)            /*!< PRESETEN (Bitfield-Mask: 0x01)                        */
43481 #define SDIO_AUTO_ASYNCINTEN_Pos          (30UL)                    /*!< ASYNCINTEN (Bit 30)                                   */
43482 #define SDIO_AUTO_ASYNCINTEN_Msk          (0x40000000UL)            /*!< ASYNCINTEN (Bitfield-Mask: 0x01)                      */
43483 #define SDIO_AUTO_SAMPLCLKSEL_Pos         (23UL)                    /*!< SAMPLCLKSEL (Bit 23)                                  */
43484 #define SDIO_AUTO_SAMPLCLKSEL_Msk         (0x800000UL)              /*!< SAMPLCLKSEL (Bitfield-Mask: 0x01)                     */
43485 #define SDIO_AUTO_STARTTUNING_Pos         (22UL)                    /*!< STARTTUNING (Bit 22)                                  */
43486 #define SDIO_AUTO_STARTTUNING_Msk         (0x400000UL)              /*!< STARTTUNING (Bitfield-Mask: 0x01)                     */
43487 #define SDIO_AUTO_DRVRSTRSEL_Pos          (20UL)                    /*!< DRVRSTRSEL (Bit 20)                                   */
43488 #define SDIO_AUTO_DRVRSTRSEL_Msk          (0x300000UL)              /*!< DRVRSTRSEL (Bitfield-Mask: 0x03)                      */
43489 #define SDIO_AUTO_SIGNALVOLT_Pos          (19UL)                    /*!< SIGNALVOLT (Bit 19)                                   */
43490 #define SDIO_AUTO_SIGNALVOLT_Msk          (0x80000UL)               /*!< SIGNALVOLT (Bitfield-Mask: 0x01)                      */
43491 #define SDIO_AUTO_UHSMODESEL_Pos          (16UL)                    /*!< UHSMODESEL (Bit 16)                                   */
43492 #define SDIO_AUTO_UHSMODESEL_Msk          (0x70000UL)               /*!< UHSMODESEL (Bitfield-Mask: 0x07)                      */
43493 #define SDIO_AUTO_NOTAUTOCMD12ERR_Pos     (7UL)                     /*!< NOTAUTOCMD12ERR (Bit 7)                               */
43494 #define SDIO_AUTO_NOTAUTOCMD12ERR_Msk     (0x80UL)                  /*!< NOTAUTOCMD12ERR (Bitfield-Mask: 0x01)                 */
43495 #define SDIO_AUTO_CMDIDXERR_Pos           (4UL)                     /*!< CMDIDXERR (Bit 4)                                     */
43496 #define SDIO_AUTO_CMDIDXERR_Msk           (0x10UL)                  /*!< CMDIDXERR (Bitfield-Mask: 0x01)                       */
43497 #define SDIO_AUTO_CMDENDERR_Pos           (3UL)                     /*!< CMDENDERR (Bit 3)                                     */
43498 #define SDIO_AUTO_CMDENDERR_Msk           (0x8UL)                   /*!< CMDENDERR (Bitfield-Mask: 0x01)                       */
43499 #define SDIO_AUTO_CMDCRCERR_Pos           (2UL)                     /*!< CMDCRCERR (Bit 2)                                     */
43500 #define SDIO_AUTO_CMDCRCERR_Msk           (0x4UL)                   /*!< CMDCRCERR (Bitfield-Mask: 0x01)                       */
43501 #define SDIO_AUTO_CMDTOERR_Pos            (1UL)                     /*!< CMDTOERR (Bit 1)                                      */
43502 #define SDIO_AUTO_CMDTOERR_Msk            (0x2UL)                   /*!< CMDTOERR (Bitfield-Mask: 0x01)                        */
43503 #define SDIO_AUTO_CMD12NOTEXEC_Pos        (0UL)                     /*!< CMD12NOTEXEC (Bit 0)                                  */
43504 #define SDIO_AUTO_CMD12NOTEXEC_Msk        (0x1UL)                   /*!< CMD12NOTEXEC (Bitfield-Mask: 0x01)                    */
43505 /* =====================================================  CAPABILITIES0  ===================================================== */
43506 #define SDIO_CAPABILITIES0_SLOTTYPE_Pos   (30UL)                    /*!< SLOTTYPE (Bit 30)                                     */
43507 #define SDIO_CAPABILITIES0_SLOTTYPE_Msk   (0xc0000000UL)            /*!< SLOTTYPE (Bitfield-Mask: 0x03)                        */
43508 #define SDIO_CAPABILITIES0_ASYNCINT_Pos   (29UL)                    /*!< ASYNCINT (Bit 29)                                     */
43509 #define SDIO_CAPABILITIES0_ASYNCINT_Msk   (0x20000000UL)            /*!< ASYNCINT (Bitfield-Mask: 0x01)                        */
43510 #define SDIO_CAPABILITIES0_SYSBUS64_Pos   (28UL)                    /*!< SYSBUS64 (Bit 28)                                     */
43511 #define SDIO_CAPABILITIES0_SYSBUS64_Msk   (0x10000000UL)            /*!< SYSBUS64 (Bitfield-Mask: 0x01)                        */
43512 #define SDIO_CAPABILITIES0_VOLT18V_Pos    (26UL)                    /*!< VOLT18V (Bit 26)                                      */
43513 #define SDIO_CAPABILITIES0_VOLT18V_Msk    (0x4000000UL)             /*!< VOLT18V (Bitfield-Mask: 0x01)                         */
43514 #define SDIO_CAPABILITIES0_VOLT30V_Pos    (25UL)                    /*!< VOLT30V (Bit 25)                                      */
43515 #define SDIO_CAPABILITIES0_VOLT30V_Msk    (0x2000000UL)             /*!< VOLT30V (Bitfield-Mask: 0x01)                         */
43516 #define SDIO_CAPABILITIES0_VOLT33V_Pos    (24UL)                    /*!< VOLT33V (Bit 24)                                      */
43517 #define SDIO_CAPABILITIES0_VOLT33V_Msk    (0x1000000UL)             /*!< VOLT33V (Bitfield-Mask: 0x01)                         */
43518 #define SDIO_CAPABILITIES0_SUSPRES_Pos    (23UL)                    /*!< SUSPRES (Bit 23)                                      */
43519 #define SDIO_CAPABILITIES0_SUSPRES_Msk    (0x800000UL)              /*!< SUSPRES (Bitfield-Mask: 0x01)                         */
43520 #define SDIO_CAPABILITIES0_SDMA_Pos       (22UL)                    /*!< SDMA (Bit 22)                                         */
43521 #define SDIO_CAPABILITIES0_SDMA_Msk       (0x400000UL)              /*!< SDMA (Bitfield-Mask: 0x01)                            */
43522 #define SDIO_CAPABILITIES0_HIGHSPEED_Pos  (21UL)                    /*!< HIGHSPEED (Bit 21)                                    */
43523 #define SDIO_CAPABILITIES0_HIGHSPEED_Msk  (0x200000UL)              /*!< HIGHSPEED (Bitfield-Mask: 0x01)                       */
43524 #define SDIO_CAPABILITIES0_ADMA2_Pos      (19UL)                    /*!< ADMA2 (Bit 19)                                        */
43525 #define SDIO_CAPABILITIES0_ADMA2_Msk      (0x80000UL)               /*!< ADMA2 (Bitfield-Mask: 0x01)                           */
43526 #define SDIO_CAPABILITIES0_EXTMEDIA_Pos   (18UL)                    /*!< EXTMEDIA (Bit 18)                                     */
43527 #define SDIO_CAPABILITIES0_EXTMEDIA_Msk   (0x40000UL)               /*!< EXTMEDIA (Bitfield-Mask: 0x01)                        */
43528 #define SDIO_CAPABILITIES0_MAXBLKLEN_Pos  (16UL)                    /*!< MAXBLKLEN (Bit 16)                                    */
43529 #define SDIO_CAPABILITIES0_MAXBLKLEN_Msk  (0x30000UL)               /*!< MAXBLKLEN (Bitfield-Mask: 0x03)                       */
43530 #define SDIO_CAPABILITIES0_SDCLKFREQ_Pos  (8UL)                     /*!< SDCLKFREQ (Bit 8)                                     */
43531 #define SDIO_CAPABILITIES0_SDCLKFREQ_Msk  (0xff00UL)                /*!< SDCLKFREQ (Bitfield-Mask: 0xff)                       */
43532 #define SDIO_CAPABILITIES0_TOCLKUNIT_Pos  (7UL)                     /*!< TOCLKUNIT (Bit 7)                                     */
43533 #define SDIO_CAPABILITIES0_TOCLKUNIT_Msk  (0x80UL)                  /*!< TOCLKUNIT (Bitfield-Mask: 0x01)                       */
43534 #define SDIO_CAPABILITIES0_TOCLKFREQ_Pos  (0UL)                     /*!< TOCLKFREQ (Bit 0)                                     */
43535 #define SDIO_CAPABILITIES0_TOCLKFREQ_Msk  (0x3fUL)                  /*!< TOCLKFREQ (Bitfield-Mask: 0x3f)                       */
43536 /* =====================================================  CAPABILITIES1  ===================================================== */
43537 #define SDIO_CAPABILITIES1_SPIBLOCKMODE_Pos (25UL)                  /*!< SPIBLOCKMODE (Bit 25)                                 */
43538 #define SDIO_CAPABILITIES1_SPIBLOCKMODE_Msk (0x2000000UL)           /*!< SPIBLOCKMODE (Bitfield-Mask: 0x01)                    */
43539 #define SDIO_CAPABILITIES1_SPIMODE_Pos    (24UL)                    /*!< SPIMODE (Bit 24)                                      */
43540 #define SDIO_CAPABILITIES1_SPIMODE_Msk    (0x1000000UL)             /*!< SPIMODE (Bitfield-Mask: 0x01)                         */
43541 #define SDIO_CAPABILITIES1_CLKMULT_Pos    (16UL)                    /*!< CLKMULT (Bit 16)                                      */
43542 #define SDIO_CAPABILITIES1_CLKMULT_Msk    (0xff0000UL)              /*!< CLKMULT (Bitfield-Mask: 0xff)                         */
43543 #define SDIO_CAPABILITIES1_RETUNINGMODES_Pos (14UL)                 /*!< RETUNINGMODES (Bit 14)                                */
43544 #define SDIO_CAPABILITIES1_RETUNINGMODES_Msk (0xc000UL)             /*!< RETUNINGMODES (Bitfield-Mask: 0x03)                   */
43545 #define SDIO_CAPABILITIES1_TUNINGSDR50_Pos (13UL)                   /*!< TUNINGSDR50 (Bit 13)                                  */
43546 #define SDIO_CAPABILITIES1_TUNINGSDR50_Msk (0x2000UL)               /*!< TUNINGSDR50 (Bitfield-Mask: 0x01)                     */
43547 #define SDIO_CAPABILITIES1_RETUNINGTMRCNT_Pos (8UL)                 /*!< RETUNINGTMRCNT (Bit 8)                                */
43548 #define SDIO_CAPABILITIES1_RETUNINGTMRCNT_Msk (0xf00UL)             /*!< RETUNINGTMRCNT (Bitfield-Mask: 0x0f)                  */
43549 #define SDIO_CAPABILITIES1_TYPED_Pos      (6UL)                     /*!< TYPED (Bit 6)                                         */
43550 #define SDIO_CAPABILITIES1_TYPED_Msk      (0x40UL)                  /*!< TYPED (Bitfield-Mask: 0x01)                           */
43551 #define SDIO_CAPABILITIES1_TYPEC_Pos      (5UL)                     /*!< TYPEC (Bit 5)                                         */
43552 #define SDIO_CAPABILITIES1_TYPEC_Msk      (0x20UL)                  /*!< TYPEC (Bitfield-Mask: 0x01)                           */
43553 #define SDIO_CAPABILITIES1_TYPEA_Pos      (4UL)                     /*!< TYPEA (Bit 4)                                         */
43554 #define SDIO_CAPABILITIES1_TYPEA_Msk      (0x10UL)                  /*!< TYPEA (Bitfield-Mask: 0x01)                           */
43555 #define SDIO_CAPABILITIES1_DDR50_Pos      (2UL)                     /*!< DDR50 (Bit 2)                                         */
43556 #define SDIO_CAPABILITIES1_DDR50_Msk      (0x4UL)                   /*!< DDR50 (Bitfield-Mask: 0x01)                           */
43557 #define SDIO_CAPABILITIES1_SDR104_Pos     (1UL)                     /*!< SDR104 (Bit 1)                                        */
43558 #define SDIO_CAPABILITIES1_SDR104_Msk     (0x2UL)                   /*!< SDR104 (Bitfield-Mask: 0x01)                          */
43559 #define SDIO_CAPABILITIES1_SDR50_Pos      (0UL)                     /*!< SDR50 (Bit 0)                                         */
43560 #define SDIO_CAPABILITIES1_SDR50_Msk      (0x1UL)                   /*!< SDR50 (Bitfield-Mask: 0x01)                           */
43561 /* =======================================================  MAXIMUM0  ======================================================== */
43562 #define SDIO_MAXIMUM0_ALLBITSRSVD_Pos     (0UL)                     /*!< ALLBITSRSVD (Bit 0)                                   */
43563 #define SDIO_MAXIMUM0_ALLBITSRSVD_Msk     (0xffffffffUL)            /*!< ALLBITSRSVD (Bitfield-Mask: 0xffffffff)               */
43564 /* =======================================================  MAXIMUM1  ======================================================== */
43565 #define SDIO_MAXIMUM1_MAXCURR18V_Pos      (16UL)                    /*!< MAXCURR18V (Bit 16)                                   */
43566 #define SDIO_MAXIMUM1_MAXCURR18V_Msk      (0xff0000UL)              /*!< MAXCURR18V (Bitfield-Mask: 0xff)                      */
43567 #define SDIO_MAXIMUM1_MAXCURR30V_Pos      (8UL)                     /*!< MAXCURR30V (Bit 8)                                    */
43568 #define SDIO_MAXIMUM1_MAXCURR30V_Msk      (0xff00UL)                /*!< MAXCURR30V (Bitfield-Mask: 0xff)                      */
43569 #define SDIO_MAXIMUM1_MAXCURR33V_Pos      (0UL)                     /*!< MAXCURR33V (Bit 0)                                    */
43570 #define SDIO_MAXIMUM1_MAXCURR33V_Msk      (0xffUL)                  /*!< MAXCURR33V (Bitfield-Mask: 0xff)                      */
43571 /* =========================================================  FORCE  ========================================================= */
43572 #define SDIO_FORCE_FORCEADMAERR_Pos       (25UL)                    /*!< FORCEADMAERR (Bit 25)                                 */
43573 #define SDIO_FORCE_FORCEADMAERR_Msk       (0x2000000UL)             /*!< FORCEADMAERR (Bitfield-Mask: 0x01)                    */
43574 #define SDIO_FORCE_FORCEACMDERR_Pos       (24UL)                    /*!< FORCEACMDERR (Bit 24)                                 */
43575 #define SDIO_FORCE_FORCEACMDERR_Msk       (0x1000000UL)             /*!< FORCEACMDERR (Bitfield-Mask: 0x01)                    */
43576 #define SDIO_FORCE_FORCECURRLIMITERR_Pos  (23UL)                    /*!< FORCECURRLIMITERR (Bit 23)                            */
43577 #define SDIO_FORCE_FORCECURRLIMITERR_Msk  (0x800000UL)              /*!< FORCECURRLIMITERR (Bitfield-Mask: 0x01)               */
43578 #define SDIO_FORCE_FORCEDATAENDERR_Pos    (22UL)                    /*!< FORCEDATAENDERR (Bit 22)                              */
43579 #define SDIO_FORCE_FORCEDATAENDERR_Msk    (0x400000UL)              /*!< FORCEDATAENDERR (Bitfield-Mask: 0x01)                 */
43580 #define SDIO_FORCE_FORCEDATACRCERR_Pos    (21UL)                    /*!< FORCEDATACRCERR (Bit 21)                              */
43581 #define SDIO_FORCE_FORCEDATACRCERR_Msk    (0x200000UL)              /*!< FORCEDATACRCERR (Bitfield-Mask: 0x01)                 */
43582 #define SDIO_FORCE_FORCEDATATOERR_Pos     (20UL)                    /*!< FORCEDATATOERR (Bit 20)                               */
43583 #define SDIO_FORCE_FORCEDATATOERR_Msk     (0x100000UL)              /*!< FORCEDATATOERR (Bitfield-Mask: 0x01)                  */
43584 #define SDIO_FORCE_FORCECMDIDXERR_Pos     (19UL)                    /*!< FORCECMDIDXERR (Bit 19)                               */
43585 #define SDIO_FORCE_FORCECMDIDXERR_Msk     (0x80000UL)               /*!< FORCECMDIDXERR (Bitfield-Mask: 0x01)                  */
43586 #define SDIO_FORCE_FORCECMDENDERR_Pos     (18UL)                    /*!< FORCECMDENDERR (Bit 18)                               */
43587 #define SDIO_FORCE_FORCECMDENDERR_Msk     (0x40000UL)               /*!< FORCECMDENDERR (Bitfield-Mask: 0x01)                  */
43588 #define SDIO_FORCE_FORCECMDCRCERR_Pos     (17UL)                    /*!< FORCECMDCRCERR (Bit 17)                               */
43589 #define SDIO_FORCE_FORCECMDCRCERR_Msk     (0x20000UL)               /*!< FORCECMDCRCERR (Bitfield-Mask: 0x01)                  */
43590 #define SDIO_FORCE_FORCECMDTOERR_Pos      (16UL)                    /*!< FORCECMDTOERR (Bit 16)                                */
43591 #define SDIO_FORCE_FORCECMDTOERR_Msk      (0x10000UL)               /*!< FORCECMDTOERR (Bitfield-Mask: 0x01)                   */
43592 #define SDIO_FORCE_FORCEACMDISSUEDERR_Pos (7UL)                     /*!< FORCEACMDISSUEDERR (Bit 7)                            */
43593 #define SDIO_FORCE_FORCEACMDISSUEDERR_Msk (0x80UL)                  /*!< FORCEACMDISSUEDERR (Bitfield-Mask: 0x01)              */
43594 #define SDIO_FORCE_FORCEACMDIDXERR_Pos    (4UL)                     /*!< FORCEACMDIDXERR (Bit 4)                               */
43595 #define SDIO_FORCE_FORCEACMDIDXERR_Msk    (0x10UL)                  /*!< FORCEACMDIDXERR (Bitfield-Mask: 0x01)                 */
43596 #define SDIO_FORCE_FORCEACMDENDERR_Pos    (3UL)                     /*!< FORCEACMDENDERR (Bit 3)                               */
43597 #define SDIO_FORCE_FORCEACMDENDERR_Msk    (0x8UL)                   /*!< FORCEACMDENDERR (Bitfield-Mask: 0x01)                 */
43598 #define SDIO_FORCE_FORCEACMDCRCERR_Pos    (2UL)                     /*!< FORCEACMDCRCERR (Bit 2)                               */
43599 #define SDIO_FORCE_FORCEACMDCRCERR_Msk    (0x4UL)                   /*!< FORCEACMDCRCERR (Bitfield-Mask: 0x01)                 */
43600 #define SDIO_FORCE_FORCEACMDTOERR_Pos     (1UL)                     /*!< FORCEACMDTOERR (Bit 1)                                */
43601 #define SDIO_FORCE_FORCEACMDTOERR_Msk     (0x2UL)                   /*!< FORCEACMDTOERR (Bitfield-Mask: 0x01)                  */
43602 #define SDIO_FORCE_FORCEACMD12NOT_Pos     (0UL)                     /*!< FORCEACMD12NOT (Bit 0)                                */
43603 #define SDIO_FORCE_FORCEACMD12NOT_Msk     (0x1UL)                   /*!< FORCEACMD12NOT (Bitfield-Mask: 0x01)                  */
43604 /* =========================================================  ADMA  ========================================================== */
43605 #define SDIO_ADMA_ADMALENMISMATCHERR_Pos  (2UL)                     /*!< ADMALENMISMATCHERR (Bit 2)                            */
43606 #define SDIO_ADMA_ADMALENMISMATCHERR_Msk  (0x4UL)                   /*!< ADMALENMISMATCHERR (Bitfield-Mask: 0x01)              */
43607 #define SDIO_ADMA_ADMAERRORSTATE_Pos      (0UL)                     /*!< ADMAERRORSTATE (Bit 0)                                */
43608 #define SDIO_ADMA_ADMAERRORSTATE_Msk      (0x3UL)                   /*!< ADMAERRORSTATE (Bitfield-Mask: 0x03)                  */
43609 /* =======================================================  ADMALOWD  ======================================================== */
43610 #define SDIO_ADMALOWD_LOWD_Pos            (0UL)                     /*!< LOWD (Bit 0)                                          */
43611 #define SDIO_ADMALOWD_LOWD_Msk            (0xffffffffUL)            /*!< LOWD (Bitfield-Mask: 0xffffffff)                      */
43612 /* =======================================================  ADMAHIWD  ======================================================== */
43613 #define SDIO_ADMAHIWD_HIWD_Pos            (0UL)                     /*!< HIWD (Bit 0)                                          */
43614 #define SDIO_ADMAHIWD_HIWD_Msk            (0xffffffffUL)            /*!< HIWD (Bitfield-Mask: 0xffffffff)                      */
43615 /* ========================================================  PRESET0  ======================================================== */
43616 #define SDIO_PRESET0_DEFSPDRVRSTRSEL_Pos  (30UL)                    /*!< DEFSPDRVRSTRSEL (Bit 30)                              */
43617 #define SDIO_PRESET0_DEFSPDRVRSTRSEL_Msk  (0xc0000000UL)            /*!< DEFSPDRVRSTRSEL (Bitfield-Mask: 0x03)                 */
43618 #define SDIO_PRESET0_DEFSPCLKGENSEL_Pos   (26UL)                    /*!< DEFSPCLKGENSEL (Bit 26)                               */
43619 #define SDIO_PRESET0_DEFSPCLKGENSEL_Msk   (0x4000000UL)             /*!< DEFSPCLKGENSEL (Bitfield-Mask: 0x01)                  */
43620 #define SDIO_PRESET0_DEFSPSDCLKFREQSEL_Pos (16UL)                   /*!< DEFSPSDCLKFREQSEL (Bit 16)                            */
43621 #define SDIO_PRESET0_DEFSPSDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< DEFSPSDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
43622 #define SDIO_PRESET0_HISPDRVRSTRSEL_Pos   (14UL)                    /*!< HISPDRVRSTRSEL (Bit 14)                               */
43623 #define SDIO_PRESET0_HISPDRVRSTRSEL_Msk   (0xc000UL)                /*!< HISPDRVRSTRSEL (Bitfield-Mask: 0x03)                  */
43624 #define SDIO_PRESET0_HISPCLKGENSEL_Pos    (10UL)                    /*!< HISPCLKGENSEL (Bit 10)                                */
43625 #define SDIO_PRESET0_HISPCLKGENSEL_Msk    (0x400UL)                 /*!< HISPCLKGENSEL (Bitfield-Mask: 0x01)                   */
43626 #define SDIO_PRESET0_HISPSDCLKFREQSEL_Pos (0UL)                     /*!< HISPSDCLKFREQSEL (Bit 0)                              */
43627 #define SDIO_PRESET0_HISPSDCLKFREQSEL_Msk (0x3ffUL)                 /*!< HISPSDCLKFREQSEL (Bitfield-Mask: 0x3ff)               */
43628 /* ========================================================  PRESET1  ======================================================== */
43629 #define SDIO_PRESET1_SDR12DRVRSTRSEL_Pos  (30UL)                    /*!< SDR12DRVRSTRSEL (Bit 30)                              */
43630 #define SDIO_PRESET1_SDR12DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< SDR12DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
43631 #define SDIO_PRESET1_SDR12CLKGENSEL_Pos   (26UL)                    /*!< SDR12CLKGENSEL (Bit 26)                               */
43632 #define SDIO_PRESET1_SDR12CLKGENSEL_Msk   (0x4000000UL)             /*!< SDR12CLKGENSEL (Bitfield-Mask: 0x01)                  */
43633 #define SDIO_PRESET1_SDR12SDCLKFREQSEL_Pos (16UL)                   /*!< SDR12SDCLKFREQSEL (Bit 16)                            */
43634 #define SDIO_PRESET1_SDR12SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< SDR12SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
43635 #define SDIO_PRESET1_HSDRVRSTRSEL_Pos     (14UL)                    /*!< HSDRVRSTRSEL (Bit 14)                                 */
43636 #define SDIO_PRESET1_HSDRVRSTRSEL_Msk     (0xc000UL)                /*!< HSDRVRSTRSEL (Bitfield-Mask: 0x03)                    */
43637 #define SDIO_PRESET1_HSCLKGENSEL_Pos      (10UL)                    /*!< HSCLKGENSEL (Bit 10)                                  */
43638 #define SDIO_PRESET1_HSCLKGENSEL_Msk      (0x400UL)                 /*!< HSCLKGENSEL (Bitfield-Mask: 0x01)                     */
43639 #define SDIO_PRESET1_HSSDCLKFREQSEL_Pos   (0UL)                     /*!< HSSDCLKFREQSEL (Bit 0)                                */
43640 #define SDIO_PRESET1_HSSDCLKFREQSEL_Msk   (0x3ffUL)                 /*!< HSSDCLKFREQSEL (Bitfield-Mask: 0x3ff)                 */
43641 /* ========================================================  PRESET2  ======================================================== */
43642 #define SDIO_PRESET2_SDR50DRVRSTRSEL_Pos  (30UL)                    /*!< SDR50DRVRSTRSEL (Bit 30)                              */
43643 #define SDIO_PRESET2_SDR50DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< SDR50DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
43644 #define SDIO_PRESET2_SDR50CLKGENSEL_Pos   (26UL)                    /*!< SDR50CLKGENSEL (Bit 26)                               */
43645 #define SDIO_PRESET2_SDR50CLKGENSEL_Msk   (0x4000000UL)             /*!< SDR50CLKGENSEL (Bitfield-Mask: 0x01)                  */
43646 #define SDIO_PRESET2_SDR50SDCLKFREQSEL_Pos (16UL)                   /*!< SDR50SDCLKFREQSEL (Bit 16)                            */
43647 #define SDIO_PRESET2_SDR50SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< SDR50SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
43648 #define SDIO_PRESET2_SDR25DRVRSTRSEL_Pos  (14UL)                    /*!< SDR25DRVRSTRSEL (Bit 14)                              */
43649 #define SDIO_PRESET2_SDR25DRVRSTRSEL_Msk  (0xc000UL)                /*!< SDR25DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
43650 #define SDIO_PRESET2_SDR25CLKGENSEL_Pos   (10UL)                    /*!< SDR25CLKGENSEL (Bit 10)                               */
43651 #define SDIO_PRESET2_SDR25CLKGENSEL_Msk   (0x400UL)                 /*!< SDR25CLKGENSEL (Bitfield-Mask: 0x01)                  */
43652 #define SDIO_PRESET2_SDR25SDCLKFREQSEL_Pos (0UL)                    /*!< SDR25SDCLKFREQSEL (Bit 0)                             */
43653 #define SDIO_PRESET2_SDR25SDCLKFREQSEL_Msk (0x3ffUL)                /*!< SDR25SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
43654 /* ========================================================  PRESET3  ======================================================== */
43655 #define SDIO_PRESET3_DDR50DRVRSTRSEL_Pos  (30UL)                    /*!< DDR50DRVRSTRSEL (Bit 30)                              */
43656 #define SDIO_PRESET3_DDR50DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< DDR50DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
43657 #define SDIO_PRESET3_DDR50CLKGENSEL_Pos   (26UL)                    /*!< DDR50CLKGENSEL (Bit 26)                               */
43658 #define SDIO_PRESET3_DDR50CLKGENSEL_Msk   (0x4000000UL)             /*!< DDR50CLKGENSEL (Bitfield-Mask: 0x01)                  */
43659 #define SDIO_PRESET3_DDR50SDCLKFREQSEL_Pos (16UL)                   /*!< DDR50SDCLKFREQSEL (Bit 16)                            */
43660 #define SDIO_PRESET3_DDR50SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< DDR50SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
43661 #define SDIO_PRESET3_SDR104DRVRSTRSEL_Pos (14UL)                    /*!< SDR104DRVRSTRSEL (Bit 14)                             */
43662 #define SDIO_PRESET3_SDR104DRVRSTRSEL_Msk (0xc000UL)                /*!< SDR104DRVRSTRSEL (Bitfield-Mask: 0x03)                */
43663 #define SDIO_PRESET3_SDR104CLKGENSEL_Pos  (10UL)                    /*!< SDR104CLKGENSEL (Bit 10)                              */
43664 #define SDIO_PRESET3_SDR104CLKGENSEL_Msk  (0x400UL)                 /*!< SDR104CLKGENSEL (Bitfield-Mask: 0x01)                 */
43665 #define SDIO_PRESET3_SDR104SDCLKFREQSEL_Pos (0UL)                   /*!< SDR104SDCLKFREQSEL (Bit 0)                            */
43666 #define SDIO_PRESET3_SDR104SDCLKFREQSEL_Msk (0x3ffUL)               /*!< SDR104SDCLKFREQSEL (Bitfield-Mask: 0x3ff)             */
43667 /* ======================================================  BOOTTOCTRL  ======================================================= */
43668 #define SDIO_BOOTTOCTRL_BOOTDATATO_Pos    (0UL)                     /*!< BOOTDATATO (Bit 0)                                    */
43669 #define SDIO_BOOTTOCTRL_BOOTDATATO_Msk    (0xffffffffUL)            /*!< BOOTDATATO (Bitfield-Mask: 0xffffffff)                */
43670 /* ========================================================  VENDOR  ========================================================= */
43671 #define SDIO_VENDOR_DLYDIS_Pos            (1UL)                     /*!< DLYDIS (Bit 1)                                        */
43672 #define SDIO_VENDOR_DLYDIS_Msk            (0x2UL)                   /*!< DLYDIS (Bitfield-Mask: 0x01)                          */
43673 #define SDIO_VENDOR_GATESDCLKEN_Pos       (0UL)                     /*!< GATESDCLKEN (Bit 0)                                   */
43674 #define SDIO_VENDOR_GATESDCLKEN_Msk       (0x1UL)                   /*!< GATESDCLKEN (Bitfield-Mask: 0x01)                     */
43675 /* =======================================================  SLOTSTAT  ======================================================== */
43676 #define SDIO_SLOTSTAT_VENDORVER_Pos       (24UL)                    /*!< VENDORVER (Bit 24)                                    */
43677 #define SDIO_SLOTSTAT_VENDORVER_Msk       (0xff000000UL)            /*!< VENDORVER (Bitfield-Mask: 0xff)                       */
43678 #define SDIO_SLOTSTAT_SPECVER_Pos         (16UL)                    /*!< SPECVER (Bit 16)                                      */
43679 #define SDIO_SLOTSTAT_SPECVER_Msk         (0xff0000UL)              /*!< SPECVER (Bitfield-Mask: 0xff)                         */
43680 #define SDIO_SLOTSTAT_INTSLOT0_Pos        (0UL)                     /*!< INTSLOT0 (Bit 0)                                      */
43681 #define SDIO_SLOTSTAT_INTSLOT0_Msk        (0x1UL)                   /*!< INTSLOT0 (Bitfield-Mask: 0x01)                        */
43682 
43683 
43684 /* =========================================================================================================================== */
43685 /* ================                                         SECURITY                                          ================ */
43686 /* =========================================================================================================================== */
43687 
43688 /* =========================================================  CTRL  ========================================================== */
43689 #define SECURITY_CTRL_CRCERROR_Pos        (31UL)                    /*!< CRCERROR (Bit 31)                                     */
43690 #define SECURITY_CTRL_CRCERROR_Msk        (0x80000000UL)            /*!< CRCERROR (Bitfield-Mask: 0x01)                        */
43691 #define SECURITY_CTRL_FUNCTION_Pos        (4UL)                     /*!< FUNCTION (Bit 4)                                      */
43692 #define SECURITY_CTRL_FUNCTION_Msk        (0xf0UL)                  /*!< FUNCTION (Bitfield-Mask: 0x0f)                        */
43693 #define SECURITY_CTRL_ENABLE_Pos          (0UL)                     /*!< ENABLE (Bit 0)                                        */
43694 #define SECURITY_CTRL_ENABLE_Msk          (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
43695 /* ========================================================  SRCADDR  ======================================================== */
43696 #define SECURITY_SRCADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
43697 #define SECURITY_SRCADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
43698 /* ==========================================================  LEN  ========================================================== */
43699 #define SECURITY_LEN_LEN_Pos              (2UL)                     /*!< LEN (Bit 2)                                           */
43700 #define SECURITY_LEN_LEN_Msk              (0xfffffcUL)              /*!< LEN (Bitfield-Mask: 0x3fffff)                         */
43701 /* ========================================================  RESULT  ========================================================= */
43702 #define SECURITY_RESULT_CRC_Pos           (0UL)                     /*!< CRC (Bit 0)                                           */
43703 #define SECURITY_RESULT_CRC_Msk           (0xffffffffUL)            /*!< CRC (Bitfield-Mask: 0xffffffff)                       */
43704 /* =======================================================  LOCKCTRL  ======================================================== */
43705 #define SECURITY_LOCKCTRL_SELECT_Pos      (0UL)                     /*!< SELECT (Bit 0)                                        */
43706 #define SECURITY_LOCKCTRL_SELECT_Msk      (0xffUL)                  /*!< SELECT (Bitfield-Mask: 0xff)                          */
43707 /* =======================================================  LOCKSTAT  ======================================================== */
43708 #define SECURITY_LOCKSTAT_STATUS_Pos      (0UL)                     /*!< STATUS (Bit 0)                                        */
43709 #define SECURITY_LOCKSTAT_STATUS_Msk      (0xffffffffUL)            /*!< STATUS (Bitfield-Mask: 0xffffffff)                    */
43710 /* =========================================================  KEY0  ========================================================== */
43711 #define SECURITY_KEY0_KEY0_Pos            (0UL)                     /*!< KEY0 (Bit 0)                                          */
43712 #define SECURITY_KEY0_KEY0_Msk            (0xffffffffUL)            /*!< KEY0 (Bitfield-Mask: 0xffffffff)                      */
43713 /* =========================================================  KEY1  ========================================================== */
43714 #define SECURITY_KEY1_KEY1_Pos            (0UL)                     /*!< KEY1 (Bit 0)                                          */
43715 #define SECURITY_KEY1_KEY1_Msk            (0xffffffffUL)            /*!< KEY1 (Bitfield-Mask: 0xffffffff)                      */
43716 /* =========================================================  KEY2  ========================================================== */
43717 #define SECURITY_KEY2_KEY2_Pos            (0UL)                     /*!< KEY2 (Bit 0)                                          */
43718 #define SECURITY_KEY2_KEY2_Msk            (0xffffffffUL)            /*!< KEY2 (Bitfield-Mask: 0xffffffff)                      */
43719 /* =========================================================  KEY3  ========================================================== */
43720 #define SECURITY_KEY3_KEY3_Pos            (0UL)                     /*!< KEY3 (Bit 0)                                          */
43721 #define SECURITY_KEY3_KEY3_Msk            (0xffffffffUL)            /*!< KEY3 (Bitfield-Mask: 0xffffffff)                      */
43722 
43723 
43724 /* =========================================================================================================================== */
43725 /* ================                                          STIMER                                           ================ */
43726 /* =========================================================================================================================== */
43727 
43728 /* =========================================================  STCFG  ========================================================= */
43729 #define STIMER_STCFG_FREEZE_Pos           (31UL)                    /*!< FREEZE (Bit 31)                                       */
43730 #define STIMER_STCFG_FREEZE_Msk           (0x80000000UL)            /*!< FREEZE (Bitfield-Mask: 0x01)                          */
43731 #define STIMER_STCFG_CLEAR_Pos            (30UL)                    /*!< CLEAR (Bit 30)                                        */
43732 #define STIMER_STCFG_CLEAR_Msk            (0x40000000UL)            /*!< CLEAR (Bitfield-Mask: 0x01)                           */
43733 #define STIMER_STCFG_COMPAREHEN_Pos       (15UL)                    /*!< COMPAREHEN (Bit 15)                                   */
43734 #define STIMER_STCFG_COMPAREHEN_Msk       (0x8000UL)                /*!< COMPAREHEN (Bitfield-Mask: 0x01)                      */
43735 #define STIMER_STCFG_COMPAREGEN_Pos       (14UL)                    /*!< COMPAREGEN (Bit 14)                                   */
43736 #define STIMER_STCFG_COMPAREGEN_Msk       (0x4000UL)                /*!< COMPAREGEN (Bitfield-Mask: 0x01)                      */
43737 #define STIMER_STCFG_COMPAREFEN_Pos       (13UL)                    /*!< COMPAREFEN (Bit 13)                                   */
43738 #define STIMER_STCFG_COMPAREFEN_Msk       (0x2000UL)                /*!< COMPAREFEN (Bitfield-Mask: 0x01)                      */
43739 #define STIMER_STCFG_COMPAREEEN_Pos       (12UL)                    /*!< COMPAREEEN (Bit 12)                                   */
43740 #define STIMER_STCFG_COMPAREEEN_Msk       (0x1000UL)                /*!< COMPAREEEN (Bitfield-Mask: 0x01)                      */
43741 #define STIMER_STCFG_COMPAREDEN_Pos       (11UL)                    /*!< COMPAREDEN (Bit 11)                                   */
43742 #define STIMER_STCFG_COMPAREDEN_Msk       (0x800UL)                 /*!< COMPAREDEN (Bitfield-Mask: 0x01)                      */
43743 #define STIMER_STCFG_COMPARECEN_Pos       (10UL)                    /*!< COMPARECEN (Bit 10)                                   */
43744 #define STIMER_STCFG_COMPARECEN_Msk       (0x400UL)                 /*!< COMPARECEN (Bitfield-Mask: 0x01)                      */
43745 #define STIMER_STCFG_COMPAREBEN_Pos       (9UL)                     /*!< COMPAREBEN (Bit 9)                                    */
43746 #define STIMER_STCFG_COMPAREBEN_Msk       (0x200UL)                 /*!< COMPAREBEN (Bitfield-Mask: 0x01)                      */
43747 #define STIMER_STCFG_COMPAREAEN_Pos       (8UL)                     /*!< COMPAREAEN (Bit 8)                                    */
43748 #define STIMER_STCFG_COMPAREAEN_Msk       (0x100UL)                 /*!< COMPAREAEN (Bitfield-Mask: 0x01)                      */
43749 #define STIMER_STCFG_CLKSEL_Pos           (0UL)                     /*!< CLKSEL (Bit 0)                                        */
43750 #define STIMER_STCFG_CLKSEL_Msk           (0xfUL)                   /*!< CLKSEL (Bitfield-Mask: 0x0f)                          */
43751 /* =========================================================  STTMR  ========================================================= */
43752 #define STIMER_STTMR_STTMR_Pos            (0UL)                     /*!< STTMR (Bit 0)                                         */
43753 #define STIMER_STTMR_STTMR_Msk            (0xffffffffUL)            /*!< STTMR (Bitfield-Mask: 0xffffffff)                     */
43754 /* =======================================================  SCAPCTRL0  ======================================================= */
43755 #define STIMER_SCAPCTRL0_CAPTURE0_Pos     (9UL)                     /*!< CAPTURE0 (Bit 9)                                      */
43756 #define STIMER_SCAPCTRL0_CAPTURE0_Msk     (0x200UL)                 /*!< CAPTURE0 (Bitfield-Mask: 0x01)                        */
43757 #define STIMER_SCAPCTRL0_STPOL0_Pos       (8UL)                     /*!< STPOL0 (Bit 8)                                        */
43758 #define STIMER_SCAPCTRL0_STPOL0_Msk       (0x100UL)                 /*!< STPOL0 (Bitfield-Mask: 0x01)                          */
43759 #define STIMER_SCAPCTRL0_STSEL0_Pos       (0UL)                     /*!< STSEL0 (Bit 0)                                        */
43760 #define STIMER_SCAPCTRL0_STSEL0_Msk       (0x7fUL)                  /*!< STSEL0 (Bitfield-Mask: 0x7f)                          */
43761 /* =======================================================  SCAPCTRL1  ======================================================= */
43762 #define STIMER_SCAPCTRL1_CAPTURE1_Pos     (9UL)                     /*!< CAPTURE1 (Bit 9)                                      */
43763 #define STIMER_SCAPCTRL1_CAPTURE1_Msk     (0x200UL)                 /*!< CAPTURE1 (Bitfield-Mask: 0x01)                        */
43764 #define STIMER_SCAPCTRL1_STPOL1_Pos       (8UL)                     /*!< STPOL1 (Bit 8)                                        */
43765 #define STIMER_SCAPCTRL1_STPOL1_Msk       (0x100UL)                 /*!< STPOL1 (Bitfield-Mask: 0x01)                          */
43766 #define STIMER_SCAPCTRL1_STSEL1_Pos       (0UL)                     /*!< STSEL1 (Bit 0)                                        */
43767 #define STIMER_SCAPCTRL1_STSEL1_Msk       (0x7fUL)                  /*!< STSEL1 (Bitfield-Mask: 0x7f)                          */
43768 /* =======================================================  SCAPCTRL2  ======================================================= */
43769 #define STIMER_SCAPCTRL2_CAPTURE2_Pos     (9UL)                     /*!< CAPTURE2 (Bit 9)                                      */
43770 #define STIMER_SCAPCTRL2_CAPTURE2_Msk     (0x200UL)                 /*!< CAPTURE2 (Bitfield-Mask: 0x01)                        */
43771 #define STIMER_SCAPCTRL2_STPOL2_Pos       (8UL)                     /*!< STPOL2 (Bit 8)                                        */
43772 #define STIMER_SCAPCTRL2_STPOL2_Msk       (0x100UL)                 /*!< STPOL2 (Bitfield-Mask: 0x01)                          */
43773 #define STIMER_SCAPCTRL2_STSEL2_Pos       (0UL)                     /*!< STSEL2 (Bit 0)                                        */
43774 #define STIMER_SCAPCTRL2_STSEL2_Msk       (0x7fUL)                  /*!< STSEL2 (Bitfield-Mask: 0x7f)                          */
43775 /* =======================================================  SCAPCTRL3  ======================================================= */
43776 #define STIMER_SCAPCTRL3_CAPTURE3_Pos     (9UL)                     /*!< CAPTURE3 (Bit 9)                                      */
43777 #define STIMER_SCAPCTRL3_CAPTURE3_Msk     (0x200UL)                 /*!< CAPTURE3 (Bitfield-Mask: 0x01)                        */
43778 #define STIMER_SCAPCTRL3_STPOL3_Pos       (8UL)                     /*!< STPOL3 (Bit 8)                                        */
43779 #define STIMER_SCAPCTRL3_STPOL3_Msk       (0x100UL)                 /*!< STPOL3 (Bitfield-Mask: 0x01)                          */
43780 #define STIMER_SCAPCTRL3_STSEL3_Pos       (0UL)                     /*!< STSEL3 (Bit 0)                                        */
43781 #define STIMER_SCAPCTRL3_STSEL3_Msk       (0x7fUL)                  /*!< STSEL3 (Bitfield-Mask: 0x7f)                          */
43782 /* ========================================================  SCMPR0  ========================================================= */
43783 #define STIMER_SCMPR0_SCMPR0_Pos          (0UL)                     /*!< SCMPR0 (Bit 0)                                        */
43784 #define STIMER_SCMPR0_SCMPR0_Msk          (0xffffffffUL)            /*!< SCMPR0 (Bitfield-Mask: 0xffffffff)                    */
43785 /* ========================================================  SCMPR1  ========================================================= */
43786 #define STIMER_SCMPR1_SCMPR1_Pos          (0UL)                     /*!< SCMPR1 (Bit 0)                                        */
43787 #define STIMER_SCMPR1_SCMPR1_Msk          (0xffffffffUL)            /*!< SCMPR1 (Bitfield-Mask: 0xffffffff)                    */
43788 /* ========================================================  SCMPR2  ========================================================= */
43789 #define STIMER_SCMPR2_SCMPR2_Pos          (0UL)                     /*!< SCMPR2 (Bit 0)                                        */
43790 #define STIMER_SCMPR2_SCMPR2_Msk          (0xffffffffUL)            /*!< SCMPR2 (Bitfield-Mask: 0xffffffff)                    */
43791 /* ========================================================  SCMPR3  ========================================================= */
43792 #define STIMER_SCMPR3_SCMPR3_Pos          (0UL)                     /*!< SCMPR3 (Bit 0)                                        */
43793 #define STIMER_SCMPR3_SCMPR3_Msk          (0xffffffffUL)            /*!< SCMPR3 (Bitfield-Mask: 0xffffffff)                    */
43794 /* ========================================================  SCMPR4  ========================================================= */
43795 #define STIMER_SCMPR4_SCMPR4_Pos          (0UL)                     /*!< SCMPR4 (Bit 0)                                        */
43796 #define STIMER_SCMPR4_SCMPR4_Msk          (0xffffffffUL)            /*!< SCMPR4 (Bitfield-Mask: 0xffffffff)                    */
43797 /* ========================================================  SCMPR5  ========================================================= */
43798 #define STIMER_SCMPR5_SCMPR5_Pos          (0UL)                     /*!< SCMPR5 (Bit 0)                                        */
43799 #define STIMER_SCMPR5_SCMPR5_Msk          (0xffffffffUL)            /*!< SCMPR5 (Bitfield-Mask: 0xffffffff)                    */
43800 /* ========================================================  SCMPR6  ========================================================= */
43801 #define STIMER_SCMPR6_SCMPR6_Pos          (0UL)                     /*!< SCMPR6 (Bit 0)                                        */
43802 #define STIMER_SCMPR6_SCMPR6_Msk          (0xffffffffUL)            /*!< SCMPR6 (Bitfield-Mask: 0xffffffff)                    */
43803 /* ========================================================  SCMPR7  ========================================================= */
43804 #define STIMER_SCMPR7_SCMPR7_Pos          (0UL)                     /*!< SCMPR7 (Bit 0)                                        */
43805 #define STIMER_SCMPR7_SCMPR7_Msk          (0xffffffffUL)            /*!< SCMPR7 (Bitfield-Mask: 0xffffffff)                    */
43806 /* ========================================================  SCAPT0  ========================================================= */
43807 #define STIMER_SCAPT0_SCAPT0_Pos          (0UL)                     /*!< SCAPT0 (Bit 0)                                        */
43808 #define STIMER_SCAPT0_SCAPT0_Msk          (0xffffffffUL)            /*!< SCAPT0 (Bitfield-Mask: 0xffffffff)                    */
43809 /* ========================================================  SCAPT1  ========================================================= */
43810 #define STIMER_SCAPT1_SCAPT1_Pos          (0UL)                     /*!< SCAPT1 (Bit 0)                                        */
43811 #define STIMER_SCAPT1_SCAPT1_Msk          (0xffffffffUL)            /*!< SCAPT1 (Bitfield-Mask: 0xffffffff)                    */
43812 /* ========================================================  SCAPT2  ========================================================= */
43813 #define STIMER_SCAPT2_SCAPT2_Pos          (0UL)                     /*!< SCAPT2 (Bit 0)                                        */
43814 #define STIMER_SCAPT2_SCAPT2_Msk          (0xffffffffUL)            /*!< SCAPT2 (Bitfield-Mask: 0xffffffff)                    */
43815 /* ========================================================  SCAPT3  ========================================================= */
43816 #define STIMER_SCAPT3_SCAPT3_Pos          (0UL)                     /*!< SCAPT3 (Bit 0)                                        */
43817 #define STIMER_SCAPT3_SCAPT3_Msk          (0xffffffffUL)            /*!< SCAPT3 (Bitfield-Mask: 0xffffffff)                    */
43818 /* =========================================================  SNVR0  ========================================================= */
43819 #define STIMER_SNVR0_SNVR0_Pos            (0UL)                     /*!< SNVR0 (Bit 0)                                         */
43820 #define STIMER_SNVR0_SNVR0_Msk            (0xffffffffUL)            /*!< SNVR0 (Bitfield-Mask: 0xffffffff)                     */
43821 /* =========================================================  SNVR1  ========================================================= */
43822 #define STIMER_SNVR1_SNVR1_Pos            (0UL)                     /*!< SNVR1 (Bit 0)                                         */
43823 #define STIMER_SNVR1_SNVR1_Msk            (0xffffffffUL)            /*!< SNVR1 (Bitfield-Mask: 0xffffffff)                     */
43824 /* =========================================================  SNVR2  ========================================================= */
43825 #define STIMER_SNVR2_SNVR2_Pos            (0UL)                     /*!< SNVR2 (Bit 0)                                         */
43826 #define STIMER_SNVR2_SNVR2_Msk            (0xffffffffUL)            /*!< SNVR2 (Bitfield-Mask: 0xffffffff)                     */
43827 /* =======================================================  STMINTEN  ======================================================== */
43828 #define STIMER_STMINTEN_CAPTURED_Pos      (12UL)                    /*!< CAPTURED (Bit 12)                                     */
43829 #define STIMER_STMINTEN_CAPTURED_Msk      (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
43830 #define STIMER_STMINTEN_CAPTUREC_Pos      (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
43831 #define STIMER_STMINTEN_CAPTUREC_Msk      (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
43832 #define STIMER_STMINTEN_CAPTUREB_Pos      (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
43833 #define STIMER_STMINTEN_CAPTUREB_Msk      (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
43834 #define STIMER_STMINTEN_CAPTUREA_Pos      (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
43835 #define STIMER_STMINTEN_CAPTUREA_Msk      (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
43836 #define STIMER_STMINTEN_OVERFLOW_Pos      (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
43837 #define STIMER_STMINTEN_OVERFLOW_Msk      (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
43838 #define STIMER_STMINTEN_COMPAREH_Pos      (7UL)                     /*!< COMPAREH (Bit 7)                                      */
43839 #define STIMER_STMINTEN_COMPAREH_Msk      (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
43840 #define STIMER_STMINTEN_COMPAREG_Pos      (6UL)                     /*!< COMPAREG (Bit 6)                                      */
43841 #define STIMER_STMINTEN_COMPAREG_Msk      (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
43842 #define STIMER_STMINTEN_COMPAREF_Pos      (5UL)                     /*!< COMPAREF (Bit 5)                                      */
43843 #define STIMER_STMINTEN_COMPAREF_Msk      (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
43844 #define STIMER_STMINTEN_COMPAREE_Pos      (4UL)                     /*!< COMPAREE (Bit 4)                                      */
43845 #define STIMER_STMINTEN_COMPAREE_Msk      (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
43846 #define STIMER_STMINTEN_COMPARED_Pos      (3UL)                     /*!< COMPARED (Bit 3)                                      */
43847 #define STIMER_STMINTEN_COMPARED_Msk      (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
43848 #define STIMER_STMINTEN_COMPAREC_Pos      (2UL)                     /*!< COMPAREC (Bit 2)                                      */
43849 #define STIMER_STMINTEN_COMPAREC_Msk      (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
43850 #define STIMER_STMINTEN_COMPAREB_Pos      (1UL)                     /*!< COMPAREB (Bit 1)                                      */
43851 #define STIMER_STMINTEN_COMPAREB_Msk      (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
43852 #define STIMER_STMINTEN_COMPAREA_Pos      (0UL)                     /*!< COMPAREA (Bit 0)                                      */
43853 #define STIMER_STMINTEN_COMPAREA_Msk      (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
43854 /* ======================================================  STMINTSTAT  ======================================================= */
43855 #define STIMER_STMINTSTAT_CAPTURED_Pos    (12UL)                    /*!< CAPTURED (Bit 12)                                     */
43856 #define STIMER_STMINTSTAT_CAPTURED_Msk    (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
43857 #define STIMER_STMINTSTAT_CAPTUREC_Pos    (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
43858 #define STIMER_STMINTSTAT_CAPTUREC_Msk    (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
43859 #define STIMER_STMINTSTAT_CAPTUREB_Pos    (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
43860 #define STIMER_STMINTSTAT_CAPTUREB_Msk    (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
43861 #define STIMER_STMINTSTAT_CAPTUREA_Pos    (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
43862 #define STIMER_STMINTSTAT_CAPTUREA_Msk    (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
43863 #define STIMER_STMINTSTAT_OVERFLOW_Pos    (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
43864 #define STIMER_STMINTSTAT_OVERFLOW_Msk    (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
43865 #define STIMER_STMINTSTAT_COMPAREH_Pos    (7UL)                     /*!< COMPAREH (Bit 7)                                      */
43866 #define STIMER_STMINTSTAT_COMPAREH_Msk    (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
43867 #define STIMER_STMINTSTAT_COMPAREG_Pos    (6UL)                     /*!< COMPAREG (Bit 6)                                      */
43868 #define STIMER_STMINTSTAT_COMPAREG_Msk    (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
43869 #define STIMER_STMINTSTAT_COMPAREF_Pos    (5UL)                     /*!< COMPAREF (Bit 5)                                      */
43870 #define STIMER_STMINTSTAT_COMPAREF_Msk    (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
43871 #define STIMER_STMINTSTAT_COMPAREE_Pos    (4UL)                     /*!< COMPAREE (Bit 4)                                      */
43872 #define STIMER_STMINTSTAT_COMPAREE_Msk    (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
43873 #define STIMER_STMINTSTAT_COMPARED_Pos    (3UL)                     /*!< COMPARED (Bit 3)                                      */
43874 #define STIMER_STMINTSTAT_COMPARED_Msk    (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
43875 #define STIMER_STMINTSTAT_COMPAREC_Pos    (2UL)                     /*!< COMPAREC (Bit 2)                                      */
43876 #define STIMER_STMINTSTAT_COMPAREC_Msk    (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
43877 #define STIMER_STMINTSTAT_COMPAREB_Pos    (1UL)                     /*!< COMPAREB (Bit 1)                                      */
43878 #define STIMER_STMINTSTAT_COMPAREB_Msk    (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
43879 #define STIMER_STMINTSTAT_COMPAREA_Pos    (0UL)                     /*!< COMPAREA (Bit 0)                                      */
43880 #define STIMER_STMINTSTAT_COMPAREA_Msk    (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
43881 /* =======================================================  STMINTCLR  ======================================================= */
43882 #define STIMER_STMINTCLR_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
43883 #define STIMER_STMINTCLR_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
43884 #define STIMER_STMINTCLR_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
43885 #define STIMER_STMINTCLR_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
43886 #define STIMER_STMINTCLR_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
43887 #define STIMER_STMINTCLR_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
43888 #define STIMER_STMINTCLR_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
43889 #define STIMER_STMINTCLR_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
43890 #define STIMER_STMINTCLR_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
43891 #define STIMER_STMINTCLR_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
43892 #define STIMER_STMINTCLR_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
43893 #define STIMER_STMINTCLR_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
43894 #define STIMER_STMINTCLR_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
43895 #define STIMER_STMINTCLR_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
43896 #define STIMER_STMINTCLR_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
43897 #define STIMER_STMINTCLR_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
43898 #define STIMER_STMINTCLR_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
43899 #define STIMER_STMINTCLR_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
43900 #define STIMER_STMINTCLR_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
43901 #define STIMER_STMINTCLR_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
43902 #define STIMER_STMINTCLR_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
43903 #define STIMER_STMINTCLR_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
43904 #define STIMER_STMINTCLR_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
43905 #define STIMER_STMINTCLR_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
43906 #define STIMER_STMINTCLR_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
43907 #define STIMER_STMINTCLR_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
43908 /* =======================================================  STMINTSET  ======================================================= */
43909 #define STIMER_STMINTSET_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
43910 #define STIMER_STMINTSET_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
43911 #define STIMER_STMINTSET_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
43912 #define STIMER_STMINTSET_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
43913 #define STIMER_STMINTSET_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
43914 #define STIMER_STMINTSET_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
43915 #define STIMER_STMINTSET_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
43916 #define STIMER_STMINTSET_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
43917 #define STIMER_STMINTSET_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
43918 #define STIMER_STMINTSET_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
43919 #define STIMER_STMINTSET_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
43920 #define STIMER_STMINTSET_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
43921 #define STIMER_STMINTSET_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
43922 #define STIMER_STMINTSET_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
43923 #define STIMER_STMINTSET_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
43924 #define STIMER_STMINTSET_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
43925 #define STIMER_STMINTSET_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
43926 #define STIMER_STMINTSET_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
43927 #define STIMER_STMINTSET_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
43928 #define STIMER_STMINTSET_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
43929 #define STIMER_STMINTSET_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
43930 #define STIMER_STMINTSET_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
43931 #define STIMER_STMINTSET_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
43932 #define STIMER_STMINTSET_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
43933 #define STIMER_STMINTSET_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
43934 #define STIMER_STMINTSET_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
43935 
43936 
43937 /* =========================================================================================================================== */
43938 /* ================                                           TIMER                                           ================ */
43939 /* =========================================================================================================================== */
43940 
43941 /* =========================================================  CTRL  ========================================================== */
43942 #define TIMER_CTRL_RESET_Pos              (31UL)                    /*!< RESET (Bit 31)                                        */
43943 #define TIMER_CTRL_RESET_Msk              (0x80000000UL)            /*!< RESET (Bitfield-Mask: 0x01)                           */
43944 /* ========================================================  STATUS  ========================================================= */
43945 #define TIMER_STATUS_NTIMERS_Pos          (16UL)                    /*!< NTIMERS (Bit 16)                                      */
43946 #define TIMER_STATUS_NTIMERS_Msk          (0x1f0000UL)              /*!< NTIMERS (Bitfield-Mask: 0x1f)                         */
43947 #define TIMER_STATUS_ACTIVE_Pos           (0UL)                     /*!< ACTIVE (Bit 0)                                        */
43948 #define TIMER_STATUS_ACTIVE_Msk           (0xffffUL)                /*!< ACTIVE (Bitfield-Mask: 0xffff)                        */
43949 /* ========================================================  GLOBEN  ========================================================= */
43950 #define TIMER_GLOBEN_ADCEN_Pos            (31UL)                    /*!< ADCEN (Bit 31)                                        */
43951 #define TIMER_GLOBEN_ADCEN_Msk            (0x80000000UL)            /*!< ADCEN (Bitfield-Mask: 0x01)                           */
43952 #define TIMER_GLOBEN_AUDADCEN_Pos         (30UL)                    /*!< AUDADCEN (Bit 30)                                     */
43953 #define TIMER_GLOBEN_AUDADCEN_Msk         (0x40000000UL)            /*!< AUDADCEN (Bitfield-Mask: 0x01)                        */
43954 #define TIMER_GLOBEN_ENABLEALLINPUTS_Pos  (29UL)                    /*!< ENABLEALLINPUTS (Bit 29)                              */
43955 #define TIMER_GLOBEN_ENABLEALLINPUTS_Msk  (0x20000000UL)            /*!< ENABLEALLINPUTS (Bitfield-Mask: 0x01)                 */
43956 #define TIMER_GLOBEN_ENB15_Pos            (15UL)                    /*!< ENB15 (Bit 15)                                        */
43957 #define TIMER_GLOBEN_ENB15_Msk            (0x8000UL)                /*!< ENB15 (Bitfield-Mask: 0x01)                           */
43958 #define TIMER_GLOBEN_ENB14_Pos            (14UL)                    /*!< ENB14 (Bit 14)                                        */
43959 #define TIMER_GLOBEN_ENB14_Msk            (0x4000UL)                /*!< ENB14 (Bitfield-Mask: 0x01)                           */
43960 #define TIMER_GLOBEN_ENB13_Pos            (13UL)                    /*!< ENB13 (Bit 13)                                        */
43961 #define TIMER_GLOBEN_ENB13_Msk            (0x2000UL)                /*!< ENB13 (Bitfield-Mask: 0x01)                           */
43962 #define TIMER_GLOBEN_ENB12_Pos            (12UL)                    /*!< ENB12 (Bit 12)                                        */
43963 #define TIMER_GLOBEN_ENB12_Msk            (0x1000UL)                /*!< ENB12 (Bitfield-Mask: 0x01)                           */
43964 #define TIMER_GLOBEN_ENB11_Pos            (11UL)                    /*!< ENB11 (Bit 11)                                        */
43965 #define TIMER_GLOBEN_ENB11_Msk            (0x800UL)                 /*!< ENB11 (Bitfield-Mask: 0x01)                           */
43966 #define TIMER_GLOBEN_ENB10_Pos            (10UL)                    /*!< ENB10 (Bit 10)                                        */
43967 #define TIMER_GLOBEN_ENB10_Msk            (0x400UL)                 /*!< ENB10 (Bitfield-Mask: 0x01)                           */
43968 #define TIMER_GLOBEN_ENB9_Pos             (9UL)                     /*!< ENB9 (Bit 9)                                          */
43969 #define TIMER_GLOBEN_ENB9_Msk             (0x200UL)                 /*!< ENB9 (Bitfield-Mask: 0x01)                            */
43970 #define TIMER_GLOBEN_ENB8_Pos             (8UL)                     /*!< ENB8 (Bit 8)                                          */
43971 #define TIMER_GLOBEN_ENB8_Msk             (0x100UL)                 /*!< ENB8 (Bitfield-Mask: 0x01)                            */
43972 #define TIMER_GLOBEN_ENB7_Pos             (7UL)                     /*!< ENB7 (Bit 7)                                          */
43973 #define TIMER_GLOBEN_ENB7_Msk             (0x80UL)                  /*!< ENB7 (Bitfield-Mask: 0x01)                            */
43974 #define TIMER_GLOBEN_ENB6_Pos             (6UL)                     /*!< ENB6 (Bit 6)                                          */
43975 #define TIMER_GLOBEN_ENB6_Msk             (0x40UL)                  /*!< ENB6 (Bitfield-Mask: 0x01)                            */
43976 #define TIMER_GLOBEN_ENB5_Pos             (5UL)                     /*!< ENB5 (Bit 5)                                          */
43977 #define TIMER_GLOBEN_ENB5_Msk             (0x20UL)                  /*!< ENB5 (Bitfield-Mask: 0x01)                            */
43978 #define TIMER_GLOBEN_ENB4_Pos             (4UL)                     /*!< ENB4 (Bit 4)                                          */
43979 #define TIMER_GLOBEN_ENB4_Msk             (0x10UL)                  /*!< ENB4 (Bitfield-Mask: 0x01)                            */
43980 #define TIMER_GLOBEN_ENB3_Pos             (3UL)                     /*!< ENB3 (Bit 3)                                          */
43981 #define TIMER_GLOBEN_ENB3_Msk             (0x8UL)                   /*!< ENB3 (Bitfield-Mask: 0x01)                            */
43982 #define TIMER_GLOBEN_ENB2_Pos             (2UL)                     /*!< ENB2 (Bit 2)                                          */
43983 #define TIMER_GLOBEN_ENB2_Msk             (0x4UL)                   /*!< ENB2 (Bitfield-Mask: 0x01)                            */
43984 #define TIMER_GLOBEN_ENB1_Pos             (1UL)                     /*!< ENB1 (Bit 1)                                          */
43985 #define TIMER_GLOBEN_ENB1_Msk             (0x2UL)                   /*!< ENB1 (Bitfield-Mask: 0x01)                            */
43986 #define TIMER_GLOBEN_ENB0_Pos             (0UL)                     /*!< ENB0 (Bit 0)                                          */
43987 #define TIMER_GLOBEN_ENB0_Msk             (0x1UL)                   /*!< ENB0 (Bitfield-Mask: 0x01)                            */
43988 /* =========================================================  INTEN  ========================================================= */
43989 #define TIMER_INTEN_TMR151INT_Pos         (31UL)                    /*!< TMR151INT (Bit 31)                                    */
43990 #define TIMER_INTEN_TMR151INT_Msk         (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
43991 #define TIMER_INTEN_TMR150INT_Pos         (30UL)                    /*!< TMR150INT (Bit 30)                                    */
43992 #define TIMER_INTEN_TMR150INT_Msk         (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
43993 #define TIMER_INTEN_TMR141INT_Pos         (29UL)                    /*!< TMR141INT (Bit 29)                                    */
43994 #define TIMER_INTEN_TMR141INT_Msk         (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
43995 #define TIMER_INTEN_TMR140INT_Pos         (28UL)                    /*!< TMR140INT (Bit 28)                                    */
43996 #define TIMER_INTEN_TMR140INT_Msk         (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
43997 #define TIMER_INTEN_TMR131INT_Pos         (27UL)                    /*!< TMR131INT (Bit 27)                                    */
43998 #define TIMER_INTEN_TMR131INT_Msk         (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
43999 #define TIMER_INTEN_TMR130INT_Pos         (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44000 #define TIMER_INTEN_TMR130INT_Msk         (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
44001 #define TIMER_INTEN_TMR121INT_Pos         (25UL)                    /*!< TMR121INT (Bit 25)                                    */
44002 #define TIMER_INTEN_TMR121INT_Msk         (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
44003 #define TIMER_INTEN_TMR120INT_Pos         (24UL)                    /*!< TMR120INT (Bit 24)                                    */
44004 #define TIMER_INTEN_TMR120INT_Msk         (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
44005 #define TIMER_INTEN_TMR111INT_Pos         (23UL)                    /*!< TMR111INT (Bit 23)                                    */
44006 #define TIMER_INTEN_TMR111INT_Msk         (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
44007 #define TIMER_INTEN_TMR110INT_Pos         (22UL)                    /*!< TMR110INT (Bit 22)                                    */
44008 #define TIMER_INTEN_TMR110INT_Msk         (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
44009 #define TIMER_INTEN_TMR101INT_Pos         (21UL)                    /*!< TMR101INT (Bit 21)                                    */
44010 #define TIMER_INTEN_TMR101INT_Msk         (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
44011 #define TIMER_INTEN_TMR100INT_Pos         (20UL)                    /*!< TMR100INT (Bit 20)                                    */
44012 #define TIMER_INTEN_TMR100INT_Msk         (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
44013 #define TIMER_INTEN_TMR91INT_Pos          (19UL)                    /*!< TMR91INT (Bit 19)                                     */
44014 #define TIMER_INTEN_TMR91INT_Msk          (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
44015 #define TIMER_INTEN_TMR90INT_Pos          (18UL)                    /*!< TMR90INT (Bit 18)                                     */
44016 #define TIMER_INTEN_TMR90INT_Msk          (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
44017 #define TIMER_INTEN_TMR81INT_Pos          (17UL)                    /*!< TMR81INT (Bit 17)                                     */
44018 #define TIMER_INTEN_TMR81INT_Msk          (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
44019 #define TIMER_INTEN_TMR80INT_Pos          (16UL)                    /*!< TMR80INT (Bit 16)                                     */
44020 #define TIMER_INTEN_TMR80INT_Msk          (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
44021 #define TIMER_INTEN_TMR71INT_Pos          (15UL)                    /*!< TMR71INT (Bit 15)                                     */
44022 #define TIMER_INTEN_TMR71INT_Msk          (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
44023 #define TIMER_INTEN_TMR70INT_Pos          (14UL)                    /*!< TMR70INT (Bit 14)                                     */
44024 #define TIMER_INTEN_TMR70INT_Msk          (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
44025 #define TIMER_INTEN_TMR61INT_Pos          (13UL)                    /*!< TMR61INT (Bit 13)                                     */
44026 #define TIMER_INTEN_TMR61INT_Msk          (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
44027 #define TIMER_INTEN_TMR60INT_Pos          (12UL)                    /*!< TMR60INT (Bit 12)                                     */
44028 #define TIMER_INTEN_TMR60INT_Msk          (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
44029 #define TIMER_INTEN_TMR51INT_Pos          (11UL)                    /*!< TMR51INT (Bit 11)                                     */
44030 #define TIMER_INTEN_TMR51INT_Msk          (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
44031 #define TIMER_INTEN_TMR50INT_Pos          (10UL)                    /*!< TMR50INT (Bit 10)                                     */
44032 #define TIMER_INTEN_TMR50INT_Msk          (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
44033 #define TIMER_INTEN_TMR41INT_Pos          (9UL)                     /*!< TMR41INT (Bit 9)                                      */
44034 #define TIMER_INTEN_TMR41INT_Msk          (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
44035 #define TIMER_INTEN_TMR40INT_Pos          (8UL)                     /*!< TMR40INT (Bit 8)                                      */
44036 #define TIMER_INTEN_TMR40INT_Msk          (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
44037 #define TIMER_INTEN_TMR31INT_Pos          (7UL)                     /*!< TMR31INT (Bit 7)                                      */
44038 #define TIMER_INTEN_TMR31INT_Msk          (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
44039 #define TIMER_INTEN_TMR30INT_Pos          (6UL)                     /*!< TMR30INT (Bit 6)                                      */
44040 #define TIMER_INTEN_TMR30INT_Msk          (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
44041 #define TIMER_INTEN_TMR21INT_Pos          (5UL)                     /*!< TMR21INT (Bit 5)                                      */
44042 #define TIMER_INTEN_TMR21INT_Msk          (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
44043 #define TIMER_INTEN_TMR20INT_Pos          (4UL)                     /*!< TMR20INT (Bit 4)                                      */
44044 #define TIMER_INTEN_TMR20INT_Msk          (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
44045 #define TIMER_INTEN_TMR11INT_Pos          (3UL)                     /*!< TMR11INT (Bit 3)                                      */
44046 #define TIMER_INTEN_TMR11INT_Msk          (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
44047 #define TIMER_INTEN_TMR10INT_Pos          (2UL)                     /*!< TMR10INT (Bit 2)                                      */
44048 #define TIMER_INTEN_TMR10INT_Msk          (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
44049 #define TIMER_INTEN_TMR01INT_Pos          (1UL)                     /*!< TMR01INT (Bit 1)                                      */
44050 #define TIMER_INTEN_TMR01INT_Msk          (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
44051 #define TIMER_INTEN_TMR00INT_Pos          (0UL)                     /*!< TMR00INT (Bit 0)                                      */
44052 #define TIMER_INTEN_TMR00INT_Msk          (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
44053 /* ========================================================  INTSTAT  ======================================================== */
44054 #define TIMER_INTSTAT_TMR151INT_Pos       (31UL)                    /*!< TMR151INT (Bit 31)                                    */
44055 #define TIMER_INTSTAT_TMR151INT_Msk       (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
44056 #define TIMER_INTSTAT_TMR150INT_Pos       (30UL)                    /*!< TMR150INT (Bit 30)                                    */
44057 #define TIMER_INTSTAT_TMR150INT_Msk       (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
44058 #define TIMER_INTSTAT_TMR141INT_Pos       (29UL)                    /*!< TMR141INT (Bit 29)                                    */
44059 #define TIMER_INTSTAT_TMR141INT_Msk       (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
44060 #define TIMER_INTSTAT_TMR140INT_Pos       (28UL)                    /*!< TMR140INT (Bit 28)                                    */
44061 #define TIMER_INTSTAT_TMR140INT_Msk       (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
44062 #define TIMER_INTSTAT_TMR131INT_Pos       (27UL)                    /*!< TMR131INT (Bit 27)                                    */
44063 #define TIMER_INTSTAT_TMR131INT_Msk       (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
44064 #define TIMER_INTSTAT_TMR130INT_Pos       (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44065 #define TIMER_INTSTAT_TMR130INT_Msk       (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
44066 #define TIMER_INTSTAT_TMR121INT_Pos       (25UL)                    /*!< TMR121INT (Bit 25)                                    */
44067 #define TIMER_INTSTAT_TMR121INT_Msk       (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
44068 #define TIMER_INTSTAT_TMR120INT_Pos       (24UL)                    /*!< TMR120INT (Bit 24)                                    */
44069 #define TIMER_INTSTAT_TMR120INT_Msk       (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
44070 #define TIMER_INTSTAT_TMR111INT_Pos       (23UL)                    /*!< TMR111INT (Bit 23)                                    */
44071 #define TIMER_INTSTAT_TMR111INT_Msk       (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
44072 #define TIMER_INTSTAT_TMR110INT_Pos       (22UL)                    /*!< TMR110INT (Bit 22)                                    */
44073 #define TIMER_INTSTAT_TMR110INT_Msk       (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
44074 #define TIMER_INTSTAT_TMR101INT_Pos       (21UL)                    /*!< TMR101INT (Bit 21)                                    */
44075 #define TIMER_INTSTAT_TMR101INT_Msk       (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
44076 #define TIMER_INTSTAT_TMR100INT_Pos       (20UL)                    /*!< TMR100INT (Bit 20)                                    */
44077 #define TIMER_INTSTAT_TMR100INT_Msk       (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
44078 #define TIMER_INTSTAT_TMR91INT_Pos        (19UL)                    /*!< TMR91INT (Bit 19)                                     */
44079 #define TIMER_INTSTAT_TMR91INT_Msk        (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
44080 #define TIMER_INTSTAT_TMR90INT_Pos        (18UL)                    /*!< TMR90INT (Bit 18)                                     */
44081 #define TIMER_INTSTAT_TMR90INT_Msk        (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
44082 #define TIMER_INTSTAT_TMR81INT_Pos        (17UL)                    /*!< TMR81INT (Bit 17)                                     */
44083 #define TIMER_INTSTAT_TMR81INT_Msk        (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
44084 #define TIMER_INTSTAT_TMR80INT_Pos        (16UL)                    /*!< TMR80INT (Bit 16)                                     */
44085 #define TIMER_INTSTAT_TMR80INT_Msk        (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
44086 #define TIMER_INTSTAT_TMR71INT_Pos        (15UL)                    /*!< TMR71INT (Bit 15)                                     */
44087 #define TIMER_INTSTAT_TMR71INT_Msk        (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
44088 #define TIMER_INTSTAT_TMR70INT_Pos        (14UL)                    /*!< TMR70INT (Bit 14)                                     */
44089 #define TIMER_INTSTAT_TMR70INT_Msk        (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
44090 #define TIMER_INTSTAT_TMR61INT_Pos        (13UL)                    /*!< TMR61INT (Bit 13)                                     */
44091 #define TIMER_INTSTAT_TMR61INT_Msk        (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
44092 #define TIMER_INTSTAT_TMR60INT_Pos        (12UL)                    /*!< TMR60INT (Bit 12)                                     */
44093 #define TIMER_INTSTAT_TMR60INT_Msk        (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
44094 #define TIMER_INTSTAT_TMR51INT_Pos        (11UL)                    /*!< TMR51INT (Bit 11)                                     */
44095 #define TIMER_INTSTAT_TMR51INT_Msk        (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
44096 #define TIMER_INTSTAT_TMR50INT_Pos        (10UL)                    /*!< TMR50INT (Bit 10)                                     */
44097 #define TIMER_INTSTAT_TMR50INT_Msk        (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
44098 #define TIMER_INTSTAT_TMR41INT_Pos        (9UL)                     /*!< TMR41INT (Bit 9)                                      */
44099 #define TIMER_INTSTAT_TMR41INT_Msk        (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
44100 #define TIMER_INTSTAT_TMR40INT_Pos        (8UL)                     /*!< TMR40INT (Bit 8)                                      */
44101 #define TIMER_INTSTAT_TMR40INT_Msk        (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
44102 #define TIMER_INTSTAT_TMR31INT_Pos        (7UL)                     /*!< TMR31INT (Bit 7)                                      */
44103 #define TIMER_INTSTAT_TMR31INT_Msk        (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
44104 #define TIMER_INTSTAT_TMR30INT_Pos        (6UL)                     /*!< TMR30INT (Bit 6)                                      */
44105 #define TIMER_INTSTAT_TMR30INT_Msk        (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
44106 #define TIMER_INTSTAT_TMR21INT_Pos        (5UL)                     /*!< TMR21INT (Bit 5)                                      */
44107 #define TIMER_INTSTAT_TMR21INT_Msk        (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
44108 #define TIMER_INTSTAT_TMR20INT_Pos        (4UL)                     /*!< TMR20INT (Bit 4)                                      */
44109 #define TIMER_INTSTAT_TMR20INT_Msk        (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
44110 #define TIMER_INTSTAT_TMR11INT_Pos        (3UL)                     /*!< TMR11INT (Bit 3)                                      */
44111 #define TIMER_INTSTAT_TMR11INT_Msk        (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
44112 #define TIMER_INTSTAT_TMR10INT_Pos        (2UL)                     /*!< TMR10INT (Bit 2)                                      */
44113 #define TIMER_INTSTAT_TMR10INT_Msk        (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
44114 #define TIMER_INTSTAT_TMR01INT_Pos        (1UL)                     /*!< TMR01INT (Bit 1)                                      */
44115 #define TIMER_INTSTAT_TMR01INT_Msk        (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
44116 #define TIMER_INTSTAT_TMR00INT_Pos        (0UL)                     /*!< TMR00INT (Bit 0)                                      */
44117 #define TIMER_INTSTAT_TMR00INT_Msk        (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
44118 /* ========================================================  INTCLR  ========================================================= */
44119 #define TIMER_INTCLR_TMR151INT_Pos        (31UL)                    /*!< TMR151INT (Bit 31)                                    */
44120 #define TIMER_INTCLR_TMR151INT_Msk        (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
44121 #define TIMER_INTCLR_TMR150INT_Pos        (30UL)                    /*!< TMR150INT (Bit 30)                                    */
44122 #define TIMER_INTCLR_TMR150INT_Msk        (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
44123 #define TIMER_INTCLR_TMR141INT_Pos        (29UL)                    /*!< TMR141INT (Bit 29)                                    */
44124 #define TIMER_INTCLR_TMR141INT_Msk        (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
44125 #define TIMER_INTCLR_TMR140INT_Pos        (28UL)                    /*!< TMR140INT (Bit 28)                                    */
44126 #define TIMER_INTCLR_TMR140INT_Msk        (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
44127 #define TIMER_INTCLR_TMR131INT_Pos        (27UL)                    /*!< TMR131INT (Bit 27)                                    */
44128 #define TIMER_INTCLR_TMR131INT_Msk        (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
44129 #define TIMER_INTCLR_TMR130INT_Pos        (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44130 #define TIMER_INTCLR_TMR130INT_Msk        (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
44131 #define TIMER_INTCLR_TMR121INT_Pos        (25UL)                    /*!< TMR121INT (Bit 25)                                    */
44132 #define TIMER_INTCLR_TMR121INT_Msk        (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
44133 #define TIMER_INTCLR_TMR120INT_Pos        (24UL)                    /*!< TMR120INT (Bit 24)                                    */
44134 #define TIMER_INTCLR_TMR120INT_Msk        (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
44135 #define TIMER_INTCLR_TMR111INT_Pos        (23UL)                    /*!< TMR111INT (Bit 23)                                    */
44136 #define TIMER_INTCLR_TMR111INT_Msk        (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
44137 #define TIMER_INTCLR_TMR110INT_Pos        (22UL)                    /*!< TMR110INT (Bit 22)                                    */
44138 #define TIMER_INTCLR_TMR110INT_Msk        (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
44139 #define TIMER_INTCLR_TMR101INT_Pos        (21UL)                    /*!< TMR101INT (Bit 21)                                    */
44140 #define TIMER_INTCLR_TMR101INT_Msk        (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
44141 #define TIMER_INTCLR_TMR100INT_Pos        (20UL)                    /*!< TMR100INT (Bit 20)                                    */
44142 #define TIMER_INTCLR_TMR100INT_Msk        (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
44143 #define TIMER_INTCLR_TMR91INT_Pos         (19UL)                    /*!< TMR91INT (Bit 19)                                     */
44144 #define TIMER_INTCLR_TMR91INT_Msk         (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
44145 #define TIMER_INTCLR_TMR90INT_Pos         (18UL)                    /*!< TMR90INT (Bit 18)                                     */
44146 #define TIMER_INTCLR_TMR90INT_Msk         (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
44147 #define TIMER_INTCLR_TMR81INT_Pos         (17UL)                    /*!< TMR81INT (Bit 17)                                     */
44148 #define TIMER_INTCLR_TMR81INT_Msk         (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
44149 #define TIMER_INTCLR_TMR80INT_Pos         (16UL)                    /*!< TMR80INT (Bit 16)                                     */
44150 #define TIMER_INTCLR_TMR80INT_Msk         (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
44151 #define TIMER_INTCLR_TMR71INT_Pos         (15UL)                    /*!< TMR71INT (Bit 15)                                     */
44152 #define TIMER_INTCLR_TMR71INT_Msk         (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
44153 #define TIMER_INTCLR_TMR70INT_Pos         (14UL)                    /*!< TMR70INT (Bit 14)                                     */
44154 #define TIMER_INTCLR_TMR70INT_Msk         (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
44155 #define TIMER_INTCLR_TMR61INT_Pos         (13UL)                    /*!< TMR61INT (Bit 13)                                     */
44156 #define TIMER_INTCLR_TMR61INT_Msk         (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
44157 #define TIMER_INTCLR_TMR60INT_Pos         (12UL)                    /*!< TMR60INT (Bit 12)                                     */
44158 #define TIMER_INTCLR_TMR60INT_Msk         (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
44159 #define TIMER_INTCLR_TMR51INT_Pos         (11UL)                    /*!< TMR51INT (Bit 11)                                     */
44160 #define TIMER_INTCLR_TMR51INT_Msk         (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
44161 #define TIMER_INTCLR_TMR50INT_Pos         (10UL)                    /*!< TMR50INT (Bit 10)                                     */
44162 #define TIMER_INTCLR_TMR50INT_Msk         (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
44163 #define TIMER_INTCLR_TMR41INT_Pos         (9UL)                     /*!< TMR41INT (Bit 9)                                      */
44164 #define TIMER_INTCLR_TMR41INT_Msk         (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
44165 #define TIMER_INTCLR_TMR40INT_Pos         (8UL)                     /*!< TMR40INT (Bit 8)                                      */
44166 #define TIMER_INTCLR_TMR40INT_Msk         (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
44167 #define TIMER_INTCLR_TMR31INT_Pos         (7UL)                     /*!< TMR31INT (Bit 7)                                      */
44168 #define TIMER_INTCLR_TMR31INT_Msk         (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
44169 #define TIMER_INTCLR_TMR30INT_Pos         (6UL)                     /*!< TMR30INT (Bit 6)                                      */
44170 #define TIMER_INTCLR_TMR30INT_Msk         (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
44171 #define TIMER_INTCLR_TMR21INT_Pos         (5UL)                     /*!< TMR21INT (Bit 5)                                      */
44172 #define TIMER_INTCLR_TMR21INT_Msk         (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
44173 #define TIMER_INTCLR_TMR20INT_Pos         (4UL)                     /*!< TMR20INT (Bit 4)                                      */
44174 #define TIMER_INTCLR_TMR20INT_Msk         (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
44175 #define TIMER_INTCLR_TMR11INT_Pos         (3UL)                     /*!< TMR11INT (Bit 3)                                      */
44176 #define TIMER_INTCLR_TMR11INT_Msk         (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
44177 #define TIMER_INTCLR_TMR10INT_Pos         (2UL)                     /*!< TMR10INT (Bit 2)                                      */
44178 #define TIMER_INTCLR_TMR10INT_Msk         (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
44179 #define TIMER_INTCLR_TMR01INT_Pos         (1UL)                     /*!< TMR01INT (Bit 1)                                      */
44180 #define TIMER_INTCLR_TMR01INT_Msk         (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
44181 #define TIMER_INTCLR_TMR00INT_Pos         (0UL)                     /*!< TMR00INT (Bit 0)                                      */
44182 #define TIMER_INTCLR_TMR00INT_Msk         (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
44183 /* ========================================================  INTSET  ========================================================= */
44184 #define TIMER_INTSET_TMR151INT_Pos        (31UL)                    /*!< TMR151INT (Bit 31)                                    */
44185 #define TIMER_INTSET_TMR151INT_Msk        (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
44186 #define TIMER_INTSET_TMR150INT_Pos        (30UL)                    /*!< TMR150INT (Bit 30)                                    */
44187 #define TIMER_INTSET_TMR150INT_Msk        (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
44188 #define TIMER_INTSET_TMR141INT_Pos        (29UL)                    /*!< TMR141INT (Bit 29)                                    */
44189 #define TIMER_INTSET_TMR141INT_Msk        (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
44190 #define TIMER_INTSET_TMR140INT_Pos        (28UL)                    /*!< TMR140INT (Bit 28)                                    */
44191 #define TIMER_INTSET_TMR140INT_Msk        (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
44192 #define TIMER_INTSET_TMR131INT_Pos        (27UL)                    /*!< TMR131INT (Bit 27)                                    */
44193 #define TIMER_INTSET_TMR131INT_Msk        (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
44194 #define TIMER_INTSET_TMR130INT_Pos        (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44195 #define TIMER_INTSET_TMR130INT_Msk        (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
44196 #define TIMER_INTSET_TMR121INT_Pos        (25UL)                    /*!< TMR121INT (Bit 25)                                    */
44197 #define TIMER_INTSET_TMR121INT_Msk        (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
44198 #define TIMER_INTSET_TMR120INT_Pos        (24UL)                    /*!< TMR120INT (Bit 24)                                    */
44199 #define TIMER_INTSET_TMR120INT_Msk        (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
44200 #define TIMER_INTSET_TMR111INT_Pos        (23UL)                    /*!< TMR111INT (Bit 23)                                    */
44201 #define TIMER_INTSET_TMR111INT_Msk        (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
44202 #define TIMER_INTSET_TMR110INT_Pos        (22UL)                    /*!< TMR110INT (Bit 22)                                    */
44203 #define TIMER_INTSET_TMR110INT_Msk        (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
44204 #define TIMER_INTSET_TMR101INT_Pos        (21UL)                    /*!< TMR101INT (Bit 21)                                    */
44205 #define TIMER_INTSET_TMR101INT_Msk        (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
44206 #define TIMER_INTSET_TMR100INT_Pos        (20UL)                    /*!< TMR100INT (Bit 20)                                    */
44207 #define TIMER_INTSET_TMR100INT_Msk        (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
44208 #define TIMER_INTSET_TMR91INT_Pos         (19UL)                    /*!< TMR91INT (Bit 19)                                     */
44209 #define TIMER_INTSET_TMR91INT_Msk         (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
44210 #define TIMER_INTSET_TMR90INT_Pos         (18UL)                    /*!< TMR90INT (Bit 18)                                     */
44211 #define TIMER_INTSET_TMR90INT_Msk         (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
44212 #define TIMER_INTSET_TMR81INT_Pos         (17UL)                    /*!< TMR81INT (Bit 17)                                     */
44213 #define TIMER_INTSET_TMR81INT_Msk         (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
44214 #define TIMER_INTSET_TMR80INT_Pos         (16UL)                    /*!< TMR80INT (Bit 16)                                     */
44215 #define TIMER_INTSET_TMR80INT_Msk         (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
44216 #define TIMER_INTSET_TMR71INT_Pos         (15UL)                    /*!< TMR71INT (Bit 15)                                     */
44217 #define TIMER_INTSET_TMR71INT_Msk         (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
44218 #define TIMER_INTSET_TMR70INT_Pos         (14UL)                    /*!< TMR70INT (Bit 14)                                     */
44219 #define TIMER_INTSET_TMR70INT_Msk         (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
44220 #define TIMER_INTSET_TMR61INT_Pos         (13UL)                    /*!< TMR61INT (Bit 13)                                     */
44221 #define TIMER_INTSET_TMR61INT_Msk         (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
44222 #define TIMER_INTSET_TMR60INT_Pos         (12UL)                    /*!< TMR60INT (Bit 12)                                     */
44223 #define TIMER_INTSET_TMR60INT_Msk         (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
44224 #define TIMER_INTSET_TMR51INT_Pos         (11UL)                    /*!< TMR51INT (Bit 11)                                     */
44225 #define TIMER_INTSET_TMR51INT_Msk         (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
44226 #define TIMER_INTSET_TMR50INT_Pos         (10UL)                    /*!< TMR50INT (Bit 10)                                     */
44227 #define TIMER_INTSET_TMR50INT_Msk         (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
44228 #define TIMER_INTSET_TMR41INT_Pos         (9UL)                     /*!< TMR41INT (Bit 9)                                      */
44229 #define TIMER_INTSET_TMR41INT_Msk         (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
44230 #define TIMER_INTSET_TMR40INT_Pos         (8UL)                     /*!< TMR40INT (Bit 8)                                      */
44231 #define TIMER_INTSET_TMR40INT_Msk         (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
44232 #define TIMER_INTSET_TMR31INT_Pos         (7UL)                     /*!< TMR31INT (Bit 7)                                      */
44233 #define TIMER_INTSET_TMR31INT_Msk         (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
44234 #define TIMER_INTSET_TMR30INT_Pos         (6UL)                     /*!< TMR30INT (Bit 6)                                      */
44235 #define TIMER_INTSET_TMR30INT_Msk         (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
44236 #define TIMER_INTSET_TMR21INT_Pos         (5UL)                     /*!< TMR21INT (Bit 5)                                      */
44237 #define TIMER_INTSET_TMR21INT_Msk         (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
44238 #define TIMER_INTSET_TMR20INT_Pos         (4UL)                     /*!< TMR20INT (Bit 4)                                      */
44239 #define TIMER_INTSET_TMR20INT_Msk         (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
44240 #define TIMER_INTSET_TMR11INT_Pos         (3UL)                     /*!< TMR11INT (Bit 3)                                      */
44241 #define TIMER_INTSET_TMR11INT_Msk         (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
44242 #define TIMER_INTSET_TMR10INT_Pos         (2UL)                     /*!< TMR10INT (Bit 2)                                      */
44243 #define TIMER_INTSET_TMR10INT_Msk         (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
44244 #define TIMER_INTSET_TMR01INT_Pos         (1UL)                     /*!< TMR01INT (Bit 1)                                      */
44245 #define TIMER_INTSET_TMR01INT_Msk         (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
44246 #define TIMER_INTSET_TMR00INT_Pos         (0UL)                     /*!< TMR00INT (Bit 0)                                      */
44247 #define TIMER_INTSET_TMR00INT_Msk         (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
44248 /* ========================================================  OUTCFG0  ======================================================== */
44249 #define TIMER_OUTCFG0_OUTCFG3_Pos         (24UL)                    /*!< OUTCFG3 (Bit 24)                                      */
44250 #define TIMER_OUTCFG0_OUTCFG3_Msk         (0x3f000000UL)            /*!< OUTCFG3 (Bitfield-Mask: 0x3f)                         */
44251 #define TIMER_OUTCFG0_OUTCFG2_Pos         (16UL)                    /*!< OUTCFG2 (Bit 16)                                      */
44252 #define TIMER_OUTCFG0_OUTCFG2_Msk         (0x3f0000UL)              /*!< OUTCFG2 (Bitfield-Mask: 0x3f)                         */
44253 #define TIMER_OUTCFG0_OUTCFG1_Pos         (8UL)                     /*!< OUTCFG1 (Bit 8)                                       */
44254 #define TIMER_OUTCFG0_OUTCFG1_Msk         (0x3f00UL)                /*!< OUTCFG1 (Bitfield-Mask: 0x3f)                         */
44255 #define TIMER_OUTCFG0_OUTCFG0_Pos         (0UL)                     /*!< OUTCFG0 (Bit 0)                                       */
44256 #define TIMER_OUTCFG0_OUTCFG0_Msk         (0x3fUL)                  /*!< OUTCFG0 (Bitfield-Mask: 0x3f)                         */
44257 /* ========================================================  OUTCFG1  ======================================================== */
44258 #define TIMER_OUTCFG1_OUTCFG7_Pos         (24UL)                    /*!< OUTCFG7 (Bit 24)                                      */
44259 #define TIMER_OUTCFG1_OUTCFG7_Msk         (0x3f000000UL)            /*!< OUTCFG7 (Bitfield-Mask: 0x3f)                         */
44260 #define TIMER_OUTCFG1_OUTCFG6_Pos         (16UL)                    /*!< OUTCFG6 (Bit 16)                                      */
44261 #define TIMER_OUTCFG1_OUTCFG6_Msk         (0x3f0000UL)              /*!< OUTCFG6 (Bitfield-Mask: 0x3f)                         */
44262 #define TIMER_OUTCFG1_OUTCFG5_Pos         (8UL)                     /*!< OUTCFG5 (Bit 8)                                       */
44263 #define TIMER_OUTCFG1_OUTCFG5_Msk         (0x3f00UL)                /*!< OUTCFG5 (Bitfield-Mask: 0x3f)                         */
44264 #define TIMER_OUTCFG1_OUTCFG4_Pos         (0UL)                     /*!< OUTCFG4 (Bit 0)                                       */
44265 #define TIMER_OUTCFG1_OUTCFG4_Msk         (0x3fUL)                  /*!< OUTCFG4 (Bitfield-Mask: 0x3f)                         */
44266 /* ========================================================  OUTCFG2  ======================================================== */
44267 #define TIMER_OUTCFG2_OUTCFG11_Pos        (24UL)                    /*!< OUTCFG11 (Bit 24)                                     */
44268 #define TIMER_OUTCFG2_OUTCFG11_Msk        (0x3f000000UL)            /*!< OUTCFG11 (Bitfield-Mask: 0x3f)                        */
44269 #define TIMER_OUTCFG2_OUTCFG10_Pos        (16UL)                    /*!< OUTCFG10 (Bit 16)                                     */
44270 #define TIMER_OUTCFG2_OUTCFG10_Msk        (0x3f0000UL)              /*!< OUTCFG10 (Bitfield-Mask: 0x3f)                        */
44271 #define TIMER_OUTCFG2_OUTCFG9_Pos         (8UL)                     /*!< OUTCFG9 (Bit 8)                                       */
44272 #define TIMER_OUTCFG2_OUTCFG9_Msk         (0x3f00UL)                /*!< OUTCFG9 (Bitfield-Mask: 0x3f)                         */
44273 #define TIMER_OUTCFG2_OUTCFG8_Pos         (0UL)                     /*!< OUTCFG8 (Bit 0)                                       */
44274 #define TIMER_OUTCFG2_OUTCFG8_Msk         (0x3fUL)                  /*!< OUTCFG8 (Bitfield-Mask: 0x3f)                         */
44275 /* ========================================================  OUTCFG3  ======================================================== */
44276 #define TIMER_OUTCFG3_OUTCFG15_Pos        (24UL)                    /*!< OUTCFG15 (Bit 24)                                     */
44277 #define TIMER_OUTCFG3_OUTCFG15_Msk        (0x3f000000UL)            /*!< OUTCFG15 (Bitfield-Mask: 0x3f)                        */
44278 #define TIMER_OUTCFG3_OUTCFG14_Pos        (16UL)                    /*!< OUTCFG14 (Bit 16)                                     */
44279 #define TIMER_OUTCFG3_OUTCFG14_Msk        (0x3f0000UL)              /*!< OUTCFG14 (Bitfield-Mask: 0x3f)                        */
44280 #define TIMER_OUTCFG3_OUTCFG13_Pos        (8UL)                     /*!< OUTCFG13 (Bit 8)                                      */
44281 #define TIMER_OUTCFG3_OUTCFG13_Msk        (0x3f00UL)                /*!< OUTCFG13 (Bitfield-Mask: 0x3f)                        */
44282 #define TIMER_OUTCFG3_OUTCFG12_Pos        (0UL)                     /*!< OUTCFG12 (Bit 0)                                      */
44283 #define TIMER_OUTCFG3_OUTCFG12_Msk        (0x3fUL)                  /*!< OUTCFG12 (Bitfield-Mask: 0x3f)                        */
44284 /* ========================================================  OUTCFG4  ======================================================== */
44285 #define TIMER_OUTCFG4_OUTCFG19_Pos        (24UL)                    /*!< OUTCFG19 (Bit 24)                                     */
44286 #define TIMER_OUTCFG4_OUTCFG19_Msk        (0x3f000000UL)            /*!< OUTCFG19 (Bitfield-Mask: 0x3f)                        */
44287 #define TIMER_OUTCFG4_OUTCFG18_Pos        (16UL)                    /*!< OUTCFG18 (Bit 16)                                     */
44288 #define TIMER_OUTCFG4_OUTCFG18_Msk        (0x3f0000UL)              /*!< OUTCFG18 (Bitfield-Mask: 0x3f)                        */
44289 #define TIMER_OUTCFG4_OUTCFG17_Pos        (8UL)                     /*!< OUTCFG17 (Bit 8)                                      */
44290 #define TIMER_OUTCFG4_OUTCFG17_Msk        (0x3f00UL)                /*!< OUTCFG17 (Bitfield-Mask: 0x3f)                        */
44291 #define TIMER_OUTCFG4_OUTCFG16_Pos        (0UL)                     /*!< OUTCFG16 (Bit 0)                                      */
44292 #define TIMER_OUTCFG4_OUTCFG16_Msk        (0x3fUL)                  /*!< OUTCFG16 (Bitfield-Mask: 0x3f)                        */
44293 /* ========================================================  OUTCFG5  ======================================================== */
44294 #define TIMER_OUTCFG5_OUTCFG23_Pos        (24UL)                    /*!< OUTCFG23 (Bit 24)                                     */
44295 #define TIMER_OUTCFG5_OUTCFG23_Msk        (0x3f000000UL)            /*!< OUTCFG23 (Bitfield-Mask: 0x3f)                        */
44296 #define TIMER_OUTCFG5_OUTCFG22_Pos        (16UL)                    /*!< OUTCFG22 (Bit 16)                                     */
44297 #define TIMER_OUTCFG5_OUTCFG22_Msk        (0x3f0000UL)              /*!< OUTCFG22 (Bitfield-Mask: 0x3f)                        */
44298 #define TIMER_OUTCFG5_OUTCFG21_Pos        (8UL)                     /*!< OUTCFG21 (Bit 8)                                      */
44299 #define TIMER_OUTCFG5_OUTCFG21_Msk        (0x3f00UL)                /*!< OUTCFG21 (Bitfield-Mask: 0x3f)                        */
44300 #define TIMER_OUTCFG5_OUTCFG20_Pos        (0UL)                     /*!< OUTCFG20 (Bit 0)                                      */
44301 #define TIMER_OUTCFG5_OUTCFG20_Msk        (0x3fUL)                  /*!< OUTCFG20 (Bitfield-Mask: 0x3f)                        */
44302 /* ========================================================  OUTCFG6  ======================================================== */
44303 #define TIMER_OUTCFG6_OUTCFG27_Pos        (24UL)                    /*!< OUTCFG27 (Bit 24)                                     */
44304 #define TIMER_OUTCFG6_OUTCFG27_Msk        (0x3f000000UL)            /*!< OUTCFG27 (Bitfield-Mask: 0x3f)                        */
44305 #define TIMER_OUTCFG6_OUTCFG26_Pos        (16UL)                    /*!< OUTCFG26 (Bit 16)                                     */
44306 #define TIMER_OUTCFG6_OUTCFG26_Msk        (0x3f0000UL)              /*!< OUTCFG26 (Bitfield-Mask: 0x3f)                        */
44307 #define TIMER_OUTCFG6_OUTCFG25_Pos        (8UL)                     /*!< OUTCFG25 (Bit 8)                                      */
44308 #define TIMER_OUTCFG6_OUTCFG25_Msk        (0x3f00UL)                /*!< OUTCFG25 (Bitfield-Mask: 0x3f)                        */
44309 #define TIMER_OUTCFG6_OUTCFG24_Pos        (0UL)                     /*!< OUTCFG24 (Bit 0)                                      */
44310 #define TIMER_OUTCFG6_OUTCFG24_Msk        (0x3fUL)                  /*!< OUTCFG24 (Bitfield-Mask: 0x3f)                        */
44311 /* ========================================================  OUTCFG7  ======================================================== */
44312 #define TIMER_OUTCFG7_OUTCFG31_Pos        (24UL)                    /*!< OUTCFG31 (Bit 24)                                     */
44313 #define TIMER_OUTCFG7_OUTCFG31_Msk        (0x3f000000UL)            /*!< OUTCFG31 (Bitfield-Mask: 0x3f)                        */
44314 #define TIMER_OUTCFG7_OUTCFG30_Pos        (16UL)                    /*!< OUTCFG30 (Bit 16)                                     */
44315 #define TIMER_OUTCFG7_OUTCFG30_Msk        (0x3f0000UL)              /*!< OUTCFG30 (Bitfield-Mask: 0x3f)                        */
44316 #define TIMER_OUTCFG7_OUTCFG29_Pos        (8UL)                     /*!< OUTCFG29 (Bit 8)                                      */
44317 #define TIMER_OUTCFG7_OUTCFG29_Msk        (0x3f00UL)                /*!< OUTCFG29 (Bitfield-Mask: 0x3f)                        */
44318 #define TIMER_OUTCFG7_OUTCFG28_Pos        (0UL)                     /*!< OUTCFG28 (Bit 0)                                      */
44319 #define TIMER_OUTCFG7_OUTCFG28_Msk        (0x3fUL)                  /*!< OUTCFG28 (Bitfield-Mask: 0x3f)                        */
44320 /* ========================================================  OUTCFG8  ======================================================== */
44321 #define TIMER_OUTCFG8_OUTCFG35_Pos        (24UL)                    /*!< OUTCFG35 (Bit 24)                                     */
44322 #define TIMER_OUTCFG8_OUTCFG35_Msk        (0x3f000000UL)            /*!< OUTCFG35 (Bitfield-Mask: 0x3f)                        */
44323 #define TIMER_OUTCFG8_OUTCFG34_Pos        (16UL)                    /*!< OUTCFG34 (Bit 16)                                     */
44324 #define TIMER_OUTCFG8_OUTCFG34_Msk        (0x3f0000UL)              /*!< OUTCFG34 (Bitfield-Mask: 0x3f)                        */
44325 #define TIMER_OUTCFG8_OUTCFG33_Pos        (8UL)                     /*!< OUTCFG33 (Bit 8)                                      */
44326 #define TIMER_OUTCFG8_OUTCFG33_Msk        (0x3f00UL)                /*!< OUTCFG33 (Bitfield-Mask: 0x3f)                        */
44327 #define TIMER_OUTCFG8_OUTCFG32_Pos        (0UL)                     /*!< OUTCFG32 (Bit 0)                                      */
44328 #define TIMER_OUTCFG8_OUTCFG32_Msk        (0x3fUL)                  /*!< OUTCFG32 (Bitfield-Mask: 0x3f)                        */
44329 /* ========================================================  OUTCFG9  ======================================================== */
44330 #define TIMER_OUTCFG9_OUTCFG39_Pos        (24UL)                    /*!< OUTCFG39 (Bit 24)                                     */
44331 #define TIMER_OUTCFG9_OUTCFG39_Msk        (0x3f000000UL)            /*!< OUTCFG39 (Bitfield-Mask: 0x3f)                        */
44332 #define TIMER_OUTCFG9_OUTCFG38_Pos        (16UL)                    /*!< OUTCFG38 (Bit 16)                                     */
44333 #define TIMER_OUTCFG9_OUTCFG38_Msk        (0x3f0000UL)              /*!< OUTCFG38 (Bitfield-Mask: 0x3f)                        */
44334 #define TIMER_OUTCFG9_OUTCFG37_Pos        (8UL)                     /*!< OUTCFG37 (Bit 8)                                      */
44335 #define TIMER_OUTCFG9_OUTCFG37_Msk        (0x3f00UL)                /*!< OUTCFG37 (Bitfield-Mask: 0x3f)                        */
44336 #define TIMER_OUTCFG9_OUTCFG36_Pos        (0UL)                     /*!< OUTCFG36 (Bit 0)                                      */
44337 #define TIMER_OUTCFG9_OUTCFG36_Msk        (0x3fUL)                  /*!< OUTCFG36 (Bitfield-Mask: 0x3f)                        */
44338 /* =======================================================  OUTCFG10  ======================================================== */
44339 #define TIMER_OUTCFG10_OUTCFG43_Pos       (24UL)                    /*!< OUTCFG43 (Bit 24)                                     */
44340 #define TIMER_OUTCFG10_OUTCFG43_Msk       (0x3f000000UL)            /*!< OUTCFG43 (Bitfield-Mask: 0x3f)                        */
44341 #define TIMER_OUTCFG10_OUTCFG42_Pos       (16UL)                    /*!< OUTCFG42 (Bit 16)                                     */
44342 #define TIMER_OUTCFG10_OUTCFG42_Msk       (0x3f0000UL)              /*!< OUTCFG42 (Bitfield-Mask: 0x3f)                        */
44343 #define TIMER_OUTCFG10_OUTCFG41_Pos       (8UL)                     /*!< OUTCFG41 (Bit 8)                                      */
44344 #define TIMER_OUTCFG10_OUTCFG41_Msk       (0x3f00UL)                /*!< OUTCFG41 (Bitfield-Mask: 0x3f)                        */
44345 #define TIMER_OUTCFG10_OUTCFG40_Pos       (0UL)                     /*!< OUTCFG40 (Bit 0)                                      */
44346 #define TIMER_OUTCFG10_OUTCFG40_Msk       (0x3fUL)                  /*!< OUTCFG40 (Bitfield-Mask: 0x3f)                        */
44347 /* =======================================================  OUTCFG11  ======================================================== */
44348 #define TIMER_OUTCFG11_OUTCFG47_Pos       (24UL)                    /*!< OUTCFG47 (Bit 24)                                     */
44349 #define TIMER_OUTCFG11_OUTCFG47_Msk       (0x3f000000UL)            /*!< OUTCFG47 (Bitfield-Mask: 0x3f)                        */
44350 #define TIMER_OUTCFG11_OUTCFG46_Pos       (16UL)                    /*!< OUTCFG46 (Bit 16)                                     */
44351 #define TIMER_OUTCFG11_OUTCFG46_Msk       (0x3f0000UL)              /*!< OUTCFG46 (Bitfield-Mask: 0x3f)                        */
44352 #define TIMER_OUTCFG11_OUTCFG45_Pos       (8UL)                     /*!< OUTCFG45 (Bit 8)                                      */
44353 #define TIMER_OUTCFG11_OUTCFG45_Msk       (0x3f00UL)                /*!< OUTCFG45 (Bitfield-Mask: 0x3f)                        */
44354 #define TIMER_OUTCFG11_OUTCFG44_Pos       (0UL)                     /*!< OUTCFG44 (Bit 0)                                      */
44355 #define TIMER_OUTCFG11_OUTCFG44_Msk       (0x3fUL)                  /*!< OUTCFG44 (Bitfield-Mask: 0x3f)                        */
44356 /* =======================================================  OUTCFG12  ======================================================== */
44357 #define TIMER_OUTCFG12_OUTCFG51_Pos       (24UL)                    /*!< OUTCFG51 (Bit 24)                                     */
44358 #define TIMER_OUTCFG12_OUTCFG51_Msk       (0x3f000000UL)            /*!< OUTCFG51 (Bitfield-Mask: 0x3f)                        */
44359 #define TIMER_OUTCFG12_OUTCFG50_Pos       (16UL)                    /*!< OUTCFG50 (Bit 16)                                     */
44360 #define TIMER_OUTCFG12_OUTCFG50_Msk       (0x3f0000UL)              /*!< OUTCFG50 (Bitfield-Mask: 0x3f)                        */
44361 #define TIMER_OUTCFG12_OUTCFG49_Pos       (8UL)                     /*!< OUTCFG49 (Bit 8)                                      */
44362 #define TIMER_OUTCFG12_OUTCFG49_Msk       (0x3f00UL)                /*!< OUTCFG49 (Bitfield-Mask: 0x3f)                        */
44363 #define TIMER_OUTCFG12_OUTCFG48_Pos       (0UL)                     /*!< OUTCFG48 (Bit 0)                                      */
44364 #define TIMER_OUTCFG12_OUTCFG48_Msk       (0x3fUL)                  /*!< OUTCFG48 (Bitfield-Mask: 0x3f)                        */
44365 /* =======================================================  OUTCFG13  ======================================================== */
44366 #define TIMER_OUTCFG13_OUTCFG55_Pos       (24UL)                    /*!< OUTCFG55 (Bit 24)                                     */
44367 #define TIMER_OUTCFG13_OUTCFG55_Msk       (0x3f000000UL)            /*!< OUTCFG55 (Bitfield-Mask: 0x3f)                        */
44368 #define TIMER_OUTCFG13_OUTCFG54_Pos       (16UL)                    /*!< OUTCFG54 (Bit 16)                                     */
44369 #define TIMER_OUTCFG13_OUTCFG54_Msk       (0x3f0000UL)              /*!< OUTCFG54 (Bitfield-Mask: 0x3f)                        */
44370 #define TIMER_OUTCFG13_OUTCFG53_Pos       (8UL)                     /*!< OUTCFG53 (Bit 8)                                      */
44371 #define TIMER_OUTCFG13_OUTCFG53_Msk       (0x3f00UL)                /*!< OUTCFG53 (Bitfield-Mask: 0x3f)                        */
44372 #define TIMER_OUTCFG13_OUTCFG52_Pos       (0UL)                     /*!< OUTCFG52 (Bit 0)                                      */
44373 #define TIMER_OUTCFG13_OUTCFG52_Msk       (0x3fUL)                  /*!< OUTCFG52 (Bitfield-Mask: 0x3f)                        */
44374 /* =======================================================  OUTCFG14  ======================================================== */
44375 #define TIMER_OUTCFG14_OUTCFG59_Pos       (24UL)                    /*!< OUTCFG59 (Bit 24)                                     */
44376 #define TIMER_OUTCFG14_OUTCFG59_Msk       (0x3f000000UL)            /*!< OUTCFG59 (Bitfield-Mask: 0x3f)                        */
44377 #define TIMER_OUTCFG14_OUTCFG58_Pos       (16UL)                    /*!< OUTCFG58 (Bit 16)                                     */
44378 #define TIMER_OUTCFG14_OUTCFG58_Msk       (0x3f0000UL)              /*!< OUTCFG58 (Bitfield-Mask: 0x3f)                        */
44379 #define TIMER_OUTCFG14_OUTCFG57_Pos       (8UL)                     /*!< OUTCFG57 (Bit 8)                                      */
44380 #define TIMER_OUTCFG14_OUTCFG57_Msk       (0x3f00UL)                /*!< OUTCFG57 (Bitfield-Mask: 0x3f)                        */
44381 #define TIMER_OUTCFG14_OUTCFG56_Pos       (0UL)                     /*!< OUTCFG56 (Bit 0)                                      */
44382 #define TIMER_OUTCFG14_OUTCFG56_Msk       (0x3fUL)                  /*!< OUTCFG56 (Bitfield-Mask: 0x3f)                        */
44383 /* =======================================================  OUTCFG15  ======================================================== */
44384 #define TIMER_OUTCFG15_OUTCFG63_Pos       (24UL)                    /*!< OUTCFG63 (Bit 24)                                     */
44385 #define TIMER_OUTCFG15_OUTCFG63_Msk       (0x3f000000UL)            /*!< OUTCFG63 (Bitfield-Mask: 0x3f)                        */
44386 #define TIMER_OUTCFG15_OUTCFG62_Pos       (16UL)                    /*!< OUTCFG62 (Bit 16)                                     */
44387 #define TIMER_OUTCFG15_OUTCFG62_Msk       (0x3f0000UL)              /*!< OUTCFG62 (Bitfield-Mask: 0x3f)                        */
44388 #define TIMER_OUTCFG15_OUTCFG61_Pos       (8UL)                     /*!< OUTCFG61 (Bit 8)                                      */
44389 #define TIMER_OUTCFG15_OUTCFG61_Msk       (0x3f00UL)                /*!< OUTCFG61 (Bitfield-Mask: 0x3f)                        */
44390 #define TIMER_OUTCFG15_OUTCFG60_Pos       (0UL)                     /*!< OUTCFG60 (Bit 0)                                      */
44391 #define TIMER_OUTCFG15_OUTCFG60_Msk       (0x3fUL)                  /*!< OUTCFG60 (Bitfield-Mask: 0x3f)                        */
44392 /* =======================================================  OUTCFG16  ======================================================== */
44393 #define TIMER_OUTCFG16_OUTCFG67_Pos       (24UL)                    /*!< OUTCFG67 (Bit 24)                                     */
44394 #define TIMER_OUTCFG16_OUTCFG67_Msk       (0x3f000000UL)            /*!< OUTCFG67 (Bitfield-Mask: 0x3f)                        */
44395 #define TIMER_OUTCFG16_OUTCFG66_Pos       (16UL)                    /*!< OUTCFG66 (Bit 16)                                     */
44396 #define TIMER_OUTCFG16_OUTCFG66_Msk       (0x3f0000UL)              /*!< OUTCFG66 (Bitfield-Mask: 0x3f)                        */
44397 #define TIMER_OUTCFG16_OUTCFG65_Pos       (8UL)                     /*!< OUTCFG65 (Bit 8)                                      */
44398 #define TIMER_OUTCFG16_OUTCFG65_Msk       (0x3f00UL)                /*!< OUTCFG65 (Bitfield-Mask: 0x3f)                        */
44399 #define TIMER_OUTCFG16_OUTCFG64_Pos       (0UL)                     /*!< OUTCFG64 (Bit 0)                                      */
44400 #define TIMER_OUTCFG16_OUTCFG64_Msk       (0x3fUL)                  /*!< OUTCFG64 (Bitfield-Mask: 0x3f)                        */
44401 /* =======================================================  OUTCFG17  ======================================================== */
44402 #define TIMER_OUTCFG17_OUTCFG71_Pos       (24UL)                    /*!< OUTCFG71 (Bit 24)                                     */
44403 #define TIMER_OUTCFG17_OUTCFG71_Msk       (0x3f000000UL)            /*!< OUTCFG71 (Bitfield-Mask: 0x3f)                        */
44404 #define TIMER_OUTCFG17_OUTCFG70_Pos       (16UL)                    /*!< OUTCFG70 (Bit 16)                                     */
44405 #define TIMER_OUTCFG17_OUTCFG70_Msk       (0x3f0000UL)              /*!< OUTCFG70 (Bitfield-Mask: 0x3f)                        */
44406 #define TIMER_OUTCFG17_OUTCFG69_Pos       (8UL)                     /*!< OUTCFG69 (Bit 8)                                      */
44407 #define TIMER_OUTCFG17_OUTCFG69_Msk       (0x3f00UL)                /*!< OUTCFG69 (Bitfield-Mask: 0x3f)                        */
44408 #define TIMER_OUTCFG17_OUTCFG68_Pos       (0UL)                     /*!< OUTCFG68 (Bit 0)                                      */
44409 #define TIMER_OUTCFG17_OUTCFG68_Msk       (0x3fUL)                  /*!< OUTCFG68 (Bitfield-Mask: 0x3f)                        */
44410 /* =======================================================  OUTCFG18  ======================================================== */
44411 #define TIMER_OUTCFG18_OUTCFG75_Pos       (24UL)                    /*!< OUTCFG75 (Bit 24)                                     */
44412 #define TIMER_OUTCFG18_OUTCFG75_Msk       (0x3f000000UL)            /*!< OUTCFG75 (Bitfield-Mask: 0x3f)                        */
44413 #define TIMER_OUTCFG18_OUTCFG74_Pos       (16UL)                    /*!< OUTCFG74 (Bit 16)                                     */
44414 #define TIMER_OUTCFG18_OUTCFG74_Msk       (0x3f0000UL)              /*!< OUTCFG74 (Bitfield-Mask: 0x3f)                        */
44415 #define TIMER_OUTCFG18_OUTCFG73_Pos       (8UL)                     /*!< OUTCFG73 (Bit 8)                                      */
44416 #define TIMER_OUTCFG18_OUTCFG73_Msk       (0x3f00UL)                /*!< OUTCFG73 (Bitfield-Mask: 0x3f)                        */
44417 #define TIMER_OUTCFG18_OUTCFG72_Pos       (0UL)                     /*!< OUTCFG72 (Bit 0)                                      */
44418 #define TIMER_OUTCFG18_OUTCFG72_Msk       (0x3fUL)                  /*!< OUTCFG72 (Bitfield-Mask: 0x3f)                        */
44419 /* =======================================================  OUTCFG19  ======================================================== */
44420 #define TIMER_OUTCFG19_OUTCFG79_Pos       (24UL)                    /*!< OUTCFG79 (Bit 24)                                     */
44421 #define TIMER_OUTCFG19_OUTCFG79_Msk       (0x3f000000UL)            /*!< OUTCFG79 (Bitfield-Mask: 0x3f)                        */
44422 #define TIMER_OUTCFG19_OUTCFG78_Pos       (16UL)                    /*!< OUTCFG78 (Bit 16)                                     */
44423 #define TIMER_OUTCFG19_OUTCFG78_Msk       (0x3f0000UL)              /*!< OUTCFG78 (Bitfield-Mask: 0x3f)                        */
44424 #define TIMER_OUTCFG19_OUTCFG77_Pos       (8UL)                     /*!< OUTCFG77 (Bit 8)                                      */
44425 #define TIMER_OUTCFG19_OUTCFG77_Msk       (0x3f00UL)                /*!< OUTCFG77 (Bitfield-Mask: 0x3f)                        */
44426 #define TIMER_OUTCFG19_OUTCFG76_Pos       (0UL)                     /*!< OUTCFG76 (Bit 0)                                      */
44427 #define TIMER_OUTCFG19_OUTCFG76_Msk       (0x3fUL)                  /*!< OUTCFG76 (Bitfield-Mask: 0x3f)                        */
44428 /* =======================================================  OUTCFG20  ======================================================== */
44429 #define TIMER_OUTCFG20_OUTCFG83_Pos       (24UL)                    /*!< OUTCFG83 (Bit 24)                                     */
44430 #define TIMER_OUTCFG20_OUTCFG83_Msk       (0x3f000000UL)            /*!< OUTCFG83 (Bitfield-Mask: 0x3f)                        */
44431 #define TIMER_OUTCFG20_OUTCFG82_Pos       (16UL)                    /*!< OUTCFG82 (Bit 16)                                     */
44432 #define TIMER_OUTCFG20_OUTCFG82_Msk       (0x3f0000UL)              /*!< OUTCFG82 (Bitfield-Mask: 0x3f)                        */
44433 #define TIMER_OUTCFG20_OUTCFG81_Pos       (8UL)                     /*!< OUTCFG81 (Bit 8)                                      */
44434 #define TIMER_OUTCFG20_OUTCFG81_Msk       (0x3f00UL)                /*!< OUTCFG81 (Bitfield-Mask: 0x3f)                        */
44435 #define TIMER_OUTCFG20_OUTCFG80_Pos       (0UL)                     /*!< OUTCFG80 (Bit 0)                                      */
44436 #define TIMER_OUTCFG20_OUTCFG80_Msk       (0x3fUL)                  /*!< OUTCFG80 (Bitfield-Mask: 0x3f)                        */
44437 /* =======================================================  OUTCFG21  ======================================================== */
44438 #define TIMER_OUTCFG21_OUTCFG87_Pos       (24UL)                    /*!< OUTCFG87 (Bit 24)                                     */
44439 #define TIMER_OUTCFG21_OUTCFG87_Msk       (0x3f000000UL)            /*!< OUTCFG87 (Bitfield-Mask: 0x3f)                        */
44440 #define TIMER_OUTCFG21_OUTCFG86_Pos       (16UL)                    /*!< OUTCFG86 (Bit 16)                                     */
44441 #define TIMER_OUTCFG21_OUTCFG86_Msk       (0x3f0000UL)              /*!< OUTCFG86 (Bitfield-Mask: 0x3f)                        */
44442 #define TIMER_OUTCFG21_OUTCFG85_Pos       (8UL)                     /*!< OUTCFG85 (Bit 8)                                      */
44443 #define TIMER_OUTCFG21_OUTCFG85_Msk       (0x3f00UL)                /*!< OUTCFG85 (Bitfield-Mask: 0x3f)                        */
44444 #define TIMER_OUTCFG21_OUTCFG84_Pos       (0UL)                     /*!< OUTCFG84 (Bit 0)                                      */
44445 #define TIMER_OUTCFG21_OUTCFG84_Msk       (0x3fUL)                  /*!< OUTCFG84 (Bitfield-Mask: 0x3f)                        */
44446 /* =======================================================  OUTCFG22  ======================================================== */
44447 #define TIMER_OUTCFG22_OUTCFG91_Pos       (24UL)                    /*!< OUTCFG91 (Bit 24)                                     */
44448 #define TIMER_OUTCFG22_OUTCFG91_Msk       (0x3f000000UL)            /*!< OUTCFG91 (Bitfield-Mask: 0x3f)                        */
44449 #define TIMER_OUTCFG22_OUTCFG90_Pos       (16UL)                    /*!< OUTCFG90 (Bit 16)                                     */
44450 #define TIMER_OUTCFG22_OUTCFG90_Msk       (0x3f0000UL)              /*!< OUTCFG90 (Bitfield-Mask: 0x3f)                        */
44451 #define TIMER_OUTCFG22_OUTCFG89_Pos       (8UL)                     /*!< OUTCFG89 (Bit 8)                                      */
44452 #define TIMER_OUTCFG22_OUTCFG89_Msk       (0x3f00UL)                /*!< OUTCFG89 (Bitfield-Mask: 0x3f)                        */
44453 #define TIMER_OUTCFG22_OUTCFG88_Pos       (0UL)                     /*!< OUTCFG88 (Bit 0)                                      */
44454 #define TIMER_OUTCFG22_OUTCFG88_Msk       (0x3fUL)                  /*!< OUTCFG88 (Bitfield-Mask: 0x3f)                        */
44455 /* =======================================================  OUTCFG23  ======================================================== */
44456 #define TIMER_OUTCFG23_OUTCFG95_Pos       (24UL)                    /*!< OUTCFG95 (Bit 24)                                     */
44457 #define TIMER_OUTCFG23_OUTCFG95_Msk       (0x3f000000UL)            /*!< OUTCFG95 (Bitfield-Mask: 0x3f)                        */
44458 #define TIMER_OUTCFG23_OUTCFG94_Pos       (16UL)                    /*!< OUTCFG94 (Bit 16)                                     */
44459 #define TIMER_OUTCFG23_OUTCFG94_Msk       (0x3f0000UL)              /*!< OUTCFG94 (Bitfield-Mask: 0x3f)                        */
44460 #define TIMER_OUTCFG23_OUTCFG93_Pos       (8UL)                     /*!< OUTCFG93 (Bit 8)                                      */
44461 #define TIMER_OUTCFG23_OUTCFG93_Msk       (0x3f00UL)                /*!< OUTCFG93 (Bitfield-Mask: 0x3f)                        */
44462 #define TIMER_OUTCFG23_OUTCFG92_Pos       (0UL)                     /*!< OUTCFG92 (Bit 0)                                      */
44463 #define TIMER_OUTCFG23_OUTCFG92_Msk       (0x3fUL)                  /*!< OUTCFG92 (Bitfield-Mask: 0x3f)                        */
44464 /* =======================================================  OUTCFG24  ======================================================== */
44465 #define TIMER_OUTCFG24_OUTCFG99_Pos       (24UL)                    /*!< OUTCFG99 (Bit 24)                                     */
44466 #define TIMER_OUTCFG24_OUTCFG99_Msk       (0x3f000000UL)            /*!< OUTCFG99 (Bitfield-Mask: 0x3f)                        */
44467 #define TIMER_OUTCFG24_OUTCFG98_Pos       (16UL)                    /*!< OUTCFG98 (Bit 16)                                     */
44468 #define TIMER_OUTCFG24_OUTCFG98_Msk       (0x3f0000UL)              /*!< OUTCFG98 (Bitfield-Mask: 0x3f)                        */
44469 #define TIMER_OUTCFG24_OUTCFG97_Pos       (8UL)                     /*!< OUTCFG97 (Bit 8)                                      */
44470 #define TIMER_OUTCFG24_OUTCFG97_Msk       (0x3f00UL)                /*!< OUTCFG97 (Bitfield-Mask: 0x3f)                        */
44471 #define TIMER_OUTCFG24_OUTCFG96_Pos       (0UL)                     /*!< OUTCFG96 (Bit 0)                                      */
44472 #define TIMER_OUTCFG24_OUTCFG96_Msk       (0x3fUL)                  /*!< OUTCFG96 (Bitfield-Mask: 0x3f)                        */
44473 /* =======================================================  OUTCFG25  ======================================================== */
44474 #define TIMER_OUTCFG25_OUTCFG103_Pos      (24UL)                    /*!< OUTCFG103 (Bit 24)                                    */
44475 #define TIMER_OUTCFG25_OUTCFG103_Msk      (0x3f000000UL)            /*!< OUTCFG103 (Bitfield-Mask: 0x3f)                       */
44476 #define TIMER_OUTCFG25_OUTCFG102_Pos      (16UL)                    /*!< OUTCFG102 (Bit 16)                                    */
44477 #define TIMER_OUTCFG25_OUTCFG102_Msk      (0x3f0000UL)              /*!< OUTCFG102 (Bitfield-Mask: 0x3f)                       */
44478 #define TIMER_OUTCFG25_OUTCFG101_Pos      (8UL)                     /*!< OUTCFG101 (Bit 8)                                     */
44479 #define TIMER_OUTCFG25_OUTCFG101_Msk      (0x3f00UL)                /*!< OUTCFG101 (Bitfield-Mask: 0x3f)                       */
44480 #define TIMER_OUTCFG25_OUTCFG100_Pos      (0UL)                     /*!< OUTCFG100 (Bit 0)                                     */
44481 #define TIMER_OUTCFG25_OUTCFG100_Msk      (0x3fUL)                  /*!< OUTCFG100 (Bitfield-Mask: 0x3f)                       */
44482 /* =======================================================  OUTCFG26  ======================================================== */
44483 #define TIMER_OUTCFG26_OUTCFG107_Pos      (24UL)                    /*!< OUTCFG107 (Bit 24)                                    */
44484 #define TIMER_OUTCFG26_OUTCFG107_Msk      (0x3f000000UL)            /*!< OUTCFG107 (Bitfield-Mask: 0x3f)                       */
44485 #define TIMER_OUTCFG26_OUTCFG106_Pos      (16UL)                    /*!< OUTCFG106 (Bit 16)                                    */
44486 #define TIMER_OUTCFG26_OUTCFG106_Msk      (0x3f0000UL)              /*!< OUTCFG106 (Bitfield-Mask: 0x3f)                       */
44487 #define TIMER_OUTCFG26_OUTCFG105_Pos      (8UL)                     /*!< OUTCFG105 (Bit 8)                                     */
44488 #define TIMER_OUTCFG26_OUTCFG105_Msk      (0x3f00UL)                /*!< OUTCFG105 (Bitfield-Mask: 0x3f)                       */
44489 #define TIMER_OUTCFG26_OUTCFG104_Pos      (0UL)                     /*!< OUTCFG104 (Bit 0)                                     */
44490 #define TIMER_OUTCFG26_OUTCFG104_Msk      (0x3fUL)                  /*!< OUTCFG104 (Bitfield-Mask: 0x3f)                       */
44491 /* =======================================================  OUTCFG27  ======================================================== */
44492 #define TIMER_OUTCFG27_OUTCFG111_Pos      (24UL)                    /*!< OUTCFG111 (Bit 24)                                    */
44493 #define TIMER_OUTCFG27_OUTCFG111_Msk      (0x3f000000UL)            /*!< OUTCFG111 (Bitfield-Mask: 0x3f)                       */
44494 #define TIMER_OUTCFG27_OUTCFG110_Pos      (16UL)                    /*!< OUTCFG110 (Bit 16)                                    */
44495 #define TIMER_OUTCFG27_OUTCFG110_Msk      (0x3f0000UL)              /*!< OUTCFG110 (Bitfield-Mask: 0x3f)                       */
44496 #define TIMER_OUTCFG27_OUTCFG109_Pos      (8UL)                     /*!< OUTCFG109 (Bit 8)                                     */
44497 #define TIMER_OUTCFG27_OUTCFG109_Msk      (0x3f00UL)                /*!< OUTCFG109 (Bitfield-Mask: 0x3f)                       */
44498 #define TIMER_OUTCFG27_OUTCFG108_Pos      (0UL)                     /*!< OUTCFG108 (Bit 0)                                     */
44499 #define TIMER_OUTCFG27_OUTCFG108_Msk      (0x3fUL)                  /*!< OUTCFG108 (Bitfield-Mask: 0x3f)                       */
44500 /* =======================================================  OUTCFG28  ======================================================== */
44501 #define TIMER_OUTCFG28_OUTCFG115_Pos      (24UL)                    /*!< OUTCFG115 (Bit 24)                                    */
44502 #define TIMER_OUTCFG28_OUTCFG115_Msk      (0x3f000000UL)            /*!< OUTCFG115 (Bitfield-Mask: 0x3f)                       */
44503 #define TIMER_OUTCFG28_OUTCFG114_Pos      (16UL)                    /*!< OUTCFG114 (Bit 16)                                    */
44504 #define TIMER_OUTCFG28_OUTCFG114_Msk      (0x3f0000UL)              /*!< OUTCFG114 (Bitfield-Mask: 0x3f)                       */
44505 #define TIMER_OUTCFG28_OUTCFG113_Pos      (8UL)                     /*!< OUTCFG113 (Bit 8)                                     */
44506 #define TIMER_OUTCFG28_OUTCFG113_Msk      (0x3f00UL)                /*!< OUTCFG113 (Bitfield-Mask: 0x3f)                       */
44507 #define TIMER_OUTCFG28_OUTCFG112_Pos      (0UL)                     /*!< OUTCFG112 (Bit 0)                                     */
44508 #define TIMER_OUTCFG28_OUTCFG112_Msk      (0x3fUL)                  /*!< OUTCFG112 (Bitfield-Mask: 0x3f)                       */
44509 /* =======================================================  OUTCFG29  ======================================================== */
44510 #define TIMER_OUTCFG29_OUTCFG119_Pos      (24UL)                    /*!< OUTCFG119 (Bit 24)                                    */
44511 #define TIMER_OUTCFG29_OUTCFG119_Msk      (0x3f000000UL)            /*!< OUTCFG119 (Bitfield-Mask: 0x3f)                       */
44512 #define TIMER_OUTCFG29_OUTCFG118_Pos      (16UL)                    /*!< OUTCFG118 (Bit 16)                                    */
44513 #define TIMER_OUTCFG29_OUTCFG118_Msk      (0x3f0000UL)              /*!< OUTCFG118 (Bitfield-Mask: 0x3f)                       */
44514 #define TIMER_OUTCFG29_OUTCFG117_Pos      (8UL)                     /*!< OUTCFG117 (Bit 8)                                     */
44515 #define TIMER_OUTCFG29_OUTCFG117_Msk      (0x3f00UL)                /*!< OUTCFG117 (Bitfield-Mask: 0x3f)                       */
44516 #define TIMER_OUTCFG29_OUTCFG116_Pos      (0UL)                     /*!< OUTCFG116 (Bit 0)                                     */
44517 #define TIMER_OUTCFG29_OUTCFG116_Msk      (0x3fUL)                  /*!< OUTCFG116 (Bitfield-Mask: 0x3f)                       */
44518 /* =======================================================  OUTCFG30  ======================================================== */
44519 #define TIMER_OUTCFG30_OUTCFG123_Pos      (24UL)                    /*!< OUTCFG123 (Bit 24)                                    */
44520 #define TIMER_OUTCFG30_OUTCFG123_Msk      (0x3f000000UL)            /*!< OUTCFG123 (Bitfield-Mask: 0x3f)                       */
44521 #define TIMER_OUTCFG30_OUTCFG122_Pos      (16UL)                    /*!< OUTCFG122 (Bit 16)                                    */
44522 #define TIMER_OUTCFG30_OUTCFG122_Msk      (0x3f0000UL)              /*!< OUTCFG122 (Bitfield-Mask: 0x3f)                       */
44523 #define TIMER_OUTCFG30_OUTCFG121_Pos      (8UL)                     /*!< OUTCFG121 (Bit 8)                                     */
44524 #define TIMER_OUTCFG30_OUTCFG121_Msk      (0x3f00UL)                /*!< OUTCFG121 (Bitfield-Mask: 0x3f)                       */
44525 #define TIMER_OUTCFG30_OUTCFG120_Pos      (0UL)                     /*!< OUTCFG120 (Bit 0)                                     */
44526 #define TIMER_OUTCFG30_OUTCFG120_Msk      (0x3fUL)                  /*!< OUTCFG120 (Bitfield-Mask: 0x3f)                       */
44527 /* =======================================================  OUTCFG31  ======================================================== */
44528 #define TIMER_OUTCFG31_OUTCFG127_Pos      (24UL)                    /*!< OUTCFG127 (Bit 24)                                    */
44529 #define TIMER_OUTCFG31_OUTCFG127_Msk      (0x3f000000UL)            /*!< OUTCFG127 (Bitfield-Mask: 0x3f)                       */
44530 #define TIMER_OUTCFG31_OUTCFG126_Pos      (16UL)                    /*!< OUTCFG126 (Bit 16)                                    */
44531 #define TIMER_OUTCFG31_OUTCFG126_Msk      (0x3f0000UL)              /*!< OUTCFG126 (Bitfield-Mask: 0x3f)                       */
44532 #define TIMER_OUTCFG31_OUTCFG125_Pos      (8UL)                     /*!< OUTCFG125 (Bit 8)                                     */
44533 #define TIMER_OUTCFG31_OUTCFG125_Msk      (0x3f00UL)                /*!< OUTCFG125 (Bitfield-Mask: 0x3f)                       */
44534 #define TIMER_OUTCFG31_OUTCFG124_Pos      (0UL)                     /*!< OUTCFG124 (Bit 0)                                     */
44535 #define TIMER_OUTCFG31_OUTCFG124_Msk      (0x3fUL)                  /*!< OUTCFG124 (Bitfield-Mask: 0x3f)                       */
44536 /* =========================================================  AUXEN  ========================================================= */
44537 #define TIMER_AUXEN_STMREN_Pos            (16UL)                    /*!< STMREN (Bit 16)                                       */
44538 #define TIMER_AUXEN_STMREN_Msk            (0x10000UL)               /*!< STMREN (Bitfield-Mask: 0x01)                          */
44539 #define TIMER_AUXEN_TMR15EN_Pos           (15UL)                    /*!< TMR15EN (Bit 15)                                      */
44540 #define TIMER_AUXEN_TMR15EN_Msk           (0x8000UL)                /*!< TMR15EN (Bitfield-Mask: 0x01)                         */
44541 #define TIMER_AUXEN_TMR14EN_Pos           (14UL)                    /*!< TMR14EN (Bit 14)                                      */
44542 #define TIMER_AUXEN_TMR14EN_Msk           (0x4000UL)                /*!< TMR14EN (Bitfield-Mask: 0x01)                         */
44543 #define TIMER_AUXEN_TMR13EN_Pos           (13UL)                    /*!< TMR13EN (Bit 13)                                      */
44544 #define TIMER_AUXEN_TMR13EN_Msk           (0x2000UL)                /*!< TMR13EN (Bitfield-Mask: 0x01)                         */
44545 #define TIMER_AUXEN_TMR12EN_Pos           (12UL)                    /*!< TMR12EN (Bit 12)                                      */
44546 #define TIMER_AUXEN_TMR12EN_Msk           (0x1000UL)                /*!< TMR12EN (Bitfield-Mask: 0x01)                         */
44547 #define TIMER_AUXEN_TMR11EN_Pos           (11UL)                    /*!< TMR11EN (Bit 11)                                      */
44548 #define TIMER_AUXEN_TMR11EN_Msk           (0x800UL)                 /*!< TMR11EN (Bitfield-Mask: 0x01)                         */
44549 #define TIMER_AUXEN_TMR10EN_Pos           (10UL)                    /*!< TMR10EN (Bit 10)                                      */
44550 #define TIMER_AUXEN_TMR10EN_Msk           (0x400UL)                 /*!< TMR10EN (Bitfield-Mask: 0x01)                         */
44551 #define TIMER_AUXEN_TMR09EN_Pos           (9UL)                     /*!< TMR09EN (Bit 9)                                       */
44552 #define TIMER_AUXEN_TMR09EN_Msk           (0x200UL)                 /*!< TMR09EN (Bitfield-Mask: 0x01)                         */
44553 #define TIMER_AUXEN_TMR08EN_Pos           (8UL)                     /*!< TMR08EN (Bit 8)                                       */
44554 #define TIMER_AUXEN_TMR08EN_Msk           (0x100UL)                 /*!< TMR08EN (Bitfield-Mask: 0x01)                         */
44555 #define TIMER_AUXEN_TMR07EN_Pos           (7UL)                     /*!< TMR07EN (Bit 7)                                       */
44556 #define TIMER_AUXEN_TMR07EN_Msk           (0x80UL)                  /*!< TMR07EN (Bitfield-Mask: 0x01)                         */
44557 #define TIMER_AUXEN_TMR06EN_Pos           (6UL)                     /*!< TMR06EN (Bit 6)                                       */
44558 #define TIMER_AUXEN_TMR06EN_Msk           (0x40UL)                  /*!< TMR06EN (Bitfield-Mask: 0x01)                         */
44559 #define TIMER_AUXEN_TMR05EN_Pos           (5UL)                     /*!< TMR05EN (Bit 5)                                       */
44560 #define TIMER_AUXEN_TMR05EN_Msk           (0x20UL)                  /*!< TMR05EN (Bitfield-Mask: 0x01)                         */
44561 #define TIMER_AUXEN_TMR04EN_Pos           (4UL)                     /*!< TMR04EN (Bit 4)                                       */
44562 #define TIMER_AUXEN_TMR04EN_Msk           (0x10UL)                  /*!< TMR04EN (Bitfield-Mask: 0x01)                         */
44563 #define TIMER_AUXEN_TMR03EN_Pos           (3UL)                     /*!< TMR03EN (Bit 3)                                       */
44564 #define TIMER_AUXEN_TMR03EN_Msk           (0x8UL)                   /*!< TMR03EN (Bitfield-Mask: 0x01)                         */
44565 #define TIMER_AUXEN_TMR02EN_Pos           (2UL)                     /*!< TMR02EN (Bit 2)                                       */
44566 #define TIMER_AUXEN_TMR02EN_Msk           (0x4UL)                   /*!< TMR02EN (Bitfield-Mask: 0x01)                         */
44567 #define TIMER_AUXEN_TMR01EN_Pos           (1UL)                     /*!< TMR01EN (Bit 1)                                       */
44568 #define TIMER_AUXEN_TMR01EN_Msk           (0x2UL)                   /*!< TMR01EN (Bitfield-Mask: 0x01)                         */
44569 #define TIMER_AUXEN_TMR00EN_Pos           (0UL)                     /*!< TMR00EN (Bit 0)                                       */
44570 #define TIMER_AUXEN_TMR00EN_Msk           (0x1UL)                   /*!< TMR00EN (Bitfield-Mask: 0x01)                         */
44571 /* =========================================================  CTRL0  ========================================================= */
44572 #define TIMER_CTRL0_TMR0LMT_Pos           (24UL)                    /*!< TMR0LMT (Bit 24)                                      */
44573 #define TIMER_CTRL0_TMR0LMT_Msk           (0xff000000UL)            /*!< TMR0LMT (Bitfield-Mask: 0xff)                         */
44574 #define TIMER_CTRL0_TMR0TMODE_Pos         (16UL)                    /*!< TMR0TMODE (Bit 16)                                    */
44575 #define TIMER_CTRL0_TMR0TMODE_Msk         (0x30000UL)               /*!< TMR0TMODE (Bitfield-Mask: 0x03)                       */
44576 #define TIMER_CTRL0_TMR0CLK_Pos           (8UL)                     /*!< TMR0CLK (Bit 8)                                       */
44577 #define TIMER_CTRL0_TMR0CLK_Msk           (0xff00UL)                /*!< TMR0CLK (Bitfield-Mask: 0xff)                         */
44578 #define TIMER_CTRL0_TMR0FN_Pos            (4UL)                     /*!< TMR0FN (Bit 4)                                        */
44579 #define TIMER_CTRL0_TMR0FN_Msk            (0xf0UL)                  /*!< TMR0FN (Bitfield-Mask: 0x0f)                          */
44580 #define TIMER_CTRL0_TMR0POL1_Pos          (3UL)                     /*!< TMR0POL1 (Bit 3)                                      */
44581 #define TIMER_CTRL0_TMR0POL1_Msk          (0x8UL)                   /*!< TMR0POL1 (Bitfield-Mask: 0x01)                        */
44582 #define TIMER_CTRL0_TMR0POL0_Pos          (2UL)                     /*!< TMR0POL0 (Bit 2)                                      */
44583 #define TIMER_CTRL0_TMR0POL0_Msk          (0x4UL)                   /*!< TMR0POL0 (Bitfield-Mask: 0x01)                        */
44584 #define TIMER_CTRL0_TMR0CLR_Pos           (1UL)                     /*!< TMR0CLR (Bit 1)                                       */
44585 #define TIMER_CTRL0_TMR0CLR_Msk           (0x2UL)                   /*!< TMR0CLR (Bitfield-Mask: 0x01)                         */
44586 #define TIMER_CTRL0_TMR0EN_Pos            (0UL)                     /*!< TMR0EN (Bit 0)                                        */
44587 #define TIMER_CTRL0_TMR0EN_Msk            (0x1UL)                   /*!< TMR0EN (Bitfield-Mask: 0x01)                          */
44588 /* ========================================================  TIMER0  ========================================================= */
44589 #define TIMER_TIMER0_TIMER0_Pos           (0UL)                     /*!< TIMER0 (Bit 0)                                        */
44590 #define TIMER_TIMER0_TIMER0_Msk           (0xffffffffUL)            /*!< TIMER0 (Bitfield-Mask: 0xffffffff)                    */
44591 /* =======================================================  TMR0CMP0  ======================================================== */
44592 #define TIMER_TMR0CMP0_TMR0CMP0_Pos       (0UL)                     /*!< TMR0CMP0 (Bit 0)                                      */
44593 #define TIMER_TMR0CMP0_TMR0CMP0_Msk       (0xffffffffUL)            /*!< TMR0CMP0 (Bitfield-Mask: 0xffffffff)                  */
44594 /* =======================================================  TMR0CMP1  ======================================================== */
44595 #define TIMER_TMR0CMP1_TMR0CMP1_Pos       (0UL)                     /*!< TMR0CMP1 (Bit 0)                                      */
44596 #define TIMER_TMR0CMP1_TMR0CMP1_Msk       (0xffffffffUL)            /*!< TMR0CMP1 (Bitfield-Mask: 0xffffffff)                  */
44597 /* =========================================================  MODE0  ========================================================= */
44598 #define TIMER_MODE0_TMR0TRIGSEL_Pos       (8UL)                     /*!< TMR0TRIGSEL (Bit 8)                                   */
44599 #define TIMER_MODE0_TMR0TRIGSEL_Msk       (0xff00UL)                /*!< TMR0TRIGSEL (Bitfield-Mask: 0xff)                     */
44600 /* =========================================================  CTRL1  ========================================================= */
44601 #define TIMER_CTRL1_TMR1LMT_Pos           (24UL)                    /*!< TMR1LMT (Bit 24)                                      */
44602 #define TIMER_CTRL1_TMR1LMT_Msk           (0xff000000UL)            /*!< TMR1LMT (Bitfield-Mask: 0xff)                         */
44603 #define TIMER_CTRL1_TMR1TMODE_Pos         (16UL)                    /*!< TMR1TMODE (Bit 16)                                    */
44604 #define TIMER_CTRL1_TMR1TMODE_Msk         (0x30000UL)               /*!< TMR1TMODE (Bitfield-Mask: 0x03)                       */
44605 #define TIMER_CTRL1_TMR1CLK_Pos           (8UL)                     /*!< TMR1CLK (Bit 8)                                       */
44606 #define TIMER_CTRL1_TMR1CLK_Msk           (0xff00UL)                /*!< TMR1CLK (Bitfield-Mask: 0xff)                         */
44607 #define TIMER_CTRL1_TMR1FN_Pos            (4UL)                     /*!< TMR1FN (Bit 4)                                        */
44608 #define TIMER_CTRL1_TMR1FN_Msk            (0xf0UL)                  /*!< TMR1FN (Bitfield-Mask: 0x0f)                          */
44609 #define TIMER_CTRL1_TMR1POL1_Pos          (3UL)                     /*!< TMR1POL1 (Bit 3)                                      */
44610 #define TIMER_CTRL1_TMR1POL1_Msk          (0x8UL)                   /*!< TMR1POL1 (Bitfield-Mask: 0x01)                        */
44611 #define TIMER_CTRL1_TMR1POL0_Pos          (2UL)                     /*!< TMR1POL0 (Bit 2)                                      */
44612 #define TIMER_CTRL1_TMR1POL0_Msk          (0x4UL)                   /*!< TMR1POL0 (Bitfield-Mask: 0x01)                        */
44613 #define TIMER_CTRL1_TMR1CLR_Pos           (1UL)                     /*!< TMR1CLR (Bit 1)                                       */
44614 #define TIMER_CTRL1_TMR1CLR_Msk           (0x2UL)                   /*!< TMR1CLR (Bitfield-Mask: 0x01)                         */
44615 #define TIMER_CTRL1_TMR1EN_Pos            (0UL)                     /*!< TMR1EN (Bit 0)                                        */
44616 #define TIMER_CTRL1_TMR1EN_Msk            (0x1UL)                   /*!< TMR1EN (Bitfield-Mask: 0x01)                          */
44617 /* ========================================================  TIMER1  ========================================================= */
44618 #define TIMER_TIMER1_TIMER1_Pos           (0UL)                     /*!< TIMER1 (Bit 0)                                        */
44619 #define TIMER_TIMER1_TIMER1_Msk           (0xffffffffUL)            /*!< TIMER1 (Bitfield-Mask: 0xffffffff)                    */
44620 /* =======================================================  TMR1CMP0  ======================================================== */
44621 #define TIMER_TMR1CMP0_TMR1CMP0_Pos       (0UL)                     /*!< TMR1CMP0 (Bit 0)                                      */
44622 #define TIMER_TMR1CMP0_TMR1CMP0_Msk       (0xffffffffUL)            /*!< TMR1CMP0 (Bitfield-Mask: 0xffffffff)                  */
44623 /* =======================================================  TMR1CMP1  ======================================================== */
44624 #define TIMER_TMR1CMP1_TMR1CMP1_Pos       (0UL)                     /*!< TMR1CMP1 (Bit 0)                                      */
44625 #define TIMER_TMR1CMP1_TMR1CMP1_Msk       (0xffffffffUL)            /*!< TMR1CMP1 (Bitfield-Mask: 0xffffffff)                  */
44626 /* =========================================================  MODE1  ========================================================= */
44627 #define TIMER_MODE1_TMR1TRIGSEL_Pos       (8UL)                     /*!< TMR1TRIGSEL (Bit 8)                                   */
44628 #define TIMER_MODE1_TMR1TRIGSEL_Msk       (0xff00UL)                /*!< TMR1TRIGSEL (Bitfield-Mask: 0xff)                     */
44629 /* =========================================================  CTRL2  ========================================================= */
44630 #define TIMER_CTRL2_TMR2LMT_Pos           (24UL)                    /*!< TMR2LMT (Bit 24)                                      */
44631 #define TIMER_CTRL2_TMR2LMT_Msk           (0xff000000UL)            /*!< TMR2LMT (Bitfield-Mask: 0xff)                         */
44632 #define TIMER_CTRL2_TMR2TMODE_Pos         (16UL)                    /*!< TMR2TMODE (Bit 16)                                    */
44633 #define TIMER_CTRL2_TMR2TMODE_Msk         (0x30000UL)               /*!< TMR2TMODE (Bitfield-Mask: 0x03)                       */
44634 #define TIMER_CTRL2_TMR2CLK_Pos           (8UL)                     /*!< TMR2CLK (Bit 8)                                       */
44635 #define TIMER_CTRL2_TMR2CLK_Msk           (0xff00UL)                /*!< TMR2CLK (Bitfield-Mask: 0xff)                         */
44636 #define TIMER_CTRL2_TMR2FN_Pos            (4UL)                     /*!< TMR2FN (Bit 4)                                        */
44637 #define TIMER_CTRL2_TMR2FN_Msk            (0xf0UL)                  /*!< TMR2FN (Bitfield-Mask: 0x0f)                          */
44638 #define TIMER_CTRL2_TMR2POL1_Pos          (3UL)                     /*!< TMR2POL1 (Bit 3)                                      */
44639 #define TIMER_CTRL2_TMR2POL1_Msk          (0x8UL)                   /*!< TMR2POL1 (Bitfield-Mask: 0x01)                        */
44640 #define TIMER_CTRL2_TMR2POL0_Pos          (2UL)                     /*!< TMR2POL0 (Bit 2)                                      */
44641 #define TIMER_CTRL2_TMR2POL0_Msk          (0x4UL)                   /*!< TMR2POL0 (Bitfield-Mask: 0x01)                        */
44642 #define TIMER_CTRL2_TMR2CLR_Pos           (1UL)                     /*!< TMR2CLR (Bit 1)                                       */
44643 #define TIMER_CTRL2_TMR2CLR_Msk           (0x2UL)                   /*!< TMR2CLR (Bitfield-Mask: 0x01)                         */
44644 #define TIMER_CTRL2_TMR2EN_Pos            (0UL)                     /*!< TMR2EN (Bit 0)                                        */
44645 #define TIMER_CTRL2_TMR2EN_Msk            (0x1UL)                   /*!< TMR2EN (Bitfield-Mask: 0x01)                          */
44646 /* ========================================================  TIMER2  ========================================================= */
44647 #define TIMER_TIMER2_TIMER2_Pos           (0UL)                     /*!< TIMER2 (Bit 0)                                        */
44648 #define TIMER_TIMER2_TIMER2_Msk           (0xffffffffUL)            /*!< TIMER2 (Bitfield-Mask: 0xffffffff)                    */
44649 /* =======================================================  TMR2CMP0  ======================================================== */
44650 #define TIMER_TMR2CMP0_TMR2CMP0_Pos       (0UL)                     /*!< TMR2CMP0 (Bit 0)                                      */
44651 #define TIMER_TMR2CMP0_TMR2CMP0_Msk       (0xffffffffUL)            /*!< TMR2CMP0 (Bitfield-Mask: 0xffffffff)                  */
44652 /* =======================================================  TMR2CMP1  ======================================================== */
44653 #define TIMER_TMR2CMP1_TMR2CMP1_Pos       (0UL)                     /*!< TMR2CMP1 (Bit 0)                                      */
44654 #define TIMER_TMR2CMP1_TMR2CMP1_Msk       (0xffffffffUL)            /*!< TMR2CMP1 (Bitfield-Mask: 0xffffffff)                  */
44655 /* =========================================================  MODE2  ========================================================= */
44656 #define TIMER_MODE2_TMR2TRIGSEL_Pos       (8UL)                     /*!< TMR2TRIGSEL (Bit 8)                                   */
44657 #define TIMER_MODE2_TMR2TRIGSEL_Msk       (0xff00UL)                /*!< TMR2TRIGSEL (Bitfield-Mask: 0xff)                     */
44658 /* =========================================================  CTRL3  ========================================================= */
44659 #define TIMER_CTRL3_TMR3LMT_Pos           (24UL)                    /*!< TMR3LMT (Bit 24)                                      */
44660 #define TIMER_CTRL3_TMR3LMT_Msk           (0xff000000UL)            /*!< TMR3LMT (Bitfield-Mask: 0xff)                         */
44661 #define TIMER_CTRL3_TMR3TMODE_Pos         (16UL)                    /*!< TMR3TMODE (Bit 16)                                    */
44662 #define TIMER_CTRL3_TMR3TMODE_Msk         (0x30000UL)               /*!< TMR3TMODE (Bitfield-Mask: 0x03)                       */
44663 #define TIMER_CTRL3_TMR3CLK_Pos           (8UL)                     /*!< TMR3CLK (Bit 8)                                       */
44664 #define TIMER_CTRL3_TMR3CLK_Msk           (0xff00UL)                /*!< TMR3CLK (Bitfield-Mask: 0xff)                         */
44665 #define TIMER_CTRL3_TMR3FN_Pos            (4UL)                     /*!< TMR3FN (Bit 4)                                        */
44666 #define TIMER_CTRL3_TMR3FN_Msk            (0xf0UL)                  /*!< TMR3FN (Bitfield-Mask: 0x0f)                          */
44667 #define TIMER_CTRL3_TMR3POL1_Pos          (3UL)                     /*!< TMR3POL1 (Bit 3)                                      */
44668 #define TIMER_CTRL3_TMR3POL1_Msk          (0x8UL)                   /*!< TMR3POL1 (Bitfield-Mask: 0x01)                        */
44669 #define TIMER_CTRL3_TMR3POL0_Pos          (2UL)                     /*!< TMR3POL0 (Bit 2)                                      */
44670 #define TIMER_CTRL3_TMR3POL0_Msk          (0x4UL)                   /*!< TMR3POL0 (Bitfield-Mask: 0x01)                        */
44671 #define TIMER_CTRL3_TMR3CLR_Pos           (1UL)                     /*!< TMR3CLR (Bit 1)                                       */
44672 #define TIMER_CTRL3_TMR3CLR_Msk           (0x2UL)                   /*!< TMR3CLR (Bitfield-Mask: 0x01)                         */
44673 #define TIMER_CTRL3_TMR3EN_Pos            (0UL)                     /*!< TMR3EN (Bit 0)                                        */
44674 #define TIMER_CTRL3_TMR3EN_Msk            (0x1UL)                   /*!< TMR3EN (Bitfield-Mask: 0x01)                          */
44675 /* ========================================================  TIMER3  ========================================================= */
44676 #define TIMER_TIMER3_TIMER3_Pos           (0UL)                     /*!< TIMER3 (Bit 0)                                        */
44677 #define TIMER_TIMER3_TIMER3_Msk           (0xffffffffUL)            /*!< TIMER3 (Bitfield-Mask: 0xffffffff)                    */
44678 /* =======================================================  TMR3CMP0  ======================================================== */
44679 #define TIMER_TMR3CMP0_TMR3CMP0_Pos       (0UL)                     /*!< TMR3CMP0 (Bit 0)                                      */
44680 #define TIMER_TMR3CMP0_TMR3CMP0_Msk       (0xffffffffUL)            /*!< TMR3CMP0 (Bitfield-Mask: 0xffffffff)                  */
44681 /* =======================================================  TMR3CMP1  ======================================================== */
44682 #define TIMER_TMR3CMP1_TMR3CMP1_Pos       (0UL)                     /*!< TMR3CMP1 (Bit 0)                                      */
44683 #define TIMER_TMR3CMP1_TMR3CMP1_Msk       (0xffffffffUL)            /*!< TMR3CMP1 (Bitfield-Mask: 0xffffffff)                  */
44684 /* =========================================================  MODE3  ========================================================= */
44685 #define TIMER_MODE3_TMR3TRIGSEL_Pos       (8UL)                     /*!< TMR3TRIGSEL (Bit 8)                                   */
44686 #define TIMER_MODE3_TMR3TRIGSEL_Msk       (0xff00UL)                /*!< TMR3TRIGSEL (Bitfield-Mask: 0xff)                     */
44687 /* =========================================================  CTRL4  ========================================================= */
44688 #define TIMER_CTRL4_TMR4LMT_Pos           (24UL)                    /*!< TMR4LMT (Bit 24)                                      */
44689 #define TIMER_CTRL4_TMR4LMT_Msk           (0xff000000UL)            /*!< TMR4LMT (Bitfield-Mask: 0xff)                         */
44690 #define TIMER_CTRL4_TMR4TMODE_Pos         (16UL)                    /*!< TMR4TMODE (Bit 16)                                    */
44691 #define TIMER_CTRL4_TMR4TMODE_Msk         (0x30000UL)               /*!< TMR4TMODE (Bitfield-Mask: 0x03)                       */
44692 #define TIMER_CTRL4_TMR4CLK_Pos           (8UL)                     /*!< TMR4CLK (Bit 8)                                       */
44693 #define TIMER_CTRL4_TMR4CLK_Msk           (0xff00UL)                /*!< TMR4CLK (Bitfield-Mask: 0xff)                         */
44694 #define TIMER_CTRL4_TMR4FN_Pos            (4UL)                     /*!< TMR4FN (Bit 4)                                        */
44695 #define TIMER_CTRL4_TMR4FN_Msk            (0xf0UL)                  /*!< TMR4FN (Bitfield-Mask: 0x0f)                          */
44696 #define TIMER_CTRL4_TMR4POL1_Pos          (3UL)                     /*!< TMR4POL1 (Bit 3)                                      */
44697 #define TIMER_CTRL4_TMR4POL1_Msk          (0x8UL)                   /*!< TMR4POL1 (Bitfield-Mask: 0x01)                        */
44698 #define TIMER_CTRL4_TMR4POL0_Pos          (2UL)                     /*!< TMR4POL0 (Bit 2)                                      */
44699 #define TIMER_CTRL4_TMR4POL0_Msk          (0x4UL)                   /*!< TMR4POL0 (Bitfield-Mask: 0x01)                        */
44700 #define TIMER_CTRL4_TMR4CLR_Pos           (1UL)                     /*!< TMR4CLR (Bit 1)                                       */
44701 #define TIMER_CTRL4_TMR4CLR_Msk           (0x2UL)                   /*!< TMR4CLR (Bitfield-Mask: 0x01)                         */
44702 #define TIMER_CTRL4_TMR4EN_Pos            (0UL)                     /*!< TMR4EN (Bit 0)                                        */
44703 #define TIMER_CTRL4_TMR4EN_Msk            (0x1UL)                   /*!< TMR4EN (Bitfield-Mask: 0x01)                          */
44704 /* ========================================================  TIMER4  ========================================================= */
44705 #define TIMER_TIMER4_TIMER4_Pos           (0UL)                     /*!< TIMER4 (Bit 0)                                        */
44706 #define TIMER_TIMER4_TIMER4_Msk           (0xffffffffUL)            /*!< TIMER4 (Bitfield-Mask: 0xffffffff)                    */
44707 /* =======================================================  TMR4CMP0  ======================================================== */
44708 #define TIMER_TMR4CMP0_TMR4CMP0_Pos       (0UL)                     /*!< TMR4CMP0 (Bit 0)                                      */
44709 #define TIMER_TMR4CMP0_TMR4CMP0_Msk       (0xffffffffUL)            /*!< TMR4CMP0 (Bitfield-Mask: 0xffffffff)                  */
44710 /* =======================================================  TMR4CMP1  ======================================================== */
44711 #define TIMER_TMR4CMP1_TMR4CMP1_Pos       (0UL)                     /*!< TMR4CMP1 (Bit 0)                                      */
44712 #define TIMER_TMR4CMP1_TMR4CMP1_Msk       (0xffffffffUL)            /*!< TMR4CMP1 (Bitfield-Mask: 0xffffffff)                  */
44713 /* =========================================================  MODE4  ========================================================= */
44714 #define TIMER_MODE4_TMR4TRIGSEL_Pos       (8UL)                     /*!< TMR4TRIGSEL (Bit 8)                                   */
44715 #define TIMER_MODE4_TMR4TRIGSEL_Msk       (0xff00UL)                /*!< TMR4TRIGSEL (Bitfield-Mask: 0xff)                     */
44716 /* =========================================================  CTRL5  ========================================================= */
44717 #define TIMER_CTRL5_TMR5LMT_Pos           (24UL)                    /*!< TMR5LMT (Bit 24)                                      */
44718 #define TIMER_CTRL5_TMR5LMT_Msk           (0xff000000UL)            /*!< TMR5LMT (Bitfield-Mask: 0xff)                         */
44719 #define TIMER_CTRL5_TMR5TMODE_Pos         (16UL)                    /*!< TMR5TMODE (Bit 16)                                    */
44720 #define TIMER_CTRL5_TMR5TMODE_Msk         (0x30000UL)               /*!< TMR5TMODE (Bitfield-Mask: 0x03)                       */
44721 #define TIMER_CTRL5_TMR5CLK_Pos           (8UL)                     /*!< TMR5CLK (Bit 8)                                       */
44722 #define TIMER_CTRL5_TMR5CLK_Msk           (0xff00UL)                /*!< TMR5CLK (Bitfield-Mask: 0xff)                         */
44723 #define TIMER_CTRL5_TMR5FN_Pos            (4UL)                     /*!< TMR5FN (Bit 4)                                        */
44724 #define TIMER_CTRL5_TMR5FN_Msk            (0xf0UL)                  /*!< TMR5FN (Bitfield-Mask: 0x0f)                          */
44725 #define TIMER_CTRL5_TMR5POL1_Pos          (3UL)                     /*!< TMR5POL1 (Bit 3)                                      */
44726 #define TIMER_CTRL5_TMR5POL1_Msk          (0x8UL)                   /*!< TMR5POL1 (Bitfield-Mask: 0x01)                        */
44727 #define TIMER_CTRL5_TMR5POL0_Pos          (2UL)                     /*!< TMR5POL0 (Bit 2)                                      */
44728 #define TIMER_CTRL5_TMR5POL0_Msk          (0x4UL)                   /*!< TMR5POL0 (Bitfield-Mask: 0x01)                        */
44729 #define TIMER_CTRL5_TMR5CLR_Pos           (1UL)                     /*!< TMR5CLR (Bit 1)                                       */
44730 #define TIMER_CTRL5_TMR5CLR_Msk           (0x2UL)                   /*!< TMR5CLR (Bitfield-Mask: 0x01)                         */
44731 #define TIMER_CTRL5_TMR5EN_Pos            (0UL)                     /*!< TMR5EN (Bit 0)                                        */
44732 #define TIMER_CTRL5_TMR5EN_Msk            (0x1UL)                   /*!< TMR5EN (Bitfield-Mask: 0x01)                          */
44733 /* ========================================================  TIMER5  ========================================================= */
44734 #define TIMER_TIMER5_TIMER5_Pos           (0UL)                     /*!< TIMER5 (Bit 0)                                        */
44735 #define TIMER_TIMER5_TIMER5_Msk           (0xffffffffUL)            /*!< TIMER5 (Bitfield-Mask: 0xffffffff)                    */
44736 /* =======================================================  TMR5CMP0  ======================================================== */
44737 #define TIMER_TMR5CMP0_TMR5CMP0_Pos       (0UL)                     /*!< TMR5CMP0 (Bit 0)                                      */
44738 #define TIMER_TMR5CMP0_TMR5CMP0_Msk       (0xffffffffUL)            /*!< TMR5CMP0 (Bitfield-Mask: 0xffffffff)                  */
44739 /* =======================================================  TMR5CMP1  ======================================================== */
44740 #define TIMER_TMR5CMP1_TMR5CMP1_Pos       (0UL)                     /*!< TMR5CMP1 (Bit 0)                                      */
44741 #define TIMER_TMR5CMP1_TMR5CMP1_Msk       (0xffffffffUL)            /*!< TMR5CMP1 (Bitfield-Mask: 0xffffffff)                  */
44742 /* =========================================================  MODE5  ========================================================= */
44743 #define TIMER_MODE5_TMR5TRIGSEL_Pos       (8UL)                     /*!< TMR5TRIGSEL (Bit 8)                                   */
44744 #define TIMER_MODE5_TMR5TRIGSEL_Msk       (0xff00UL)                /*!< TMR5TRIGSEL (Bitfield-Mask: 0xff)                     */
44745 /* =========================================================  CTRL6  ========================================================= */
44746 #define TIMER_CTRL6_TMR6LMT_Pos           (24UL)                    /*!< TMR6LMT (Bit 24)                                      */
44747 #define TIMER_CTRL6_TMR6LMT_Msk           (0xff000000UL)            /*!< TMR6LMT (Bitfield-Mask: 0xff)                         */
44748 #define TIMER_CTRL6_TMR6TMODE_Pos         (16UL)                    /*!< TMR6TMODE (Bit 16)                                    */
44749 #define TIMER_CTRL6_TMR6TMODE_Msk         (0x30000UL)               /*!< TMR6TMODE (Bitfield-Mask: 0x03)                       */
44750 #define TIMER_CTRL6_TMR6CLK_Pos           (8UL)                     /*!< TMR6CLK (Bit 8)                                       */
44751 #define TIMER_CTRL6_TMR6CLK_Msk           (0xff00UL)                /*!< TMR6CLK (Bitfield-Mask: 0xff)                         */
44752 #define TIMER_CTRL6_TMR6FN_Pos            (4UL)                     /*!< TMR6FN (Bit 4)                                        */
44753 #define TIMER_CTRL6_TMR6FN_Msk            (0xf0UL)                  /*!< TMR6FN (Bitfield-Mask: 0x0f)                          */
44754 #define TIMER_CTRL6_TMR6POL1_Pos          (3UL)                     /*!< TMR6POL1 (Bit 3)                                      */
44755 #define TIMER_CTRL6_TMR6POL1_Msk          (0x8UL)                   /*!< TMR6POL1 (Bitfield-Mask: 0x01)                        */
44756 #define TIMER_CTRL6_TMR6POL0_Pos          (2UL)                     /*!< TMR6POL0 (Bit 2)                                      */
44757 #define TIMER_CTRL6_TMR6POL0_Msk          (0x4UL)                   /*!< TMR6POL0 (Bitfield-Mask: 0x01)                        */
44758 #define TIMER_CTRL6_TMR6CLR_Pos           (1UL)                     /*!< TMR6CLR (Bit 1)                                       */
44759 #define TIMER_CTRL6_TMR6CLR_Msk           (0x2UL)                   /*!< TMR6CLR (Bitfield-Mask: 0x01)                         */
44760 #define TIMER_CTRL6_TMR6EN_Pos            (0UL)                     /*!< TMR6EN (Bit 0)                                        */
44761 #define TIMER_CTRL6_TMR6EN_Msk            (0x1UL)                   /*!< TMR6EN (Bitfield-Mask: 0x01)                          */
44762 /* ========================================================  TIMER6  ========================================================= */
44763 #define TIMER_TIMER6_TIMER6_Pos           (0UL)                     /*!< TIMER6 (Bit 0)                                        */
44764 #define TIMER_TIMER6_TIMER6_Msk           (0xffffffffUL)            /*!< TIMER6 (Bitfield-Mask: 0xffffffff)                    */
44765 /* =======================================================  TMR6CMP0  ======================================================== */
44766 #define TIMER_TMR6CMP0_TMR6CMP0_Pos       (0UL)                     /*!< TMR6CMP0 (Bit 0)                                      */
44767 #define TIMER_TMR6CMP0_TMR6CMP0_Msk       (0xffffffffUL)            /*!< TMR6CMP0 (Bitfield-Mask: 0xffffffff)                  */
44768 /* =======================================================  TMR6CMP1  ======================================================== */
44769 #define TIMER_TMR6CMP1_TMR6CMP1_Pos       (0UL)                     /*!< TMR6CMP1 (Bit 0)                                      */
44770 #define TIMER_TMR6CMP1_TMR6CMP1_Msk       (0xffffffffUL)            /*!< TMR6CMP1 (Bitfield-Mask: 0xffffffff)                  */
44771 /* =========================================================  MODE6  ========================================================= */
44772 #define TIMER_MODE6_TMR6TRIGSEL_Pos       (8UL)                     /*!< TMR6TRIGSEL (Bit 8)                                   */
44773 #define TIMER_MODE6_TMR6TRIGSEL_Msk       (0xff00UL)                /*!< TMR6TRIGSEL (Bitfield-Mask: 0xff)                     */
44774 /* =========================================================  CTRL7  ========================================================= */
44775 #define TIMER_CTRL7_TMR7LMT_Pos           (24UL)                    /*!< TMR7LMT (Bit 24)                                      */
44776 #define TIMER_CTRL7_TMR7LMT_Msk           (0xff000000UL)            /*!< TMR7LMT (Bitfield-Mask: 0xff)                         */
44777 #define TIMER_CTRL7_TMR7TMODE_Pos         (16UL)                    /*!< TMR7TMODE (Bit 16)                                    */
44778 #define TIMER_CTRL7_TMR7TMODE_Msk         (0x30000UL)               /*!< TMR7TMODE (Bitfield-Mask: 0x03)                       */
44779 #define TIMER_CTRL7_TMR7CLK_Pos           (8UL)                     /*!< TMR7CLK (Bit 8)                                       */
44780 #define TIMER_CTRL7_TMR7CLK_Msk           (0xff00UL)                /*!< TMR7CLK (Bitfield-Mask: 0xff)                         */
44781 #define TIMER_CTRL7_TMR7FN_Pos            (4UL)                     /*!< TMR7FN (Bit 4)                                        */
44782 #define TIMER_CTRL7_TMR7FN_Msk            (0xf0UL)                  /*!< TMR7FN (Bitfield-Mask: 0x0f)                          */
44783 #define TIMER_CTRL7_TMR7POL1_Pos          (3UL)                     /*!< TMR7POL1 (Bit 3)                                      */
44784 #define TIMER_CTRL7_TMR7POL1_Msk          (0x8UL)                   /*!< TMR7POL1 (Bitfield-Mask: 0x01)                        */
44785 #define TIMER_CTRL7_TMR7POL0_Pos          (2UL)                     /*!< TMR7POL0 (Bit 2)                                      */
44786 #define TIMER_CTRL7_TMR7POL0_Msk          (0x4UL)                   /*!< TMR7POL0 (Bitfield-Mask: 0x01)                        */
44787 #define TIMER_CTRL7_TMR7CLR_Pos           (1UL)                     /*!< TMR7CLR (Bit 1)                                       */
44788 #define TIMER_CTRL7_TMR7CLR_Msk           (0x2UL)                   /*!< TMR7CLR (Bitfield-Mask: 0x01)                         */
44789 #define TIMER_CTRL7_TMR7EN_Pos            (0UL)                     /*!< TMR7EN (Bit 0)                                        */
44790 #define TIMER_CTRL7_TMR7EN_Msk            (0x1UL)                   /*!< TMR7EN (Bitfield-Mask: 0x01)                          */
44791 /* ========================================================  TIMER7  ========================================================= */
44792 #define TIMER_TIMER7_TIMER7_Pos           (0UL)                     /*!< TIMER7 (Bit 0)                                        */
44793 #define TIMER_TIMER7_TIMER7_Msk           (0xffffffffUL)            /*!< TIMER7 (Bitfield-Mask: 0xffffffff)                    */
44794 /* =======================================================  TMR7CMP0  ======================================================== */
44795 #define TIMER_TMR7CMP0_TMR7CMP0_Pos       (0UL)                     /*!< TMR7CMP0 (Bit 0)                                      */
44796 #define TIMER_TMR7CMP0_TMR7CMP0_Msk       (0xffffffffUL)            /*!< TMR7CMP0 (Bitfield-Mask: 0xffffffff)                  */
44797 /* =======================================================  TMR7CMP1  ======================================================== */
44798 #define TIMER_TMR7CMP1_TMR7CMP1_Pos       (0UL)                     /*!< TMR7CMP1 (Bit 0)                                      */
44799 #define TIMER_TMR7CMP1_TMR7CMP1_Msk       (0xffffffffUL)            /*!< TMR7CMP1 (Bitfield-Mask: 0xffffffff)                  */
44800 /* =========================================================  MODE7  ========================================================= */
44801 #define TIMER_MODE7_TMR7TRIGSEL_Pos       (8UL)                     /*!< TMR7TRIGSEL (Bit 8)                                   */
44802 #define TIMER_MODE7_TMR7TRIGSEL_Msk       (0xff00UL)                /*!< TMR7TRIGSEL (Bitfield-Mask: 0xff)                     */
44803 /* =========================================================  CTRL8  ========================================================= */
44804 #define TIMER_CTRL8_TMR8LMT_Pos           (24UL)                    /*!< TMR8LMT (Bit 24)                                      */
44805 #define TIMER_CTRL8_TMR8LMT_Msk           (0xff000000UL)            /*!< TMR8LMT (Bitfield-Mask: 0xff)                         */
44806 #define TIMER_CTRL8_TMR8TMODE_Pos         (16UL)                    /*!< TMR8TMODE (Bit 16)                                    */
44807 #define TIMER_CTRL8_TMR8TMODE_Msk         (0x30000UL)               /*!< TMR8TMODE (Bitfield-Mask: 0x03)                       */
44808 #define TIMER_CTRL8_TMR8CLK_Pos           (8UL)                     /*!< TMR8CLK (Bit 8)                                       */
44809 #define TIMER_CTRL8_TMR8CLK_Msk           (0xff00UL)                /*!< TMR8CLK (Bitfield-Mask: 0xff)                         */
44810 #define TIMER_CTRL8_TMR8FN_Pos            (4UL)                     /*!< TMR8FN (Bit 4)                                        */
44811 #define TIMER_CTRL8_TMR8FN_Msk            (0xf0UL)                  /*!< TMR8FN (Bitfield-Mask: 0x0f)                          */
44812 #define TIMER_CTRL8_TMR8POL1_Pos          (3UL)                     /*!< TMR8POL1 (Bit 3)                                      */
44813 #define TIMER_CTRL8_TMR8POL1_Msk          (0x8UL)                   /*!< TMR8POL1 (Bitfield-Mask: 0x01)                        */
44814 #define TIMER_CTRL8_TMR8POL0_Pos          (2UL)                     /*!< TMR8POL0 (Bit 2)                                      */
44815 #define TIMER_CTRL8_TMR8POL0_Msk          (0x4UL)                   /*!< TMR8POL0 (Bitfield-Mask: 0x01)                        */
44816 #define TIMER_CTRL8_TMR8CLR_Pos           (1UL)                     /*!< TMR8CLR (Bit 1)                                       */
44817 #define TIMER_CTRL8_TMR8CLR_Msk           (0x2UL)                   /*!< TMR8CLR (Bitfield-Mask: 0x01)                         */
44818 #define TIMER_CTRL8_TMR8EN_Pos            (0UL)                     /*!< TMR8EN (Bit 0)                                        */
44819 #define TIMER_CTRL8_TMR8EN_Msk            (0x1UL)                   /*!< TMR8EN (Bitfield-Mask: 0x01)                          */
44820 /* ========================================================  TIMER8  ========================================================= */
44821 #define TIMER_TIMER8_TIMER8_Pos           (0UL)                     /*!< TIMER8 (Bit 0)                                        */
44822 #define TIMER_TIMER8_TIMER8_Msk           (0xffffffffUL)            /*!< TIMER8 (Bitfield-Mask: 0xffffffff)                    */
44823 /* =======================================================  TMR8CMP0  ======================================================== */
44824 #define TIMER_TMR8CMP0_TMR8CMP0_Pos       (0UL)                     /*!< TMR8CMP0 (Bit 0)                                      */
44825 #define TIMER_TMR8CMP0_TMR8CMP0_Msk       (0xffffffffUL)            /*!< TMR8CMP0 (Bitfield-Mask: 0xffffffff)                  */
44826 /* =======================================================  TMR8CMP1  ======================================================== */
44827 #define TIMER_TMR8CMP1_TMR8CMP1_Pos       (0UL)                     /*!< TMR8CMP1 (Bit 0)                                      */
44828 #define TIMER_TMR8CMP1_TMR8CMP1_Msk       (0xffffffffUL)            /*!< TMR8CMP1 (Bitfield-Mask: 0xffffffff)                  */
44829 /* =========================================================  MODE8  ========================================================= */
44830 #define TIMER_MODE8_TMR8TRIGSEL_Pos       (8UL)                     /*!< TMR8TRIGSEL (Bit 8)                                   */
44831 #define TIMER_MODE8_TMR8TRIGSEL_Msk       (0xff00UL)                /*!< TMR8TRIGSEL (Bitfield-Mask: 0xff)                     */
44832 /* =========================================================  CTRL9  ========================================================= */
44833 #define TIMER_CTRL9_TMR9LMT_Pos           (24UL)                    /*!< TMR9LMT (Bit 24)                                      */
44834 #define TIMER_CTRL9_TMR9LMT_Msk           (0xff000000UL)            /*!< TMR9LMT (Bitfield-Mask: 0xff)                         */
44835 #define TIMER_CTRL9_TMR9TMODE_Pos         (16UL)                    /*!< TMR9TMODE (Bit 16)                                    */
44836 #define TIMER_CTRL9_TMR9TMODE_Msk         (0x30000UL)               /*!< TMR9TMODE (Bitfield-Mask: 0x03)                       */
44837 #define TIMER_CTRL9_TMR9CLK_Pos           (8UL)                     /*!< TMR9CLK (Bit 8)                                       */
44838 #define TIMER_CTRL9_TMR9CLK_Msk           (0xff00UL)                /*!< TMR9CLK (Bitfield-Mask: 0xff)                         */
44839 #define TIMER_CTRL9_TMR9FN_Pos            (4UL)                     /*!< TMR9FN (Bit 4)                                        */
44840 #define TIMER_CTRL9_TMR9FN_Msk            (0xf0UL)                  /*!< TMR9FN (Bitfield-Mask: 0x0f)                          */
44841 #define TIMER_CTRL9_TMR9POL1_Pos          (3UL)                     /*!< TMR9POL1 (Bit 3)                                      */
44842 #define TIMER_CTRL9_TMR9POL1_Msk          (0x8UL)                   /*!< TMR9POL1 (Bitfield-Mask: 0x01)                        */
44843 #define TIMER_CTRL9_TMR9POL0_Pos          (2UL)                     /*!< TMR9POL0 (Bit 2)                                      */
44844 #define TIMER_CTRL9_TMR9POL0_Msk          (0x4UL)                   /*!< TMR9POL0 (Bitfield-Mask: 0x01)                        */
44845 #define TIMER_CTRL9_TMR9CLR_Pos           (1UL)                     /*!< TMR9CLR (Bit 1)                                       */
44846 #define TIMER_CTRL9_TMR9CLR_Msk           (0x2UL)                   /*!< TMR9CLR (Bitfield-Mask: 0x01)                         */
44847 #define TIMER_CTRL9_TMR9EN_Pos            (0UL)                     /*!< TMR9EN (Bit 0)                                        */
44848 #define TIMER_CTRL9_TMR9EN_Msk            (0x1UL)                   /*!< TMR9EN (Bitfield-Mask: 0x01)                          */
44849 /* ========================================================  TIMER9  ========================================================= */
44850 #define TIMER_TIMER9_TIMER9_Pos           (0UL)                     /*!< TIMER9 (Bit 0)                                        */
44851 #define TIMER_TIMER9_TIMER9_Msk           (0xffffffffUL)            /*!< TIMER9 (Bitfield-Mask: 0xffffffff)                    */
44852 /* =======================================================  TMR9CMP0  ======================================================== */
44853 #define TIMER_TMR9CMP0_TMR9CMP0_Pos       (0UL)                     /*!< TMR9CMP0 (Bit 0)                                      */
44854 #define TIMER_TMR9CMP0_TMR9CMP0_Msk       (0xffffffffUL)            /*!< TMR9CMP0 (Bitfield-Mask: 0xffffffff)                  */
44855 /* =======================================================  TMR9CMP1  ======================================================== */
44856 #define TIMER_TMR9CMP1_TMR9CMP1_Pos       (0UL)                     /*!< TMR9CMP1 (Bit 0)                                      */
44857 #define TIMER_TMR9CMP1_TMR9CMP1_Msk       (0xffffffffUL)            /*!< TMR9CMP1 (Bitfield-Mask: 0xffffffff)                  */
44858 /* =========================================================  MODE9  ========================================================= */
44859 #define TIMER_MODE9_TMR9TRIGSEL_Pos       (8UL)                     /*!< TMR9TRIGSEL (Bit 8)                                   */
44860 #define TIMER_MODE9_TMR9TRIGSEL_Msk       (0xff00UL)                /*!< TMR9TRIGSEL (Bitfield-Mask: 0xff)                     */
44861 /* ========================================================  CTRL10  ========================================================= */
44862 #define TIMER_CTRL10_TMR10LMT_Pos         (24UL)                    /*!< TMR10LMT (Bit 24)                                     */
44863 #define TIMER_CTRL10_TMR10LMT_Msk         (0xff000000UL)            /*!< TMR10LMT (Bitfield-Mask: 0xff)                        */
44864 #define TIMER_CTRL10_TMR10TMODE_Pos       (16UL)                    /*!< TMR10TMODE (Bit 16)                                   */
44865 #define TIMER_CTRL10_TMR10TMODE_Msk       (0x30000UL)               /*!< TMR10TMODE (Bitfield-Mask: 0x03)                      */
44866 #define TIMER_CTRL10_TMR10CLK_Pos         (8UL)                     /*!< TMR10CLK (Bit 8)                                      */
44867 #define TIMER_CTRL10_TMR10CLK_Msk         (0xff00UL)                /*!< TMR10CLK (Bitfield-Mask: 0xff)                        */
44868 #define TIMER_CTRL10_TMR10FN_Pos          (4UL)                     /*!< TMR10FN (Bit 4)                                       */
44869 #define TIMER_CTRL10_TMR10FN_Msk          (0xf0UL)                  /*!< TMR10FN (Bitfield-Mask: 0x0f)                         */
44870 #define TIMER_CTRL10_TMR10POL1_Pos        (3UL)                     /*!< TMR10POL1 (Bit 3)                                     */
44871 #define TIMER_CTRL10_TMR10POL1_Msk        (0x8UL)                   /*!< TMR10POL1 (Bitfield-Mask: 0x01)                       */
44872 #define TIMER_CTRL10_TMR10POL0_Pos        (2UL)                     /*!< TMR10POL0 (Bit 2)                                     */
44873 #define TIMER_CTRL10_TMR10POL0_Msk        (0x4UL)                   /*!< TMR10POL0 (Bitfield-Mask: 0x01)                       */
44874 #define TIMER_CTRL10_TMR10CLR_Pos         (1UL)                     /*!< TMR10CLR (Bit 1)                                      */
44875 #define TIMER_CTRL10_TMR10CLR_Msk         (0x2UL)                   /*!< TMR10CLR (Bitfield-Mask: 0x01)                        */
44876 #define TIMER_CTRL10_TMR10EN_Pos          (0UL)                     /*!< TMR10EN (Bit 0)                                       */
44877 #define TIMER_CTRL10_TMR10EN_Msk          (0x1UL)                   /*!< TMR10EN (Bitfield-Mask: 0x01)                         */
44878 /* ========================================================  TIMER10  ======================================================== */
44879 #define TIMER_TIMER10_TIMER10_Pos         (0UL)                     /*!< TIMER10 (Bit 0)                                       */
44880 #define TIMER_TIMER10_TIMER10_Msk         (0xffffffffUL)            /*!< TIMER10 (Bitfield-Mask: 0xffffffff)                   */
44881 /* =======================================================  TMR10CMP0  ======================================================= */
44882 #define TIMER_TMR10CMP0_TMR10CMP0_Pos     (0UL)                     /*!< TMR10CMP0 (Bit 0)                                     */
44883 #define TIMER_TMR10CMP0_TMR10CMP0_Msk     (0xffffffffUL)            /*!< TMR10CMP0 (Bitfield-Mask: 0xffffffff)                 */
44884 /* =======================================================  TMR10CMP1  ======================================================= */
44885 #define TIMER_TMR10CMP1_TMR10CMP1_Pos     (0UL)                     /*!< TMR10CMP1 (Bit 0)                                     */
44886 #define TIMER_TMR10CMP1_TMR10CMP1_Msk     (0xffffffffUL)            /*!< TMR10CMP1 (Bitfield-Mask: 0xffffffff)                 */
44887 /* ========================================================  MODE10  ========================================================= */
44888 #define TIMER_MODE10_TMR10TRIGSEL_Pos     (8UL)                     /*!< TMR10TRIGSEL (Bit 8)                                  */
44889 #define TIMER_MODE10_TMR10TRIGSEL_Msk     (0xff00UL)                /*!< TMR10TRIGSEL (Bitfield-Mask: 0xff)                    */
44890 /* ========================================================  CTRL11  ========================================================= */
44891 #define TIMER_CTRL11_TMR11LMT_Pos         (24UL)                    /*!< TMR11LMT (Bit 24)                                     */
44892 #define TIMER_CTRL11_TMR11LMT_Msk         (0xff000000UL)            /*!< TMR11LMT (Bitfield-Mask: 0xff)                        */
44893 #define TIMER_CTRL11_TMR11TMODE_Pos       (16UL)                    /*!< TMR11TMODE (Bit 16)                                   */
44894 #define TIMER_CTRL11_TMR11TMODE_Msk       (0x30000UL)               /*!< TMR11TMODE (Bitfield-Mask: 0x03)                      */
44895 #define TIMER_CTRL11_TMR11CLK_Pos         (8UL)                     /*!< TMR11CLK (Bit 8)                                      */
44896 #define TIMER_CTRL11_TMR11CLK_Msk         (0xff00UL)                /*!< TMR11CLK (Bitfield-Mask: 0xff)                        */
44897 #define TIMER_CTRL11_TMR11FN_Pos          (4UL)                     /*!< TMR11FN (Bit 4)                                       */
44898 #define TIMER_CTRL11_TMR11FN_Msk          (0xf0UL)                  /*!< TMR11FN (Bitfield-Mask: 0x0f)                         */
44899 #define TIMER_CTRL11_TMR11POL1_Pos        (3UL)                     /*!< TMR11POL1 (Bit 3)                                     */
44900 #define TIMER_CTRL11_TMR11POL1_Msk        (0x8UL)                   /*!< TMR11POL1 (Bitfield-Mask: 0x01)                       */
44901 #define TIMER_CTRL11_TMR11POL0_Pos        (2UL)                     /*!< TMR11POL0 (Bit 2)                                     */
44902 #define TIMER_CTRL11_TMR11POL0_Msk        (0x4UL)                   /*!< TMR11POL0 (Bitfield-Mask: 0x01)                       */
44903 #define TIMER_CTRL11_TMR11CLR_Pos         (1UL)                     /*!< TMR11CLR (Bit 1)                                      */
44904 #define TIMER_CTRL11_TMR11CLR_Msk         (0x2UL)                   /*!< TMR11CLR (Bitfield-Mask: 0x01)                        */
44905 #define TIMER_CTRL11_TMR11EN_Pos          (0UL)                     /*!< TMR11EN (Bit 0)                                       */
44906 #define TIMER_CTRL11_TMR11EN_Msk          (0x1UL)                   /*!< TMR11EN (Bitfield-Mask: 0x01)                         */
44907 /* ========================================================  TIMER11  ======================================================== */
44908 #define TIMER_TIMER11_TIMER11_Pos         (0UL)                     /*!< TIMER11 (Bit 0)                                       */
44909 #define TIMER_TIMER11_TIMER11_Msk         (0xffffffffUL)            /*!< TIMER11 (Bitfield-Mask: 0xffffffff)                   */
44910 /* =======================================================  TMR11CMP0  ======================================================= */
44911 #define TIMER_TMR11CMP0_TMR11CMP0_Pos     (0UL)                     /*!< TMR11CMP0 (Bit 0)                                     */
44912 #define TIMER_TMR11CMP0_TMR11CMP0_Msk     (0xffffffffUL)            /*!< TMR11CMP0 (Bitfield-Mask: 0xffffffff)                 */
44913 /* =======================================================  TMR11CMP1  ======================================================= */
44914 #define TIMER_TMR11CMP1_TMR11CMP1_Pos     (0UL)                     /*!< TMR11CMP1 (Bit 0)                                     */
44915 #define TIMER_TMR11CMP1_TMR11CMP1_Msk     (0xffffffffUL)            /*!< TMR11CMP1 (Bitfield-Mask: 0xffffffff)                 */
44916 /* ========================================================  MODE11  ========================================================= */
44917 #define TIMER_MODE11_TMR11TRIGSEL_Pos     (8UL)                     /*!< TMR11TRIGSEL (Bit 8)                                  */
44918 #define TIMER_MODE11_TMR11TRIGSEL_Msk     (0xff00UL)                /*!< TMR11TRIGSEL (Bitfield-Mask: 0xff)                    */
44919 /* ========================================================  CTRL12  ========================================================= */
44920 #define TIMER_CTRL12_TMR12LMT_Pos         (24UL)                    /*!< TMR12LMT (Bit 24)                                     */
44921 #define TIMER_CTRL12_TMR12LMT_Msk         (0xff000000UL)            /*!< TMR12LMT (Bitfield-Mask: 0xff)                        */
44922 #define TIMER_CTRL12_TMR12TMODE_Pos       (16UL)                    /*!< TMR12TMODE (Bit 16)                                   */
44923 #define TIMER_CTRL12_TMR12TMODE_Msk       (0x30000UL)               /*!< TMR12TMODE (Bitfield-Mask: 0x03)                      */
44924 #define TIMER_CTRL12_TMR12CLK_Pos         (8UL)                     /*!< TMR12CLK (Bit 8)                                      */
44925 #define TIMER_CTRL12_TMR12CLK_Msk         (0xff00UL)                /*!< TMR12CLK (Bitfield-Mask: 0xff)                        */
44926 #define TIMER_CTRL12_TMR12FN_Pos          (4UL)                     /*!< TMR12FN (Bit 4)                                       */
44927 #define TIMER_CTRL12_TMR12FN_Msk          (0xf0UL)                  /*!< TMR12FN (Bitfield-Mask: 0x0f)                         */
44928 #define TIMER_CTRL12_TMR12POL1_Pos        (3UL)                     /*!< TMR12POL1 (Bit 3)                                     */
44929 #define TIMER_CTRL12_TMR12POL1_Msk        (0x8UL)                   /*!< TMR12POL1 (Bitfield-Mask: 0x01)                       */
44930 #define TIMER_CTRL12_TMR12POL0_Pos        (2UL)                     /*!< TMR12POL0 (Bit 2)                                     */
44931 #define TIMER_CTRL12_TMR12POL0_Msk        (0x4UL)                   /*!< TMR12POL0 (Bitfield-Mask: 0x01)                       */
44932 #define TIMER_CTRL12_TMR12CLR_Pos         (1UL)                     /*!< TMR12CLR (Bit 1)                                      */
44933 #define TIMER_CTRL12_TMR12CLR_Msk         (0x2UL)                   /*!< TMR12CLR (Bitfield-Mask: 0x01)                        */
44934 #define TIMER_CTRL12_TMR12EN_Pos          (0UL)                     /*!< TMR12EN (Bit 0)                                       */
44935 #define TIMER_CTRL12_TMR12EN_Msk          (0x1UL)                   /*!< TMR12EN (Bitfield-Mask: 0x01)                         */
44936 /* ========================================================  TIMER12  ======================================================== */
44937 #define TIMER_TIMER12_TIMER12_Pos         (0UL)                     /*!< TIMER12 (Bit 0)                                       */
44938 #define TIMER_TIMER12_TIMER12_Msk         (0xffffffffUL)            /*!< TIMER12 (Bitfield-Mask: 0xffffffff)                   */
44939 /* =======================================================  TMR12CMP0  ======================================================= */
44940 #define TIMER_TMR12CMP0_TMR12CMP0_Pos     (0UL)                     /*!< TMR12CMP0 (Bit 0)                                     */
44941 #define TIMER_TMR12CMP0_TMR12CMP0_Msk     (0xffffffffUL)            /*!< TMR12CMP0 (Bitfield-Mask: 0xffffffff)                 */
44942 /* =======================================================  TMR12CMP1  ======================================================= */
44943 #define TIMER_TMR12CMP1_TMR12CMP1_Pos     (0UL)                     /*!< TMR12CMP1 (Bit 0)                                     */
44944 #define TIMER_TMR12CMP1_TMR12CMP1_Msk     (0xffffffffUL)            /*!< TMR12CMP1 (Bitfield-Mask: 0xffffffff)                 */
44945 /* ========================================================  MODE12  ========================================================= */
44946 #define TIMER_MODE12_TMR12TRIGSEL_Pos     (8UL)                     /*!< TMR12TRIGSEL (Bit 8)                                  */
44947 #define TIMER_MODE12_TMR12TRIGSEL_Msk     (0xff00UL)                /*!< TMR12TRIGSEL (Bitfield-Mask: 0xff)                    */
44948 /* ========================================================  CTRL13  ========================================================= */
44949 #define TIMER_CTRL13_TMR13LMT_Pos         (24UL)                    /*!< TMR13LMT (Bit 24)                                     */
44950 #define TIMER_CTRL13_TMR13LMT_Msk         (0xff000000UL)            /*!< TMR13LMT (Bitfield-Mask: 0xff)                        */
44951 #define TIMER_CTRL13_TMR13TMODE_Pos       (16UL)                    /*!< TMR13TMODE (Bit 16)                                   */
44952 #define TIMER_CTRL13_TMR13TMODE_Msk       (0x30000UL)               /*!< TMR13TMODE (Bitfield-Mask: 0x03)                      */
44953 #define TIMER_CTRL13_TMR13CLK_Pos         (8UL)                     /*!< TMR13CLK (Bit 8)                                      */
44954 #define TIMER_CTRL13_TMR13CLK_Msk         (0xff00UL)                /*!< TMR13CLK (Bitfield-Mask: 0xff)                        */
44955 #define TIMER_CTRL13_TMR13FN_Pos          (4UL)                     /*!< TMR13FN (Bit 4)                                       */
44956 #define TIMER_CTRL13_TMR13FN_Msk          (0xf0UL)                  /*!< TMR13FN (Bitfield-Mask: 0x0f)                         */
44957 #define TIMER_CTRL13_TMR13POL1_Pos        (3UL)                     /*!< TMR13POL1 (Bit 3)                                     */
44958 #define TIMER_CTRL13_TMR13POL1_Msk        (0x8UL)                   /*!< TMR13POL1 (Bitfield-Mask: 0x01)                       */
44959 #define TIMER_CTRL13_TMR13POL0_Pos        (2UL)                     /*!< TMR13POL0 (Bit 2)                                     */
44960 #define TIMER_CTRL13_TMR13POL0_Msk        (0x4UL)                   /*!< TMR13POL0 (Bitfield-Mask: 0x01)                       */
44961 #define TIMER_CTRL13_TMR13CLR_Pos         (1UL)                     /*!< TMR13CLR (Bit 1)                                      */
44962 #define TIMER_CTRL13_TMR13CLR_Msk         (0x2UL)                   /*!< TMR13CLR (Bitfield-Mask: 0x01)                        */
44963 #define TIMER_CTRL13_TMR13EN_Pos          (0UL)                     /*!< TMR13EN (Bit 0)                                       */
44964 #define TIMER_CTRL13_TMR13EN_Msk          (0x1UL)                   /*!< TMR13EN (Bitfield-Mask: 0x01)                         */
44965 /* ========================================================  TIMER13  ======================================================== */
44966 #define TIMER_TIMER13_TIMER13_Pos         (0UL)                     /*!< TIMER13 (Bit 0)                                       */
44967 #define TIMER_TIMER13_TIMER13_Msk         (0xffffffffUL)            /*!< TIMER13 (Bitfield-Mask: 0xffffffff)                   */
44968 /* =======================================================  TMR13CMP0  ======================================================= */
44969 #define TIMER_TMR13CMP0_TMR13CMP0_Pos     (0UL)                     /*!< TMR13CMP0 (Bit 0)                                     */
44970 #define TIMER_TMR13CMP0_TMR13CMP0_Msk     (0xffffffffUL)            /*!< TMR13CMP0 (Bitfield-Mask: 0xffffffff)                 */
44971 /* =======================================================  TMR13CMP1  ======================================================= */
44972 #define TIMER_TMR13CMP1_TMR13CMP1_Pos     (0UL)                     /*!< TMR13CMP1 (Bit 0)                                     */
44973 #define TIMER_TMR13CMP1_TMR13CMP1_Msk     (0xffffffffUL)            /*!< TMR13CMP1 (Bitfield-Mask: 0xffffffff)                 */
44974 /* ========================================================  MODE13  ========================================================= */
44975 #define TIMER_MODE13_TMR13TRIGSEL_Pos     (8UL)                     /*!< TMR13TRIGSEL (Bit 8)                                  */
44976 #define TIMER_MODE13_TMR13TRIGSEL_Msk     (0xff00UL)                /*!< TMR13TRIGSEL (Bitfield-Mask: 0xff)                    */
44977 /* ========================================================  CTRL14  ========================================================= */
44978 #define TIMER_CTRL14_TMR14LMT_Pos         (24UL)                    /*!< TMR14LMT (Bit 24)                                     */
44979 #define TIMER_CTRL14_TMR14LMT_Msk         (0xff000000UL)            /*!< TMR14LMT (Bitfield-Mask: 0xff)                        */
44980 #define TIMER_CTRL14_TMR14TMODE_Pos       (16UL)                    /*!< TMR14TMODE (Bit 16)                                   */
44981 #define TIMER_CTRL14_TMR14TMODE_Msk       (0x30000UL)               /*!< TMR14TMODE (Bitfield-Mask: 0x03)                      */
44982 #define TIMER_CTRL14_TMR14CLK_Pos         (8UL)                     /*!< TMR14CLK (Bit 8)                                      */
44983 #define TIMER_CTRL14_TMR14CLK_Msk         (0xff00UL)                /*!< TMR14CLK (Bitfield-Mask: 0xff)                        */
44984 #define TIMER_CTRL14_TMR14FN_Pos          (4UL)                     /*!< TMR14FN (Bit 4)                                       */
44985 #define TIMER_CTRL14_TMR14FN_Msk          (0xf0UL)                  /*!< TMR14FN (Bitfield-Mask: 0x0f)                         */
44986 #define TIMER_CTRL14_TMR14POL1_Pos        (3UL)                     /*!< TMR14POL1 (Bit 3)                                     */
44987 #define TIMER_CTRL14_TMR14POL1_Msk        (0x8UL)                   /*!< TMR14POL1 (Bitfield-Mask: 0x01)                       */
44988 #define TIMER_CTRL14_TMR14POL0_Pos        (2UL)                     /*!< TMR14POL0 (Bit 2)                                     */
44989 #define TIMER_CTRL14_TMR14POL0_Msk        (0x4UL)                   /*!< TMR14POL0 (Bitfield-Mask: 0x01)                       */
44990 #define TIMER_CTRL14_TMR14CLR_Pos         (1UL)                     /*!< TMR14CLR (Bit 1)                                      */
44991 #define TIMER_CTRL14_TMR14CLR_Msk         (0x2UL)                   /*!< TMR14CLR (Bitfield-Mask: 0x01)                        */
44992 #define TIMER_CTRL14_TMR14EN_Pos          (0UL)                     /*!< TMR14EN (Bit 0)                                       */
44993 #define TIMER_CTRL14_TMR14EN_Msk          (0x1UL)                   /*!< TMR14EN (Bitfield-Mask: 0x01)                         */
44994 /* ========================================================  TIMER14  ======================================================== */
44995 #define TIMER_TIMER14_TIMER14_Pos         (0UL)                     /*!< TIMER14 (Bit 0)                                       */
44996 #define TIMER_TIMER14_TIMER14_Msk         (0xffffffffUL)            /*!< TIMER14 (Bitfield-Mask: 0xffffffff)                   */
44997 /* =======================================================  TMR14CMP0  ======================================================= */
44998 #define TIMER_TMR14CMP0_TMR14CMP0_Pos     (0UL)                     /*!< TMR14CMP0 (Bit 0)                                     */
44999 #define TIMER_TMR14CMP0_TMR14CMP0_Msk     (0xffffffffUL)            /*!< TMR14CMP0 (Bitfield-Mask: 0xffffffff)                 */
45000 /* =======================================================  TMR14CMP1  ======================================================= */
45001 #define TIMER_TMR14CMP1_TMR14CMP1_Pos     (0UL)                     /*!< TMR14CMP1 (Bit 0)                                     */
45002 #define TIMER_TMR14CMP1_TMR14CMP1_Msk     (0xffffffffUL)            /*!< TMR14CMP1 (Bitfield-Mask: 0xffffffff)                 */
45003 /* ========================================================  MODE14  ========================================================= */
45004 #define TIMER_MODE14_TMR14TRIGSEL_Pos     (8UL)                     /*!< TMR14TRIGSEL (Bit 8)                                  */
45005 #define TIMER_MODE14_TMR14TRIGSEL_Msk     (0xff00UL)                /*!< TMR14TRIGSEL (Bitfield-Mask: 0xff)                    */
45006 /* ========================================================  CTRL15  ========================================================= */
45007 #define TIMER_CTRL15_TMR15LMT_Pos         (24UL)                    /*!< TMR15LMT (Bit 24)                                     */
45008 #define TIMER_CTRL15_TMR15LMT_Msk         (0xff000000UL)            /*!< TMR15LMT (Bitfield-Mask: 0xff)                        */
45009 #define TIMER_CTRL15_TMR15TMODE_Pos       (16UL)                    /*!< TMR15TMODE (Bit 16)                                   */
45010 #define TIMER_CTRL15_TMR15TMODE_Msk       (0x30000UL)               /*!< TMR15TMODE (Bitfield-Mask: 0x03)                      */
45011 #define TIMER_CTRL15_TMR15CLK_Pos         (8UL)                     /*!< TMR15CLK (Bit 8)                                      */
45012 #define TIMER_CTRL15_TMR15CLK_Msk         (0xff00UL)                /*!< TMR15CLK (Bitfield-Mask: 0xff)                        */
45013 #define TIMER_CTRL15_TMR15FN_Pos          (4UL)                     /*!< TMR15FN (Bit 4)                                       */
45014 #define TIMER_CTRL15_TMR15FN_Msk          (0xf0UL)                  /*!< TMR15FN (Bitfield-Mask: 0x0f)                         */
45015 #define TIMER_CTRL15_TMR15POL1_Pos        (3UL)                     /*!< TMR15POL1 (Bit 3)                                     */
45016 #define TIMER_CTRL15_TMR15POL1_Msk        (0x8UL)                   /*!< TMR15POL1 (Bitfield-Mask: 0x01)                       */
45017 #define TIMER_CTRL15_TMR15POL0_Pos        (2UL)                     /*!< TMR15POL0 (Bit 2)                                     */
45018 #define TIMER_CTRL15_TMR15POL0_Msk        (0x4UL)                   /*!< TMR15POL0 (Bitfield-Mask: 0x01)                       */
45019 #define TIMER_CTRL15_TMR15CLR_Pos         (1UL)                     /*!< TMR15CLR (Bit 1)                                      */
45020 #define TIMER_CTRL15_TMR15CLR_Msk         (0x2UL)                   /*!< TMR15CLR (Bitfield-Mask: 0x01)                        */
45021 #define TIMER_CTRL15_TMR15EN_Pos          (0UL)                     /*!< TMR15EN (Bit 0)                                       */
45022 #define TIMER_CTRL15_TMR15EN_Msk          (0x1UL)                   /*!< TMR15EN (Bitfield-Mask: 0x01)                         */
45023 /* ========================================================  TIMER15  ======================================================== */
45024 #define TIMER_TIMER15_TIMER15_Pos         (0UL)                     /*!< TIMER15 (Bit 0)                                       */
45025 #define TIMER_TIMER15_TIMER15_Msk         (0xffffffffUL)            /*!< TIMER15 (Bitfield-Mask: 0xffffffff)                   */
45026 /* =======================================================  TMR15CMP0  ======================================================= */
45027 #define TIMER_TMR15CMP0_TMR15CMP0_Pos     (0UL)                     /*!< TMR15CMP0 (Bit 0)                                     */
45028 #define TIMER_TMR15CMP0_TMR15CMP0_Msk     (0xffffffffUL)            /*!< TMR15CMP0 (Bitfield-Mask: 0xffffffff)                 */
45029 /* =======================================================  TMR15CMP1  ======================================================= */
45030 #define TIMER_TMR15CMP1_TMR15CMP1_Pos     (0UL)                     /*!< TMR15CMP1 (Bit 0)                                     */
45031 #define TIMER_TMR15CMP1_TMR15CMP1_Msk     (0xffffffffUL)            /*!< TMR15CMP1 (Bitfield-Mask: 0xffffffff)                 */
45032 /* ========================================================  MODE15  ========================================================= */
45033 #define TIMER_MODE15_TMR15TRIGSEL_Pos     (8UL)                     /*!< TMR15TRIGSEL (Bit 8)                                  */
45034 #define TIMER_MODE15_TMR15TRIGSEL_Msk     (0xff00UL)                /*!< TMR15TRIGSEL (Bitfield-Mask: 0xff)                    */
45035 
45036 
45037 /* =========================================================================================================================== */
45038 /* ================                                           UART0                                           ================ */
45039 /* =========================================================================================================================== */
45040 
45041 /* ==========================================================  DR  =========================================================== */
45042 #define UART0_DR_OEDATA_Pos               (11UL)                    /*!< OEDATA (Bit 11)                                       */
45043 #define UART0_DR_OEDATA_Msk               (0x800UL)                 /*!< OEDATA (Bitfield-Mask: 0x01)                          */
45044 #define UART0_DR_BEDATA_Pos               (10UL)                    /*!< BEDATA (Bit 10)                                       */
45045 #define UART0_DR_BEDATA_Msk               (0x400UL)                 /*!< BEDATA (Bitfield-Mask: 0x01)                          */
45046 #define UART0_DR_PEDATA_Pos               (9UL)                     /*!< PEDATA (Bit 9)                                        */
45047 #define UART0_DR_PEDATA_Msk               (0x200UL)                 /*!< PEDATA (Bitfield-Mask: 0x01)                          */
45048 #define UART0_DR_FEDATA_Pos               (8UL)                     /*!< FEDATA (Bit 8)                                        */
45049 #define UART0_DR_FEDATA_Msk               (0x100UL)                 /*!< FEDATA (Bitfield-Mask: 0x01)                          */
45050 #define UART0_DR_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
45051 #define UART0_DR_DATA_Msk                 (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
45052 /* ==========================================================  RSR  ========================================================== */
45053 #define UART0_RSR_OESTAT_Pos              (3UL)                     /*!< OESTAT (Bit 3)                                        */
45054 #define UART0_RSR_OESTAT_Msk              (0x8UL)                   /*!< OESTAT (Bitfield-Mask: 0x01)                          */
45055 #define UART0_RSR_BESTAT_Pos              (2UL)                     /*!< BESTAT (Bit 2)                                        */
45056 #define UART0_RSR_BESTAT_Msk              (0x4UL)                   /*!< BESTAT (Bitfield-Mask: 0x01)                          */
45057 #define UART0_RSR_PESTAT_Pos              (1UL)                     /*!< PESTAT (Bit 1)                                        */
45058 #define UART0_RSR_PESTAT_Msk              (0x2UL)                   /*!< PESTAT (Bitfield-Mask: 0x01)                          */
45059 #define UART0_RSR_FESTAT_Pos              (0UL)                     /*!< FESTAT (Bit 0)                                        */
45060 #define UART0_RSR_FESTAT_Msk              (0x1UL)                   /*!< FESTAT (Bitfield-Mask: 0x01)                          */
45061 /* ==========================================================  FR  =========================================================== */
45062 #define UART0_FR_TXBUSY_Pos               (8UL)                     /*!< TXBUSY (Bit 8)                                        */
45063 #define UART0_FR_TXBUSY_Msk               (0x100UL)                 /*!< TXBUSY (Bitfield-Mask: 0x01)                          */
45064 #define UART0_FR_TXFE_Pos                 (7UL)                     /*!< TXFE (Bit 7)                                          */
45065 #define UART0_FR_TXFE_Msk                 (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
45066 #define UART0_FR_RXFF_Pos                 (6UL)                     /*!< RXFF (Bit 6)                                          */
45067 #define UART0_FR_RXFF_Msk                 (0x40UL)                  /*!< RXFF (Bitfield-Mask: 0x01)                            */
45068 #define UART0_FR_TXFF_Pos                 (5UL)                     /*!< TXFF (Bit 5)                                          */
45069 #define UART0_FR_TXFF_Msk                 (0x20UL)                  /*!< TXFF (Bitfield-Mask: 0x01)                            */
45070 #define UART0_FR_RXFE_Pos                 (4UL)                     /*!< RXFE (Bit 4)                                          */
45071 #define UART0_FR_RXFE_Msk                 (0x10UL)                  /*!< RXFE (Bitfield-Mask: 0x01)                            */
45072 #define UART0_FR_BUSY_Pos                 (3UL)                     /*!< BUSY (Bit 3)                                          */
45073 #define UART0_FR_BUSY_Msk                 (0x8UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
45074 #define UART0_FR_DCD_Pos                  (2UL)                     /*!< DCD (Bit 2)                                           */
45075 #define UART0_FR_DCD_Msk                  (0x4UL)                   /*!< DCD (Bitfield-Mask: 0x01)                             */
45076 #define UART0_FR_DSR_Pos                  (1UL)                     /*!< DSR (Bit 1)                                           */
45077 #define UART0_FR_DSR_Msk                  (0x2UL)                   /*!< DSR (Bitfield-Mask: 0x01)                             */
45078 #define UART0_FR_CTS_Pos                  (0UL)                     /*!< CTS (Bit 0)                                           */
45079 #define UART0_FR_CTS_Msk                  (0x1UL)                   /*!< CTS (Bitfield-Mask: 0x01)                             */
45080 /* =========================================================  ILPR  ========================================================== */
45081 #define UART0_ILPR_ILPDVSR_Pos            (0UL)                     /*!< ILPDVSR (Bit 0)                                       */
45082 #define UART0_ILPR_ILPDVSR_Msk            (0xffUL)                  /*!< ILPDVSR (Bitfield-Mask: 0xff)                         */
45083 /* =========================================================  IBRD  ========================================================== */
45084 #define UART0_IBRD_DIVINT_Pos             (0UL)                     /*!< DIVINT (Bit 0)                                        */
45085 #define UART0_IBRD_DIVINT_Msk             (0xffffUL)                /*!< DIVINT (Bitfield-Mask: 0xffff)                        */
45086 /* =========================================================  FBRD  ========================================================== */
45087 #define UART0_FBRD_DIVFRAC_Pos            (0UL)                     /*!< DIVFRAC (Bit 0)                                       */
45088 #define UART0_FBRD_DIVFRAC_Msk            (0x3fUL)                  /*!< DIVFRAC (Bitfield-Mask: 0x3f)                         */
45089 /* =========================================================  LCRH  ========================================================== */
45090 #define UART0_LCRH_SPS_Pos                (7UL)                     /*!< SPS (Bit 7)                                           */
45091 #define UART0_LCRH_SPS_Msk                (0x80UL)                  /*!< SPS (Bitfield-Mask: 0x01)                             */
45092 #define UART0_LCRH_WLEN_Pos               (5UL)                     /*!< WLEN (Bit 5)                                          */
45093 #define UART0_LCRH_WLEN_Msk               (0x60UL)                  /*!< WLEN (Bitfield-Mask: 0x03)                            */
45094 #define UART0_LCRH_FEN_Pos                (4UL)                     /*!< FEN (Bit 4)                                           */
45095 #define UART0_LCRH_FEN_Msk                (0x10UL)                  /*!< FEN (Bitfield-Mask: 0x01)                             */
45096 #define UART0_LCRH_STP2_Pos               (3UL)                     /*!< STP2 (Bit 3)                                          */
45097 #define UART0_LCRH_STP2_Msk               (0x8UL)                   /*!< STP2 (Bitfield-Mask: 0x01)                            */
45098 #define UART0_LCRH_EPS_Pos                (2UL)                     /*!< EPS (Bit 2)                                           */
45099 #define UART0_LCRH_EPS_Msk                (0x4UL)                   /*!< EPS (Bitfield-Mask: 0x01)                             */
45100 #define UART0_LCRH_PEN_Pos                (1UL)                     /*!< PEN (Bit 1)                                           */
45101 #define UART0_LCRH_PEN_Msk                (0x2UL)                   /*!< PEN (Bitfield-Mask: 0x01)                             */
45102 #define UART0_LCRH_BRK_Pos                (0UL)                     /*!< BRK (Bit 0)                                           */
45103 #define UART0_LCRH_BRK_Msk                (0x1UL)                   /*!< BRK (Bitfield-Mask: 0x01)                             */
45104 /* ==========================================================  CR  =========================================================== */
45105 #define UART0_CR_CTSEN_Pos                (15UL)                    /*!< CTSEN (Bit 15)                                        */
45106 #define UART0_CR_CTSEN_Msk                (0x8000UL)                /*!< CTSEN (Bitfield-Mask: 0x01)                           */
45107 #define UART0_CR_RTSEN_Pos                (14UL)                    /*!< RTSEN (Bit 14)                                        */
45108 #define UART0_CR_RTSEN_Msk                (0x4000UL)                /*!< RTSEN (Bitfield-Mask: 0x01)                           */
45109 #define UART0_CR_OUT2_Pos                 (13UL)                    /*!< OUT2 (Bit 13)                                         */
45110 #define UART0_CR_OUT2_Msk                 (0x2000UL)                /*!< OUT2 (Bitfield-Mask: 0x01)                            */
45111 #define UART0_CR_OUT1_Pos                 (12UL)                    /*!< OUT1 (Bit 12)                                         */
45112 #define UART0_CR_OUT1_Msk                 (0x1000UL)                /*!< OUT1 (Bitfield-Mask: 0x01)                            */
45113 #define UART0_CR_RTS_Pos                  (11UL)                    /*!< RTS (Bit 11)                                          */
45114 #define UART0_CR_RTS_Msk                  (0x800UL)                 /*!< RTS (Bitfield-Mask: 0x01)                             */
45115 #define UART0_CR_DTR_Pos                  (10UL)                    /*!< DTR (Bit 10)                                          */
45116 #define UART0_CR_DTR_Msk                  (0x400UL)                 /*!< DTR (Bitfield-Mask: 0x01)                             */
45117 #define UART0_CR_RXE_Pos                  (9UL)                     /*!< RXE (Bit 9)                                           */
45118 #define UART0_CR_RXE_Msk                  (0x200UL)                 /*!< RXE (Bitfield-Mask: 0x01)                             */
45119 #define UART0_CR_TXE_Pos                  (8UL)                     /*!< TXE (Bit 8)                                           */
45120 #define UART0_CR_TXE_Msk                  (0x100UL)                 /*!< TXE (Bitfield-Mask: 0x01)                             */
45121 #define UART0_CR_LBE_Pos                  (7UL)                     /*!< LBE (Bit 7)                                           */
45122 #define UART0_CR_LBE_Msk                  (0x80UL)                  /*!< LBE (Bitfield-Mask: 0x01)                             */
45123 #define UART0_CR_CLKSEL_Pos               (4UL)                     /*!< CLKSEL (Bit 4)                                        */
45124 #define UART0_CR_CLKSEL_Msk               (0x70UL)                  /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
45125 #define UART0_CR_CLKEN_Pos                (3UL)                     /*!< CLKEN (Bit 3)                                         */
45126 #define UART0_CR_CLKEN_Msk                (0x8UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
45127 #define UART0_CR_SIRLP_Pos                (2UL)                     /*!< SIRLP (Bit 2)                                         */
45128 #define UART0_CR_SIRLP_Msk                (0x4UL)                   /*!< SIRLP (Bitfield-Mask: 0x01)                           */
45129 #define UART0_CR_SIREN_Pos                (1UL)                     /*!< SIREN (Bit 1)                                         */
45130 #define UART0_CR_SIREN_Msk                (0x2UL)                   /*!< SIREN (Bitfield-Mask: 0x01)                           */
45131 #define UART0_CR_UARTEN_Pos               (0UL)                     /*!< UARTEN (Bit 0)                                        */
45132 #define UART0_CR_UARTEN_Msk               (0x1UL)                   /*!< UARTEN (Bitfield-Mask: 0x01)                          */
45133 /* =========================================================  IFLS  ========================================================== */
45134 #define UART0_IFLS_RXIFLSEL_Pos           (3UL)                     /*!< RXIFLSEL (Bit 3)                                      */
45135 #define UART0_IFLS_RXIFLSEL_Msk           (0x38UL)                  /*!< RXIFLSEL (Bitfield-Mask: 0x07)                        */
45136 #define UART0_IFLS_TXIFLSEL_Pos           (0UL)                     /*!< TXIFLSEL (Bit 0)                                      */
45137 #define UART0_IFLS_TXIFLSEL_Msk           (0x7UL)                   /*!< TXIFLSEL (Bitfield-Mask: 0x07)                        */
45138 /* ==========================================================  IER  ========================================================== */
45139 #define UART0_IER_OEIM_Pos                (10UL)                    /*!< OEIM (Bit 10)                                         */
45140 #define UART0_IER_OEIM_Msk                (0x400UL)                 /*!< OEIM (Bitfield-Mask: 0x01)                            */
45141 #define UART0_IER_BEIM_Pos                (9UL)                     /*!< BEIM (Bit 9)                                          */
45142 #define UART0_IER_BEIM_Msk                (0x200UL)                 /*!< BEIM (Bitfield-Mask: 0x01)                            */
45143 #define UART0_IER_PEIM_Pos                (8UL)                     /*!< PEIM (Bit 8)                                          */
45144 #define UART0_IER_PEIM_Msk                (0x100UL)                 /*!< PEIM (Bitfield-Mask: 0x01)                            */
45145 #define UART0_IER_FEIM_Pos                (7UL)                     /*!< FEIM (Bit 7)                                          */
45146 #define UART0_IER_FEIM_Msk                (0x80UL)                  /*!< FEIM (Bitfield-Mask: 0x01)                            */
45147 #define UART0_IER_RTIM_Pos                (6UL)                     /*!< RTIM (Bit 6)                                          */
45148 #define UART0_IER_RTIM_Msk                (0x40UL)                  /*!< RTIM (Bitfield-Mask: 0x01)                            */
45149 #define UART0_IER_TXIM_Pos                (5UL)                     /*!< TXIM (Bit 5)                                          */
45150 #define UART0_IER_TXIM_Msk                (0x20UL)                  /*!< TXIM (Bitfield-Mask: 0x01)                            */
45151 #define UART0_IER_RXIM_Pos                (4UL)                     /*!< RXIM (Bit 4)                                          */
45152 #define UART0_IER_RXIM_Msk                (0x10UL)                  /*!< RXIM (Bitfield-Mask: 0x01)                            */
45153 #define UART0_IER_DSRMIM_Pos              (3UL)                     /*!< DSRMIM (Bit 3)                                        */
45154 #define UART0_IER_DSRMIM_Msk              (0x8UL)                   /*!< DSRMIM (Bitfield-Mask: 0x01)                          */
45155 #define UART0_IER_DCDMIM_Pos              (2UL)                     /*!< DCDMIM (Bit 2)                                        */
45156 #define UART0_IER_DCDMIM_Msk              (0x4UL)                   /*!< DCDMIM (Bitfield-Mask: 0x01)                          */
45157 #define UART0_IER_CTSMIM_Pos              (1UL)                     /*!< CTSMIM (Bit 1)                                        */
45158 #define UART0_IER_CTSMIM_Msk              (0x2UL)                   /*!< CTSMIM (Bitfield-Mask: 0x01)                          */
45159 #define UART0_IER_TXCMPMIM_Pos            (0UL)                     /*!< TXCMPMIM (Bit 0)                                      */
45160 #define UART0_IER_TXCMPMIM_Msk            (0x1UL)                   /*!< TXCMPMIM (Bitfield-Mask: 0x01)                        */
45161 /* ==========================================================  IES  ========================================================== */
45162 #define UART0_IES_OERIS_Pos               (10UL)                    /*!< OERIS (Bit 10)                                        */
45163 #define UART0_IES_OERIS_Msk               (0x400UL)                 /*!< OERIS (Bitfield-Mask: 0x01)                           */
45164 #define UART0_IES_BERIS_Pos               (9UL)                     /*!< BERIS (Bit 9)                                         */
45165 #define UART0_IES_BERIS_Msk               (0x200UL)                 /*!< BERIS (Bitfield-Mask: 0x01)                           */
45166 #define UART0_IES_PERIS_Pos               (8UL)                     /*!< PERIS (Bit 8)                                         */
45167 #define UART0_IES_PERIS_Msk               (0x100UL)                 /*!< PERIS (Bitfield-Mask: 0x01)                           */
45168 #define UART0_IES_FERIS_Pos               (7UL)                     /*!< FERIS (Bit 7)                                         */
45169 #define UART0_IES_FERIS_Msk               (0x80UL)                  /*!< FERIS (Bitfield-Mask: 0x01)                           */
45170 #define UART0_IES_RTRIS_Pos               (6UL)                     /*!< RTRIS (Bit 6)                                         */
45171 #define UART0_IES_RTRIS_Msk               (0x40UL)                  /*!< RTRIS (Bitfield-Mask: 0x01)                           */
45172 #define UART0_IES_TXRIS_Pos               (5UL)                     /*!< TXRIS (Bit 5)                                         */
45173 #define UART0_IES_TXRIS_Msk               (0x20UL)                  /*!< TXRIS (Bitfield-Mask: 0x01)                           */
45174 #define UART0_IES_RXRIS_Pos               (4UL)                     /*!< RXRIS (Bit 4)                                         */
45175 #define UART0_IES_RXRIS_Msk               (0x10UL)                  /*!< RXRIS (Bitfield-Mask: 0x01)                           */
45176 #define UART0_IES_DSRMRIS_Pos             (3UL)                     /*!< DSRMRIS (Bit 3)                                       */
45177 #define UART0_IES_DSRMRIS_Msk             (0x8UL)                   /*!< DSRMRIS (Bitfield-Mask: 0x01)                         */
45178 #define UART0_IES_DCDMRIS_Pos             (2UL)                     /*!< DCDMRIS (Bit 2)                                       */
45179 #define UART0_IES_DCDMRIS_Msk             (0x4UL)                   /*!< DCDMRIS (Bitfield-Mask: 0x01)                         */
45180 #define UART0_IES_CTSMRIS_Pos             (1UL)                     /*!< CTSMRIS (Bit 1)                                       */
45181 #define UART0_IES_CTSMRIS_Msk             (0x2UL)                   /*!< CTSMRIS (Bitfield-Mask: 0x01)                         */
45182 #define UART0_IES_TXCMPMRIS_Pos           (0UL)                     /*!< TXCMPMRIS (Bit 0)                                     */
45183 #define UART0_IES_TXCMPMRIS_Msk           (0x1UL)                   /*!< TXCMPMRIS (Bitfield-Mask: 0x01)                       */
45184 /* ==========================================================  MIS  ========================================================== */
45185 #define UART0_MIS_OEMIS_Pos               (10UL)                    /*!< OEMIS (Bit 10)                                        */
45186 #define UART0_MIS_OEMIS_Msk               (0x400UL)                 /*!< OEMIS (Bitfield-Mask: 0x01)                           */
45187 #define UART0_MIS_BEMIS_Pos               (9UL)                     /*!< BEMIS (Bit 9)                                         */
45188 #define UART0_MIS_BEMIS_Msk               (0x200UL)                 /*!< BEMIS (Bitfield-Mask: 0x01)                           */
45189 #define UART0_MIS_PEMIS_Pos               (8UL)                     /*!< PEMIS (Bit 8)                                         */
45190 #define UART0_MIS_PEMIS_Msk               (0x100UL)                 /*!< PEMIS (Bitfield-Mask: 0x01)                           */
45191 #define UART0_MIS_FEMIS_Pos               (7UL)                     /*!< FEMIS (Bit 7)                                         */
45192 #define UART0_MIS_FEMIS_Msk               (0x80UL)                  /*!< FEMIS (Bitfield-Mask: 0x01)                           */
45193 #define UART0_MIS_RTMIS_Pos               (6UL)                     /*!< RTMIS (Bit 6)                                         */
45194 #define UART0_MIS_RTMIS_Msk               (0x40UL)                  /*!< RTMIS (Bitfield-Mask: 0x01)                           */
45195 #define UART0_MIS_TXMIS_Pos               (5UL)                     /*!< TXMIS (Bit 5)                                         */
45196 #define UART0_MIS_TXMIS_Msk               (0x20UL)                  /*!< TXMIS (Bitfield-Mask: 0x01)                           */
45197 #define UART0_MIS_RXMIS_Pos               (4UL)                     /*!< RXMIS (Bit 4)                                         */
45198 #define UART0_MIS_RXMIS_Msk               (0x10UL)                  /*!< RXMIS (Bitfield-Mask: 0x01)                           */
45199 #define UART0_MIS_DSRMMIS_Pos             (3UL)                     /*!< DSRMMIS (Bit 3)                                       */
45200 #define UART0_MIS_DSRMMIS_Msk             (0x8UL)                   /*!< DSRMMIS (Bitfield-Mask: 0x01)                         */
45201 #define UART0_MIS_DCDMMIS_Pos             (2UL)                     /*!< DCDMMIS (Bit 2)                                       */
45202 #define UART0_MIS_DCDMMIS_Msk             (0x4UL)                   /*!< DCDMMIS (Bitfield-Mask: 0x01)                         */
45203 #define UART0_MIS_CTSMMIS_Pos             (1UL)                     /*!< CTSMMIS (Bit 1)                                       */
45204 #define UART0_MIS_CTSMMIS_Msk             (0x2UL)                   /*!< CTSMMIS (Bitfield-Mask: 0x01)                         */
45205 #define UART0_MIS_TXCMPMMIS_Pos           (0UL)                     /*!< TXCMPMMIS (Bit 0)                                     */
45206 #define UART0_MIS_TXCMPMMIS_Msk           (0x1UL)                   /*!< TXCMPMMIS (Bitfield-Mask: 0x01)                       */
45207 /* ==========================================================  IEC  ========================================================== */
45208 #define UART0_IEC_OEIC_Pos                (10UL)                    /*!< OEIC (Bit 10)                                         */
45209 #define UART0_IEC_OEIC_Msk                (0x400UL)                 /*!< OEIC (Bitfield-Mask: 0x01)                            */
45210 #define UART0_IEC_BEIC_Pos                (9UL)                     /*!< BEIC (Bit 9)                                          */
45211 #define UART0_IEC_BEIC_Msk                (0x200UL)                 /*!< BEIC (Bitfield-Mask: 0x01)                            */
45212 #define UART0_IEC_PEIC_Pos                (8UL)                     /*!< PEIC (Bit 8)                                          */
45213 #define UART0_IEC_PEIC_Msk                (0x100UL)                 /*!< PEIC (Bitfield-Mask: 0x01)                            */
45214 #define UART0_IEC_FEIC_Pos                (7UL)                     /*!< FEIC (Bit 7)                                          */
45215 #define UART0_IEC_FEIC_Msk                (0x80UL)                  /*!< FEIC (Bitfield-Mask: 0x01)                            */
45216 #define UART0_IEC_RTIC_Pos                (6UL)                     /*!< RTIC (Bit 6)                                          */
45217 #define UART0_IEC_RTIC_Msk                (0x40UL)                  /*!< RTIC (Bitfield-Mask: 0x01)                            */
45218 #define UART0_IEC_TXIC_Pos                (5UL)                     /*!< TXIC (Bit 5)                                          */
45219 #define UART0_IEC_TXIC_Msk                (0x20UL)                  /*!< TXIC (Bitfield-Mask: 0x01)                            */
45220 #define UART0_IEC_RXIC_Pos                (4UL)                     /*!< RXIC (Bit 4)                                          */
45221 #define UART0_IEC_RXIC_Msk                (0x10UL)                  /*!< RXIC (Bitfield-Mask: 0x01)                            */
45222 #define UART0_IEC_DSRMIC_Pos              (3UL)                     /*!< DSRMIC (Bit 3)                                        */
45223 #define UART0_IEC_DSRMIC_Msk              (0x8UL)                   /*!< DSRMIC (Bitfield-Mask: 0x01)                          */
45224 #define UART0_IEC_DCDMIC_Pos              (2UL)                     /*!< DCDMIC (Bit 2)                                        */
45225 #define UART0_IEC_DCDMIC_Msk              (0x4UL)                   /*!< DCDMIC (Bitfield-Mask: 0x01)                          */
45226 #define UART0_IEC_CTSMIC_Pos              (1UL)                     /*!< CTSMIC (Bit 1)                                        */
45227 #define UART0_IEC_CTSMIC_Msk              (0x2UL)                   /*!< CTSMIC (Bitfield-Mask: 0x01)                          */
45228 #define UART0_IEC_TXCMPMIC_Pos            (0UL)                     /*!< TXCMPMIC (Bit 0)                                      */
45229 #define UART0_IEC_TXCMPMIC_Msk            (0x1UL)                   /*!< TXCMPMIC (Bitfield-Mask: 0x01)                        */
45230 
45231 
45232 /* =========================================================================================================================== */
45233 /* ================                                          USBPHY                                           ================ */
45234 /* =========================================================================================================================== */
45235 
45236 /* =========================================================  REG00  ========================================================= */
45237 #define USBPHY_REG00_BF75_Pos             (5UL)                     /*!< BF75 (Bit 5)                                          */
45238 #define USBPHY_REG00_BF75_Msk             (0xe0UL)                  /*!< BF75 (Bitfield-Mask: 0x07)                            */
45239 #define USBPHY_REG00_BF43_Pos             (3UL)                     /*!< BF43 (Bit 3)                                          */
45240 #define USBPHY_REG00_BF43_Msk             (0x18UL)                  /*!< BF43 (Bitfield-Mask: 0x03)                            */
45241 #define USBPHY_REG00_BF20_Pos             (0UL)                     /*!< BF20 (Bit 0)                                          */
45242 #define USBPHY_REG00_BF20_Msk             (0x7UL)                   /*!< BF20 (Bitfield-Mask: 0x07)                            */
45243 /* =========================================================  REG04  ========================================================= */
45244 #define USBPHY_REG04_BF76_Pos             (6UL)                     /*!< BF76 (Bit 6)                                          */
45245 #define USBPHY_REG04_BF76_Msk             (0xc0UL)                  /*!< BF76 (Bitfield-Mask: 0x03)                            */
45246 #define USBPHY_REG04_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
45247 #define USBPHY_REG04_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
45248 #define USBPHY_REG04_BF43_Pos             (3UL)                     /*!< BF43 (Bit 3)                                          */
45249 #define USBPHY_REG04_BF43_Msk             (0x18UL)                  /*!< BF43 (Bitfield-Mask: 0x03)                            */
45250 #define USBPHY_REG04_BF20_Pos             (0UL)                     /*!< BF20 (Bit 0)                                          */
45251 #define USBPHY_REG04_BF20_Msk             (0x7UL)                   /*!< BF20 (Bitfield-Mask: 0x07)                            */
45252 /* =========================================================  REG08  ========================================================= */
45253 #define USBPHY_REG08_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
45254 #define USBPHY_REG08_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
45255 #define USBPHY_REG08_BF64_Pos             (4UL)                     /*!< BF64 (Bit 4)                                          */
45256 #define USBPHY_REG08_BF64_Msk             (0x70UL)                  /*!< BF64 (Bitfield-Mask: 0x07)                            */
45257 #define USBPHY_REG08_BF30_Pos             (0UL)                     /*!< BF30 (Bit 0)                                          */
45258 #define USBPHY_REG08_BF30_Msk             (0xfUL)                   /*!< BF30 (Bitfield-Mask: 0x0f)                            */
45259 /* =========================================================  REG0C  ========================================================= */
45260 #define USBPHY_REG0C_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
45261 #define USBPHY_REG0C_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
45262 #define USBPHY_REG0C_BF62_Pos             (2UL)                     /*!< BF62 (Bit 2)                                          */
45263 #define USBPHY_REG0C_BF62_Msk             (0x7cUL)                  /*!< BF62 (Bitfield-Mask: 0x1f)                            */
45264 #define USBPHY_REG0C_BF10_Pos             (0UL)                     /*!< BF10 (Bit 0)                                          */
45265 #define USBPHY_REG0C_BF10_Msk             (0x3UL)                   /*!< BF10 (Bitfield-Mask: 0x03)                            */
45266 /* =========================================================  REG10  ========================================================= */
45267 #define USBPHY_REG10_BF74_Pos             (4UL)                     /*!< BF74 (Bit 4)                                          */
45268 #define USBPHY_REG10_BF74_Msk             (0xf0UL)                  /*!< BF74 (Bitfield-Mask: 0x0f)                            */
45269 #define USBPHY_REG10_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
45270 #define USBPHY_REG10_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
45271 #define USBPHY_REG10_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
45272 #define USBPHY_REG10_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
45273 #define USBPHY_REG10_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
45274 #define USBPHY_REG10_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
45275 #define USBPHY_REG10_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45276 #define USBPHY_REG10_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45277 /* =========================================================  REG14  ========================================================= */
45278 #define USBPHY_REG14_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
45279 #define USBPHY_REG14_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
45280 #define USBPHY_REG14_BF66_Pos             (6UL)                     /*!< BF66 (Bit 6)                                          */
45281 #define USBPHY_REG14_BF66_Msk             (0x40UL)                  /*!< BF66 (Bitfield-Mask: 0x01)                            */
45282 #define USBPHY_REG14_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
45283 #define USBPHY_REG14_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
45284 #define USBPHY_REG14_BF42_Pos             (2UL)                     /*!< BF42 (Bit 2)                                          */
45285 #define USBPHY_REG14_BF42_Msk             (0x1cUL)                  /*!< BF42 (Bitfield-Mask: 0x07)                            */
45286 #define USBPHY_REG14_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
45287 #define USBPHY_REG14_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
45288 #define USBPHY_REG14_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45289 #define USBPHY_REG14_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45290 /* =========================================================  REG18  ========================================================= */
45291 #define USBPHY_REG18_BF73_Pos             (3UL)                     /*!< BF73 (Bit 3)                                          */
45292 #define USBPHY_REG18_BF73_Msk             (0xf8UL)                  /*!< BF73 (Bitfield-Mask: 0x1f)                            */
45293 #define USBPHY_REG18_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
45294 #define USBPHY_REG18_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
45295 #define USBPHY_REG18_BF10_Pos             (0UL)                     /*!< BF10 (Bit 0)                                          */
45296 #define USBPHY_REG18_BF10_Msk             (0x3UL)                   /*!< BF10 (Bitfield-Mask: 0x03)                            */
45297 /* =========================================================  REG1C  ========================================================= */
45298 #define USBPHY_REG1C_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
45299 #define USBPHY_REG1C_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
45300 #define USBPHY_REG1C_BF66_Pos             (6UL)                     /*!< BF66 (Bit 6)                                          */
45301 #define USBPHY_REG1C_BF66_Msk             (0x40UL)                  /*!< BF66 (Bitfield-Mask: 0x01)                            */
45302 #define USBPHY_REG1C_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
45303 #define USBPHY_REG1C_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
45304 #define USBPHY_REG1C_BF44_Pos             (4UL)                     /*!< BF44 (Bit 4)                                          */
45305 #define USBPHY_REG1C_BF44_Msk             (0x10UL)                  /*!< BF44 (Bitfield-Mask: 0x01)                            */
45306 #define USBPHY_REG1C_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
45307 #define USBPHY_REG1C_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
45308 #define USBPHY_REG1C_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
45309 #define USBPHY_REG1C_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
45310 #define USBPHY_REG1C_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
45311 #define USBPHY_REG1C_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
45312 #define USBPHY_REG1C_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45313 #define USBPHY_REG1C_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45314 /* =========================================================  REG20  ========================================================= */
45315 #define USBPHY_REG20_BF76_Pos             (6UL)                     /*!< BF76 (Bit 6)                                          */
45316 #define USBPHY_REG20_BF76_Msk             (0xc0UL)                  /*!< BF76 (Bitfield-Mask: 0x03)                            */
45317 #define USBPHY_REG20_BF54_Pos             (4UL)                     /*!< BF54 (Bit 4)                                          */
45318 #define USBPHY_REG20_BF54_Msk             (0x30UL)                  /*!< BF54 (Bitfield-Mask: 0x03)                            */
45319 #define USBPHY_REG20_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
45320 #define USBPHY_REG20_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
45321 #define USBPHY_REG20_BF20_Pos             (0UL)                     /*!< BF20 (Bit 0)                                          */
45322 #define USBPHY_REG20_BF20_Msk             (0x7UL)                   /*!< BF20 (Bitfield-Mask: 0x07)                            */
45323 /* =========================================================  REG24  ========================================================= */
45324 #define USBPHY_REG24_BF71_Pos             (1UL)                     /*!< BF71 (Bit 1)                                          */
45325 #define USBPHY_REG24_BF71_Msk             (0xfeUL)                  /*!< BF71 (Bitfield-Mask: 0x7f)                            */
45326 #define USBPHY_REG24_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45327 #define USBPHY_REG24_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45328 /* =========================================================  REG28  ========================================================= */
45329 #define USBPHY_REG28_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45330 #define USBPHY_REG28_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45331 /* =========================================================  REG2C  ========================================================= */
45332 #define USBPHY_REG2C_BF75_Pos             (5UL)                     /*!< BF75 (Bit 5)                                          */
45333 #define USBPHY_REG2C_BF75_Msk             (0xe0UL)                  /*!< BF75 (Bitfield-Mask: 0x07)                            */
45334 #define USBPHY_REG2C_BF44_Pos             (4UL)                     /*!< BF44 (Bit 4)                                          */
45335 #define USBPHY_REG2C_BF44_Msk             (0x10UL)                  /*!< BF44 (Bitfield-Mask: 0x01)                            */
45336 #define USBPHY_REG2C_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
45337 #define USBPHY_REG2C_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
45338 #define USBPHY_REG2C_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
45339 #define USBPHY_REG2C_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
45340 #define USBPHY_REG2C_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
45341 #define USBPHY_REG2C_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
45342 #define USBPHY_REG2C_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45343 #define USBPHY_REG2C_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45344 /* =========================================================  REG30  ========================================================= */
45345 #define USBPHY_REG30_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45346 #define USBPHY_REG30_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45347 /* =========================================================  REG34  ========================================================= */
45348 #define USBPHY_REG34_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45349 #define USBPHY_REG34_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45350 /* =========================================================  REG38  ========================================================= */
45351 #define USBPHY_REG38_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45352 #define USBPHY_REG38_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45353 /* =========================================================  REG3C  ========================================================= */
45354 #define USBPHY_REG3C_BF75_Pos             (5UL)                     /*!< BF75 (Bit 5)                                          */
45355 #define USBPHY_REG3C_BF75_Msk             (0xe0UL)                  /*!< BF75 (Bitfield-Mask: 0x07)                            */
45356 #define USBPHY_REG3C_BF42_Pos             (2UL)                     /*!< BF42 (Bit 2)                                          */
45357 #define USBPHY_REG3C_BF42_Msk             (0x1cUL)                  /*!< BF42 (Bitfield-Mask: 0x07)                            */
45358 #define USBPHY_REG3C_BF10_Pos             (0UL)                     /*!< BF10 (Bit 0)                                          */
45359 #define USBPHY_REG3C_BF10_Msk             (0x3UL)                   /*!< BF10 (Bitfield-Mask: 0x03)                            */
45360 /* =========================================================  REG40  ========================================================= */
45361 #define USBPHY_REG40_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
45362 #define USBPHY_REG40_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
45363 #define USBPHY_REG40_BF60_Pos             (0UL)                     /*!< BF60 (Bit 0)                                          */
45364 #define USBPHY_REG40_BF60_Msk             (0x7fUL)                  /*!< BF60 (Bitfield-Mask: 0x7f)                            */
45365 /* =========================================================  REG44  ========================================================= */
45366 #define USBPHY_REG44_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
45367 #define USBPHY_REG44_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
45368 #define USBPHY_REG44_BF65_Pos             (5UL)                     /*!< BF65 (Bit 5)                                          */
45369 #define USBPHY_REG44_BF65_Msk             (0x60UL)                  /*!< BF65 (Bitfield-Mask: 0x03)                            */
45370 #define USBPHY_REG44_BF42_Pos             (2UL)                     /*!< BF42 (Bit 2)                                          */
45371 #define USBPHY_REG44_BF42_Msk             (0x1cUL)                  /*!< BF42 (Bitfield-Mask: 0x07)                            */
45372 #define USBPHY_REG44_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
45373 #define USBPHY_REG44_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
45374 #define USBPHY_REG44_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45375 #define USBPHY_REG44_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45376 /* =========================================================  REG48  ========================================================= */
45377 #define USBPHY_REG48_BF71_Pos             (1UL)                     /*!< BF71 (Bit 1)                                          */
45378 #define USBPHY_REG48_BF71_Msk             (0xfeUL)                  /*!< BF71 (Bitfield-Mask: 0x7f)                            */
45379 #define USBPHY_REG48_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45380 #define USBPHY_REG48_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45381 /* =========================================================  REG4C  ========================================================= */
45382 #define USBPHY_REG4C_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45383 #define USBPHY_REG4C_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45384 /* =========================================================  REG50  ========================================================= */
45385 #define USBPHY_REG50_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45386 #define USBPHY_REG50_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45387 /* =========================================================  REG54  ========================================================= */
45388 #define USBPHY_REG54_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45389 #define USBPHY_REG54_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45390 /* =========================================================  REG58  ========================================================= */
45391 #define USBPHY_REG58_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45392 #define USBPHY_REG58_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45393 /* =========================================================  REG5C  ========================================================= */
45394 #define USBPHY_REG5C_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45395 #define USBPHY_REG5C_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45396 /* =========================================================  REG60  ========================================================= */
45397 #define USBPHY_REG60_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45398 #define USBPHY_REG60_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45399 /* =========================================================  REG64  ========================================================= */
45400 #define USBPHY_REG64_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45401 #define USBPHY_REG64_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45402 /* =========================================================  REG68  ========================================================= */
45403 #define USBPHY_REG68_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45404 #define USBPHY_REG68_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45405 /* =========================================================  REG6C  ========================================================= */
45406 #define USBPHY_REG6C_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45407 #define USBPHY_REG6C_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45408 /* =========================================================  REG70  ========================================================= */
45409 #define USBPHY_REG70_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45410 #define USBPHY_REG70_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45411 /* =========================================================  REG74  ========================================================= */
45412 #define USBPHY_REG74_BF74_Pos             (4UL)                     /*!< BF74 (Bit 4)                                          */
45413 #define USBPHY_REG74_BF74_Msk             (0xf0UL)                  /*!< BF74 (Bitfield-Mask: 0x0f)                            */
45414 #define USBPHY_REG74_BF31_Pos             (1UL)                     /*!< BF31 (Bit 1)                                          */
45415 #define USBPHY_REG74_BF31_Msk             (0xeUL)                   /*!< BF31 (Bitfield-Mask: 0x07)                            */
45416 #define USBPHY_REG74_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45417 #define USBPHY_REG74_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45418 /* =========================================================  REG78  ========================================================= */
45419 #define USBPHY_REG78_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45420 #define USBPHY_REG78_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45421 /* =========================================================  REG7C  ========================================================= */
45422 #define USBPHY_REG7C_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
45423 #define USBPHY_REG7C_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
45424 #define USBPHY_REG7C_BF66_Pos             (6UL)                     /*!< BF66 (Bit 6)                                          */
45425 #define USBPHY_REG7C_BF66_Msk             (0x40UL)                  /*!< BF66 (Bitfield-Mask: 0x01)                            */
45426 #define USBPHY_REG7C_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
45427 #define USBPHY_REG7C_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
45428 #define USBPHY_REG7C_BF40_Pos             (0UL)                     /*!< BF40 (Bit 0)                                          */
45429 #define USBPHY_REG7C_BF40_Msk             (0x1fUL)                  /*!< BF40 (Bitfield-Mask: 0x1f)                            */
45430 /* =========================================================  REG80  ========================================================= */
45431 #define USBPHY_REG80_BF73_Pos             (3UL)                     /*!< BF73 (Bit 3)                                          */
45432 #define USBPHY_REG80_BF73_Msk             (0xf8UL)                  /*!< BF73 (Bitfield-Mask: 0x1f)                            */
45433 #define USBPHY_REG80_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
45434 #define USBPHY_REG80_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
45435 #define USBPHY_REG80_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
45436 #define USBPHY_REG80_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
45437 #define USBPHY_REG80_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
45438 #define USBPHY_REG80_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
45439 /* =========================================================  REG84  ========================================================= */
45440 #define USBPHY_REG84_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
45441 #define USBPHY_REG84_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
45442 
45443 
45444 /* =========================================================================================================================== */
45445 /* ================                                            USB                                            ================ */
45446 /* =========================================================================================================================== */
45447 
45448 /* =========================================================  CFG0  ========================================================== */
45449 #define USB_CFG0_EP5InIntStat_Pos         (21UL)                    /*!< EP5InIntStat (Bit 21)                                 */
45450 #define USB_CFG0_EP5InIntStat_Msk         (0x200000UL)              /*!< EP5InIntStat (Bitfield-Mask: 0x01)                    */
45451 #define USB_CFG0_EP4InIntStat_Pos         (20UL)                    /*!< EP4InIntStat (Bit 20)                                 */
45452 #define USB_CFG0_EP4InIntStat_Msk         (0x100000UL)              /*!< EP4InIntStat (Bitfield-Mask: 0x01)                    */
45453 #define USB_CFG0_EP3InIntStat_Pos         (19UL)                    /*!< EP3InIntStat (Bit 19)                                 */
45454 #define USB_CFG0_EP3InIntStat_Msk         (0x80000UL)               /*!< EP3InIntStat (Bitfield-Mask: 0x01)                    */
45455 #define USB_CFG0_EP2InIntStat_Pos         (18UL)                    /*!< EP2InIntStat (Bit 18)                                 */
45456 #define USB_CFG0_EP2InIntStat_Msk         (0x40000UL)               /*!< EP2InIntStat (Bitfield-Mask: 0x01)                    */
45457 #define USB_CFG0_EP1InIntStat_Pos         (17UL)                    /*!< EP1InIntStat (Bit 17)                                 */
45458 #define USB_CFG0_EP1InIntStat_Msk         (0x20000UL)               /*!< EP1InIntStat (Bitfield-Mask: 0x01)                    */
45459 #define USB_CFG0_EP0InIntStat_Pos         (16UL)                    /*!< EP0InIntStat (Bit 16)                                 */
45460 #define USB_CFG0_EP0InIntStat_Msk         (0x10000UL)               /*!< EP0InIntStat (Bitfield-Mask: 0x01)                    */
45461 #define USB_CFG0_ISOUpdate_Pos            (15UL)                    /*!< ISOUpdate (Bit 15)                                    */
45462 #define USB_CFG0_ISOUpdate_Msk            (0x8000UL)                /*!< ISOUpdate (Bitfield-Mask: 0x01)                       */
45463 #define USB_CFG0_AMSPECIFIC_Pos           (14UL)                    /*!< AMSPECIFIC (Bit 14)                                   */
45464 #define USB_CFG0_AMSPECIFIC_Msk           (0x4000UL)                /*!< AMSPECIFIC (Bitfield-Mask: 0x01)                      */
45465 #define USB_CFG0_HSEnab_Pos               (13UL)                    /*!< HSEnab (Bit 13)                                       */
45466 #define USB_CFG0_HSEnab_Msk               (0x2000UL)                /*!< HSEnab (Bitfield-Mask: 0x01)                          */
45467 #define USB_CFG0_HSMode_Pos               (12UL)                    /*!< HSMode (Bit 12)                                       */
45468 #define USB_CFG0_HSMode_Msk               (0x1000UL)                /*!< HSMode (Bitfield-Mask: 0x01)                          */
45469 #define USB_CFG0_Reset_Pos                (11UL)                    /*!< Reset (Bit 11)                                        */
45470 #define USB_CFG0_Reset_Msk                (0x800UL)                 /*!< Reset (Bitfield-Mask: 0x01)                           */
45471 #define USB_CFG0_Resume_Pos               (10UL)                    /*!< Resume (Bit 10)                                       */
45472 #define USB_CFG0_Resume_Msk               (0x400UL)                 /*!< Resume (Bitfield-Mask: 0x01)                          */
45473 #define USB_CFG0_Suspen_Pos               (9UL)                     /*!< Suspen (Bit 9)                                        */
45474 #define USB_CFG0_Suspen_Msk               (0x200UL)                 /*!< Suspen (Bitfield-Mask: 0x01)                          */
45475 #define USB_CFG0_Enabl_Pos                (8UL)                     /*!< Enabl (Bit 8)                                         */
45476 #define USB_CFG0_Enabl_Msk                (0x100UL)                 /*!< Enabl (Bitfield-Mask: 0x01)                           */
45477 #define USB_CFG0_Update_Pos               (7UL)                     /*!< Update (Bit 7)                                        */
45478 #define USB_CFG0_Update_Msk               (0x80UL)                  /*!< Update (Bitfield-Mask: 0x01)                          */
45479 #define USB_CFG0_FuncAddr_Pos             (0UL)                     /*!< FuncAddr (Bit 0)                                      */
45480 #define USB_CFG0_FuncAddr_Msk             (0x7fUL)                  /*!< FuncAddr (Bitfield-Mask: 0x7f)                        */
45481 /* =========================================================  CFG1  ========================================================== */
45482 #define USB_CFG1_EP5InIntEn_Pos           (21UL)                    /*!< EP5InIntEn (Bit 21)                                   */
45483 #define USB_CFG1_EP5InIntEn_Msk           (0x200000UL)              /*!< EP5InIntEn (Bitfield-Mask: 0x01)                      */
45484 #define USB_CFG1_EP4InIntEn_Pos           (20UL)                    /*!< EP4InIntEn (Bit 20)                                   */
45485 #define USB_CFG1_EP4InIntEn_Msk           (0x100000UL)              /*!< EP4InIntEn (Bitfield-Mask: 0x01)                      */
45486 #define USB_CFG1_EP3InIntEn_Pos           (19UL)                    /*!< EP3InIntEn (Bit 19)                                   */
45487 #define USB_CFG1_EP3InIntEn_Msk           (0x80000UL)               /*!< EP3InIntEn (Bitfield-Mask: 0x01)                      */
45488 #define USB_CFG1_EP2InIntEn_Pos           (18UL)                    /*!< EP2InIntEn (Bit 18)                                   */
45489 #define USB_CFG1_EP2InIntEn_Msk           (0x40000UL)               /*!< EP2InIntEn (Bitfield-Mask: 0x01)                      */
45490 #define USB_CFG1_EP1InIntEn_Pos           (17UL)                    /*!< EP1InIntEn (Bit 17)                                   */
45491 #define USB_CFG1_EP1InIntEn_Msk           (0x20000UL)               /*!< EP1InIntEn (Bitfield-Mask: 0x01)                      */
45492 #define USB_CFG1_EP0InIntEn_Pos           (16UL)                    /*!< EP0InIntEn (Bit 16)                                   */
45493 #define USB_CFG1_EP0InIntEn_Msk           (0x10000UL)               /*!< EP0InIntEn (Bitfield-Mask: 0x01)                      */
45494 #define USB_CFG1_EP5OutIntStat_Pos        (5UL)                     /*!< EP5OutIntStat (Bit 5)                                 */
45495 #define USB_CFG1_EP5OutIntStat_Msk        (0x20UL)                  /*!< EP5OutIntStat (Bitfield-Mask: 0x01)                   */
45496 #define USB_CFG1_EP4OutIntStat_Pos        (4UL)                     /*!< EP4OutIntStat (Bit 4)                                 */
45497 #define USB_CFG1_EP4OutIntStat_Msk        (0x10UL)                  /*!< EP4OutIntStat (Bitfield-Mask: 0x01)                   */
45498 #define USB_CFG1_EP3OutIntStat_Pos        (3UL)                     /*!< EP3OutIntStat (Bit 3)                                 */
45499 #define USB_CFG1_EP3OutIntStat_Msk        (0x8UL)                   /*!< EP3OutIntStat (Bitfield-Mask: 0x01)                   */
45500 #define USB_CFG1_EP2OutIntStat_Pos        (2UL)                     /*!< EP2OutIntStat (Bit 2)                                 */
45501 #define USB_CFG1_EP2OutIntStat_Msk        (0x4UL)                   /*!< EP2OutIntStat (Bitfield-Mask: 0x01)                   */
45502 #define USB_CFG1_EP1OutIntStat_Pos        (1UL)                     /*!< EP1OutIntStat (Bit 1)                                 */
45503 #define USB_CFG1_EP1OutIntStat_Msk        (0x2UL)                   /*!< EP1OutIntStat (Bitfield-Mask: 0x01)                   */
45504 #define USB_CFG1_EP0OutIntStat_Pos        (0UL)                     /*!< EP0OutIntStat (Bit 0)                                 */
45505 #define USB_CFG1_EP0OutIntStat_Msk        (0x1UL)                   /*!< EP0OutIntStat (Bitfield-Mask: 0x01)                   */
45506 /* =========================================================  CFG2  ========================================================== */
45507 #define USB_CFG2_SOFE_Pos                 (27UL)                    /*!< SOFE (Bit 27)                                         */
45508 #define USB_CFG2_SOFE_Msk                 (0x8000000UL)             /*!< SOFE (Bitfield-Mask: 0x01)                            */
45509 #define USB_CFG2_ResetE_Pos               (26UL)                    /*!< ResetE (Bit 26)                                       */
45510 #define USB_CFG2_ResetE_Msk               (0x4000000UL)             /*!< ResetE (Bitfield-Mask: 0x01)                          */
45511 #define USB_CFG2_ResumeE_Pos              (25UL)                    /*!< ResumeE (Bit 25)                                      */
45512 #define USB_CFG2_ResumeE_Msk              (0x2000000UL)             /*!< ResumeE (Bitfield-Mask: 0x01)                         */
45513 #define USB_CFG2_SuspendE_Pos             (24UL)                    /*!< SuspendE (Bit 24)                                     */
45514 #define USB_CFG2_SuspendE_Msk             (0x1000000UL)             /*!< SuspendE (Bitfield-Mask: 0x01)                        */
45515 #define USB_CFG2_SOF_Pos                  (19UL)                    /*!< SOF (Bit 19)                                          */
45516 #define USB_CFG2_SOF_Msk                  (0x80000UL)               /*!< SOF (Bitfield-Mask: 0x01)                             */
45517 #define USB_CFG2_Reset_Pos                (18UL)                    /*!< Reset (Bit 18)                                        */
45518 #define USB_CFG2_Reset_Msk                (0x40000UL)               /*!< Reset (Bitfield-Mask: 0x01)                           */
45519 #define USB_CFG2_Resume_Pos               (17UL)                    /*!< Resume (Bit 17)                                       */
45520 #define USB_CFG2_Resume_Msk               (0x20000UL)               /*!< Resume (Bitfield-Mask: 0x01)                          */
45521 #define USB_CFG2_Suspend_Pos              (16UL)                    /*!< Suspend (Bit 16)                                      */
45522 #define USB_CFG2_Suspend_Msk              (0x10000UL)               /*!< Suspend (Bitfield-Mask: 0x01)                         */
45523 #define USB_CFG2_EP5OutIntEn_Pos          (5UL)                     /*!< EP5OutIntEn (Bit 5)                                   */
45524 #define USB_CFG2_EP5OutIntEn_Msk          (0x20UL)                  /*!< EP5OutIntEn (Bitfield-Mask: 0x01)                     */
45525 #define USB_CFG2_EP4OutIntEn_Pos          (4UL)                     /*!< EP4OutIntEn (Bit 4)                                   */
45526 #define USB_CFG2_EP4OutIntEn_Msk          (0x10UL)                  /*!< EP4OutIntEn (Bitfield-Mask: 0x01)                     */
45527 #define USB_CFG2_EP3OutIntEn_Pos          (3UL)                     /*!< EP3OutIntEn (Bit 3)                                   */
45528 #define USB_CFG2_EP3OutIntEn_Msk          (0x8UL)                   /*!< EP3OutIntEn (Bitfield-Mask: 0x01)                     */
45529 #define USB_CFG2_EP2OutIntEn_Pos          (2UL)                     /*!< EP2OutIntEn (Bit 2)                                   */
45530 #define USB_CFG2_EP2OutIntEn_Msk          (0x4UL)                   /*!< EP2OutIntEn (Bitfield-Mask: 0x01)                     */
45531 #define USB_CFG2_EP1OutIntEn_Pos          (1UL)                     /*!< EP1OutIntEn (Bit 1)                                   */
45532 #define USB_CFG2_EP1OutIntEn_Msk          (0x2UL)                   /*!< EP1OutIntEn (Bitfield-Mask: 0x01)                     */
45533 #define USB_CFG2_EP0OutIntEn_Pos          (0UL)                     /*!< EP0OutIntEn (Bit 0)                                   */
45534 #define USB_CFG2_EP0OutIntEn_Msk          (0x1UL)                   /*!< EP0OutIntEn (Bitfield-Mask: 0x01)                     */
45535 /* =========================================================  CFG3  ========================================================== */
45536 #define USB_CFG3_ForceFS_Pos              (29UL)                    /*!< ForceFS (Bit 29)                                      */
45537 #define USB_CFG3_ForceFS_Msk              (0x20000000UL)            /*!< ForceFS (Bitfield-Mask: 0x01)                         */
45538 #define USB_CFG3_ForceHS_Pos              (28UL)                    /*!< ForceHS (Bit 28)                                      */
45539 #define USB_CFG3_ForceHS_Msk              (0x10000000UL)            /*!< ForceHS (Bitfield-Mask: 0x01)                         */
45540 #define USB_CFG3_TestPacket_Pos           (27UL)                    /*!< TestPacket (Bit 27)                                   */
45541 #define USB_CFG3_TestPacket_Msk           (0x8000000UL)             /*!< TestPacket (Bitfield-Mask: 0x01)                      */
45542 #define USB_CFG3_TestK_Pos                (26UL)                    /*!< TestK (Bit 26)                                        */
45543 #define USB_CFG3_TestK_Msk                (0x4000000UL)             /*!< TestK (Bitfield-Mask: 0x01)                           */
45544 #define USB_CFG3_TestJ_Pos                (25UL)                    /*!< TestJ (Bit 25)                                        */
45545 #define USB_CFG3_TestJ_Msk                (0x2000000UL)             /*!< TestJ (Bitfield-Mask: 0x01)                           */
45546 #define USB_CFG3_TestSE0NAK_Pos           (24UL)                    /*!< TestSE0NAK (Bit 24)                                   */
45547 #define USB_CFG3_TestSE0NAK_Msk           (0x1000000UL)             /*!< TestSE0NAK (Bitfield-Mask: 0x01)                      */
45548 #define USB_CFG3_ENDPOINT_Pos             (16UL)                    /*!< ENDPOINT (Bit 16)                                     */
45549 #define USB_CFG3_ENDPOINT_Msk             (0xf0000UL)               /*!< ENDPOINT (Bitfield-Mask: 0x0f)                        */
45550 #define USB_CFG3_FRMNUM_Pos               (0UL)                     /*!< FRMNUM (Bit 0)                                        */
45551 #define USB_CFG3_FRMNUM_Msk               (0xffffUL)                /*!< FRMNUM (Bitfield-Mask: 0xffff)                        */
45552 /* =========================================================  IDX0  ========================================================== */
45553 #define USB_IDX0_AutoSet_Pos              (31UL)                    /*!< AutoSet (Bit 31)                                      */
45554 #define USB_IDX0_AutoSet_Msk              (0x80000000UL)            /*!< AutoSet (Bitfield-Mask: 0x01)                         */
45555 #define USB_IDX0_ISO_Pos                  (30UL)                    /*!< ISO (Bit 30)                                          */
45556 #define USB_IDX0_ISO_Msk                  (0x40000000UL)            /*!< ISO (Bitfield-Mask: 0x01)                             */
45557 #define USB_IDX0_Mode_Pos                 (29UL)                    /*!< Mode (Bit 29)                                         */
45558 #define USB_IDX0_Mode_Msk                 (0x20000000UL)            /*!< Mode (Bitfield-Mask: 0x01)                            */
45559 #define USB_IDX0_FrcDataTog_Pos           (27UL)                    /*!< FrcDataTog (Bit 27)                                   */
45560 #define USB_IDX0_FrcDataTog_Msk           (0x8000000UL)             /*!< FrcDataTog (Bitfield-Mask: 0x01)                      */
45561 #define USB_IDX0_DPktBufDis_Pos           (25UL)                    /*!< DPktBufDis (Bit 25)                                   */
45562 #define USB_IDX0_DPktBufDis_Msk           (0x2000000UL)             /*!< DPktBufDis (Bitfield-Mask: 0x01)                      */
45563 #define USB_IDX0_D0_Pos                   (24UL)                    /*!< D0 (Bit 24)                                           */
45564 #define USB_IDX0_D0_Msk                   (0x1000000UL)             /*!< D0 (Bitfield-Mask: 0x01)                              */
45565 #define USB_IDX0_IncompTxServiceSetupEnd_Pos (23UL)                 /*!< IncompTxServiceSetupEnd (Bit 23)                      */
45566 #define USB_IDX0_IncompTxServiceSetupEnd_Msk (0x800000UL)           /*!< IncompTxServiceSetupEnd (Bitfield-Mask: 0x01)         */
45567 #define USB_IDX0_ClrDataTogServicedOutPktRdy_Pos (22UL)             /*!< ClrDataTogServicedOutPktRdy (Bit 22)                  */
45568 #define USB_IDX0_ClrDataTogServicedOutPktRdy_Msk (0x400000UL)       /*!< ClrDataTogServicedOutPktRdy (Bitfield-Mask: 0x01)     */
45569 #define USB_IDX0_SentStallSendStall_Pos   (21UL)                    /*!< SentStallSendStall (Bit 21)                           */
45570 #define USB_IDX0_SentStallSendStall_Msk   (0x200000UL)              /*!< SentStallSendStall (Bitfield-Mask: 0x01)              */
45571 #define USB_IDX0_SendStallSetupEnd_Pos    (20UL)                    /*!< SendStallSetupEnd (Bit 20)                            */
45572 #define USB_IDX0_SendStallSetupEnd_Msk    (0x100000UL)              /*!< SendStallSetupEnd (Bitfield-Mask: 0x01)               */
45573 #define USB_IDX0_FlushFIFODataEnd_Pos     (19UL)                    /*!< FlushFIFODataEnd (Bit 19)                             */
45574 #define USB_IDX0_FlushFIFODataEnd_Msk     (0x80000UL)               /*!< FlushFIFODataEnd (Bitfield-Mask: 0x01)                */
45575 #define USB_IDX0_UnderRunSentStall_Pos    (18UL)                    /*!< UnderRunSentStall (Bit 18)                            */
45576 #define USB_IDX0_UnderRunSentStall_Msk    (0x40000UL)               /*!< UnderRunSentStall (Bitfield-Mask: 0x01)               */
45577 #define USB_IDX0_FIFONotEmptyInPktRdy_Pos (17UL)                    /*!< FIFONotEmptyInPktRdy (Bit 17)                         */
45578 #define USB_IDX0_FIFONotEmptyInPktRdy_Msk (0x20000UL)               /*!< FIFONotEmptyInPktRdy (Bitfield-Mask: 0x01)            */
45579 #define USB_IDX0_InPktRdyOutPktRdy_Pos    (16UL)                    /*!< InPktRdyOutPktRdy (Bit 16)                            */
45580 #define USB_IDX0_InPktRdyOutPktRdy_Msk    (0x10000UL)               /*!< InPktRdyOutPktRdy (Bitfield-Mask: 0x01)               */
45581 #define USB_IDX0_PKTSPLITOPTION_Pos       (11UL)                    /*!< PKTSPLITOPTION (Bit 11)                               */
45582 #define USB_IDX0_PKTSPLITOPTION_Msk       (0xf800UL)                /*!< PKTSPLITOPTION (Bitfield-Mask: 0x1f)                  */
45583 #define USB_IDX0_MAXPAYLOAD_Pos           (0UL)                     /*!< MAXPAYLOAD (Bit 0)                                    */
45584 #define USB_IDX0_MAXPAYLOAD_Msk           (0x7ffUL)                 /*!< MAXPAYLOAD (Bitfield-Mask: 0x7ff)                     */
45585 /* =========================================================  IDX1  ========================================================== */
45586 #define USB_IDX1_AutoClear_Pos            (31UL)                    /*!< AutoClear (Bit 31)                                    */
45587 #define USB_IDX1_AutoClear_Msk            (0x80000000UL)            /*!< AutoClear (Bitfield-Mask: 0x01)                       */
45588 #define USB_IDX1_ISO_Pos                  (30UL)                    /*!< ISO (Bit 30)                                          */
45589 #define USB_IDX1_ISO_Msk                  (0x40000000UL)            /*!< ISO (Bitfield-Mask: 0x01)                             */
45590 #define USB_IDX1_DisNye_Pos               (28UL)                    /*!< DisNye (Bit 28)                                       */
45591 #define USB_IDX1_DisNye_Msk               (0x10000000UL)            /*!< DisNye (Bitfield-Mask: 0x01)                          */
45592 #define USB_IDX1_DPktBufDis_Pos           (25UL)                    /*!< DPktBufDis (Bit 25)                                   */
45593 #define USB_IDX1_DPktBufDis_Msk           (0x2000000UL)             /*!< DPktBufDis (Bitfield-Mask: 0x01)                      */
45594 #define USB_IDX1_IncompRx_Pos             (24UL)                    /*!< IncompRx (Bit 24)                                     */
45595 #define USB_IDX1_IncompRx_Msk             (0x1000000UL)             /*!< IncompRx (Bitfield-Mask: 0x01)                        */
45596 #define USB_IDX1_ClrDataTog_Pos           (23UL)                    /*!< ClrDataTog (Bit 23)                                   */
45597 #define USB_IDX1_ClrDataTog_Msk           (0x800000UL)              /*!< ClrDataTog (Bitfield-Mask: 0x01)                      */
45598 #define USB_IDX1_SentStall_Pos            (22UL)                    /*!< SentStall (Bit 22)                                    */
45599 #define USB_IDX1_SentStall_Msk            (0x400000UL)              /*!< SentStall (Bitfield-Mask: 0x01)                       */
45600 #define USB_IDX1_SendStall_Pos            (21UL)                    /*!< SendStall (Bit 21)                                    */
45601 #define USB_IDX1_SendStall_Msk            (0x200000UL)              /*!< SendStall (Bitfield-Mask: 0x01)                       */
45602 #define USB_IDX1_FlushFIFO_Pos            (20UL)                    /*!< FlushFIFO (Bit 20)                                    */
45603 #define USB_IDX1_FlushFIFO_Msk            (0x100000UL)              /*!< FlushFIFO (Bitfield-Mask: 0x01)                       */
45604 #define USB_IDX1_DataError_Pos            (19UL)                    /*!< DataError (Bit 19)                                    */
45605 #define USB_IDX1_DataError_Msk            (0x80000UL)               /*!< DataError (Bitfield-Mask: 0x01)                       */
45606 #define USB_IDX1_OverRun_Pos              (18UL)                    /*!< OverRun (Bit 18)                                      */
45607 #define USB_IDX1_OverRun_Msk              (0x40000UL)               /*!< OverRun (Bitfield-Mask: 0x01)                         */
45608 #define USB_IDX1_FIFOFull_Pos             (17UL)                    /*!< FIFOFull (Bit 17)                                     */
45609 #define USB_IDX1_FIFOFull_Msk             (0x20000UL)               /*!< FIFOFull (Bitfield-Mask: 0x01)                        */
45610 #define USB_IDX1_OutPktRdy_Pos            (16UL)                    /*!< OutPktRdy (Bit 16)                                    */
45611 #define USB_IDX1_OutPktRdy_Msk            (0x10000UL)               /*!< OutPktRdy (Bitfield-Mask: 0x01)                       */
45612 #define USB_IDX1_PKTSPLITOPTION_Pos       (11UL)                    /*!< PKTSPLITOPTION (Bit 11)                               */
45613 #define USB_IDX1_PKTSPLITOPTION_Msk       (0xf800UL)                /*!< PKTSPLITOPTION (Bitfield-Mask: 0x1f)                  */
45614 #define USB_IDX1_MAXPAYLOAD_Pos           (0UL)                     /*!< MAXPAYLOAD (Bit 0)                                    */
45615 #define USB_IDX1_MAXPAYLOAD_Msk           (0x7ffUL)                 /*!< MAXPAYLOAD (Bitfield-Mask: 0x7ff)                     */
45616 /* =========================================================  IDX2  ========================================================== */
45617 #define USB_IDX2_OUTFIFOSZ_Pos            (24UL)                    /*!< OUTFIFOSZ (Bit 24)                                    */
45618 #define USB_IDX2_OUTFIFOSZ_Msk            (0x1f000000UL)            /*!< OUTFIFOSZ (Bitfield-Mask: 0x1f)                       */
45619 #define USB_IDX2_INFIFOSZ_Pos             (16UL)                    /*!< INFIFOSZ (Bit 16)                                     */
45620 #define USB_IDX2_INFIFOSZ_Msk             (0x1f0000UL)              /*!< INFIFOSZ (Bitfield-Mask: 0x1f)                        */
45621 #define USB_IDX2_ENDPTOUTCOUNT_Pos        (0UL)                     /*!< ENDPTOUTCOUNT (Bit 0)                                 */
45622 #define USB_IDX2_ENDPTOUTCOUNT_Msk        (0x1fffUL)                /*!< ENDPTOUTCOUNT (Bitfield-Mask: 0x1fff)                 */
45623 /* ========================================================  FIFOADD  ======================================================== */
45624 #define USB_FIFOADD_OUTFIFOADD_Pos        (16UL)                    /*!< OUTFIFOADD (Bit 16)                                   */
45625 #define USB_FIFOADD_OUTFIFOADD_Msk        (0x1fff0000UL)            /*!< OUTFIFOADD (Bitfield-Mask: 0x1fff)                    */
45626 #define USB_FIFOADD_INFIFOADD_Pos         (0UL)                     /*!< INFIFOADD (Bit 0)                                     */
45627 #define USB_FIFOADD_INFIFOADD_Msk         (0x1fffUL)                /*!< INFIFOADD (Bitfield-Mask: 0x1fff)                     */
45628 /* =========================================================  FIFO0  ========================================================= */
45629 #define USB_FIFO0_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
45630 #define USB_FIFO0_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
45631 /* =========================================================  FIFO1  ========================================================= */
45632 #define USB_FIFO1_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
45633 #define USB_FIFO1_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
45634 /* =========================================================  FIFO2  ========================================================= */
45635 #define USB_FIFO2_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
45636 #define USB_FIFO2_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
45637 /* =========================================================  FIFO3  ========================================================= */
45638 #define USB_FIFO3_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
45639 #define USB_FIFO3_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
45640 /* =========================================================  FIFO4  ========================================================= */
45641 #define USB_FIFO4_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
45642 #define USB_FIFO4_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
45643 /* =========================================================  FIFO5  ========================================================= */
45644 #define USB_FIFO5_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
45645 #define USB_FIFO5_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
45646 /* ========================================================  HWVERS  ========================================================= */
45647 #define USB_HWVERS_RC_Pos                 (15UL)                    /*!< RC (Bit 15)                                           */
45648 #define USB_HWVERS_RC_Msk                 (0x8000UL)                /*!< RC (Bitfield-Mask: 0x01)                              */
45649 #define USB_HWVERS_xx_Pos                 (10UL)                    /*!< xx (Bit 10)                                           */
45650 #define USB_HWVERS_xx_Msk                 (0x7c00UL)                /*!< xx (Bitfield-Mask: 0x1f)                              */
45651 #define USB_HWVERS_yyy_Pos                (0UL)                     /*!< yyy (Bit 0)                                           */
45652 #define USB_HWVERS_yyy_Msk                (0x3ffUL)                 /*!< yyy (Bitfield-Mask: 0x3ff)                            */
45653 /* =========================================================  INFO  ========================================================== */
45654 #define USB_INFO_RSTXS_Pos                (17UL)                    /*!< RSTXS (Bit 17)                                        */
45655 #define USB_INFO_RSTXS_Msk                (0x20000UL)               /*!< RSTXS (Bitfield-Mask: 0x01)                           */
45656 #define USB_INFO_RSTS_Pos                 (16UL)                    /*!< RSTS (Bit 16)                                         */
45657 #define USB_INFO_RSTS_Msk                 (0x10000UL)               /*!< RSTS (Bitfield-Mask: 0x01)                            */
45658 #define USB_INFO_RamBits_Pos              (8UL)                     /*!< RamBits (Bit 8)                                       */
45659 #define USB_INFO_RamBits_Msk              (0xf00UL)                 /*!< RamBits (Bitfield-Mask: 0x0f)                         */
45660 #define USB_INFO_OutEndPoints_Pos         (4UL)                     /*!< OutEndPoints (Bit 4)                                  */
45661 #define USB_INFO_OutEndPoints_Msk         (0xf0UL)                  /*!< OutEndPoints (Bitfield-Mask: 0x0f)                    */
45662 #define USB_INFO_InEndPoints_Pos          (0UL)                     /*!< InEndPoints (Bit 0)                                   */
45663 #define USB_INFO_InEndPoints_Msk          (0xfUL)                   /*!< InEndPoints (Bitfield-Mask: 0x0f)                     */
45664 /* =======================================================  TIMEOUT1  ======================================================== */
45665 #define USB_TIMEOUT1_CTUCH_Pos            (0UL)                     /*!< CTUCH (Bit 0)                                         */
45666 #define USB_TIMEOUT1_CTUCH_Msk            (0xffffUL)                /*!< CTUCH (Bitfield-Mask: 0xffff)                         */
45667 /* =======================================================  TIMEOUT2  ======================================================== */
45668 #define USB_TIMEOUT2_CTHRSTN_Pos          (0UL)                     /*!< CTHRSTN (Bit 0)                                       */
45669 #define USB_TIMEOUT2_CTHRSTN_Msk          (0xffffUL)                /*!< CTHRSTN (Bitfield-Mask: 0xffff)                       */
45670 /* ========================================================  CLKCTRL  ======================================================== */
45671 #define USB_CLKCTRL_PHYREFCLKSEL_Pos      (24UL)                    /*!< PHYREFCLKSEL (Bit 24)                                 */
45672 #define USB_CLKCTRL_PHYREFCLKSEL_Msk      (0x3000000UL)             /*!< PHYREFCLKSEL (Bitfield-Mask: 0x03)                    */
45673 #define USB_CLKCTRL_PHYAPBLCLKDIS_Pos     (16UL)                    /*!< PHYAPBLCLKDIS (Bit 16)                                */
45674 #define USB_CLKCTRL_PHYAPBLCLKDIS_Msk     (0x10000UL)               /*!< PHYAPBLCLKDIS (Bitfield-Mask: 0x01)                   */
45675 #define USB_CLKCTRL_CTRLAPBCLKDIS_Pos     (8UL)                     /*!< CTRLAPBCLKDIS (Bit 8)                                 */
45676 #define USB_CLKCTRL_CTRLAPBCLKDIS_Msk     (0x100UL)                 /*!< CTRLAPBCLKDIS (Bitfield-Mask: 0x01)                   */
45677 #define USB_CLKCTRL_PHYREFCLKDIS_Pos      (0UL)                     /*!< PHYREFCLKDIS (Bit 0)                                  */
45678 #define USB_CLKCTRL_PHYREFCLKDIS_Msk      (0x1UL)                   /*!< PHYREFCLKDIS (Bitfield-Mask: 0x01)                    */
45679 /* =======================================================  SRAMCTRL  ======================================================== */
45680 #define USB_SRAMCTRL_STOV_Pos             (14UL)                    /*!< STOV (Bit 14)                                         */
45681 #define USB_SRAMCTRL_STOV_Msk             (0x4000UL)                /*!< STOV (Bitfield-Mask: 0x01)                            */
45682 #define USB_SRAMCTRL_WABL_Pos             (13UL)                    /*!< WABL (Bit 13)                                         */
45683 #define USB_SRAMCTRL_WABL_Msk             (0x2000UL)                /*!< WABL (Bitfield-Mask: 0x01)                            */
45684 #define USB_SRAMCTRL_WABLM_Pos            (10UL)                    /*!< WABLM (Bit 10)                                        */
45685 #define USB_SRAMCTRL_WABLM_Msk            (0x1c00UL)                /*!< WABLM (Bitfield-Mask: 0x07)                           */
45686 #define USB_SRAMCTRL_RAWL_Pos             (9UL)                     /*!< RAWL (Bit 9)                                          */
45687 #define USB_SRAMCTRL_RAWL_Msk             (0x200UL)                 /*!< RAWL (Bitfield-Mask: 0x01)                            */
45688 #define USB_SRAMCTRL_RAWLM_Pos            (7UL)                     /*!< RAWLM (Bit 7)                                         */
45689 #define USB_SRAMCTRL_RAWLM_Msk            (0x180UL)                 /*!< RAWLM (Bitfield-Mask: 0x03)                           */
45690 #define USB_SRAMCTRL_EMAW_Pos             (5UL)                     /*!< EMAW (Bit 5)                                          */
45691 #define USB_SRAMCTRL_EMAW_Msk             (0x60UL)                  /*!< EMAW (Bitfield-Mask: 0x03)                            */
45692 #define USB_SRAMCTRL_EMAS_Pos             (4UL)                     /*!< EMAS (Bit 4)                                          */
45693 #define USB_SRAMCTRL_EMAS_Msk             (0x10UL)                  /*!< EMAS (Bitfield-Mask: 0x01)                            */
45694 #define USB_SRAMCTRL_EMA_Pos              (1UL)                     /*!< EMA (Bit 1)                                           */
45695 #define USB_SRAMCTRL_EMA_Msk              (0xeUL)                   /*!< EMA (Bitfield-Mask: 0x07)                             */
45696 #define USB_SRAMCTRL_RET1N_Pos            (0UL)                     /*!< RET1N (Bit 0)                                         */
45697 #define USB_SRAMCTRL_RET1N_Msk            (0x1UL)                   /*!< RET1N (Bitfield-Mask: 0x01)                           */
45698 /* ===================================================  UTMISTICKYSTATUS  ==================================================== */
45699 #define USB_UTMISTICKYSTATUS_obsportstciky_Pos (0UL)                /*!< obsportstciky (Bit 0)                                 */
45700 #define USB_UTMISTICKYSTATUS_obsportstciky_Msk (0x3UL)              /*!< obsportstciky (Bitfield-Mask: 0x03)                   */
45701 /* ======================================================  OBSCLRSTAT  ======================================================= */
45702 #define USB_OBSCLRSTAT_CLRSTAT_Pos        (0UL)                     /*!< CLRSTAT (Bit 0)                                       */
45703 #define USB_OBSCLRSTAT_CLRSTAT_Msk        (0x1UL)                   /*!< CLRSTAT (Bitfield-Mask: 0x01)                         */
45704 /* =====================================================  DPDMPULLDOWN  ====================================================== */
45705 #define USB_DPDMPULLDOWN_DPPULLDOWN_Pos   (1UL)                     /*!< DPPULLDOWN (Bit 1)                                    */
45706 #define USB_DPDMPULLDOWN_DPPULLDOWN_Msk   (0x2UL)                   /*!< DPPULLDOWN (Bitfield-Mask: 0x01)                      */
45707 #define USB_DPDMPULLDOWN_DMPULLDOWN_Pos   (0UL)                     /*!< DMPULLDOWN (Bit 0)                                    */
45708 #define USB_DPDMPULLDOWN_DMPULLDOWN_Msk   (0x1UL)                   /*!< DMPULLDOWN (Bitfield-Mask: 0x01)                      */
45709 /* ======================================================  BCDETSTATUS  ====================================================== */
45710 #define USB_BCDETSTATUS_DMCOMPOUT_Pos     (5UL)                     /*!< DMCOMPOUT (Bit 5)                                     */
45711 #define USB_BCDETSTATUS_DMCOMPOUT_Msk     (0x20UL)                  /*!< DMCOMPOUT (Bitfield-Mask: 0x01)                       */
45712 #define USB_BCDETSTATUS_DPCOMPOUT_Pos     (4UL)                     /*!< DPCOMPOUT (Bit 4)                                     */
45713 #define USB_BCDETSTATUS_DPCOMPOUT_Msk     (0x10UL)                  /*!< DPCOMPOUT (Bitfield-Mask: 0x01)                       */
45714 #define USB_BCDETSTATUS_DCPDETECTED_Pos   (2UL)                     /*!< DCPDETECTED (Bit 2)                                   */
45715 #define USB_BCDETSTATUS_DCPDETECTED_Msk   (0x4UL)                   /*!< DCPDETECTED (Bitfield-Mask: 0x01)                     */
45716 #define USB_BCDETSTATUS_CPDETECTED_Pos    (1UL)                     /*!< CPDETECTED (Bit 1)                                    */
45717 #define USB_BCDETSTATUS_CPDETECTED_Msk    (0x2UL)                   /*!< CPDETECTED (Bitfield-Mask: 0x01)                      */
45718 #define USB_BCDETSTATUS_DPATTACHED_Pos    (0UL)                     /*!< DPATTACHED (Bit 0)                                    */
45719 #define USB_BCDETSTATUS_DPATTACHED_Msk    (0x1UL)                   /*!< DPATTACHED (Bitfield-Mask: 0x01)                      */
45720 /* ======================================================  BCDETCRTL1  ======================================================= */
45721 #define USB_BCDETCRTL1_USBSWRESET_Pos     (31UL)                    /*!< USBSWRESET (Bit 31)                                   */
45722 #define USB_BCDETCRTL1_USBSWRESET_Msk     (0x80000000UL)            /*!< USBSWRESET (Bitfield-Mask: 0x01)                      */
45723 #define USB_BCDETCRTL1_USBDCOMPEN_Pos     (11UL)                    /*!< USBDCOMPEN (Bit 11)                                   */
45724 #define USB_BCDETCRTL1_USBDCOMPEN_Msk     (0x800UL)                 /*!< USBDCOMPEN (Bitfield-Mask: 0x01)                      */
45725 #define USB_BCDETCRTL1_USBDCOMPREF_Pos    (8UL)                     /*!< USBDCOMPREF (Bit 8)                                   */
45726 #define USB_BCDETCRTL1_USBDCOMPREF_Msk    (0x300UL)                 /*!< USBDCOMPREF (Bitfield-Mask: 0x03)                     */
45727 #define USB_BCDETCRTL1_IDPSINKEN_Pos      (7UL)                     /*!< IDPSINKEN (Bit 7)                                     */
45728 #define USB_BCDETCRTL1_IDPSINKEN_Msk      (0x80UL)                  /*!< IDPSINKEN (Bitfield-Mask: 0x01)                       */
45729 #define USB_BCDETCRTL1_VDMSRCEN_Pos       (6UL)                     /*!< VDMSRCEN (Bit 6)                                      */
45730 #define USB_BCDETCRTL1_VDMSRCEN_Msk       (0x40UL)                  /*!< VDMSRCEN (Bitfield-Mask: 0x01)                        */
45731 #define USB_BCDETCRTL1_RDMPDWNEN_Pos      (5UL)                     /*!< RDMPDWNEN (Bit 5)                                     */
45732 #define USB_BCDETCRTL1_RDMPDWNEN_Msk      (0x20UL)                  /*!< RDMPDWNEN (Bitfield-Mask: 0x01)                       */
45733 #define USB_BCDETCRTL1_VDPSRCEN_Pos       (4UL)                     /*!< VDPSRCEN (Bit 4)                                      */
45734 #define USB_BCDETCRTL1_VDPSRCEN_Msk       (0x10UL)                  /*!< VDPSRCEN (Bitfield-Mask: 0x01)                        */
45735 #define USB_BCDETCRTL1_IDPSRCEN_Pos       (3UL)                     /*!< IDPSRCEN (Bit 3)                                      */
45736 #define USB_BCDETCRTL1_IDPSRCEN_Msk       (0x8UL)                   /*!< IDPSRCEN (Bitfield-Mask: 0x01)                        */
45737 #define USB_BCDETCRTL1_IDMSINKEN_Pos      (2UL)                     /*!< IDMSINKEN (Bit 2)                                     */
45738 #define USB_BCDETCRTL1_IDMSINKEN_Msk      (0x4UL)                   /*!< IDMSINKEN (Bitfield-Mask: 0x01)                       */
45739 #define USB_BCDETCRTL1_BCWEAKPULLDOWNEN_Pos (1UL)                   /*!< BCWEAKPULLDOWNEN (Bit 1)                              */
45740 #define USB_BCDETCRTL1_BCWEAKPULLDOWNEN_Msk (0x2UL)                 /*!< BCWEAKPULLDOWNEN (Bitfield-Mask: 0x01)                */
45741 #define USB_BCDETCRTL1_BCWEAKPULLUPEN_Pos (0UL)                     /*!< BCWEAKPULLUPEN (Bit 0)                                */
45742 #define USB_BCDETCRTL1_BCWEAKPULLUPEN_Msk (0x1UL)                   /*!< BCWEAKPULLUPEN (Bitfield-Mask: 0x01)                  */
45743 /* ======================================================  BCDETCRTL2  ======================================================= */
45744 #define USB_BCDETCRTL2_BCWEAKPULLDOWNTUNE_Pos (10UL)                /*!< BCWEAKPULLDOWNTUNE (Bit 10)                           */
45745 #define USB_BCDETCRTL2_BCWEAKPULLDOWNTUNE_Msk (0xc00UL)             /*!< BCWEAKPULLDOWNTUNE (Bitfield-Mask: 0x03)              */
45746 #define USB_BCDETCRTL2_BCWEAKPULLUPTUNE_Pos (8UL)                   /*!< BCWEAKPULLUPTUNE (Bit 8)                              */
45747 #define USB_BCDETCRTL2_BCWEAKPULLUPTUNE_Msk (0x300UL)               /*!< BCWEAKPULLUPTUNE (Bitfield-Mask: 0x03)                */
45748 #define USB_BCDETCRTL2_FORCEDCPDET_Pos    (3UL)                     /*!< FORCEDCPDET (Bit 3)                                   */
45749 #define USB_BCDETCRTL2_FORCEDCPDET_Msk    (0x8UL)                   /*!< FORCEDCPDET (Bitfield-Mask: 0x01)                     */
45750 #define USB_BCDETCRTL2_FORCECPDET_Pos     (2UL)                     /*!< FORCECPDET (Bit 2)                                    */
45751 #define USB_BCDETCRTL2_FORCECPDET_Msk     (0x4UL)                   /*!< FORCECPDET (Bitfield-Mask: 0x01)                      */
45752 #define USB_BCDETCRTL2_FORCEDPATTACHED_Pos (1UL)                    /*!< FORCEDPATTACHED (Bit 1)                               */
45753 #define USB_BCDETCRTL2_FORCEDPATTACHED_Msk (0x2UL)                  /*!< FORCEDPATTACHED (Bitfield-Mask: 0x01)                 */
45754 #define USB_BCDETCRTL2_CHARGEDETBYP_Pos   (0UL)                     /*!< CHARGEDETBYP (Bit 0)                                  */
45755 #define USB_BCDETCRTL2_CHARGEDETBYP_Msk   (0x1UL)                   /*!< CHARGEDETBYP (Bitfield-Mask: 0x01)                    */
45756 
45757 
45758 /* =========================================================================================================================== */
45759 /* ================                                           VCOMP                                           ================ */
45760 /* =========================================================================================================================== */
45761 
45762 /* ==========================================================  CFG  ========================================================== */
45763 #define VCOMP_CFG_LVLSEL_Pos              (16UL)                    /*!< LVLSEL (Bit 16)                                       */
45764 #define VCOMP_CFG_LVLSEL_Msk              (0xf0000UL)               /*!< LVLSEL (Bitfield-Mask: 0x0f)                          */
45765 #define VCOMP_CFG_NSEL_Pos                (8UL)                     /*!< NSEL (Bit 8)                                          */
45766 #define VCOMP_CFG_NSEL_Msk                (0x300UL)                 /*!< NSEL (Bitfield-Mask: 0x03)                            */
45767 #define VCOMP_CFG_PSEL_Pos                (0UL)                     /*!< PSEL (Bit 0)                                          */
45768 #define VCOMP_CFG_PSEL_Msk                (0x3UL)                   /*!< PSEL (Bitfield-Mask: 0x03)                            */
45769 /* =========================================================  STAT  ========================================================== */
45770 #define VCOMP_STAT_PWDSTAT_Pos            (1UL)                     /*!< PWDSTAT (Bit 1)                                       */
45771 #define VCOMP_STAT_PWDSTAT_Msk            (0x2UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
45772 #define VCOMP_STAT_CMPOUT_Pos             (0UL)                     /*!< CMPOUT (Bit 0)                                        */
45773 #define VCOMP_STAT_CMPOUT_Msk             (0x1UL)                   /*!< CMPOUT (Bitfield-Mask: 0x01)                          */
45774 /* ========================================================  PWDKEY  ========================================================= */
45775 #define VCOMP_PWDKEY_PWDKEY_Pos           (0UL)                     /*!< PWDKEY (Bit 0)                                        */
45776 #define VCOMP_PWDKEY_PWDKEY_Msk           (0xffffffffUL)            /*!< PWDKEY (Bitfield-Mask: 0xffffffff)                    */
45777 /* =========================================================  INTEN  ========================================================= */
45778 #define VCOMP_INTEN_OUTHI_Pos             (1UL)                     /*!< OUTHI (Bit 1)                                         */
45779 #define VCOMP_INTEN_OUTHI_Msk             (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
45780 #define VCOMP_INTEN_OUTLOW_Pos            (0UL)                     /*!< OUTLOW (Bit 0)                                        */
45781 #define VCOMP_INTEN_OUTLOW_Msk            (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
45782 /* ========================================================  INTSTAT  ======================================================== */
45783 #define VCOMP_INTSTAT_OUTHI_Pos           (1UL)                     /*!< OUTHI (Bit 1)                                         */
45784 #define VCOMP_INTSTAT_OUTHI_Msk           (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
45785 #define VCOMP_INTSTAT_OUTLOW_Pos          (0UL)                     /*!< OUTLOW (Bit 0)                                        */
45786 #define VCOMP_INTSTAT_OUTLOW_Msk          (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
45787 /* ========================================================  INTCLR  ========================================================= */
45788 #define VCOMP_INTCLR_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
45789 #define VCOMP_INTCLR_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
45790 #define VCOMP_INTCLR_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
45791 #define VCOMP_INTCLR_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
45792 /* ========================================================  INTSET  ========================================================= */
45793 #define VCOMP_INTSET_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
45794 #define VCOMP_INTSET_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
45795 #define VCOMP_INTSET_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
45796 #define VCOMP_INTSET_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
45797 
45798 
45799 /* =========================================================================================================================== */
45800 /* ================                                            WDT                                            ================ */
45801 /* =========================================================================================================================== */
45802 
45803 /* ==========================================================  CFG  ========================================================== */
45804 #define WDT_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
45805 #define WDT_CFG_CLKSEL_Msk                (0x7000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
45806 #define WDT_CFG_INTVAL_Pos                (16UL)                    /*!< INTVAL (Bit 16)                                       */
45807 #define WDT_CFG_INTVAL_Msk                (0xff0000UL)              /*!< INTVAL (Bitfield-Mask: 0xff)                          */
45808 #define WDT_CFG_RESVAL_Pos                (8UL)                     /*!< RESVAL (Bit 8)                                        */
45809 #define WDT_CFG_RESVAL_Msk                (0xff00UL)                /*!< RESVAL (Bitfield-Mask: 0xff)                          */
45810 #define WDT_CFG_DSPRESETINTEN_Pos         (3UL)                     /*!< DSPRESETINTEN (Bit 3)                                 */
45811 #define WDT_CFG_DSPRESETINTEN_Msk         (0x8UL)                   /*!< DSPRESETINTEN (Bitfield-Mask: 0x01)                   */
45812 #define WDT_CFG_RESEN_Pos                 (2UL)                     /*!< RESEN (Bit 2)                                         */
45813 #define WDT_CFG_RESEN_Msk                 (0x4UL)                   /*!< RESEN (Bitfield-Mask: 0x01)                           */
45814 #define WDT_CFG_INTEN_Pos                 (1UL)                     /*!< INTEN (Bit 1)                                         */
45815 #define WDT_CFG_INTEN_Msk                 (0x2UL)                   /*!< INTEN (Bitfield-Mask: 0x01)                           */
45816 #define WDT_CFG_WDTEN_Pos                 (0UL)                     /*!< WDTEN (Bit 0)                                         */
45817 #define WDT_CFG_WDTEN_Msk                 (0x1UL)                   /*!< WDTEN (Bitfield-Mask: 0x01)                           */
45818 /* =========================================================  RSTRT  ========================================================= */
45819 #define WDT_RSTRT_RSTRT_Pos               (0UL)                     /*!< RSTRT (Bit 0)                                         */
45820 #define WDT_RSTRT_RSTRT_Msk               (0xffUL)                  /*!< RSTRT (Bitfield-Mask: 0xff)                           */
45821 /* =========================================================  LOCK  ========================================================== */
45822 #define WDT_LOCK_LOCK_Pos                 (0UL)                     /*!< LOCK (Bit 0)                                          */
45823 #define WDT_LOCK_LOCK_Msk                 (0xffUL)                  /*!< LOCK (Bitfield-Mask: 0xff)                            */
45824 /* =========================================================  COUNT  ========================================================= */
45825 #define WDT_COUNT_COUNT_Pos               (0UL)                     /*!< COUNT (Bit 0)                                         */
45826 #define WDT_COUNT_COUNT_Msk               (0xffUL)                  /*!< COUNT (Bitfield-Mask: 0xff)                           */
45827 /* ========================================================  DSP0CFG  ======================================================== */
45828 #define WDT_DSP0CFG_DSP0PMRESVAL_Pos      (24UL)                    /*!< DSP0PMRESVAL (Bit 24)                                 */
45829 #define WDT_DSP0CFG_DSP0PMRESVAL_Msk      (0xff000000UL)            /*!< DSP0PMRESVAL (Bitfield-Mask: 0xff)                    */
45830 #define WDT_DSP0CFG_DSP0INTVAL_Pos        (16UL)                    /*!< DSP0INTVAL (Bit 16)                                   */
45831 #define WDT_DSP0CFG_DSP0INTVAL_Msk        (0xff0000UL)              /*!< DSP0INTVAL (Bitfield-Mask: 0xff)                      */
45832 #define WDT_DSP0CFG_DSP0RESVAL_Pos        (8UL)                     /*!< DSP0RESVAL (Bit 8)                                    */
45833 #define WDT_DSP0CFG_DSP0RESVAL_Msk        (0xff00UL)                /*!< DSP0RESVAL (Bitfield-Mask: 0xff)                      */
45834 #define WDT_DSP0CFG_DSP0PMRESEN_Pos       (3UL)                     /*!< DSP0PMRESEN (Bit 3)                                   */
45835 #define WDT_DSP0CFG_DSP0PMRESEN_Msk       (0x8UL)                   /*!< DSP0PMRESEN (Bitfield-Mask: 0x01)                     */
45836 #define WDT_DSP0CFG_DSP0RESEN_Pos         (2UL)                     /*!< DSP0RESEN (Bit 2)                                     */
45837 #define WDT_DSP0CFG_DSP0RESEN_Msk         (0x4UL)                   /*!< DSP0RESEN (Bitfield-Mask: 0x01)                       */
45838 #define WDT_DSP0CFG_DSP0INTEN_Pos         (1UL)                     /*!< DSP0INTEN (Bit 1)                                     */
45839 #define WDT_DSP0CFG_DSP0INTEN_Msk         (0x2UL)                   /*!< DSP0INTEN (Bitfield-Mask: 0x01)                       */
45840 #define WDT_DSP0CFG_DSP0WDTEN_Pos         (0UL)                     /*!< DSP0WDTEN (Bit 0)                                     */
45841 #define WDT_DSP0CFG_DSP0WDTEN_Msk         (0x1UL)                   /*!< DSP0WDTEN (Bitfield-Mask: 0x01)                       */
45842 /* =======================================================  DSP0RSTRT  ======================================================= */
45843 #define WDT_DSP0RSTRT_DSP0RSTART_Pos      (0UL)                     /*!< DSP0RSTART (Bit 0)                                    */
45844 #define WDT_DSP0RSTRT_DSP0RSTART_Msk      (0xffUL)                  /*!< DSP0RSTART (Bitfield-Mask: 0xff)                      */
45845 /* =======================================================  DSP0TLOCK  ======================================================= */
45846 #define WDT_DSP0TLOCK_DSP0LOCK_Pos        (0UL)                     /*!< DSP0LOCK (Bit 0)                                      */
45847 #define WDT_DSP0TLOCK_DSP0LOCK_Msk        (0xffUL)                  /*!< DSP0LOCK (Bitfield-Mask: 0xff)                        */
45848 /* =======================================================  DSP0COUNT  ======================================================= */
45849 #define WDT_DSP0COUNT_DSP0COUNT_Pos       (0UL)                     /*!< DSP0COUNT (Bit 0)                                     */
45850 #define WDT_DSP0COUNT_DSP0COUNT_Msk       (0xffUL)                  /*!< DSP0COUNT (Bitfield-Mask: 0xff)                       */
45851 /* ========================================================  DSP1CFG  ======================================================== */
45852 #define WDT_DSP1CFG_DSP1PMRESVAL_Pos      (24UL)                    /*!< DSP1PMRESVAL (Bit 24)                                 */
45853 #define WDT_DSP1CFG_DSP1PMRESVAL_Msk      (0xff000000UL)            /*!< DSP1PMRESVAL (Bitfield-Mask: 0xff)                    */
45854 #define WDT_DSP1CFG_DSP1INTVAL_Pos        (16UL)                    /*!< DSP1INTVAL (Bit 16)                                   */
45855 #define WDT_DSP1CFG_DSP1INTVAL_Msk        (0xff0000UL)              /*!< DSP1INTVAL (Bitfield-Mask: 0xff)                      */
45856 #define WDT_DSP1CFG_DSP1RESVAL_Pos        (8UL)                     /*!< DSP1RESVAL (Bit 8)                                    */
45857 #define WDT_DSP1CFG_DSP1RESVAL_Msk        (0xff00UL)                /*!< DSP1RESVAL (Bitfield-Mask: 0xff)                      */
45858 #define WDT_DSP1CFG_DSP1PMRESEN_Pos       (3UL)                     /*!< DSP1PMRESEN (Bit 3)                                   */
45859 #define WDT_DSP1CFG_DSP1PMRESEN_Msk       (0x8UL)                   /*!< DSP1PMRESEN (Bitfield-Mask: 0x01)                     */
45860 #define WDT_DSP1CFG_DSP1RESEN_Pos         (2UL)                     /*!< DSP1RESEN (Bit 2)                                     */
45861 #define WDT_DSP1CFG_DSP1RESEN_Msk         (0x4UL)                   /*!< DSP1RESEN (Bitfield-Mask: 0x01)                       */
45862 #define WDT_DSP1CFG_DSP1INTEN_Pos         (1UL)                     /*!< DSP1INTEN (Bit 1)                                     */
45863 #define WDT_DSP1CFG_DSP1INTEN_Msk         (0x2UL)                   /*!< DSP1INTEN (Bitfield-Mask: 0x01)                       */
45864 #define WDT_DSP1CFG_DSP1WDTEN_Pos         (0UL)                     /*!< DSP1WDTEN (Bit 0)                                     */
45865 #define WDT_DSP1CFG_DSP1WDTEN_Msk         (0x1UL)                   /*!< DSP1WDTEN (Bitfield-Mask: 0x01)                       */
45866 /* =======================================================  DSP1RSTRT  ======================================================= */
45867 #define WDT_DSP1RSTRT_DSP1RSTART_Pos      (0UL)                     /*!< DSP1RSTART (Bit 0)                                    */
45868 #define WDT_DSP1RSTRT_DSP1RSTART_Msk      (0xffUL)                  /*!< DSP1RSTART (Bitfield-Mask: 0xff)                      */
45869 /* =======================================================  DSP1TLOCK  ======================================================= */
45870 #define WDT_DSP1TLOCK_DSP1LOCK_Pos        (0UL)                     /*!< DSP1LOCK (Bit 0)                                      */
45871 #define WDT_DSP1TLOCK_DSP1LOCK_Msk        (0xffUL)                  /*!< DSP1LOCK (Bitfield-Mask: 0xff)                        */
45872 /* =======================================================  DSP1COUNT  ======================================================= */
45873 #define WDT_DSP1COUNT_DSP1COUNT_Pos       (0UL)                     /*!< DSP1COUNT (Bit 0)                                     */
45874 #define WDT_DSP1COUNT_DSP1COUNT_Msk       (0xffUL)                  /*!< DSP1COUNT (Bitfield-Mask: 0xff)                       */
45875 /* =======================================================  WDTIEREN  ======================================================== */
45876 #define WDT_WDTIEREN_DSPRESETINT_Pos      (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
45877 #define WDT_WDTIEREN_DSPRESETINT_Msk      (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
45878 #define WDT_WDTIEREN_WDTINT_Pos           (0UL)                     /*!< WDTINT (Bit 0)                                        */
45879 #define WDT_WDTIEREN_WDTINT_Msk           (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
45880 /* ======================================================  WDTIERSTAT  ======================================================= */
45881 #define WDT_WDTIERSTAT_DSPRESETINT_Pos    (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
45882 #define WDT_WDTIERSTAT_DSPRESETINT_Msk    (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
45883 #define WDT_WDTIERSTAT_WDTINT_Pos         (0UL)                     /*!< WDTINT (Bit 0)                                        */
45884 #define WDT_WDTIERSTAT_WDTINT_Msk         (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
45885 /* =======================================================  WDTIERCLR  ======================================================= */
45886 #define WDT_WDTIERCLR_DSPRESETINT_Pos     (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
45887 #define WDT_WDTIERCLR_DSPRESETINT_Msk     (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
45888 #define WDT_WDTIERCLR_WDTINT_Pos          (0UL)                     /*!< WDTINT (Bit 0)                                        */
45889 #define WDT_WDTIERCLR_WDTINT_Msk          (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
45890 /* =======================================================  WDTIERSET  ======================================================= */
45891 #define WDT_WDTIERSET_DSPRESETINT_Pos     (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
45892 #define WDT_WDTIERSET_DSPRESETINT_Msk     (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
45893 #define WDT_WDTIERSET_WDTINT_Pos          (0UL)                     /*!< WDTINT (Bit 0)                                        */
45894 #define WDT_WDTIERSET_WDTINT_Msk          (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
45895 /* =======================================================  DSP0IEREN  ======================================================= */
45896 #define WDT_DSP0IEREN_DSP0INT_Pos         (0UL)                     /*!< DSP0INT (Bit 0)                                       */
45897 #define WDT_DSP0IEREN_DSP0INT_Msk         (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
45898 /* ======================================================  DSP0IERSTAT  ====================================================== */
45899 #define WDT_DSP0IERSTAT_DSP0INT_Pos       (0UL)                     /*!< DSP0INT (Bit 0)                                       */
45900 #define WDT_DSP0IERSTAT_DSP0INT_Msk       (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
45901 /* ======================================================  DSP0IERCLR  ======================================================= */
45902 #define WDT_DSP0IERCLR_DSP0INT_Pos        (0UL)                     /*!< DSP0INT (Bit 0)                                       */
45903 #define WDT_DSP0IERCLR_DSP0INT_Msk        (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
45904 /* ======================================================  DSP0IERSET  ======================================================= */
45905 #define WDT_DSP0IERSET_DSP0INT_Pos        (0UL)                     /*!< DSP0INT (Bit 0)                                       */
45906 #define WDT_DSP0IERSET_DSP0INT_Msk        (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
45907 /* =======================================================  DSP1IEREN  ======================================================= */
45908 #define WDT_DSP1IEREN_DSP1INT_Pos         (0UL)                     /*!< DSP1INT (Bit 0)                                       */
45909 #define WDT_DSP1IEREN_DSP1INT_Msk         (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
45910 /* ======================================================  DSP1IERSTAT  ====================================================== */
45911 #define WDT_DSP1IERSTAT_DSP1INT_Pos       (0UL)                     /*!< DSP1INT (Bit 0)                                       */
45912 #define WDT_DSP1IERSTAT_DSP1INT_Msk       (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
45913 /* ======================================================  DSP1IERCLR  ======================================================= */
45914 #define WDT_DSP1IERCLR_DSP1INT_Pos        (0UL)                     /*!< DSP1INT (Bit 0)                                       */
45915 #define WDT_DSP1IERCLR_DSP1INT_Msk        (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
45916 /* ======================================================  DSP1IERSET  ======================================================= */
45917 #define WDT_DSP1IERSET_DSP1INT_Pos        (0UL)                     /*!< DSP1INT (Bit 0)                                       */
45918 #define WDT_DSP1IERSET_DSP1INT_Msk        (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
45919 
45920 /** @} */ /* End of group PosMask_peripherals */
45921 
45922 
45923 /* =========================================================================================================================== */
45924 /* ================                           Enumerated Values Peripheral Section                            ================ */
45925 /* =========================================================================================================================== */
45926 
45927 
45928 /** @addtogroup EnumValue_peripherals
45929   * @{
45930   */
45931 
45932 
45933 
45934 /* =========================================================================================================================== */
45935 /* ================                                            ADC                                            ================ */
45936 /* =========================================================================================================================== */
45937 
45938 /* ==========================================================  CFG  ========================================================== */
45939 /* ================================================  ADC CFG CLKSEL [24..25]  ================================================ */
45940 typedef enum {                                  /*!< ADC_CFG_CLKSEL                                                            */
45941   ADC_CFG_CLKSEL_HFRC_48MHZ            = 0,     /*!< HFRC_48MHZ : This setting must not be used for CLKSEL for the
45942                                                      GP ADC even though it is the default setting. Software
45943                                                      must set CLKSEL to HFRC_24MHZ after any reset event and
45944                                                      before enabling the ADC.                                                  */
45945   ADC_CFG_CLKSEL_HFRC_48MHZ1           = 1,     /*!< HFRC_48MHZ1 : This setting must not be used for CLKSEL for the
45946                                                      GP ADC.                                                                   */
45947   ADC_CFG_CLKSEL_HFRC_24MHZ            = 2,     /*!< HFRC_24MHZ : HFRC clock at 24 MHz. This setting is the only
45948                                                      valid setting for the GP ADC.                                             */
45949   ADC_CFG_CLKSEL_HFRC2_48MHZ           = 3,     /*!< HFRC2_48MHZ : This setting must not be used for CLKSEL for the
45950                                                      GP ADC.                                                                   */
45951 } ADC_CFG_CLKSEL_Enum;
45952 
45953 /* ==============================================  ADC CFG RPTTRIGSEL [20..20]  ============================================== */
45954 typedef enum {                                  /*!< ADC_CFG_RPTTRIGSEL                                                        */
45955   ADC_CFG_RPTTRIGSEL_TMR               = 0,     /*!< TMR : Trigger from on-chip timer.                                         */
45956   ADC_CFG_RPTTRIGSEL_INT               = 1,     /*!< INT : Trigger from ADC-internal timer.                                    */
45957 } ADC_CFG_RPTTRIGSEL_Enum;
45958 
45959 /* ===============================================  ADC CFG TRIGPOL [19..19]  ================================================ */
45960 typedef enum {                                  /*!< ADC_CFG_TRIGPOL                                                           */
45961   ADC_CFG_TRIGPOL_RISING_EDGE          = 0,     /*!< RISING_EDGE : Trigger on rising edge.                                     */
45962   ADC_CFG_TRIGPOL_FALLING_EDGE         = 1,     /*!< FALLING_EDGE : Trigger on falling edge.                                   */
45963 } ADC_CFG_TRIGPOL_Enum;
45964 
45965 /* ===============================================  ADC CFG TRIGSEL [16..18]  ================================================ */
45966 typedef enum {                                  /*!< ADC_CFG_TRIGSEL                                                           */
45967   ADC_CFG_TRIGSEL_EXT0                 = 0,     /*!< EXT0 : Off chip External Trigger0 (ADC_ET0)                               */
45968   ADC_CFG_TRIGSEL_EXT1                 = 1,     /*!< EXT1 : Off chip External Trigger1 (ADC_ET1)                               */
45969   ADC_CFG_TRIGSEL_EXT2                 = 2,     /*!< EXT2 : Off chip External Trigger2 (ADC_ET2)                               */
45970   ADC_CFG_TRIGSEL_EXT3                 = 3,     /*!< EXT3 : Off chip External Trigger3 (ADC_ET3)                               */
45971   ADC_CFG_TRIGSEL_VCOMP                = 4,     /*!< VCOMP : Voltage Comparator Output                                         */
45972   ADC_CFG_TRIGSEL_SWT                  = 7,     /*!< SWT : Software Trigger                                                    */
45973 } ADC_CFG_TRIGSEL_Enum;
45974 
45975 /* ==============================================  ADC CFG DFIFORDEN [12..12]  =============================================== */
45976 typedef enum {                                  /*!< ADC_CFG_DFIFORDEN                                                         */
45977   ADC_CFG_DFIFORDEN_DIS                = 0,     /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
45978                                                      will not POP an entry off the FIFO.                                       */
45979   ADC_CFG_DFIFORDEN_EN                 = 1,     /*!< EN : Reads to the FIFOPR registger will automatically pop an
45980                                                      entry off the FIFO.                                                       */
45981 } ADC_CFG_DFIFORDEN_Enum;
45982 
45983 /* =================================================  ADC CFG CKMODE [4..4]  ================================================= */
45984 typedef enum {                                  /*!< ADC_CFG_CKMODE                                                            */
45985   ADC_CFG_CKMODE_LPCKMODE              = 0,     /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
45986                                                      LPCKMODE to 0x1 while configuring the ADC.                                */
45987   ADC_CFG_CKMODE_LLCKMODE              = 1,     /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
45988                                                      will remain on while in functioning in LPMODE0.                           */
45989 } ADC_CFG_CKMODE_Enum;
45990 
45991 /* =================================================  ADC CFG LPMODE [3..3]  ================================================= */
45992 typedef enum {                                  /*!< ADC_CFG_LPMODE                                                            */
45993   ADC_CFG_LPMODE_MODE0                 = 0,     /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between
45994                                                      scans with minimum latency between a trigger event and
45995                                                      sample data collection.                                                   */
45996   ADC_CFG_LPMODE_MODE1                 = 1,     /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
45997                                                      associated with the ADC until the next trigger event. Between
45998                                                      scans, the reference buffer requires up to 50us of delay
45999                                                      from a scan trigger event before the conversion will commence
46000                                                      while operating in this mode.                                             */
46001 } ADC_CFG_LPMODE_Enum;
46002 
46003 /* =================================================  ADC CFG RPTEN [2..2]  ================================================== */
46004 typedef enum {                                  /*!< ADC_CFG_RPTEN                                                             */
46005   ADC_CFG_RPTEN_SINGLE_SCAN            = 0,     /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single
46006                                                      scan upon each trigger event.                                             */
46007   ADC_CFG_RPTEN_REPEATING_SCAN         = 1,     /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete
46008                                                      its first scan upon the initial trigger event and all subsequent
46009                                                      scans will occur at regular intervals defined by the configuration
46010                                                      programmed for the CTTMRA3 timer or the ADC-internal timer
46011                                                      (see the RPTTRIGSEL field) until the timer is disabled
46012                                                      or the ADC is disabled. When disabling the ADC (setting
46013                                                      ADCEN to '0'), the RPTEN bit should be cleared.                           */
46014 } ADC_CFG_RPTEN_Enum;
46015 
46016 /* =================================================  ADC CFG ADCEN [0..0]  ================================================== */
46017 typedef enum {                                  /*!< ADC_CFG_ADCEN                                                             */
46018   ADC_CFG_ADCEN_DIS                    = 0,     /*!< DIS : Disable the ADC module.                                             */
46019   ADC_CFG_ADCEN_EN                     = 1,     /*!< EN : Enable the ADC module.                                               */
46020 } ADC_CFG_ADCEN_Enum;
46021 
46022 /* =========================================================  STAT  ========================================================== */
46023 /* ================================================  ADC STAT PWDSTAT [0..0]  ================================================ */
46024 typedef enum {                                  /*!< ADC_STAT_PWDSTAT                                                          */
46025   ADC_STAT_PWDSTAT_ON                  = 0,     /*!< ON : Powered on.                                                          */
46026   ADC_STAT_PWDSTAT_POWERED_DOWN        = 1,     /*!< POWERED_DOWN : ADC Low Power Mode 1.                                      */
46027 } ADC_STAT_PWDSTAT_Enum;
46028 
46029 /* ==========================================================  SWT  ========================================================== */
46030 /* ==================================================  ADC SWT SWT [0..7]  =================================================== */
46031 typedef enum {                                  /*!< ADC_SWT_SWT                                                               */
46032   ADC_SWT_SWT_GEN_SW_TRIGGER           = 55,    /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger.         */
46033   ADC_SWT_SWT_NO_SW_TRIGGER            = 0,     /*!< NO_SW_TRIGGER : Default value.                                            */
46034 } ADC_SWT_SWT_Enum;
46035 
46036 /* ========================================================  SL0CFG  ========================================================= */
46037 /* ==============================================  ADC SL0CFG ADSEL0 [24..26]  =============================================== */
46038 typedef enum {                                  /*!< ADC_SL0CFG_ADSEL0                                                         */
46039   ADC_SL0CFG_ADSEL0_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46040                                                      module for this slot.                                                     */
46041   ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46042                                                      module for this slot.                                                     */
46043   ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46044                                                      module for this slot.                                                     */
46045   ADC_SL0CFG_ADSEL0_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46046                                                      module for this slot.                                                     */
46047   ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46048                                                      divide module for this slot.                                              */
46049   ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46050                                                      divide module for this slot.                                              */
46051   ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46052                                                      divide module for this slot.                                              */
46053   ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46054                                                      divide module for this slot.                                              */
46055 } ADC_SL0CFG_ADSEL0_Enum;
46056 
46057 /* ==============================================  ADC SL0CFG PRMODE0 [16..17]  ============================================== */
46058 typedef enum {                                  /*!< ADC_SL0CFG_PRMODE0                                                        */
46059   ADC_SL0CFG_PRMODE0_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46060   ADC_SL0CFG_PRMODE0_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46061   ADC_SL0CFG_PRMODE0_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46062   ADC_SL0CFG_PRMODE0_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46063 } ADC_SL0CFG_PRMODE0_Enum;
46064 
46065 /* ===============================================  ADC SL0CFG CHSEL0 [8..11]  =============================================== */
46066 typedef enum {                                  /*!< ADC_SL0CFG_CHSEL0                                                         */
46067   ADC_SL0CFG_CHSEL0_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46068   ADC_SL0CFG_CHSEL0_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46069   ADC_SL0CFG_CHSEL0_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46070   ADC_SL0CFG_CHSEL0_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46071   ADC_SL0CFG_CHSEL0_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46072   ADC_SL0CFG_CHSEL0_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46073   ADC_SL0CFG_CHSEL0_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46074   ADC_SL0CFG_CHSEL0_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46075   ADC_SL0CFG_CHSEL0_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46076   ADC_SL0CFG_CHSEL0_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46077   ADC_SL0CFG_CHSEL0_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46078   ADC_SL0CFG_CHSEL0_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46079 } ADC_SL0CFG_CHSEL0_Enum;
46080 
46081 /* ================================================  ADC SL0CFG WCEN0 [1..1]  ================================================ */
46082 typedef enum {                                  /*!< ADC_SL0CFG_WCEN0                                                          */
46083   ADC_SL0CFG_WCEN0_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 0.                              */
46084   ADC_SL0CFG_WCEN0_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 0.                            */
46085 } ADC_SL0CFG_WCEN0_Enum;
46086 
46087 /* ================================================  ADC SL0CFG SLEN0 [0..0]  ================================================ */
46088 typedef enum {                                  /*!< ADC_SL0CFG_SLEN0                                                          */
46089   ADC_SL0CFG_SLEN0_SLEN                = 1,     /*!< SLEN : Enable slot 0 for ADC conversions.                                 */
46090   ADC_SL0CFG_SLEN0_SLDIS               = 0,     /*!< SLDIS : Disable slot 0 for ADC conversions.                               */
46091 } ADC_SL0CFG_SLEN0_Enum;
46092 
46093 /* ========================================================  SL1CFG  ========================================================= */
46094 /* ==============================================  ADC SL1CFG ADSEL1 [24..26]  =============================================== */
46095 typedef enum {                                  /*!< ADC_SL1CFG_ADSEL1                                                         */
46096   ADC_SL1CFG_ADSEL1_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46097                                                      module for this slot.                                                     */
46098   ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46099                                                      module for this slot.                                                     */
46100   ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46101                                                      module for this slot.                                                     */
46102   ADC_SL1CFG_ADSEL1_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46103                                                      module for this slot.                                                     */
46104   ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46105                                                      divide module for this slot.                                              */
46106   ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46107                                                      divide module for this slot.                                              */
46108   ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46109                                                      divide module for this slot.                                              */
46110   ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46111                                                      divide module for this slot.                                              */
46112 } ADC_SL1CFG_ADSEL1_Enum;
46113 
46114 /* ==============================================  ADC SL1CFG PRMODE1 [16..17]  ============================================== */
46115 typedef enum {                                  /*!< ADC_SL1CFG_PRMODE1                                                        */
46116   ADC_SL1CFG_PRMODE1_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46117   ADC_SL1CFG_PRMODE1_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46118   ADC_SL1CFG_PRMODE1_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46119   ADC_SL1CFG_PRMODE1_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46120 } ADC_SL1CFG_PRMODE1_Enum;
46121 
46122 /* ===============================================  ADC SL1CFG CHSEL1 [8..11]  =============================================== */
46123 typedef enum {                                  /*!< ADC_SL1CFG_CHSEL1                                                         */
46124   ADC_SL1CFG_CHSEL1_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46125   ADC_SL1CFG_CHSEL1_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46126   ADC_SL1CFG_CHSEL1_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46127   ADC_SL1CFG_CHSEL1_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46128   ADC_SL1CFG_CHSEL1_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46129   ADC_SL1CFG_CHSEL1_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46130   ADC_SL1CFG_CHSEL1_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46131   ADC_SL1CFG_CHSEL1_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46132   ADC_SL1CFG_CHSEL1_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46133   ADC_SL1CFG_CHSEL1_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46134   ADC_SL1CFG_CHSEL1_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46135   ADC_SL1CFG_CHSEL1_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46136 } ADC_SL1CFG_CHSEL1_Enum;
46137 
46138 /* ================================================  ADC SL1CFG WCEN1 [1..1]  ================================================ */
46139 typedef enum {                                  /*!< ADC_SL1CFG_WCEN1                                                          */
46140   ADC_SL1CFG_WCEN1_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 1.                              */
46141   ADC_SL1CFG_WCEN1_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 1.                            */
46142 } ADC_SL1CFG_WCEN1_Enum;
46143 
46144 /* ================================================  ADC SL1CFG SLEN1 [0..0]  ================================================ */
46145 typedef enum {                                  /*!< ADC_SL1CFG_SLEN1                                                          */
46146   ADC_SL1CFG_SLEN1_SLEN                = 1,     /*!< SLEN : Enable slot 1 for ADC conversions.                                 */
46147   ADC_SL1CFG_SLEN1_SLDIS               = 0,     /*!< SLDIS : Disable slot 1 for ADC conversions.                               */
46148 } ADC_SL1CFG_SLEN1_Enum;
46149 
46150 /* ========================================================  SL2CFG  ========================================================= */
46151 /* ==============================================  ADC SL2CFG ADSEL2 [24..26]  =============================================== */
46152 typedef enum {                                  /*!< ADC_SL2CFG_ADSEL2                                                         */
46153   ADC_SL2CFG_ADSEL2_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46154                                                      module for this slot.                                                     */
46155   ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46156                                                      module for this slot.                                                     */
46157   ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46158                                                      module for this slot.                                                     */
46159   ADC_SL2CFG_ADSEL2_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46160                                                      module for this slot.                                                     */
46161   ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46162                                                      divide module for this slot.                                              */
46163   ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46164                                                      divide module for this slot.                                              */
46165   ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46166                                                      divide module for this slot.                                              */
46167   ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46168                                                      divide module for this slot.                                              */
46169 } ADC_SL2CFG_ADSEL2_Enum;
46170 
46171 /* ==============================================  ADC SL2CFG PRMODE2 [16..17]  ============================================== */
46172 typedef enum {                                  /*!< ADC_SL2CFG_PRMODE2                                                        */
46173   ADC_SL2CFG_PRMODE2_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46174   ADC_SL2CFG_PRMODE2_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46175   ADC_SL2CFG_PRMODE2_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46176   ADC_SL2CFG_PRMODE2_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46177 } ADC_SL2CFG_PRMODE2_Enum;
46178 
46179 /* ===============================================  ADC SL2CFG CHSEL2 [8..11]  =============================================== */
46180 typedef enum {                                  /*!< ADC_SL2CFG_CHSEL2                                                         */
46181   ADC_SL2CFG_CHSEL2_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46182   ADC_SL2CFG_CHSEL2_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46183   ADC_SL2CFG_CHSEL2_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46184   ADC_SL2CFG_CHSEL2_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46185   ADC_SL2CFG_CHSEL2_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46186   ADC_SL2CFG_CHSEL2_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46187   ADC_SL2CFG_CHSEL2_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46188   ADC_SL2CFG_CHSEL2_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46189   ADC_SL2CFG_CHSEL2_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46190   ADC_SL2CFG_CHSEL2_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46191   ADC_SL2CFG_CHSEL2_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46192   ADC_SL2CFG_CHSEL2_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46193 } ADC_SL2CFG_CHSEL2_Enum;
46194 
46195 /* ================================================  ADC SL2CFG WCEN2 [1..1]  ================================================ */
46196 typedef enum {                                  /*!< ADC_SL2CFG_WCEN2                                                          */
46197   ADC_SL2CFG_WCEN2_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 2.                              */
46198   ADC_SL2CFG_WCEN2_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 2.                            */
46199 } ADC_SL2CFG_WCEN2_Enum;
46200 
46201 /* ================================================  ADC SL2CFG SLEN2 [0..0]  ================================================ */
46202 typedef enum {                                  /*!< ADC_SL2CFG_SLEN2                                                          */
46203   ADC_SL2CFG_SLEN2_SLEN                = 1,     /*!< SLEN : Enable slot 2 for ADC conversions.                                 */
46204   ADC_SL2CFG_SLEN2_SLDIS               = 0,     /*!< SLDIS : Disable slot 2 for ADC conversions.                               */
46205 } ADC_SL2CFG_SLEN2_Enum;
46206 
46207 /* ========================================================  SL3CFG  ========================================================= */
46208 /* ==============================================  ADC SL3CFG ADSEL3 [24..26]  =============================================== */
46209 typedef enum {                                  /*!< ADC_SL3CFG_ADSEL3                                                         */
46210   ADC_SL3CFG_ADSEL3_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46211                                                      module for this slot.                                                     */
46212   ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46213                                                      module for this slot.                                                     */
46214   ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46215                                                      module for this slot.                                                     */
46216   ADC_SL3CFG_ADSEL3_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46217                                                      module for this slot.                                                     */
46218   ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46219                                                      divide module for this slot.                                              */
46220   ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46221                                                      divide module for this slot.                                              */
46222   ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46223                                                      divide module for this slot.                                              */
46224   ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46225                                                      divide module for this slot.                                              */
46226 } ADC_SL3CFG_ADSEL3_Enum;
46227 
46228 /* ==============================================  ADC SL3CFG PRMODE3 [16..17]  ============================================== */
46229 typedef enum {                                  /*!< ADC_SL3CFG_PRMODE3                                                        */
46230   ADC_SL3CFG_PRMODE3_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46231   ADC_SL3CFG_PRMODE3_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46232   ADC_SL3CFG_PRMODE3_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46233   ADC_SL3CFG_PRMODE3_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46234 } ADC_SL3CFG_PRMODE3_Enum;
46235 
46236 /* ===============================================  ADC SL3CFG CHSEL3 [8..11]  =============================================== */
46237 typedef enum {                                  /*!< ADC_SL3CFG_CHSEL3                                                         */
46238   ADC_SL3CFG_CHSEL3_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46239   ADC_SL3CFG_CHSEL3_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46240   ADC_SL3CFG_CHSEL3_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46241   ADC_SL3CFG_CHSEL3_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46242   ADC_SL3CFG_CHSEL3_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46243   ADC_SL3CFG_CHSEL3_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46244   ADC_SL3CFG_CHSEL3_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46245   ADC_SL3CFG_CHSEL3_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46246   ADC_SL3CFG_CHSEL3_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46247   ADC_SL3CFG_CHSEL3_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46248   ADC_SL3CFG_CHSEL3_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46249   ADC_SL3CFG_CHSEL3_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46250 } ADC_SL3CFG_CHSEL3_Enum;
46251 
46252 /* ================================================  ADC SL3CFG WCEN3 [1..1]  ================================================ */
46253 typedef enum {                                  /*!< ADC_SL3CFG_WCEN3                                                          */
46254   ADC_SL3CFG_WCEN3_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 3.                              */
46255   ADC_SL3CFG_WCEN3_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 3.                            */
46256 } ADC_SL3CFG_WCEN3_Enum;
46257 
46258 /* ================================================  ADC SL3CFG SLEN3 [0..0]  ================================================ */
46259 typedef enum {                                  /*!< ADC_SL3CFG_SLEN3                                                          */
46260   ADC_SL3CFG_SLEN3_SLEN                = 1,     /*!< SLEN : Enable slot 3 for ADC conversions.                                 */
46261   ADC_SL3CFG_SLEN3_SLDIS               = 0,     /*!< SLDIS : Disable slot 3 for ADC conversions.                               */
46262 } ADC_SL3CFG_SLEN3_Enum;
46263 
46264 /* ========================================================  SL4CFG  ========================================================= */
46265 /* ==============================================  ADC SL4CFG ADSEL4 [24..26]  =============================================== */
46266 typedef enum {                                  /*!< ADC_SL4CFG_ADSEL4                                                         */
46267   ADC_SL4CFG_ADSEL4_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46268                                                      module for this slot.                                                     */
46269   ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46270                                                      module for this slot.                                                     */
46271   ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46272                                                      module for this slot.                                                     */
46273   ADC_SL4CFG_ADSEL4_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46274                                                      module for this slot.                                                     */
46275   ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46276                                                      divide module for this slot.                                              */
46277   ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46278                                                      divide module for this slot.                                              */
46279   ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46280                                                      divide module for this slot.                                              */
46281   ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46282                                                      divide module for this slot.                                              */
46283 } ADC_SL4CFG_ADSEL4_Enum;
46284 
46285 /* ==============================================  ADC SL4CFG PRMODE4 [16..17]  ============================================== */
46286 typedef enum {                                  /*!< ADC_SL4CFG_PRMODE4                                                        */
46287   ADC_SL4CFG_PRMODE4_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46288   ADC_SL4CFG_PRMODE4_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46289   ADC_SL4CFG_PRMODE4_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46290   ADC_SL4CFG_PRMODE4_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46291 } ADC_SL4CFG_PRMODE4_Enum;
46292 
46293 /* ===============================================  ADC SL4CFG CHSEL4 [8..11]  =============================================== */
46294 typedef enum {                                  /*!< ADC_SL4CFG_CHSEL4                                                         */
46295   ADC_SL4CFG_CHSEL4_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46296   ADC_SL4CFG_CHSEL4_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46297   ADC_SL4CFG_CHSEL4_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46298   ADC_SL4CFG_CHSEL4_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46299   ADC_SL4CFG_CHSEL4_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46300   ADC_SL4CFG_CHSEL4_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46301   ADC_SL4CFG_CHSEL4_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46302   ADC_SL4CFG_CHSEL4_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46303   ADC_SL4CFG_CHSEL4_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46304   ADC_SL4CFG_CHSEL4_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46305   ADC_SL4CFG_CHSEL4_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46306   ADC_SL4CFG_CHSEL4_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46307 } ADC_SL4CFG_CHSEL4_Enum;
46308 
46309 /* ================================================  ADC SL4CFG WCEN4 [1..1]  ================================================ */
46310 typedef enum {                                  /*!< ADC_SL4CFG_WCEN4                                                          */
46311   ADC_SL4CFG_WCEN4_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 4.                              */
46312   ADC_SL4CFG_WCEN4_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 4.                            */
46313 } ADC_SL4CFG_WCEN4_Enum;
46314 
46315 /* ================================================  ADC SL4CFG SLEN4 [0..0]  ================================================ */
46316 typedef enum {                                  /*!< ADC_SL4CFG_SLEN4                                                          */
46317   ADC_SL4CFG_SLEN4_SLEN                = 1,     /*!< SLEN : Enable slot 4 for ADC conversions.                                 */
46318   ADC_SL4CFG_SLEN4_SLDIS               = 0,     /*!< SLDIS : Disable slot 4 for ADC conversions.                               */
46319 } ADC_SL4CFG_SLEN4_Enum;
46320 
46321 /* ========================================================  SL5CFG  ========================================================= */
46322 /* ==============================================  ADC SL5CFG ADSEL5 [24..26]  =============================================== */
46323 typedef enum {                                  /*!< ADC_SL5CFG_ADSEL5                                                         */
46324   ADC_SL5CFG_ADSEL5_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46325                                                      module for this slot.                                                     */
46326   ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46327                                                      module for this slot.                                                     */
46328   ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46329                                                      module for this slot.                                                     */
46330   ADC_SL5CFG_ADSEL5_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46331                                                      module for this slot.                                                     */
46332   ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46333                                                      divide module for this slot.                                              */
46334   ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46335                                                      divide module for this slot.                                              */
46336   ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46337                                                      divide module for this slot.                                              */
46338   ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46339                                                      divide module for this slot.                                              */
46340 } ADC_SL5CFG_ADSEL5_Enum;
46341 
46342 /* ==============================================  ADC SL5CFG PRMODE5 [16..17]  ============================================== */
46343 typedef enum {                                  /*!< ADC_SL5CFG_PRMODE5                                                        */
46344   ADC_SL5CFG_PRMODE5_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46345   ADC_SL5CFG_PRMODE5_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46346   ADC_SL5CFG_PRMODE5_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46347   ADC_SL5CFG_PRMODE5_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46348 } ADC_SL5CFG_PRMODE5_Enum;
46349 
46350 /* ===============================================  ADC SL5CFG CHSEL5 [8..11]  =============================================== */
46351 typedef enum {                                  /*!< ADC_SL5CFG_CHSEL5                                                         */
46352   ADC_SL5CFG_CHSEL5_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46353   ADC_SL5CFG_CHSEL5_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46354   ADC_SL5CFG_CHSEL5_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46355   ADC_SL5CFG_CHSEL5_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46356   ADC_SL5CFG_CHSEL5_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46357   ADC_SL5CFG_CHSEL5_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46358   ADC_SL5CFG_CHSEL5_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46359   ADC_SL5CFG_CHSEL5_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46360   ADC_SL5CFG_CHSEL5_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46361   ADC_SL5CFG_CHSEL5_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46362   ADC_SL5CFG_CHSEL5_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46363   ADC_SL5CFG_CHSEL5_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46364 } ADC_SL5CFG_CHSEL5_Enum;
46365 
46366 /* ================================================  ADC SL5CFG WCEN5 [1..1]  ================================================ */
46367 typedef enum {                                  /*!< ADC_SL5CFG_WCEN5                                                          */
46368   ADC_SL5CFG_WCEN5_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 5.                              */
46369   ADC_SL5CFG_WCEN5_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 5.                            */
46370 } ADC_SL5CFG_WCEN5_Enum;
46371 
46372 /* ================================================  ADC SL5CFG SLEN5 [0..0]  ================================================ */
46373 typedef enum {                                  /*!< ADC_SL5CFG_SLEN5                                                          */
46374   ADC_SL5CFG_SLEN5_SLEN                = 1,     /*!< SLEN : Enable slot 5 for ADC conversions.                                 */
46375   ADC_SL5CFG_SLEN5_SLDIS               = 0,     /*!< SLDIS : Disable slot 5 for ADC conversions.                               */
46376 } ADC_SL5CFG_SLEN5_Enum;
46377 
46378 /* ========================================================  SL6CFG  ========================================================= */
46379 /* ==============================================  ADC SL6CFG ADSEL6 [24..26]  =============================================== */
46380 typedef enum {                                  /*!< ADC_SL6CFG_ADSEL6                                                         */
46381   ADC_SL6CFG_ADSEL6_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46382                                                      module for this slot.                                                     */
46383   ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46384                                                      module for this slot.                                                     */
46385   ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46386                                                      module for this slot.                                                     */
46387   ADC_SL6CFG_ADSEL6_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46388                                                      module for this slot.                                                     */
46389   ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46390                                                      divide module for this slot.                                              */
46391   ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46392                                                      divide module for this slot.                                              */
46393   ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46394                                                      divide module for this slot.                                              */
46395   ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46396                                                      divide module for this slot.                                              */
46397 } ADC_SL6CFG_ADSEL6_Enum;
46398 
46399 /* ==============================================  ADC SL6CFG PRMODE6 [16..17]  ============================================== */
46400 typedef enum {                                  /*!< ADC_SL6CFG_PRMODE6                                                        */
46401   ADC_SL6CFG_PRMODE6_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46402   ADC_SL6CFG_PRMODE6_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46403   ADC_SL6CFG_PRMODE6_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46404   ADC_SL6CFG_PRMODE6_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46405 } ADC_SL6CFG_PRMODE6_Enum;
46406 
46407 /* ===============================================  ADC SL6CFG CHSEL6 [8..11]  =============================================== */
46408 typedef enum {                                  /*!< ADC_SL6CFG_CHSEL6                                                         */
46409   ADC_SL6CFG_CHSEL6_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46410   ADC_SL6CFG_CHSEL6_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46411   ADC_SL6CFG_CHSEL6_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46412   ADC_SL6CFG_CHSEL6_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46413   ADC_SL6CFG_CHSEL6_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46414   ADC_SL6CFG_CHSEL6_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46415   ADC_SL6CFG_CHSEL6_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46416   ADC_SL6CFG_CHSEL6_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46417   ADC_SL6CFG_CHSEL6_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46418   ADC_SL6CFG_CHSEL6_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46419   ADC_SL6CFG_CHSEL6_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46420   ADC_SL6CFG_CHSEL6_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46421 } ADC_SL6CFG_CHSEL6_Enum;
46422 
46423 /* ================================================  ADC SL6CFG WCEN6 [1..1]  ================================================ */
46424 typedef enum {                                  /*!< ADC_SL6CFG_WCEN6                                                          */
46425   ADC_SL6CFG_WCEN6_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 6.                              */
46426   ADC_SL6CFG_WCEN6_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 6.                            */
46427 } ADC_SL6CFG_WCEN6_Enum;
46428 
46429 /* ================================================  ADC SL6CFG SLEN6 [0..0]  ================================================ */
46430 typedef enum {                                  /*!< ADC_SL6CFG_SLEN6                                                          */
46431   ADC_SL6CFG_SLEN6_SLEN                = 1,     /*!< SLEN : Enable slot 6 for ADC conversions.                                 */
46432   ADC_SL6CFG_SLEN6_SLDIS               = 0,     /*!< SLDIS : Disable slot 6 for ADC conversions.                               */
46433 } ADC_SL6CFG_SLEN6_Enum;
46434 
46435 /* ========================================================  SL7CFG  ========================================================= */
46436 /* ==============================================  ADC SL7CFG ADSEL7 [24..26]  =============================================== */
46437 typedef enum {                                  /*!< ADC_SL7CFG_ADSEL7                                                         */
46438   ADC_SL7CFG_ADSEL7_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46439                                                      module for this slot.                                                     */
46440   ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46441                                                      module for this slot.                                                     */
46442   ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46443                                                      module for this slot.                                                     */
46444   ADC_SL7CFG_ADSEL7_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46445                                                      module for this slot.                                                     */
46446   ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46447                                                      divide module for this slot.                                              */
46448   ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46449                                                      divide module for this slot.                                              */
46450   ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46451                                                      divide module for this slot.                                              */
46452   ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46453                                                      divide module for this slot.                                              */
46454 } ADC_SL7CFG_ADSEL7_Enum;
46455 
46456 /* ==============================================  ADC SL7CFG PRMODE7 [16..17]  ============================================== */
46457 typedef enum {                                  /*!< ADC_SL7CFG_PRMODE7                                                        */
46458   ADC_SL7CFG_PRMODE7_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46459   ADC_SL7CFG_PRMODE7_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46460   ADC_SL7CFG_PRMODE7_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46461   ADC_SL7CFG_PRMODE7_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46462 } ADC_SL7CFG_PRMODE7_Enum;
46463 
46464 /* ===============================================  ADC SL7CFG CHSEL7 [8..11]  =============================================== */
46465 typedef enum {                                  /*!< ADC_SL7CFG_CHSEL7                                                         */
46466   ADC_SL7CFG_CHSEL7_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46467   ADC_SL7CFG_CHSEL7_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46468   ADC_SL7CFG_CHSEL7_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46469   ADC_SL7CFG_CHSEL7_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46470   ADC_SL7CFG_CHSEL7_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46471   ADC_SL7CFG_CHSEL7_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46472   ADC_SL7CFG_CHSEL7_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46473   ADC_SL7CFG_CHSEL7_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46474   ADC_SL7CFG_CHSEL7_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46475   ADC_SL7CFG_CHSEL7_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46476   ADC_SL7CFG_CHSEL7_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46477   ADC_SL7CFG_CHSEL7_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46478 } ADC_SL7CFG_CHSEL7_Enum;
46479 
46480 /* ================================================  ADC SL7CFG WCEN7 [1..1]  ================================================ */
46481 typedef enum {                                  /*!< ADC_SL7CFG_WCEN7                                                          */
46482   ADC_SL7CFG_WCEN7_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 7.                              */
46483   ADC_SL7CFG_WCEN7_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 7.                            */
46484 } ADC_SL7CFG_WCEN7_Enum;
46485 
46486 /* ================================================  ADC SL7CFG SLEN7 [0..0]  ================================================ */
46487 typedef enum {                                  /*!< ADC_SL7CFG_SLEN7                                                          */
46488   ADC_SL7CFG_SLEN7_SLEN                = 1,     /*!< SLEN : Enable slot 7 for ADC conversions.                                 */
46489   ADC_SL7CFG_SLEN7_SLDIS               = 0,     /*!< SLDIS : Disable slot 7 for ADC conversions.                               */
46490 } ADC_SL7CFG_SLEN7_Enum;
46491 
46492 /* =========================================================  WULIM  ========================================================= */
46493 /* =========================================================  WLLIM  ========================================================= */
46494 /* ========================================================  SCWLIM  ========================================================= */
46495 /* =========================================================  FIFO  ========================================================== */
46496 /* ========================================================  FIFOPR  ========================================================= */
46497 /* =====================================================  INTTRIGTIMER  ====================================================== */
46498 /* ===========================================  ADC INTTRIGTIMER TIMEREN [31..31]  =========================================== */
46499 typedef enum {                                  /*!< ADC_INTTRIGTIMER_TIMEREN                                                  */
46500   ADC_INTTRIGTIMER_TIMEREN_DIS         = 0,     /*!< DIS : Disable the ADC-internal trigger timer.                             */
46501   ADC_INTTRIGTIMER_TIMEREN_EN          = 1,     /*!< EN : Enable the ADC-internal trigger timer.                               */
46502 } ADC_INTTRIGTIMER_TIMEREN_Enum;
46503 
46504 /* =========================================================  ZXCFG  ========================================================= */
46505 /* =========================================================  ZXLIM  ========================================================= */
46506 /* ========================================================  GAINCFG  ======================================================== */
46507 /* =============================================  ADC GAINCFG UPDATEMODE [4..4]  ============================================= */
46508 typedef enum {                                  /*!< ADC_GAINCFG_UPDATEMODE                                                    */
46509   ADC_GAINCFG_UPDATEMODE_IMMED         = 0,     /*!< IMMED : Immediate update mode. Once gain is written, it is immediately
46510                                                      encoded and provided to the PGA.                                          */
46511   ADC_GAINCFG_UPDATEMODE_ZX            = 1,     /*!< ZX : Update gain only at detected zero crossing as configured
46512                                                      by ZX registers.                                                          */
46513 } ADC_GAINCFG_UPDATEMODE_Enum;
46514 
46515 /* =========================================================  GAIN  ========================================================== */
46516 /* ========================================================  SATCFG  ========================================================= */
46517 /* ========================================================  SATLIM  ========================================================= */
46518 /* ========================================================  SATMAX  ========================================================= */
46519 /* ========================================================  SATCLR  ========================================================= */
46520 /* =========================================================  INTEN  ========================================================= */
46521 /* ===============================================  ADC INTEN SATCB [11..11]  ================================================ */
46522 typedef enum {                                  /*!< ADC_INTEN_SATCB                                                           */
46523   ADC_INTEN_SATCB_SATCBINT             = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
46524                                                      occurred on either slot 2 or 3 (channel B)                                */
46525   ADC_INTEN_SATCB_NONSATCBINT          = 0,     /*!< NONSATCBINT : No-Saturation                                               */
46526 } ADC_INTEN_SATCB_Enum;
46527 
46528 /* ===============================================  ADC INTEN SATCA [10..10]  ================================================ */
46529 typedef enum {                                  /*!< ADC_INTEN_SATCA                                                           */
46530   ADC_INTEN_SATCA_SATCAINT             = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
46531                                                      occurred on either slot 0 or 1 (channel A)                                */
46532   ADC_INTEN_SATCA_NONSATCAINT          = 0,     /*!< NONSATCAINT : No Saturation                                               */
46533 } ADC_INTEN_SATCA_Enum;
46534 
46535 /* =================================================  ADC INTEN ZXCB [9..9]  ================================================= */
46536 typedef enum {                                  /*!< ADC_INTEN_ZXCB                                                            */
46537   ADC_INTEN_ZXCB_ZXCBINT               = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
46538                                                      occurred on either slot 2 or 3 (channel B)                                */
46539   ADC_INTEN_ZXCB_NONZXCBINT            = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
46540 } ADC_INTEN_ZXCB_Enum;
46541 
46542 /* =================================================  ADC INTEN ZXCA [8..8]  ================================================= */
46543 typedef enum {                                  /*!< ADC_INTEN_ZXCA                                                            */
46544   ADC_INTEN_ZXCA_ZXCAINT               = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
46545                                                      occurred on either slot 0 or 1 (channel A)                                */
46546   ADC_INTEN_ZXCA_NONZXCAINT            = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
46547 } ADC_INTEN_ZXCA_Enum;
46548 
46549 /* =================================================  ADC INTEN DERR [7..7]  ================================================= */
46550 typedef enum {                                  /*!< ADC_INTEN_DERR                                                            */
46551   ADC_INTEN_DERR_DMAERROR              = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
46552   ADC_INTEN_DERR_NODMAERROR            = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
46553 } ADC_INTEN_DERR_Enum;
46554 
46555 /* =================================================  ADC INTEN DCMP [6..6]  ================================================= */
46556 typedef enum {                                  /*!< ADC_INTEN_DCMP                                                            */
46557   ADC_INTEN_DCMP_DMACOMPLETE           = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
46558   ADC_INTEN_DCMP_DMAON                 = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
46559 } ADC_INTEN_DCMP_Enum;
46560 
46561 /* ================================================  ADC INTEN WCINC [5..5]  ================================================= */
46562 typedef enum {                                  /*!< ADC_INTEN_WCINC                                                           */
46563   ADC_INTEN_WCINC_WCINCINT             = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
46564   ADC_INTEN_WCINC_WCINCNOINT           = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
46565 } ADC_INTEN_WCINC_Enum;
46566 
46567 /* ================================================  ADC INTEN WCEXC [4..4]  ================================================= */
46568 typedef enum {                                  /*!< ADC_INTEN_WCEXC                                                           */
46569   ADC_INTEN_WCEXC_WCEXCINT             = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
46570   ADC_INTEN_WCEXC_WCEXCNOINT           = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
46571 } ADC_INTEN_WCEXC_Enum;
46572 
46573 /* ===============================================  ADC INTEN FIFOOVR2 [3..3]  =============================================== */
46574 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR2                                                        */
46575   ADC_INTEN_FIFOOVR2_FIFOFULLINT       = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
46576   ADC_INTEN_FIFOOVR2_FIFOFULLNOINT     = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
46577 } ADC_INTEN_FIFOOVR2_Enum;
46578 
46579 /* ===============================================  ADC INTEN FIFOOVR1 [2..2]  =============================================== */
46580 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR1                                                        */
46581   ADC_INTEN_FIFOOVR1_FIFO75INT         = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
46582   ADC_INTEN_FIFOOVR1_FIFO75NOINT       = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
46583 } ADC_INTEN_FIFOOVR1_Enum;
46584 
46585 /* ================================================  ADC INTEN SCNCMP [1..1]  ================================================ */
46586 typedef enum {                                  /*!< ADC_INTEN_SCNCMP                                                          */
46587   ADC_INTEN_SCNCMP_SCNCMPINT           = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
46588   ADC_INTEN_SCNCMP_SCNCMPNOINT         = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
46589 } ADC_INTEN_SCNCMP_Enum;
46590 
46591 /* ================================================  ADC INTEN CNVCMP [0..0]  ================================================ */
46592 typedef enum {                                  /*!< ADC_INTEN_CNVCMP                                                          */
46593   ADC_INTEN_CNVCMP_CNVCMPINT           = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
46594   ADC_INTEN_CNVCMP_CNVCMPNOINT         = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
46595 } ADC_INTEN_CNVCMP_Enum;
46596 
46597 /* ========================================================  INTSTAT  ======================================================== */
46598 /* ==============================================  ADC INTSTAT SATCB [11..11]  =============================================== */
46599 typedef enum {                                  /*!< ADC_INTSTAT_SATCB                                                         */
46600   ADC_INTSTAT_SATCB_SATCBINT           = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
46601                                                      occurred on either slot 2 or 3 (channel B)                                */
46602   ADC_INTSTAT_SATCB_NONSATCBINT        = 0,     /*!< NONSATCBINT : No-Saturation                                               */
46603 } ADC_INTSTAT_SATCB_Enum;
46604 
46605 /* ==============================================  ADC INTSTAT SATCA [10..10]  =============================================== */
46606 typedef enum {                                  /*!< ADC_INTSTAT_SATCA                                                         */
46607   ADC_INTSTAT_SATCA_SATCAINT           = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
46608                                                      occurred on either slot 0 or 1 (channel A)                                */
46609   ADC_INTSTAT_SATCA_NONSATCAINT        = 0,     /*!< NONSATCAINT : No Saturation                                               */
46610 } ADC_INTSTAT_SATCA_Enum;
46611 
46612 /* ================================================  ADC INTSTAT ZXCB [9..9]  ================================================ */
46613 typedef enum {                                  /*!< ADC_INTSTAT_ZXCB                                                          */
46614   ADC_INTSTAT_ZXCB_ZXCBINT             = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
46615                                                      occurred on either slot 2 or 3 (channel B)                                */
46616   ADC_INTSTAT_ZXCB_NONZXCBINT          = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
46617 } ADC_INTSTAT_ZXCB_Enum;
46618 
46619 /* ================================================  ADC INTSTAT ZXCA [8..8]  ================================================ */
46620 typedef enum {                                  /*!< ADC_INTSTAT_ZXCA                                                          */
46621   ADC_INTSTAT_ZXCA_ZXCAINT             = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
46622                                                      occurred on either slot 0 or 1 (channel A)                                */
46623   ADC_INTSTAT_ZXCA_NONZXCAINT          = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
46624 } ADC_INTSTAT_ZXCA_Enum;
46625 
46626 /* ================================================  ADC INTSTAT DERR [7..7]  ================================================ */
46627 typedef enum {                                  /*!< ADC_INTSTAT_DERR                                                          */
46628   ADC_INTSTAT_DERR_DMAERROR            = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
46629   ADC_INTSTAT_DERR_NODMAERROR          = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
46630 } ADC_INTSTAT_DERR_Enum;
46631 
46632 /* ================================================  ADC INTSTAT DCMP [6..6]  ================================================ */
46633 typedef enum {                                  /*!< ADC_INTSTAT_DCMP                                                          */
46634   ADC_INTSTAT_DCMP_DMACOMPLETE         = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
46635   ADC_INTSTAT_DCMP_DMAON               = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
46636 } ADC_INTSTAT_DCMP_Enum;
46637 
46638 /* ===============================================  ADC INTSTAT WCINC [5..5]  ================================================ */
46639 typedef enum {                                  /*!< ADC_INTSTAT_WCINC                                                         */
46640   ADC_INTSTAT_WCINC_WCINCINT           = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
46641   ADC_INTSTAT_WCINC_WCINCNOINT         = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
46642 } ADC_INTSTAT_WCINC_Enum;
46643 
46644 /* ===============================================  ADC INTSTAT WCEXC [4..4]  ================================================ */
46645 typedef enum {                                  /*!< ADC_INTSTAT_WCEXC                                                         */
46646   ADC_INTSTAT_WCEXC_WCEXCINT           = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
46647   ADC_INTSTAT_WCEXC_WCEXCNOINT         = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
46648 } ADC_INTSTAT_WCEXC_Enum;
46649 
46650 /* ==============================================  ADC INTSTAT FIFOOVR2 [3..3]  ============================================== */
46651 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR2                                                      */
46652   ADC_INTSTAT_FIFOOVR2_FIFOFULLINT     = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
46653   ADC_INTSTAT_FIFOOVR2_FIFOFULLNOINT   = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
46654 } ADC_INTSTAT_FIFOOVR2_Enum;
46655 
46656 /* ==============================================  ADC INTSTAT FIFOOVR1 [2..2]  ============================================== */
46657 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR1                                                      */
46658   ADC_INTSTAT_FIFOOVR1_FIFO75INT       = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
46659   ADC_INTSTAT_FIFOOVR1_FIFO75NOINT     = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
46660 } ADC_INTSTAT_FIFOOVR1_Enum;
46661 
46662 /* ===============================================  ADC INTSTAT SCNCMP [1..1]  =============================================== */
46663 typedef enum {                                  /*!< ADC_INTSTAT_SCNCMP                                                        */
46664   ADC_INTSTAT_SCNCMP_SCNCMPINT         = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
46665   ADC_INTSTAT_SCNCMP_SCNCMPNOINT       = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
46666 } ADC_INTSTAT_SCNCMP_Enum;
46667 
46668 /* ===============================================  ADC INTSTAT CNVCMP [0..0]  =============================================== */
46669 typedef enum {                                  /*!< ADC_INTSTAT_CNVCMP                                                        */
46670   ADC_INTSTAT_CNVCMP_CNVCMPINT         = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
46671   ADC_INTSTAT_CNVCMP_CNVCMPNOINT       = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
46672 } ADC_INTSTAT_CNVCMP_Enum;
46673 
46674 /* ========================================================  INTCLR  ========================================================= */
46675 /* ===============================================  ADC INTCLR SATCB [11..11]  =============================================== */
46676 typedef enum {                                  /*!< ADC_INTCLR_SATCB                                                          */
46677   ADC_INTCLR_SATCB_SATCBINT            = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
46678                                                      occurred on either slot 2 or 3 (channel B)                                */
46679   ADC_INTCLR_SATCB_NONSATCBINT         = 0,     /*!< NONSATCBINT : No-Saturation                                               */
46680 } ADC_INTCLR_SATCB_Enum;
46681 
46682 /* ===============================================  ADC INTCLR SATCA [10..10]  =============================================== */
46683 typedef enum {                                  /*!< ADC_INTCLR_SATCA                                                          */
46684   ADC_INTCLR_SATCA_SATCAINT            = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
46685                                                      occurred on either slot 0 or 1 (channel A)                                */
46686   ADC_INTCLR_SATCA_NONSATCAINT         = 0,     /*!< NONSATCAINT : No Saturation                                               */
46687 } ADC_INTCLR_SATCA_Enum;
46688 
46689 /* ================================================  ADC INTCLR ZXCB [9..9]  ================================================= */
46690 typedef enum {                                  /*!< ADC_INTCLR_ZXCB                                                           */
46691   ADC_INTCLR_ZXCB_ZXCBINT              = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
46692                                                      occurred on either slot 2 or 3 (channel B)                                */
46693   ADC_INTCLR_ZXCB_NONZXCBINT           = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
46694 } ADC_INTCLR_ZXCB_Enum;
46695 
46696 /* ================================================  ADC INTCLR ZXCA [8..8]  ================================================= */
46697 typedef enum {                                  /*!< ADC_INTCLR_ZXCA                                                           */
46698   ADC_INTCLR_ZXCA_ZXCAINT              = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
46699                                                      occurred on either slot 0 or 1 (channel A)                                */
46700   ADC_INTCLR_ZXCA_NONZXCAINT           = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
46701 } ADC_INTCLR_ZXCA_Enum;
46702 
46703 /* ================================================  ADC INTCLR DERR [7..7]  ================================================= */
46704 typedef enum {                                  /*!< ADC_INTCLR_DERR                                                           */
46705   ADC_INTCLR_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
46706   ADC_INTCLR_DERR_NODMAERROR           = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
46707 } ADC_INTCLR_DERR_Enum;
46708 
46709 /* ================================================  ADC INTCLR DCMP [6..6]  ================================================= */
46710 typedef enum {                                  /*!< ADC_INTCLR_DCMP                                                           */
46711   ADC_INTCLR_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
46712   ADC_INTCLR_DCMP_DMAON                = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
46713 } ADC_INTCLR_DCMP_Enum;
46714 
46715 /* ================================================  ADC INTCLR WCINC [5..5]  ================================================ */
46716 typedef enum {                                  /*!< ADC_INTCLR_WCINC                                                          */
46717   ADC_INTCLR_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
46718   ADC_INTCLR_WCINC_WCINCNOINT          = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
46719 } ADC_INTCLR_WCINC_Enum;
46720 
46721 /* ================================================  ADC INTCLR WCEXC [4..4]  ================================================ */
46722 typedef enum {                                  /*!< ADC_INTCLR_WCEXC                                                          */
46723   ADC_INTCLR_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
46724   ADC_INTCLR_WCEXC_WCEXCNOINT          = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
46725 } ADC_INTCLR_WCEXC_Enum;
46726 
46727 /* ==============================================  ADC INTCLR FIFOOVR2 [3..3]  =============================================== */
46728 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR2                                                       */
46729   ADC_INTCLR_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
46730   ADC_INTCLR_FIFOOVR2_FIFOFULLNOINT    = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
46731 } ADC_INTCLR_FIFOOVR2_Enum;
46732 
46733 /* ==============================================  ADC INTCLR FIFOOVR1 [2..2]  =============================================== */
46734 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR1                                                       */
46735   ADC_INTCLR_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
46736   ADC_INTCLR_FIFOOVR1_FIFO75NOINT      = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
46737 } ADC_INTCLR_FIFOOVR1_Enum;
46738 
46739 /* ===============================================  ADC INTCLR SCNCMP [1..1]  ================================================ */
46740 typedef enum {                                  /*!< ADC_INTCLR_SCNCMP                                                         */
46741   ADC_INTCLR_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
46742   ADC_INTCLR_SCNCMP_SCNCMPNOINT        = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
46743 } ADC_INTCLR_SCNCMP_Enum;
46744 
46745 /* ===============================================  ADC INTCLR CNVCMP [0..0]  ================================================ */
46746 typedef enum {                                  /*!< ADC_INTCLR_CNVCMP                                                         */
46747   ADC_INTCLR_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
46748   ADC_INTCLR_CNVCMP_CNVCMPNOINT        = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
46749 } ADC_INTCLR_CNVCMP_Enum;
46750 
46751 /* ========================================================  INTSET  ========================================================= */
46752 /* ===============================================  ADC INTSET SATCB [11..11]  =============================================== */
46753 typedef enum {                                  /*!< ADC_INTSET_SATCB                                                          */
46754   ADC_INTSET_SATCB_SATCBINT            = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
46755                                                      occurred on either slot 2 or 3 (channel B)                                */
46756   ADC_INTSET_SATCB_NONSATCBINT         = 0,     /*!< NONSATCBINT : No-Saturation                                               */
46757 } ADC_INTSET_SATCB_Enum;
46758 
46759 /* ===============================================  ADC INTSET SATCA [10..10]  =============================================== */
46760 typedef enum {                                  /*!< ADC_INTSET_SATCA                                                          */
46761   ADC_INTSET_SATCA_SATCAINT            = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
46762                                                      occurred on either slot 0 or 1 (channel A)                                */
46763   ADC_INTSET_SATCA_NONSATCAINT         = 0,     /*!< NONSATCAINT : No Saturation                                               */
46764 } ADC_INTSET_SATCA_Enum;
46765 
46766 /* ================================================  ADC INTSET ZXCB [9..9]  ================================================= */
46767 typedef enum {                                  /*!< ADC_INTSET_ZXCB                                                           */
46768   ADC_INTSET_ZXCB_ZXCBINT              = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
46769                                                      occurred on either slot 2 or 3 (channel B)                                */
46770   ADC_INTSET_ZXCB_NONZXCBINT           = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
46771 } ADC_INTSET_ZXCB_Enum;
46772 
46773 /* ================================================  ADC INTSET ZXCA [8..8]  ================================================= */
46774 typedef enum {                                  /*!< ADC_INTSET_ZXCA                                                           */
46775   ADC_INTSET_ZXCA_ZXCAINT              = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
46776                                                      occurred on either slot 0 or 1 (channel A)                                */
46777   ADC_INTSET_ZXCA_NONZXCAINT           = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
46778 } ADC_INTSET_ZXCA_Enum;
46779 
46780 /* ================================================  ADC INTSET DERR [7..7]  ================================================= */
46781 typedef enum {                                  /*!< ADC_INTSET_DERR                                                           */
46782   ADC_INTSET_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
46783   ADC_INTSET_DERR_NODMAERROR           = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
46784 } ADC_INTSET_DERR_Enum;
46785 
46786 /* ================================================  ADC INTSET DCMP [6..6]  ================================================= */
46787 typedef enum {                                  /*!< ADC_INTSET_DCMP                                                           */
46788   ADC_INTSET_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
46789   ADC_INTSET_DCMP_DMAON                = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
46790 } ADC_INTSET_DCMP_Enum;
46791 
46792 /* ================================================  ADC INTSET WCINC [5..5]  ================================================ */
46793 typedef enum {                                  /*!< ADC_INTSET_WCINC                                                          */
46794   ADC_INTSET_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
46795   ADC_INTSET_WCINC_WCINCNOINT          = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
46796 } ADC_INTSET_WCINC_Enum;
46797 
46798 /* ================================================  ADC INTSET WCEXC [4..4]  ================================================ */
46799 typedef enum {                                  /*!< ADC_INTSET_WCEXC                                                          */
46800   ADC_INTSET_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
46801   ADC_INTSET_WCEXC_WCEXCNOINT          = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
46802 } ADC_INTSET_WCEXC_Enum;
46803 
46804 /* ==============================================  ADC INTSET FIFOOVR2 [3..3]  =============================================== */
46805 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR2                                                       */
46806   ADC_INTSET_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
46807   ADC_INTSET_FIFOOVR2_FIFOFULLNOINT    = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
46808 } ADC_INTSET_FIFOOVR2_Enum;
46809 
46810 /* ==============================================  ADC INTSET FIFOOVR1 [2..2]  =============================================== */
46811 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR1                                                       */
46812   ADC_INTSET_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
46813   ADC_INTSET_FIFOOVR1_FIFO75NOINT      = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
46814 } ADC_INTSET_FIFOOVR1_Enum;
46815 
46816 /* ===============================================  ADC INTSET SCNCMP [1..1]  ================================================ */
46817 typedef enum {                                  /*!< ADC_INTSET_SCNCMP                                                         */
46818   ADC_INTSET_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
46819   ADC_INTSET_SCNCMP_SCNCMPNOINT        = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
46820 } ADC_INTSET_SCNCMP_Enum;
46821 
46822 /* ===============================================  ADC INTSET CNVCMP [0..0]  ================================================ */
46823 typedef enum {                                  /*!< ADC_INTSET_CNVCMP                                                         */
46824   ADC_INTSET_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
46825   ADC_INTSET_CNVCMP_CNVCMPNOINT        = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
46826 } ADC_INTSET_CNVCMP_Enum;
46827 
46828 /* =======================================================  DMATRIGEN  ======================================================= */
46829 /* ======================================================  DMATRIGSTAT  ====================================================== */
46830 /* ========================================================  DMACFG  ========================================================= */
46831 /* ==============================================  ADC DMACFG DMAMSK [17..17]  =============================================== */
46832 typedef enum {                                  /*!< ADC_DMACFG_DMAMSK                                                         */
46833   ADC_DMACFG_DMAMSK_DIS                = 0,     /*!< DIS : FIFO Contents are copied directly to memory without modification.   */
46834   ADC_DMACFG_DMAMSK_EN                 = 1,     /*!< EN : Only the FIFODATA contents are copied to memory on DMA
46835                                                      transfers. The SLOTNUM and FIFOCNT contents are cleared
46836                                                      to zero.                                                                  */
46837 } ADC_DMACFG_DMAMSK_Enum;
46838 
46839 /* ==============================================  ADC DMACFG DMADYNPRI [9..9]  ============================================== */
46840 typedef enum {                                  /*!< ADC_DMACFG_DMADYNPRI                                                      */
46841   ADC_DMACFG_DMADYNPRI_DIS             = 0,     /*!< DIS : Disable dynamic priority (use DMAPRI setting only)                  */
46842   ADC_DMACFG_DMADYNPRI_EN              = 1,     /*!< EN : Enable dynamic priority                                              */
46843 } ADC_DMACFG_DMADYNPRI_Enum;
46844 
46845 /* ===============================================  ADC DMACFG DMAPRI [8..8]  ================================================ */
46846 typedef enum {                                  /*!< ADC_DMACFG_DMAPRI                                                         */
46847   ADC_DMACFG_DMAPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
46848   ADC_DMACFG_DMAPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
46849 } ADC_DMACFG_DMAPRI_Enum;
46850 
46851 /* ===============================================  ADC DMACFG DMADIR [2..2]  ================================================ */
46852 typedef enum {                                  /*!< ADC_DMACFG_DMADIR                                                         */
46853   ADC_DMACFG_DMADIR_P2M                = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
46854   ADC_DMACFG_DMADIR_M2P                = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
46855 } ADC_DMACFG_DMADIR_Enum;
46856 
46857 /* ================================================  ADC DMACFG DMAEN [0..0]  ================================================ */
46858 typedef enum {                                  /*!< ADC_DMACFG_DMAEN                                                          */
46859   ADC_DMACFG_DMAEN_DIS                 = 0,     /*!< DIS : Disable DMA Function                                                */
46860   ADC_DMACFG_DMAEN_EN                  = 1,     /*!< EN : Enable DMA Function                                                  */
46861 } ADC_DMACFG_DMAEN_Enum;
46862 
46863 /* ======================================================  DMATOTCOUNT  ====================================================== */
46864 /* ======================================================  DMATARGADDR  ====================================================== */
46865 /* ========================================================  DMASTAT  ======================================================== */
46866 
46867 
46868 /* =========================================================================================================================== */
46869 /* ================                                          APBDMA                                           ================ */
46870 /* =========================================================================================================================== */
46871 
46872 /* ========================================================  BBVALUE  ======================================================== */
46873 /* ======================================================  BBSETCLEAR  ======================================================= */
46874 /* ========================================================  BBINPUT  ======================================================== */
46875 /* =======================================================  DEBUGDATA  ======================================================= */
46876 /* =========================================================  DEBUG  ========================================================= */
46877 /* ==============================================  APBDMA DEBUG DEBUGEN [0..3]  ============================================== */
46878 typedef enum {                                  /*!< APBDMA_DEBUG_DEBUGEN                                                      */
46879   APBDMA_DEBUG_DEBUGEN_OFF             = 0,     /*!< OFF : Debug Disabled                                                      */
46880   APBDMA_DEBUG_DEBUGEN_ARB             = 1,     /*!< ARB : Debug Arb values                                                    */
46881 } APBDMA_DEBUG_DEBUGEN_Enum;
46882 
46883 
46884 
46885 /* =========================================================================================================================== */
46886 /* ================                                          AUDADC                                           ================ */
46887 /* =========================================================================================================================== */
46888 
46889 /* ==========================================================  CFG  ========================================================== */
46890 /* ==============================================  AUDADC CFG CLKSEL [24..25]  =============================================== */
46891 typedef enum {                                  /*!< AUDADC_CFG_CLKSEL                                                         */
46892   AUDADC_CFG_CLKSEL_OFF                = 0,     /*!< OFF : Off mode. The HFRC, HFRC2, or high frequency XTAL clock
46893                                                      must be selected for the AUDADC to function. The AUDADC
46894                                                      controller automatically shuts off the clock in its low
46895                                                      power modes. When setting ADCEN to '0', the CLKSEL should
46896                                                      remain set to one of the two clock selects for proper power
46897                                                      down sequencing.                                                          */
46898   AUDADC_CFG_CLKSEL_HFRC_48MHz         = 1,     /*!< HFRC_48MHz : HFRC Clock                                                   */
46899   AUDADC_CFG_CLKSEL_XTALHS_24MHz       = 2,     /*!< XTALHS_24MHz : High frequency XTAL (nominally 24.567 MHz, but
46900                                                      can vary depending on which XTAL is selected)                             */
46901   AUDADC_CFG_CLKSEL_HFRC2_48MHz        = 3,     /*!< HFRC2_48MHz : HFRC2 Clock                                                 */
46902 } AUDADC_CFG_CLKSEL_Enum;
46903 
46904 /* ============================================  AUDADC CFG RPTTRIGSEL [20..20]  ============================================= */
46905 typedef enum {                                  /*!< AUDADC_CFG_RPTTRIGSEL                                                     */
46906   AUDADC_CFG_RPTTRIGSEL_TMR            = 0,     /*!< TMR : Trigger from on-chip timer.                                         */
46907   AUDADC_CFG_RPTTRIGSEL_INT            = 1,     /*!< INT : Trigger from AUDADC-internal timer.                                 */
46908 } AUDADC_CFG_RPTTRIGSEL_Enum;
46909 
46910 /* ==============================================  AUDADC CFG TRIGPOL [19..19]  ============================================== */
46911 typedef enum {                                  /*!< AUDADC_CFG_TRIGPOL                                                        */
46912   AUDADC_CFG_TRIGPOL_RISING_EDGE       = 0,     /*!< RISING_EDGE : Trigger on rising edge.                                     */
46913   AUDADC_CFG_TRIGPOL_FALLING_EDGE      = 1,     /*!< FALLING_EDGE : Trigger on falling edge.                                   */
46914 } AUDADC_CFG_TRIGPOL_Enum;
46915 
46916 /* ==============================================  AUDADC CFG TRIGSEL [16..18]  ============================================== */
46917 typedef enum {                                  /*!< AUDADC_CFG_TRIGSEL                                                        */
46918   AUDADC_CFG_TRIGSEL_EXT0              = 0,     /*!< EXT0 : Off chip External Trigger0 (ADC_ET0)                               */
46919   AUDADC_CFG_TRIGSEL_EXT1              = 1,     /*!< EXT1 : Off chip External Trigger1 (ADC_ET1)                               */
46920   AUDADC_CFG_TRIGSEL_EXT2              = 2,     /*!< EXT2 : Off chip External Trigger2 (ADC_ET2)                               */
46921   AUDADC_CFG_TRIGSEL_EXT3              = 3,     /*!< EXT3 : Off chip External Trigger3 (ADC_ET3)                               */
46922   AUDADC_CFG_TRIGSEL_VCOMP             = 4,     /*!< VCOMP : Voltage Comparator Output                                         */
46923   AUDADC_CFG_TRIGSEL_SWT               = 7,     /*!< SWT : Software Trigger                                                    */
46924 } AUDADC_CFG_TRIGSEL_Enum;
46925 
46926 /* =============================================  AUDADC CFG SAMPMODE [13..13]  ============================================== */
46927 typedef enum {                                  /*!< AUDADC_CFG_SAMPMODE                                                       */
46928   AUDADC_CFG_SAMPMODE_LP               = 0,     /*!< LP : Max of 2 low-gain PGA channels configured on slots 0 and
46929                                                      2. In this mode, slots 1 and 3, if enabled, will still
46930                                                      consume time but not perform conversions.                                 */
46931   AUDADC_CFG_SAMPMODE_MED              = 1,     /*!< MED : Max of 2 low-gain and 2 high-gain PGA channels. In this
46932                                                      mode, conversions will be performed on all enabled slots
46933                                                      0 through 3.                                                              */
46934 } AUDADC_CFG_SAMPMODE_Enum;
46935 
46936 /* =============================================  AUDADC CFG DFIFORDEN [12..12]  ============================================= */
46937 typedef enum {                                  /*!< AUDADC_CFG_DFIFORDEN                                                      */
46938   AUDADC_CFG_DFIFORDEN_DIS             = 0,     /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
46939                                                      will not POP an entry off the FIFO.                                       */
46940   AUDADC_CFG_DFIFORDEN_EN              = 1,     /*!< EN : Reads to the FIFOPR registger will automatically pop an
46941                                                      entry off the FIFO.                                                       */
46942 } AUDADC_CFG_DFIFORDEN_Enum;
46943 
46944 /* ===============================================  AUDADC CFG CKMODE [4..4]  ================================================ */
46945 typedef enum {                                  /*!< AUDADC_CFG_CKMODE                                                         */
46946   AUDADC_CFG_CKMODE_LPCKMODE           = 0,     /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
46947                                                      LPCKMODE to 0x1 while configuring the AUDADC.                             */
46948   AUDADC_CFG_CKMODE_LLCKMODE           = 1,     /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
46949                                                      will remain on while in functioning in LPMODE0.                           */
46950 } AUDADC_CFG_CKMODE_Enum;
46951 
46952 /* ===============================================  AUDADC CFG LPMODE [3..3]  ================================================ */
46953 typedef enum {                                  /*!< AUDADC_CFG_LPMODE                                                         */
46954   AUDADC_CFG_LPMODE_MODE0              = 0,     /*!< MODE0 : Low Power Mode 0. Leaves the AUDADC fully powered between
46955                                                      scans with minimum latency between a trigger event and
46956                                                      sample data collection.                                                   */
46957   AUDADC_CFG_LPMODE_MODE1              = 1,     /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
46958                                                      associated with the AUDADC until the next trigger event.
46959                                                      Between scans, the reference buffer requires up to 50us
46960                                                      of delay from a scan trigger event before the conversion
46961                                                      will commence while operating in this mode.                               */
46962 } AUDADC_CFG_LPMODE_Enum;
46963 
46964 /* ================================================  AUDADC CFG RPTEN [2..2]  ================================================ */
46965 typedef enum {                                  /*!< AUDADC_CFG_RPTEN                                                          */
46966   AUDADC_CFG_RPTEN_SINGLE_SCAN         = 0,     /*!< SINGLE_SCAN : In Single Scan Mode, the AUDADC will complete
46967                                                      a single scan upon each trigger event.                                    */
46968   AUDADC_CFG_RPTEN_REPEATING_SCAN      = 1,     /*!< REPEATING_SCAN : In Repeating Scan Mode, the AUDADC will complete
46969                                                      its first scan upon the initial trigger event and all subsequent
46970                                                      scans will occur at regular intervals defined by the configuration
46971                                                      programmed for the CTTMRA3 timer or the AUDADC-internal
46972                                                      timer (see the RPTTRIGSEL field) until the timer is disabled
46973                                                      or the AUDADC is disabled. When disabling the AUDADC (setting
46974                                                      ADCEN to '0'), the RPTEN bit should be cleared.                           */
46975 } AUDADC_CFG_RPTEN_Enum;
46976 
46977 /* ================================================  AUDADC CFG ADCEN [0..0]  ================================================ */
46978 typedef enum {                                  /*!< AUDADC_CFG_ADCEN                                                          */
46979   AUDADC_CFG_ADCEN_DIS                 = 0,     /*!< DIS : Disable the AUDADC module.                                          */
46980   AUDADC_CFG_ADCEN_EN                  = 1,     /*!< EN : Enable the AUDADC module.                                            */
46981 } AUDADC_CFG_ADCEN_Enum;
46982 
46983 /* =========================================================  STAT  ========================================================== */
46984 /* ==============================================  AUDADC STAT PWDSTAT [0..0]  =============================================== */
46985 typedef enum {                                  /*!< AUDADC_STAT_PWDSTAT                                                       */
46986   AUDADC_STAT_PWDSTAT_ON               = 0,     /*!< ON : Powered on.                                                          */
46987   AUDADC_STAT_PWDSTAT_POWERED_DOWN     = 1,     /*!< POWERED_DOWN : AUDADC Low Power Mode 1.                                   */
46988 } AUDADC_STAT_PWDSTAT_Enum;
46989 
46990 /* ==========================================================  SWT  ========================================================== */
46991 /* =================================================  AUDADC SWT SWT [0..7]  ================================================= */
46992 typedef enum {                                  /*!< AUDADC_SWT_SWT                                                            */
46993   AUDADC_SWT_SWT_GEN_SW_TRIGGER        = 55,    /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger.         */
46994   AUDADC_SWT_SWT_NO_SW_TRIGGER         = 0,     /*!< NO_SW_TRIGGER : Default value.                                            */
46995 } AUDADC_SWT_SWT_Enum;
46996 
46997 /* ========================================================  SL0CFG  ========================================================= */
46998 /* =============================================  AUDADC SL0CFG ADSEL0 [24..26]  ============================================= */
46999 typedef enum {                                  /*!< AUDADC_SL0CFG_ADSEL0                                                      */
47000   AUDADC_SL0CFG_ADSEL0_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47001                                                      module for this slot.                                                     */
47002   AUDADC_SL0CFG_ADSEL0_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47003                                                      module for this slot.                                                     */
47004   AUDADC_SL0CFG_ADSEL0_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47005                                                      module for this slot.                                                     */
47006   AUDADC_SL0CFG_ADSEL0_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47007                                                      module for this slot.                                                     */
47008   AUDADC_SL0CFG_ADSEL0_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47009                                                      divide module for this slot.                                              */
47010   AUDADC_SL0CFG_ADSEL0_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47011                                                      divide module for this slot.                                              */
47012   AUDADC_SL0CFG_ADSEL0_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47013                                                      divide module for this slot.                                              */
47014   AUDADC_SL0CFG_ADSEL0_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47015                                                      divide module for this slot.                                              */
47016 } AUDADC_SL0CFG_ADSEL0_Enum;
47017 
47018 /* ============================================  AUDADC SL0CFG PRMODE0 [16..17]  ============================================= */
47019 typedef enum {                                  /*!< AUDADC_SL0CFG_PRMODE0                                                     */
47020   AUDADC_SL0CFG_PRMODE0_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47021   AUDADC_SL0CFG_PRMODE0_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47022   AUDADC_SL0CFG_PRMODE0_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47023   AUDADC_SL0CFG_PRMODE0_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47024 } AUDADC_SL0CFG_PRMODE0_Enum;
47025 
47026 /* =============================================  AUDADC SL0CFG CHSEL0 [8..11]  ============================================== */
47027 typedef enum {                                  /*!< AUDADC_SL0CFG_CHSEL0                                                      */
47028   AUDADC_SL0CFG_CHSEL0_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47029   AUDADC_SL0CFG_CHSEL0_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47030   AUDADC_SL0CFG_CHSEL0_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47031   AUDADC_SL0CFG_CHSEL0_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47032 } AUDADC_SL0CFG_CHSEL0_Enum;
47033 
47034 /* ==============================================  AUDADC SL0CFG WCEN0 [1..1]  =============================================== */
47035 typedef enum {                                  /*!< AUDADC_SL0CFG_WCEN0                                                       */
47036   AUDADC_SL0CFG_WCEN0_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 0.                              */
47037   AUDADC_SL0CFG_WCEN0_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 0.                            */
47038 } AUDADC_SL0CFG_WCEN0_Enum;
47039 
47040 /* ==============================================  AUDADC SL0CFG SLEN0 [0..0]  =============================================== */
47041 typedef enum {                                  /*!< AUDADC_SL0CFG_SLEN0                                                       */
47042   AUDADC_SL0CFG_SLEN0_SLEN             = 1,     /*!< SLEN : Enable slot 0 for AUDADC conversions.                              */
47043   AUDADC_SL0CFG_SLEN0_SLDIS            = 0,     /*!< SLDIS : Disable slot 0 for AUDADC conversions.                            */
47044 } AUDADC_SL0CFG_SLEN0_Enum;
47045 
47046 /* ========================================================  SL1CFG  ========================================================= */
47047 /* =============================================  AUDADC SL1CFG ADSEL1 [24..26]  ============================================= */
47048 typedef enum {                                  /*!< AUDADC_SL1CFG_ADSEL1                                                      */
47049   AUDADC_SL1CFG_ADSEL1_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47050                                                      module for this slot.                                                     */
47051   AUDADC_SL1CFG_ADSEL1_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47052                                                      module for this slot.                                                     */
47053   AUDADC_SL1CFG_ADSEL1_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47054                                                      module for this slot.                                                     */
47055   AUDADC_SL1CFG_ADSEL1_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47056                                                      module for this slot.                                                     */
47057   AUDADC_SL1CFG_ADSEL1_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47058                                                      divide module for this slot.                                              */
47059   AUDADC_SL1CFG_ADSEL1_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47060                                                      divide module for this slot.                                              */
47061   AUDADC_SL1CFG_ADSEL1_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47062                                                      divide module for this slot.                                              */
47063   AUDADC_SL1CFG_ADSEL1_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47064                                                      divide module for this slot.                                              */
47065 } AUDADC_SL1CFG_ADSEL1_Enum;
47066 
47067 /* ============================================  AUDADC SL1CFG PRMODE1 [16..17]  ============================================= */
47068 typedef enum {                                  /*!< AUDADC_SL1CFG_PRMODE1                                                     */
47069   AUDADC_SL1CFG_PRMODE1_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47070   AUDADC_SL1CFG_PRMODE1_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47071   AUDADC_SL1CFG_PRMODE1_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47072   AUDADC_SL1CFG_PRMODE1_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47073 } AUDADC_SL1CFG_PRMODE1_Enum;
47074 
47075 /* =============================================  AUDADC SL1CFG CHSEL1 [8..11]  ============================================== */
47076 typedef enum {                                  /*!< AUDADC_SL1CFG_CHSEL1                                                      */
47077   AUDADC_SL1CFG_CHSEL1_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47078   AUDADC_SL1CFG_CHSEL1_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47079   AUDADC_SL1CFG_CHSEL1_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47080   AUDADC_SL1CFG_CHSEL1_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47081 } AUDADC_SL1CFG_CHSEL1_Enum;
47082 
47083 /* ==============================================  AUDADC SL1CFG WCEN1 [1..1]  =============================================== */
47084 typedef enum {                                  /*!< AUDADC_SL1CFG_WCEN1                                                       */
47085   AUDADC_SL1CFG_WCEN1_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 1.                              */
47086   AUDADC_SL1CFG_WCEN1_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 1.                            */
47087 } AUDADC_SL1CFG_WCEN1_Enum;
47088 
47089 /* ==============================================  AUDADC SL1CFG SLEN1 [0..0]  =============================================== */
47090 typedef enum {                                  /*!< AUDADC_SL1CFG_SLEN1                                                       */
47091   AUDADC_SL1CFG_SLEN1_SLEN             = 1,     /*!< SLEN : Enable slot 1 for AUDADC conversions.                              */
47092   AUDADC_SL1CFG_SLEN1_SLDIS            = 0,     /*!< SLDIS : Disable slot 1 for AUDADC conversions.                            */
47093 } AUDADC_SL1CFG_SLEN1_Enum;
47094 
47095 /* ========================================================  SL2CFG  ========================================================= */
47096 /* =============================================  AUDADC SL2CFG ADSEL2 [24..26]  ============================================= */
47097 typedef enum {                                  /*!< AUDADC_SL2CFG_ADSEL2                                                      */
47098   AUDADC_SL2CFG_ADSEL2_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47099                                                      module for this slot.                                                     */
47100   AUDADC_SL2CFG_ADSEL2_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47101                                                      module for this slot.                                                     */
47102   AUDADC_SL2CFG_ADSEL2_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47103                                                      module for this slot.                                                     */
47104   AUDADC_SL2CFG_ADSEL2_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47105                                                      module for this slot.                                                     */
47106   AUDADC_SL2CFG_ADSEL2_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47107                                                      divide module for this slot.                                              */
47108   AUDADC_SL2CFG_ADSEL2_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47109                                                      divide module for this slot.                                              */
47110   AUDADC_SL2CFG_ADSEL2_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47111                                                      divide module for this slot.                                              */
47112   AUDADC_SL2CFG_ADSEL2_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47113                                                      divide module for this slot.                                              */
47114 } AUDADC_SL2CFG_ADSEL2_Enum;
47115 
47116 /* ============================================  AUDADC SL2CFG PRMODE2 [16..17]  ============================================= */
47117 typedef enum {                                  /*!< AUDADC_SL2CFG_PRMODE2                                                     */
47118   AUDADC_SL2CFG_PRMODE2_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47119   AUDADC_SL2CFG_PRMODE2_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47120   AUDADC_SL2CFG_PRMODE2_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47121   AUDADC_SL2CFG_PRMODE2_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47122 } AUDADC_SL2CFG_PRMODE2_Enum;
47123 
47124 /* =============================================  AUDADC SL2CFG CHSEL2 [8..11]  ============================================== */
47125 typedef enum {                                  /*!< AUDADC_SL2CFG_CHSEL2                                                      */
47126   AUDADC_SL2CFG_CHSEL2_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47127   AUDADC_SL2CFG_CHSEL2_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47128   AUDADC_SL2CFG_CHSEL2_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47129   AUDADC_SL2CFG_CHSEL2_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47130 } AUDADC_SL2CFG_CHSEL2_Enum;
47131 
47132 /* ==============================================  AUDADC SL2CFG WCEN2 [1..1]  =============================================== */
47133 typedef enum {                                  /*!< AUDADC_SL2CFG_WCEN2                                                       */
47134   AUDADC_SL2CFG_WCEN2_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 2.                              */
47135   AUDADC_SL2CFG_WCEN2_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 2.                            */
47136 } AUDADC_SL2CFG_WCEN2_Enum;
47137 
47138 /* ==============================================  AUDADC SL2CFG SLEN2 [0..0]  =============================================== */
47139 typedef enum {                                  /*!< AUDADC_SL2CFG_SLEN2                                                       */
47140   AUDADC_SL2CFG_SLEN2_SLEN             = 1,     /*!< SLEN : Enable slot 2 for AUDADC conversions.                              */
47141   AUDADC_SL2CFG_SLEN2_SLDIS            = 0,     /*!< SLDIS : Disable slot 2 for AUDADC conversions.                            */
47142 } AUDADC_SL2CFG_SLEN2_Enum;
47143 
47144 /* ========================================================  SL3CFG  ========================================================= */
47145 /* =============================================  AUDADC SL3CFG ADSEL3 [24..26]  ============================================= */
47146 typedef enum {                                  /*!< AUDADC_SL3CFG_ADSEL3                                                      */
47147   AUDADC_SL3CFG_ADSEL3_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47148                                                      module for this slot.                                                     */
47149   AUDADC_SL3CFG_ADSEL3_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47150                                                      module for this slot.                                                     */
47151   AUDADC_SL3CFG_ADSEL3_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47152                                                      module for this slot.                                                     */
47153   AUDADC_SL3CFG_ADSEL3_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47154                                                      module for this slot.                                                     */
47155   AUDADC_SL3CFG_ADSEL3_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47156                                                      divide module for this slot.                                              */
47157   AUDADC_SL3CFG_ADSEL3_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47158                                                      divide module for this slot.                                              */
47159   AUDADC_SL3CFG_ADSEL3_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47160                                                      divide module for this slot.                                              */
47161   AUDADC_SL3CFG_ADSEL3_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47162                                                      divide module for this slot.                                              */
47163 } AUDADC_SL3CFG_ADSEL3_Enum;
47164 
47165 /* ============================================  AUDADC SL3CFG PRMODE3 [16..17]  ============================================= */
47166 typedef enum {                                  /*!< AUDADC_SL3CFG_PRMODE3                                                     */
47167   AUDADC_SL3CFG_PRMODE3_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47168   AUDADC_SL3CFG_PRMODE3_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47169   AUDADC_SL3CFG_PRMODE3_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47170   AUDADC_SL3CFG_PRMODE3_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47171 } AUDADC_SL3CFG_PRMODE3_Enum;
47172 
47173 /* =============================================  AUDADC SL3CFG CHSEL3 [8..11]  ============================================== */
47174 typedef enum {                                  /*!< AUDADC_SL3CFG_CHSEL3                                                      */
47175   AUDADC_SL3CFG_CHSEL3_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47176   AUDADC_SL3CFG_CHSEL3_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47177   AUDADC_SL3CFG_CHSEL3_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47178   AUDADC_SL3CFG_CHSEL3_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47179 } AUDADC_SL3CFG_CHSEL3_Enum;
47180 
47181 /* ==============================================  AUDADC SL3CFG WCEN3 [1..1]  =============================================== */
47182 typedef enum {                                  /*!< AUDADC_SL3CFG_WCEN3                                                       */
47183   AUDADC_SL3CFG_WCEN3_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 3.                              */
47184   AUDADC_SL3CFG_WCEN3_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 3.                            */
47185 } AUDADC_SL3CFG_WCEN3_Enum;
47186 
47187 /* ==============================================  AUDADC SL3CFG SLEN3 [0..0]  =============================================== */
47188 typedef enum {                                  /*!< AUDADC_SL3CFG_SLEN3                                                       */
47189   AUDADC_SL3CFG_SLEN3_SLEN             = 1,     /*!< SLEN : Enable slot 3 for AUDADC conversions.                              */
47190   AUDADC_SL3CFG_SLEN3_SLDIS            = 0,     /*!< SLDIS : Disable slot 3 for AUDADC conversions.                            */
47191 } AUDADC_SL3CFG_SLEN3_Enum;
47192 
47193 /* ========================================================  SL4CFG  ========================================================= */
47194 /* =============================================  AUDADC SL4CFG ADSEL4 [24..26]  ============================================= */
47195 typedef enum {                                  /*!< AUDADC_SL4CFG_ADSEL4                                                      */
47196   AUDADC_SL4CFG_ADSEL4_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47197                                                      module for this slot.                                                     */
47198   AUDADC_SL4CFG_ADSEL4_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47199                                                      module for this slot.                                                     */
47200   AUDADC_SL4CFG_ADSEL4_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47201                                                      module for this slot.                                                     */
47202   AUDADC_SL4CFG_ADSEL4_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47203                                                      module for this slot.                                                     */
47204   AUDADC_SL4CFG_ADSEL4_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47205                                                      divide module for this slot.                                              */
47206   AUDADC_SL4CFG_ADSEL4_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47207                                                      divide module for this slot.                                              */
47208   AUDADC_SL4CFG_ADSEL4_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47209                                                      divide module for this slot.                                              */
47210   AUDADC_SL4CFG_ADSEL4_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47211                                                      divide module for this slot.                                              */
47212 } AUDADC_SL4CFG_ADSEL4_Enum;
47213 
47214 /* ============================================  AUDADC SL4CFG PRMODE4 [16..17]  ============================================= */
47215 typedef enum {                                  /*!< AUDADC_SL4CFG_PRMODE4                                                     */
47216   AUDADC_SL4CFG_PRMODE4_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47217   AUDADC_SL4CFG_PRMODE4_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47218   AUDADC_SL4CFG_PRMODE4_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47219   AUDADC_SL4CFG_PRMODE4_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47220 } AUDADC_SL4CFG_PRMODE4_Enum;
47221 
47222 /* =============================================  AUDADC SL4CFG CHSEL4 [8..11]  ============================================== */
47223 typedef enum {                                  /*!< AUDADC_SL4CFG_CHSEL4                                                      */
47224   AUDADC_SL4CFG_CHSEL4_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47225   AUDADC_SL4CFG_CHSEL4_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47226   AUDADC_SL4CFG_CHSEL4_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47227   AUDADC_SL4CFG_CHSEL4_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47228 } AUDADC_SL4CFG_CHSEL4_Enum;
47229 
47230 /* ==============================================  AUDADC SL4CFG WCEN4 [1..1]  =============================================== */
47231 typedef enum {                                  /*!< AUDADC_SL4CFG_WCEN4                                                       */
47232   AUDADC_SL4CFG_WCEN4_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 4.                              */
47233   AUDADC_SL4CFG_WCEN4_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 4.                            */
47234 } AUDADC_SL4CFG_WCEN4_Enum;
47235 
47236 /* ==============================================  AUDADC SL4CFG SLEN4 [0..0]  =============================================== */
47237 typedef enum {                                  /*!< AUDADC_SL4CFG_SLEN4                                                       */
47238   AUDADC_SL4CFG_SLEN4_SLEN             = 1,     /*!< SLEN : Enable slot 4 for AUDADC conversions.                              */
47239   AUDADC_SL4CFG_SLEN4_SLDIS            = 0,     /*!< SLDIS : Disable slot 4 for AUDADC conversions.                            */
47240 } AUDADC_SL4CFG_SLEN4_Enum;
47241 
47242 /* ========================================================  SL5CFG  ========================================================= */
47243 /* =============================================  AUDADC SL5CFG ADSEL5 [24..26]  ============================================= */
47244 typedef enum {                                  /*!< AUDADC_SL5CFG_ADSEL5                                                      */
47245   AUDADC_SL5CFG_ADSEL5_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47246                                                      module for this slot.                                                     */
47247   AUDADC_SL5CFG_ADSEL5_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47248                                                      module for this slot.                                                     */
47249   AUDADC_SL5CFG_ADSEL5_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47250                                                      module for this slot.                                                     */
47251   AUDADC_SL5CFG_ADSEL5_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47252                                                      module for this slot.                                                     */
47253   AUDADC_SL5CFG_ADSEL5_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47254                                                      divide module for this slot.                                              */
47255   AUDADC_SL5CFG_ADSEL5_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47256                                                      divide module for this slot.                                              */
47257   AUDADC_SL5CFG_ADSEL5_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47258                                                      divide module for this slot.                                              */
47259   AUDADC_SL5CFG_ADSEL5_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47260                                                      divide module for this slot.                                              */
47261 } AUDADC_SL5CFG_ADSEL5_Enum;
47262 
47263 /* ============================================  AUDADC SL5CFG PRMODE5 [16..17]  ============================================= */
47264 typedef enum {                                  /*!< AUDADC_SL5CFG_PRMODE5                                                     */
47265   AUDADC_SL5CFG_PRMODE5_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47266   AUDADC_SL5CFG_PRMODE5_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47267   AUDADC_SL5CFG_PRMODE5_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47268   AUDADC_SL5CFG_PRMODE5_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47269 } AUDADC_SL5CFG_PRMODE5_Enum;
47270 
47271 /* =============================================  AUDADC SL5CFG CHSEL5 [8..11]  ============================================== */
47272 typedef enum {                                  /*!< AUDADC_SL5CFG_CHSEL5                                                      */
47273   AUDADC_SL5CFG_CHSEL5_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47274   AUDADC_SL5CFG_CHSEL5_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47275   AUDADC_SL5CFG_CHSEL5_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47276   AUDADC_SL5CFG_CHSEL5_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47277 } AUDADC_SL5CFG_CHSEL5_Enum;
47278 
47279 /* ==============================================  AUDADC SL5CFG WCEN5 [1..1]  =============================================== */
47280 typedef enum {                                  /*!< AUDADC_SL5CFG_WCEN5                                                       */
47281   AUDADC_SL5CFG_WCEN5_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 5.                              */
47282   AUDADC_SL5CFG_WCEN5_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 5.                            */
47283 } AUDADC_SL5CFG_WCEN5_Enum;
47284 
47285 /* ==============================================  AUDADC SL5CFG SLEN5 [0..0]  =============================================== */
47286 typedef enum {                                  /*!< AUDADC_SL5CFG_SLEN5                                                       */
47287   AUDADC_SL5CFG_SLEN5_SLEN             = 1,     /*!< SLEN : Enable slot 5 for AUDADC conversions.                              */
47288   AUDADC_SL5CFG_SLEN5_SLDIS            = 0,     /*!< SLDIS : Disable slot 5 for AUDADC conversions.                            */
47289 } AUDADC_SL5CFG_SLEN5_Enum;
47290 
47291 /* ========================================================  SL6CFG  ========================================================= */
47292 /* =============================================  AUDADC SL6CFG ADSEL6 [24..26]  ============================================= */
47293 typedef enum {                                  /*!< AUDADC_SL6CFG_ADSEL6                                                      */
47294   AUDADC_SL6CFG_ADSEL6_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47295                                                      module for this slot.                                                     */
47296   AUDADC_SL6CFG_ADSEL6_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47297                                                      module for this slot.                                                     */
47298   AUDADC_SL6CFG_ADSEL6_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47299                                                      module for this slot.                                                     */
47300   AUDADC_SL6CFG_ADSEL6_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47301                                                      module for this slot.                                                     */
47302   AUDADC_SL6CFG_ADSEL6_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47303                                                      divide module for this slot.                                              */
47304   AUDADC_SL6CFG_ADSEL6_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47305                                                      divide module for this slot.                                              */
47306   AUDADC_SL6CFG_ADSEL6_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47307                                                      divide module for this slot.                                              */
47308   AUDADC_SL6CFG_ADSEL6_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47309                                                      divide module for this slot.                                              */
47310 } AUDADC_SL6CFG_ADSEL6_Enum;
47311 
47312 /* ============================================  AUDADC SL6CFG PRMODE6 [16..17]  ============================================= */
47313 typedef enum {                                  /*!< AUDADC_SL6CFG_PRMODE6                                                     */
47314   AUDADC_SL6CFG_PRMODE6_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47315   AUDADC_SL6CFG_PRMODE6_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47316   AUDADC_SL6CFG_PRMODE6_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47317   AUDADC_SL6CFG_PRMODE6_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47318 } AUDADC_SL6CFG_PRMODE6_Enum;
47319 
47320 /* =============================================  AUDADC SL6CFG CHSEL6 [8..11]  ============================================== */
47321 typedef enum {                                  /*!< AUDADC_SL6CFG_CHSEL6                                                      */
47322   AUDADC_SL6CFG_CHSEL6_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47323   AUDADC_SL6CFG_CHSEL6_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47324   AUDADC_SL6CFG_CHSEL6_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47325   AUDADC_SL6CFG_CHSEL6_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47326 } AUDADC_SL6CFG_CHSEL6_Enum;
47327 
47328 /* ==============================================  AUDADC SL6CFG WCEN6 [1..1]  =============================================== */
47329 typedef enum {                                  /*!< AUDADC_SL6CFG_WCEN6                                                       */
47330   AUDADC_SL6CFG_WCEN6_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 6.                              */
47331   AUDADC_SL6CFG_WCEN6_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 6.                            */
47332 } AUDADC_SL6CFG_WCEN6_Enum;
47333 
47334 /* ==============================================  AUDADC SL6CFG SLEN6 [0..0]  =============================================== */
47335 typedef enum {                                  /*!< AUDADC_SL6CFG_SLEN6                                                       */
47336   AUDADC_SL6CFG_SLEN6_SLEN             = 1,     /*!< SLEN : Enable slot 6 for AUDADC conversions.                              */
47337   AUDADC_SL6CFG_SLEN6_SLDIS            = 0,     /*!< SLDIS : Disable slot 6 for AUDADC conversions.                            */
47338 } AUDADC_SL6CFG_SLEN6_Enum;
47339 
47340 /* ========================================================  SL7CFG  ========================================================= */
47341 /* =============================================  AUDADC SL7CFG ADSEL7 [24..26]  ============================================= */
47342 typedef enum {                                  /*!< AUDADC_SL7CFG_ADSEL7                                                      */
47343   AUDADC_SL7CFG_ADSEL7_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47344                                                      module for this slot.                                                     */
47345   AUDADC_SL7CFG_ADSEL7_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47346                                                      module for this slot.                                                     */
47347   AUDADC_SL7CFG_ADSEL7_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47348                                                      module for this slot.                                                     */
47349   AUDADC_SL7CFG_ADSEL7_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47350                                                      module for this slot.                                                     */
47351   AUDADC_SL7CFG_ADSEL7_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47352                                                      divide module for this slot.                                              */
47353   AUDADC_SL7CFG_ADSEL7_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47354                                                      divide module for this slot.                                              */
47355   AUDADC_SL7CFG_ADSEL7_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47356                                                      divide module for this slot.                                              */
47357   AUDADC_SL7CFG_ADSEL7_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47358                                                      divide module for this slot.                                              */
47359 } AUDADC_SL7CFG_ADSEL7_Enum;
47360 
47361 /* ============================================  AUDADC SL7CFG PRMODE7 [16..17]  ============================================= */
47362 typedef enum {                                  /*!< AUDADC_SL7CFG_PRMODE7                                                     */
47363   AUDADC_SL7CFG_PRMODE7_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47364   AUDADC_SL7CFG_PRMODE7_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47365   AUDADC_SL7CFG_PRMODE7_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47366   AUDADC_SL7CFG_PRMODE7_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47367 } AUDADC_SL7CFG_PRMODE7_Enum;
47368 
47369 /* =============================================  AUDADC SL7CFG CHSEL7 [8..11]  ============================================== */
47370 typedef enum {                                  /*!< AUDADC_SL7CFG_CHSEL7                                                      */
47371   AUDADC_SL7CFG_CHSEL7_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47372   AUDADC_SL7CFG_CHSEL7_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47373   AUDADC_SL7CFG_CHSEL7_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47374   AUDADC_SL7CFG_CHSEL7_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47375 } AUDADC_SL7CFG_CHSEL7_Enum;
47376 
47377 /* ==============================================  AUDADC SL7CFG WCEN7 [1..1]  =============================================== */
47378 typedef enum {                                  /*!< AUDADC_SL7CFG_WCEN7                                                       */
47379   AUDADC_SL7CFG_WCEN7_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 7.                              */
47380   AUDADC_SL7CFG_WCEN7_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 7.                            */
47381 } AUDADC_SL7CFG_WCEN7_Enum;
47382 
47383 /* ==============================================  AUDADC SL7CFG SLEN7 [0..0]  =============================================== */
47384 typedef enum {                                  /*!< AUDADC_SL7CFG_SLEN7                                                       */
47385   AUDADC_SL7CFG_SLEN7_SLEN             = 1,     /*!< SLEN : Enable slot 7 for AUDADC conversions.                              */
47386   AUDADC_SL7CFG_SLEN7_SLDIS            = 0,     /*!< SLDIS : Disable slot 7 for AUDADC conversions.                            */
47387 } AUDADC_SL7CFG_SLEN7_Enum;
47388 
47389 /* =========================================================  WULIM  ========================================================= */
47390 /* =========================================================  WLLIM  ========================================================= */
47391 /* ========================================================  SCWLIM  ========================================================= */
47392 /* =========================================================  FIFO  ========================================================== */
47393 /* ========================================================  FIFOPR  ========================================================= */
47394 /* =====================================================  INTTRIGTIMER  ====================================================== */
47395 /* =========================================  AUDADC INTTRIGTIMER TIMEREN [31..31]  ========================================== */
47396 typedef enum {                                  /*!< AUDADC_INTTRIGTIMER_TIMEREN                                               */
47397   AUDADC_INTTRIGTIMER_TIMEREN_DIS      = 0,     /*!< DIS : Disable the AUDADC-internal trigger timer.                          */
47398   AUDADC_INTTRIGTIMER_TIMEREN_EN       = 1,     /*!< EN : Enable the AUDADC-internal trigger timer.                            */
47399 } AUDADC_INTTRIGTIMER_TIMEREN_Enum;
47400 
47401 /* =======================================================  FIFOSTAT  ======================================================== */
47402 /* ======================================================  DATAOFFSET  ======================================================= */
47403 /* =========================================================  ZXCFG  ========================================================= */
47404 /* =========================================================  ZXLIM  ========================================================= */
47405 /* ========================================================  GAINCFG  ======================================================== */
47406 /* ===========================================  AUDADC GAINCFG UPDATEMODE [4..4]  ============================================ */
47407 typedef enum {                                  /*!< AUDADC_GAINCFG_UPDATEMODE                                                 */
47408   AUDADC_GAINCFG_UPDATEMODE_IMMED      = 0,     /*!< IMMED : Immediate update mode. Once gain is written, it is immediately
47409                                                      encoded and provided to the PGA.                                          */
47410   AUDADC_GAINCFG_UPDATEMODE_ZX         = 1,     /*!< ZX : Update gain only at detected zero crossing as configured
47411                                                      by ZX registers.                                                          */
47412 } AUDADC_GAINCFG_UPDATEMODE_Enum;
47413 
47414 /* =========================================================  GAIN  ========================================================== */
47415 /* ========================================================  SATCFG  ========================================================= */
47416 /* ========================================================  SATLIM  ========================================================= */
47417 /* ========================================================  SATMAX  ========================================================= */
47418 /* ========================================================  SATCLR  ========================================================= */
47419 /* =========================================================  INTEN  ========================================================= */
47420 /* ==============================================  AUDADC INTEN SATCB [11..11]  ============================================== */
47421 typedef enum {                                  /*!< AUDADC_INTEN_SATCB                                                        */
47422   AUDADC_INTEN_SATCB_SATCBINT          = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47423                                                      occurred on either slot 2 or 3 (channel B)                                */
47424 } AUDADC_INTEN_SATCB_Enum;
47425 
47426 /* ==============================================  AUDADC INTEN SATCA [10..10]  ============================================== */
47427 typedef enum {                                  /*!< AUDADC_INTEN_SATCA                                                        */
47428   AUDADC_INTEN_SATCA_SATCAINT          = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47429                                                      occurred on either slot 0 or 1 (channel A)                                */
47430 } AUDADC_INTEN_SATCA_Enum;
47431 
47432 /* ===============================================  AUDADC INTEN ZXCB [9..9]  ================================================ */
47433 typedef enum {                                  /*!< AUDADC_INTEN_ZXCB                                                         */
47434   AUDADC_INTEN_ZXCB_ZXCBINT            = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47435                                                      occurred on either slot 2 or 3 (channel B)                                */
47436 } AUDADC_INTEN_ZXCB_Enum;
47437 
47438 /* ===============================================  AUDADC INTEN ZXCA [8..8]  ================================================ */
47439 typedef enum {                                  /*!< AUDADC_INTEN_ZXCA                                                         */
47440   AUDADC_INTEN_ZXCA_ZXCAINT            = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47441                                                      occurred on either slot 0 or 1 (channel A)                                */
47442 } AUDADC_INTEN_ZXCA_Enum;
47443 
47444 /* ===============================================  AUDADC INTEN DERR [7..7]  ================================================ */
47445 typedef enum {                                  /*!< AUDADC_INTEN_DERR                                                         */
47446   AUDADC_INTEN_DERR_DMAERROR           = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47447 } AUDADC_INTEN_DERR_Enum;
47448 
47449 /* ===============================================  AUDADC INTEN DCMP [6..6]  ================================================ */
47450 typedef enum {                                  /*!< AUDADC_INTEN_DCMP                                                         */
47451   AUDADC_INTEN_DCMP_DMACOMPLETE        = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47452 } AUDADC_INTEN_DCMP_Enum;
47453 
47454 /* ===============================================  AUDADC INTEN WCINC [5..5]  =============================================== */
47455 typedef enum {                                  /*!< AUDADC_INTEN_WCINC                                                        */
47456   AUDADC_INTEN_WCINC_WCINCINT          = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47457 } AUDADC_INTEN_WCINC_Enum;
47458 
47459 /* ===============================================  AUDADC INTEN WCEXC [4..4]  =============================================== */
47460 typedef enum {                                  /*!< AUDADC_INTEN_WCEXC                                                        */
47461   AUDADC_INTEN_WCEXC_WCEXCINT          = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47462 } AUDADC_INTEN_WCEXC_Enum;
47463 
47464 /* =============================================  AUDADC INTEN FIFOOVR2 [3..3]  ============================================== */
47465 typedef enum {                                  /*!< AUDADC_INTEN_FIFOOVR2                                                     */
47466   AUDADC_INTEN_FIFOOVR2_FIFOFULLINT    = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47467 } AUDADC_INTEN_FIFOOVR2_Enum;
47468 
47469 /* =============================================  AUDADC INTEN FIFOOVR1 [2..2]  ============================================== */
47470 typedef enum {                                  /*!< AUDADC_INTEN_FIFOOVR1                                                     */
47471   AUDADC_INTEN_FIFOOVR1_FIFO75INT      = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47472 } AUDADC_INTEN_FIFOOVR1_Enum;
47473 
47474 /* ==============================================  AUDADC INTEN SCNCMP [1..1]  =============================================== */
47475 typedef enum {                                  /*!< AUDADC_INTEN_SCNCMP                                                       */
47476   AUDADC_INTEN_SCNCMP_SCNCMPINT        = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
47477 } AUDADC_INTEN_SCNCMP_Enum;
47478 
47479 /* ==============================================  AUDADC INTEN CNVCMP [0..0]  =============================================== */
47480 typedef enum {                                  /*!< AUDADC_INTEN_CNVCMP                                                       */
47481   AUDADC_INTEN_CNVCMP_CNVCMPINT        = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
47482 } AUDADC_INTEN_CNVCMP_Enum;
47483 
47484 /* ========================================================  INTSTAT  ======================================================== */
47485 /* =============================================  AUDADC INTSTAT SATCB [11..11]  ============================================= */
47486 typedef enum {                                  /*!< AUDADC_INTSTAT_SATCB                                                      */
47487   AUDADC_INTSTAT_SATCB_SATCBINT        = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47488                                                      occurred on either slot 2 or 3 (channel B)                                */
47489 } AUDADC_INTSTAT_SATCB_Enum;
47490 
47491 /* =============================================  AUDADC INTSTAT SATCA [10..10]  ============================================= */
47492 typedef enum {                                  /*!< AUDADC_INTSTAT_SATCA                                                      */
47493   AUDADC_INTSTAT_SATCA_SATCAINT        = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47494                                                      occurred on either slot 0 or 1 (channel A)                                */
47495 } AUDADC_INTSTAT_SATCA_Enum;
47496 
47497 /* ==============================================  AUDADC INTSTAT ZXCB [9..9]  =============================================== */
47498 typedef enum {                                  /*!< AUDADC_INTSTAT_ZXCB                                                       */
47499   AUDADC_INTSTAT_ZXCB_ZXCBINT          = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47500                                                      occurred on either slot 2 or 3 (channel B)                                */
47501 } AUDADC_INTSTAT_ZXCB_Enum;
47502 
47503 /* ==============================================  AUDADC INTSTAT ZXCA [8..8]  =============================================== */
47504 typedef enum {                                  /*!< AUDADC_INTSTAT_ZXCA                                                       */
47505   AUDADC_INTSTAT_ZXCA_ZXCAINT          = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47506                                                      occurred on either slot 0 or 1 (channel A)                                */
47507 } AUDADC_INTSTAT_ZXCA_Enum;
47508 
47509 /* ==============================================  AUDADC INTSTAT DERR [7..7]  =============================================== */
47510 typedef enum {                                  /*!< AUDADC_INTSTAT_DERR                                                       */
47511   AUDADC_INTSTAT_DERR_DMAERROR         = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47512 } AUDADC_INTSTAT_DERR_Enum;
47513 
47514 /* ==============================================  AUDADC INTSTAT DCMP [6..6]  =============================================== */
47515 typedef enum {                                  /*!< AUDADC_INTSTAT_DCMP                                                       */
47516   AUDADC_INTSTAT_DCMP_DMACOMPLETE      = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47517 } AUDADC_INTSTAT_DCMP_Enum;
47518 
47519 /* ==============================================  AUDADC INTSTAT WCINC [5..5]  ============================================== */
47520 typedef enum {                                  /*!< AUDADC_INTSTAT_WCINC                                                      */
47521   AUDADC_INTSTAT_WCINC_WCINCINT        = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47522 } AUDADC_INTSTAT_WCINC_Enum;
47523 
47524 /* ==============================================  AUDADC INTSTAT WCEXC [4..4]  ============================================== */
47525 typedef enum {                                  /*!< AUDADC_INTSTAT_WCEXC                                                      */
47526   AUDADC_INTSTAT_WCEXC_WCEXCINT        = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47527 } AUDADC_INTSTAT_WCEXC_Enum;
47528 
47529 /* ============================================  AUDADC INTSTAT FIFOOVR2 [3..3]  ============================================= */
47530 typedef enum {                                  /*!< AUDADC_INTSTAT_FIFOOVR2                                                   */
47531   AUDADC_INTSTAT_FIFOOVR2_FIFOFULLINT  = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47532 } AUDADC_INTSTAT_FIFOOVR2_Enum;
47533 
47534 /* ============================================  AUDADC INTSTAT FIFOOVR1 [2..2]  ============================================= */
47535 typedef enum {                                  /*!< AUDADC_INTSTAT_FIFOOVR1                                                   */
47536   AUDADC_INTSTAT_FIFOOVR1_FIFO75INT    = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47537 } AUDADC_INTSTAT_FIFOOVR1_Enum;
47538 
47539 /* =============================================  AUDADC INTSTAT SCNCMP [1..1]  ============================================== */
47540 typedef enum {                                  /*!< AUDADC_INTSTAT_SCNCMP                                                     */
47541   AUDADC_INTSTAT_SCNCMP_SCNCMPINT      = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
47542 } AUDADC_INTSTAT_SCNCMP_Enum;
47543 
47544 /* =============================================  AUDADC INTSTAT CNVCMP [0..0]  ============================================== */
47545 typedef enum {                                  /*!< AUDADC_INTSTAT_CNVCMP                                                     */
47546   AUDADC_INTSTAT_CNVCMP_CNVCMPINT      = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
47547 } AUDADC_INTSTAT_CNVCMP_Enum;
47548 
47549 /* ========================================================  INTCLR  ========================================================= */
47550 /* =============================================  AUDADC INTCLR SATCB [11..11]  ============================================== */
47551 typedef enum {                                  /*!< AUDADC_INTCLR_SATCB                                                       */
47552   AUDADC_INTCLR_SATCB_SATCBINT         = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47553                                                      occurred on either slot 2 or 3 (channel B)                                */
47554 } AUDADC_INTCLR_SATCB_Enum;
47555 
47556 /* =============================================  AUDADC INTCLR SATCA [10..10]  ============================================== */
47557 typedef enum {                                  /*!< AUDADC_INTCLR_SATCA                                                       */
47558   AUDADC_INTCLR_SATCA_SATCAINT         = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47559                                                      occurred on either slot 0 or 1 (channel A)                                */
47560 } AUDADC_INTCLR_SATCA_Enum;
47561 
47562 /* ===============================================  AUDADC INTCLR ZXCB [9..9]  =============================================== */
47563 typedef enum {                                  /*!< AUDADC_INTCLR_ZXCB                                                        */
47564   AUDADC_INTCLR_ZXCB_ZXCBINT           = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47565                                                      occurred on either slot 2 or 3 (channel B)                                */
47566 } AUDADC_INTCLR_ZXCB_Enum;
47567 
47568 /* ===============================================  AUDADC INTCLR ZXCA [8..8]  =============================================== */
47569 typedef enum {                                  /*!< AUDADC_INTCLR_ZXCA                                                        */
47570   AUDADC_INTCLR_ZXCA_ZXCAINT           = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47571                                                      occurred on either slot 0 or 1 (channel A)                                */
47572 } AUDADC_INTCLR_ZXCA_Enum;
47573 
47574 /* ===============================================  AUDADC INTCLR DERR [7..7]  =============================================== */
47575 typedef enum {                                  /*!< AUDADC_INTCLR_DERR                                                        */
47576   AUDADC_INTCLR_DERR_DMAERROR          = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47577 } AUDADC_INTCLR_DERR_Enum;
47578 
47579 /* ===============================================  AUDADC INTCLR DCMP [6..6]  =============================================== */
47580 typedef enum {                                  /*!< AUDADC_INTCLR_DCMP                                                        */
47581   AUDADC_INTCLR_DCMP_DMACOMPLETE       = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47582 } AUDADC_INTCLR_DCMP_Enum;
47583 
47584 /* ==============================================  AUDADC INTCLR WCINC [5..5]  =============================================== */
47585 typedef enum {                                  /*!< AUDADC_INTCLR_WCINC                                                       */
47586   AUDADC_INTCLR_WCINC_WCINCINT         = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47587 } AUDADC_INTCLR_WCINC_Enum;
47588 
47589 /* ==============================================  AUDADC INTCLR WCEXC [4..4]  =============================================== */
47590 typedef enum {                                  /*!< AUDADC_INTCLR_WCEXC                                                       */
47591   AUDADC_INTCLR_WCEXC_WCEXCINT         = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47592 } AUDADC_INTCLR_WCEXC_Enum;
47593 
47594 /* =============================================  AUDADC INTCLR FIFOOVR2 [3..3]  ============================================= */
47595 typedef enum {                                  /*!< AUDADC_INTCLR_FIFOOVR2                                                    */
47596   AUDADC_INTCLR_FIFOOVR2_FIFOFULLINT   = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47597 } AUDADC_INTCLR_FIFOOVR2_Enum;
47598 
47599 /* =============================================  AUDADC INTCLR FIFOOVR1 [2..2]  ============================================= */
47600 typedef enum {                                  /*!< AUDADC_INTCLR_FIFOOVR1                                                    */
47601   AUDADC_INTCLR_FIFOOVR1_FIFO75INT     = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47602 } AUDADC_INTCLR_FIFOOVR1_Enum;
47603 
47604 /* ==============================================  AUDADC INTCLR SCNCMP [1..1]  ============================================== */
47605 typedef enum {                                  /*!< AUDADC_INTCLR_SCNCMP                                                      */
47606   AUDADC_INTCLR_SCNCMP_SCNCMPINT       = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
47607 } AUDADC_INTCLR_SCNCMP_Enum;
47608 
47609 /* ==============================================  AUDADC INTCLR CNVCMP [0..0]  ============================================== */
47610 typedef enum {                                  /*!< AUDADC_INTCLR_CNVCMP                                                      */
47611   AUDADC_INTCLR_CNVCMP_CNVCMPINT       = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
47612 } AUDADC_INTCLR_CNVCMP_Enum;
47613 
47614 /* ========================================================  INTSET  ========================================================= */
47615 /* =============================================  AUDADC INTSET SATCB [11..11]  ============================================== */
47616 typedef enum {                                  /*!< AUDADC_INTSET_SATCB                                                       */
47617   AUDADC_INTSET_SATCB_SATCBINT         = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47618                                                      occurred on either slot 2 or 3 (channel B)                                */
47619 } AUDADC_INTSET_SATCB_Enum;
47620 
47621 /* =============================================  AUDADC INTSET SATCA [10..10]  ============================================== */
47622 typedef enum {                                  /*!< AUDADC_INTSET_SATCA                                                       */
47623   AUDADC_INTSET_SATCA_SATCAINT         = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47624                                                      occurred on either slot 0 or 1 (channel A)                                */
47625 } AUDADC_INTSET_SATCA_Enum;
47626 
47627 /* ===============================================  AUDADC INTSET ZXCB [9..9]  =============================================== */
47628 typedef enum {                                  /*!< AUDADC_INTSET_ZXCB                                                        */
47629   AUDADC_INTSET_ZXCB_ZXCBINT           = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47630                                                      occurred on either slot 2 or 3 (channel B)                                */
47631 } AUDADC_INTSET_ZXCB_Enum;
47632 
47633 /* ===============================================  AUDADC INTSET ZXCA [8..8]  =============================================== */
47634 typedef enum {                                  /*!< AUDADC_INTSET_ZXCA                                                        */
47635   AUDADC_INTSET_ZXCA_ZXCAINT           = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47636                                                      occurred on either slot 0 or 1 (channel A)                                */
47637 } AUDADC_INTSET_ZXCA_Enum;
47638 
47639 /* ===============================================  AUDADC INTSET DERR [7..7]  =============================================== */
47640 typedef enum {                                  /*!< AUDADC_INTSET_DERR                                                        */
47641   AUDADC_INTSET_DERR_DMAERROR          = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47642 } AUDADC_INTSET_DERR_Enum;
47643 
47644 /* ===============================================  AUDADC INTSET DCMP [6..6]  =============================================== */
47645 typedef enum {                                  /*!< AUDADC_INTSET_DCMP                                                        */
47646   AUDADC_INTSET_DCMP_DMACOMPLETE       = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47647 } AUDADC_INTSET_DCMP_Enum;
47648 
47649 /* ==============================================  AUDADC INTSET WCINC [5..5]  =============================================== */
47650 typedef enum {                                  /*!< AUDADC_INTSET_WCINC                                                       */
47651   AUDADC_INTSET_WCINC_WCINCINT         = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47652 } AUDADC_INTSET_WCINC_Enum;
47653 
47654 /* ==============================================  AUDADC INTSET WCEXC [4..4]  =============================================== */
47655 typedef enum {                                  /*!< AUDADC_INTSET_WCEXC                                                       */
47656   AUDADC_INTSET_WCEXC_WCEXCINT         = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47657 } AUDADC_INTSET_WCEXC_Enum;
47658 
47659 /* =============================================  AUDADC INTSET FIFOOVR2 [3..3]  ============================================= */
47660 typedef enum {                                  /*!< AUDADC_INTSET_FIFOOVR2                                                    */
47661   AUDADC_INTSET_FIFOOVR2_FIFOFULLINT   = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47662 } AUDADC_INTSET_FIFOOVR2_Enum;
47663 
47664 /* =============================================  AUDADC INTSET FIFOOVR1 [2..2]  ============================================= */
47665 typedef enum {                                  /*!< AUDADC_INTSET_FIFOOVR1                                                    */
47666   AUDADC_INTSET_FIFOOVR1_FIFO75INT     = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47667 } AUDADC_INTSET_FIFOOVR1_Enum;
47668 
47669 /* ==============================================  AUDADC INTSET SCNCMP [1..1]  ============================================== */
47670 typedef enum {                                  /*!< AUDADC_INTSET_SCNCMP                                                      */
47671   AUDADC_INTSET_SCNCMP_SCNCMPINT       = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
47672 } AUDADC_INTSET_SCNCMP_Enum;
47673 
47674 /* ==============================================  AUDADC INTSET CNVCMP [0..0]  ============================================== */
47675 typedef enum {                                  /*!< AUDADC_INTSET_CNVCMP                                                      */
47676   AUDADC_INTSET_CNVCMP_CNVCMPINT       = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
47677 } AUDADC_INTSET_CNVCMP_Enum;
47678 
47679 /* =======================================================  DMATRIGEN  ======================================================= */
47680 /* ======================================================  DMATRIGSTAT  ====================================================== */
47681 /* ========================================================  DMACFG  ========================================================= */
47682 /* ============================================  AUDADC DMACFG DMADYNPRI [9..9]  ============================================= */
47683 typedef enum {                                  /*!< AUDADC_DMACFG_DMADYNPRI                                                   */
47684   AUDADC_DMACFG_DMADYNPRI_DIS          = 0,     /*!< DIS : Disable dynamic priority (use DMAPRI setting only)                  */
47685   AUDADC_DMACFG_DMADYNPRI_EN           = 1,     /*!< EN : Enable dynamic priority                                              */
47686 } AUDADC_DMACFG_DMADYNPRI_Enum;
47687 
47688 /* ==============================================  AUDADC DMACFG DMAPRI [8..8]  ============================================== */
47689 typedef enum {                                  /*!< AUDADC_DMACFG_DMAPRI                                                      */
47690   AUDADC_DMACFG_DMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
47691   AUDADC_DMACFG_DMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
47692 } AUDADC_DMACFG_DMAPRI_Enum;
47693 
47694 /* ==============================================  AUDADC DMACFG DMADIR [2..2]  ============================================== */
47695 typedef enum {                                  /*!< AUDADC_DMACFG_DMADIR                                                      */
47696   AUDADC_DMACFG_DMADIR_P2M             = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
47697   AUDADC_DMACFG_DMADIR_M2P             = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
47698 } AUDADC_DMACFG_DMADIR_Enum;
47699 
47700 /* ==============================================  AUDADC DMACFG DMAEN [0..0]  =============================================== */
47701 typedef enum {                                  /*!< AUDADC_DMACFG_DMAEN                                                       */
47702   AUDADC_DMACFG_DMAEN_DIS              = 0,     /*!< DIS : Disable DMA Function                                                */
47703   AUDADC_DMACFG_DMAEN_EN               = 1,     /*!< EN : Enable DMA Function                                                  */
47704 } AUDADC_DMACFG_DMAEN_Enum;
47705 
47706 /* ======================================================  DMATOTCOUNT  ====================================================== */
47707 /* ======================================================  DMATARGADDR  ====================================================== */
47708 /* ========================================================  DMASTAT  ======================================================== */
47709 
47710 
47711 /* =========================================================================================================================== */
47712 /* ================                                          CLKGEN                                           ================ */
47713 /* =========================================================================================================================== */
47714 
47715 /* =========================================================  OCTRL  ========================================================= */
47716 /* ===============================================  CLKGEN OCTRL OSEL [7..7]  ================================================ */
47717 typedef enum {                                  /*!< CLKGEN_OCTRL_OSEL                                                         */
47718   CLKGEN_OCTRL_OSEL_RTC_XT             = 0,     /*!< RTC_XT : RTC uses the XT                                                  */
47719   CLKGEN_OCTRL_OSEL_RTC_LFRC           = 1,     /*!< RTC_LFRC : RTC uses the LFRC                                              */
47720 } CLKGEN_OCTRL_OSEL_Enum;
47721 
47722 /* ========================================================  CLKOUT  ========================================================= */
47723 /* ===============================================  CLKGEN CLKOUT CKEN [7..7]  =============================================== */
47724 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKEN                                                        */
47725   CLKGEN_CLKOUT_CKEN_DIS               = 0,     /*!< DIS : Disable CLKOUT                                                      */
47726   CLKGEN_CLKOUT_CKEN_EN                = 1,     /*!< EN : Enable CLKOUT                                                        */
47727 } CLKGEN_CLKOUT_CKEN_Enum;
47728 
47729 /* ==============================================  CLKGEN CLKOUT CKSEL [0..5]  =============================================== */
47730 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKSEL                                                       */
47731   CLKGEN_CLKOUT_CKSEL_LFRC             = 0,     /*!< LFRC : LFRC clock source selection                                        */
47732   CLKGEN_CLKOUT_CKSEL_XT_DIV2          = 1,     /*!< XT_DIV2 : XT / 2 clock source selection                                   */
47733   CLKGEN_CLKOUT_CKSEL_XT_DIV4          = 2,     /*!< XT_DIV4 : XT / 4 clock source selection                                   */
47734   CLKGEN_CLKOUT_CKSEL_XT_DIV8          = 3,     /*!< XT_DIV8 : XT / 8 clock source selection                                   */
47735   CLKGEN_CLKOUT_CKSEL_XT_DIV16         = 4,     /*!< XT_DIV16 : XT / 16 clock source selection                                 */
47736   CLKGEN_CLKOUT_CKSEL_XT_DIV32         = 5,     /*!< XT_DIV32 : XT / 32 clock source selection                                 */
47737   CLKGEN_CLKOUT_CKSEL_RTC_1Hz          = 16,    /*!< RTC_1Hz : 1 Hz as selected in RTC                                         */
47738   CLKGEN_CLKOUT_CKSEL_XT_DIV2M         = 22,    /*!< XT_DIV2M : XT / 2097152 (2^21) clock source selection                     */
47739   CLKGEN_CLKOUT_CKSEL_XT               = 23,    /*!< XT : XT clock source selection                                            */
47740   CLKGEN_CLKOUT_CKSEL_CG_100Hz         = 24,    /*!< CG_100Hz : 100 Hz as selected in CLKGEN                                   */
47741   CLKGEN_CLKOUT_CKSEL_HFRC_DIV2        = 25,    /*!< HFRC_DIV2 : HFRC / 2 clock source selection                               */
47742   CLKGEN_CLKOUT_CKSEL_HFRC_DIV8        = 26,    /*!< HFRC_DIV8 : HFRC / 8 clock source selection                               */
47743   CLKGEN_CLKOUT_CKSEL_HFRC_DIV16       = 27,    /*!< HFRC_DIV16 : HFRC / 16 clock source selection                             */
47744   CLKGEN_CLKOUT_CKSEL_HFRC_DIV32       = 28,    /*!< HFRC_DIV32 : HFRC / 32 clock source selection                             */
47745   CLKGEN_CLKOUT_CKSEL_HFRC_DIV128      = 29,    /*!< HFRC_DIV128 : HFRC / 128 clock source selection                           */
47746   CLKGEN_CLKOUT_CKSEL_HFRC_DIV256      = 30,    /*!< HFRC_DIV256 : HFRC / 256 clock source selection                           */
47747   CLKGEN_CLKOUT_CKSEL_HFRC_DIV512      = 31,    /*!< HFRC_DIV512 : HFRC / 512 clock source selection                           */
47748   CLKGEN_CLKOUT_CKSEL_HFRC_DIV1024     = 32,    /*!< HFRC_DIV1024 : HFRC / 1024 clock source selection                         */
47749   CLKGEN_CLKOUT_CKSEL_FLASH_CLK        = 34,    /*!< FLASH_CLK : Flash Clock clock source selection                            */
47750   CLKGEN_CLKOUT_CKSEL_LFRC_DIV2        = 35,    /*!< LFRC_DIV2 : LFRC / 2 clock source selection                               */
47751   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32       = 36,    /*!< LFRC_DIV32 : LFRC / 32 clock source selection                             */
47752   CLKGEN_CLKOUT_CKSEL_LFRC_DIV512      = 37,    /*!< LFRC_DIV512 : LFRC / 512 clock source selection                           */
47753   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K      = 38,    /*!< LFRC_DIV32K : LFRC / 32768 clock source selection                         */
47754   CLKGEN_CLKOUT_CKSEL_XT_DIV256        = 39,    /*!< XT_DIV256 : XT / 256 clock source selection                               */
47755   CLKGEN_CLKOUT_CKSEL_XT_DIV8K         = 40,    /*!< XT_DIV8K : XT / 8192 clock source selection                               */
47756   CLKGEN_CLKOUT_CKSEL_XT_DIV64K        = 41,    /*!< XT_DIV64K : XT / 65536 (2^16) clock source selection                      */
47757   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16      = 42,    /*!< ULFRC_DIV16 : Uncal LFRC / 16 clock source selection                      */
47758   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128     = 43,    /*!< ULFRC_DIV128 : Uncal LFRC / 128 clock source selection                    */
47759   CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz        = 44,    /*!< ULFRC_1Hz : Uncal LFRC / 1024 clock source selection                      */
47760   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K      = 45,    /*!< ULFRC_DIV4K : Uncal LFRC / 4096 clock source selection                    */
47761   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M      = 46,    /*!< ULFRC_DIV1M : Uncal LFRC / 1048576 (2^20) clock source selection          */
47762   CLKGEN_CLKOUT_CKSEL_HFRC_DIV256K     = 47,    /*!< HFRC_DIV256K : HFRC / 262144 (2^18) clock source selection                */
47763   CLKGEN_CLKOUT_CKSEL_HFRC_DIV64M      = 48,    /*!< HFRC_DIV64M : HFRC / 67108864 (2^26) clock source selection               */
47764   CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M       = 49,    /*!< LFRC_DIV1M : LFRC / 1048576 (2^20) clock source selection                 */
47765   CLKGEN_CLKOUT_CKSEL_HFRCNE           = 50,    /*!< HFRCNE : HFRC (not autoenabled)                                           */
47766   CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8      = 51,    /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled)                                  */
47767   CLKGEN_CLKOUT_CKSEL_XTNE             = 53,    /*!< XTNE : XT (not autoenabled)                                               */
47768   CLKGEN_CLKOUT_CKSEL_XTNE_DIV16       = 54,    /*!< XTNE_DIV16 : XT / 16 (not autoenabled)                                    */
47769   CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32     = 55,    /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled)                                */
47770   CLKGEN_CLKOUT_CKSEL_LFRCNE           = 57,    /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values            */
47771   CLKGEN_CLKOUT_CKSEL_HFRC2_6MHz       = 58,    /*!< HFRC2_6MHz : HFRC2 6MHz clock source selection                            */
47772   CLKGEN_CLKOUT_CKSEL_HFRC2_12MHz      = 59,    /*!< HFRC2_12MHz : HFRC2 24MHz clock source selection                          */
47773   CLKGEN_CLKOUT_CKSEL_HFRC2_24MHz      = 60,    /*!< HFRC2_24MHz : HFRC2 24MHz clock source selection                          */
47774 } CLKGEN_CLKOUT_CKSEL_Enum;
47775 
47776 /* =========================================================  HFADJ  ========================================================= */
47777 /* ==========================================  CLKGEN HFADJ HFADJMAXDELTA [24..28]  ========================================== */
47778 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJMAXDELTA                                                */
47779   CLKGEN_HFADJ_HFADJMAXDELTA_DISABLED  = 0,     /*!< DISABLED : Maximum Delta function is disabled                             */
47780 } CLKGEN_HFADJ_HFADJMAXDELTA_Enum;
47781 
47782 /* ============================================  CLKGEN HFADJ HFADJGAIN [21..23]  ============================================ */
47783 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJGAIN                                                    */
47784   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1     = 0,     /*!< Gain_of_1 : HF Adjust with Gain of 1                                      */
47785   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1,    /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5                               */
47786   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2,    /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25                              */
47787   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3,    /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125                             */
47788   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4,   /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625                           */
47789   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5,   /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125                          */
47790 } CLKGEN_HFADJ_HFADJGAIN_Enum;
47791 
47792 /* ============================================  CLKGEN HFADJ HFWARMUP [20..20]  ============================================= */
47793 typedef enum {                                  /*!< CLKGEN_HFADJ_HFWARMUP                                                     */
47794   CLKGEN_HFADJ_HFWARMUP_1SEC           = 0,     /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds                          */
47795   CLKGEN_HFADJ_HFWARMUP_2SEC           = 1,     /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds                          */
47796 } CLKGEN_HFADJ_HFWARMUP_Enum;
47797 
47798 /* ==============================================  CLKGEN HFADJ HFADJCK [1..3]  ============================================== */
47799 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJCK                                                      */
47800   CLKGEN_HFADJ_HFADJCK_4SEC            = 0,     /*!< 4SEC : Autoadjust repeat period = 4 seconds                               */
47801   CLKGEN_HFADJ_HFADJCK_16SEC           = 1,     /*!< 16SEC : Autoadjust repeat period = 16 seconds                             */
47802   CLKGEN_HFADJ_HFADJCK_32SEC           = 2,     /*!< 32SEC : Autoadjust repeat period = 32 seconds                             */
47803   CLKGEN_HFADJ_HFADJCK_64SEC           = 3,     /*!< 64SEC : Autoadjust repeat period = 64 seconds                             */
47804   CLKGEN_HFADJ_HFADJCK_128SEC          = 4,     /*!< 128SEC : Autoadjust repeat period = 128 seconds                           */
47805   CLKGEN_HFADJ_HFADJCK_256SEC          = 5,     /*!< 256SEC : Autoadjust repeat period = 256 seconds                           */
47806   CLKGEN_HFADJ_HFADJCK_512SEC          = 6,     /*!< 512SEC : Autoadjust repeat period = 512 seconds                           */
47807   CLKGEN_HFADJ_HFADJCK_1024SEC         = 7,     /*!< 1024SEC : Autoadjust repeat period = 1024 seconds                         */
47808 } CLKGEN_HFADJ_HFADJCK_Enum;
47809 
47810 /* ==============================================  CLKGEN HFADJ HFADJEN [0..0]  ============================================== */
47811 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJEN                                                      */
47812   CLKGEN_HFADJ_HFADJEN_DIS             = 0,     /*!< DIS : Disable the HFRC adjustment                                         */
47813   CLKGEN_HFADJ_HFADJEN_EN              = 1,     /*!< EN : Enable the HFRC adjustment                                           */
47814 } CLKGEN_HFADJ_HFADJEN_Enum;
47815 
47816 /* ======================================================  CLOCKENSTAT  ====================================================== */
47817 /* ========================================  CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31]  ========================================= */
47818 typedef enum {                                  /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT                                            */
47819   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_XTAL_EN = 16777216,/*!< PERIPH_ALL_XTAL_EN : [24] Clock enable for PERIPH_ALL_XTAL_EN */
47820   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_HFRC_EN = 33554432,/*!< PERIPH_ALL_HFRC_EN : [25] Clock enable for PERIPH_ALL_HFRC_EN */
47821   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFADJEN = 67108864,/*!< HFADJEN : [26] HFRC Adjust enabled                                    */
47822   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFRC_EN_HFADJ = 134217728,/*!< HFRC_EN_HFADJ : [27] HFRC HFADJ enabled                        */
47823   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_nOSEL = 268435456,/*!< nOSEL : [28] ~OSEL                                                     */
47824   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_xtal_en = 536870912,/*!< clkout_xtal_en : [29] XTAL clkout enabled                     */
47825   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_hfrc_en = 1073741824,/*!< clkout_hfrc_en : [30] HFRC clkout enabled                    */
47826 } CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum;
47827 
47828 /* =====================================================  CLOCKEN2STAT  ====================================================== */
47829 /* =======================================  CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31]  ======================================== */
47830 typedef enum {                                  /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT                                          */
47831   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_ADC_CLKEN = 1,/*!< ADC_CLKEN : [0] Clock enable for the ADC.                                */
47832   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_ACTIVITY_CLKEN = 2,/*!< APBDMA_ACTIVITY_CLKEN : [1] Clock enable for the APBDMA ACTIVITY */
47833   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOH_CLKEN = 4,/*!< APBDMA_AOH_CLKEN : [2] Clock enable for the APBDMA AOH DOMAIN     */
47834   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOL_CLKEN = 8,/*!< APBDMA_AOL_CLKEN : [3] Clock enable for the APBDMA AOL DOMAIN     */
47835   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_APB_CLKEN = 16,/*!< APBDMA_APB_CLKEN : [4] Clock enable for the APBDMA_APB           */
47836   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AUD_CLKEN = 32,/*!< APBDMA_AUD_CLKEN : [5] Clock enable for the APBDMA_AUD           */
47837   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_CRYPTO_CLKEN = 64,/*!< APBDMA_CRYPTO_CLKEN : [6] Clock enable for the APBDMA_HCPA    */
47838   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DBG_CLKEN = 128,/*!< APBDMA_DBG_CLKEN : [7] Clock enable for the APBDMA_DBG          */
47839   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISP_CLKEN = 256,/*!< APBDMA_DISP_CLKEN : [8] Clock enable for the APBDMA_DISP       */
47840   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISPPHY_CLKEN = 512,/*!< APBDMA_DISPPHY_CLKEN : [9] Clock enable for the APBDMA_DISPPHY */
47841   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DSPA_CLKEN = 1024,/*!< APBDMA_DSPA_CLKEN : [10] Clock enable for the APBDMA_DSPA     */
47842   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_GFX_CLKEN = 2048,/*!< APBDMA_GFX_CLKEN : [11] Clock enable for the APBDMA_GFX        */
47843   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPA_CLKEN = 4096,/*!< APBDMA_HSPA_CLKEN : [12] Clock enable for the APBDMA_HSPA     */
47844   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPB_CLKEN = 8192,/*!< APBDMA_HSPB_CLKEN : [13] Clock enable for the APBDMA_HSPB     */
47845   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPC_CLKEN = 16384,/*!< APBDMA_HSPC_CLKEN : [14] Clock enable for the APBDMA_HSPC    */
47846   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_IOS_CLKEN = 32768,/*!< APBDMA_IOS_CLKEN : [15] Clock enable for the APBDMA_IOS       */
47847   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI0_CLKEN = 65536,/*!< APBDMA_MSPI0_CLKEN : [16] Clock enable for the APBDMA_MSPI0 */
47848   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI1_CLKEN = 131072,/*!< APBDMA_MSPI1_CLKEN : [17] Clock enable for the APBDMA_MSPI1 */
47849   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI2_CLKEN = 262144,/*!< APBDMA_MSPI2_CLKEN : [18] Clock enable for the APBDMA_MSPI2 */
47850   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_SDIO_CLKEN = 524288,/*!< APBDMA_SDIO_CLKEN : [19] Clock enable for the APBDMA_SDIO   */
47851   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_USB_CLKEN = 1048576,/*!< APBDMA_USB_CLKEN : [20] Clock enable for the APBDMA_USB     */
47852   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_AUDADC_CLKEN = 2097152,/*!< AUDADC_CLKEN : [21] Clock enable for the AUDADC                 */
47853   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_CM4_TPIU_CLKEN = 4194304,/*!< CM4_TPIU_CLKEN : [22] Clock enable for the CM4_TPIU           */
47854   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TPIU_CLKEN = 8388608,/*!< DBG_TPIU_CLKEN : [23] Clock enable for the DBG_TPIU           */
47855   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TS_CLKEN = 16777216,/*!< DBG_TS_CLKEN : [24] Clock enable for the DBG_TS                */
47856   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DISP_CLK_CLKEN = 33554432,/*!< DISP_CLK_CLKEN : [25] Clock enable for the DISP_CLK          */
47857   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DPHY_PLL_REF_CLKEN = 67108864,/*!< DPHY_PLL_REF_CLKEN : [26] Clock enable for the DPHY_PLL_REF */
47858   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_CLKEN = 134217728,/*!< DSP_I2S0_CLKEN : [27] Clock enable for the DSP_I2S0         */
47859   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_REFCLK_CLKEN = 268435456,/*!< DSP_I2S0_REFCLK_CLKEN : [28] Clock enable for the DSP_I2S0_REFCLK */
47860   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_CLKEN = 536870912,/*!< DSP_I2S1_CLKEN : [29] Clock enable for the DSP_I2S1         */
47861   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_REFCLK_CLKEN = 1073741824,/*!< DSP_I2S1_REFCLK_CLKEN : [30] Clock enable for the DSP_I2S1_REFCLK */
47862   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_MILLI_CLKEN = 0x80000000,/*!< DSP_MILLI_CLKEN : [31] Clock enable for the DSP_MILLI    */
47863 } CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum;
47864 
47865 /* =====================================================  CLOCKEN3STAT  ====================================================== */
47866 /* =======================================  CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31]  ======================================== */
47867 typedef enum {                                  /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT                                          */
47868   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM0_CLKEN = 1,/*!< DSP_PDM0_CLKEN : [0] Clock enable for the DSP_PDM0                  */
47869   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM1_CLKEN = 2,/*!< DSP_PDM1_CLKEN : [1] Clock enable for the DSP_PDM1                  */
47870   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM2_CLKEN = 4,/*!< DSP_PDM2_CLKEN : [2] Clock enable for the DSP_PDM2                  */
47871   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM3_CLKEN = 8,/*!< DSP_PDM3_CLKEN : [3] Clock enable for the DSP_PDM3                  */
47872   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_I3C0_REFCLK_CLKEN = 16,/*!< I3C0_REFCLK_CLKEN : [4] Clock enable for the I3C0_REFCLK        */
47873   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_I3C1_REFCLK_CLKEN = 32,/*!< I3C1_REFCLK_CLKEN : [5] Clock enable for the I3C1_REFCLK        */
47874   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC0_CLKEN = 64,/*!< IOMSTRIFC0_CLKEN : [6] Clock enable for the IOMSTRIFC0           */
47875   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC1_CLKEN = 128,/*!< IOMSTRIFC1_CLKEN : [7] Clock enable for the IO MASTER 1 IFC
47876                                                      INTERFACE                                                                 */
47877   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC2_CLKEN = 256,/*!< IOMSTRIFC2_CLKEN : [8] Clock enable for the IO MASTER 2 IFC
47878                                                      INTERFACE                                                                 */
47879   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC3_CLKEN = 512,/*!< IOMSTRIFC3_CLKEN : [9] Clock enable for the IO MASTER 3 IFC
47880                                                      INTERFACE                                                                 */
47881   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC4_CLKEN = 1024,/*!< IOMSTRIFC4_CLKEN : [10] Clock enable for the IO MASTER 4 IFC
47882                                                      INTERFACE                                                                 */
47883   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC5_CLKEN = 2048,/*!< IOMSTRIFC5_CLKEN : [11] Clock enable for the IO MASTER 5 IFC
47884                                                      INTERFACE                                                                 */
47885   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC6_CLKEN = 4096,/*!< IOMSTRIFC6_CLKEN : [12] Clock enable for the IO MASTER 6 IFC
47886                                                      INTERFACE                                                                 */
47887   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC7_CLKEN = 8192,/*!< IOMSTRIFC7_CLKEN : [13] Clock enable for the IO MASTER 7 IFC
47888                                                      INTERFACE                                                                 */
47889   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_CLKEN = 16384,/*!< RSTGEN_CLKEN : [14] Clock enable for the RSTGEN                   */
47890   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_POS_CLKEN = 32768,/*!< RSTGEN_POS_CLKEN : [15] Clock enable for the RSTGEN           */
47891   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_CLKEN = 65536,/*!< RTC_CLKEN : [16] Clock enable for the RTC                            */
47892   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_SDIO_XIN_CLKEN = 131072,/*!< SDIO_XIN_CLKEN : [17] Clock enable for the SDIO_XIN            */
47893   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART0HF_CLKEN = 262144,/*!< UART0HF_CLKEN : [18] Clock enable for the UART0 HF              */
47894   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART1HF_CLKEN = 524288,/*!< UART1HF_CLKEN : [19] Clock enable for the UART1 HF              */
47895   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART2HF_CLKEN = 1048576,/*!< UART2HF_CLKEN : [20] Clock enable for the UART2 HF             */
47896   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART3HF_CLKEN = 2097152,/*!< UART3HF_CLKEN : [21] Clock enable for the UART3 HF             */
47897   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_USB_REFCLK_CLKEN = 4194304,/*!< USB_REFCLK_CLKEN : [22] Clock enable for the USB_REFCLK     */
47898   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_WDT_CLKEN = 8388608,/*!< WDT_CLKEN : [23] Clock enable for the WDT                          */
47899 } CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum;
47900 
47901 /* =========================================================  MISC  ========================================================== */
47902 /* ===========================================  CLKGEN MISC PWRONCLKENDISP [6..6]  =========================================== */
47903 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENDISP                                                */
47904   CLKGEN_MISC_PWRONCLKENDISP_DISPCLKENRST = 0,  /*!< DISPCLKENRST : Enable Display Clock to run during reset                   */
47905   CLKGEN_MISC_PWRONCLKENDISP_DEFEATURE = 1,     /*!< DEFEATURE : Revert to revA behavior. Disable display clock from
47906                                                      running during reset.                                                     */
47907 } CLKGEN_MISC_PWRONCLKENDISP_Enum;
47908 
47909 /* ==============================================  CLKGEN MISC FRCHFRC2 [5..5]  ============================================== */
47910 typedef enum {                                  /*!< CLKGEN_MISC_FRCHFRC2                                                      */
47911   CLKGEN_MISC_FRCHFRC2_NOFRC           = 0,     /*!< NOFRC : Do not force HFRC2 on; stops in deep sleep mode.                  */
47912   CLKGEN_MISC_FRCHFRC2_FRC             = 1,     /*!< FRC : Force HFRC2 on; runs in deep sleep mode.                            */
47913 } CLKGEN_MISC_FRCHFRC2_Enum;
47914 
47915 /* ==========================================  CLKGEN MISC USEHFRC2FQ192MHZ [4..4]  ========================================== */
47916 typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ192MHZ                                              */
47917   CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRCFQ192MHz = 0,/*!< HFRCFQ192MHz : Use HFRC-192MHz                                            */
47918   CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRC2FQ192MHz = 1,/*!< HFRC2FQ192MHz : Use HFRC2-192MHz                                         */
47919 } CLKGEN_MISC_USEHFRC2FQ192MHZ_Enum;
47920 
47921 /* ==========================================  CLKGEN MISC USEHFRC2FQ96MHZ [3..3]  =========================================== */
47922 typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ96MHZ                                               */
47923   CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRCFQ96MHz = 0,  /*!< HFRCFQ96MHz : Use HFRC-96MHz                                              */
47924   CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRC2FQ96MHz = 1, /*!< HFRC2FQ96MHz : Use HFRC2-96MHz                                            */
47925 } CLKGEN_MISC_USEHFRC2FQ96MHZ_Enum;
47926 
47927 /* ==============================================  CLKGEN MISC FRCHFRC [0..0]  =============================================== */
47928 typedef enum {                                  /*!< CLKGEN_MISC_FRCHFRC                                                       */
47929   CLKGEN_MISC_FRCHFRC_NOFRC            = 0,     /*!< NOFRC : HFRC stops in deep sleep mode                                     */
47930   CLKGEN_MISC_FRCHFRC_FRC              = 1,     /*!< FRC : HFRC runs in deep sleep mode                                        */
47931 } CLKGEN_MISC_FRCHFRC_Enum;
47932 
47933 /* ========================================================  HF2ADJ0  ======================================================== */
47934 /* =========================================  CLKGEN HF2ADJ0 HF2ADJFASTSTREN [1..1]  ========================================= */
47935 typedef enum {                                  /*!< CLKGEN_HF2ADJ0_HF2ADJFASTSTREN                                            */
47936   CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_DIS   = 0,     /*!< DIS : Fast_start_delay disable                                            */
47937   CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_EN    = 1,     /*!< EN : Fast_start_delay enable                                              */
47938 } CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Enum;
47939 
47940 /* ============================================  CLKGEN HF2ADJ0 HF2ADJEN [0..0]  ============================================= */
47941 typedef enum {                                  /*!< CLKGEN_HF2ADJ0_HF2ADJEN                                                   */
47942   CLKGEN_HF2ADJ0_HF2ADJEN_DIS          = 0,     /*!< DIS : HF2ADJ disable                                                      */
47943   CLKGEN_HF2ADJ0_HF2ADJEN_EN           = 1,     /*!< EN : HF2ADJ enable                                                        */
47944 } CLKGEN_HF2ADJ0_HF2ADJEN_Enum;
47945 
47946 /* ========================================================  HF2ADJ1  ======================================================== */
47947 /* ==========================================  CLKGEN HF2ADJ1 HF2ADJTRIMEN [0..2]  =========================================== */
47948 typedef enum {                                  /*!< CLKGEN_HF2ADJ1_HF2ADJTRIMEN                                               */
47949   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN0 = 0,     /*!< TRIM_EN0 : 0                                                              */
47950   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN1 = 1,     /*!< TRIM_EN1 : HF2ADJTRIMOUT                                                  */
47951   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN2 = 2,     /*!< TRIM_EN2 : HF2ADJTRIMOFFSET                                               */
47952   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN3 = 3,     /*!< TRIM_EN3 : HF2ADJTRIMOUT + HF2ADJTRIMOFFSET                               */
47953   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN4 = 4,     /*!< TRIM_EN4 : HF2TUNE                                                        */
47954   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN5 = 5,     /*!< TRIM_EN5 : HF2ADJTRIMOUT + HF2TUNE                                        */
47955   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN6 = 6,     /*!< TRIM_EN6 : HF2ADJTRIMOFFSET + HF2TUNE                                     */
47956   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN7 = 7,     /*!< TRIM_EN7 : HF2ADJTRIMOUT + HF2ADJTRIMOFFSET + HF2TUNE                     */
47957 } CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Enum;
47958 
47959 /* ========================================================  HF2ADJ2  ======================================================== */
47960 /* =======================================  CLKGEN HF2ADJ2 HF2ADJXTALDIVRATIO [0..1]  ======================================== */
47961 typedef enum {                                  /*!< CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO                                         */
47962   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M = 0,/*!< XTAL32M : XTAL32MHz                                                       */
47963   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV2 = 1,/*!< XTAL32M_DIV2 : XTAL32MHz / 2                                         */
47964   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV4 = 2,/*!< XTAL32M_DIV4 : XTAL32MHz / 4                                         */
47965   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV8 = 3,/*!< XTAL32M_DIV8 : XTAL32MHz / 8                                         */
47966 } CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Enum;
47967 
47968 /* ========================================================  HF2VAL  ========================================================= */
47969 /* =======================================================  LFRCCTRL  ======================================================== */
47970 /* ======================================================  DISPCLKCTRL  ====================================================== */
47971 /* =========================================  CLKGEN DISPCLKCTRL DISPCLKSEL [4..5]  ========================================== */
47972 typedef enum {                                  /*!< CLKGEN_DISPCLKCTRL_DISPCLKSEL                                             */
47973   CLKGEN_DISPCLKCTRL_DISPCLKSEL_OFF    = 0,     /*!< OFF : Static value of 0 selected for DPHY clock input                     */
47974   CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC48 = 1,     /*!< HFRC48 : 48MHz sourced from the HFRC                                      */
47975   CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC96 = 2,     /*!< HFRC96 : 96MHz sourced from the HFRC                                      */
47976   CLKGEN_DISPCLKCTRL_DISPCLKSEL_DPHYPLL = 3,    /*!< DPHYPLL : DPHY PLL                                                        */
47977 } CLKGEN_DISPCLKCTRL_DISPCLKSEL_Enum;
47978 
47979 /* ==========================================  CLKGEN DISPCLKCTRL PLLCLKSEL [0..1]  ========================================== */
47980 typedef enum {                                  /*!< CLKGEN_DISPCLKCTRL_PLLCLKSEL                                              */
47981   CLKGEN_DISPCLKCTRL_PLLCLKSEL_OFF     = 0,     /*!< OFF : Static value of 0 selected for DPHY clock input                     */
47982   CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC12  = 1,     /*!< HFRC12 : 12MHz sourced from the HFRC                                      */
47983   CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC6   = 2,     /*!< HFRC6 : 6MHz sourced from the HFRC                                        */
47984   CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFXT_16 = 3,     /*!< HFXT_16 : High Frequency XTAL input (16MHz)                               */
47985 } CLKGEN_DISPCLKCTRL_PLLCLKSEL_Enum;
47986 
47987 
47988 
47989 /* =========================================================================================================================== */
47990 /* ================                                            CPU                                            ================ */
47991 /* =========================================================================================================================== */
47992 
47993 /* =======================================================  CACHECFG  ======================================================== */
47994 /* ==============================================  CPU CACHECFG CONFIG [4..7]  =============================================== */
47995 typedef enum {                                  /*!< CPU_CACHECFG_CONFIG                                                       */
47996   CPU_CACHECFG_CONFIG_W1_128B_512E     = 4,     /*!< W1_128B_512E : Direct mapped, 128-bit linesize, 512 entries
47997                                                      (4 SRAMs active)                                                          */
47998   CPU_CACHECFG_CONFIG_W2_128B_512E     = 5,     /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512
47999                                                      entries (8 SRAMs active)                                                  */
48000   CPU_CACHECFG_CONFIG_W1_128B_1024E    = 8,     /*!< W1_128B_1024E : Direct mapped, 128-bit linesize, 1024 entries
48001                                                      (8 SRAMs active)                                                          */
48002   CPU_CACHECFG_CONFIG_W1_128B_2048E    = 12,    /*!< W1_128B_2048E : Direct mapped, 128-bit linesize, 2048 entries
48003                                                      (4 SRAMs active)                                                          */
48004   CPU_CACHECFG_CONFIG_W2_128B_2048E    = 13,    /*!< W2_128B_2048E : Two-way set associative, 128-bit linesize, 2048
48005                                                      entries (8 SRAMs active)                                                  */
48006   CPU_CACHECFG_CONFIG_W1_128B_4096E    = 14,    /*!< W1_128B_4096E : Direct mapped, 128-bit linesize, 4096 entries
48007                                                      (8 SRAMs active)                                                          */
48008 } CPU_CACHECFG_CONFIG_Enum;
48009 
48010 /* =======================================================  CACHECTRL  ======================================================= */
48011 /* ============================================  CPU CACHECTRL RESETSTAT [1..1]  ============================================= */
48012 typedef enum {                                  /*!< CPU_CACHECTRL_RESETSTAT                                                   */
48013   CPU_CACHECTRL_RESETSTAT_CLEAR        = 1,     /*!< CLEAR : Clear Cache Stats                                                 */
48014 } CPU_CACHECTRL_RESETSTAT_Enum;
48015 
48016 /* =======================================================  NCR0START  ======================================================= */
48017 /* ========================================================  NCR0END  ======================================================== */
48018 /* =======================================================  NCR1START  ======================================================= */
48019 /* ========================================================  NCR1END  ======================================================== */
48020 /* ========================================================  DAXICFG  ======================================================== */
48021 /* ============================================  CPU DAXICFG BUFFERENABLE [8..9]  ============================================ */
48022 typedef enum {                                  /*!< CPU_DAXICFG_BUFFERENABLE                                                  */
48023   CPU_DAXICFG_BUFFERENABLE_ONE         = 0,     /*!< ONE : Single buffer mode                                                  */
48024   CPU_DAXICFG_BUFFERENABLE_TWO         = 1,     /*!< TWO : Enable Two buffers                                                  */
48025   CPU_DAXICFG_BUFFERENABLE_THREE       = 2,     /*!< THREE : Enable Three buffers                                              */
48026   CPU_DAXICFG_BUFFERENABLE_FOUR        = 3,     /*!< FOUR : Enable Four buffers                                                */
48027 } CPU_DAXICFG_BUFFERENABLE_Enum;
48028 
48029 /* =======================================================  DAXICTRL  ======================================================== */
48030 /* ====================================================  ICODEFAULTADDR  ===================================================== */
48031 /* ====================================================  DCODEFAULTADDR  ===================================================== */
48032 /* =====================================================  SYSFAULTADDR  ====================================================== */
48033 /* ======================================================  FAULTSTATUS  ====================================================== */
48034 /* ============================================  CPU FAULTSTATUS SYSFAULT [2..2]  ============================================ */
48035 typedef enum {                                  /*!< CPU_FAULTSTATUS_SYSFAULT                                                  */
48036   CPU_FAULTSTATUS_SYSFAULT_NOFAULT     = 0,     /*!< NOFAULT : No bus fault has been detected.                                 */
48037   CPU_FAULTSTATUS_SYSFAULT_FAULT       = 1,     /*!< FAULT : Bus fault detected.                                               */
48038 } CPU_FAULTSTATUS_SYSFAULT_Enum;
48039 
48040 /* ===========================================  CPU FAULTSTATUS DCODEFAULT [1..1]  =========================================== */
48041 typedef enum {                                  /*!< CPU_FAULTSTATUS_DCODEFAULT                                                */
48042   CPU_FAULTSTATUS_DCODEFAULT_NOFAULT   = 0,     /*!< NOFAULT : No DCODE fault has been detected.                               */
48043   CPU_FAULTSTATUS_DCODEFAULT_FAULT     = 1,     /*!< FAULT : DCODE fault detected.                                             */
48044 } CPU_FAULTSTATUS_DCODEFAULT_Enum;
48045 
48046 /* ===========================================  CPU FAULTSTATUS ICODEFAULT [0..0]  =========================================== */
48047 typedef enum {                                  /*!< CPU_FAULTSTATUS_ICODEFAULT                                                */
48048   CPU_FAULTSTATUS_ICODEFAULT_NOFAULT   = 0,     /*!< NOFAULT : No ICODE fault has been detected.                               */
48049   CPU_FAULTSTATUS_ICODEFAULT_FAULT     = 1,     /*!< FAULT : ICODE fault detected.                                             */
48050 } CPU_FAULTSTATUS_ICODEFAULT_Enum;
48051 
48052 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
48053 /* =======================================  CPU FAULTCAPTUREEN FAULTCAPTUREEN [0..0]  ======================================== */
48054 typedef enum {                                  /*!< CPU_FAULTCAPTUREEN_FAULTCAPTUREEN                                         */
48055   CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,    /*!< DIS : Disable fault capture.                                              */
48056   CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1,     /*!< EN : Enable fault capture.                                                */
48057 } CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum;
48058 
48059 /* =========================================================  INTEN  ========================================================= */
48060 /* ========================================================  INTSTAT  ======================================================== */
48061 /* ========================================================  INTCLR  ========================================================= */
48062 /* ========================================================  INTSET  ========================================================= */
48063 /* =====================================================  WRITEERRADDR  ====================================================== */
48064 /* =========================================================  DMON0  ========================================================= */
48065 /* =========================================================  DMON1  ========================================================= */
48066 /* =========================================================  DMON2  ========================================================= */
48067 /* =========================================================  DMON3  ========================================================= */
48068 /* =========================================================  IMON0  ========================================================= */
48069 /* =========================================================  IMON1  ========================================================= */
48070 /* =========================================================  IMON2  ========================================================= */
48071 /* =========================================================  IMON3  ========================================================= */
48072 
48073 
48074 /* =========================================================================================================================== */
48075 /* ================                                          CRYPTO                                           ================ */
48076 /* =========================================================================================================================== */
48077 
48078 /* ======================================================  MEMORYMAP0  ======================================================= */
48079 /* ======================================================  MEMORYMAP1  ======================================================= */
48080 /* ======================================================  MEMORYMAP2  ======================================================= */
48081 /* ======================================================  MEMORYMAP3  ======================================================= */
48082 /* ======================================================  MEMORYMAP4  ======================================================= */
48083 /* ======================================================  MEMORYMAP5  ======================================================= */
48084 /* ======================================================  MEMORYMAP6  ======================================================= */
48085 /* ======================================================  MEMORYMAP7  ======================================================= */
48086 /* ======================================================  MEMORYMAP8  ======================================================= */
48087 /* ======================================================  MEMORYMAP9  ======================================================= */
48088 /* ======================================================  MEMORYMAP10  ====================================================== */
48089 /* ======================================================  MEMORYMAP11  ====================================================== */
48090 /* ======================================================  MEMORYMAP12  ====================================================== */
48091 /* ======================================================  MEMORYMAP13  ====================================================== */
48092 /* ======================================================  MEMORYMAP14  ====================================================== */
48093 /* ======================================================  MEMORYMAP15  ====================================================== */
48094 /* ======================================================  MEMORYMAP16  ====================================================== */
48095 /* ======================================================  MEMORYMAP17  ====================================================== */
48096 /* ======================================================  MEMORYMAP18  ====================================================== */
48097 /* ======================================================  MEMORYMAP19  ====================================================== */
48098 /* ======================================================  MEMORYMAP20  ====================================================== */
48099 /* ======================================================  MEMORYMAP21  ====================================================== */
48100 /* ======================================================  MEMORYMAP22  ====================================================== */
48101 /* ======================================================  MEMORYMAP23  ====================================================== */
48102 /* ======================================================  MEMORYMAP24  ====================================================== */
48103 /* ======================================================  MEMORYMAP25  ====================================================== */
48104 /* ======================================================  MEMORYMAP26  ====================================================== */
48105 /* ======================================================  MEMORYMAP27  ====================================================== */
48106 /* ======================================================  MEMORYMAP28  ====================================================== */
48107 /* ======================================================  MEMORYMAP29  ====================================================== */
48108 /* ======================================================  MEMORYMAP30  ====================================================== */
48109 /* ======================================================  MEMORYMAP31  ====================================================== */
48110 /* ========================================================  OPCODE  ========================================================= */
48111 /* =============================================  CRYPTO OPCODE OPCODE [27..31]  ============================================= */
48112 typedef enum {                                  /*!< CRYPTO_OPCODE_OPCODE                                                      */
48113   CRYPTO_OPCODE_OPCODE_ADD             = 4,     /*!< ADD : Add,Inc opcode                                                      */
48114   CRYPTO_OPCODE_OPCODE_SUB             = 5,     /*!< SUB : Sub,Dec,Neg opcode                                                  */
48115   CRYPTO_OPCODE_OPCODE_MODADD          = 6,     /*!< MODADD : ModAdd,ModInc opcode                                             */
48116   CRYPTO_OPCODE_OPCODE_MODSUB          = 7,     /*!< MODSUB : ModSub,ModDec,ModNeg opcode                                      */
48117   CRYPTO_OPCODE_OPCODE_AND             = 8,     /*!< AND : AND,TST0,CLR0 opcode                                                */
48118   CRYPTO_OPCODE_OPCODE_OR              = 9,     /*!< OR : OR,COPY,SET0 opcode                                                  */
48119   CRYPTO_OPCODE_OPCODE_XOR             = 10,    /*!< XOR : XOR,FLIP0,INVERT,COMPARE opcode                                     */
48120   CRYPTO_OPCODE_OPCODE_SHR0            = 12,    /*!< SHR0 : SHR0 opcode                                                        */
48121   CRYPTO_OPCODE_OPCODE_SHR1            = 13,    /*!< SHR1 : SHR1 opcode                                                        */
48122   CRYPTO_OPCODE_OPCODE_SHL0            = 14,    /*!< SHL0 : SHL0 opcode                                                        */
48123   CRYPTO_OPCODE_OPCODE_SHL1            = 15,    /*!< SHL1 : SHL1 opcode                                                        */
48124   CRYPTO_OPCODE_OPCODE_MULLOW          = 16,    /*!< MULLOW : MulLow opcode                                                    */
48125   CRYPTO_OPCODE_OPCODE_MODMUL          = 17,    /*!< MODMUL : ModMul opcode                                                    */
48126   CRYPTO_OPCODE_OPCODE_MODMULN         = 18,    /*!< MODMULN : ModMulN opcode                                                  */
48127   CRYPTO_OPCODE_OPCODE_MODEXP          = 19,    /*!< MODEXP : ModExp opcode                                                    */
48128   CRYPTO_OPCODE_OPCODE_DIVISION        = 20,    /*!< DIVISION : Division opcode                                                */
48129   CRYPTO_OPCODE_OPCODE_DIV             = 21,    /*!< DIV : Div opcode                                                          */
48130   CRYPTO_OPCODE_OPCODE_MODDIV          = 22,    /*!< MODDIV : ModDiv opcode                                                    */
48131   CRYPTO_OPCODE_OPCODE_TERMINATE       = 0,     /*!< TERMINATE : Terminate opcode                                              */
48132 } CRYPTO_OPCODE_OPCODE_Enum;
48133 
48134 /* ======================================================  NNPT0T1ADDR  ====================================================== */
48135 /* =======================================================  PKASTATUS  ======================================================= */
48136 /* ======================================================  PKASWRESET  ======================================================= */
48137 /* =========================================================  PKAL0  ========================================================= */
48138 /* =========================================================  PKAL1  ========================================================= */
48139 /* =========================================================  PKAL2  ========================================================= */
48140 /* =========================================================  PKAL3  ========================================================= */
48141 /* =========================================================  PKAL4  ========================================================= */
48142 /* =========================================================  PKAL5  ========================================================= */
48143 /* =========================================================  PKAL6  ========================================================= */
48144 /* =========================================================  PKAL7  ========================================================= */
48145 /* ======================================================  PKAPIPERDY  ======================================================= */
48146 /* ========================================================  PKADONE  ======================================================== */
48147 /* =====================================================  PKAMONSELECT  ====================================================== */
48148 /* ======================================================  PKAVERSION  ======================================================= */
48149 /* ======================================================  PKAMONREAD  ======================================================= */
48150 /* ======================================================  PKASRAMADDR  ====================================================== */
48151 /* =====================================================  PKASRAMWDATA  ====================================================== */
48152 /* =====================================================  PKASRAMRDATA  ====================================================== */
48153 /* =====================================================  PKASRAMWRCLR  ====================================================== */
48154 /* =====================================================  PKASRAMRADDR  ====================================================== */
48155 /* =====================================================  PKAWORDACCESS  ===================================================== */
48156 /* ======================================================  PKABUFFADDR  ====================================================== */
48157 /* ========================================================  RNGIMR  ========================================================= */
48158 /* ========================================================  RNGISR  ========================================================= */
48159 /* ==========================================  CRYPTO RNGISR WHICHKATERR [25..26]  =========================================== */
48160 typedef enum {                                  /*!< CRYPTO_RNGISR_WHICHKATERR                                                 */
48161   CRYPTO_RNGISR_WHICHKATERR_INSTANT_1  = 0,     /*!< INSTANT_1 : first test of instantiation                                   */
48162   CRYPTO_RNGISR_WHICHKATERR_INSTANT_2  = 1,     /*!< INSTANT_2 : second test of instantiation                                  */
48163   CRYPTO_RNGISR_WHICHKATERR_RESEED_1   = 2,     /*!< RESEED_1 : first test of reseeding                                        */
48164   CRYPTO_RNGISR_WHICHKATERR_RESEED_2   = 3,     /*!< RESEED_2 : second test of reseeding                                       */
48165 } CRYPTO_RNGISR_WHICHKATERR_Enum;
48166 
48167 /* ========================================================  RNGICR  ========================================================= */
48168 /* ======================================================  TRNGCONFIG  ======================================================= */
48169 /* ============================================  CRYPTO TRNGCONFIG SOPSEL [2..2]  ============================================ */
48170 typedef enum {                                  /*!< CRYPTO_TRNGCONFIG_SOPSEL                                                  */
48171   CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_1  = 1,     /*!< SOP_DATA_1 : sop_data port reflects TRNG output (EHR_DATA).               */
48172   CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_2  = 0,     /*!< SOP_DATA_2 : sop_data port reflects PRNG output (RNG_READOUT).
48173                                                      Note: Secure output is used for direct connection of the
48174                                                      RNG block outputs to an engine input key.                                 */
48175 } CRYPTO_TRNGCONFIG_SOPSEL_Enum;
48176 
48177 /* =======================================================  TRNGVALID  ======================================================= */
48178 /* =======================================================  EHRDATA0  ======================================================== */
48179 /* =======================================================  EHRDATA1  ======================================================== */
48180 /* =======================================================  EHRDATA2  ======================================================== */
48181 /* =======================================================  EHRDATA3  ======================================================== */
48182 /* =======================================================  EHRDATA4  ======================================================== */
48183 /* =======================================================  EHRDATA5  ======================================================== */
48184 /* ====================================================  RNDSOURCEENABLE  ==================================================== */
48185 /* ======================================================  SAMPLECNT1  ======================================================= */
48186 /* ===================================================  AUTOCORRSTATISTIC  =================================================== */
48187 /* ===================================================  TRNGDEBUGCONTROL  ==================================================== */
48188 /* ======================================================  RNGSWRESET  ======================================================= */
48189 /* ====================================================  RNGDEBUGENINPUT  ==================================================== */
48190 /* ========================================================  RNGBUSY  ======================================================== */
48191 /* ====================================================  RSTBITSCOUNTER  ===================================================== */
48192 /* ======================================================  RNGVERSION  ======================================================= */
48193 /* ========================================  CRYPTO RNGVERSION RNGUSE5SBOXES [7..7]  ========================================= */
48194 typedef enum {                                  /*!< CRYPTO_RNGVERSION_RNGUSE5SBOXES                                           */
48195   CRYPTO_RNGVERSION_RNGUSE5SBOXES_20_SBOX_AES = 0,/*!< 20_SBOX_AES : 20 SBOX AES                                               */
48196   CRYPTO_RNGVERSION_RNGUSE5SBOXES_5_SBOX_AES = 1,/*!< 5_SBOX_AES : 5 SBOX AES                                                  */
48197 } CRYPTO_RNGVERSION_RNGUSE5SBOXES_Enum;
48198 
48199 /* =======================================  CRYPTO RNGVERSION RESEEDINGEXISTS [6..6]  ======================================== */
48200 typedef enum {                                  /*!< CRYPTO_RNGVERSION_RESEEDINGEXISTS                                         */
48201   CRYPTO_RNGVERSION_RESEEDINGEXISTS_EXISTS = 1, /*!< EXISTS : exists                                                           */
48202   CRYPTO_RNGVERSION_RESEEDINGEXISTS_NORESEED = 0,/*!< NORESEED : Reseed does not exists                                        */
48203 } CRYPTO_RNGVERSION_RESEEDINGEXISTS_Enum;
48204 
48205 /* ==========================================  CRYPTO RNGVERSION KATEXISTS [5..5]  =========================================== */
48206 typedef enum {                                  /*!< CRYPTO_RNGVERSION_KATEXISTS                                               */
48207   CRYPTO_RNGVERSION_KATEXISTS_NO_EXIST = 0,     /*!< NO_EXIST : does not exist                                                 */
48208   CRYPTO_RNGVERSION_KATEXISTS_EXISTS   = 1,     /*!< EXISTS : exists                                                           */
48209 } CRYPTO_RNGVERSION_KATEXISTS_Enum;
48210 
48211 /* ==========================================  CRYPTO RNGVERSION PRNGEXISTS [4..4]  ========================================== */
48212 typedef enum {                                  /*!< CRYPTO_RNGVERSION_PRNGEXISTS                                              */
48213   CRYPTO_RNGVERSION_PRNGEXISTS_NO_EXIST = 0,    /*!< NO_EXIST : does not exist                                                 */
48214   CRYPTO_RNGVERSION_PRNGEXISTS_EXISTS  = 1,     /*!< EXISTS : exists                                                           */
48215 } CRYPTO_RNGVERSION_PRNGEXISTS_Enum;
48216 
48217 /* ======================================  CRYPTO RNGVERSION TRNGTESTSBYPASSEN [3..3]  ======================================= */
48218 typedef enum {                                  /*!< CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN                                       */
48219   CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_NE = 0,/*!< TRNG_NE : trng tests bypass not enabled                                 */
48220   CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_E = 1,/*!< TRNG_E : trng tests bypass enabled                                       */
48221 } CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Enum;
48222 
48223 /* ========================================  CRYPTO RNGVERSION AUTOCORREXISTS [2..2]  ======================================== */
48224 typedef enum {                                  /*!< CRYPTO_RNGVERSION_AUTOCORREXISTS                                          */
48225   CRYPTO_RNGVERSION_AUTOCORREXISTS_NO_EXIST = 0,/*!< NO_EXIST : does not exist                                                 */
48226   CRYPTO_RNGVERSION_AUTOCORREXISTS_EXISTS = 1,  /*!< EXISTS : exists                                                           */
48227 } CRYPTO_RNGVERSION_AUTOCORREXISTS_Enum;
48228 
48229 /* =========================================  CRYPTO RNGVERSION CRNGTEXISTS [1..1]  ========================================== */
48230 typedef enum {                                  /*!< CRYPTO_RNGVERSION_CRNGTEXISTS                                             */
48231   CRYPTO_RNGVERSION_CRNGTEXISTS_NO_EXIST = 0,   /*!< NO_EXIST : does not exist                                                 */
48232   CRYPTO_RNGVERSION_CRNGTEXISTS_EXISTS = 1,     /*!< EXISTS : exists                                                           */
48233 } CRYPTO_RNGVERSION_CRNGTEXISTS_Enum;
48234 
48235 /* =========================================  CRYPTO RNGVERSION EHRWIDTH192 [0..0]  ========================================== */
48236 typedef enum {                                  /*!< CRYPTO_RNGVERSION_EHRWIDTH192                                             */
48237   CRYPTO_RNGVERSION_EHRWIDTH192_128_EHR = 0,    /*!< 128_EHR : 128 bit EHR                                                     */
48238   CRYPTO_RNGVERSION_EHRWIDTH192_192_EHR = 1,    /*!< 192_EHR : 192 bit EHR                                                     */
48239 } CRYPTO_RNGVERSION_EHRWIDTH192_Enum;
48240 
48241 /* =====================================================  RNGCLKENABLE  ====================================================== */
48242 /* =====================================================  RNGDMAENABLE  ====================================================== */
48243 /* =====================================================  RNGDMASRCMASK  ===================================================== */
48244 /* ====================================================  RNGDMASRAMADDR  ===================================================== */
48245 /* ====================================================  RNGWATCHDOGVAL  ===================================================== */
48246 /* =====================================================  RNGDMASTATUS  ====================================================== */
48247 /* ===================================================  CHACHACONTROLREG  ==================================================== */
48248 /* ======================================  CRYPTO CHACHACONTROLREG NUMOFROUNDS [4..5]  ======================================= */
48249 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_NUMOFROUNDS                                       */
48250   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_20_ROUNDS = 0,/*!< 20_ROUNDS : 20 rounds                                                 */
48251   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_12_ROUNDS = 1,/*!< 12_ROUNDS : 12 rounds                                                 */
48252   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_8_ROUNDS = 2,/*!< 8_ROUNDS : 8 rounds                                                    */
48253   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_N_A = 3,  /*!< N_A : Not applicable                                                      */
48254 } CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Enum;
48255 
48256 /* =========================================  CRYPTO CHACHACONTROLREG KEYLEN [3..3]  ========================================= */
48257 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_KEYLEN                                            */
48258   CRYPTO_CHACHACONTROLREG_KEYLEN_256_BIT = 0,   /*!< 256_BIT : 256 bit.                                                        */
48259   CRYPTO_CHACHACONTROLREG_KEYLEN_128_BIT = 1,   /*!< 128_BIT : 128 bit.                                                        */
48260 } CRYPTO_CHACHACONTROLREG_KEYLEN_Enum;
48261 
48262 /* ===================================  CRYPTO CHACHACONTROLREG CALCKEYFORPOLY1305 [2..2]  =================================== */
48263 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305                                */
48264   CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_DISABLE = 0,/*!< DISABLE : disable.                                               */
48265   CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_ENABLE = 1,/*!< ENABLE : enable.                                                  */
48266 } CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Enum;
48267 
48268 /* ======================================  CRYPTO CHACHACONTROLREG INITFROMHOST [1..1]  ====================================== */
48269 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_INITFROMHOST                                      */
48270   CRYPTO_CHACHACONTROLREG_INITFROMHOST_DISABLE = 0,/*!< DISABLE : disable.                                                     */
48271   CRYPTO_CHACHACONTROLREG_INITFROMHOST_ENABLE = 1,/*!< ENABLE : enable.                                                        */
48272 } CRYPTO_CHACHACONTROLREG_INITFROMHOST_Enum;
48273 
48274 /* =====================================  CRYPTO CHACHACONTROLREG CHACHAORSALSA [0..0]  ====================================== */
48275 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_CHACHAORSALSA                                     */
48276   CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_CHACHA = 0,/*!< CHACHA : ChaCha mode,                                                  */
48277   CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_SALSA = 1,/*!< SALSA : Salsa mode.                                                     */
48278 } CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Enum;
48279 
48280 /* =====================================================  CHACHAVERSION  ===================================================== */
48281 /* ======================================================  CHACHAKEY0  ======================================================= */
48282 /* ======================================================  CHACHAKEY1  ======================================================= */
48283 /* ======================================================  CHACHAKEY2  ======================================================= */
48284 /* ======================================================  CHACHAKEY3  ======================================================= */
48285 /* ======================================================  CHACHAKEY4  ======================================================= */
48286 /* ======================================================  CHACHAKEY5  ======================================================= */
48287 /* ======================================================  CHACHAKEY6  ======================================================= */
48288 /* ======================================================  CHACHAKEY7  ======================================================= */
48289 /* =======================================================  CHACHAIV0  ======================================================= */
48290 /* =======================================================  CHACHAIV1  ======================================================= */
48291 /* ======================================================  CHACHABUSY  ======================================================= */
48292 /* =====================================================  CHACHAHWFLAGS  ===================================================== */
48293 /* ========================================  CRYPTO CHACHAHWFLAGS FASTCHACHA [2..2]  ========================================= */
48294 typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_FASTCHACHA                                           */
48295   CRYPTO_CHACHAHWFLAGS_FASTCHACHA_DISABLE = 0,  /*!< DISABLE : disable.                                                        */
48296   CRYPTO_CHACHAHWFLAGS_FASTCHACHA_ENABLE = 1,   /*!< ENABLE : enable.                                                          */
48297 } CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Enum;
48298 
48299 /* ========================================  CRYPTO CHACHAHWFLAGS SALSAEXISTS [1..1]  ======================================== */
48300 typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_SALSAEXISTS                                          */
48301   CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_DISABLE = 0, /*!< DISABLE : disable.                                                        */
48302   CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_ENABLE = 1,  /*!< ENABLE : enable.                                                          */
48303 } CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Enum;
48304 
48305 /* =======================================  CRYPTO CHACHAHWFLAGS CHACHAEXISTS [0..0]  ======================================== */
48306 typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS                                         */
48307   CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_DISABLE = 0,/*!< DISABLE : disable.                                                        */
48308   CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_ENABLE = 1, /*!< ENABLE : enable.                                                          */
48309 } CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Enum;
48310 
48311 /* ===================================================  CHACHABLOCKCNTLSB  =================================================== */
48312 /* ===================================================  CHACHABLOCKCNTMSB  =================================================== */
48313 /* =====================================================  CHACHASWRESET  ===================================================== */
48314 /* ===================================================  CHACHAFORPOLYKEY0  =================================================== */
48315 /* ===================================================  CHACHAFORPOLYKEY1  =================================================== */
48316 /* ===================================================  CHACHAFORPOLYKEY2  =================================================== */
48317 /* ===================================================  CHACHAFORPOLYKEY3  =================================================== */
48318 /* ===================================================  CHACHAFORPOLYKEY4  =================================================== */
48319 /* ===================================================  CHACHAFORPOLYKEY5  =================================================== */
48320 /* ===================================================  CHACHAFORPOLYKEY6  =================================================== */
48321 /* ===================================================  CHACHAFORPOLYKEY7  =================================================== */
48322 /* ==============================================  CHACHABYTEWORDORDERCNTLREG  =============================================== */
48323 /* =============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADOUTBYTEORDER [4..4]  ============================== */
48324 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER                     */
48325   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_DISABLE = 0,/*!< DISABLE : disable.                                    */
48326   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each byte in each word output (b0->b3,
48327                                                      b1->b2, b2->b1,b3->b0))                                                   */
48328 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Enum;
48329 
48330 /* =============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADOUTWORDORDER [3..3]  ============================== */
48331 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER                     */
48332   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_DISABLE = 0,/*!< DISABLE : disable.                                    */
48333   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each word in 128 bit output ( w0->w3,
48334                                                      w1->w2, w2->w1,w3-w0))                                                    */
48335 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Enum;
48336 
48337 /* ===========================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHACOREMATRIXLBEORDER [2..2]  =========================== */
48338 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER                */
48339   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_DISABLE = 0,/*!< DISABLE : disable.                               */
48340   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each quarter of a matrix (m[0-127]->m[384-511],
48341                                                      m[128-255]->m[256-383], m[256-383]->m[128-255], m[384-511]->m[0-127]))    */
48342 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Enum;
48343 
48344 /* ==============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADINBYTEORDER [1..1]  ============================== */
48345 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER                      */
48346   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_DISABLE = 0,/*!< DISABLE : disable.                                     */
48347   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each byte in each word input (b0->b3,
48348                                                      b1->b2, b2->b1,b3->b0))                                                   */
48349 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Enum;
48350 
48351 /* ==============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADINWORDORDER [0..0]  ============================== */
48352 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER                      */
48353   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_DISABLE = 0,/*!< DISABLE : disable.                                     */
48354   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each word in 128 bit input ( w0->w3,
48355                                                      w1->w2, w2->w1,w3-w0))                                                    */
48356 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Enum;
48357 
48358 /* ====================================================  CHACHADEBUGREG  ===================================================== */
48359 /* ===================================  CRYPTO CHACHADEBUGREG CHACHADEBUGFSMSTATE [0..1]  ==================================== */
48360 typedef enum {                                  /*!< CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE                                 */
48361   CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_IDLE_STATE = 0,/*!< IDLE_STATE : The idle state.                                   */
48362   CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_INIT_STATE = 1,/*!< INIT_STATE : The init state.                                   */
48363 } CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Enum;
48364 
48365 /* =======================================================  AESKEY00  ======================================================== */
48366 /* =======================================================  AESKEY01  ======================================================== */
48367 /* =======================================================  AESKEY02  ======================================================== */
48368 /* =======================================================  AESKEY03  ======================================================== */
48369 /* =======================================================  AESKEY04  ======================================================== */
48370 /* =======================================================  AESKEY05  ======================================================== */
48371 /* =======================================================  AESKEY06  ======================================================== */
48372 /* =======================================================  AESKEY07  ======================================================== */
48373 /* =======================================================  AESKEY10  ======================================================== */
48374 /* =======================================================  AESKEY11  ======================================================== */
48375 /* =======================================================  AESKEY12  ======================================================== */
48376 /* =======================================================  AESKEY13  ======================================================== */
48377 /* =======================================================  AESKEY14  ======================================================== */
48378 /* =======================================================  AESKEY15  ======================================================== */
48379 /* =======================================================  AESKEY16  ======================================================== */
48380 /* =======================================================  AESKEY17  ======================================================== */
48381 /* ========================================================  AESIV00  ======================================================== */
48382 /* ========================================================  AESIV01  ======================================================== */
48383 /* ========================================================  AESIV02  ======================================================== */
48384 /* ========================================================  AESIV03  ======================================================== */
48385 /* ========================================================  AESIV10  ======================================================== */
48386 /* ========================================================  AESIV11  ======================================================== */
48387 /* ========================================================  AESIV12  ======================================================== */
48388 /* ========================================================  AESIV13  ======================================================== */
48389 /* =======================================================  AESCTR00  ======================================================== */
48390 /* =======================================================  AESCTR01  ======================================================== */
48391 /* =======================================================  AESCTR02  ======================================================== */
48392 /* =======================================================  AESCTR03  ======================================================== */
48393 /* ========================================================  AESBUSY  ======================================================== */
48394 /* =========================================================  AESSK  ========================================================= */
48395 /* ======================================================  AESCMACINIT  ====================================================== */
48396 /* ========================================================  AESSK1  ========================================================= */
48397 /* ===================================================  AESREMAININGBYTES  =================================================== */
48398 /* ======================================================  AESCONTROL  ======================================================= */
48399 /* ======================================  CRYPTO AESCONTROL AESXORCRYPTOKEY [29..29]  ======================================= */
48400 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESXORCRYPTOKEY                                         */
48401   CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY = 0,/*!< CRYPTOKEY : The value that is written to AES_KEY0 is the value
48402                                                      of the HW cryptokey, as is.                                               */
48403   CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY_XOR = 1,/*!< CRYPTOKEY_XOR : The value that is written to AES_KEY0 is the
48404                                                      value of the HW cryptokey xored with the current value
48405                                                      of AES_KEY0.                                                              */
48406 } CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Enum;
48407 
48408 /* =====================================  CRYPTO AESCONTROL AESOUTMIDTUNTOHASH [28..28]  ===================================== */
48409 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH                                      */
48410   CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_2 = 0,/*!< HASH_2 : The AES engine writes to the hash the result of the
48411                                                      second tunnel stage.                                                      */
48412   CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_1 = 1,/*!< HASH_1 : The AES engine writes to the hash the result of the
48413                                                      first tunnel stage.                                                       */
48414 } CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Enum;
48415 
48416 /* ======================================  CRYPTO AESCONTROL AESTUNNELB1PADEN [26..26]  ====================================== */
48417 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNELB1PADEN                                        */
48418   CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_NO_PAD = 0,/*!< DATA_NO_PAD : The data input to the second tunnel block is not
48419                                                      padded with zeros.                                                        */
48420   CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_IS_PAD = 1,/*!< DATA_IS_PAD : The data input to the second tunnel block is padded
48421                                                      with zeros.                                                               */
48422 } CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Enum;
48423 
48424 /* ===================================  CRYPTO AESCONTROL AESOUTPUTMIDTUNNELDATA [25..25]  =================================== */
48425 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA                                  */
48426   CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_2 = 0,/*!< ENGINE_RSLT_2 : The AES engine outputs the result of the second
48427                                                      tunnel stage (standard tunneling).                                        */
48428   CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_1 = 1,/*!< ENGINE_RSLT_1 : The AES engine outputs the result of the first
48429                                                      tunnel stage.                                                             */
48430 } CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Enum;
48431 
48432 /* =====================================  CRYPTO AESCONTROL AESTUNNEL0ENCRYPT [24..24]  ====================================== */
48433 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT                                       */
48434   CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_D = 0,/*!< TUNNEL_1_D : the first tunnel stage performs decrypt operations.     */
48435   CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_E = 1,/*!< TUNNEL_1_E : the first tunnel stage performs encrypt operations.     */
48436 } CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Enum;
48437 
48438 /* ==================================  CRYPTO AESCONTROL AESTUNB1USESPADDEDDATAIN [23..23]  ================================== */
48439 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN                                */
48440   CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_BLOCK_1 = 0,/*!< BLOCK_1 : the output of the first block (standard tunneling
48441                                                      operation).                                                               */
48442   CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_AFTER_PAD = 1,/*!< AFTER_PAD : data_in after padding rather than the output of
48443                                                      the first block.                                                          */
48444 } CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Enum;
48445 
48446 /* =====================================  CRYPTO AESCONTROL AESTUNNEL1DECRYPT [22..22]  ====================================== */
48447 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT                                       */
48448   CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_E = 0,/*!< TUNNEL_2_E : the second tunnel stage performs encrypt operations.    */
48449   CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_D = 1,/*!< TUNNEL_2_D : the second tunnel stage performs decrypt operations.    */
48450 } CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Enum;
48451 
48452 /* ===========================================  CRYPTO AESCONTROL NKKEY1 [14..15]  =========================================== */
48453 typedef enum {                                  /*!< CRYPTO_AESCONTROL_NKKEY1                                                  */
48454   CRYPTO_AESCONTROL_NKKEY1_128_BITS_KEY = 0,    /*!< 128_BITS_KEY : 128 bits key                                               */
48455   CRYPTO_AESCONTROL_NKKEY1_192_BITS_KEY = 1,    /*!< 192_BITS_KEY : 192 bits key                                               */
48456   CRYPTO_AESCONTROL_NKKEY1_256_BITS_KEY = 2,    /*!< 256_BITS_KEY : 256 bits key                                               */
48457   CRYPTO_AESCONTROL_NKKEY1_N_A         = 3,     /*!< N_A : Not applicable                                                      */
48458 } CRYPTO_AESCONTROL_NKKEY1_Enum;
48459 
48460 /* ===========================================  CRYPTO AESCONTROL NKKEY0 [12..13]  =========================================== */
48461 typedef enum {                                  /*!< CRYPTO_AESCONTROL_NKKEY0                                                  */
48462   CRYPTO_AESCONTROL_NKKEY0_128_BITS_KEY = 0,    /*!< 128_BITS_KEY : 128 bits key                                               */
48463   CRYPTO_AESCONTROL_NKKEY0_192_BITS_KEY = 1,    /*!< 192_BITS_KEY : 192 bits key                                               */
48464   CRYPTO_AESCONTROL_NKKEY0_256_BITS_KEY = 2,    /*!< 256_BITS_KEY : 256 bits key                                               */
48465   CRYPTO_AESCONTROL_NKKEY0_N_A         = 3,     /*!< N_A : Not applicable                                                      */
48466 } CRYPTO_AESCONTROL_NKKEY0_Enum;
48467 
48468 /* =======================================  CRYPTO AESCONTROL AESTUNNELISON [10..10]  ======================================== */
48469 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNELISON                                           */
48470   CRYPTO_AESCONTROL_AESTUNNELISON_STD_NONTUNNEL = 0,/*!< STD_NONTUNNEL : standard non-tunneling operations                     */
48471   CRYPTO_AESCONTROL_AESTUNNELISON_TUNNEL = 1,   /*!< TUNNEL : tunneling operations.                                            */
48472 } CRYPTO_AESCONTROL_AESTUNNELISON_Enum;
48473 
48474 /* ===========================================  CRYPTO AESCONTROL MODEKEY1 [5..7]  =========================================== */
48475 typedef enum {                                  /*!< CRYPTO_AESCONTROL_MODEKEY1                                                */
48476   CRYPTO_AESCONTROL_MODEKEY1_ECB       = 0,     /*!< ECB : ECB modekey1                                                        */
48477   CRYPTO_AESCONTROL_MODEKEY1_CBC       = 1,     /*!< CBC : CBC modekey1                                                        */
48478   CRYPTO_AESCONTROL_MODEKEY1_CTR       = 2,     /*!< CTR : CTR modekey1                                                        */
48479   CRYPTO_AESCONTROL_MODEKEY1_CBC_MAC   = 3,     /*!< CBC_MAC : CBC MAC modekey1                                                */
48480   CRYPTO_AESCONTROL_MODEKEY1_XEX_XTS   = 4,     /*!< XEX_XTS : XEX_XTS modekey1                                                */
48481   CRYPTO_AESCONTROL_MODEKEY1_XCBC_MAC  = 5,     /*!< XCBC_MAC : XCBC MAC modekey1                                              */
48482   CRYPTO_AESCONTROL_MODEKEY1_OFB       = 6,     /*!< OFB : OFB modekey1                                                        */
48483   CRYPTO_AESCONTROL_MODEKEY1_CMAC      = 7,     /*!< CMAC : CMAC modekey1                                                      */
48484 } CRYPTO_AESCONTROL_MODEKEY1_Enum;
48485 
48486 /* ===========================================  CRYPTO AESCONTROL MODEKEY0 [2..4]  =========================================== */
48487 typedef enum {                                  /*!< CRYPTO_AESCONTROL_MODEKEY0                                                */
48488   CRYPTO_AESCONTROL_MODEKEY0_ECB       = 0,     /*!< ECB : ECB modekey0                                                        */
48489   CRYPTO_AESCONTROL_MODEKEY0_CBC       = 1,     /*!< CBC : CBC modekey0                                                        */
48490   CRYPTO_AESCONTROL_MODEKEY0_CTR       = 2,     /*!< CTR : CTR modekey0                                                        */
48491   CRYPTO_AESCONTROL_MODEKEY0_CBCMAC    = 3,     /*!< CBCMAC : CBCMAC modekey0                                                  */
48492   CRYPTO_AESCONTROL_MODEKEY0_XEX_XTS   = 4,     /*!< XEX_XTS : XEX XTS modekey0                                                */
48493   CRYPTO_AESCONTROL_MODEKEY0_XCBC_MAC  = 5,     /*!< XCBC_MAC : XCBC MAC modekey0                                              */
48494   CRYPTO_AESCONTROL_MODEKEY0_OFB       = 6,     /*!< OFB : OFB modekey0                                                        */
48495   CRYPTO_AESCONTROL_MODEKEY0_CMAC      = 7,     /*!< CMAC : CMAC modekey0                                                      */
48496 } CRYPTO_AESCONTROL_MODEKEY0_Enum;
48497 
48498 /* ===========================================  CRYPTO AESCONTROL DECKEY0 [0..0]  ============================================ */
48499 typedef enum {                                  /*!< CRYPTO_AESCONTROL_DECKEY0                                                 */
48500   CRYPTO_AESCONTROL_DECKEY0_ENCRYPT    = 0,     /*!< ENCRYPT : Encrypt                                                         */
48501   CRYPTO_AESCONTROL_DECKEY0_DECRYPT    = 1,     /*!< DECRYPT : Decrypt                                                         */
48502 } CRYPTO_AESCONTROL_DECKEY0_Enum;
48503 
48504 /* ======================================================  AESHWFLAGS  ======================================================= */
48505 /* ===================================================  AESCTRNOINCREMENT  =================================================== */
48506 /* ======================================================  AESDFAISON  ======================================================= */
48507 /* ====================================================  AESDFAERRSTATUS  ==================================================== */
48508 /* ===================================================  AESCMACSIZE0KICK  ==================================================== */
48509 /* ========================================================  HASHH0  ========================================================= */
48510 /* ========================================================  HASHH1  ========================================================= */
48511 /* ========================================================  HASHH2  ========================================================= */
48512 /* ========================================================  HASHH3  ========================================================= */
48513 /* ========================================================  HASHH4  ========================================================= */
48514 /* ========================================================  HASHH5  ========================================================= */
48515 /* ========================================================  HASHH6  ========================================================= */
48516 /* ========================================================  HASHH7  ========================================================= */
48517 /* ========================================================  HASHH8  ========================================================= */
48518 /* =====================================================  AUTOHWPADDING  ===================================================== */
48519 /* ======================================================  HASHXORDIN  ======================================================= */
48520 /* =====================================================  LOADINITSTATE  ===================================================== */
48521 /* =====================================================  HASHSELAESMAC  ===================================================== */
48522 /* =========================================  CRYPTO HASHSELAESMAC GHASHSEL [1..1]  ========================================== */
48523 typedef enum {                                  /*!< CRYPTO_HASHSELAESMAC_GHASHSEL                                             */
48524   CRYPTO_HASHSELAESMAC_GHASHSEL_HASH_MOD = 0,   /*!< HASH_MOD : select the hash module                                         */
48525   CRYPTO_HASHSELAESMAC_GHASHSEL_GHASH_MOD = 1,  /*!< GHASH_MOD : select the ghash module                                       */
48526 } CRYPTO_HASHSELAESMAC_GHASHSEL_Enum;
48527 
48528 /* =======================================  CRYPTO HASHSELAESMAC HASHSELAESMAC [0..0]  ======================================= */
48529 typedef enum {                                  /*!< CRYPTO_HASHSELAESMAC_HASHSELAESMAC                                        */
48530   CRYPTO_HASHSELAESMAC_HASHSELAESMAC_HASH_MOD = 0,/*!< HASH_MOD : select the hash module                                       */
48531   CRYPTO_HASHSELAESMAC_HASHSELAESMAC_MAC_MOD = 1,/*!< MAC_MOD : select the AES mac module                                      */
48532 } CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Enum;
48533 
48534 /* ======================================================  HASHVERSION  ====================================================== */
48535 /* ======================================================  HASHCONTROL  ====================================================== */
48536 /* ===========================================  CRYPTO HASHCONTROL MODE01 [0..1]  ============================================ */
48537 typedef enum {                                  /*!< CRYPTO_HASHCONTROL_MODE01                                                 */
48538   CRYPTO_HASHCONTROL_MODE01_MD5        = 0,     /*!< MD5 : MD5 if present                                                      */
48539   CRYPTO_HASHCONTROL_MODE01_SHA_1      = 1,     /*!< SHA_1 : SHA-1                                                             */
48540   CRYPTO_HASHCONTROL_MODE01_SHA_256    = 2,     /*!< SHA_256 : SHA-256                                                         */
48541 } CRYPTO_HASHCONTROL_MODE01_Enum;
48542 
48543 /* =======================================================  HASHPADEN  ======================================================= */
48544 /* ======================================================  HASHPADCFG  ======================================================= */
48545 /* ======================================================  HASHCURLEN0  ====================================================== */
48546 /* ======================================================  HASHCURLEN1  ====================================================== */
48547 /* =======================================================  HASHPARAM  ======================================================= */
48548 /* ====================================================  HASHAESSWRESET  ===================================================== */
48549 /* =====================================================  HASHENDIANESS  ===================================================== */
48550 /* =====================================================  AESCLKENABLE  ====================================================== */
48551 /* =============================================  CRYPTO AESCLKENABLE EN [0..0]  ============================================= */
48552 typedef enum {                                  /*!< CRYPTO_AESCLKENABLE_EN                                                    */
48553   CRYPTO_AESCLKENABLE_EN_CLK_E         = 1,     /*!< CLK_E : the AES clock is enabled.                                         */
48554   CRYPTO_AESCLKENABLE_EN_CLK_D         = 0,     /*!< CLK_D : the AES clock is disabled.                                        */
48555 } CRYPTO_AESCLKENABLE_EN_Enum;
48556 
48557 /* =====================================================  HASHCLKENABLE  ===================================================== */
48558 /* ============================================  CRYPTO HASHCLKENABLE EN [0..0]  ============================================= */
48559 typedef enum {                                  /*!< CRYPTO_HASHCLKENABLE_EN                                                   */
48560   CRYPTO_HASHCLKENABLE_EN_HASH_E       = 1,     /*!< HASH_E : the HASH clock is enabled.                                       */
48561   CRYPTO_HASHCLKENABLE_EN_HASH_D       = 0,     /*!< HASH_D : the HASH clock is disabled.                                      */
48562 } CRYPTO_HASHCLKENABLE_EN_Enum;
48563 
48564 /* =====================================================  PKACLKENABLE  ====================================================== */
48565 /* =============================================  CRYPTO PKACLKENABLE EN [0..0]  ============================================= */
48566 typedef enum {                                  /*!< CRYPTO_PKACLKENABLE_EN                                                    */
48567   CRYPTO_PKACLKENABLE_EN_PKA_E         = 1,     /*!< PKA_E : the PKA clock is enabled.                                         */
48568   CRYPTO_PKACLKENABLE_EN_PKA_D         = 0,     /*!< PKA_D : the PKA clock is disabled.                                        */
48569 } CRYPTO_PKACLKENABLE_EN_Enum;
48570 
48571 /* =====================================================  DMACLKENABLE  ====================================================== */
48572 /* =============================================  CRYPTO DMACLKENABLE EN [0..0]  ============================================= */
48573 typedef enum {                                  /*!< CRYPTO_DMACLKENABLE_EN                                                    */
48574   CRYPTO_DMACLKENABLE_EN_DMA_E         = 1,     /*!< DMA_E : the DMA clock is enabled.                                         */
48575   CRYPTO_DMACLKENABLE_EN_DMA_D         = 0,     /*!< DMA_D : the DMA clock is disabled.                                        */
48576 } CRYPTO_DMACLKENABLE_EN_Enum;
48577 
48578 /* =======================================================  CLKSTATUS  ======================================================= */
48579 /* =========================================  CRYPTO CLKSTATUS DMACLKSTATUS [8..8]  ========================================== */
48580 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_DMACLKSTATUS                                             */
48581   CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_E  = 1,     /*!< DMA_E : the DMA clock is enabled.                                         */
48582   CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_D  = 0,     /*!< DMA_D : the DMA clock is disabled.                                        */
48583 } CRYPTO_CLKSTATUS_DMACLKSTATUS_Enum;
48584 
48585 /* ========================================  CRYPTO CLKSTATUS CHACHACLKSTATUS [7..7]  ======================================== */
48586 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_CHACHACLKSTATUS                                          */
48587   CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_E = 1,/*!< CHACHA_E : the CHACHA clock is enabled.                                   */
48588   CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_D = 0,/*!< CHACHA_D : the CHACHA clock is disabled.                                  */
48589 } CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Enum;
48590 
48591 /* =========================================  CRYPTO CLKSTATUS PKACLKSTATUS [3..3]  ========================================== */
48592 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_PKACLKSTATUS                                             */
48593   CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_E  = 1,     /*!< PKA_E : the PKA clock is enabled.                                         */
48594   CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_D  = 0,     /*!< PKA_D : the PKA clock is disabled.                                        */
48595 } CRYPTO_CLKSTATUS_PKACLKSTATUS_Enum;
48596 
48597 /* =========================================  CRYPTO CLKSTATUS HASHCLKSTATUS [2..2]  ========================================= */
48598 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_HASHCLKSTATUS                                            */
48599   CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_E = 1,    /*!< HASH_E : the HASH clock is enabled.                                       */
48600   CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_D = 0,    /*!< HASH_D : the HASH clock is disabled.                                      */
48601 } CRYPTO_CLKSTATUS_HASHCLKSTATUS_Enum;
48602 
48603 /* =========================================  CRYPTO CLKSTATUS AESCLKSTATUS [0..0]  ========================================== */
48604 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_AESCLKSTATUS                                             */
48605   CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_E  = 1,     /*!< CLK_E : the AES clock is enabled.                                         */
48606   CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_D  = 0,     /*!< CLK_D : the AES clock is disabled.                                        */
48607 } CRYPTO_CLKSTATUS_AESCLKSTATUS_Enum;
48608 
48609 /* ====================================================  CHACHACLKENABLE  ==================================================== */
48610 /* ===========================================  CRYPTO CHACHACLKENABLE EN [0..0]  ============================================ */
48611 typedef enum {                                  /*!< CRYPTO_CHACHACLKENABLE_EN                                                 */
48612   CRYPTO_CHACHACLKENABLE_EN_CHACHA_E   = 1,     /*!< CHACHA_E : the CHACHA SALSA clock is enabled.                             */
48613   CRYPTO_CHACHACLKENABLE_EN_CHACHA_D   = 0,     /*!< CHACHA_D : the CHACHA SALSA clock is disabled.                            */
48614 } CRYPTO_CHACHACLKENABLE_EN_Enum;
48615 
48616 /* =======================================================  CRYPTOCTL  ======================================================= */
48617 /* =============================================  CRYPTO CRYPTOCTL MODE [0..4]  ============================================== */
48618 typedef enum {                                  /*!< CRYPTO_CRYPTOCTL_MODE                                                     */
48619   CRYPTO_CRYPTOCTL_MODE_BYPASS         = 0,     /*!< BYPASS : bypass                                                           */
48620   CRYPTO_CRYPTOCTL_MODE_AES            = 1,     /*!< AES : aes                                                                 */
48621   CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH    = 2,     /*!< AES_TO_HASH : aes to hash                                                 */
48622   CRYPTO_CRYPTOCTL_MODE_AES_AND_HASH   = 3,     /*!< AES_AND_HASH : aes and hash                                               */
48623   CRYPTO_CRYPTOCTL_MODE_DES            = 4,     /*!< DES : des                                                                 */
48624   CRYPTO_CRYPTOCTL_MODE_DES_TO_HASH    = 5,     /*!< DES_TO_HASH : des to hash                                                 */
48625   CRYPTO_CRYPTOCTL_MODE_DES_AND_HASH   = 6,     /*!< DES_AND_HASH : des and hash                                               */
48626   CRYPTO_CRYPTOCTL_MODE_HASH           = 7,     /*!< HASH : hash                                                               */
48627   CRYPTO_CRYPTOCTL_MODE_AES_MAC_AND_BYPASS = 9, /*!< AES_MAC_AND_BYPASS : aes mac and bypass                                   */
48628   CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH_AND_DOUT = 10,/*!< AES_TO_HASH_AND_DOUT : aes to hash and _dout                            */
48629   CRYPTO_CRYPTOCTL_MODE_Reserved1      = 11,    /*!< Reserved1 : reserved1                                                     */
48630   CRYPTO_CRYPTOCTL_MODE_Reserved2      = 8,     /*!< Reserved2 : reserved2                                                     */
48631 } CRYPTO_CRYPTOCTL_MODE_Enum;
48632 
48633 /* ======================================================  CRYPTOBUSY  ======================================================= */
48634 /* ==========================================  CRYPTO CRYPTOBUSY CRYPTOBUSY [0..0]  ========================================== */
48635 typedef enum {                                  /*!< CRYPTO_CRYPTOBUSY_CRYPTOBUSY                                              */
48636   CRYPTO_CRYPTOBUSY_CRYPTOBUSY_READY   = 0,     /*!< READY : Ready                                                             */
48637   CRYPTO_CRYPTOBUSY_CRYPTOBUSY_BUSY    = 1,     /*!< BUSY : Busy                                                               */
48638 } CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Enum;
48639 
48640 /* =======================================================  HASHBUSY  ======================================================== */
48641 /* ============================================  CRYPTO HASHBUSY HASHBUSY [0..0]  ============================================ */
48642 typedef enum {                                  /*!< CRYPTO_HASHBUSY_HASHBUSY                                                  */
48643   CRYPTO_HASHBUSY_HASHBUSY_READY       = 0,     /*!< READY : Ready                                                             */
48644   CRYPTO_HASHBUSY_HASHBUSY_BUSY        = 1,     /*!< BUSY : Busy                                                               */
48645 } CRYPTO_HASHBUSY_HASHBUSY_Enum;
48646 
48647 /* =======================================================  CONTEXTID  ======================================================= */
48648 /* =====================================================  GHASHSUBKEY00  ===================================================== */
48649 /* =====================================================  GHASHSUBKEY01  ===================================================== */
48650 /* =====================================================  GHASHSUBKEY02  ===================================================== */
48651 /* =====================================================  GHASHSUBKEY03  ===================================================== */
48652 /* =======================================================  GHASHIV00  ======================================================= */
48653 /* =======================================================  GHASHIV01  ======================================================= */
48654 /* =======================================================  GHASHIV02  ======================================================= */
48655 /* =======================================================  GHASHIV03  ======================================================= */
48656 /* =======================================================  GHASHBUSY  ======================================================= */
48657 /* =======================================================  GHASHINIT  ======================================================= */
48658 /* ======================================================  HOSTRGFIRR  ======================================================= */
48659 /* ======================================================  HOSTRGFIMR  ======================================================= */
48660 /* ======================================================  HOSTRGFICR  ======================================================= */
48661 /* =====================================================  HOSTRGFENDIAN  ===================================================== */
48662 /* ========================================  CRYPTO HOSTRGFENDIAN DINRDWBG [15..15]  ========================================= */
48663 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DINRDWBG                                             */
48664   CRYPTO_HOSTRGFENDIAN_DINRDWBG_LE     = 0,     /*!< LE : little endian                                                        */
48665   CRYPTO_HOSTRGFENDIAN_DINRDWBG_BE     = 1,     /*!< BE : big endian                                                           */
48666 } CRYPTO_HOSTRGFENDIAN_DINRDWBG_Enum;
48667 
48668 /* ========================================  CRYPTO HOSTRGFENDIAN DOUTWRWBG [11..11]  ======================================== */
48669 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DOUTWRWBG                                            */
48670   CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_LE    = 0,     /*!< LE : little endian                                                        */
48671   CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_BE    = 1,     /*!< BE : big endian                                                           */
48672 } CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Enum;
48673 
48674 /* ==========================================  CRYPTO HOSTRGFENDIAN DINRDBG [7..7]  ========================================== */
48675 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DINRDBG                                              */
48676   CRYPTO_HOSTRGFENDIAN_DINRDBG_LE      = 0,     /*!< LE : little endian                                                        */
48677   CRYPTO_HOSTRGFENDIAN_DINRDBG_BE      = 1,     /*!< BE : big endian                                                           */
48678 } CRYPTO_HOSTRGFENDIAN_DINRDBG_Enum;
48679 
48680 /* =========================================  CRYPTO HOSTRGFENDIAN DOUTWRBG [3..3]  ========================================== */
48681 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DOUTWRBG                                             */
48682   CRYPTO_HOSTRGFENDIAN_DOUTWRBG_LE     = 0,     /*!< LE : little endian                                                        */
48683   CRYPTO_HOSTRGFENDIAN_DOUTWRBG_BE     = 1,     /*!< BE : big endian                                                           */
48684 } CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Enum;
48685 
48686 /* ===================================================  HOSTRGFSIGNATURE  ==================================================== */
48687 /* =======================================================  HOSTBOOT  ======================================================== */
48688 /* ===================================================  HOSTCRYPTOKEYSEL  ==================================================== */
48689 /* ======================================  CRYPTO HOSTCRYPTOKEYSEL SELCRYPTOKEY [0..2]  ====================================== */
48690 typedef enum {                                  /*!< CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY                                      */
48691   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_RKEK = 0,/*!< RKEK : rkek                                                               */
48692   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Krtl = 1,/*!< Krtl : the Krtl.                                                          */
48693   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCP = 2, /*!< KCP : the provision key KCP.                                              */
48694   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCE = 3, /*!< KCE : the code encryption key KCE.                                        */
48695   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KPICV = 4,/*!< KPICV : the KPICV, The ICV provisioning key .                            */
48696   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCEICV = 5,/*!< KCEICV : the code encryption key KCEICV Note: When 'kprtl_lock'
48697                                                      is set - kprtl will be masked (trying to load it will load
48698                                                      zeros to the AES key register. When 'kcertl_lock' is set
48699                                                      - kcertl will be masked (trying to load it will load zeros
48700                                                      to the AES key register. When scan_mode is asserted all
48701                                                      the RTL keys (Krtll) will be masked.                                      */
48702 } CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Enum;
48703 
48704 /* ================================================  HOSTCORECLKGATINGENABLE  ================================================ */
48705 /* =====================================================  HOSTCCISIDLE  ====================================================== */
48706 /* =====================================================  HOSTPOWERDOWN  ===================================================== */
48707 /* =================================================  HOSTREMOVEGHASHENGINE  ================================================= */
48708 /* ================================================  HOSTREMOVECHACHAENGINE  ================================================= */
48709 /* ======================================================  AHBMSINGLES  ====================================================== */
48710 /* =======================================================  AHBMHPROT  ======================================================= */
48711 /* =====================================================  AHBMHMASTLOCK  ===================================================== */
48712 /* ======================================================  AHBMHNONSEC  ====================================================== */
48713 /* =======================================================  DINBUFFER  ======================================================= */
48714 /* =====================================================  DINMEMDMABUSY  ===================================================== */
48715 /* =======================================  CRYPTO DINMEMDMABUSY DINMEMDMABUSY [0..0]  ======================================= */
48716 typedef enum {                                  /*!< CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY                                        */
48717   CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_busy = 1,  /*!< busy : DMA busy                                                           */
48718   CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_not = 0,   /*!< not : DMA not busy                                                        */
48719 } CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Enum;
48720 
48721 /* ======================================================  SRCLLIWORD0  ====================================================== */
48722 /* ======================================================  SRCLLIWORD1  ====================================================== */
48723 /* ======================================================  SRAMSRCADDR  ====================================================== */
48724 /* ====================================================  DINSRAMBYTESLEN  ==================================================== */
48725 /* ====================================================  DINSRAMDMABUSY  ===================================================== */
48726 /* ===========================================  CRYPTO DINSRAMDMABUSY BUSY [0..0]  =========================================== */
48727 typedef enum {                                  /*!< CRYPTO_DINSRAMDMABUSY_BUSY                                                */
48728   CRYPTO_DINSRAMDMABUSY_BUSY_BUSY      = 1,     /*!< BUSY : busy                                                               */
48729   CRYPTO_DINSRAMDMABUSY_BUSY_NOT_BUSY  = 0,     /*!< NOT_BUSY : not busy                                                       */
48730 } CRYPTO_DINSRAMDMABUSY_BUSY_Enum;
48731 
48732 /* ===================================================  DINSRAMENDIANNESS  =================================================== */
48733 /* ===================================  CRYPTO DINSRAMENDIANNESS SRAMDINENDIANNESS [0..0]  =================================== */
48734 typedef enum {                                  /*!< CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS                                */
48735   CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_BE = 1,/*!< BE : big-endianness                                                   */
48736   CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_LE = 0,/*!< LE : little endianness                                                */
48737 } CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Enum;
48738 
48739 /* ====================================================  DINCPUDATASIZE  ===================================================== */
48740 /* ======================================================  FIFOINEMPTY  ====================================================== */
48741 /* ====================================================  DINFIFORSTPNTR  ===================================================== */
48742 /* ======================================================  DOUTBUFFER  ======================================================= */
48743 /* ====================================================  DOUTMEMDMABUSY  ===================================================== */
48744 /* ======================================  CRYPTO DOUTMEMDMABUSY DOUTMEMDMABUSY [0..0]  ====================================== */
48745 typedef enum {                                  /*!< CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY                                      */
48746   CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_BUSY = 1,/*!< BUSY : busy                                                               */
48747   CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_NOT_BUSY = 0,/*!< NOT_BUSY : not busy                                                   */
48748 } CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Enum;
48749 
48750 /* ======================================================  DSTLLIWORD0  ====================================================== */
48751 /* ======================================================  DSTLLIWORD1  ====================================================== */
48752 /* =====================================================  SRAMDESTADDR  ====================================================== */
48753 /* ===================================================  DOUTSRAMBYTESLEN  ==================================================== */
48754 /* ====================================================  DOUTSRAMDMABUSY  ==================================================== */
48755 /* ==========================================  CRYPTO DOUTSRAMDMABUSY BUSY [0..0]  =========================================== */
48756 typedef enum {                                  /*!< CRYPTO_DOUTSRAMDMABUSY_BUSY                                               */
48757   CRYPTO_DOUTSRAMDMABUSY_BUSY_DATA_SRAM = 0,    /*!< DATA_SRAM : all data was written to SRAM.                                 */
48758   CRYPTO_DOUTSRAMDMABUSY_BUSY_DMA_BUSY = 1,     /*!< DMA_BUSY : DOUT SRAM DMA busy.                                            */
48759 } CRYPTO_DOUTSRAMDMABUSY_BUSY_Enum;
48760 
48761 /* ==================================================  DOUTSRAMENDIANNESS  =================================================== */
48762 /* ==================================  CRYPTO DOUTSRAMENDIANNESS DOUTSRAMENDIANNESS [0..0]  ================================== */
48763 typedef enum {                                  /*!< CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS                              */
48764   CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_BE = 1,/*!< BE : big-endianness                                                 */
48765   CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_LE = 0,/*!< LE : little endianness                                              */
48766 } CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Enum;
48767 
48768 /* =====================================================  READALIGNLAST  ===================================================== */
48769 /* =====================================================  DOUTFIFOEMPTY  ===================================================== */
48770 /* =======================================  CRYPTO DOUTFIFOEMPTY DOUTFIFOEMPTY [0..0]  ======================================= */
48771 typedef enum {                                  /*!< CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY                                        */
48772   CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_NE = 0,/*!< FIFO_NE : DOUT FIFO is not empty                                         */
48773   CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_EDOUT = 1,/*!< FIFO_EDOUT : FIFO is empty                                            */
48774 } CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Enum;
48775 
48776 /* =======================================================  SRAMDATA  ======================================================== */
48777 /* =======================================================  SRAMADDR  ======================================================== */
48778 /* =====================================================  SRAMDATAREADY  ===================================================== */
48779 /* =====================================================  PERIPHERALID4  ===================================================== */
48780 /* =====================================================  PERIPHERALID0  ===================================================== */
48781 /* =====================================================  PERIPHERALID1  ===================================================== */
48782 /* =====================================================  PERIPHERALID2  ===================================================== */
48783 /* =====================================================  PERIPHERALID3  ===================================================== */
48784 /* =====================================================  COMPONENTID0  ====================================================== */
48785 /* =====================================================  COMPONENTID1  ====================================================== */
48786 /* =====================================================  COMPONENTID2  ====================================================== */
48787 /* =====================================================  COMPONENTID3  ====================================================== */
48788 /* ======================================================  HOSTDCUEN0  ======================================================= */
48789 /* ======================================================  HOSTDCUEN1  ======================================================= */
48790 /* ======================================================  HOSTDCUEN2  ======================================================= */
48791 /* ======================================================  HOSTDCUEN3  ======================================================= */
48792 /* =====================================================  HOSTDCULOCK0  ====================================================== */
48793 /* =====================================================  HOSTDCULOCK1  ====================================================== */
48794 /* =====================================================  HOSTDCULOCK2  ====================================================== */
48795 /* =====================================================  HOSTDCULOCK3  ====================================================== */
48796 /* ===============================================  AOICVDCURESTRICTIONMASK0  ================================================ */
48797 /* ===============================================  AOICVDCURESTRICTIONMASK1  ================================================ */
48798 /* ===============================================  AOICVDCURESTRICTIONMASK2  ================================================ */
48799 /* ===============================================  AOICVDCURESTRICTIONMASK3  ================================================ */
48800 /* ===================================================  AOCCSECDEBUGRESET  =================================================== */
48801 /* ====================================================  HOSTAOLOCKBITS  ===================================================== */
48802 /* ====================================================  AOAPBFILTERING  ===================================================== */
48803 /* =======================================================  AOCCGPPC  ======================================================== */
48804 /* ====================================================  HOSTRGFCCSWRST  ===================================================== */
48805 /* =================================================  AIBFUSEPROGCOMPLETED  ================================================== */
48806 /* ====================================================  NVMDEBUGSTATUS  ===================================================== */
48807 /* ==========================================  CRYPTO NVMDEBUGSTATUS NVMSM [1..3]  =========================================== */
48808 typedef enum {                                  /*!< CRYPTO_NVMDEBUGSTATUS_NVMSM                                               */
48809   CRYPTO_NVMDEBUGSTATUS_NVMSM_IDLE     = 0,     /*!< IDLE : IDLE NVMSM                                                         */
48810   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_DUMMY = 1,   /*!< READ_DUMMY : READ_DUMMY NVMSM                                             */
48811   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_MAN_FLAG = 2,/*!< READ_MAN_FLAG : READ_MAN_FLAG NVMSM                                       */
48812   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_OEM_FLAG = 3,/*!< READ_OEM_FLAG : READ_OEM_FLAG NVMSM                                       */
48813   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_GPPC = 4,    /*!< READ_GPPC : READ_GPPC NVMSM                                               */
48814   CRYPTO_NVMDEBUGSTATUS_NVMSM_DECODE   = 5,     /*!< DECODE : DECODE NVMSM                                                     */
48815   CRYPTO_NVMDEBUGSTATUS_NVMSM_OTP_LCS_VALID = 6,/*!< OTP_LCS_VALID : OTP_LCS_VALID NVMSM                                       */
48816   CRYPTO_NVMDEBUGSTATUS_NVMSM_LCS_IS_VALID = 7, /*!< LCS_IS_VALID : LCS_IS_VALID NVMSM                                         */
48817 } CRYPTO_NVMDEBUGSTATUS_NVMSM_Enum;
48818 
48819 /* ======================================================  LCSISVALID  ======================================================= */
48820 /* =======================================================  NVMISIDLE  ======================================================= */
48821 /* ========================================================  LCSREG  ========================================================= */
48822 /* ==============================================  CRYPTO LCSREG LCSREG [0..2]  ============================================== */
48823 typedef enum {                                  /*!< CRYPTO_LCSREG_LCSREG                                                      */
48824   CRYPTO_LCSREG_LCSREG_CM              = 0,     /*!< CM : CM lifecycle state                                                   */
48825   CRYPTO_LCSREG_LCSREG_DM              = 1,     /*!< DM : DM lifecycle state                                                   */
48826   CRYPTO_LCSREG_LCSREG_SE              = 5,     /*!< SE : SE lifecycle state                                                   */
48827   CRYPTO_LCSREG_LCSREG_RMA             = 7,     /*!< RMA : RMA lifecycle state                                                 */
48828 } CRYPTO_LCSREG_LCSREG_Enum;
48829 
48830 /* ===================================================  HOSTSHADOWKDRREG  ==================================================== */
48831 /* ===================================================  HOSTSHADOWKCPREG  ==================================================== */
48832 /* ===================================================  HOSTSHADOWKCEREG  ==================================================== */
48833 /* ==================================================  HOSTSHADOWKPICVREG  =================================================== */
48834 /* ==================================================  HOSTSHADOWKCEICVREG  ================================================== */
48835 /* ====================================================  OTPADDRWIDTHDEF  ==================================================== */
48836 
48837 
48838 /* =========================================================================================================================== */
48839 /* ================                                            DC                                             ================ */
48840 /* =========================================================================================================================== */
48841 
48842 /* =========================================================  MODE  ========================================================== */
48843 /* ===============================================  DC MODE VSYNCPOL [28..28]  =============================================== */
48844 typedef enum {                                  /*!< DC_MODE_VSYNCPOL                                                          */
48845   DC_MODE_VSYNCPOL_VSYNC_NEG           = 1,     /*!< VSYNC_NEG : VSYNC polarity is negative                                    */
48846   DC_MODE_VSYNCPOL_VSYNC_POS           = 0,     /*!< VSYNC_POS : VSYNC polarity is positive                                    */
48847 } DC_MODE_VSYNCPOL_Enum;
48848 
48849 /* ===============================================  DC MODE HSYNCPOL [27..27]  =============================================== */
48850 typedef enum {                                  /*!< DC_MODE_HSYNCPOL                                                          */
48851   DC_MODE_HSYNCPOL_HSYNC_NEG           = 1,     /*!< HSYNC_NEG : HSYNC polarity is negative                                    */
48852   DC_MODE_HSYNCPOL_HSYNC_POS           = 0,     /*!< HSYNC_POS : HSYNC polarity is positive                                    */
48853 } DC_MODE_HSYNCPOL_Enum;
48854 
48855 /* ================================================  DC MODE DEPOL [26..26]  ================================================= */
48856 typedef enum {                                  /*!< DC_MODE_DEPOL                                                             */
48857   DC_MODE_DEPOL_DE_NEG                 = 1,     /*!< DE_NEG : DE polarity is negative                                          */
48858   DC_MODE_DEPOL_DE_POS                 = 0,     /*!< DE_POS : DE polarity is positive                                          */
48859 } DC_MODE_DEPOL_Enum;
48860 
48861 /* ==============================================  DC MODE PIXCLKPOL [22..22]  =============================================== */
48862 typedef enum {                                  /*!< DC_MODE_PIXCLKPOL                                                         */
48863   DC_MODE_PIXCLKPOL_POL_NEG            = 1,     /*!< POL_NEG : Pixel Clock out polarity is negative                            */
48864   DC_MODE_PIXCLKPOL_POL_POS            = 0,     /*!< POL_POS : Pixel Clock out polarity is positive                            */
48865 } DC_MODE_PIXCLKPOL_Enum;
48866 
48867 /* =================================================  DC MODE COLFMT [9..9]  ================================================= */
48868 typedef enum {                                  /*!< DC_MODE_COLFMT                                                            */
48869   DC_MODE_COLFMT_YUV_EN                = 1,     /*!< YUV_EN : YUV/YCbCr format is enabled                                      */
48870   DC_MODE_COLFMT_RGB_EN                = 0,     /*!< RGB_EN : RGB format is enabled                                            */
48871 } DC_MODE_COLFMT_Enum;
48872 
48873 /* ================================================  DC MODE DISPFMT [5..8]  ================================================= */
48874 typedef enum {                                  /*!< DC_MODE_DISPFMT                                                           */
48875   DC_MODE_DISPFMT_DPI                  = 0,     /*!< DPI : DPI Interface                                                       */
48876   DC_MODE_DISPFMT_BYTE3                = 1,     /*!< BYTE3 : Byte-3 beat Interface                                             */
48877   DC_MODE_DISPFMT_BYTE4                = 2,     /*!< BYTE4 : Byte-4 beat (RGBX) Interface                                      */
48878   DC_MODE_DISPFMT_SERIAL               = 3,     /*!< SERIAL : Two phase serial 12-bit                                          */
48879   DC_MODE_DISPFMT_LVDS2                = 4,     /*!< LVDS2 : LVDS 24-bit unbalanced single pixel format 2                      */
48880   DC_MODE_DISPFMT_LVDS1                = 5,     /*!< LVDS1 : LVDS 24-bit unbalanced single pixel format 1                      */
48881   DC_MODE_DISPFMT_YUYV                 = 6,     /*!< YUYV : YUYV (16-bit mode)                                                 */
48882   DC_MODE_DISPFMT_BT656                = 7,     /*!< BT656 : BT.656                                                            */
48883   DC_MODE_DISPFMT_JDI                  = 8,     /*!< JDI : JDI MIP                                                             */
48884 } DC_MODE_DISPFMT_Enum;
48885 
48886 /* ========================================================  CLKCTRL  ======================================================== */
48887 /* =============================================  DC CLKCTRL SECCLKDIV [27..31]  ============================================= */
48888 typedef enum {                                  /*!< DC_CLKCTRL_SECCLKDIV                                                      */
48889   DC_CLKCTRL_SECCLKDIV_SDIV_0          = 0,     /*!< SDIV_0 : No division                                                      */
48890   DC_CLKCTRL_SECCLKDIV_SDIV_1          = 1,     /*!< SDIV_1 : No division                                                      */
48891   DC_CLKCTRL_SECCLKDIV_SDIV_2          = 2,     /*!< SDIV_2 : Divided by 2                                                     */
48892   DC_CLKCTRL_SECCLKDIV_SDIV_3          = 3,     /*!< SDIV_3 : Divided by 3                                                     */
48893   DC_CLKCTRL_SECCLKDIV_SDIV_4          = 4,     /*!< SDIV_4 : Divided by 4                                                     */
48894   DC_CLKCTRL_SECCLKDIV_SDIV_5          = 5,     /*!< SDIV_5 : Divided by 5                                                     */
48895   DC_CLKCTRL_SECCLKDIV_SDIV_6          = 6,     /*!< SDIV_6 : Divided by 6                                                     */
48896   DC_CLKCTRL_SECCLKDIV_SDIV_7          = 7,     /*!< SDIV_7 : Divided by 7                                                     */
48897   DC_CLKCTRL_SECCLKDIV_SDIV_8          = 8,     /*!< SDIV_8 : Divided by 8                                                     */
48898   DC_CLKCTRL_SECCLKDIV_SDIV_9          = 9,     /*!< SDIV_9 : Divided by 9                                                     */
48899   DC_CLKCTRL_SECCLKDIV_SDIV_10         = 10,    /*!< SDIV_10 : Divided by 10                                                   */
48900   DC_CLKCTRL_SECCLKDIV_SDIV_11         = 11,    /*!< SDIV_11 : Divided by 11                                                   */
48901   DC_CLKCTRL_SECCLKDIV_SDIV_12         = 12,    /*!< SDIV_12 : Divided by 12                                                   */
48902   DC_CLKCTRL_SECCLKDIV_SDIV_13         = 13,    /*!< SDIV_13 : Divided by 13                                                   */
48903   DC_CLKCTRL_SECCLKDIV_SDIV_14         = 14,    /*!< SDIV_14 : Divided by 14                                                   */
48904   DC_CLKCTRL_SECCLKDIV_SDIV_15         = 15,    /*!< SDIV_15 : Divided by 15                                                   */
48905 } DC_CLKCTRL_SECCLKDIV_Enum;
48906 
48907 /* =============================================  DC CLKCTRL DIVIDEVALUE [0..5]  ============================================= */
48908 typedef enum {                                  /*!< DC_CLKCTRL_DIVIDEVALUE                                                    */
48909   DC_CLKCTRL_DIVIDEVALUE_FDIV_0        = 0,     /*!< FDIV_0 : Divided by 0                                                     */
48910   DC_CLKCTRL_DIVIDEVALUE_FDIV_2        = 2,     /*!< FDIV_2 : Divided by 2                                                     */
48911   DC_CLKCTRL_DIVIDEVALUE_FDIV_3        = 3,     /*!< FDIV_3 : Divided by 3                                                     */
48912   DC_CLKCTRL_DIVIDEVALUE_FDIV_4        = 4,     /*!< FDIV_4 : Divided by 4                                                     */
48913   DC_CLKCTRL_DIVIDEVALUE_FDIV_5        = 5,     /*!< FDIV_5 : Divided by 5                                                     */
48914   DC_CLKCTRL_DIVIDEVALUE_FDIV_6        = 6,     /*!< FDIV_6 : Divided by 6                                                     */
48915   DC_CLKCTRL_DIVIDEVALUE_FDIV_7        = 7,     /*!< FDIV_7 : Divided by 7                                                     */
48916   DC_CLKCTRL_DIVIDEVALUE_FDIV_8        = 8,     /*!< FDIV_8 : Divided by 8                                                     */
48917   DC_CLKCTRL_DIVIDEVALUE_FDIV_9        = 9,     /*!< FDIV_9 : Divided by 9                                                     */
48918   DC_CLKCTRL_DIVIDEVALUE_FDIV_10       = 10,    /*!< FDIV_10 : Divided by 10                                                   */
48919   DC_CLKCTRL_DIVIDEVALUE_FDIV_11       = 11,    /*!< FDIV_11 : Divided by 11                                                   */
48920   DC_CLKCTRL_DIVIDEVALUE_FDIV_12       = 12,    /*!< FDIV_12 : Divided by 12                                                   */
48921   DC_CLKCTRL_DIVIDEVALUE_FDIV_13       = 13,    /*!< FDIV_13 : Divided by 13                                                   */
48922   DC_CLKCTRL_DIVIDEVALUE_FDIV_14       = 14,    /*!< FDIV_14 : Divided by 14                                                   */
48923   DC_CLKCTRL_DIVIDEVALUE_FDIV_15       = 15,    /*!< FDIV_15 : Divided by 15                                                   */
48924   DC_CLKCTRL_DIVIDEVALUE_FDIV_16       = 16,    /*!< FDIV_16 : Divided by 16                                                   */
48925   DC_CLKCTRL_DIVIDEVALUE_FDIV_17       = 17,    /*!< FDIV_17 : Divided by 17                                                   */
48926   DC_CLKCTRL_DIVIDEVALUE_FDIV_18       = 18,    /*!< FDIV_18 : Divided by 18                                                   */
48927   DC_CLKCTRL_DIVIDEVALUE_FDIV_19       = 19,    /*!< FDIV_19 : Divided by 19                                                   */
48928   DC_CLKCTRL_DIVIDEVALUE_FDIV_20       = 20,    /*!< FDIV_20 : Divided by 20                                                   */
48929   DC_CLKCTRL_DIVIDEVALUE_FDIV_21       = 21,    /*!< FDIV_21 : Divided by 21                                                   */
48930   DC_CLKCTRL_DIVIDEVALUE_FDIV_22       = 22,    /*!< FDIV_22 : Divided by 22                                                   */
48931   DC_CLKCTRL_DIVIDEVALUE_FDIV_23       = 23,    /*!< FDIV_23 : Divided by 23                                                   */
48932   DC_CLKCTRL_DIVIDEVALUE_FDIV_24       = 24,    /*!< FDIV_24 : Divided by 24                                                   */
48933   DC_CLKCTRL_DIVIDEVALUE_FDIV_25       = 25,    /*!< FDIV_25 : Divided by 25                                                   */
48934   DC_CLKCTRL_DIVIDEVALUE_FDIV_26       = 26,    /*!< FDIV_26 : Divided by 26                                                   */
48935   DC_CLKCTRL_DIVIDEVALUE_FDIV_27       = 27,    /*!< FDIV_27 : Divided by 27                                                   */
48936   DC_CLKCTRL_DIVIDEVALUE_FDIV_28       = 28,    /*!< FDIV_28 : Divided by 28                                                   */
48937   DC_CLKCTRL_DIVIDEVALUE_FDIV_29       = 29,    /*!< FDIV_29 : Divided by 29                                                   */
48938   DC_CLKCTRL_DIVIDEVALUE_FDIV_30       = 30,    /*!< FDIV_30 : Divided by 30                                                   */
48939   DC_CLKCTRL_DIVIDEVALUE_FDIV_31       = 31,    /*!< FDIV_31 : Divided by 31                                                   */
48940 } DC_CLKCTRL_DIVIDEVALUE_Enum;
48941 
48942 /* ========================================================  BGCOLOR  ======================================================== */
48943 /* =========================================================  RESXY  ========================================================= */
48944 /* =====================================================  FRONTPORCHXY  ====================================================== */
48945 /* ======================================================  BLANKINGXY  ======================================================= */
48946 /* ======================================================  BACKPORCHXY  ====================================================== */
48947 /* =======================================================  CURSORXY  ======================================================== */
48948 /* ========================================================  DBICFG  ========================================================= */
48949 /* ===============================================  DC DBICFG CSXSET [29..29]  =============================================== */
48950 typedef enum {                                  /*!< DC_DBICFG_CSXSET                                                          */
48951   DC_DBICFG_CSXSET_CSX1                = 1,     /*!< CSX1 : is set to one if DBI_CFG[29] has the value of one                  */
48952   DC_DBICFG_CSXSET_CSX0                = 0,     /*!< CSX0 : is set to zero if DBI_CFG[29] has the value of zero                */
48953 } DC_DBICFG_CSXSET_Enum;
48954 
48955 /* ==============================================  DC DBICFG TYPEBWIDTH [6..7]  ============================================== */
48956 typedef enum {                                  /*!< DC_DBICFG_TYPEBWIDTH                                                      */
48957   DC_DBICFG_TYPEBWIDTH_INT_16          = 0,     /*!< INT_16 : 16-bit interface                                                 */
48958   DC_DBICFG_TYPEBWIDTH_INT_9           = 1,     /*!< INT_9 : 9-bit interface                                                   */
48959   DC_DBICFG_TYPEBWIDTH_INT_8           = 2,     /*!< INT_8 : 8-bit interface                                                   */
48960   DC_DBICFG_TYPEBWIDTH_INT_SERIAL      = 3,     /*!< INT_SERIAL : Serial interface                                             */
48961 } DC_DBICFG_TYPEBWIDTH_Enum;
48962 
48963 /* =============================================  DC DBICFG DATAWDORDER [3..5]  ============================================== */
48964 typedef enum {                                  /*!< DC_DBICFG_DATAWDORDER                                                     */
48965   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT0  = 0,     /*!< WD_ORDER_OPT0 : option 0                                                  */
48966   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT1  = 1,     /*!< WD_ORDER_OPT1 : option 1                                                  */
48967   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT2  = 2,     /*!< WD_ORDER_OPT2 : option 2                                                  */
48968   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT3  = 3,     /*!< WD_ORDER_OPT3 : option 3                                                  */
48969 } DC_DBICFG_DATAWDORDER_Enum;
48970 
48971 /* =============================================  DC DBICFG DBICOLORFMT [0..2]  ============================================== */
48972 typedef enum {                                  /*!< DC_DBICFG_DBICOLORFMT                                                     */
48973   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB111 = 1,     /*!< DBI_FMT_RGB111 : RGB111 (3 bits/pixel)                                    */
48974   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB332 = 2,     /*!< DBI_FMT_RGB332 : RGB332 (8 bits/pixel)                                    */
48975   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB444 = 3,     /*!< DBI_FMT_RGB444 : RGB444 (12 bits/pixel)                                   */
48976   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB565 = 5,     /*!< DBI_FMT_RGB565 : RGB565 (16 bits/pixel)                                   */
48977   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB666 = 6,     /*!< DBI_FMT_RGB666 : RGB666 (18 bits/pixel)                                   */
48978   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB888 = 7,     /*!< DBI_FMT_RGB888 : RGB888 (24 bits/pixel)                                   */
48979 } DC_DBICFG_DBICOLORFMT_Enum;
48980 
48981 /* ========================================================  DCGPIO  ========================================================= */
48982 /* ======================================================  LAYER0MODE  ======================================================= */
48983 /* ==========================================  DC LAYER0MODE LAYER0DBLEND [12..15]  ========================================== */
48984 typedef enum {                                  /*!< DC_LAYER0MODE_LAYER0DBLEND                                                */
48985   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DBLACK_BLEND = 0,/*!< LAYER0_DBLACK_BLEND : blend black                                    */
48986   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DWHITE_BLEND = 1,/*!< LAYER0_DWHITE_BLEND : blend white                                    */
48987   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALBHAS_BLEND = 2,/*!< LAYER0_DALBHAS_BLEND : blend alpha source                           */
48988   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHAG_BLEND = 3,/*!< LAYER0_DALPHAG_BLEND : blend alpha global                           */
48989   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHASG_BLEND = 4,/*!< LAYER0_DALPHASG_BLEND : blend alpha source and alpha global        */
48990   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_BLEND_SRC = 5,/*!< LAYER0_DINVERT_BLEND_SRC : blend inverted source                */
48991   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER0_DINVERT_GLOBAL_BLEND : blend inverted global          */
48992   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERTSG_BLEND = 7,/*!< LAYER0_DINVERTSG_BLEND : blend inverted source and inverted
48993                                                      global                                                                    */
48994   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHA_BLEND = 10,/*!< LAYER0_DALPHA_BLEND : blend alpha destination                       */
48995   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_BLEND_DST = 13,/*!< LAYER0_DINVERT_BLEND_DST : blend inverted destination          */
48996 } DC_LAYER0MODE_LAYER0DBLEND_Enum;
48997 
48998 /* ==========================================  DC LAYER0MODE LAYER0SBLEND [8..11]  =========================================== */
48999 typedef enum {                                  /*!< DC_LAYER0MODE_LAYER0SBLEND                                                */
49000   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SBLACK_BLEND = 0,/*!< LAYER0_SBLACK_BLEND : blend black                                    */
49001   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SWHITE_BLEND = 1,/*!< LAYER0_SWHITE_BLEND : blend white                                    */
49002   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALBHAS_BLEND = 2,/*!< LAYER0_SALBHAS_BLEND : blend alpha source                           */
49003   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHAG_BLEND = 3,/*!< LAYER0_SALPHAG_BLEND : blend alpha global                           */
49004   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHASG_BLEND = 4,/*!< LAYER0_SALPHASG_BLEND : blend alpha source and alpha global        */
49005   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_BLEND_SRC = 5,/*!< LAYER0_SINVERT_BLEND_SRC : blend inverted source                */
49006   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_GLOBAL_BLEND = 6,/*!< LAYER0_SINVERT_GLOBAL_BLEND : blend inverted global          */
49007   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERTSG_BLEND = 7,/*!< LAYER0_SINVERTSG_BLEND : blend inverted source and inverted
49008                                                      global                                                                    */
49009   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHA_BLEND = 10,/*!< LAYER0_SALPHA_BLEND : blend alpha destination                       */
49010   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_BLEND_DST = 13,/*!< LAYER0_SINVERT_BLEND_DST : blend inverted destination          */
49011 } DC_LAYER0MODE_LAYER0SBLEND_Enum;
49012 
49013 /* ==========================================  DC LAYER0MODE LAYER0COLMODE [0..4]  =========================================== */
49014 typedef enum {                                  /*!< DC_LAYER0MODE_LAYER0COLMODE                                               */
49015   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_LUTBLE = 0,/*!< LAYER0CM_LUTBLE : 8-bit color palette look-up table (LUT8)              */
49016   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGBX5551 = 1,/*!< LAYER0CM_RGBX5551 : 16-bit RGBX5551 color format                      */
49017   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGBX8888 = 2,/*!< LAYER0CM_RGBX8888 : 32-bit RGBX8888 color format                      */
49018   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGB332 = 4,/*!< LAYER0CM_RGB332 : 8-bit RGB332 color format                             */
49019   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGB565 = 5,/*!< LAYER0CM_RGB565 : 16-bit RGB565 color format                            */
49020   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_XRGB8888 = 6,/*!< LAYER0CM_XRGB8888 : 32-bit XRGB8888 color format                      */
49021   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L8 = 7,  /*!< LAYER0CM_L8 : L8 Grayscale/Palette format                                 */
49022   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L1 = 8,  /*!< LAYER0CM_L1 : L1 Grayscale/Palette format                                 */
49023   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L4 = 9,  /*!< LAYER0CM_L4 : L4 Grayscale/Palette format                                 */
49024   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_YUYV = 10,/*!< LAYER0CM_YUYV : color format                                             */
49025   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RBG = 11,/*!< LAYER0CM_RBG : 24-bit RGB color format                                    */
49026   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_YUY2 = 12,/*!< LAYER0CM_YUY2 : YUY2 color format                                        */
49027   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_ABGR8888 = 13,/*!< LAYER0CM_ABGR8888 : 32-bit ABGR8888 color format                     */
49028   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_BGRA8888 = 14,/*!< LAYER0CM_BGRA8888 : 32-bit BGRA8888 color format                     */
49029   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_Video = 16,/*!< LAYER0CM_Video : Video 420 Mode                                         */
49030   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_Trilinear = 17,/*!< LAYER0CM_Trilinear : Trilinea 420 Video Mode                        */
49031 } DC_LAYER0MODE_LAYER0COLMODE_Enum;
49032 
49033 /* =====================================================  LAYER0STARTXY  ===================================================== */
49034 /* =====================================================  LAYER0SIZEXY  ====================================================== */
49035 /* ======================================================  LAYER0ADDR  ======================================================= */
49036 /* =====================================================  LAYER0STRIDE  ====================================================== */
49037 /* ======================================  DC LAYER0STRIDE LAYER0AXIFIFOTHLD [19..20]  ======================================= */
49038 typedef enum {                                  /*!< DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD                                         */
49039   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_HALF_SZ = 0,/*!< LAYER0_BURST_HALF_SZ : half fifo (default)                   */
49040   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_2 = 1,/*!< LAYER0_BURST_2 : 2 burst-size                                      */
49041   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_4 = 2,/*!< LAYER0_BURST_4 : 4 burst-size                                      */
49042   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_8 = 3,/*!< LAYER0_BURST_8 : 8 burst-size                                      */
49043 } DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_Enum;
49044 
49045 /* ======================================  DC LAYER0STRIDE LAYER0AXIBURSTBITS [16..18]  ====================================== */
49046 typedef enum {                                  /*!< DC_LAYER0STRIDE_LAYER0AXIBURSTBITS                                        */
49047   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_DEF = 0,/*!< LAYER0_BEATS_DEF : 16-beats (default)                           */
49048   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_2 = 1,/*!< LAYER0_BEATS_2 : 2-beats                                          */
49049   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_4 = 2,/*!< LAYER0_BEATS_4 : 4-beats                                          */
49050   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_8 = 3,/*!< LAYER0_BEATS_8 : 8-beats                                          */
49051   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_16 = 4,/*!< LAYER0_BEATS_16 : 16-beats (CHECK mistake?)                      */
49052   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_32 = 5,/*!< LAYER0_BEATS_32 : 32-beats (AXI4 only)                           */
49053   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_64 = 6,/*!< LAYER0_BEATS_64 : 64-beats (AXI4 only)                           */
49054   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_128 = 7,/*!< LAYER0_BEATS_128 : 128-beats (AXI4 only)                        */
49055 } DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_Enum;
49056 
49057 /* ======================================================  LAYER0RESXY  ====================================================== */
49058 /* =====================================================  LAYER0SCALEX  ====================================================== */
49059 /* =====================================================  LAYER0SCALEY  ====================================================== */
49060 /* ======================================================  LAYER1MODE  ======================================================= */
49061 /* ==========================================  DC LAYER1MODE LAYER1DBLEND [12..15]  ========================================== */
49062 typedef enum {                                  /*!< DC_LAYER1MODE_LAYER1DBLEND                                                */
49063   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DBLACK_BLEND = 0,/*!< LAYER1_DBLACK_BLEND : blend black                                    */
49064   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DWHITE_BLEND = 1,/*!< LAYER1_DWHITE_BLEND : blend white                                    */
49065   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALBHAS_BLEND = 2,/*!< LAYER1_DALBHAS_BLEND : blend alpha source                           */
49066   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHAG_BLEND = 3,/*!< LAYER1_DALPHAG_BLEND : blend alpha global                           */
49067   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHASG_BLEND = 4,/*!< LAYER1_DALPHASG_BLEND : blend alpha source and alpha global        */
49068   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_BLEND_SRC = 5,/*!< LAYER1_DINVERT_BLEND_SRC : blend inverted source                */
49069   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER1_DINVERT_GLOBAL_BLEND : blend inverted global          */
49070   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERTSG_BLEND = 7,/*!< LAYER1_DINVERTSG_BLEND : blend inverted source and inverted
49071                                                      global                                                                    */
49072   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHA_BLEND = 10,/*!< LAYER1_DALPHA_BLEND : blend alpha destination                       */
49073   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_BLEND_DST = 13,/*!< LAYER1_DINVERT_BLEND_DST : blend inverted destination          */
49074 } DC_LAYER1MODE_LAYER1DBLEND_Enum;
49075 
49076 /* ==========================================  DC LAYER1MODE LAYER1SBLEND [8..11]  =========================================== */
49077 typedef enum {                                  /*!< DC_LAYER1MODE_LAYER1SBLEND                                                */
49078   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SBLACK_BLEND = 0,/*!< LAYER1_SBLACK_BLEND : blend black                                    */
49079   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SWHITE_BLEND = 1,/*!< LAYER1_SWHITE_BLEND : blend white                                    */
49080   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALBHAS_BLEND = 2,/*!< LAYER1_SALBHAS_BLEND : blend alpha source                           */
49081   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHAG_BLEND = 3,/*!< LAYER1_SALPHAG_BLEND : blend alpha global                           */
49082   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHASG_BLEND = 4,/*!< LAYER1_SALPHASG_BLEND : blend alpha source and alpha global        */
49083   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_BLEND_SRC = 5,/*!< LAYER1_SINVERT_BLEND_SRC : blend inverted source                */
49084   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_GLOBAL_BLEND = 6,/*!< LAYER1_SINVERT_GLOBAL_BLEND : blend inverted global          */
49085   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERTSG_BLEND = 7,/*!< LAYER1_SINVERTSG_BLEND : blend inverted source and inverted
49086                                                      global                                                                    */
49087   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHA_BLEND = 10,/*!< LAYER1_SALPHA_BLEND : blend alpha destination                       */
49088   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_BLEND_DST = 13,/*!< LAYER1_SINVERT_BLEND_DST : blend inverted destination          */
49089 } DC_LAYER1MODE_LAYER1SBLEND_Enum;
49090 
49091 /* =========================================  DC LAYER1MODE LAYER1COLORMODE [0..4]  ========================================== */
49092 typedef enum {                                  /*!< DC_LAYER1MODE_LAYER1COLORMODE                                             */
49093   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_LUTBLE = 0,/*!< LAYER1_LUTBLE : 8-bit color palette look-up table (LUT8)                */
49094   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGBX5551 = 1,/*!< LAYER1_RGBX5551 : 16-bit RGBX5551 color format                        */
49095   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGBX8888 = 2,/*!< LAYER1_RGBX8888 : 32-bit RGBX8888 color format                        */
49096   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB332 = 4,/*!< LAYER1_RGB332 : 8-bit RGB332 color format                               */
49097   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB565 = 5,/*!< LAYER1_RGB565 : 16-bit RGB565 color format                              */
49098   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_XRGB8888 = 6,/*!< LAYER1_XRGB8888 : 32-bit XRGB8888 color format                        */
49099   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L8 = 7,  /*!< LAYER1_L8 : L8 Grayscale/Palette format                                   */
49100   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L1 = 8,  /*!< LAYER1_L1 : L1 Grayscale/Palette format                                   */
49101   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L4 = 9,  /*!< LAYER1_L4 : L4 Grayscale/Palette format                                   */
49102   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_YUYV = 10,/*!< LAYER1_YUYV : YUYV color format                                          */
49103   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB = 11,/*!< LAYER1_RGB : 24-bit RGB color format                                      */
49104   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_YUY2 = 12,/*!< LAYER1_YUY2 : YUY2 color format                                          */
49105   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_ABGR8888 = 13,/*!< LAYER1_ABGR8888 : 32-bit ABGR8888 color format                       */
49106   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_BGRA8888 = 14,/*!< LAYER1_BGRA8888 : 32-bit BGRA8888 color format                       */
49107   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_VIDEO420 = 16,/*!< LAYER1_VIDEO420 : Video 420 Mode                                     */
49108   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_TRILIN420 = 17,/*!< LAYER1_TRILIN420 : Trilinear 420 Video Mode                         */
49109 } DC_LAYER1MODE_LAYER1COLORMODE_Enum;
49110 
49111 /* =====================================================  LAYER1STARTXY  ===================================================== */
49112 /* =====================================================  LAYER1SIZEXY  ====================================================== */
49113 /* ======================================================  LAYER1ADDR  ======================================================= */
49114 /* =====================================================  LAYER1STRIDE  ====================================================== */
49115 /* ======================================  DC LAYER1STRIDE LAYER1AXIFIFOTHLD [19..20]  ======================================= */
49116 typedef enum {                                  /*!< DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD                                         */
49117   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_HALF_SZ = 0,/*!< LAYER1_BURST_HALF_SZ : half fifo (default)                   */
49118   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_2 = 1,/*!< LAYER1_BURST_2 : 2 burst-size                                      */
49119   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_4 = 2,/*!< LAYER1_BURST_4 : 4 burst-size                                      */
49120   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_8 = 3,/*!< LAYER1_BURST_8 : 8 burst-size                                      */
49121 } DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_Enum;
49122 
49123 /* ======================================  DC LAYER1STRIDE LAYER1AXIBURSTBITS [16..18]  ====================================== */
49124 typedef enum {                                  /*!< DC_LAYER1STRIDE_LAYER1AXIBURSTBITS                                        */
49125   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_DEF = 0,/*!< LAYER1_BEATS_DEF : 16-beats (default)                           */
49126   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_2 = 1,/*!< LAYER1_BEATS_2 : 2-beats                                          */
49127   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_4 = 2,/*!< LAYER1_BEATS_4 : 4-beats                                          */
49128   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_8 = 3,/*!< LAYER1_BEATS_8 : 8-beats                                          */
49129   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_16 = 4,/*!< LAYER1_BEATS_16 : 16-beats (CHECK mistake?)                      */
49130   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_32 = 5,/*!< LAYER1_BEATS_32 : 32-beats (AXI4 only)                           */
49131   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_64 = 6,/*!< LAYER1_BEATS_64 : 64-beats (AXI4 only)                           */
49132   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_128 = 7,/*!< LAYER1_BEATS_128 : 128-beats (AXI4 only)                        */
49133 } DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_Enum;
49134 
49135 /* ======================================================  LAYER1RESXY  ====================================================== */
49136 /* =====================================================  LAYER1SCALEX  ====================================================== */
49137 /* =====================================================  LAYER1SCALEY  ====================================================== */
49138 /* ======================================================  LAYER2MODE  ======================================================= */
49139 /* ==========================================  DC LAYER2MODE LAYER2DBLEND [12..15]  ========================================== */
49140 typedef enum {                                  /*!< DC_LAYER2MODE_LAYER2DBLEND                                                */
49141   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DBLACK_BLEND = 0,/*!< LAYER2_DBLACK_BLEND : blend black                                    */
49142   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DWHITE_BLEND = 1,/*!< LAYER2_DWHITE_BLEND : blend white                                    */
49143   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALBHAS_BLEND = 2,/*!< LAYER2_DALBHAS_BLEND : blend alpha source                           */
49144   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHAG_BLEND = 3,/*!< LAYER2_DALPHAG_BLEND : blend alpha global                           */
49145   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHASG_BLEND = 4,/*!< LAYER2_DALPHASG_BLEND : blend alpha source and alpha global        */
49146   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_BLEND_SRC = 5,/*!< LAYER2_DINVERT_BLEND_SRC : blend inverted source                */
49147   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER2_DINVERT_GLOBAL_BLEND : blend inverted global          */
49148   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERTSG_BLEND = 7,/*!< LAYER2_DINVERTSG_BLEND : blend inverted source and inverted
49149                                                      global                                                                    */
49150   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHA_BLEND = 10,/*!< LAYER2_DALPHA_BLEND : blend alpha destination                       */
49151   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_BLEND_DST = 13,/*!< LAYER2_DINVERT_BLEND_DST : blend inverted destination          */
49152 } DC_LAYER2MODE_LAYER2DBLEND_Enum;
49153 
49154 /* ==========================================  DC LAYER2MODE LAYER2SBLEND [8..11]  =========================================== */
49155 typedef enum {                                  /*!< DC_LAYER2MODE_LAYER2SBLEND                                                */
49156   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SBLACK_BLEND = 0,/*!< LAYER2_SBLACK_BLEND : blend black                                    */
49157   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SWHITE_BLEND = 1,/*!< LAYER2_SWHITE_BLEND : blend white                                    */
49158   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALBHAS_BLEND = 2,/*!< LAYER2_SALBHAS_BLEND : blend alpha source                           */
49159   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHAG_BLEND = 3,/*!< LAYER2_SALPHAG_BLEND : blend alpha global                           */
49160   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHASG_BLEND = 4,/*!< LAYER2_SALPHASG_BLEND : blend alpha source and alpha global        */
49161   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_BLEND_SRC = 5,/*!< LAYER2_SINVERT_BLEND_SRC : blend inverted source                */
49162   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_GLOBAL_BLEND = 6,/*!< LAYER2_SINVERT_GLOBAL_BLEND : blend inverted global          */
49163   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERTSG_BLEND = 7,/*!< LAYER2_SINVERTSG_BLEND : blend inverted source and inverted
49164                                                      global                                                                    */
49165   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHA_BLEND = 10,/*!< LAYER2_SALPHA_BLEND : blend alpha destination                       */
49166   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_BLEND_DST = 13,/*!< LAYER2_SINVERT_BLEND_DST : blend inverted destination          */
49167 } DC_LAYER2MODE_LAYER2SBLEND_Enum;
49168 
49169 /* =========================================  DC LAYER2MODE LAYER2COLORMODE [0..4]  ========================================== */
49170 typedef enum {                                  /*!< DC_LAYER2MODE_LAYER2COLORMODE                                             */
49171   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_LUTBLE = 0,/*!< LAYER2_LUTBLE : 8-bit color palette look-up table (LUT8)                */
49172   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGBX5551 = 1,/*!< LAYER2_RGBX5551 : 16-bit RGBX5551 color format                        */
49173   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGBX8888 = 2,/*!< LAYER2_RGBX8888 : 32-bit RGBX8888 color format                        */
49174   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB332 = 4,/*!< LAYER2_RGB332 : 8-bit RGB332 color format                               */
49175   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB565 = 5,/*!< LAYER2_RGB565 : 16-bit RGB565 color format                              */
49176   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_XRGB8888 = 6,/*!< LAYER2_XRGB8888 : 32-bit XRGB8888 color format                        */
49177   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L8 = 7,  /*!< LAYER2_L8 : L8 Grayscale/Palette format                                   */
49178   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L1 = 8,  /*!< LAYER2_L1 : L1 Grayscale/Palette format                                   */
49179   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L4 = 9,  /*!< LAYER2_L4 : L4 Grayscale/Palette format                                   */
49180   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_YUYV = 10,/*!< LAYER2_YUYV : YUYV color format                                          */
49181   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB = 11,/*!< LAYER2_RGB : 24-bit RGB color format                                      */
49182   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_YUY2 = 12,/*!< LAYER2_YUY2 : YUY2 color format                                          */
49183   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_ABGR8888 = 13,/*!< LAYER2_ABGR8888 : 32-bit ABGR8888 color format                       */
49184   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_BGRA8888 = 14,/*!< LAYER2_BGRA8888 : 32-bit BGRA8888 color format                       */
49185   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_VIDEO420 = 16,/*!< LAYER2_VIDEO420 : Video 420 Mode                                     */
49186   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_TRILIN420 = 17,/*!< LAYER2_TRILIN420 : Trilinear 420 Video Mode                         */
49187 } DC_LAYER2MODE_LAYER2COLORMODE_Enum;
49188 
49189 /* =====================================================  LAYER2STARTXY  ===================================================== */
49190 /* =====================================================  LAYER2SIZEXY  ====================================================== */
49191 /* ======================================================  LAYER2ADDR  ======================================================= */
49192 /* =====================================================  LAYER2STRIDE  ====================================================== */
49193 /* ======================================  DC LAYER2STRIDE LAYER2AXIFIFOTHLD [19..20]  ======================================= */
49194 typedef enum {                                  /*!< DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD                                         */
49195   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_HALF_SZ = 0,/*!< LAYER2_BURST_HALF_SZ : half fifo (default)                   */
49196   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_2 = 1,/*!< LAYER2_BURST_2 : 2 burst-size                                      */
49197   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_4 = 2,/*!< LAYER2_BURST_4 : 4 burst-size                                      */
49198   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_8 = 3,/*!< LAYER2_BURST_8 : 8 burst-size                                      */
49199 } DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_Enum;
49200 
49201 /* ======================================  DC LAYER2STRIDE LAYER2AXIBURSTBITS [16..18]  ====================================== */
49202 typedef enum {                                  /*!< DC_LAYER2STRIDE_LAYER2AXIBURSTBITS                                        */
49203   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_DEF = 0,/*!< LAYER2_BEATS_DEF : 16-beats (default)                           */
49204   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_2 = 1,/*!< LAYER2_BEATS_2 : 2-beats                                          */
49205   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_4 = 2,/*!< LAYER2_BEATS_4 : 4-beats                                          */
49206   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_8 = 3,/*!< LAYER2_BEATS_8 : 8-beats                                          */
49207   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_16 = 4,/*!< LAYER2_BEATS_16 : 16-beats (CHECK mistake?)                      */
49208   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_32 = 5,/*!< LAYER2_BEATS_32 : 32-beats (AXI4 only)                           */
49209   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_64 = 6,/*!< LAYER2_BEATS_64 : 64-beats (AXI4 only)                           */
49210   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_128 = 7,/*!< LAYER2_BEATS_128 : 128-beats (AXI4 only)                        */
49211 } DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_Enum;
49212 
49213 /* ======================================================  LAYER2RESXY  ====================================================== */
49214 /* =====================================================  LAYER2SCALEX  ====================================================== */
49215 /* =====================================================  LAYER2SCALEY  ====================================================== */
49216 /* ======================================================  LAYER3MODE  ======================================================= */
49217 /* ==========================================  DC LAYER3MODE LAYER3DBLEND [12..15]  ========================================== */
49218 typedef enum {                                  /*!< DC_LAYER3MODE_LAYER3DBLEND                                                */
49219   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DBLACK_BLEND = 0,/*!< LAYER3_DBLACK_BLEND : blend black                                    */
49220   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DWHITE_BLEND = 1,/*!< LAYER3_DWHITE_BLEND : blend white                                    */
49221   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALBHAS_BLEND = 2,/*!< LAYER3_DALBHAS_BLEND : blend alpha source                           */
49222   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHAG_BLEND = 3,/*!< LAYER3_DALPHAG_BLEND : blend alpha global                           */
49223   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHASG_BLEND = 4,/*!< LAYER3_DALPHASG_BLEND : blend alpha source and alpha global        */
49224   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_BLEND_SRC = 5,/*!< LAYER3_DINVERT_BLEND_SRC : blend inverted source                */
49225   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER3_DINVERT_GLOBAL_BLEND : blend inverted global          */
49226   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERTSG_BLEND = 7,/*!< LAYER3_DINVERTSG_BLEND : blend inverted source and inverted
49227                                                      global                                                                    */
49228   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHA_BLEND = 10,/*!< LAYER3_DALPHA_BLEND : blend alpha destination                       */
49229   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_BLEND_DST = 13,/*!< LAYER3_DINVERT_BLEND_DST : blend inverted destination          */
49230 } DC_LAYER3MODE_LAYER3DBLEND_Enum;
49231 
49232 /* ==========================================  DC LAYER3MODE LAYER3SBLEND [8..11]  =========================================== */
49233 typedef enum {                                  /*!< DC_LAYER3MODE_LAYER3SBLEND                                                */
49234   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SBLACKBLEND = 0,/*!< LAYER3SBLACKBLEND : layer 3 black blend register. blend black          */
49235   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SWHITEBLEND = 1,/*!< LAYER3SWHITEBLEND : blend white                                        */
49236   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALBHASBLEND = 2,/*!< LAYER3SALBHASBLEND : blend alpha source                               */
49237   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHAGBLEND = 3,/*!< LAYER3SALPHAGBLEND : blend alpha global                               */
49238   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHASGBLEND = 4,/*!< LAYER3SALPHASGBLEND : blend alpha source and alpha global            */
49239   DC_LAYER3MODE_LAYER3SBLEND_LAYER3_SINVERT_BLEND_SRC = 5,/*!< LAYER3_SINVERT_BLEND_SRC : blend inverted source                */
49240   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SINVERTGLOBALBLEND = 6,/*!< LAYER3SINVERTGLOBALBLEND : blend inverted global                */
49241   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SINVERTSGBLEND = 7,/*!< LAYER3SINVERTSGBLEND : blend inverted source and inverted global    */
49242   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHABLEND = 10,/*!< LAYER3SALPHABLEND : blend alpha destination                           */
49243   DC_LAYER3MODE_LAYER3SBLEND_LAYER3_SINVERT_BLEND_DST = 13,/*!< LAYER3_SINVERT_BLEND_DST : blend inverted destination          */
49244 } DC_LAYER3MODE_LAYER3SBLEND_Enum;
49245 
49246 /* =========================================  DC LAYER3MODE LAYER3COLORMODE [0..4]  ========================================== */
49247 typedef enum {                                  /*!< DC_LAYER3MODE_LAYER3COLORMODE                                             */
49248   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_LUTBLE = 0,/*!< LAYER3_LUTBLE : 8-bit color palette look-up table (LUT8)                */
49249   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGBX5551 = 1,/*!< LAYER3_RGBX5551 : 16-bit RGBX5551 color format                        */
49250   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGBX8888 = 2,/*!< LAYER3_RGBX8888 : 32-bit RGBX8888 color format                        */
49251   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB332 = 4,/*!< LAYER3_RGB332 : 8-bit RGB332 color format                               */
49252   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB565 = 5,/*!< LAYER3_RGB565 : 16-bit RGB565 color format                              */
49253   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_XRGB8888 = 6,/*!< LAYER3_XRGB8888 : 32-bit XRGB8888 color format                        */
49254   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L8 = 7,  /*!< LAYER3_L8 : L8 Grayscale/Palette format                                   */
49255   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L1 = 8,  /*!< LAYER3_L1 : L1 Grayscale/Palette format                                   */
49256   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L4 = 9,  /*!< LAYER3_L4 : L4 Grayscale/Palette format                                   */
49257   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_YUYV = 10,/*!< LAYER3_YUYV : YUYV color format                                          */
49258   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB = 11,/*!< LAYER3_RGB : 24-bit RGB color format                                      */
49259   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_YUY2 = 12,/*!< LAYER3_YUY2 : YUY2 color format                                          */
49260   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_ABGR8888 = 13,/*!< LAYER3_ABGR8888 : 32-bit ABGR8888 color format                       */
49261   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_BGRA8888 = 14,/*!< LAYER3_BGRA8888 : 32-bit BGRA8888 color format                       */
49262   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_VIDEO420 = 16,/*!< LAYER3_VIDEO420 : Video 420 Mode                                     */
49263   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_TRILIN42 = 17,/*!< LAYER3_TRILIN42 : Trilinear 420 Video Mode                           */
49264 } DC_LAYER3MODE_LAYER3COLORMODE_Enum;
49265 
49266 /* =====================================================  LAYER3STARTXY  ===================================================== */
49267 /* =====================================================  LAYER3SIZEXY  ====================================================== */
49268 /* ======================================================  LAYER3ADDR  ======================================================= */
49269 /* =====================================================  LAYER3STRIDE  ====================================================== */
49270 /* ======================================  DC LAYER3STRIDE LAYER3AXIFIFOTHLD [19..20]  ======================================= */
49271 typedef enum {                                  /*!< DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD                                         */
49272   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_HALF_SZ = 0,/*!< LAYER3_BURST_HALF_SZ : half fifo (default)                   */
49273   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_2 = 1,/*!< LAYER3_BURST_2 : 2 burst-size                                      */
49274   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_4 = 2,/*!< LAYER3_BURST_4 : 4 burst-size                                      */
49275   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_8 = 3,/*!< LAYER3_BURST_8 : 8 burst-size                                      */
49276 } DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_Enum;
49277 
49278 /* ======================================  DC LAYER3STRIDE LAYER3AXIBURSTBITS [16..18]  ====================================== */
49279 typedef enum {                                  /*!< DC_LAYER3STRIDE_LAYER3AXIBURSTBITS                                        */
49280   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_DEF = 0,/*!< LAYER3_BEATS_DEF : 16-beats (default)                           */
49281   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_2 = 1,/*!< LAYER3_BEATS_2 : 2-beats                                          */
49282   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_4 = 2,/*!< LAYER3_BEATS_4 : 4-beats                                          */
49283   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_8 = 3,/*!< LAYER3_BEATS_8 : 8-beats                                          */
49284   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_16 = 4,/*!< LAYER3_BEATS_16 : 16-beats (CHECK mistake?)                      */
49285   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_32 = 5,/*!< LAYER3_BEATS_32 : 32-beats (AXI4 only)                           */
49286   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_64 = 6,/*!< LAYER3_BEATS_64 : 64-beats (AXI4 only)                           */
49287   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_128 = 7,/*!< LAYER3_BEATS_128 : 128-beats (AXI4 only)                        */
49288 } DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_Enum;
49289 
49290 /* ======================================================  LAYER3RESXY  ====================================================== */
49291 /* =====================================================  LAYER3SCALEX  ====================================================== */
49292 /* =====================================================  LAYER3SCALEY  ====================================================== */
49293 /* ========================================================  DBICMD  ========================================================= */
49294 /* ========================================================  DBIRDAT  ======================================================== */
49295 /* =========================================================  CONFG  ========================================================= */
49296 /* =========================================================  IDREG  ========================================================= */
49297 /* =======================================================  INTERRUPT  ======================================================= */
49298 /* ===========================================  DC INTERRUPT INTTRIGGER [31..31]  ============================================ */
49299 typedef enum {                                  /*!< DC_INTERRUPT_INTTRIGGER                                                   */
49300   DC_INTERRUPT_INTTRIGGER_LEVEL        = 1,     /*!< LEVEL : Level triggering is enabled                                       */
49301   DC_INTERRUPT_INTTRIGGER_EDGE         = 0,     /*!< EDGE : Edge triggering is enabled                                         */
49302 } DC_INTERRUPT_INTTRIGGER_Enum;
49303 
49304 /* ========================================================  STATUS  ========================================================= */
49305 /* ========================================================  COLMOD  ========================================================= */
49306 /* ==========================================================  CRC  ========================================================== */
49307 /* =========================================================  GLLUT  ========================================================= */
49308 /* ======================================================  CURSORDATA  ======================================================= */
49309 /* =======================================================  CURSORLUT  ======================================================= */
49310 /* =========================================================  L0LUT  ========================================================= */
49311 /* =========================================================  L1LUT  ========================================================= */
49312 /* ========================================================  L2LUT0  ========================================================= */
49313 /* =========================================================  L3LUT  ========================================================= */
49314 
49315 
49316 /* =========================================================================================================================== */
49317 /* ================                                            DSI                                            ================ */
49318 /* =========================================================================================================================== */
49319 
49320 /* ======================================================  DEVICEREADY  ====================================================== */
49321 /* ==============================================  DSI DEVICEREADY ULPS [1..2]  ============================================== */
49322 typedef enum {                                  /*!< DSI_DEVICEREADY_ULPS                                                      */
49323   DSI_DEVICEREADY_ULPS_LOW_POWER       = 2,     /*!< LOW_POWER : This pattern is set by the processor to inform that
49324                                                      entire DSI host is to be put on ultra low power [POWER
49325                                                      SAVING] mode 01 - This pattern is set by the processor
49326                                                      to inform                                                                 */
49327   DSI_DEVICEREADY_ULPS_EXIT            = 1,     /*!< EXIT : This pattern is set by the processor to inform that entire
49328                                                      DSI host is to be pu on ultr low power EXIT mode                          */
49329   DSI_DEVICEREADY_ULPS_This            = 0,     /*!< This : pattern is set by the processor to make the DSI host
49330                                                      come out of the wakeup time and resume the normal operation
49331                                                      if the DSI Host already remains in the ULPS exit state.
49332                                                      S/W needs to ensure that there is a minimum of 1ms time
49333                                                      available before clearing the UPLS exit State. 1(a). In
49334                                                      DPI Only Mode: No DPI traffic should be sent after the
49335                                                      above patterns like 10 or 01 is set in this register. Device_ready
49336                                                      bit in Device Ready register should not be disturbed or
49337                                                      should remain set while the device is subject                             */
49338 } DSI_DEVICEREADY_ULPS_Enum;
49339 
49340 /* =============================================  DSI DEVICEREADY READY [0..0]  ============================================== */
49341 typedef enum {                                  /*!< DSI_DEVICEREADY_READY                                                     */
49342   DSI_DEVICEREADY_READY_PROGRAMMED     = 1,     /*!< PROGRAMMED : Set to 1 after dphy_parameter register, all the
49343                                                      count registers, and timeout and interrupt enable registers
49344                                                      are being programmed.                                                     */
49345   DSI_DEVICEREADY_READY_READY          = 0,     /*!< READY : Set by the processor to inform that device is ready
49346                                                      for transmission. This register should be set to 1 after
49347                                                      dphy_parameter register, all the count registers, and timeout
49348                                                      and interrupt enable registers are being programmed. Note:
49349                                                      Reprogramming the registers by resetting the device_ready
49350                                                      bit results in re-enumeration of the DSI controller from
49351                                                      the power up sequence.                                                    */
49352 } DSI_DEVICEREADY_READY_Enum;
49353 
49354 /* =======================================================  INTRSTAT  ======================================================== */
49355 /* ========================================================  INTREN  ========================================================= */
49356 /* ======================================================  DSIFUNCPRG  ======================================================= */
49357 /* ============================================  DSI DSIFUNCPRG REGNAME [13..15]  ============================================ */
49358 typedef enum {                                  /*!< DSI_DSIFUNCPRG_REGNAME                                                    */
49359   DSI_DSIFUNCPRG_REGNAME_command       = 0,     /*!< command : mode is not supported]                                          */
49360   DSI_DSIFUNCPRG_REGNAME_16BIT         = 1,     /*!< 16BIT : 16 bit data                                                       */
49361   DSI_DSIFUNCPRG_REGNAME_9BIT          = 2,     /*!< 9BIT : 9 bit data                                                         */
49362   DSI_DSIFUNCPRG_REGNAME_8BIT          = 3,     /*!< 8BIT : 8 bit data                                                         */
49363 } DSI_DSIFUNCPRG_REGNAME_Enum;
49364 
49365 /* ==========================================  DSI DSIFUNCPRG SUPCOLVIDMODE [7..9]  ========================================== */
49366 typedef enum {                                  /*!< DSI_DSIFUNCPRG_SUPCOLVIDMODE                                              */
49367   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE0 = 0,   /*!< FMTVMODE0 : Video mode is not supported                                   */
49368   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE1 = 1,   /*!< FMTVMODE1 : RGB565 or 16-bit format                                       */
49369   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE2 = 2,   /*!< FMTVMODE2 : RGB666 or 18-bit format                                       */
49370   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE3 = 3,   /*!< FMTVMODE3 : RGB 666 loosely packed format                                 */
49371   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE4 = 4,   /*!< FMTVMODE4 : RGB888 or 24-bit format                                       */
49372 } DSI_DSIFUNCPRG_SUPCOLVIDMODE_Enum;
49373 
49374 /* ===========================================  DSI DSIFUNCPRG CHNUMCMODE [5..6]  ============================================ */
49375 typedef enum {                                  /*!< DSI_DSIFUNCPRG_CHNUMCMODE                                                 */
49376   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH0      = 0,     /*!< VCCH0 : Virtual command mode channel 0                                    */
49377   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH1      = 1,     /*!< VCCH1 : Virtual command mode channel 1                                    */
49378   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH2      = 2,     /*!< VCCH2 : Virtual command mode channel 2                                    */
49379   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH3      = 3,     /*!< VCCH3 : Virtual command mode channel 3                                    */
49380 } DSI_DSIFUNCPRG_CHNUMCMODE_Enum;
49381 
49382 /* =============================================  DSI DSIFUNCPRG CHNUMVM [3..4]  ============================================= */
49383 typedef enum {                                  /*!< DSI_DSIFUNCPRG_CHNUMVM                                                    */
49384   DSI_DSIFUNCPRG_CHNUMVM_VVCH0         = 0,     /*!< VVCH0 : Virtual video mode channel 0                                      */
49385   DSI_DSIFUNCPRG_CHNUMVM_VVCH1         = 1,     /*!< VVCH1 : Virtual video mode channel 1                                      */
49386   DSI_DSIFUNCPRG_CHNUMVM_VVCH2         = 2,     /*!< VVCH2 : Virtual video mode channel 2                                      */
49387   DSI_DSIFUNCPRG_CHNUMVM_VVCH3         = 3,     /*!< VVCH3 : Virtual video mode channel 3                                      */
49388 } DSI_DSIFUNCPRG_CHNUMVM_Enum;
49389 
49390 /* ============================================  DSI DSIFUNCPRG DATALANES [0..2]  ============================================ */
49391 typedef enum {                                  /*!< DSI_DSIFUNCPRG_DATALANES                                                  */
49392   DSI_DSIFUNCPRG_DATALANES_DATAL0      = 0,     /*!< DATAL0 : Zero data lane                                                   */
49393   DSI_DSIFUNCPRG_DATALANES_DATAL1      = 1,     /*!< DATAL1 : One data lane                                                    */
49394   DSI_DSIFUNCPRG_DATALANES_DATAL2      = 2,     /*!< DATAL2 : Two data lane                                                    */
49395   DSI_DSIFUNCPRG_DATALANES_DATAL3      = 3,     /*!< DATAL3 : Three data lane                                                  */
49396   DSI_DSIFUNCPRG_DATALANES_DATAL4      = 4,     /*!< DATAL4 : Four data lane                                                   */
49397 } DSI_DSIFUNCPRG_DATALANES_Enum;
49398 
49399 /* ======================================================  HSTXTIMEOUT  ====================================================== */
49400 /* ========================================================  LPRXTO  ========================================================= */
49401 /* ======================================================  TURNARNDTO  ======================================================= */
49402 /* ===================================================  DEVICERESETTIMER  ==================================================== */
49403 /* =====================================================  DPIRESOLUTION  ===================================================== */
49404 /* =======================================================  HSYNCCNT  ======================================================== */
49405 /* ====================================================  HORIZBKPORCHCNT  ==================================================== */
49406 /* ====================================================  HORIZFPORCHCNT  ===================================================== */
49407 /* ===================================================  HORZACTIVEAREACNT  =================================================== */
49408 /* =======================================================  VSYNCCNT  ======================================================== */
49409 /* ====================================================  VERTBKPORCHCNT  ===================================================== */
49410 /* =====================================================  VERTFPORCHCNT  ===================================================== */
49411 /* ===================================================  DATALANEHILOSWCNT  =================================================== */
49412 /* ==========================================================  DPI  ========================================================== */
49413 /* ======================================================  PLLLOCKCNT  ======================================================= */
49414 /* ========================================================  INITCNT  ======================================================== */
49415 /* =====================================================  MAXRETPACSZE  ====================================================== */
49416 /* =====================================================  VIDEOMODEFMT  ====================================================== */
49417 /* ===========================================  DSI VIDEOMODEFMT VIDEMDFMT [0..1]  =========================================== */
49418 typedef enum {                                  /*!< DSI_VIDEOMODEFMT_VIDEMDFMT                                                */
49419   DSI_VIDEOMODEFMT_VIDEMDFMT_VIDEMDFMT_0 = 0,   /*!< VIDEMDFMT_0 : VIDEMDFMT enum description needed here.                     */
49420   DSI_VIDEOMODEFMT_VIDEMDFMT_NONBURSTPULSE = 1, /*!< NONBURSTPULSE : Non Burst Mode with Sync Pulse                            */
49421   DSI_VIDEOMODEFMT_VIDEMDFMT_NONBURSTEVENTS = 2,/*!< NONBURSTEVENTS : Non Burst Mode with Sync events                          */
49422   DSI_VIDEOMODEFMT_VIDEMDFMT_BURST     = 3,     /*!< BURST : MODE Burst Mode                                                   */
49423 } DSI_VIDEOMODEFMT_VIDEMDFMT_Enum;
49424 
49425 /* ========================================================  CLKEOT  ========================================================= */
49426 /* =======================================================  POLARITY  ======================================================== */
49427 /* ===============================================  DSI POLARITY PBITS [0..3]  =============================================== */
49428 typedef enum {                                  /*!< DSI_POLARITY_PBITS                                                        */
49429   DSI_POLARITY_PBITS_POLV              = 0,     /*!< POLV : polarity for Vsync                                                 */
49430   DSI_POLARITY_PBITS_POLH              = 1,     /*!< POLH : Polarity for Hsync                                                 */
49431   DSI_POLARITY_PBITS_POLSD             = 2,     /*!< POLSD : Polarity for shut down                                            */
49432   DSI_POLARITY_PBITS_POLCM             = 3,     /*!< POLCM : Polarity for Color mode                                           */
49433 } DSI_POLARITY_PBITS_Enum;
49434 
49435 /* ======================================================  CLKLANESWT  ======================================================= */
49436 /* =======================================================  LPBYTECLK  ======================================================= */
49437 /* =======================================================  DPHYPARAM  ======================================================= */
49438 /* ====================================================  CLKLANETIMPARM  ===================================================== */
49439 /* =======================================================  RSTENBDFE  ======================================================= */
49440 /* =======================================================  AFETRIM0  ======================================================== */
49441 /* =======================================================  AFETRIM1  ======================================================== */
49442 /* =======================================================  AFETRIM2  ======================================================== */
49443 /* =======================================================  AFETRIM3  ======================================================== */
49444 /* =====================================================  ERRORAUTORCOV  ===================================================== */
49445 /* ====================================================  MIPIDIRDPIDIFF  ===================================================== */
49446 /* ==========================================  DSI MIPIDIRDPIDIFF DPIHIGH [15..15]  ========================================== */
49447 typedef enum {                                  /*!< DSI_MIPIDIRDPIDIFF_DPIHIGH                                                */
49448   DSI_MIPIDIRDPIDIFF_DPIHIGH_LESSTHAN  = 0,     /*!< LESSTHAN : one line time in DPI is less than to DSI line time             */
49449   DSI_MIPIDIRDPIDIFF_DPIHIGH_GREATER   = 1,     /*!< GREATER : one line time in DPI is greater than or equal to DSI
49450                                                      line time                                                                 */
49451 } DSI_MIPIDIRDPIDIFF_DPIHIGH_Enum;
49452 
49453 /* ===========================================  DSI MIPIDIRDPIDIFF MIPIDIR [0..0]  =========================================== */
49454 typedef enum {                                  /*!< DSI_MIPIDIRDPIDIFF_MIPIDIR                                                */
49455   DSI_MIPIDIRDPIDIFF_MIPIDIR_CONTROL   = 0,     /*!< CONTROL : DSI Host has the control over MIPI bus                          */
49456   DSI_MIPIDIRDPIDIFF_MIPIDIR_RECEIVE   = 1,     /*!< RECEIVE : DSI Host is in Receive mode                                     */
49457 } DSI_MIPIDIRDPIDIFF_MIPIDIR_Enum;
49458 
49459 /* ====================================================  DATALANEPOLSWAP  ==================================================== */
49460 /* =======================================  DSI DATALANEPOLSWAP DATALNPOLSWAP [0..3]  ======================================== */
49461 typedef enum {                                  /*!< DSI_DATALANEPOLSWAP_DATALNPOLSWAP                                         */
49462   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE0 = 1,  /*!< LANE0 : lane 0 polarity swap                                              */
49463   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE1 = 2,  /*!< LANE1 : lane 1 polarity swap                                              */
49464   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE2 = 4,  /*!< LANE2 : lane 2 polarity swap                                              */
49465   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE3 = 8,  /*!< LANE3 : lane 3 polarity swap                                              */
49466   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_ALLLANES = 15,/*!< ALLLANES : data lanes polarity swap                                     */
49467 } DSI_DATALANEPOLSWAP_DATALNPOLSWAP_Enum;
49468 
49469 
49470 
49471 /* =========================================================================================================================== */
49472 /* ================                                            DSP                                            ================ */
49473 /* =========================================================================================================================== */
49474 
49475 /* ========================================================  MUTEX0  ========================================================= */
49476 /* ===============================================  DSP MUTEX0 MUTEX0 [0..2]  ================================================ */
49477 typedef enum {                                  /*!< DSP_MUTEX0_MUTEX0                                                         */
49478   DSP_MUTEX0_MUTEX0_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49479   DSP_MUTEX0_MUTEX0_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49480   DSP_MUTEX0_MUTEX0_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49481   DSP_MUTEX0_MUTEX0_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49482   DSP_MUTEX0_MUTEX0_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49483   DSP_MUTEX0_MUTEX0_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49484 } DSP_MUTEX0_MUTEX0_Enum;
49485 
49486 /* ========================================================  MUTEX1  ========================================================= */
49487 /* ===============================================  DSP MUTEX1 MUTEX1 [0..2]  ================================================ */
49488 typedef enum {                                  /*!< DSP_MUTEX1_MUTEX1                                                         */
49489   DSP_MUTEX1_MUTEX1_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49490   DSP_MUTEX1_MUTEX1_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49491   DSP_MUTEX1_MUTEX1_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49492   DSP_MUTEX1_MUTEX1_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49493   DSP_MUTEX1_MUTEX1_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49494   DSP_MUTEX1_MUTEX1_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49495 } DSP_MUTEX1_MUTEX1_Enum;
49496 
49497 /* ========================================================  MUTEX2  ========================================================= */
49498 /* ===============================================  DSP MUTEX2 MUTEX2 [0..2]  ================================================ */
49499 typedef enum {                                  /*!< DSP_MUTEX2_MUTEX2                                                         */
49500   DSP_MUTEX2_MUTEX2_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49501   DSP_MUTEX2_MUTEX2_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49502   DSP_MUTEX2_MUTEX2_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49503   DSP_MUTEX2_MUTEX2_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49504   DSP_MUTEX2_MUTEX2_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49505   DSP_MUTEX2_MUTEX2_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49506 } DSP_MUTEX2_MUTEX2_Enum;
49507 
49508 /* ========================================================  MUTEX3  ========================================================= */
49509 /* ===============================================  DSP MUTEX3 MUTEX3 [0..2]  ================================================ */
49510 typedef enum {                                  /*!< DSP_MUTEX3_MUTEX3                                                         */
49511   DSP_MUTEX3_MUTEX3_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49512   DSP_MUTEX3_MUTEX3_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49513   DSP_MUTEX3_MUTEX3_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49514   DSP_MUTEX3_MUTEX3_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49515   DSP_MUTEX3_MUTEX3_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49516   DSP_MUTEX3_MUTEX3_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49517 } DSP_MUTEX3_MUTEX3_Enum;
49518 
49519 /* ========================================================  MUTEX4  ========================================================= */
49520 /* ===============================================  DSP MUTEX4 MUTEX4 [0..2]  ================================================ */
49521 typedef enum {                                  /*!< DSP_MUTEX4_MUTEX4                                                         */
49522   DSP_MUTEX4_MUTEX4_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49523   DSP_MUTEX4_MUTEX4_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49524   DSP_MUTEX4_MUTEX4_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49525   DSP_MUTEX4_MUTEX4_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49526   DSP_MUTEX4_MUTEX4_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49527   DSP_MUTEX4_MUTEX4_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49528 } DSP_MUTEX4_MUTEX4_Enum;
49529 
49530 /* ========================================================  MUTEX5  ========================================================= */
49531 /* ===============================================  DSP MUTEX5 MUTEX5 [0..2]  ================================================ */
49532 typedef enum {                                  /*!< DSP_MUTEX5_MUTEX5                                                         */
49533   DSP_MUTEX5_MUTEX5_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49534   DSP_MUTEX5_MUTEX5_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49535   DSP_MUTEX5_MUTEX5_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49536   DSP_MUTEX5_MUTEX5_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49537   DSP_MUTEX5_MUTEX5_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49538   DSP_MUTEX5_MUTEX5_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49539 } DSP_MUTEX5_MUTEX5_Enum;
49540 
49541 /* ========================================================  MUTEX6  ========================================================= */
49542 /* ===============================================  DSP MUTEX6 MUTEX6 [0..2]  ================================================ */
49543 typedef enum {                                  /*!< DSP_MUTEX6_MUTEX6                                                         */
49544   DSP_MUTEX6_MUTEX6_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49545   DSP_MUTEX6_MUTEX6_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49546   DSP_MUTEX6_MUTEX6_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49547   DSP_MUTEX6_MUTEX6_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49548   DSP_MUTEX6_MUTEX6_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49549   DSP_MUTEX6_MUTEX6_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49550 } DSP_MUTEX6_MUTEX6_Enum;
49551 
49552 /* ========================================================  MUTEX7  ========================================================= */
49553 /* ===============================================  DSP MUTEX7 MUTEX7 [0..2]  ================================================ */
49554 typedef enum {                                  /*!< DSP_MUTEX7_MUTEX7                                                         */
49555   DSP_MUTEX7_MUTEX7_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
49556   DSP_MUTEX7_MUTEX7_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
49557   DSP_MUTEX7_MUTEX7_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
49558   DSP_MUTEX7_MUTEX7_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
49559   DSP_MUTEX7_MUTEX7_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
49560   DSP_MUTEX7_MUTEX7_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
49561 } DSP_MUTEX7_MUTEX7_Enum;
49562 
49563 /* ======================================================  CPUMBINTSET  ====================================================== */
49564 /* ======================================================  CPUMBINTCLR  ====================================================== */
49565 /* =====================================================  CPUMBINTSTAT  ====================================================== */
49566 /* =====================================================  CPUCPUMBDATA  ====================================================== */
49567 /* =====================================================  DSP0CPUMBDATA  ===================================================== */
49568 /* =====================================================  DSP1CPUMBDATA  ===================================================== */
49569 /* =====================================================  DSP0MBINTSET  ====================================================== */
49570 /* =====================================================  DSP0MBINTCLR  ====================================================== */
49571 /* =====================================================  DSP0MBINTSTAT  ===================================================== */
49572 /* =====================================================  CPUDSP0MBDATA  ===================================================== */
49573 /* ====================================================  DSP0DSP0MBDATA  ===================================================== */
49574 /* ====================================================  DSP1DSP0MBDATA  ===================================================== */
49575 /* =====================================================  DSP1MBINTSET  ====================================================== */
49576 /* =====================================================  DSP1MBINTCLR  ====================================================== */
49577 /* =====================================================  DSP1MBINTSTAT  ===================================================== */
49578 /* =====================================================  CPUDSP1MBDATA  ===================================================== */
49579 /* ====================================================  DSP0DSP1MBDATA  ===================================================== */
49580 /* ====================================================  DSP1DSP1MBDATA  ===================================================== */
49581 /* ======================================================  DSP0CONTROL  ====================================================== */
49582 /* ==========================================  DSP DSP0CONTROL DSP0IDMATRIG [4..5]  ========================================== */
49583 typedef enum {                                  /*!< DSP_DSP0CONTROL_DSP0IDMATRIG                                              */
49584   DSP_DSP0CONTROL_DSP0IDMATRIG_XTRIG   = 3,     /*!< XTRIG : Trigger is disabled until a cross trigger pulse is asserted.
49585                                                      This will allow another source (determined by the XTRIGSRC
49586                                                      register) to allow the DMA descriptor chain to proceed.                   */
49587   DSP_DSP0CONTROL_DSP0IDMATRIG_SSTEP   = 2,     /*!< SSTEP : Trigger is disabled until a trigger pulse (PULSE in
49588                                                      IDMATRIG register) is asserted. This will allow a single
49589                                                      step in the DMA descriptor chain to be enabled until next
49590                                                      completion.                                                               */
49591   DSP_DSP0CONTROL_DSP0IDMATRIG_AON     = 1,     /*!< AON : Trigger is always enabled. With this set, any trigger
49592                                                      out will immediately generate a trigger in                                */
49593   DSP_DSP0CONTROL_DSP0IDMATRIG_DISABLE = 0,     /*!< DISABLE : Trigger is disabled. This will pause the iDMA indefinitely
49594                                                      until enabled.                                                            */
49595 } DSP_DSP0CONTROL_DSP0IDMATRIG_Enum;
49596 
49597 /* =====================================================  DSP0RESETVEC  ====================================================== */
49598 /* ======================================================  DSP0IRQMASK  ====================================================== */
49599 /* =====================================================  DSP0WAKEMASK  ====================================================== */
49600 /* ==================================================  DSP0RAWIRQSTAT31to0  ================================================== */
49601 /* =================================================  DSP0RAWIRQSTAT63to32  ================================================== */
49602 /* =================================================  DSP0RAWIRQSTAT95to64  ================================================== */
49603 /* =====================================================  DSP0L2LVLINT  ====================================================== */
49604 /* =====================================================  DSP0L3LVLINT  ====================================================== */
49605 /* =====================================================  DSP0L4LVLINT  ====================================================== */
49606 /* =====================================================  DSP0L5LVLINT  ====================================================== */
49607 /* ====================================================  DSP0IDMATRIGCTL  ==================================================== */
49608 /* ==================================================  DSP0INTORMASK31TO0A  ================================================== */
49609 /* =================================================  DSP0INTORMASK63TO32A  ================================================== */
49610 /* =================================================  DSP0INTORMASK95TO64A  ================================================== */
49611 /* ==================================================  DSP0INTORMASK31to0B  ================================================== */
49612 /* =================================================  DSP0INTORMASK63TO32B  ================================================== */
49613 /* =================================================  DSP0INTORMASK95TO64B  ================================================== */
49614 /* ===================================================  DSP0INTENIRQ31TO0  =================================================== */
49615 /* ==================================================  DSP0INTENIRQ63TO32  =================================================== */
49616 /* ==================================================  DSP0INTENIRQ95TO64  =================================================== */
49617 /* ======================================================  DSP1CONTROL  ====================================================== */
49618 /* ==========================================  DSP DSP1CONTROL DSP1IDMATRIG [4..5]  ========================================== */
49619 typedef enum {                                  /*!< DSP_DSP1CONTROL_DSP1IDMATRIG                                              */
49620   DSP_DSP1CONTROL_DSP1IDMATRIG_XTRIG   = 3,     /*!< XTRIG : Trigger is disabled until a cross trigger pulse is asserted.
49621                                                      This will allow another source (determined by the XTRIGSRC
49622                                                      register) to allow the DMA descriptor chain to proceed.                   */
49623   DSP_DSP1CONTROL_DSP1IDMATRIG_SSTEP   = 2,     /*!< SSTEP : Trigger is disabled until a trigger pulse (PULSE in
49624                                                      IDMATRIG register) is asserted. This will allow a single
49625                                                      step in the DMA descriptor chain to be enabled until next
49626                                                      completion.                                                               */
49627   DSP_DSP1CONTROL_DSP1IDMATRIG_AON     = 1,     /*!< AON : Trigger is always enabled. With this set, any trigger
49628                                                      out will immediately generate a trigger in                                */
49629   DSP_DSP1CONTROL_DSP1IDMATRIG_DISABLE = 0,     /*!< DISABLE : Trigger is disabled. This will pause the iDMA indefinitely
49630                                                      until enabled.                                                            */
49631 } DSP_DSP1CONTROL_DSP1IDMATRIG_Enum;
49632 
49633 /* =====================================================  DSP1RESETVEC  ====================================================== */
49634 /* ======================================================  DSP1IRQMASK  ====================================================== */
49635 /* =====================================================  DSP1WAKEMASK  ====================================================== */
49636 /* ==================================================  DSP1RAWIRQSTAT31to0  ================================================== */
49637 /* =================================================  DSP1RAWIRQSTAT63to32  ================================================== */
49638 /* =================================================  DSP1RAWIRQSTAT95to64  ================================================== */
49639 /* =====================================================  DSP1L2LVLINT  ====================================================== */
49640 /* =====================================================  DSP1L3LVLINT  ====================================================== */
49641 /* =====================================================  DSP1L4LVLINT  ====================================================== */
49642 /* =====================================================  DSP1L5LVLINT  ====================================================== */
49643 /* ====================================================  DSP1IDMATRIGCTL  ==================================================== */
49644 /* ==================================================  DSP1INTORMASK31TO0A  ================================================== */
49645 /* =================================================  DSP1INTORMASK63TO32A  ================================================== */
49646 /* =================================================  DSP1INTORMASK95TO64A  ================================================== */
49647 /* ==================================================  DSP1INTORMASK31to0B  ================================================== */
49648 /* =================================================  DSP1INTORMASK63TO32B  ================================================== */
49649 /* =================================================  DSP1INTORMASK95TO64B  ================================================== */
49650 /* ===================================================  DSP1INTENIRQ31TO0  =================================================== */
49651 /* ==================================================  DSP1INTENIRQ63TO32  =================================================== */
49652 /* ==================================================  DSP1INTENIRQ95TO64  =================================================== */
49653 
49654 
49655 /* =========================================================================================================================== */
49656 /* ================                                           FPIO                                            ================ */
49657 /* =========================================================================================================================== */
49658 
49659 /* ==========================================================  RD0  ========================================================== */
49660 /* ==========================================================  RD1  ========================================================== */
49661 /* ==========================================================  RD2  ========================================================== */
49662 /* ==========================================================  RD3  ========================================================== */
49663 /* ==========================================================  WT0  ========================================================== */
49664 /* ==========================================================  WT1  ========================================================== */
49665 /* ==========================================================  WT2  ========================================================== */
49666 /* ==========================================================  WT3  ========================================================== */
49667 /* =========================================================  WTS0  ========================================================== */
49668 /* =========================================================  WTS1  ========================================================== */
49669 /* =========================================================  WTS2  ========================================================== */
49670 /* =========================================================  WTS3  ========================================================== */
49671 /* =========================================================  WTC0  ========================================================== */
49672 /* =========================================================  WTC1  ========================================================== */
49673 /* =========================================================  WTC2  ========================================================== */
49674 /* =========================================================  WTC3  ========================================================== */
49675 /* ==========================================================  EN0  ========================================================== */
49676 /* ==========================================================  EN1  ========================================================== */
49677 /* ==========================================================  EN2  ========================================================== */
49678 /* ==========================================================  EN3  ========================================================== */
49679 /* =========================================================  ENS0  ========================================================== */
49680 /* =========================================================  ENS1  ========================================================== */
49681 /* =========================================================  ENS2  ========================================================== */
49682 /* =========================================================  ENS3  ========================================================== */
49683 /* =========================================================  ENC0  ========================================================== */
49684 /* =========================================================  ENC1  ========================================================== */
49685 /* =========================================================  ENC2  ========================================================== */
49686 /* =========================================================  ENC3  ========================================================== */
49687 
49688 
49689 /* =========================================================================================================================== */
49690 /* ================                                           GPIO                                            ================ */
49691 /* =========================================================================================================================== */
49692 
49693 /* ========================================================  PINCFG0  ======================================================== */
49694 /* =============================================  GPIO PINCFG0 NCEPOL0 [22..22]  ============================================= */
49695 typedef enum {                                  /*!< GPIO_PINCFG0_NCEPOL0                                                      */
49696   GPIO_PINCFG0_NCEPOL0_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
49697   GPIO_PINCFG0_NCEPOL0_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
49698 } GPIO_PINCFG0_NCEPOL0_Enum;
49699 
49700 /* =============================================  GPIO PINCFG0 NCESRC0 [16..21]  ============================================= */
49701 typedef enum {                                  /*!< GPIO_PINCFG0_NCESRC0                                                      */
49702   GPIO_PINCFG0_NCESRC0_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
49703   GPIO_PINCFG0_NCESRC0_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
49704   GPIO_PINCFG0_NCESRC0_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
49705   GPIO_PINCFG0_NCESRC0_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
49706   GPIO_PINCFG0_NCESRC0_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
49707   GPIO_PINCFG0_NCESRC0_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
49708   GPIO_PINCFG0_NCESRC0_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
49709   GPIO_PINCFG0_NCESRC0_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
49710   GPIO_PINCFG0_NCESRC0_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
49711   GPIO_PINCFG0_NCESRC0_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
49712   GPIO_PINCFG0_NCESRC0_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
49713   GPIO_PINCFG0_NCESRC0_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
49714   GPIO_PINCFG0_NCESRC0_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
49715   GPIO_PINCFG0_NCESRC0_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
49716   GPIO_PINCFG0_NCESRC0_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
49717   GPIO_PINCFG0_NCESRC0_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
49718   GPIO_PINCFG0_NCESRC0_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
49719   GPIO_PINCFG0_NCESRC0_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
49720   GPIO_PINCFG0_NCESRC0_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
49721   GPIO_PINCFG0_NCESRC0_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
49722   GPIO_PINCFG0_NCESRC0_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
49723   GPIO_PINCFG0_NCESRC0_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
49724   GPIO_PINCFG0_NCESRC0_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
49725   GPIO_PINCFG0_NCESRC0_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
49726   GPIO_PINCFG0_NCESRC0_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
49727   GPIO_PINCFG0_NCESRC0_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
49728   GPIO_PINCFG0_NCESRC0_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
49729   GPIO_PINCFG0_NCESRC0_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
49730   GPIO_PINCFG0_NCESRC0_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
49731   GPIO_PINCFG0_NCESRC0_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
49732   GPIO_PINCFG0_NCESRC0_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
49733   GPIO_PINCFG0_NCESRC0_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
49734   GPIO_PINCFG0_NCESRC0_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
49735   GPIO_PINCFG0_NCESRC0_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
49736   GPIO_PINCFG0_NCESRC0_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
49737   GPIO_PINCFG0_NCESRC0_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
49738   GPIO_PINCFG0_NCESRC0_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
49739   GPIO_PINCFG0_NCESRC0_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
49740   GPIO_PINCFG0_NCESRC0_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
49741   GPIO_PINCFG0_NCESRC0_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
49742   GPIO_PINCFG0_NCESRC0_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
49743   GPIO_PINCFG0_NCESRC0_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
49744   GPIO_PINCFG0_NCESRC0_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
49745 } GPIO_PINCFG0_NCESRC0_Enum;
49746 
49747 /* ============================================  GPIO PINCFG0 PULLCFG0 [13..15]  ============================================= */
49748 typedef enum {                                  /*!< GPIO_PINCFG0_PULLCFG0                                                     */
49749   GPIO_PINCFG0_PULLCFG0_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
49750   GPIO_PINCFG0_PULLCFG0_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
49751   GPIO_PINCFG0_PULLCFG0_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
49752   GPIO_PINCFG0_PULLCFG0_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
49753   GPIO_PINCFG0_PULLCFG0_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
49754   GPIO_PINCFG0_PULLCFG0_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
49755   GPIO_PINCFG0_PULLCFG0_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
49756   GPIO_PINCFG0_PULLCFG0_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
49757 } GPIO_PINCFG0_PULLCFG0_Enum;
49758 
49759 /* ===============================================  GPIO PINCFG0 DS0 [10..11]  =============================================== */
49760 typedef enum {                                  /*!< GPIO_PINCFG0_DS0                                                          */
49761   GPIO_PINCFG0_DS0_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
49762   GPIO_PINCFG0_DS0_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
49763 } GPIO_PINCFG0_DS0_Enum;
49764 
49765 /* ==============================================  GPIO PINCFG0 OUTCFG0 [8..9]  ============================================== */
49766 typedef enum {                                  /*!< GPIO_PINCFG0_OUTCFG0                                                      */
49767   GPIO_PINCFG0_OUTCFG0_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
49768   GPIO_PINCFG0_OUTCFG0_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
49769                                                      and 1 values on pin.                                                      */
49770   GPIO_PINCFG0_OUTCFG0_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
49771                                                      low, tristate otherwise.                                                  */
49772   GPIO_PINCFG0_OUTCFG0_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
49773                                                      drive 0, 1 of HiZ on pin.                                                 */
49774 } GPIO_PINCFG0_OUTCFG0_Enum;
49775 
49776 /* ==============================================  GPIO PINCFG0 IRPTEN0 [6..7]  ============================================== */
49777 typedef enum {                                  /*!< GPIO_PINCFG0_IRPTEN0                                                      */
49778   GPIO_PINCFG0_IRPTEN0_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
49779   GPIO_PINCFG0_IRPTEN0_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
49780                                                      on this GPIO                                                              */
49781   GPIO_PINCFG0_IRPTEN0_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
49782                                                      on this GPIO                                                              */
49783   GPIO_PINCFG0_IRPTEN0_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
49784                                                      GPIO                                                                      */
49785 } GPIO_PINCFG0_IRPTEN0_Enum;
49786 
49787 /* ==============================================  GPIO PINCFG0 FNCSEL0 [0..3]  ============================================== */
49788 typedef enum {                                  /*!< GPIO_PINCFG0_FNCSEL0                                                      */
49789   GPIO_PINCFG0_FNCSEL0_SWTRACECLK      = 0,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
49790   GPIO_PINCFG0_FNCSEL0_SLSCL           = 1,     /*!< SLSCL : I2C Slave clock                                                   */
49791   GPIO_PINCFG0_FNCSEL0_SLSCK           = 2,     /*!< SLSCK : SPI Slave clock                                                   */
49792   GPIO_PINCFG0_FNCSEL0_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
49793   GPIO_PINCFG0_FNCSEL0_UART0TX         = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
49794   GPIO_PINCFG0_FNCSEL0_UART1TX         = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
49795   GPIO_PINCFG0_FNCSEL0_CT0             = 6,     /*!< CT0 : Timer/Counter input or output; Selection of direction
49796                                                      is done via CTIMER register settings.                                     */
49797   GPIO_PINCFG0_FNCSEL0_NCE0            = 7,     /*!< NCE0 : IOMSTR/MSPI N Chip Select. Polarity is determined by
49798                                                      CE_POLARITY field                                                         */
49799   GPIO_PINCFG0_FNCSEL0_OBSBUS0         = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
49800   GPIO_PINCFG0_FNCSEL0_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
49801   GPIO_PINCFG0_FNCSEL0_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
49802   GPIO_PINCFG0_FNCSEL0_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
49803   GPIO_PINCFG0_FNCSEL0_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
49804   GPIO_PINCFG0_FNCSEL0_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
49805   GPIO_PINCFG0_FNCSEL0_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
49806   GPIO_PINCFG0_FNCSEL0_RESERVED15      = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
49807 } GPIO_PINCFG0_FNCSEL0_Enum;
49808 
49809 /* ========================================================  PINCFG1  ======================================================== */
49810 /* =============================================  GPIO PINCFG1 NCEPOL1 [22..22]  ============================================= */
49811 typedef enum {                                  /*!< GPIO_PINCFG1_NCEPOL1                                                      */
49812   GPIO_PINCFG1_NCEPOL1_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
49813   GPIO_PINCFG1_NCEPOL1_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
49814 } GPIO_PINCFG1_NCEPOL1_Enum;
49815 
49816 /* =============================================  GPIO PINCFG1 NCESRC1 [16..21]  ============================================= */
49817 typedef enum {                                  /*!< GPIO_PINCFG1_NCESRC1                                                      */
49818   GPIO_PINCFG1_NCESRC1_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
49819   GPIO_PINCFG1_NCESRC1_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
49820   GPIO_PINCFG1_NCESRC1_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
49821   GPIO_PINCFG1_NCESRC1_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
49822   GPIO_PINCFG1_NCESRC1_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
49823   GPIO_PINCFG1_NCESRC1_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
49824   GPIO_PINCFG1_NCESRC1_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
49825   GPIO_PINCFG1_NCESRC1_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
49826   GPIO_PINCFG1_NCESRC1_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
49827   GPIO_PINCFG1_NCESRC1_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
49828   GPIO_PINCFG1_NCESRC1_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
49829   GPIO_PINCFG1_NCESRC1_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
49830   GPIO_PINCFG1_NCESRC1_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
49831   GPIO_PINCFG1_NCESRC1_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
49832   GPIO_PINCFG1_NCESRC1_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
49833   GPIO_PINCFG1_NCESRC1_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
49834   GPIO_PINCFG1_NCESRC1_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
49835   GPIO_PINCFG1_NCESRC1_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
49836   GPIO_PINCFG1_NCESRC1_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
49837   GPIO_PINCFG1_NCESRC1_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
49838   GPIO_PINCFG1_NCESRC1_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
49839   GPIO_PINCFG1_NCESRC1_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
49840   GPIO_PINCFG1_NCESRC1_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
49841   GPIO_PINCFG1_NCESRC1_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
49842   GPIO_PINCFG1_NCESRC1_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
49843   GPIO_PINCFG1_NCESRC1_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
49844   GPIO_PINCFG1_NCESRC1_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
49845   GPIO_PINCFG1_NCESRC1_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
49846   GPIO_PINCFG1_NCESRC1_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
49847   GPIO_PINCFG1_NCESRC1_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
49848   GPIO_PINCFG1_NCESRC1_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
49849   GPIO_PINCFG1_NCESRC1_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
49850   GPIO_PINCFG1_NCESRC1_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
49851   GPIO_PINCFG1_NCESRC1_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
49852   GPIO_PINCFG1_NCESRC1_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
49853   GPIO_PINCFG1_NCESRC1_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
49854   GPIO_PINCFG1_NCESRC1_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
49855   GPIO_PINCFG1_NCESRC1_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
49856   GPIO_PINCFG1_NCESRC1_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
49857   GPIO_PINCFG1_NCESRC1_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
49858   GPIO_PINCFG1_NCESRC1_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
49859   GPIO_PINCFG1_NCESRC1_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
49860   GPIO_PINCFG1_NCESRC1_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
49861 } GPIO_PINCFG1_NCESRC1_Enum;
49862 
49863 /* ============================================  GPIO PINCFG1 PULLCFG1 [13..15]  ============================================= */
49864 typedef enum {                                  /*!< GPIO_PINCFG1_PULLCFG1                                                     */
49865   GPIO_PINCFG1_PULLCFG1_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
49866   GPIO_PINCFG1_PULLCFG1_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
49867   GPIO_PINCFG1_PULLCFG1_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
49868   GPIO_PINCFG1_PULLCFG1_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
49869   GPIO_PINCFG1_PULLCFG1_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
49870   GPIO_PINCFG1_PULLCFG1_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
49871   GPIO_PINCFG1_PULLCFG1_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
49872   GPIO_PINCFG1_PULLCFG1_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
49873 } GPIO_PINCFG1_PULLCFG1_Enum;
49874 
49875 /* ===============================================  GPIO PINCFG1 DS1 [10..11]  =============================================== */
49876 typedef enum {                                  /*!< GPIO_PINCFG1_DS1                                                          */
49877   GPIO_PINCFG1_DS1_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
49878   GPIO_PINCFG1_DS1_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
49879 } GPIO_PINCFG1_DS1_Enum;
49880 
49881 /* ==============================================  GPIO PINCFG1 OUTCFG1 [8..9]  ============================================== */
49882 typedef enum {                                  /*!< GPIO_PINCFG1_OUTCFG1                                                      */
49883   GPIO_PINCFG1_OUTCFG1_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
49884   GPIO_PINCFG1_OUTCFG1_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
49885                                                      and 1 values on pin.                                                      */
49886   GPIO_PINCFG1_OUTCFG1_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
49887                                                      low, tristate otherwise.                                                  */
49888   GPIO_PINCFG1_OUTCFG1_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
49889                                                      drive 0, 1 of HiZ on pin.                                                 */
49890 } GPIO_PINCFG1_OUTCFG1_Enum;
49891 
49892 /* ==============================================  GPIO PINCFG1 IRPTEN1 [6..7]  ============================================== */
49893 typedef enum {                                  /*!< GPIO_PINCFG1_IRPTEN1                                                      */
49894   GPIO_PINCFG1_IRPTEN1_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
49895   GPIO_PINCFG1_IRPTEN1_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
49896                                                      on this GPIO                                                              */
49897   GPIO_PINCFG1_IRPTEN1_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
49898                                                      on this GPIO                                                              */
49899   GPIO_PINCFG1_IRPTEN1_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
49900                                                      GPIO                                                                      */
49901 } GPIO_PINCFG1_IRPTEN1_Enum;
49902 
49903 /* ==============================================  GPIO PINCFG1 FNCSEL1 [0..3]  ============================================== */
49904 typedef enum {                                  /*!< GPIO_PINCFG1_FNCSEL1                                                      */
49905   GPIO_PINCFG1_FNCSEL1_SWTRACE0        = 0,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
49906   GPIO_PINCFG1_FNCSEL1_SLSDAWIR3       = 1,     /*!< SLSDAWIR3 : I2C Slave I/O data (I2C) 3 Wire Data (SPI)                    */
49907   GPIO_PINCFG1_FNCSEL1_SLMOSI          = 2,     /*!< SLMOSI : SPI Slave input data                                             */
49908   GPIO_PINCFG1_FNCSEL1_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
49909   GPIO_PINCFG1_FNCSEL1_UART2TX         = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
49910   GPIO_PINCFG1_FNCSEL1_UART3TX         = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
49911   GPIO_PINCFG1_FNCSEL1_CT1             = 6,     /*!< CT1 : Timer/Counter input or output; Selection of direction
49912                                                      is done via CTIMER register settings.                                     */
49913   GPIO_PINCFG1_FNCSEL1_NCE1            = 7,     /*!< NCE1 : IOMSTR/MSPI N Chip Select. Polarity is determined by
49914                                                      CE_POLARITY field                                                         */
49915   GPIO_PINCFG1_FNCSEL1_OBSBUS1         = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
49916   GPIO_PINCFG1_FNCSEL1_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
49917   GPIO_PINCFG1_FNCSEL1_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
49918   GPIO_PINCFG1_FNCSEL1_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
49919   GPIO_PINCFG1_FNCSEL1_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
49920   GPIO_PINCFG1_FNCSEL1_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
49921   GPIO_PINCFG1_FNCSEL1_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
49922   GPIO_PINCFG1_FNCSEL1_SCANIN4         = 15,    /*!< SCANIN4 : Internal function (SCAN)                                        */
49923 } GPIO_PINCFG1_FNCSEL1_Enum;
49924 
49925 /* ========================================================  PINCFG2  ======================================================== */
49926 /* =============================================  GPIO PINCFG2 NCEPOL2 [22..22]  ============================================= */
49927 typedef enum {                                  /*!< GPIO_PINCFG2_NCEPOL2                                                      */
49928   GPIO_PINCFG2_NCEPOL2_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
49929   GPIO_PINCFG2_NCEPOL2_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
49930 } GPIO_PINCFG2_NCEPOL2_Enum;
49931 
49932 /* =============================================  GPIO PINCFG2 NCESRC2 [16..21]  ============================================= */
49933 typedef enum {                                  /*!< GPIO_PINCFG2_NCESRC2                                                      */
49934   GPIO_PINCFG2_NCESRC2_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
49935   GPIO_PINCFG2_NCESRC2_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
49936   GPIO_PINCFG2_NCESRC2_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
49937   GPIO_PINCFG2_NCESRC2_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
49938   GPIO_PINCFG2_NCESRC2_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
49939   GPIO_PINCFG2_NCESRC2_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
49940   GPIO_PINCFG2_NCESRC2_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
49941   GPIO_PINCFG2_NCESRC2_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
49942   GPIO_PINCFG2_NCESRC2_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
49943   GPIO_PINCFG2_NCESRC2_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
49944   GPIO_PINCFG2_NCESRC2_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
49945   GPIO_PINCFG2_NCESRC2_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
49946   GPIO_PINCFG2_NCESRC2_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
49947   GPIO_PINCFG2_NCESRC2_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
49948   GPIO_PINCFG2_NCESRC2_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
49949   GPIO_PINCFG2_NCESRC2_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
49950   GPIO_PINCFG2_NCESRC2_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
49951   GPIO_PINCFG2_NCESRC2_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
49952   GPIO_PINCFG2_NCESRC2_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
49953   GPIO_PINCFG2_NCESRC2_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
49954   GPIO_PINCFG2_NCESRC2_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
49955   GPIO_PINCFG2_NCESRC2_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
49956   GPIO_PINCFG2_NCESRC2_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
49957   GPIO_PINCFG2_NCESRC2_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
49958   GPIO_PINCFG2_NCESRC2_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
49959   GPIO_PINCFG2_NCESRC2_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
49960   GPIO_PINCFG2_NCESRC2_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
49961   GPIO_PINCFG2_NCESRC2_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
49962   GPIO_PINCFG2_NCESRC2_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
49963   GPIO_PINCFG2_NCESRC2_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
49964   GPIO_PINCFG2_NCESRC2_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
49965   GPIO_PINCFG2_NCESRC2_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
49966   GPIO_PINCFG2_NCESRC2_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
49967   GPIO_PINCFG2_NCESRC2_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
49968   GPIO_PINCFG2_NCESRC2_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
49969   GPIO_PINCFG2_NCESRC2_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
49970   GPIO_PINCFG2_NCESRC2_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
49971   GPIO_PINCFG2_NCESRC2_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
49972   GPIO_PINCFG2_NCESRC2_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
49973   GPIO_PINCFG2_NCESRC2_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
49974   GPIO_PINCFG2_NCESRC2_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
49975   GPIO_PINCFG2_NCESRC2_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
49976   GPIO_PINCFG2_NCESRC2_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
49977 } GPIO_PINCFG2_NCESRC2_Enum;
49978 
49979 /* ============================================  GPIO PINCFG2 PULLCFG2 [13..15]  ============================================= */
49980 typedef enum {                                  /*!< GPIO_PINCFG2_PULLCFG2                                                     */
49981   GPIO_PINCFG2_PULLCFG2_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
49982   GPIO_PINCFG2_PULLCFG2_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
49983   GPIO_PINCFG2_PULLCFG2_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
49984   GPIO_PINCFG2_PULLCFG2_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
49985   GPIO_PINCFG2_PULLCFG2_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
49986   GPIO_PINCFG2_PULLCFG2_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
49987   GPIO_PINCFG2_PULLCFG2_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
49988   GPIO_PINCFG2_PULLCFG2_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
49989 } GPIO_PINCFG2_PULLCFG2_Enum;
49990 
49991 /* ===============================================  GPIO PINCFG2 DS2 [10..11]  =============================================== */
49992 typedef enum {                                  /*!< GPIO_PINCFG2_DS2                                                          */
49993   GPIO_PINCFG2_DS2_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
49994   GPIO_PINCFG2_DS2_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
49995 } GPIO_PINCFG2_DS2_Enum;
49996 
49997 /* ==============================================  GPIO PINCFG2 OUTCFG2 [8..9]  ============================================== */
49998 typedef enum {                                  /*!< GPIO_PINCFG2_OUTCFG2                                                      */
49999   GPIO_PINCFG2_OUTCFG2_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50000   GPIO_PINCFG2_OUTCFG2_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50001                                                      and 1 values on pin.                                                      */
50002   GPIO_PINCFG2_OUTCFG2_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50003                                                      low, tristate otherwise.                                                  */
50004   GPIO_PINCFG2_OUTCFG2_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50005                                                      drive 0, 1 of HiZ on pin.                                                 */
50006 } GPIO_PINCFG2_OUTCFG2_Enum;
50007 
50008 /* ==============================================  GPIO PINCFG2 IRPTEN2 [6..7]  ============================================== */
50009 typedef enum {                                  /*!< GPIO_PINCFG2_IRPTEN2                                                      */
50010   GPIO_PINCFG2_IRPTEN2_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50011   GPIO_PINCFG2_IRPTEN2_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50012                                                      on this GPIO                                                              */
50013   GPIO_PINCFG2_IRPTEN2_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50014                                                      on this GPIO                                                              */
50015   GPIO_PINCFG2_IRPTEN2_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50016                                                      GPIO                                                                      */
50017 } GPIO_PINCFG2_IRPTEN2_Enum;
50018 
50019 /* ==============================================  GPIO PINCFG2 FNCSEL2 [0..3]  ============================================== */
50020 typedef enum {                                  /*!< GPIO_PINCFG2_FNCSEL2                                                      */
50021   GPIO_PINCFG2_FNCSEL2_SWTRACE1        = 0,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
50022   GPIO_PINCFG2_FNCSEL2_SLMISO          = 1,     /*!< SLMISO : SPI Slave output data                                            */
50023   GPIO_PINCFG2_FNCSEL2_TRIG1           = 2,     /*!< TRIG1 : ADC trigger input                                                 */
50024   GPIO_PINCFG2_FNCSEL2_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50025   GPIO_PINCFG2_FNCSEL2_UART0RX         = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
50026   GPIO_PINCFG2_FNCSEL2_UART1RX         = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
50027   GPIO_PINCFG2_FNCSEL2_CT2             = 6,     /*!< CT2 : Timer/Counter input or output; Selection of direction
50028                                                      is done via CTIMER register settings.                                     */
50029   GPIO_PINCFG2_FNCSEL2_NCE2            = 7,     /*!< NCE2 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50030                                                      CE_POLARITY field                                                         */
50031   GPIO_PINCFG2_FNCSEL2_OBSBUS2         = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
50032   GPIO_PINCFG2_FNCSEL2_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
50033   GPIO_PINCFG2_FNCSEL2_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
50034   GPIO_PINCFG2_FNCSEL2_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50035   GPIO_PINCFG2_FNCSEL2_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50036   GPIO_PINCFG2_FNCSEL2_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50037   GPIO_PINCFG2_FNCSEL2_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50038   GPIO_PINCFG2_FNCSEL2_SCANRSTN        = 15,    /*!< SCANRSTN : Internal function (SCAN)                                       */
50039 } GPIO_PINCFG2_FNCSEL2_Enum;
50040 
50041 /* ========================================================  PINCFG3  ======================================================== */
50042 /* =============================================  GPIO PINCFG3 NCEPOL3 [22..22]  ============================================= */
50043 typedef enum {                                  /*!< GPIO_PINCFG3_NCEPOL3                                                      */
50044   GPIO_PINCFG3_NCEPOL3_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50045   GPIO_PINCFG3_NCEPOL3_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50046 } GPIO_PINCFG3_NCEPOL3_Enum;
50047 
50048 /* =============================================  GPIO PINCFG3 NCESRC3 [16..21]  ============================================= */
50049 typedef enum {                                  /*!< GPIO_PINCFG3_NCESRC3                                                      */
50050   GPIO_PINCFG3_NCESRC3_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50051   GPIO_PINCFG3_NCESRC3_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50052   GPIO_PINCFG3_NCESRC3_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50053   GPIO_PINCFG3_NCESRC3_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50054   GPIO_PINCFG3_NCESRC3_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50055   GPIO_PINCFG3_NCESRC3_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50056   GPIO_PINCFG3_NCESRC3_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50057   GPIO_PINCFG3_NCESRC3_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50058   GPIO_PINCFG3_NCESRC3_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50059   GPIO_PINCFG3_NCESRC3_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50060   GPIO_PINCFG3_NCESRC3_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50061   GPIO_PINCFG3_NCESRC3_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50062   GPIO_PINCFG3_NCESRC3_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50063   GPIO_PINCFG3_NCESRC3_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50064   GPIO_PINCFG3_NCESRC3_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50065   GPIO_PINCFG3_NCESRC3_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50066   GPIO_PINCFG3_NCESRC3_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50067   GPIO_PINCFG3_NCESRC3_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50068   GPIO_PINCFG3_NCESRC3_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50069   GPIO_PINCFG3_NCESRC3_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50070   GPIO_PINCFG3_NCESRC3_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50071   GPIO_PINCFG3_NCESRC3_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50072   GPIO_PINCFG3_NCESRC3_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50073   GPIO_PINCFG3_NCESRC3_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50074   GPIO_PINCFG3_NCESRC3_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50075   GPIO_PINCFG3_NCESRC3_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50076   GPIO_PINCFG3_NCESRC3_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50077   GPIO_PINCFG3_NCESRC3_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50078   GPIO_PINCFG3_NCESRC3_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50079   GPIO_PINCFG3_NCESRC3_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50080   GPIO_PINCFG3_NCESRC3_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50081   GPIO_PINCFG3_NCESRC3_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50082   GPIO_PINCFG3_NCESRC3_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50083   GPIO_PINCFG3_NCESRC3_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50084   GPIO_PINCFG3_NCESRC3_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50085   GPIO_PINCFG3_NCESRC3_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50086   GPIO_PINCFG3_NCESRC3_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50087   GPIO_PINCFG3_NCESRC3_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50088   GPIO_PINCFG3_NCESRC3_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50089   GPIO_PINCFG3_NCESRC3_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50090   GPIO_PINCFG3_NCESRC3_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50091   GPIO_PINCFG3_NCESRC3_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50092   GPIO_PINCFG3_NCESRC3_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50093 } GPIO_PINCFG3_NCESRC3_Enum;
50094 
50095 /* ============================================  GPIO PINCFG3 PULLCFG3 [13..15]  ============================================= */
50096 typedef enum {                                  /*!< GPIO_PINCFG3_PULLCFG3                                                     */
50097   GPIO_PINCFG3_PULLCFG3_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50098   GPIO_PINCFG3_PULLCFG3_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50099   GPIO_PINCFG3_PULLCFG3_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50100   GPIO_PINCFG3_PULLCFG3_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50101   GPIO_PINCFG3_PULLCFG3_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50102   GPIO_PINCFG3_PULLCFG3_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50103   GPIO_PINCFG3_PULLCFG3_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50104   GPIO_PINCFG3_PULLCFG3_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50105 } GPIO_PINCFG3_PULLCFG3_Enum;
50106 
50107 /* ===============================================  GPIO PINCFG3 DS3 [10..11]  =============================================== */
50108 typedef enum {                                  /*!< GPIO_PINCFG3_DS3                                                          */
50109   GPIO_PINCFG3_DS3_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50110   GPIO_PINCFG3_DS3_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50111 } GPIO_PINCFG3_DS3_Enum;
50112 
50113 /* ==============================================  GPIO PINCFG3 OUTCFG3 [8..9]  ============================================== */
50114 typedef enum {                                  /*!< GPIO_PINCFG3_OUTCFG3                                                      */
50115   GPIO_PINCFG3_OUTCFG3_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50116   GPIO_PINCFG3_OUTCFG3_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50117                                                      and 1 values on pin.                                                      */
50118   GPIO_PINCFG3_OUTCFG3_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50119                                                      low, tristate otherwise.                                                  */
50120   GPIO_PINCFG3_OUTCFG3_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50121                                                      drive 0, 1 of HiZ on pin.                                                 */
50122 } GPIO_PINCFG3_OUTCFG3_Enum;
50123 
50124 /* ==============================================  GPIO PINCFG3 IRPTEN3 [6..7]  ============================================== */
50125 typedef enum {                                  /*!< GPIO_PINCFG3_IRPTEN3                                                      */
50126   GPIO_PINCFG3_IRPTEN3_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50127   GPIO_PINCFG3_IRPTEN3_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50128                                                      on this GPIO                                                              */
50129   GPIO_PINCFG3_IRPTEN3_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50130                                                      on this GPIO                                                              */
50131   GPIO_PINCFG3_IRPTEN3_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50132                                                      GPIO                                                                      */
50133 } GPIO_PINCFG3_IRPTEN3_Enum;
50134 
50135 /* ==============================================  GPIO PINCFG3 FNCSEL3 [0..3]  ============================================== */
50136 typedef enum {                                  /*!< GPIO_PINCFG3_FNCSEL3                                                      */
50137   GPIO_PINCFG3_FNCSEL3_SWTRACE2        = 0,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
50138   GPIO_PINCFG3_FNCSEL3_SLnCE           = 1,     /*!< SLnCE : SPI Slave chip enable                                             */
50139   GPIO_PINCFG3_FNCSEL3_SWO             = 2,     /*!< SWO : Serial Wire Output                                                  */
50140   GPIO_PINCFG3_FNCSEL3_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50141   GPIO_PINCFG3_FNCSEL3_UART2RX         = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
50142   GPIO_PINCFG3_FNCSEL3_UART3RX         = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
50143   GPIO_PINCFG3_FNCSEL3_CT3             = 6,     /*!< CT3 : Timer/Counter input or output; Selection of direction
50144                                                      is done via CTIMER register settings.                                     */
50145   GPIO_PINCFG3_FNCSEL3_NCE3            = 7,     /*!< NCE3 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50146                                                      CE_POLARITY field                                                         */
50147   GPIO_PINCFG3_FNCSEL3_OBSBUS3         = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
50148   GPIO_PINCFG3_FNCSEL3_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
50149   GPIO_PINCFG3_FNCSEL3_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
50150   GPIO_PINCFG3_FNCSEL3_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50151   GPIO_PINCFG3_FNCSEL3_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50152   GPIO_PINCFG3_FNCSEL3_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50153   GPIO_PINCFG3_FNCSEL3_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50154   GPIO_PINCFG3_FNCSEL3_SCANIN5         = 15,    /*!< SCANIN5 : Internal function (SCAN)                                        */
50155 } GPIO_PINCFG3_FNCSEL3_Enum;
50156 
50157 /* ========================================================  PINCFG4  ======================================================== */
50158 /* =============================================  GPIO PINCFG4 NCEPOL4 [22..22]  ============================================= */
50159 typedef enum {                                  /*!< GPIO_PINCFG4_NCEPOL4                                                      */
50160   GPIO_PINCFG4_NCEPOL4_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50161   GPIO_PINCFG4_NCEPOL4_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50162 } GPIO_PINCFG4_NCEPOL4_Enum;
50163 
50164 /* =============================================  GPIO PINCFG4 NCESRC4 [16..21]  ============================================= */
50165 typedef enum {                                  /*!< GPIO_PINCFG4_NCESRC4                                                      */
50166   GPIO_PINCFG4_NCESRC4_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50167   GPIO_PINCFG4_NCESRC4_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50168   GPIO_PINCFG4_NCESRC4_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50169   GPIO_PINCFG4_NCESRC4_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50170   GPIO_PINCFG4_NCESRC4_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50171   GPIO_PINCFG4_NCESRC4_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50172   GPIO_PINCFG4_NCESRC4_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50173   GPIO_PINCFG4_NCESRC4_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50174   GPIO_PINCFG4_NCESRC4_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50175   GPIO_PINCFG4_NCESRC4_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50176   GPIO_PINCFG4_NCESRC4_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50177   GPIO_PINCFG4_NCESRC4_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50178   GPIO_PINCFG4_NCESRC4_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50179   GPIO_PINCFG4_NCESRC4_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50180   GPIO_PINCFG4_NCESRC4_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50181   GPIO_PINCFG4_NCESRC4_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50182   GPIO_PINCFG4_NCESRC4_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50183   GPIO_PINCFG4_NCESRC4_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50184   GPIO_PINCFG4_NCESRC4_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50185   GPIO_PINCFG4_NCESRC4_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50186   GPIO_PINCFG4_NCESRC4_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50187   GPIO_PINCFG4_NCESRC4_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50188   GPIO_PINCFG4_NCESRC4_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50189   GPIO_PINCFG4_NCESRC4_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50190   GPIO_PINCFG4_NCESRC4_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50191   GPIO_PINCFG4_NCESRC4_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50192   GPIO_PINCFG4_NCESRC4_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50193   GPIO_PINCFG4_NCESRC4_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50194   GPIO_PINCFG4_NCESRC4_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50195   GPIO_PINCFG4_NCESRC4_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50196   GPIO_PINCFG4_NCESRC4_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50197   GPIO_PINCFG4_NCESRC4_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50198   GPIO_PINCFG4_NCESRC4_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50199   GPIO_PINCFG4_NCESRC4_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50200   GPIO_PINCFG4_NCESRC4_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50201   GPIO_PINCFG4_NCESRC4_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50202   GPIO_PINCFG4_NCESRC4_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50203   GPIO_PINCFG4_NCESRC4_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50204   GPIO_PINCFG4_NCESRC4_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50205   GPIO_PINCFG4_NCESRC4_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50206   GPIO_PINCFG4_NCESRC4_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50207   GPIO_PINCFG4_NCESRC4_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50208   GPIO_PINCFG4_NCESRC4_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50209 } GPIO_PINCFG4_NCESRC4_Enum;
50210 
50211 /* ============================================  GPIO PINCFG4 PULLCFG4 [13..15]  ============================================= */
50212 typedef enum {                                  /*!< GPIO_PINCFG4_PULLCFG4                                                     */
50213   GPIO_PINCFG4_PULLCFG4_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50214   GPIO_PINCFG4_PULLCFG4_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50215   GPIO_PINCFG4_PULLCFG4_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50216   GPIO_PINCFG4_PULLCFG4_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50217   GPIO_PINCFG4_PULLCFG4_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50218   GPIO_PINCFG4_PULLCFG4_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50219   GPIO_PINCFG4_PULLCFG4_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50220   GPIO_PINCFG4_PULLCFG4_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50221 } GPIO_PINCFG4_PULLCFG4_Enum;
50222 
50223 /* ===============================================  GPIO PINCFG4 DS4 [10..11]  =============================================== */
50224 typedef enum {                                  /*!< GPIO_PINCFG4_DS4                                                          */
50225   GPIO_PINCFG4_DS4_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50226   GPIO_PINCFG4_DS4_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50227 } GPIO_PINCFG4_DS4_Enum;
50228 
50229 /* ==============================================  GPIO PINCFG4 OUTCFG4 [8..9]  ============================================== */
50230 typedef enum {                                  /*!< GPIO_PINCFG4_OUTCFG4                                                      */
50231   GPIO_PINCFG4_OUTCFG4_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50232   GPIO_PINCFG4_OUTCFG4_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50233                                                      and 1 values on pin.                                                      */
50234   GPIO_PINCFG4_OUTCFG4_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50235                                                      low, tristate otherwise.                                                  */
50236   GPIO_PINCFG4_OUTCFG4_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50237                                                      drive 0, 1 of HiZ on pin.                                                 */
50238 } GPIO_PINCFG4_OUTCFG4_Enum;
50239 
50240 /* ==============================================  GPIO PINCFG4 IRPTEN4 [6..7]  ============================================== */
50241 typedef enum {                                  /*!< GPIO_PINCFG4_IRPTEN4                                                      */
50242   GPIO_PINCFG4_IRPTEN4_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50243   GPIO_PINCFG4_IRPTEN4_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50244                                                      on this GPIO                                                              */
50245   GPIO_PINCFG4_IRPTEN4_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50246                                                      on this GPIO                                                              */
50247   GPIO_PINCFG4_IRPTEN4_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50248                                                      GPIO                                                                      */
50249 } GPIO_PINCFG4_IRPTEN4_Enum;
50250 
50251 /* ==============================================  GPIO PINCFG4 FNCSEL4 [0..3]  ============================================== */
50252 typedef enum {                                  /*!< GPIO_PINCFG4_FNCSEL4                                                      */
50253   GPIO_PINCFG4_FNCSEL4_SWTRACE3        = 0,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
50254   GPIO_PINCFG4_FNCSEL4_SLINT           = 1,     /*!< SLINT : Configurable Slave Interrupt                                      */
50255   GPIO_PINCFG4_FNCSEL4_32KHzXT         = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
50256   GPIO_PINCFG4_FNCSEL4_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50257   GPIO_PINCFG4_FNCSEL4_UART0RTS        = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
50258   GPIO_PINCFG4_FNCSEL4_UART1RTS        = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
50259   GPIO_PINCFG4_FNCSEL4_CT4             = 6,     /*!< CT4 : Timer/Counter input or output; Selection of direction
50260                                                      is done via CTIMER register settings.                                     */
50261   GPIO_PINCFG4_FNCSEL4_NCE4            = 7,     /*!< NCE4 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50262                                                      CE_POLARITY field                                                         */
50263   GPIO_PINCFG4_FNCSEL4_OBSBUS4         = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
50264   GPIO_PINCFG4_FNCSEL4_I2S0_SDIN       = 9,     /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
50265   GPIO_PINCFG4_FNCSEL4_I2S1_SDIN       = 10,    /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
50266   GPIO_PINCFG4_FNCSEL4_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50267   GPIO_PINCFG4_FNCSEL4_FLB_TDO         = 12,    /*!< FLB_TDO : Internal function (Flash Bist)                                  */
50268   GPIO_PINCFG4_FNCSEL4_FLLOAD_DIR      = 13,    /*!< FLLOAD_DIR : Internal function (Flash parallel load)                      */
50269   GPIO_PINCFG4_FNCSEL4_MDA_TDO         = 14,    /*!< MDA_TDO : Internal function (MBIST)                                       */
50270   GPIO_PINCFG4_FNCSEL4_OPCG_TRIG       = 15,    /*!< OPCG_TRIG : Internal function (SCAN)                                      */
50271 } GPIO_PINCFG4_FNCSEL4_Enum;
50272 
50273 /* ========================================================  PINCFG5  ======================================================== */
50274 /* =============================================  GPIO PINCFG5 NCEPOL5 [22..22]  ============================================= */
50275 typedef enum {                                  /*!< GPIO_PINCFG5_NCEPOL5                                                      */
50276   GPIO_PINCFG5_NCEPOL5_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50277   GPIO_PINCFG5_NCEPOL5_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50278 } GPIO_PINCFG5_NCEPOL5_Enum;
50279 
50280 /* =============================================  GPIO PINCFG5 NCESRC5 [16..21]  ============================================= */
50281 typedef enum {                                  /*!< GPIO_PINCFG5_NCESRC5                                                      */
50282   GPIO_PINCFG5_NCESRC5_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50283   GPIO_PINCFG5_NCESRC5_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50284   GPIO_PINCFG5_NCESRC5_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50285   GPIO_PINCFG5_NCESRC5_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50286   GPIO_PINCFG5_NCESRC5_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50287   GPIO_PINCFG5_NCESRC5_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50288   GPIO_PINCFG5_NCESRC5_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50289   GPIO_PINCFG5_NCESRC5_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50290   GPIO_PINCFG5_NCESRC5_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50291   GPIO_PINCFG5_NCESRC5_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50292   GPIO_PINCFG5_NCESRC5_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50293   GPIO_PINCFG5_NCESRC5_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50294   GPIO_PINCFG5_NCESRC5_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50295   GPIO_PINCFG5_NCESRC5_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50296   GPIO_PINCFG5_NCESRC5_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50297   GPIO_PINCFG5_NCESRC5_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50298   GPIO_PINCFG5_NCESRC5_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50299   GPIO_PINCFG5_NCESRC5_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50300   GPIO_PINCFG5_NCESRC5_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50301   GPIO_PINCFG5_NCESRC5_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50302   GPIO_PINCFG5_NCESRC5_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50303   GPIO_PINCFG5_NCESRC5_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50304   GPIO_PINCFG5_NCESRC5_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50305   GPIO_PINCFG5_NCESRC5_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50306   GPIO_PINCFG5_NCESRC5_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50307   GPIO_PINCFG5_NCESRC5_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50308   GPIO_PINCFG5_NCESRC5_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50309   GPIO_PINCFG5_NCESRC5_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50310   GPIO_PINCFG5_NCESRC5_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50311   GPIO_PINCFG5_NCESRC5_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50312   GPIO_PINCFG5_NCESRC5_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50313   GPIO_PINCFG5_NCESRC5_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50314   GPIO_PINCFG5_NCESRC5_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50315   GPIO_PINCFG5_NCESRC5_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50316   GPIO_PINCFG5_NCESRC5_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50317   GPIO_PINCFG5_NCESRC5_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50318   GPIO_PINCFG5_NCESRC5_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50319   GPIO_PINCFG5_NCESRC5_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50320   GPIO_PINCFG5_NCESRC5_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50321   GPIO_PINCFG5_NCESRC5_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50322   GPIO_PINCFG5_NCESRC5_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50323   GPIO_PINCFG5_NCESRC5_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50324   GPIO_PINCFG5_NCESRC5_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50325 } GPIO_PINCFG5_NCESRC5_Enum;
50326 
50327 /* ============================================  GPIO PINCFG5 PULLCFG5 [13..15]  ============================================= */
50328 typedef enum {                                  /*!< GPIO_PINCFG5_PULLCFG5                                                     */
50329   GPIO_PINCFG5_PULLCFG5_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50330   GPIO_PINCFG5_PULLCFG5_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50331   GPIO_PINCFG5_PULLCFG5_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50332   GPIO_PINCFG5_PULLCFG5_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50333   GPIO_PINCFG5_PULLCFG5_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50334   GPIO_PINCFG5_PULLCFG5_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50335   GPIO_PINCFG5_PULLCFG5_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50336   GPIO_PINCFG5_PULLCFG5_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50337 } GPIO_PINCFG5_PULLCFG5_Enum;
50338 
50339 /* ===============================================  GPIO PINCFG5 DS5 [10..11]  =============================================== */
50340 typedef enum {                                  /*!< GPIO_PINCFG5_DS5                                                          */
50341   GPIO_PINCFG5_DS5_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50342   GPIO_PINCFG5_DS5_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50343   GPIO_PINCFG5_DS5_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
50344   GPIO_PINCFG5_DS5_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
50345 } GPIO_PINCFG5_DS5_Enum;
50346 
50347 /* ==============================================  GPIO PINCFG5 OUTCFG5 [8..9]  ============================================== */
50348 typedef enum {                                  /*!< GPIO_PINCFG5_OUTCFG5                                                      */
50349   GPIO_PINCFG5_OUTCFG5_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50350   GPIO_PINCFG5_OUTCFG5_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50351                                                      and 1 values on pin.                                                      */
50352   GPIO_PINCFG5_OUTCFG5_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50353                                                      low, tristate otherwise.                                                  */
50354   GPIO_PINCFG5_OUTCFG5_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50355                                                      drive 0, 1 of HiZ on pin.                                                 */
50356 } GPIO_PINCFG5_OUTCFG5_Enum;
50357 
50358 /* ==============================================  GPIO PINCFG5 IRPTEN5 [6..7]  ============================================== */
50359 typedef enum {                                  /*!< GPIO_PINCFG5_IRPTEN5                                                      */
50360   GPIO_PINCFG5_IRPTEN5_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50361   GPIO_PINCFG5_IRPTEN5_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50362                                                      on this GPIO                                                              */
50363   GPIO_PINCFG5_IRPTEN5_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50364                                                      on this GPIO                                                              */
50365   GPIO_PINCFG5_IRPTEN5_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50366                                                      GPIO                                                                      */
50367 } GPIO_PINCFG5_IRPTEN5_Enum;
50368 
50369 /* ==============================================  GPIO PINCFG5 FNCSEL5 [0..3]  ============================================== */
50370 typedef enum {                                  /*!< GPIO_PINCFG5_FNCSEL5                                                      */
50371   GPIO_PINCFG5_FNCSEL5_M0SCL           = 0,     /*!< M0SCL : Serial I2C Master Clock output (IOM 0)                            */
50372   GPIO_PINCFG5_FNCSEL5_M0SCK           = 1,     /*!< M0SCK : Serial SPI Master Clock output (IOM 0)                            */
50373   GPIO_PINCFG5_FNCSEL5_I2S0_CLK        = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
50374                                                      in master mode and input mode for slave mode. (I2S Master/Slave
50375                                                      2)                                                                        */
50376   GPIO_PINCFG5_FNCSEL5_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50377   GPIO_PINCFG5_FNCSEL5_UART2RTS        = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
50378   GPIO_PINCFG5_FNCSEL5_UART3RTS        = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
50379   GPIO_PINCFG5_FNCSEL5_CT5             = 6,     /*!< CT5 : Timer/Counter input or output; Selection of direction
50380                                                      is done via CTIMER register settings.                                     */
50381   GPIO_PINCFG5_FNCSEL5_NCE5            = 7,     /*!< NCE5 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50382                                                      CE_POLARITY field                                                         */
50383   GPIO_PINCFG5_FNCSEL5_OBSBUS5         = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
50384   GPIO_PINCFG5_FNCSEL5_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
50385   GPIO_PINCFG5_FNCSEL5_I2S1_CLK        = 10,    /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
50386                                                      in master mode and input mode for slave mode. (I2S Master/Slave
50387                                                      2)                                                                        */
50388   GPIO_PINCFG5_FNCSEL5_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50389   GPIO_PINCFG5_FNCSEL5_FLB_TDI         = 12,    /*!< FLB_TDI : Internal function (Flash Bist)                                  */
50390   GPIO_PINCFG5_FNCSEL5_FLLOAD_DATA     = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
50391   GPIO_PINCFG5_FNCSEL5_MDA_SRST        = 14,    /*!< MDA_SRST : Internal function (MBIST)                                      */
50392   GPIO_PINCFG5_FNCSEL5_DFT_ISO         = 15,    /*!< DFT_ISO : Internal function (SCAN)                                        */
50393 } GPIO_PINCFG5_FNCSEL5_Enum;
50394 
50395 /* ========================================================  PINCFG6  ======================================================== */
50396 /* =============================================  GPIO PINCFG6 NCEPOL6 [22..22]  ============================================= */
50397 typedef enum {                                  /*!< GPIO_PINCFG6_NCEPOL6                                                      */
50398   GPIO_PINCFG6_NCEPOL6_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50399   GPIO_PINCFG6_NCEPOL6_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50400 } GPIO_PINCFG6_NCEPOL6_Enum;
50401 
50402 /* =============================================  GPIO PINCFG6 NCESRC6 [16..21]  ============================================= */
50403 typedef enum {                                  /*!< GPIO_PINCFG6_NCESRC6                                                      */
50404   GPIO_PINCFG6_NCESRC6_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50405   GPIO_PINCFG6_NCESRC6_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50406   GPIO_PINCFG6_NCESRC6_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50407   GPIO_PINCFG6_NCESRC6_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50408   GPIO_PINCFG6_NCESRC6_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50409   GPIO_PINCFG6_NCESRC6_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50410   GPIO_PINCFG6_NCESRC6_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50411   GPIO_PINCFG6_NCESRC6_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50412   GPIO_PINCFG6_NCESRC6_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50413   GPIO_PINCFG6_NCESRC6_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50414   GPIO_PINCFG6_NCESRC6_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50415   GPIO_PINCFG6_NCESRC6_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50416   GPIO_PINCFG6_NCESRC6_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50417   GPIO_PINCFG6_NCESRC6_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50418   GPIO_PINCFG6_NCESRC6_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50419   GPIO_PINCFG6_NCESRC6_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50420   GPIO_PINCFG6_NCESRC6_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50421   GPIO_PINCFG6_NCESRC6_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50422   GPIO_PINCFG6_NCESRC6_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50423   GPIO_PINCFG6_NCESRC6_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50424   GPIO_PINCFG6_NCESRC6_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50425   GPIO_PINCFG6_NCESRC6_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50426   GPIO_PINCFG6_NCESRC6_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50427   GPIO_PINCFG6_NCESRC6_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50428   GPIO_PINCFG6_NCESRC6_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50429   GPIO_PINCFG6_NCESRC6_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50430   GPIO_PINCFG6_NCESRC6_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50431   GPIO_PINCFG6_NCESRC6_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50432   GPIO_PINCFG6_NCESRC6_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50433   GPIO_PINCFG6_NCESRC6_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50434   GPIO_PINCFG6_NCESRC6_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50435   GPIO_PINCFG6_NCESRC6_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50436   GPIO_PINCFG6_NCESRC6_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50437   GPIO_PINCFG6_NCESRC6_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50438   GPIO_PINCFG6_NCESRC6_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50439   GPIO_PINCFG6_NCESRC6_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50440   GPIO_PINCFG6_NCESRC6_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50441   GPIO_PINCFG6_NCESRC6_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50442   GPIO_PINCFG6_NCESRC6_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50443   GPIO_PINCFG6_NCESRC6_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50444   GPIO_PINCFG6_NCESRC6_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50445   GPIO_PINCFG6_NCESRC6_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50446   GPIO_PINCFG6_NCESRC6_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50447 } GPIO_PINCFG6_NCESRC6_Enum;
50448 
50449 /* ============================================  GPIO PINCFG6 PULLCFG6 [13..15]  ============================================= */
50450 typedef enum {                                  /*!< GPIO_PINCFG6_PULLCFG6                                                     */
50451   GPIO_PINCFG6_PULLCFG6_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50452   GPIO_PINCFG6_PULLCFG6_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50453   GPIO_PINCFG6_PULLCFG6_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50454   GPIO_PINCFG6_PULLCFG6_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50455   GPIO_PINCFG6_PULLCFG6_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50456   GPIO_PINCFG6_PULLCFG6_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50457   GPIO_PINCFG6_PULLCFG6_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50458   GPIO_PINCFG6_PULLCFG6_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50459 } GPIO_PINCFG6_PULLCFG6_Enum;
50460 
50461 /* ===============================================  GPIO PINCFG6 DS6 [10..11]  =============================================== */
50462 typedef enum {                                  /*!< GPIO_PINCFG6_DS6                                                          */
50463   GPIO_PINCFG6_DS6_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50464   GPIO_PINCFG6_DS6_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50465   GPIO_PINCFG6_DS6_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
50466   GPIO_PINCFG6_DS6_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
50467 } GPIO_PINCFG6_DS6_Enum;
50468 
50469 /* ==============================================  GPIO PINCFG6 OUTCFG6 [8..9]  ============================================== */
50470 typedef enum {                                  /*!< GPIO_PINCFG6_OUTCFG6                                                      */
50471   GPIO_PINCFG6_OUTCFG6_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50472   GPIO_PINCFG6_OUTCFG6_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50473                                                      and 1 values on pin.                                                      */
50474   GPIO_PINCFG6_OUTCFG6_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50475                                                      low, tristate otherwise.                                                  */
50476   GPIO_PINCFG6_OUTCFG6_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50477                                                      drive 0, 1 of HiZ on pin.                                                 */
50478 } GPIO_PINCFG6_OUTCFG6_Enum;
50479 
50480 /* ==============================================  GPIO PINCFG6 IRPTEN6 [6..7]  ============================================== */
50481 typedef enum {                                  /*!< GPIO_PINCFG6_IRPTEN6                                                      */
50482   GPIO_PINCFG6_IRPTEN6_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50483   GPIO_PINCFG6_IRPTEN6_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50484                                                      on this GPIO                                                              */
50485   GPIO_PINCFG6_IRPTEN6_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50486                                                      on this GPIO                                                              */
50487   GPIO_PINCFG6_IRPTEN6_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50488                                                      GPIO                                                                      */
50489 } GPIO_PINCFG6_IRPTEN6_Enum;
50490 
50491 /* ==============================================  GPIO PINCFG6 FNCSEL6 [0..3]  ============================================== */
50492 typedef enum {                                  /*!< GPIO_PINCFG6_FNCSEL6                                                      */
50493   GPIO_PINCFG6_FNCSEL6_M0SDAWIR3       = 0,     /*!< M0SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
50494                                                      Master Data I/O (SPI 3 wire mode) (IOM 0)                                 */
50495   GPIO_PINCFG6_FNCSEL6_M0MOSI          = 1,     /*!< M0MOSI : Serial SPI Master MOSI output (IOM 0)                            */
50496   GPIO_PINCFG6_FNCSEL6_I2S0_DATA       = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
50497                                                      in master mode and input mode for slave mode. (I2S Master/Slave
50498                                                      2)                                                                        */
50499   GPIO_PINCFG6_FNCSEL6_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50500   GPIO_PINCFG6_FNCSEL6_UART0CTS        = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
50501   GPIO_PINCFG6_FNCSEL6_UART1CTS        = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
50502   GPIO_PINCFG6_FNCSEL6_CT6             = 6,     /*!< CT6 : Timer/Counter input or output; Selection of direction
50503                                                      is done via CTIMER register settings.                                     */
50504   GPIO_PINCFG6_FNCSEL6_NCE6            = 7,     /*!< NCE6 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50505                                                      CE_POLARITY field                                                         */
50506   GPIO_PINCFG6_FNCSEL6_OBSBUS6         = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
50507   GPIO_PINCFG6_FNCSEL6_I2S0_SDOUT      = 9,     /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
50508   GPIO_PINCFG6_FNCSEL6_I2S1_SDOUT      = 10,    /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
50509   GPIO_PINCFG6_FNCSEL6_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50510   GPIO_PINCFG6_FNCSEL6_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50511   GPIO_PINCFG6_FNCSEL6_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50512   GPIO_PINCFG6_FNCSEL6_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50513   GPIO_PINCFG6_FNCSEL6_SCANIN6         = 15,    /*!< SCANIN6 : Internal function (SCAN)                                        */
50514 } GPIO_PINCFG6_FNCSEL6_Enum;
50515 
50516 /* ========================================================  PINCFG7  ======================================================== */
50517 /* =============================================  GPIO PINCFG7 NCEPOL7 [22..22]  ============================================= */
50518 typedef enum {                                  /*!< GPIO_PINCFG7_NCEPOL7                                                      */
50519   GPIO_PINCFG7_NCEPOL7_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50520   GPIO_PINCFG7_NCEPOL7_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50521 } GPIO_PINCFG7_NCEPOL7_Enum;
50522 
50523 /* =============================================  GPIO PINCFG7 NCESRC7 [16..21]  ============================================= */
50524 typedef enum {                                  /*!< GPIO_PINCFG7_NCESRC7                                                      */
50525   GPIO_PINCFG7_NCESRC7_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50526   GPIO_PINCFG7_NCESRC7_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50527   GPIO_PINCFG7_NCESRC7_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50528   GPIO_PINCFG7_NCESRC7_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50529   GPIO_PINCFG7_NCESRC7_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50530   GPIO_PINCFG7_NCESRC7_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50531   GPIO_PINCFG7_NCESRC7_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50532   GPIO_PINCFG7_NCESRC7_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50533   GPIO_PINCFG7_NCESRC7_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50534   GPIO_PINCFG7_NCESRC7_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50535   GPIO_PINCFG7_NCESRC7_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50536   GPIO_PINCFG7_NCESRC7_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50537   GPIO_PINCFG7_NCESRC7_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50538   GPIO_PINCFG7_NCESRC7_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50539   GPIO_PINCFG7_NCESRC7_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50540   GPIO_PINCFG7_NCESRC7_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50541   GPIO_PINCFG7_NCESRC7_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50542   GPIO_PINCFG7_NCESRC7_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50543   GPIO_PINCFG7_NCESRC7_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50544   GPIO_PINCFG7_NCESRC7_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50545   GPIO_PINCFG7_NCESRC7_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50546   GPIO_PINCFG7_NCESRC7_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50547   GPIO_PINCFG7_NCESRC7_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50548   GPIO_PINCFG7_NCESRC7_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50549   GPIO_PINCFG7_NCESRC7_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50550   GPIO_PINCFG7_NCESRC7_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50551   GPIO_PINCFG7_NCESRC7_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50552   GPIO_PINCFG7_NCESRC7_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50553   GPIO_PINCFG7_NCESRC7_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50554   GPIO_PINCFG7_NCESRC7_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50555   GPIO_PINCFG7_NCESRC7_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50556   GPIO_PINCFG7_NCESRC7_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50557   GPIO_PINCFG7_NCESRC7_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50558   GPIO_PINCFG7_NCESRC7_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50559   GPIO_PINCFG7_NCESRC7_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50560   GPIO_PINCFG7_NCESRC7_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50561   GPIO_PINCFG7_NCESRC7_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50562   GPIO_PINCFG7_NCESRC7_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50563   GPIO_PINCFG7_NCESRC7_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50564   GPIO_PINCFG7_NCESRC7_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50565   GPIO_PINCFG7_NCESRC7_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50566   GPIO_PINCFG7_NCESRC7_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50567   GPIO_PINCFG7_NCESRC7_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50568 } GPIO_PINCFG7_NCESRC7_Enum;
50569 
50570 /* ============================================  GPIO PINCFG7 PULLCFG7 [13..15]  ============================================= */
50571 typedef enum {                                  /*!< GPIO_PINCFG7_PULLCFG7                                                     */
50572   GPIO_PINCFG7_PULLCFG7_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50573   GPIO_PINCFG7_PULLCFG7_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50574   GPIO_PINCFG7_PULLCFG7_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50575   GPIO_PINCFG7_PULLCFG7_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50576   GPIO_PINCFG7_PULLCFG7_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50577   GPIO_PINCFG7_PULLCFG7_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50578   GPIO_PINCFG7_PULLCFG7_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50579   GPIO_PINCFG7_PULLCFG7_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50580 } GPIO_PINCFG7_PULLCFG7_Enum;
50581 
50582 /* ===============================================  GPIO PINCFG7 DS7 [10..11]  =============================================== */
50583 typedef enum {                                  /*!< GPIO_PINCFG7_DS7                                                          */
50584   GPIO_PINCFG7_DS7_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50585   GPIO_PINCFG7_DS7_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50586   GPIO_PINCFG7_DS7_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
50587   GPIO_PINCFG7_DS7_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
50588 } GPIO_PINCFG7_DS7_Enum;
50589 
50590 /* ==============================================  GPIO PINCFG7 OUTCFG7 [8..9]  ============================================== */
50591 typedef enum {                                  /*!< GPIO_PINCFG7_OUTCFG7                                                      */
50592   GPIO_PINCFG7_OUTCFG7_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50593   GPIO_PINCFG7_OUTCFG7_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50594                                                      and 1 values on pin.                                                      */
50595   GPIO_PINCFG7_OUTCFG7_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50596                                                      low, tristate otherwise.                                                  */
50597   GPIO_PINCFG7_OUTCFG7_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50598                                                      drive 0, 1 of HiZ on pin.                                                 */
50599 } GPIO_PINCFG7_OUTCFG7_Enum;
50600 
50601 /* ==============================================  GPIO PINCFG7 IRPTEN7 [6..7]  ============================================== */
50602 typedef enum {                                  /*!< GPIO_PINCFG7_IRPTEN7                                                      */
50603   GPIO_PINCFG7_IRPTEN7_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50604   GPIO_PINCFG7_IRPTEN7_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50605                                                      on this GPIO                                                              */
50606   GPIO_PINCFG7_IRPTEN7_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50607                                                      on this GPIO                                                              */
50608   GPIO_PINCFG7_IRPTEN7_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50609                                                      GPIO                                                                      */
50610 } GPIO_PINCFG7_IRPTEN7_Enum;
50611 
50612 /* ==============================================  GPIO PINCFG7 FNCSEL7 [0..3]  ============================================== */
50613 typedef enum {                                  /*!< GPIO_PINCFG7_FNCSEL7                                                      */
50614   GPIO_PINCFG7_FNCSEL7_M0MISO          = 0,     /*!< M0MISO : Serial SPI MASTER MISO input (IOM 0)                             */
50615   GPIO_PINCFG7_FNCSEL7_TRIG0           = 1,     /*!< TRIG0 : ADC trigger input                                                 */
50616   GPIO_PINCFG7_FNCSEL7_I2S0_WS         = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
50617                                                      in master mode and input mode for slave mode. (I2S Master/Slave
50618                                                      2)                                                                        */
50619   GPIO_PINCFG7_FNCSEL7_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50620   GPIO_PINCFG7_FNCSEL7_UART2CTS        = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
50621   GPIO_PINCFG7_FNCSEL7_UART3CTS        = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
50622   GPIO_PINCFG7_FNCSEL7_CT7             = 6,     /*!< CT7 : Timer/Counter input or output; Selection of direction
50623                                                      is done via CTIMER register settings.                                     */
50624   GPIO_PINCFG7_FNCSEL7_NCE7            = 7,     /*!< NCE7 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50625                                                      CE_POLARITY field                                                         */
50626   GPIO_PINCFG7_FNCSEL7_OBSBUS7         = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
50627   GPIO_PINCFG7_FNCSEL7_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
50628   GPIO_PINCFG7_FNCSEL7_I2S1_WS         = 10,    /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
50629                                                      in master mode and input mode for slave mode. (I2S Master/Slave
50630                                                      2)                                                                        */
50631   GPIO_PINCFG7_FNCSEL7_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50632   GPIO_PINCFG7_FNCSEL7_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50633   GPIO_PINCFG7_FNCSEL7_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50634   GPIO_PINCFG7_FNCSEL7_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50635   GPIO_PINCFG7_FNCSEL7_SCANIN7         = 15,    /*!< SCANIN7 : Internal function (SCAN)                                        */
50636 } GPIO_PINCFG7_FNCSEL7_Enum;
50637 
50638 /* ========================================================  PINCFG8  ======================================================== */
50639 /* =============================================  GPIO PINCFG8 NCEPOL8 [22..22]  ============================================= */
50640 typedef enum {                                  /*!< GPIO_PINCFG8_NCEPOL8                                                      */
50641   GPIO_PINCFG8_NCEPOL8_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50642   GPIO_PINCFG8_NCEPOL8_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50643 } GPIO_PINCFG8_NCEPOL8_Enum;
50644 
50645 /* =============================================  GPIO PINCFG8 NCESRC8 [16..21]  ============================================= */
50646 typedef enum {                                  /*!< GPIO_PINCFG8_NCESRC8                                                      */
50647   GPIO_PINCFG8_NCESRC8_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50648   GPIO_PINCFG8_NCESRC8_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50649   GPIO_PINCFG8_NCESRC8_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50650   GPIO_PINCFG8_NCESRC8_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50651   GPIO_PINCFG8_NCESRC8_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50652   GPIO_PINCFG8_NCESRC8_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50653   GPIO_PINCFG8_NCESRC8_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50654   GPIO_PINCFG8_NCESRC8_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50655   GPIO_PINCFG8_NCESRC8_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50656   GPIO_PINCFG8_NCESRC8_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50657   GPIO_PINCFG8_NCESRC8_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50658   GPIO_PINCFG8_NCESRC8_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50659   GPIO_PINCFG8_NCESRC8_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50660   GPIO_PINCFG8_NCESRC8_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50661   GPIO_PINCFG8_NCESRC8_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50662   GPIO_PINCFG8_NCESRC8_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50663   GPIO_PINCFG8_NCESRC8_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50664   GPIO_PINCFG8_NCESRC8_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50665   GPIO_PINCFG8_NCESRC8_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50666   GPIO_PINCFG8_NCESRC8_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50667   GPIO_PINCFG8_NCESRC8_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50668   GPIO_PINCFG8_NCESRC8_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50669   GPIO_PINCFG8_NCESRC8_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50670   GPIO_PINCFG8_NCESRC8_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50671   GPIO_PINCFG8_NCESRC8_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50672   GPIO_PINCFG8_NCESRC8_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50673   GPIO_PINCFG8_NCESRC8_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50674   GPIO_PINCFG8_NCESRC8_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50675   GPIO_PINCFG8_NCESRC8_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50676   GPIO_PINCFG8_NCESRC8_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50677   GPIO_PINCFG8_NCESRC8_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50678   GPIO_PINCFG8_NCESRC8_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50679   GPIO_PINCFG8_NCESRC8_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50680   GPIO_PINCFG8_NCESRC8_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50681   GPIO_PINCFG8_NCESRC8_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50682   GPIO_PINCFG8_NCESRC8_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50683   GPIO_PINCFG8_NCESRC8_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50684   GPIO_PINCFG8_NCESRC8_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50685   GPIO_PINCFG8_NCESRC8_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50686   GPIO_PINCFG8_NCESRC8_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50687   GPIO_PINCFG8_NCESRC8_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50688   GPIO_PINCFG8_NCESRC8_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50689   GPIO_PINCFG8_NCESRC8_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50690 } GPIO_PINCFG8_NCESRC8_Enum;
50691 
50692 /* ============================================  GPIO PINCFG8 PULLCFG8 [13..15]  ============================================= */
50693 typedef enum {                                  /*!< GPIO_PINCFG8_PULLCFG8                                                     */
50694   GPIO_PINCFG8_PULLCFG8_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50695   GPIO_PINCFG8_PULLCFG8_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50696   GPIO_PINCFG8_PULLCFG8_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50697   GPIO_PINCFG8_PULLCFG8_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50698   GPIO_PINCFG8_PULLCFG8_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50699   GPIO_PINCFG8_PULLCFG8_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50700   GPIO_PINCFG8_PULLCFG8_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50701   GPIO_PINCFG8_PULLCFG8_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50702 } GPIO_PINCFG8_PULLCFG8_Enum;
50703 
50704 /* ===============================================  GPIO PINCFG8 DS8 [10..11]  =============================================== */
50705 typedef enum {                                  /*!< GPIO_PINCFG8_DS8                                                          */
50706   GPIO_PINCFG8_DS8_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50707   GPIO_PINCFG8_DS8_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50708   GPIO_PINCFG8_DS8_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
50709   GPIO_PINCFG8_DS8_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
50710 } GPIO_PINCFG8_DS8_Enum;
50711 
50712 /* ==============================================  GPIO PINCFG8 OUTCFG8 [8..9]  ============================================== */
50713 typedef enum {                                  /*!< GPIO_PINCFG8_OUTCFG8                                                      */
50714   GPIO_PINCFG8_OUTCFG8_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50715   GPIO_PINCFG8_OUTCFG8_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50716                                                      and 1 values on pin.                                                      */
50717   GPIO_PINCFG8_OUTCFG8_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50718                                                      low, tristate otherwise.                                                  */
50719   GPIO_PINCFG8_OUTCFG8_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50720                                                      drive 0, 1 of HiZ on pin.                                                 */
50721 } GPIO_PINCFG8_OUTCFG8_Enum;
50722 
50723 /* ==============================================  GPIO PINCFG8 IRPTEN8 [6..7]  ============================================== */
50724 typedef enum {                                  /*!< GPIO_PINCFG8_IRPTEN8                                                      */
50725   GPIO_PINCFG8_IRPTEN8_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50726   GPIO_PINCFG8_IRPTEN8_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50727                                                      on this GPIO                                                              */
50728   GPIO_PINCFG8_IRPTEN8_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50729                                                      on this GPIO                                                              */
50730   GPIO_PINCFG8_IRPTEN8_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50731                                                      GPIO                                                                      */
50732 } GPIO_PINCFG8_IRPTEN8_Enum;
50733 
50734 /* ==============================================  GPIO PINCFG8 FNCSEL8 [0..3]  ============================================== */
50735 typedef enum {                                  /*!< GPIO_PINCFG8_FNCSEL8                                                      */
50736   GPIO_PINCFG8_FNCSEL8_CMPRF1          = 0,     /*!< CMPRF1 : Comparator reference 1                                           */
50737   GPIO_PINCFG8_FNCSEL8_TRIG1           = 1,     /*!< TRIG1 : ADC trigger input                                                 */
50738   GPIO_PINCFG8_FNCSEL8_RESERVED2       = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
50739   GPIO_PINCFG8_FNCSEL8_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50740   GPIO_PINCFG8_FNCSEL8_M1SCL           = 4,     /*!< M1SCL : Serial I2C Master Clock output (IOM 1)                            */
50741   GPIO_PINCFG8_FNCSEL8_M1SCK           = 5,     /*!< M1SCK : Serial SPI Master Clock output (IOM 1)                            */
50742   GPIO_PINCFG8_FNCSEL8_CT8             = 6,     /*!< CT8 : Timer/Counter input or output; Selection of direction
50743                                                      is done via CTIMER register settings.                                     */
50744   GPIO_PINCFG8_FNCSEL8_NCE8            = 7,     /*!< NCE8 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50745                                                      CE_POLARITY field                                                         */
50746   GPIO_PINCFG8_FNCSEL8_OBSBUS8         = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
50747   GPIO_PINCFG8_FNCSEL8_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
50748   GPIO_PINCFG8_FNCSEL8_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
50749   GPIO_PINCFG8_FNCSEL8_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50750   GPIO_PINCFG8_FNCSEL8_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50751   GPIO_PINCFG8_FNCSEL8_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50752   GPIO_PINCFG8_FNCSEL8_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50753   GPIO_PINCFG8_FNCSEL8_SCANOUT4        = 15,    /*!< SCANOUT4 : Internal function (SCAN)                                       */
50754 } GPIO_PINCFG8_FNCSEL8_Enum;
50755 
50756 /* ========================================================  PINCFG9  ======================================================== */
50757 /* =============================================  GPIO PINCFG9 NCEPOL9 [22..22]  ============================================= */
50758 typedef enum {                                  /*!< GPIO_PINCFG9_NCEPOL9                                                      */
50759   GPIO_PINCFG9_NCEPOL9_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50760   GPIO_PINCFG9_NCEPOL9_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50761 } GPIO_PINCFG9_NCEPOL9_Enum;
50762 
50763 /* =============================================  GPIO PINCFG9 NCESRC9 [16..21]  ============================================= */
50764 typedef enum {                                  /*!< GPIO_PINCFG9_NCESRC9                                                      */
50765   GPIO_PINCFG9_NCESRC9_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50766   GPIO_PINCFG9_NCESRC9_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50767   GPIO_PINCFG9_NCESRC9_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50768   GPIO_PINCFG9_NCESRC9_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50769   GPIO_PINCFG9_NCESRC9_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50770   GPIO_PINCFG9_NCESRC9_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50771   GPIO_PINCFG9_NCESRC9_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50772   GPIO_PINCFG9_NCESRC9_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50773   GPIO_PINCFG9_NCESRC9_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50774   GPIO_PINCFG9_NCESRC9_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50775   GPIO_PINCFG9_NCESRC9_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50776   GPIO_PINCFG9_NCESRC9_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50777   GPIO_PINCFG9_NCESRC9_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50778   GPIO_PINCFG9_NCESRC9_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50779   GPIO_PINCFG9_NCESRC9_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50780   GPIO_PINCFG9_NCESRC9_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50781   GPIO_PINCFG9_NCESRC9_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50782   GPIO_PINCFG9_NCESRC9_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50783   GPIO_PINCFG9_NCESRC9_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50784   GPIO_PINCFG9_NCESRC9_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50785   GPIO_PINCFG9_NCESRC9_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50786   GPIO_PINCFG9_NCESRC9_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50787   GPIO_PINCFG9_NCESRC9_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50788   GPIO_PINCFG9_NCESRC9_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50789   GPIO_PINCFG9_NCESRC9_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50790   GPIO_PINCFG9_NCESRC9_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50791   GPIO_PINCFG9_NCESRC9_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50792   GPIO_PINCFG9_NCESRC9_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50793   GPIO_PINCFG9_NCESRC9_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50794   GPIO_PINCFG9_NCESRC9_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50795   GPIO_PINCFG9_NCESRC9_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50796   GPIO_PINCFG9_NCESRC9_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50797   GPIO_PINCFG9_NCESRC9_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50798   GPIO_PINCFG9_NCESRC9_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50799   GPIO_PINCFG9_NCESRC9_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50800   GPIO_PINCFG9_NCESRC9_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50801   GPIO_PINCFG9_NCESRC9_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50802   GPIO_PINCFG9_NCESRC9_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50803   GPIO_PINCFG9_NCESRC9_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50804   GPIO_PINCFG9_NCESRC9_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50805   GPIO_PINCFG9_NCESRC9_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50806   GPIO_PINCFG9_NCESRC9_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50807   GPIO_PINCFG9_NCESRC9_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50808 } GPIO_PINCFG9_NCESRC9_Enum;
50809 
50810 /* ============================================  GPIO PINCFG9 PULLCFG9 [13..15]  ============================================= */
50811 typedef enum {                                  /*!< GPIO_PINCFG9_PULLCFG9                                                     */
50812   GPIO_PINCFG9_PULLCFG9_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50813   GPIO_PINCFG9_PULLCFG9_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50814   GPIO_PINCFG9_PULLCFG9_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50815   GPIO_PINCFG9_PULLCFG9_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50816   GPIO_PINCFG9_PULLCFG9_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50817   GPIO_PINCFG9_PULLCFG9_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50818   GPIO_PINCFG9_PULLCFG9_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50819   GPIO_PINCFG9_PULLCFG9_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50820 } GPIO_PINCFG9_PULLCFG9_Enum;
50821 
50822 /* ===============================================  GPIO PINCFG9 DS9 [10..11]  =============================================== */
50823 typedef enum {                                  /*!< GPIO_PINCFG9_DS9                                                          */
50824   GPIO_PINCFG9_DS9_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50825   GPIO_PINCFG9_DS9_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50826   GPIO_PINCFG9_DS9_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
50827   GPIO_PINCFG9_DS9_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
50828 } GPIO_PINCFG9_DS9_Enum;
50829 
50830 /* ==============================================  GPIO PINCFG9 OUTCFG9 [8..9]  ============================================== */
50831 typedef enum {                                  /*!< GPIO_PINCFG9_OUTCFG9                                                      */
50832   GPIO_PINCFG9_OUTCFG9_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50833   GPIO_PINCFG9_OUTCFG9_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50834                                                      and 1 values on pin.                                                      */
50835   GPIO_PINCFG9_OUTCFG9_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50836                                                      low, tristate otherwise.                                                  */
50837   GPIO_PINCFG9_OUTCFG9_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50838                                                      drive 0, 1 of HiZ on pin.                                                 */
50839 } GPIO_PINCFG9_OUTCFG9_Enum;
50840 
50841 /* ==============================================  GPIO PINCFG9 IRPTEN9 [6..7]  ============================================== */
50842 typedef enum {                                  /*!< GPIO_PINCFG9_IRPTEN9                                                      */
50843   GPIO_PINCFG9_IRPTEN9_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50844   GPIO_PINCFG9_IRPTEN9_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50845                                                      on this GPIO                                                              */
50846   GPIO_PINCFG9_IRPTEN9_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50847                                                      on this GPIO                                                              */
50848   GPIO_PINCFG9_IRPTEN9_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50849                                                      GPIO                                                                      */
50850 } GPIO_PINCFG9_IRPTEN9_Enum;
50851 
50852 /* ==============================================  GPIO PINCFG9 FNCSEL9 [0..3]  ============================================== */
50853 typedef enum {                                  /*!< GPIO_PINCFG9_FNCSEL9                                                      */
50854   GPIO_PINCFG9_FNCSEL9_CMPRF0          = 0,     /*!< CMPRF0 : Comparator reference 0                                           */
50855   GPIO_PINCFG9_FNCSEL9_TRIG2           = 1,     /*!< TRIG2 : ADC trigger input                                                 */
50856   GPIO_PINCFG9_FNCSEL9_RESERVED2       = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
50857   GPIO_PINCFG9_FNCSEL9_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50858   GPIO_PINCFG9_FNCSEL9_M1SDAWIR3       = 4,     /*!< M1SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
50859                                                      Master Data I/O (SPI 3 wire mode) (IOM 1)                                 */
50860   GPIO_PINCFG9_FNCSEL9_M1MOSI          = 5,     /*!< M1MOSI : Serial SPI Master MOSI output (IOM 1)                            */
50861   GPIO_PINCFG9_FNCSEL9_CT9             = 6,     /*!< CT9 : Timer/Counter input or output; Selection of direction
50862                                                      is done via CTIMER register settings.                                     */
50863   GPIO_PINCFG9_FNCSEL9_NCE9            = 7,     /*!< NCE9 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50864                                                      CE_POLARITY field                                                         */
50865   GPIO_PINCFG9_FNCSEL9_OBSBUS9         = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
50866   GPIO_PINCFG9_FNCSEL9_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
50867   GPIO_PINCFG9_FNCSEL9_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
50868   GPIO_PINCFG9_FNCSEL9_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50869   GPIO_PINCFG9_FNCSEL9_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50870   GPIO_PINCFG9_FNCSEL9_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50871   GPIO_PINCFG9_FNCSEL9_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50872   GPIO_PINCFG9_FNCSEL9_SCANOUT5        = 15,    /*!< SCANOUT5 : Internal function (SCAN)                                       */
50873 } GPIO_PINCFG9_FNCSEL9_Enum;
50874 
50875 /* =======================================================  PINCFG10  ======================================================== */
50876 /* ============================================  GPIO PINCFG10 NCEPOL10 [22..22]  ============================================ */
50877 typedef enum {                                  /*!< GPIO_PINCFG10_NCEPOL10                                                    */
50878   GPIO_PINCFG10_NCEPOL10_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
50879   GPIO_PINCFG10_NCEPOL10_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
50880 } GPIO_PINCFG10_NCEPOL10_Enum;
50881 
50882 /* ============================================  GPIO PINCFG10 NCESRC10 [16..21]  ============================================ */
50883 typedef enum {                                  /*!< GPIO_PINCFG10_NCESRC10                                                    */
50884   GPIO_PINCFG10_NCESRC10_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50885   GPIO_PINCFG10_NCESRC10_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50886   GPIO_PINCFG10_NCESRC10_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50887   GPIO_PINCFG10_NCESRC10_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50888   GPIO_PINCFG10_NCESRC10_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50889   GPIO_PINCFG10_NCESRC10_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50890   GPIO_PINCFG10_NCESRC10_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50891   GPIO_PINCFG10_NCESRC10_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50892   GPIO_PINCFG10_NCESRC10_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50893   GPIO_PINCFG10_NCESRC10_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50894   GPIO_PINCFG10_NCESRC10_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50895   GPIO_PINCFG10_NCESRC10_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50896   GPIO_PINCFG10_NCESRC10_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50897   GPIO_PINCFG10_NCESRC10_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50898   GPIO_PINCFG10_NCESRC10_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50899   GPIO_PINCFG10_NCESRC10_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50900   GPIO_PINCFG10_NCESRC10_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50901   GPIO_PINCFG10_NCESRC10_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50902   GPIO_PINCFG10_NCESRC10_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50903   GPIO_PINCFG10_NCESRC10_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50904   GPIO_PINCFG10_NCESRC10_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50905   GPIO_PINCFG10_NCESRC10_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50906   GPIO_PINCFG10_NCESRC10_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50907   GPIO_PINCFG10_NCESRC10_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50908   GPIO_PINCFG10_NCESRC10_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50909   GPIO_PINCFG10_NCESRC10_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50910   GPIO_PINCFG10_NCESRC10_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50911   GPIO_PINCFG10_NCESRC10_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50912   GPIO_PINCFG10_NCESRC10_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50913   GPIO_PINCFG10_NCESRC10_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50914   GPIO_PINCFG10_NCESRC10_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50915   GPIO_PINCFG10_NCESRC10_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50916   GPIO_PINCFG10_NCESRC10_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50917   GPIO_PINCFG10_NCESRC10_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50918   GPIO_PINCFG10_NCESRC10_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50919   GPIO_PINCFG10_NCESRC10_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50920   GPIO_PINCFG10_NCESRC10_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50921   GPIO_PINCFG10_NCESRC10_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50922   GPIO_PINCFG10_NCESRC10_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50923   GPIO_PINCFG10_NCESRC10_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50924   GPIO_PINCFG10_NCESRC10_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50925   GPIO_PINCFG10_NCESRC10_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50926   GPIO_PINCFG10_NCESRC10_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
50927 } GPIO_PINCFG10_NCESRC10_Enum;
50928 
50929 /* ===========================================  GPIO PINCFG10 PULLCFG10 [13..15]  ============================================ */
50930 typedef enum {                                  /*!< GPIO_PINCFG10_PULLCFG10                                                   */
50931   GPIO_PINCFG10_PULLCFG10_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50932   GPIO_PINCFG10_PULLCFG10_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50933   GPIO_PINCFG10_PULLCFG10_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50934   GPIO_PINCFG10_PULLCFG10_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50935   GPIO_PINCFG10_PULLCFG10_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
50936   GPIO_PINCFG10_PULLCFG10_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
50937   GPIO_PINCFG10_PULLCFG10_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
50938   GPIO_PINCFG10_PULLCFG10_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
50939 } GPIO_PINCFG10_PULLCFG10_Enum;
50940 
50941 /* ==============================================  GPIO PINCFG10 DS10 [10..11]  ============================================== */
50942 typedef enum {                                  /*!< GPIO_PINCFG10_DS10                                                        */
50943   GPIO_PINCFG10_DS10_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50944   GPIO_PINCFG10_DS10_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50945   GPIO_PINCFG10_DS10_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
50946   GPIO_PINCFG10_DS10_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
50947 } GPIO_PINCFG10_DS10_Enum;
50948 
50949 /* =============================================  GPIO PINCFG10 OUTCFG10 [8..9]  ============================================= */
50950 typedef enum {                                  /*!< GPIO_PINCFG10_OUTCFG10                                                    */
50951   GPIO_PINCFG10_OUTCFG10_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
50952   GPIO_PINCFG10_OUTCFG10_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50953                                                      and 1 values on pin.                                                      */
50954   GPIO_PINCFG10_OUTCFG10_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50955                                                      low, tristate otherwise.                                                  */
50956   GPIO_PINCFG10_OUTCFG10_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50957                                                      drive 0, 1 of HiZ on pin.                                                 */
50958 } GPIO_PINCFG10_OUTCFG10_Enum;
50959 
50960 /* =============================================  GPIO PINCFG10 IRPTEN10 [6..7]  ============================================= */
50961 typedef enum {                                  /*!< GPIO_PINCFG10_IRPTEN10                                                    */
50962   GPIO_PINCFG10_IRPTEN10_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50963   GPIO_PINCFG10_IRPTEN10_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50964                                                      on this GPIO                                                              */
50965   GPIO_PINCFG10_IRPTEN10_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50966                                                      on this GPIO                                                              */
50967   GPIO_PINCFG10_IRPTEN10_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50968                                                      GPIO                                                                      */
50969 } GPIO_PINCFG10_IRPTEN10_Enum;
50970 
50971 /* =============================================  GPIO PINCFG10 FNCSEL10 [0..3]  ============================================= */
50972 typedef enum {                                  /*!< GPIO_PINCFG10_FNCSEL10                                                    */
50973   GPIO_PINCFG10_FNCSEL10_CMPIN0        = 0,     /*!< CMPIN0 : Voltage comparator input 0                                       */
50974   GPIO_PINCFG10_FNCSEL10_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
50975   GPIO_PINCFG10_FNCSEL10_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
50976   GPIO_PINCFG10_FNCSEL10_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
50977   GPIO_PINCFG10_FNCSEL10_M1MISO        = 4,     /*!< M1MISO : Serial SPI MASTER MISO input (IOM 1)                             */
50978   GPIO_PINCFG10_FNCSEL10_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
50979   GPIO_PINCFG10_FNCSEL10_CT10          = 6,     /*!< CT10 : Timer/Counter input or output; Selection of direction
50980                                                      is done via CTIMER register settings.                                     */
50981   GPIO_PINCFG10_FNCSEL10_NCE10         = 7,     /*!< NCE10 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50982                                                      CE_POLARITY field                                                         */
50983   GPIO_PINCFG10_FNCSEL10_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
50984   GPIO_PINCFG10_FNCSEL10_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
50985   GPIO_PINCFG10_FNCSEL10_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
50986   GPIO_PINCFG10_FNCSEL10_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
50987   GPIO_PINCFG10_FNCSEL10_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50988   GPIO_PINCFG10_FNCSEL10_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50989   GPIO_PINCFG10_FNCSEL10_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50990   GPIO_PINCFG10_FNCSEL10_OPCG_LOAD     = 15,    /*!< OPCG_LOAD : Internal function (SCAN)                                      */
50991 } GPIO_PINCFG10_FNCSEL10_Enum;
50992 
50993 /* =======================================================  PINCFG11  ======================================================== */
50994 /* ============================================  GPIO PINCFG11 NCEPOL11 [22..22]  ============================================ */
50995 typedef enum {                                  /*!< GPIO_PINCFG11_NCEPOL11                                                    */
50996   GPIO_PINCFG11_NCEPOL11_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
50997   GPIO_PINCFG11_NCEPOL11_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
50998 } GPIO_PINCFG11_NCEPOL11_Enum;
50999 
51000 /* ============================================  GPIO PINCFG11 NCESRC11 [16..21]  ============================================ */
51001 typedef enum {                                  /*!< GPIO_PINCFG11_NCESRC11                                                    */
51002   GPIO_PINCFG11_NCESRC11_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51003   GPIO_PINCFG11_NCESRC11_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51004   GPIO_PINCFG11_NCESRC11_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51005   GPIO_PINCFG11_NCESRC11_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51006   GPIO_PINCFG11_NCESRC11_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51007   GPIO_PINCFG11_NCESRC11_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51008   GPIO_PINCFG11_NCESRC11_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51009   GPIO_PINCFG11_NCESRC11_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51010   GPIO_PINCFG11_NCESRC11_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51011   GPIO_PINCFG11_NCESRC11_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51012   GPIO_PINCFG11_NCESRC11_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51013   GPIO_PINCFG11_NCESRC11_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51014   GPIO_PINCFG11_NCESRC11_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51015   GPIO_PINCFG11_NCESRC11_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51016   GPIO_PINCFG11_NCESRC11_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51017   GPIO_PINCFG11_NCESRC11_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51018   GPIO_PINCFG11_NCESRC11_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51019   GPIO_PINCFG11_NCESRC11_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51020   GPIO_PINCFG11_NCESRC11_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51021   GPIO_PINCFG11_NCESRC11_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51022   GPIO_PINCFG11_NCESRC11_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51023   GPIO_PINCFG11_NCESRC11_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51024   GPIO_PINCFG11_NCESRC11_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51025   GPIO_PINCFG11_NCESRC11_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51026   GPIO_PINCFG11_NCESRC11_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51027   GPIO_PINCFG11_NCESRC11_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51028   GPIO_PINCFG11_NCESRC11_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51029   GPIO_PINCFG11_NCESRC11_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51030   GPIO_PINCFG11_NCESRC11_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51031   GPIO_PINCFG11_NCESRC11_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51032   GPIO_PINCFG11_NCESRC11_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51033   GPIO_PINCFG11_NCESRC11_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51034   GPIO_PINCFG11_NCESRC11_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51035   GPIO_PINCFG11_NCESRC11_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51036   GPIO_PINCFG11_NCESRC11_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51037   GPIO_PINCFG11_NCESRC11_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51038   GPIO_PINCFG11_NCESRC11_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51039   GPIO_PINCFG11_NCESRC11_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51040   GPIO_PINCFG11_NCESRC11_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51041   GPIO_PINCFG11_NCESRC11_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51042   GPIO_PINCFG11_NCESRC11_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51043   GPIO_PINCFG11_NCESRC11_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51044   GPIO_PINCFG11_NCESRC11_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51045 } GPIO_PINCFG11_NCESRC11_Enum;
51046 
51047 /* ===========================================  GPIO PINCFG11 PULLCFG11 [13..15]  ============================================ */
51048 typedef enum {                                  /*!< GPIO_PINCFG11_PULLCFG11                                                   */
51049   GPIO_PINCFG11_PULLCFG11_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51050   GPIO_PINCFG11_PULLCFG11_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51051   GPIO_PINCFG11_PULLCFG11_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51052   GPIO_PINCFG11_PULLCFG11_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51053   GPIO_PINCFG11_PULLCFG11_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51054   GPIO_PINCFG11_PULLCFG11_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51055   GPIO_PINCFG11_PULLCFG11_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51056   GPIO_PINCFG11_PULLCFG11_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51057 } GPIO_PINCFG11_PULLCFG11_Enum;
51058 
51059 /* ==============================================  GPIO PINCFG11 DS11 [10..11]  ============================================== */
51060 typedef enum {                                  /*!< GPIO_PINCFG11_DS11                                                        */
51061   GPIO_PINCFG11_DS11_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51062   GPIO_PINCFG11_DS11_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51063 } GPIO_PINCFG11_DS11_Enum;
51064 
51065 /* =============================================  GPIO PINCFG11 OUTCFG11 [8..9]  ============================================= */
51066 typedef enum {                                  /*!< GPIO_PINCFG11_OUTCFG11                                                    */
51067   GPIO_PINCFG11_OUTCFG11_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51068   GPIO_PINCFG11_OUTCFG11_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51069                                                      and 1 values on pin.                                                      */
51070   GPIO_PINCFG11_OUTCFG11_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51071                                                      low, tristate otherwise.                                                  */
51072   GPIO_PINCFG11_OUTCFG11_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51073                                                      drive 0, 1 of HiZ on pin.                                                 */
51074 } GPIO_PINCFG11_OUTCFG11_Enum;
51075 
51076 /* =============================================  GPIO PINCFG11 IRPTEN11 [6..7]  ============================================= */
51077 typedef enum {                                  /*!< GPIO_PINCFG11_IRPTEN11                                                    */
51078   GPIO_PINCFG11_IRPTEN11_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51079   GPIO_PINCFG11_IRPTEN11_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51080                                                      on this GPIO                                                              */
51081   GPIO_PINCFG11_IRPTEN11_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51082                                                      on this GPIO                                                              */
51083   GPIO_PINCFG11_IRPTEN11_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51084                                                      GPIO                                                                      */
51085 } GPIO_PINCFG11_IRPTEN11_Enum;
51086 
51087 /* =============================================  GPIO PINCFG11 FNCSEL11 [0..3]  ============================================= */
51088 typedef enum {                                  /*!< GPIO_PINCFG11_FNCSEL11                                                    */
51089   GPIO_PINCFG11_FNCSEL11_CMPIN1        = 0,     /*!< CMPIN1 : Voltage comparator input 1                                       */
51090   GPIO_PINCFG11_FNCSEL11_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
51091   GPIO_PINCFG11_FNCSEL11_I2S0_CLK      = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
51092                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51093                                                      2)                                                                        */
51094   GPIO_PINCFG11_FNCSEL11_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51095   GPIO_PINCFG11_FNCSEL11_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
51096   GPIO_PINCFG11_FNCSEL11_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
51097   GPIO_PINCFG11_FNCSEL11_CT11          = 6,     /*!< CT11 : Timer/Counter input or output; Selection of direction
51098                                                      is done via CTIMER register settings.                                     */
51099   GPIO_PINCFG11_FNCSEL11_NCE11         = 7,     /*!< NCE11 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51100                                                      CE_POLARITY field                                                         */
51101   GPIO_PINCFG11_FNCSEL11_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
51102   GPIO_PINCFG11_FNCSEL11_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51103   GPIO_PINCFG11_FNCSEL11_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51104   GPIO_PINCFG11_FNCSEL11_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51105   GPIO_PINCFG11_FNCSEL11_FLB_TCLK      = 12,    /*!< FLB_TCLK : Internal function (Flash Bist)                                 */
51106   GPIO_PINCFG11_FNCSEL11_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
51107   GPIO_PINCFG11_FNCSEL11_MDA_TCK       = 14,    /*!< MDA_TCK : Internal function (MBIST)                                       */
51108   GPIO_PINCFG11_FNCSEL11_SCANIN0       = 15,    /*!< SCANIN0 : Internal function (SCAN)                                        */
51109 } GPIO_PINCFG11_FNCSEL11_Enum;
51110 
51111 /* =======================================================  PINCFG12  ======================================================== */
51112 /* ============================================  GPIO PINCFG12 NCEPOL12 [22..22]  ============================================ */
51113 typedef enum {                                  /*!< GPIO_PINCFG12_NCEPOL12                                                    */
51114   GPIO_PINCFG12_NCEPOL12_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51115   GPIO_PINCFG12_NCEPOL12_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51116 } GPIO_PINCFG12_NCEPOL12_Enum;
51117 
51118 /* ============================================  GPIO PINCFG12 NCESRC12 [16..21]  ============================================ */
51119 typedef enum {                                  /*!< GPIO_PINCFG12_NCESRC12                                                    */
51120   GPIO_PINCFG12_NCESRC12_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51121   GPIO_PINCFG12_NCESRC12_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51122   GPIO_PINCFG12_NCESRC12_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51123   GPIO_PINCFG12_NCESRC12_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51124   GPIO_PINCFG12_NCESRC12_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51125   GPIO_PINCFG12_NCESRC12_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51126   GPIO_PINCFG12_NCESRC12_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51127   GPIO_PINCFG12_NCESRC12_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51128   GPIO_PINCFG12_NCESRC12_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51129   GPIO_PINCFG12_NCESRC12_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51130   GPIO_PINCFG12_NCESRC12_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51131   GPIO_PINCFG12_NCESRC12_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51132   GPIO_PINCFG12_NCESRC12_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51133   GPIO_PINCFG12_NCESRC12_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51134   GPIO_PINCFG12_NCESRC12_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51135   GPIO_PINCFG12_NCESRC12_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51136   GPIO_PINCFG12_NCESRC12_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51137   GPIO_PINCFG12_NCESRC12_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51138   GPIO_PINCFG12_NCESRC12_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51139   GPIO_PINCFG12_NCESRC12_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51140   GPIO_PINCFG12_NCESRC12_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51141   GPIO_PINCFG12_NCESRC12_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51142   GPIO_PINCFG12_NCESRC12_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51143   GPIO_PINCFG12_NCESRC12_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51144   GPIO_PINCFG12_NCESRC12_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51145   GPIO_PINCFG12_NCESRC12_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51146   GPIO_PINCFG12_NCESRC12_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51147   GPIO_PINCFG12_NCESRC12_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51148   GPIO_PINCFG12_NCESRC12_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51149   GPIO_PINCFG12_NCESRC12_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51150   GPIO_PINCFG12_NCESRC12_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51151   GPIO_PINCFG12_NCESRC12_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51152   GPIO_PINCFG12_NCESRC12_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51153   GPIO_PINCFG12_NCESRC12_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51154   GPIO_PINCFG12_NCESRC12_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51155   GPIO_PINCFG12_NCESRC12_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51156   GPIO_PINCFG12_NCESRC12_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51157   GPIO_PINCFG12_NCESRC12_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51158   GPIO_PINCFG12_NCESRC12_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51159   GPIO_PINCFG12_NCESRC12_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51160   GPIO_PINCFG12_NCESRC12_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51161   GPIO_PINCFG12_NCESRC12_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51162   GPIO_PINCFG12_NCESRC12_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51163 } GPIO_PINCFG12_NCESRC12_Enum;
51164 
51165 /* ===========================================  GPIO PINCFG12 PULLCFG12 [13..15]  ============================================ */
51166 typedef enum {                                  /*!< GPIO_PINCFG12_PULLCFG12                                                   */
51167   GPIO_PINCFG12_PULLCFG12_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51168   GPIO_PINCFG12_PULLCFG12_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51169   GPIO_PINCFG12_PULLCFG12_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51170   GPIO_PINCFG12_PULLCFG12_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51171   GPIO_PINCFG12_PULLCFG12_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51172   GPIO_PINCFG12_PULLCFG12_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51173   GPIO_PINCFG12_PULLCFG12_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51174   GPIO_PINCFG12_PULLCFG12_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51175 } GPIO_PINCFG12_PULLCFG12_Enum;
51176 
51177 /* ==============================================  GPIO PINCFG12 DS12 [10..11]  ============================================== */
51178 typedef enum {                                  /*!< GPIO_PINCFG12_DS12                                                        */
51179   GPIO_PINCFG12_DS12_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51180   GPIO_PINCFG12_DS12_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51181 } GPIO_PINCFG12_DS12_Enum;
51182 
51183 /* =============================================  GPIO PINCFG12 OUTCFG12 [8..9]  ============================================= */
51184 typedef enum {                                  /*!< GPIO_PINCFG12_OUTCFG12                                                    */
51185   GPIO_PINCFG12_OUTCFG12_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51186   GPIO_PINCFG12_OUTCFG12_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51187                                                      and 1 values on pin.                                                      */
51188   GPIO_PINCFG12_OUTCFG12_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51189                                                      low, tristate otherwise.                                                  */
51190   GPIO_PINCFG12_OUTCFG12_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51191                                                      drive 0, 1 of HiZ on pin.                                                 */
51192 } GPIO_PINCFG12_OUTCFG12_Enum;
51193 
51194 /* =============================================  GPIO PINCFG12 IRPTEN12 [6..7]  ============================================= */
51195 typedef enum {                                  /*!< GPIO_PINCFG12_IRPTEN12                                                    */
51196   GPIO_PINCFG12_IRPTEN12_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51197   GPIO_PINCFG12_IRPTEN12_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51198                                                      on this GPIO                                                              */
51199   GPIO_PINCFG12_IRPTEN12_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51200                                                      on this GPIO                                                              */
51201   GPIO_PINCFG12_IRPTEN12_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51202                                                      GPIO                                                                      */
51203 } GPIO_PINCFG12_IRPTEN12_Enum;
51204 
51205 /* =============================================  GPIO PINCFG12 FNCSEL12 [0..3]  ============================================= */
51206 typedef enum {                                  /*!< GPIO_PINCFG12_FNCSEL12                                                    */
51207   GPIO_PINCFG12_FNCSEL12_ADCSE7        = 0,     /*!< ADCSE7 : Analog to Digital Converter SE IN7                               */
51208   GPIO_PINCFG12_FNCSEL12_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
51209   GPIO_PINCFG12_FNCSEL12_I2S0_DATA     = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
51210                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51211                                                      2)                                                                        */
51212   GPIO_PINCFG12_FNCSEL12_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51213   GPIO_PINCFG12_FNCSEL12_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
51214   GPIO_PINCFG12_FNCSEL12_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
51215   GPIO_PINCFG12_FNCSEL12_CT12          = 6,     /*!< CT12 : Timer/Counter input or output; Selection of direction
51216                                                      is done via CTIMER register settings.                                     */
51217   GPIO_PINCFG12_FNCSEL12_NCE12         = 7,     /*!< NCE12 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51218                                                      CE_POLARITY field                                                         */
51219   GPIO_PINCFG12_FNCSEL12_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
51220   GPIO_PINCFG12_FNCSEL12_CMPRF2        = 9,     /*!< CMPRF2 : Comparator reference 2                                           */
51221   GPIO_PINCFG12_FNCSEL12_I2S0_SDOUT    = 10,    /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
51222   GPIO_PINCFG12_FNCSEL12_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51223   GPIO_PINCFG12_FNCSEL12_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51224   GPIO_PINCFG12_FNCSEL12_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51225   GPIO_PINCFG12_FNCSEL12_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51226   GPIO_PINCFG12_FNCSEL12_SCANOUT3      = 15,    /*!< SCANOUT3 : Internal function (SCAN)                                       */
51227 } GPIO_PINCFG12_FNCSEL12_Enum;
51228 
51229 /* =======================================================  PINCFG13  ======================================================== */
51230 /* ============================================  GPIO PINCFG13 NCEPOL13 [22..22]  ============================================ */
51231 typedef enum {                                  /*!< GPIO_PINCFG13_NCEPOL13                                                    */
51232   GPIO_PINCFG13_NCEPOL13_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51233   GPIO_PINCFG13_NCEPOL13_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51234 } GPIO_PINCFG13_NCEPOL13_Enum;
51235 
51236 /* ============================================  GPIO PINCFG13 NCESRC13 [16..21]  ============================================ */
51237 typedef enum {                                  /*!< GPIO_PINCFG13_NCESRC13                                                    */
51238   GPIO_PINCFG13_NCESRC13_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51239   GPIO_PINCFG13_NCESRC13_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51240   GPIO_PINCFG13_NCESRC13_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51241   GPIO_PINCFG13_NCESRC13_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51242   GPIO_PINCFG13_NCESRC13_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51243   GPIO_PINCFG13_NCESRC13_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51244   GPIO_PINCFG13_NCESRC13_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51245   GPIO_PINCFG13_NCESRC13_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51246   GPIO_PINCFG13_NCESRC13_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51247   GPIO_PINCFG13_NCESRC13_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51248   GPIO_PINCFG13_NCESRC13_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51249   GPIO_PINCFG13_NCESRC13_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51250   GPIO_PINCFG13_NCESRC13_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51251   GPIO_PINCFG13_NCESRC13_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51252   GPIO_PINCFG13_NCESRC13_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51253   GPIO_PINCFG13_NCESRC13_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51254   GPIO_PINCFG13_NCESRC13_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51255   GPIO_PINCFG13_NCESRC13_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51256   GPIO_PINCFG13_NCESRC13_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51257   GPIO_PINCFG13_NCESRC13_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51258   GPIO_PINCFG13_NCESRC13_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51259   GPIO_PINCFG13_NCESRC13_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51260   GPIO_PINCFG13_NCESRC13_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51261   GPIO_PINCFG13_NCESRC13_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51262   GPIO_PINCFG13_NCESRC13_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51263   GPIO_PINCFG13_NCESRC13_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51264   GPIO_PINCFG13_NCESRC13_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51265   GPIO_PINCFG13_NCESRC13_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51266   GPIO_PINCFG13_NCESRC13_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51267   GPIO_PINCFG13_NCESRC13_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51268   GPIO_PINCFG13_NCESRC13_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51269   GPIO_PINCFG13_NCESRC13_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51270   GPIO_PINCFG13_NCESRC13_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51271   GPIO_PINCFG13_NCESRC13_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51272   GPIO_PINCFG13_NCESRC13_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51273   GPIO_PINCFG13_NCESRC13_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51274   GPIO_PINCFG13_NCESRC13_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51275   GPIO_PINCFG13_NCESRC13_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51276   GPIO_PINCFG13_NCESRC13_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51277   GPIO_PINCFG13_NCESRC13_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51278   GPIO_PINCFG13_NCESRC13_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51279   GPIO_PINCFG13_NCESRC13_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51280   GPIO_PINCFG13_NCESRC13_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51281 } GPIO_PINCFG13_NCESRC13_Enum;
51282 
51283 /* ===========================================  GPIO PINCFG13 PULLCFG13 [13..15]  ============================================ */
51284 typedef enum {                                  /*!< GPIO_PINCFG13_PULLCFG13                                                   */
51285   GPIO_PINCFG13_PULLCFG13_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51286   GPIO_PINCFG13_PULLCFG13_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51287   GPIO_PINCFG13_PULLCFG13_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51288   GPIO_PINCFG13_PULLCFG13_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51289   GPIO_PINCFG13_PULLCFG13_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51290   GPIO_PINCFG13_PULLCFG13_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51291   GPIO_PINCFG13_PULLCFG13_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51292   GPIO_PINCFG13_PULLCFG13_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51293 } GPIO_PINCFG13_PULLCFG13_Enum;
51294 
51295 /* ==============================================  GPIO PINCFG13 DS13 [10..11]  ============================================== */
51296 typedef enum {                                  /*!< GPIO_PINCFG13_DS13                                                        */
51297   GPIO_PINCFG13_DS13_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51298   GPIO_PINCFG13_DS13_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51299 } GPIO_PINCFG13_DS13_Enum;
51300 
51301 /* =============================================  GPIO PINCFG13 OUTCFG13 [8..9]  ============================================= */
51302 typedef enum {                                  /*!< GPIO_PINCFG13_OUTCFG13                                                    */
51303   GPIO_PINCFG13_OUTCFG13_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51304   GPIO_PINCFG13_OUTCFG13_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51305                                                      and 1 values on pin.                                                      */
51306   GPIO_PINCFG13_OUTCFG13_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51307                                                      low, tristate otherwise.                                                  */
51308   GPIO_PINCFG13_OUTCFG13_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51309                                                      drive 0, 1 of HiZ on pin.                                                 */
51310 } GPIO_PINCFG13_OUTCFG13_Enum;
51311 
51312 /* =============================================  GPIO PINCFG13 IRPTEN13 [6..7]  ============================================= */
51313 typedef enum {                                  /*!< GPIO_PINCFG13_IRPTEN13                                                    */
51314   GPIO_PINCFG13_IRPTEN13_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51315   GPIO_PINCFG13_IRPTEN13_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51316                                                      on this GPIO                                                              */
51317   GPIO_PINCFG13_IRPTEN13_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51318                                                      on this GPIO                                                              */
51319   GPIO_PINCFG13_IRPTEN13_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51320                                                      GPIO                                                                      */
51321 } GPIO_PINCFG13_IRPTEN13_Enum;
51322 
51323 /* =============================================  GPIO PINCFG13 FNCSEL13 [0..3]  ============================================= */
51324 typedef enum {                                  /*!< GPIO_PINCFG13_FNCSEL13                                                    */
51325   GPIO_PINCFG13_FNCSEL13_ADCSE6        = 0,     /*!< ADCSE6 : Analog to Digital Converter SE IN6                               */
51326   GPIO_PINCFG13_FNCSEL13_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
51327   GPIO_PINCFG13_FNCSEL13_I2S0_WS       = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
51328                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51329                                                      2)                                                                        */
51330   GPIO_PINCFG13_FNCSEL13_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51331   GPIO_PINCFG13_FNCSEL13_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
51332   GPIO_PINCFG13_FNCSEL13_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
51333   GPIO_PINCFG13_FNCSEL13_CT13          = 6,     /*!< CT13 : Timer/Counter input or output; Selection of direction
51334                                                      is done via CTIMER register settings.                                     */
51335   GPIO_PINCFG13_FNCSEL13_NCE13         = 7,     /*!< NCE13 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51336                                                      CE_POLARITY field                                                         */
51337   GPIO_PINCFG13_FNCSEL13_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
51338   GPIO_PINCFG13_FNCSEL13_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51339   GPIO_PINCFG13_FNCSEL13_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51340   GPIO_PINCFG13_FNCSEL13_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51341   GPIO_PINCFG13_FNCSEL13_FLB_FCLK      = 12,    /*!< FLB_FCLK : Internal function (Flash Bist)                                 */
51342   GPIO_PINCFG13_FNCSEL13_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
51343   GPIO_PINCFG13_FNCSEL13_MDA_TDI       = 14,    /*!< MDA_TDI : Internal function (MBIST)                                       */
51344   GPIO_PINCFG13_FNCSEL13_SCANOUT0      = 15,    /*!< SCANOUT0 : Internal function (SCAN)                                       */
51345 } GPIO_PINCFG13_FNCSEL13_Enum;
51346 
51347 /* =======================================================  PINCFG14  ======================================================== */
51348 /* ============================================  GPIO PINCFG14 NCEPOL14 [22..22]  ============================================ */
51349 typedef enum {                                  /*!< GPIO_PINCFG14_NCEPOL14                                                    */
51350   GPIO_PINCFG14_NCEPOL14_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51351   GPIO_PINCFG14_NCEPOL14_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51352 } GPIO_PINCFG14_NCEPOL14_Enum;
51353 
51354 /* ============================================  GPIO PINCFG14 NCESRC14 [16..21]  ============================================ */
51355 typedef enum {                                  /*!< GPIO_PINCFG14_NCESRC14                                                    */
51356   GPIO_PINCFG14_NCESRC14_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51357   GPIO_PINCFG14_NCESRC14_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51358   GPIO_PINCFG14_NCESRC14_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51359   GPIO_PINCFG14_NCESRC14_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51360   GPIO_PINCFG14_NCESRC14_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51361   GPIO_PINCFG14_NCESRC14_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51362   GPIO_PINCFG14_NCESRC14_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51363   GPIO_PINCFG14_NCESRC14_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51364   GPIO_PINCFG14_NCESRC14_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51365   GPIO_PINCFG14_NCESRC14_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51366   GPIO_PINCFG14_NCESRC14_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51367   GPIO_PINCFG14_NCESRC14_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51368   GPIO_PINCFG14_NCESRC14_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51369   GPIO_PINCFG14_NCESRC14_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51370   GPIO_PINCFG14_NCESRC14_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51371   GPIO_PINCFG14_NCESRC14_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51372   GPIO_PINCFG14_NCESRC14_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51373   GPIO_PINCFG14_NCESRC14_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51374   GPIO_PINCFG14_NCESRC14_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51375   GPIO_PINCFG14_NCESRC14_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51376   GPIO_PINCFG14_NCESRC14_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51377   GPIO_PINCFG14_NCESRC14_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51378   GPIO_PINCFG14_NCESRC14_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51379   GPIO_PINCFG14_NCESRC14_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51380   GPIO_PINCFG14_NCESRC14_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51381   GPIO_PINCFG14_NCESRC14_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51382   GPIO_PINCFG14_NCESRC14_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51383   GPIO_PINCFG14_NCESRC14_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51384   GPIO_PINCFG14_NCESRC14_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51385   GPIO_PINCFG14_NCESRC14_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51386   GPIO_PINCFG14_NCESRC14_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51387   GPIO_PINCFG14_NCESRC14_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51388   GPIO_PINCFG14_NCESRC14_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51389   GPIO_PINCFG14_NCESRC14_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51390   GPIO_PINCFG14_NCESRC14_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51391   GPIO_PINCFG14_NCESRC14_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51392   GPIO_PINCFG14_NCESRC14_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51393   GPIO_PINCFG14_NCESRC14_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51394   GPIO_PINCFG14_NCESRC14_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51395   GPIO_PINCFG14_NCESRC14_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51396   GPIO_PINCFG14_NCESRC14_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51397   GPIO_PINCFG14_NCESRC14_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51398   GPIO_PINCFG14_NCESRC14_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51399 } GPIO_PINCFG14_NCESRC14_Enum;
51400 
51401 /* ===========================================  GPIO PINCFG14 PULLCFG14 [13..15]  ============================================ */
51402 typedef enum {                                  /*!< GPIO_PINCFG14_PULLCFG14                                                   */
51403   GPIO_PINCFG14_PULLCFG14_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51404   GPIO_PINCFG14_PULLCFG14_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51405   GPIO_PINCFG14_PULLCFG14_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51406   GPIO_PINCFG14_PULLCFG14_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51407   GPIO_PINCFG14_PULLCFG14_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51408   GPIO_PINCFG14_PULLCFG14_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51409   GPIO_PINCFG14_PULLCFG14_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51410   GPIO_PINCFG14_PULLCFG14_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51411 } GPIO_PINCFG14_PULLCFG14_Enum;
51412 
51413 /* ==============================================  GPIO PINCFG14 DS14 [10..11]  ============================================== */
51414 typedef enum {                                  /*!< GPIO_PINCFG14_DS14                                                        */
51415   GPIO_PINCFG14_DS14_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51416   GPIO_PINCFG14_DS14_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51417 } GPIO_PINCFG14_DS14_Enum;
51418 
51419 /* =============================================  GPIO PINCFG14 OUTCFG14 [8..9]  ============================================= */
51420 typedef enum {                                  /*!< GPIO_PINCFG14_OUTCFG14                                                    */
51421   GPIO_PINCFG14_OUTCFG14_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51422   GPIO_PINCFG14_OUTCFG14_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51423                                                      and 1 values on pin.                                                      */
51424   GPIO_PINCFG14_OUTCFG14_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51425                                                      low, tristate otherwise.                                                  */
51426   GPIO_PINCFG14_OUTCFG14_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51427                                                      drive 0, 1 of HiZ on pin.                                                 */
51428 } GPIO_PINCFG14_OUTCFG14_Enum;
51429 
51430 /* =============================================  GPIO PINCFG14 IRPTEN14 [6..7]  ============================================= */
51431 typedef enum {                                  /*!< GPIO_PINCFG14_IRPTEN14                                                    */
51432   GPIO_PINCFG14_IRPTEN14_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51433   GPIO_PINCFG14_IRPTEN14_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51434                                                      on this GPIO                                                              */
51435   GPIO_PINCFG14_IRPTEN14_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51436                                                      on this GPIO                                                              */
51437   GPIO_PINCFG14_IRPTEN14_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51438                                                      GPIO                                                                      */
51439 } GPIO_PINCFG14_IRPTEN14_Enum;
51440 
51441 /* =============================================  GPIO PINCFG14 FNCSEL14 [0..3]  ============================================= */
51442 typedef enum {                                  /*!< GPIO_PINCFG14_FNCSEL14                                                    */
51443   GPIO_PINCFG14_FNCSEL14_ADCSE5        = 0,     /*!< ADCSE5 : Analog to Digital Converter SE IN5                               */
51444   GPIO_PINCFG14_FNCSEL14_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
51445   GPIO_PINCFG14_FNCSEL14_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
51446   GPIO_PINCFG14_FNCSEL14_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51447   GPIO_PINCFG14_FNCSEL14_MILLI_CLK     = 4,     /*!< MILLI_CLK : MILLI Clock                                                   */
51448   GPIO_PINCFG14_FNCSEL14_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
51449   GPIO_PINCFG14_FNCSEL14_CT14          = 6,     /*!< CT14 : Timer/Counter input or output; Selection of direction
51450                                                      is done via CTIMER register settings.                                     */
51451   GPIO_PINCFG14_FNCSEL14_NCE14         = 7,     /*!< NCE14 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51452                                                      CE_POLARITY field                                                         */
51453   GPIO_PINCFG14_FNCSEL14_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
51454   GPIO_PINCFG14_FNCSEL14_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51455   GPIO_PINCFG14_FNCSEL14_I2S0_SDIN     = 10,    /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
51456   GPIO_PINCFG14_FNCSEL14_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51457   GPIO_PINCFG14_FNCSEL14_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51458   GPIO_PINCFG14_FNCSEL14_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
51459   GPIO_PINCFG14_FNCSEL14_MDA_TRSTN     = 14,    /*!< MDA_TRSTN : Internal function (MBIST)                                     */
51460   GPIO_PINCFG14_FNCSEL14_SCANOUT2      = 15,    /*!< SCANOUT2 : Internal function (SCAN)                                       */
51461 } GPIO_PINCFG14_FNCSEL14_Enum;
51462 
51463 /* =======================================================  PINCFG15  ======================================================== */
51464 /* ============================================  GPIO PINCFG15 NCEPOL15 [22..22]  ============================================ */
51465 typedef enum {                                  /*!< GPIO_PINCFG15_NCEPOL15                                                    */
51466   GPIO_PINCFG15_NCEPOL15_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51467   GPIO_PINCFG15_NCEPOL15_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51468 } GPIO_PINCFG15_NCEPOL15_Enum;
51469 
51470 /* ============================================  GPIO PINCFG15 NCESRC15 [16..21]  ============================================ */
51471 typedef enum {                                  /*!< GPIO_PINCFG15_NCESRC15                                                    */
51472   GPIO_PINCFG15_NCESRC15_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51473   GPIO_PINCFG15_NCESRC15_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51474   GPIO_PINCFG15_NCESRC15_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51475   GPIO_PINCFG15_NCESRC15_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51476   GPIO_PINCFG15_NCESRC15_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51477   GPIO_PINCFG15_NCESRC15_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51478   GPIO_PINCFG15_NCESRC15_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51479   GPIO_PINCFG15_NCESRC15_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51480   GPIO_PINCFG15_NCESRC15_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51481   GPIO_PINCFG15_NCESRC15_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51482   GPIO_PINCFG15_NCESRC15_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51483   GPIO_PINCFG15_NCESRC15_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51484   GPIO_PINCFG15_NCESRC15_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51485   GPIO_PINCFG15_NCESRC15_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51486   GPIO_PINCFG15_NCESRC15_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51487   GPIO_PINCFG15_NCESRC15_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51488   GPIO_PINCFG15_NCESRC15_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51489   GPIO_PINCFG15_NCESRC15_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51490   GPIO_PINCFG15_NCESRC15_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51491   GPIO_PINCFG15_NCESRC15_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51492   GPIO_PINCFG15_NCESRC15_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51493   GPIO_PINCFG15_NCESRC15_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51494   GPIO_PINCFG15_NCESRC15_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51495   GPIO_PINCFG15_NCESRC15_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51496   GPIO_PINCFG15_NCESRC15_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51497   GPIO_PINCFG15_NCESRC15_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51498   GPIO_PINCFG15_NCESRC15_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51499   GPIO_PINCFG15_NCESRC15_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51500   GPIO_PINCFG15_NCESRC15_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51501   GPIO_PINCFG15_NCESRC15_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51502   GPIO_PINCFG15_NCESRC15_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51503   GPIO_PINCFG15_NCESRC15_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51504   GPIO_PINCFG15_NCESRC15_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51505   GPIO_PINCFG15_NCESRC15_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51506   GPIO_PINCFG15_NCESRC15_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51507   GPIO_PINCFG15_NCESRC15_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51508   GPIO_PINCFG15_NCESRC15_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51509   GPIO_PINCFG15_NCESRC15_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51510   GPIO_PINCFG15_NCESRC15_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51511   GPIO_PINCFG15_NCESRC15_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51512   GPIO_PINCFG15_NCESRC15_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51513   GPIO_PINCFG15_NCESRC15_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51514   GPIO_PINCFG15_NCESRC15_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51515 } GPIO_PINCFG15_NCESRC15_Enum;
51516 
51517 /* ===========================================  GPIO PINCFG15 PULLCFG15 [13..15]  ============================================ */
51518 typedef enum {                                  /*!< GPIO_PINCFG15_PULLCFG15                                                   */
51519   GPIO_PINCFG15_PULLCFG15_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51520   GPIO_PINCFG15_PULLCFG15_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51521   GPIO_PINCFG15_PULLCFG15_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51522   GPIO_PINCFG15_PULLCFG15_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51523   GPIO_PINCFG15_PULLCFG15_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51524   GPIO_PINCFG15_PULLCFG15_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51525   GPIO_PINCFG15_PULLCFG15_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51526   GPIO_PINCFG15_PULLCFG15_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51527 } GPIO_PINCFG15_PULLCFG15_Enum;
51528 
51529 /* ==============================================  GPIO PINCFG15 DS15 [10..11]  ============================================== */
51530 typedef enum {                                  /*!< GPIO_PINCFG15_DS15                                                        */
51531   GPIO_PINCFG15_DS15_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51532   GPIO_PINCFG15_DS15_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51533 } GPIO_PINCFG15_DS15_Enum;
51534 
51535 /* =============================================  GPIO PINCFG15 OUTCFG15 [8..9]  ============================================= */
51536 typedef enum {                                  /*!< GPIO_PINCFG15_OUTCFG15                                                    */
51537   GPIO_PINCFG15_OUTCFG15_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51538   GPIO_PINCFG15_OUTCFG15_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51539                                                      and 1 values on pin.                                                      */
51540   GPIO_PINCFG15_OUTCFG15_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51541                                                      low, tristate otherwise.                                                  */
51542   GPIO_PINCFG15_OUTCFG15_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51543                                                      drive 0, 1 of HiZ on pin.                                                 */
51544 } GPIO_PINCFG15_OUTCFG15_Enum;
51545 
51546 /* =============================================  GPIO PINCFG15 IRPTEN15 [6..7]  ============================================= */
51547 typedef enum {                                  /*!< GPIO_PINCFG15_IRPTEN15                                                    */
51548   GPIO_PINCFG15_IRPTEN15_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51549   GPIO_PINCFG15_IRPTEN15_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51550                                                      on this GPIO                                                              */
51551   GPIO_PINCFG15_IRPTEN15_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51552                                                      on this GPIO                                                              */
51553   GPIO_PINCFG15_IRPTEN15_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51554                                                      GPIO                                                                      */
51555 } GPIO_PINCFG15_IRPTEN15_Enum;
51556 
51557 /* =============================================  GPIO PINCFG15 FNCSEL15 [0..3]  ============================================= */
51558 typedef enum {                                  /*!< GPIO_PINCFG15_FNCSEL15                                                    */
51559   GPIO_PINCFG15_FNCSEL15_ADCSE4        = 0,     /*!< ADCSE4 : Analog to Digital Converter SE IN4                               */
51560   GPIO_PINCFG15_FNCSEL15_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
51561   GPIO_PINCFG15_FNCSEL15_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
51562   GPIO_PINCFG15_FNCSEL15_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51563   GPIO_PINCFG15_FNCSEL15_MILLI_REC_DAT = 4,     /*!< MILLI_REC_DAT : MILLI Record Data                                         */
51564   GPIO_PINCFG15_FNCSEL15_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
51565   GPIO_PINCFG15_FNCSEL15_CT15          = 6,     /*!< CT15 : Timer/Counter input or output; Selection of direction
51566                                                      is done via CTIMER register settings.                                     */
51567   GPIO_PINCFG15_FNCSEL15_NCE15         = 7,     /*!< NCE15 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51568                                                      CE_POLARITY field                                                         */
51569   GPIO_PINCFG15_FNCSEL15_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
51570   GPIO_PINCFG15_FNCSEL15_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51571   GPIO_PINCFG15_FNCSEL15_REFCLK_EXT    = 10,    /*!< REFCLK_EXT : External Reference Clock                                     */
51572   GPIO_PINCFG15_FNCSEL15_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51573   GPIO_PINCFG15_FNCSEL15_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51574   GPIO_PINCFG15_FNCSEL15_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
51575   GPIO_PINCFG15_FNCSEL15_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51576   GPIO_PINCFG15_FNCSEL15_SCANOUT1      = 15,    /*!< SCANOUT1 : Internal function (SCAN)                                       */
51577 } GPIO_PINCFG15_FNCSEL15_Enum;
51578 
51579 /* =======================================================  PINCFG16  ======================================================== */
51580 /* ============================================  GPIO PINCFG16 NCEPOL16 [22..22]  ============================================ */
51581 typedef enum {                                  /*!< GPIO_PINCFG16_NCEPOL16                                                    */
51582   GPIO_PINCFG16_NCEPOL16_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51583   GPIO_PINCFG16_NCEPOL16_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51584 } GPIO_PINCFG16_NCEPOL16_Enum;
51585 
51586 /* ============================================  GPIO PINCFG16 NCESRC16 [16..21]  ============================================ */
51587 typedef enum {                                  /*!< GPIO_PINCFG16_NCESRC16                                                    */
51588   GPIO_PINCFG16_NCESRC16_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51589   GPIO_PINCFG16_NCESRC16_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51590   GPIO_PINCFG16_NCESRC16_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51591   GPIO_PINCFG16_NCESRC16_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51592   GPIO_PINCFG16_NCESRC16_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51593   GPIO_PINCFG16_NCESRC16_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51594   GPIO_PINCFG16_NCESRC16_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51595   GPIO_PINCFG16_NCESRC16_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51596   GPIO_PINCFG16_NCESRC16_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51597   GPIO_PINCFG16_NCESRC16_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51598   GPIO_PINCFG16_NCESRC16_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51599   GPIO_PINCFG16_NCESRC16_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51600   GPIO_PINCFG16_NCESRC16_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51601   GPIO_PINCFG16_NCESRC16_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51602   GPIO_PINCFG16_NCESRC16_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51603   GPIO_PINCFG16_NCESRC16_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51604   GPIO_PINCFG16_NCESRC16_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51605   GPIO_PINCFG16_NCESRC16_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51606   GPIO_PINCFG16_NCESRC16_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51607   GPIO_PINCFG16_NCESRC16_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51608   GPIO_PINCFG16_NCESRC16_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51609   GPIO_PINCFG16_NCESRC16_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51610   GPIO_PINCFG16_NCESRC16_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51611   GPIO_PINCFG16_NCESRC16_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51612   GPIO_PINCFG16_NCESRC16_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51613   GPIO_PINCFG16_NCESRC16_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51614   GPIO_PINCFG16_NCESRC16_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51615   GPIO_PINCFG16_NCESRC16_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51616   GPIO_PINCFG16_NCESRC16_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51617   GPIO_PINCFG16_NCESRC16_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51618   GPIO_PINCFG16_NCESRC16_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51619   GPIO_PINCFG16_NCESRC16_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51620   GPIO_PINCFG16_NCESRC16_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51621   GPIO_PINCFG16_NCESRC16_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51622   GPIO_PINCFG16_NCESRC16_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51623   GPIO_PINCFG16_NCESRC16_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51624   GPIO_PINCFG16_NCESRC16_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51625   GPIO_PINCFG16_NCESRC16_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51626   GPIO_PINCFG16_NCESRC16_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51627   GPIO_PINCFG16_NCESRC16_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51628   GPIO_PINCFG16_NCESRC16_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51629   GPIO_PINCFG16_NCESRC16_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51630   GPIO_PINCFG16_NCESRC16_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51631 } GPIO_PINCFG16_NCESRC16_Enum;
51632 
51633 /* ===========================================  GPIO PINCFG16 PULLCFG16 [13..15]  ============================================ */
51634 typedef enum {                                  /*!< GPIO_PINCFG16_PULLCFG16                                                   */
51635   GPIO_PINCFG16_PULLCFG16_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51636   GPIO_PINCFG16_PULLCFG16_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51637   GPIO_PINCFG16_PULLCFG16_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51638   GPIO_PINCFG16_PULLCFG16_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51639   GPIO_PINCFG16_PULLCFG16_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51640   GPIO_PINCFG16_PULLCFG16_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51641   GPIO_PINCFG16_PULLCFG16_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51642   GPIO_PINCFG16_PULLCFG16_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51643 } GPIO_PINCFG16_PULLCFG16_Enum;
51644 
51645 /* ==============================================  GPIO PINCFG16 DS16 [10..11]  ============================================== */
51646 typedef enum {                                  /*!< GPIO_PINCFG16_DS16                                                        */
51647   GPIO_PINCFG16_DS16_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51648   GPIO_PINCFG16_DS16_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51649 } GPIO_PINCFG16_DS16_Enum;
51650 
51651 /* =============================================  GPIO PINCFG16 OUTCFG16 [8..9]  ============================================= */
51652 typedef enum {                                  /*!< GPIO_PINCFG16_OUTCFG16                                                    */
51653   GPIO_PINCFG16_OUTCFG16_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51654   GPIO_PINCFG16_OUTCFG16_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51655                                                      and 1 values on pin.                                                      */
51656   GPIO_PINCFG16_OUTCFG16_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51657                                                      low, tristate otherwise.                                                  */
51658   GPIO_PINCFG16_OUTCFG16_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51659                                                      drive 0, 1 of HiZ on pin.                                                 */
51660 } GPIO_PINCFG16_OUTCFG16_Enum;
51661 
51662 /* =============================================  GPIO PINCFG16 IRPTEN16 [6..7]  ============================================= */
51663 typedef enum {                                  /*!< GPIO_PINCFG16_IRPTEN16                                                    */
51664   GPIO_PINCFG16_IRPTEN16_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51665   GPIO_PINCFG16_IRPTEN16_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51666                                                      on this GPIO                                                              */
51667   GPIO_PINCFG16_IRPTEN16_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51668                                                      on this GPIO                                                              */
51669   GPIO_PINCFG16_IRPTEN16_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51670                                                      GPIO                                                                      */
51671 } GPIO_PINCFG16_IRPTEN16_Enum;
51672 
51673 /* =============================================  GPIO PINCFG16 FNCSEL16 [0..3]  ============================================= */
51674 typedef enum {                                  /*!< GPIO_PINCFG16_FNCSEL16                                                    */
51675   GPIO_PINCFG16_FNCSEL16_ADCSE3        = 0,     /*!< ADCSE3 : Analog to Digital Converter SE IN3                               */
51676   GPIO_PINCFG16_FNCSEL16_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
51677   GPIO_PINCFG16_FNCSEL16_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
51678                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51679                                                      2)                                                                        */
51680   GPIO_PINCFG16_FNCSEL16_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51681   GPIO_PINCFG16_FNCSEL16_MILLI_PBDATA1 = 4,     /*!< MILLI_PBDATA1 : MILLI Playback Data1                                      */
51682   GPIO_PINCFG16_FNCSEL16_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
51683   GPIO_PINCFG16_FNCSEL16_CT16          = 6,     /*!< CT16 : Timer/Counter input or output; Selection of direction
51684                                                      is done via CTIMER register settings.                                     */
51685   GPIO_PINCFG16_FNCSEL16_NCE16         = 7,     /*!< NCE16 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51686                                                      CE_POLARITY field                                                         */
51687   GPIO_PINCFG16_FNCSEL16_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
51688   GPIO_PINCFG16_FNCSEL16_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51689   GPIO_PINCFG16_FNCSEL16_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51690   GPIO_PINCFG16_FNCSEL16_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51691   GPIO_PINCFG16_FNCSEL16_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51692   GPIO_PINCFG16_FNCSEL16_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51693   GPIO_PINCFG16_FNCSEL16_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51694   GPIO_PINCFG16_FNCSEL16_DFT_RET       = 15,    /*!< DFT_RET : Internal function (SCAN)                                        */
51695 } GPIO_PINCFG16_FNCSEL16_Enum;
51696 
51697 /* =======================================================  PINCFG17  ======================================================== */
51698 /* ============================================  GPIO PINCFG17 NCEPOL17 [22..22]  ============================================ */
51699 typedef enum {                                  /*!< GPIO_PINCFG17_NCEPOL17                                                    */
51700   GPIO_PINCFG17_NCEPOL17_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51701   GPIO_PINCFG17_NCEPOL17_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51702 } GPIO_PINCFG17_NCEPOL17_Enum;
51703 
51704 /* ============================================  GPIO PINCFG17 NCESRC17 [16..21]  ============================================ */
51705 typedef enum {                                  /*!< GPIO_PINCFG17_NCESRC17                                                    */
51706   GPIO_PINCFG17_NCESRC17_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51707   GPIO_PINCFG17_NCESRC17_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51708   GPIO_PINCFG17_NCESRC17_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51709   GPIO_PINCFG17_NCESRC17_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51710   GPIO_PINCFG17_NCESRC17_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51711   GPIO_PINCFG17_NCESRC17_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51712   GPIO_PINCFG17_NCESRC17_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51713   GPIO_PINCFG17_NCESRC17_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51714   GPIO_PINCFG17_NCESRC17_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51715   GPIO_PINCFG17_NCESRC17_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51716   GPIO_PINCFG17_NCESRC17_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51717   GPIO_PINCFG17_NCESRC17_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51718   GPIO_PINCFG17_NCESRC17_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51719   GPIO_PINCFG17_NCESRC17_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51720   GPIO_PINCFG17_NCESRC17_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51721   GPIO_PINCFG17_NCESRC17_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51722   GPIO_PINCFG17_NCESRC17_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51723   GPIO_PINCFG17_NCESRC17_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51724   GPIO_PINCFG17_NCESRC17_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51725   GPIO_PINCFG17_NCESRC17_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51726   GPIO_PINCFG17_NCESRC17_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51727   GPIO_PINCFG17_NCESRC17_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51728   GPIO_PINCFG17_NCESRC17_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51729   GPIO_PINCFG17_NCESRC17_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51730   GPIO_PINCFG17_NCESRC17_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51731   GPIO_PINCFG17_NCESRC17_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51732   GPIO_PINCFG17_NCESRC17_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51733   GPIO_PINCFG17_NCESRC17_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51734   GPIO_PINCFG17_NCESRC17_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51735   GPIO_PINCFG17_NCESRC17_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51736   GPIO_PINCFG17_NCESRC17_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51737   GPIO_PINCFG17_NCESRC17_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51738   GPIO_PINCFG17_NCESRC17_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51739   GPIO_PINCFG17_NCESRC17_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51740   GPIO_PINCFG17_NCESRC17_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51741   GPIO_PINCFG17_NCESRC17_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51742   GPIO_PINCFG17_NCESRC17_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51743   GPIO_PINCFG17_NCESRC17_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51744   GPIO_PINCFG17_NCESRC17_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51745   GPIO_PINCFG17_NCESRC17_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51746   GPIO_PINCFG17_NCESRC17_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51747   GPIO_PINCFG17_NCESRC17_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51748   GPIO_PINCFG17_NCESRC17_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51749 } GPIO_PINCFG17_NCESRC17_Enum;
51750 
51751 /* ===========================================  GPIO PINCFG17 PULLCFG17 [13..15]  ============================================ */
51752 typedef enum {                                  /*!< GPIO_PINCFG17_PULLCFG17                                                   */
51753   GPIO_PINCFG17_PULLCFG17_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51754   GPIO_PINCFG17_PULLCFG17_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51755   GPIO_PINCFG17_PULLCFG17_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51756   GPIO_PINCFG17_PULLCFG17_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51757   GPIO_PINCFG17_PULLCFG17_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51758   GPIO_PINCFG17_PULLCFG17_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51759   GPIO_PINCFG17_PULLCFG17_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51760   GPIO_PINCFG17_PULLCFG17_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51761 } GPIO_PINCFG17_PULLCFG17_Enum;
51762 
51763 /* ==============================================  GPIO PINCFG17 DS17 [10..11]  ============================================== */
51764 typedef enum {                                  /*!< GPIO_PINCFG17_DS17                                                        */
51765   GPIO_PINCFG17_DS17_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51766   GPIO_PINCFG17_DS17_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51767 } GPIO_PINCFG17_DS17_Enum;
51768 
51769 /* =============================================  GPIO PINCFG17 OUTCFG17 [8..9]  ============================================= */
51770 typedef enum {                                  /*!< GPIO_PINCFG17_OUTCFG17                                                    */
51771   GPIO_PINCFG17_OUTCFG17_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51772   GPIO_PINCFG17_OUTCFG17_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51773                                                      and 1 values on pin.                                                      */
51774   GPIO_PINCFG17_OUTCFG17_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51775                                                      low, tristate otherwise.                                                  */
51776   GPIO_PINCFG17_OUTCFG17_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51777                                                      drive 0, 1 of HiZ on pin.                                                 */
51778 } GPIO_PINCFG17_OUTCFG17_Enum;
51779 
51780 /* =============================================  GPIO PINCFG17 IRPTEN17 [6..7]  ============================================= */
51781 typedef enum {                                  /*!< GPIO_PINCFG17_IRPTEN17                                                    */
51782   GPIO_PINCFG17_IRPTEN17_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51783   GPIO_PINCFG17_IRPTEN17_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51784                                                      on this GPIO                                                              */
51785   GPIO_PINCFG17_IRPTEN17_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51786                                                      on this GPIO                                                              */
51787   GPIO_PINCFG17_IRPTEN17_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51788                                                      GPIO                                                                      */
51789 } GPIO_PINCFG17_IRPTEN17_Enum;
51790 
51791 /* =============================================  GPIO PINCFG17 FNCSEL17 [0..3]  ============================================= */
51792 typedef enum {                                  /*!< GPIO_PINCFG17_FNCSEL17                                                    */
51793   GPIO_PINCFG17_FNCSEL17_ADCSE2        = 0,     /*!< ADCSE2 : Analog to Digital Converter SE IN2                               */
51794   GPIO_PINCFG17_FNCSEL17_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
51795   GPIO_PINCFG17_FNCSEL17_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
51796                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51797                                                      2)                                                                        */
51798   GPIO_PINCFG17_FNCSEL17_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51799   GPIO_PINCFG17_FNCSEL17_MILLI_PBDATA2 = 4,     /*!< MILLI_PBDATA2 : MILLI Playback Data2                                      */
51800   GPIO_PINCFG17_FNCSEL17_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
51801   GPIO_PINCFG17_FNCSEL17_CT17          = 6,     /*!< CT17 : Timer/Counter input or output; Selection of direction
51802                                                      is done via CTIMER register settings.                                     */
51803   GPIO_PINCFG17_FNCSEL17_NCE17         = 7,     /*!< NCE17 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51804                                                      CE_POLARITY field                                                         */
51805   GPIO_PINCFG17_FNCSEL17_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
51806   GPIO_PINCFG17_FNCSEL17_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
51807   GPIO_PINCFG17_FNCSEL17_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51808   GPIO_PINCFG17_FNCSEL17_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51809   GPIO_PINCFG17_FNCSEL17_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51810   GPIO_PINCFG17_FNCSEL17_FLLOAD_STRB   = 13,    /*!< FLLOAD_STRB : Internal function (Flash parallel load)                     */
51811   GPIO_PINCFG17_FNCSEL17_MDA_TMS       = 14,    /*!< MDA_TMS : Internal function (MBIST)                                       */
51812   GPIO_PINCFG17_FNCSEL17_OPCG_CLK      = 15,    /*!< OPCG_CLK : Internal function (SCAN)                                       */
51813 } GPIO_PINCFG17_FNCSEL17_Enum;
51814 
51815 /* =======================================================  PINCFG18  ======================================================== */
51816 /* ============================================  GPIO PINCFG18 NCEPOL18 [22..22]  ============================================ */
51817 typedef enum {                                  /*!< GPIO_PINCFG18_NCEPOL18                                                    */
51818   GPIO_PINCFG18_NCEPOL18_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51819   GPIO_PINCFG18_NCEPOL18_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51820 } GPIO_PINCFG18_NCEPOL18_Enum;
51821 
51822 /* ============================================  GPIO PINCFG18 NCESRC18 [16..21]  ============================================ */
51823 typedef enum {                                  /*!< GPIO_PINCFG18_NCESRC18                                                    */
51824   GPIO_PINCFG18_NCESRC18_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51825   GPIO_PINCFG18_NCESRC18_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51826   GPIO_PINCFG18_NCESRC18_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51827   GPIO_PINCFG18_NCESRC18_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51828   GPIO_PINCFG18_NCESRC18_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51829   GPIO_PINCFG18_NCESRC18_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51830   GPIO_PINCFG18_NCESRC18_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51831   GPIO_PINCFG18_NCESRC18_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51832   GPIO_PINCFG18_NCESRC18_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51833   GPIO_PINCFG18_NCESRC18_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51834   GPIO_PINCFG18_NCESRC18_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51835   GPIO_PINCFG18_NCESRC18_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51836   GPIO_PINCFG18_NCESRC18_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51837   GPIO_PINCFG18_NCESRC18_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51838   GPIO_PINCFG18_NCESRC18_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51839   GPIO_PINCFG18_NCESRC18_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51840   GPIO_PINCFG18_NCESRC18_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51841   GPIO_PINCFG18_NCESRC18_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51842   GPIO_PINCFG18_NCESRC18_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51843   GPIO_PINCFG18_NCESRC18_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51844   GPIO_PINCFG18_NCESRC18_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51845   GPIO_PINCFG18_NCESRC18_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51846   GPIO_PINCFG18_NCESRC18_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51847   GPIO_PINCFG18_NCESRC18_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51848   GPIO_PINCFG18_NCESRC18_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51849   GPIO_PINCFG18_NCESRC18_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51850   GPIO_PINCFG18_NCESRC18_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51851   GPIO_PINCFG18_NCESRC18_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51852   GPIO_PINCFG18_NCESRC18_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51853   GPIO_PINCFG18_NCESRC18_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51854   GPIO_PINCFG18_NCESRC18_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51855   GPIO_PINCFG18_NCESRC18_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51856   GPIO_PINCFG18_NCESRC18_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51857   GPIO_PINCFG18_NCESRC18_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51858   GPIO_PINCFG18_NCESRC18_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51859   GPIO_PINCFG18_NCESRC18_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51860   GPIO_PINCFG18_NCESRC18_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51861   GPIO_PINCFG18_NCESRC18_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51862   GPIO_PINCFG18_NCESRC18_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51863   GPIO_PINCFG18_NCESRC18_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51864   GPIO_PINCFG18_NCESRC18_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51865   GPIO_PINCFG18_NCESRC18_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51866   GPIO_PINCFG18_NCESRC18_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51867 } GPIO_PINCFG18_NCESRC18_Enum;
51868 
51869 /* ===========================================  GPIO PINCFG18 PULLCFG18 [13..15]  ============================================ */
51870 typedef enum {                                  /*!< GPIO_PINCFG18_PULLCFG18                                                   */
51871   GPIO_PINCFG18_PULLCFG18_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51872   GPIO_PINCFG18_PULLCFG18_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51873   GPIO_PINCFG18_PULLCFG18_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51874   GPIO_PINCFG18_PULLCFG18_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51875   GPIO_PINCFG18_PULLCFG18_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51876   GPIO_PINCFG18_PULLCFG18_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51877   GPIO_PINCFG18_PULLCFG18_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51878   GPIO_PINCFG18_PULLCFG18_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51879 } GPIO_PINCFG18_PULLCFG18_Enum;
51880 
51881 /* ==============================================  GPIO PINCFG18 DS18 [10..11]  ============================================== */
51882 typedef enum {                                  /*!< GPIO_PINCFG18_DS18                                                        */
51883   GPIO_PINCFG18_DS18_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51884   GPIO_PINCFG18_DS18_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51885 } GPIO_PINCFG18_DS18_Enum;
51886 
51887 /* =============================================  GPIO PINCFG18 OUTCFG18 [8..9]  ============================================= */
51888 typedef enum {                                  /*!< GPIO_PINCFG18_OUTCFG18                                                    */
51889   GPIO_PINCFG18_OUTCFG18_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
51890   GPIO_PINCFG18_OUTCFG18_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51891                                                      and 1 values on pin.                                                      */
51892   GPIO_PINCFG18_OUTCFG18_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51893                                                      low, tristate otherwise.                                                  */
51894   GPIO_PINCFG18_OUTCFG18_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51895                                                      drive 0, 1 of HiZ on pin.                                                 */
51896 } GPIO_PINCFG18_OUTCFG18_Enum;
51897 
51898 /* =============================================  GPIO PINCFG18 IRPTEN18 [6..7]  ============================================= */
51899 typedef enum {                                  /*!< GPIO_PINCFG18_IRPTEN18                                                    */
51900   GPIO_PINCFG18_IRPTEN18_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51901   GPIO_PINCFG18_IRPTEN18_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51902                                                      on this GPIO                                                              */
51903   GPIO_PINCFG18_IRPTEN18_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51904                                                      on this GPIO                                                              */
51905   GPIO_PINCFG18_IRPTEN18_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51906                                                      GPIO                                                                      */
51907 } GPIO_PINCFG18_IRPTEN18_Enum;
51908 
51909 /* =============================================  GPIO PINCFG18 FNCSEL18 [0..3]  ============================================= */
51910 typedef enum {                                  /*!< GPIO_PINCFG18_FNCSEL18                                                    */
51911   GPIO_PINCFG18_FNCSEL18_ADCSE1        = 0,     /*!< ADCSE1 : Analog to Digital Converter SE IN1                               */
51912   GPIO_PINCFG18_FNCSEL18_ANATEST2      = 1,     /*!< ANATEST2 : Ambiq Analog test I/O - Unbuffered                             */
51913   GPIO_PINCFG18_FNCSEL18_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
51914                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51915                                                      2)                                                                        */
51916   GPIO_PINCFG18_FNCSEL18_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
51917   GPIO_PINCFG18_FNCSEL18_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
51918   GPIO_PINCFG18_FNCSEL18_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
51919   GPIO_PINCFG18_FNCSEL18_CT18          = 6,     /*!< CT18 : Timer/Counter input or output; Selection of direction
51920                                                      is done via CTIMER register settings.                                     */
51921   GPIO_PINCFG18_FNCSEL18_NCE18         = 7,     /*!< NCE18 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51922                                                      CE_POLARITY field                                                         */
51923   GPIO_PINCFG18_FNCSEL18_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
51924   GPIO_PINCFG18_FNCSEL18_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51925   GPIO_PINCFG18_FNCSEL18_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51926   GPIO_PINCFG18_FNCSEL18_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
51927   GPIO_PINCFG18_FNCSEL18_FLB_TMS       = 12,    /*!< FLB_TMS : Internal function (Flash Bist)                                  */
51928   GPIO_PINCFG18_FNCSEL18_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
51929   GPIO_PINCFG18_FNCSEL18_MDA_HFRC_EXT  = 14,    /*!< MDA_HFRC_EXT : Internal function (MBIST)                                  */
51930   GPIO_PINCFG18_FNCSEL18_SCANIN1       = 15,    /*!< SCANIN1 : Internal function (SCAN)                                        */
51931 } GPIO_PINCFG18_FNCSEL18_Enum;
51932 
51933 /* =======================================================  PINCFG19  ======================================================== */
51934 /* ============================================  GPIO PINCFG19 NCEPOL19 [22..22]  ============================================ */
51935 typedef enum {                                  /*!< GPIO_PINCFG19_NCEPOL19                                                    */
51936   GPIO_PINCFG19_NCEPOL19_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51937   GPIO_PINCFG19_NCEPOL19_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51938 } GPIO_PINCFG19_NCEPOL19_Enum;
51939 
51940 /* ============================================  GPIO PINCFG19 NCESRC19 [16..21]  ============================================ */
51941 typedef enum {                                  /*!< GPIO_PINCFG19_NCESRC19                                                    */
51942   GPIO_PINCFG19_NCESRC19_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51943   GPIO_PINCFG19_NCESRC19_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51944   GPIO_PINCFG19_NCESRC19_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51945   GPIO_PINCFG19_NCESRC19_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51946   GPIO_PINCFG19_NCESRC19_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51947   GPIO_PINCFG19_NCESRC19_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51948   GPIO_PINCFG19_NCESRC19_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51949   GPIO_PINCFG19_NCESRC19_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51950   GPIO_PINCFG19_NCESRC19_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51951   GPIO_PINCFG19_NCESRC19_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51952   GPIO_PINCFG19_NCESRC19_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51953   GPIO_PINCFG19_NCESRC19_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51954   GPIO_PINCFG19_NCESRC19_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51955   GPIO_PINCFG19_NCESRC19_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51956   GPIO_PINCFG19_NCESRC19_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51957   GPIO_PINCFG19_NCESRC19_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51958   GPIO_PINCFG19_NCESRC19_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51959   GPIO_PINCFG19_NCESRC19_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51960   GPIO_PINCFG19_NCESRC19_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51961   GPIO_PINCFG19_NCESRC19_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51962   GPIO_PINCFG19_NCESRC19_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51963   GPIO_PINCFG19_NCESRC19_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51964   GPIO_PINCFG19_NCESRC19_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51965   GPIO_PINCFG19_NCESRC19_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51966   GPIO_PINCFG19_NCESRC19_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51967   GPIO_PINCFG19_NCESRC19_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51968   GPIO_PINCFG19_NCESRC19_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51969   GPIO_PINCFG19_NCESRC19_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51970   GPIO_PINCFG19_NCESRC19_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51971   GPIO_PINCFG19_NCESRC19_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51972   GPIO_PINCFG19_NCESRC19_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51973   GPIO_PINCFG19_NCESRC19_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51974   GPIO_PINCFG19_NCESRC19_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51975   GPIO_PINCFG19_NCESRC19_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51976   GPIO_PINCFG19_NCESRC19_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51977   GPIO_PINCFG19_NCESRC19_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51978   GPIO_PINCFG19_NCESRC19_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51979   GPIO_PINCFG19_NCESRC19_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51980   GPIO_PINCFG19_NCESRC19_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51981   GPIO_PINCFG19_NCESRC19_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51982   GPIO_PINCFG19_NCESRC19_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51983   GPIO_PINCFG19_NCESRC19_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51984   GPIO_PINCFG19_NCESRC19_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
51985 } GPIO_PINCFG19_NCESRC19_Enum;
51986 
51987 /* ===========================================  GPIO PINCFG19 PULLCFG19 [13..15]  ============================================ */
51988 typedef enum {                                  /*!< GPIO_PINCFG19_PULLCFG19                                                   */
51989   GPIO_PINCFG19_PULLCFG19_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51990   GPIO_PINCFG19_PULLCFG19_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51991   GPIO_PINCFG19_PULLCFG19_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51992   GPIO_PINCFG19_PULLCFG19_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51993   GPIO_PINCFG19_PULLCFG19_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
51994   GPIO_PINCFG19_PULLCFG19_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
51995   GPIO_PINCFG19_PULLCFG19_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
51996   GPIO_PINCFG19_PULLCFG19_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
51997 } GPIO_PINCFG19_PULLCFG19_Enum;
51998 
51999 /* ==============================================  GPIO PINCFG19 DS19 [10..11]  ============================================== */
52000 typedef enum {                                  /*!< GPIO_PINCFG19_DS19                                                        */
52001   GPIO_PINCFG19_DS19_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52002   GPIO_PINCFG19_DS19_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52003 } GPIO_PINCFG19_DS19_Enum;
52004 
52005 /* =============================================  GPIO PINCFG19 OUTCFG19 [8..9]  ============================================= */
52006 typedef enum {                                  /*!< GPIO_PINCFG19_OUTCFG19                                                    */
52007   GPIO_PINCFG19_OUTCFG19_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52008   GPIO_PINCFG19_OUTCFG19_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52009                                                      and 1 values on pin.                                                      */
52010   GPIO_PINCFG19_OUTCFG19_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52011                                                      low, tristate otherwise.                                                  */
52012   GPIO_PINCFG19_OUTCFG19_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52013                                                      drive 0, 1 of HiZ on pin.                                                 */
52014 } GPIO_PINCFG19_OUTCFG19_Enum;
52015 
52016 /* =============================================  GPIO PINCFG19 IRPTEN19 [6..7]  ============================================= */
52017 typedef enum {                                  /*!< GPIO_PINCFG19_IRPTEN19                                                    */
52018   GPIO_PINCFG19_IRPTEN19_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52019   GPIO_PINCFG19_IRPTEN19_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52020                                                      on this GPIO                                                              */
52021   GPIO_PINCFG19_IRPTEN19_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52022                                                      on this GPIO                                                              */
52023   GPIO_PINCFG19_IRPTEN19_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52024                                                      GPIO                                                                      */
52025 } GPIO_PINCFG19_IRPTEN19_Enum;
52026 
52027 /* =============================================  GPIO PINCFG19 FNCSEL19 [0..3]  ============================================= */
52028 typedef enum {                                  /*!< GPIO_PINCFG19_FNCSEL19                                                    */
52029   GPIO_PINCFG19_FNCSEL19_ADCSE0        = 0,     /*!< ADCSE0 : Analog to Digital Converter SE IN0                               */
52030   GPIO_PINCFG19_FNCSEL19_ANATEST1      = 1,     /*!< ANATEST1 : Ambiq Analog test I/O - Buffered                               */
52031   GPIO_PINCFG19_FNCSEL19_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52032   GPIO_PINCFG19_FNCSEL19_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52033   GPIO_PINCFG19_FNCSEL19_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
52034   GPIO_PINCFG19_FNCSEL19_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
52035   GPIO_PINCFG19_FNCSEL19_CT19          = 6,     /*!< CT19 : Timer/Counter input or output; Selection of direction
52036                                                      is done via CTIMER register settings.                                     */
52037   GPIO_PINCFG19_FNCSEL19_NCE19         = 7,     /*!< NCE19 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52038                                                      CE_POLARITY field                                                         */
52039   GPIO_PINCFG19_FNCSEL19_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
52040   GPIO_PINCFG19_FNCSEL19_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
52041   GPIO_PINCFG19_FNCSEL19_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52042   GPIO_PINCFG19_FNCSEL19_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52043   GPIO_PINCFG19_FNCSEL19_FLB_TRSTN     = 12,    /*!< FLB_TRSTN : Internal function (Flash Bist)                                */
52044   GPIO_PINCFG19_FNCSEL19_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
52045   GPIO_PINCFG19_FNCSEL19_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52046   GPIO_PINCFG19_FNCSEL19_SCANIN2       = 15,    /*!< SCANIN2 : Internal function (SCAN)                                        */
52047 } GPIO_PINCFG19_FNCSEL19_Enum;
52048 
52049 /* =======================================================  PINCFG20  ======================================================== */
52050 /* ============================================  GPIO PINCFG20 NCEPOL20 [22..22]  ============================================ */
52051 typedef enum {                                  /*!< GPIO_PINCFG20_NCEPOL20                                                    */
52052   GPIO_PINCFG20_NCEPOL20_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52053   GPIO_PINCFG20_NCEPOL20_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52054 } GPIO_PINCFG20_NCEPOL20_Enum;
52055 
52056 /* ============================================  GPIO PINCFG20 NCESRC20 [16..21]  ============================================ */
52057 typedef enum {                                  /*!< GPIO_PINCFG20_NCESRC20                                                    */
52058   GPIO_PINCFG20_NCESRC20_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52059   GPIO_PINCFG20_NCESRC20_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52060   GPIO_PINCFG20_NCESRC20_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52061   GPIO_PINCFG20_NCESRC20_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52062   GPIO_PINCFG20_NCESRC20_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52063   GPIO_PINCFG20_NCESRC20_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52064   GPIO_PINCFG20_NCESRC20_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52065   GPIO_PINCFG20_NCESRC20_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52066   GPIO_PINCFG20_NCESRC20_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52067   GPIO_PINCFG20_NCESRC20_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52068   GPIO_PINCFG20_NCESRC20_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52069   GPIO_PINCFG20_NCESRC20_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52070   GPIO_PINCFG20_NCESRC20_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52071   GPIO_PINCFG20_NCESRC20_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52072   GPIO_PINCFG20_NCESRC20_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52073   GPIO_PINCFG20_NCESRC20_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52074   GPIO_PINCFG20_NCESRC20_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52075   GPIO_PINCFG20_NCESRC20_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52076   GPIO_PINCFG20_NCESRC20_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52077   GPIO_PINCFG20_NCESRC20_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52078   GPIO_PINCFG20_NCESRC20_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52079   GPIO_PINCFG20_NCESRC20_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52080   GPIO_PINCFG20_NCESRC20_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52081   GPIO_PINCFG20_NCESRC20_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52082   GPIO_PINCFG20_NCESRC20_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52083   GPIO_PINCFG20_NCESRC20_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52084   GPIO_PINCFG20_NCESRC20_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52085   GPIO_PINCFG20_NCESRC20_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52086   GPIO_PINCFG20_NCESRC20_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52087   GPIO_PINCFG20_NCESRC20_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52088   GPIO_PINCFG20_NCESRC20_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52089   GPIO_PINCFG20_NCESRC20_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52090   GPIO_PINCFG20_NCESRC20_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52091   GPIO_PINCFG20_NCESRC20_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52092   GPIO_PINCFG20_NCESRC20_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52093   GPIO_PINCFG20_NCESRC20_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52094   GPIO_PINCFG20_NCESRC20_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52095   GPIO_PINCFG20_NCESRC20_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52096   GPIO_PINCFG20_NCESRC20_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52097   GPIO_PINCFG20_NCESRC20_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52098   GPIO_PINCFG20_NCESRC20_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52099   GPIO_PINCFG20_NCESRC20_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52100   GPIO_PINCFG20_NCESRC20_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52101 } GPIO_PINCFG20_NCESRC20_Enum;
52102 
52103 /* ===========================================  GPIO PINCFG20 PULLCFG20 [13..15]  ============================================ */
52104 typedef enum {                                  /*!< GPIO_PINCFG20_PULLCFG20                                                   */
52105   GPIO_PINCFG20_PULLCFG20_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52106   GPIO_PINCFG20_PULLCFG20_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52107   GPIO_PINCFG20_PULLCFG20_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52108   GPIO_PINCFG20_PULLCFG20_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52109   GPIO_PINCFG20_PULLCFG20_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52110   GPIO_PINCFG20_PULLCFG20_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52111   GPIO_PINCFG20_PULLCFG20_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52112   GPIO_PINCFG20_PULLCFG20_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52113 } GPIO_PINCFG20_PULLCFG20_Enum;
52114 
52115 /* ==============================================  GPIO PINCFG20 DS20 [10..11]  ============================================== */
52116 typedef enum {                                  /*!< GPIO_PINCFG20_DS20                                                        */
52117   GPIO_PINCFG20_DS20_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52118   GPIO_PINCFG20_DS20_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52119 } GPIO_PINCFG20_DS20_Enum;
52120 
52121 /* =============================================  GPIO PINCFG20 OUTCFG20 [8..9]  ============================================= */
52122 typedef enum {                                  /*!< GPIO_PINCFG20_OUTCFG20                                                    */
52123   GPIO_PINCFG20_OUTCFG20_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52124   GPIO_PINCFG20_OUTCFG20_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52125                                                      and 1 values on pin.                                                      */
52126   GPIO_PINCFG20_OUTCFG20_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52127                                                      low, tristate otherwise.                                                  */
52128   GPIO_PINCFG20_OUTCFG20_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52129                                                      drive 0, 1 of HiZ on pin.                                                 */
52130 } GPIO_PINCFG20_OUTCFG20_Enum;
52131 
52132 /* =============================================  GPIO PINCFG20 IRPTEN20 [6..7]  ============================================= */
52133 typedef enum {                                  /*!< GPIO_PINCFG20_IRPTEN20                                                    */
52134   GPIO_PINCFG20_IRPTEN20_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52135   GPIO_PINCFG20_IRPTEN20_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52136                                                      on this GPIO                                                              */
52137   GPIO_PINCFG20_IRPTEN20_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52138                                                      on this GPIO                                                              */
52139   GPIO_PINCFG20_IRPTEN20_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52140                                                      GPIO                                                                      */
52141 } GPIO_PINCFG20_IRPTEN20_Enum;
52142 
52143 /* =============================================  GPIO PINCFG20 FNCSEL20 [0..3]  ============================================= */
52144 typedef enum {                                  /*!< GPIO_PINCFG20_FNCSEL20                                                    */
52145   GPIO_PINCFG20_FNCSEL20_SWDCK         = 0,     /*!< SWDCK : Serial Wire Debug clock input                                     */
52146   GPIO_PINCFG20_FNCSEL20_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
52147   GPIO_PINCFG20_FNCSEL20_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52148   GPIO_PINCFG20_FNCSEL20_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52149   GPIO_PINCFG20_FNCSEL20_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
52150   GPIO_PINCFG20_FNCSEL20_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
52151   GPIO_PINCFG20_FNCSEL20_CT20          = 6,     /*!< CT20 : Timer/Counter input or output; Selection of direction
52152                                                      is done via CTIMER register settings.                                     */
52153   GPIO_PINCFG20_FNCSEL20_NCE20         = 7,     /*!< NCE20 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52154                                                      CE_POLARITY field                                                         */
52155   GPIO_PINCFG20_FNCSEL20_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
52156   GPIO_PINCFG20_FNCSEL20_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52157   GPIO_PINCFG20_FNCSEL20_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52158   GPIO_PINCFG20_FNCSEL20_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52159   GPIO_PINCFG20_FNCSEL20_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52160   GPIO_PINCFG20_FNCSEL20_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52161   GPIO_PINCFG20_FNCSEL20_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52162   GPIO_PINCFG20_FNCSEL20_SCANCLK       = 15,    /*!< SCANCLK : Internal function (SCAN)                                        */
52163 } GPIO_PINCFG20_FNCSEL20_Enum;
52164 
52165 /* =======================================================  PINCFG21  ======================================================== */
52166 /* ============================================  GPIO PINCFG21 NCEPOL21 [22..22]  ============================================ */
52167 typedef enum {                                  /*!< GPIO_PINCFG21_NCEPOL21                                                    */
52168   GPIO_PINCFG21_NCEPOL21_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52169   GPIO_PINCFG21_NCEPOL21_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52170 } GPIO_PINCFG21_NCEPOL21_Enum;
52171 
52172 /* ============================================  GPIO PINCFG21 NCESRC21 [16..21]  ============================================ */
52173 typedef enum {                                  /*!< GPIO_PINCFG21_NCESRC21                                                    */
52174   GPIO_PINCFG21_NCESRC21_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52175   GPIO_PINCFG21_NCESRC21_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52176   GPIO_PINCFG21_NCESRC21_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52177   GPIO_PINCFG21_NCESRC21_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52178   GPIO_PINCFG21_NCESRC21_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52179   GPIO_PINCFG21_NCESRC21_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52180   GPIO_PINCFG21_NCESRC21_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52181   GPIO_PINCFG21_NCESRC21_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52182   GPIO_PINCFG21_NCESRC21_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52183   GPIO_PINCFG21_NCESRC21_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52184   GPIO_PINCFG21_NCESRC21_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52185   GPIO_PINCFG21_NCESRC21_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52186   GPIO_PINCFG21_NCESRC21_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52187   GPIO_PINCFG21_NCESRC21_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52188   GPIO_PINCFG21_NCESRC21_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52189   GPIO_PINCFG21_NCESRC21_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52190   GPIO_PINCFG21_NCESRC21_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52191   GPIO_PINCFG21_NCESRC21_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52192   GPIO_PINCFG21_NCESRC21_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52193   GPIO_PINCFG21_NCESRC21_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52194   GPIO_PINCFG21_NCESRC21_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52195   GPIO_PINCFG21_NCESRC21_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52196   GPIO_PINCFG21_NCESRC21_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52197   GPIO_PINCFG21_NCESRC21_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52198   GPIO_PINCFG21_NCESRC21_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52199   GPIO_PINCFG21_NCESRC21_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52200   GPIO_PINCFG21_NCESRC21_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52201   GPIO_PINCFG21_NCESRC21_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52202   GPIO_PINCFG21_NCESRC21_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52203   GPIO_PINCFG21_NCESRC21_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52204   GPIO_PINCFG21_NCESRC21_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52205   GPIO_PINCFG21_NCESRC21_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52206   GPIO_PINCFG21_NCESRC21_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52207   GPIO_PINCFG21_NCESRC21_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52208   GPIO_PINCFG21_NCESRC21_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52209   GPIO_PINCFG21_NCESRC21_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52210   GPIO_PINCFG21_NCESRC21_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52211   GPIO_PINCFG21_NCESRC21_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52212   GPIO_PINCFG21_NCESRC21_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52213   GPIO_PINCFG21_NCESRC21_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52214   GPIO_PINCFG21_NCESRC21_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52215   GPIO_PINCFG21_NCESRC21_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52216   GPIO_PINCFG21_NCESRC21_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52217 } GPIO_PINCFG21_NCESRC21_Enum;
52218 
52219 /* ===========================================  GPIO PINCFG21 PULLCFG21 [13..15]  ============================================ */
52220 typedef enum {                                  /*!< GPIO_PINCFG21_PULLCFG21                                                   */
52221   GPIO_PINCFG21_PULLCFG21_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52222   GPIO_PINCFG21_PULLCFG21_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52223   GPIO_PINCFG21_PULLCFG21_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52224   GPIO_PINCFG21_PULLCFG21_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52225   GPIO_PINCFG21_PULLCFG21_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52226   GPIO_PINCFG21_PULLCFG21_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52227   GPIO_PINCFG21_PULLCFG21_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52228   GPIO_PINCFG21_PULLCFG21_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52229 } GPIO_PINCFG21_PULLCFG21_Enum;
52230 
52231 /* ==============================================  GPIO PINCFG21 DS21 [10..11]  ============================================== */
52232 typedef enum {                                  /*!< GPIO_PINCFG21_DS21                                                        */
52233   GPIO_PINCFG21_DS21_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52234   GPIO_PINCFG21_DS21_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52235 } GPIO_PINCFG21_DS21_Enum;
52236 
52237 /* =============================================  GPIO PINCFG21 OUTCFG21 [8..9]  ============================================= */
52238 typedef enum {                                  /*!< GPIO_PINCFG21_OUTCFG21                                                    */
52239   GPIO_PINCFG21_OUTCFG21_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52240   GPIO_PINCFG21_OUTCFG21_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52241                                                      and 1 values on pin.                                                      */
52242   GPIO_PINCFG21_OUTCFG21_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52243                                                      low, tristate otherwise.                                                  */
52244   GPIO_PINCFG21_OUTCFG21_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52245                                                      drive 0, 1 of HiZ on pin.                                                 */
52246 } GPIO_PINCFG21_OUTCFG21_Enum;
52247 
52248 /* =============================================  GPIO PINCFG21 IRPTEN21 [6..7]  ============================================= */
52249 typedef enum {                                  /*!< GPIO_PINCFG21_IRPTEN21                                                    */
52250   GPIO_PINCFG21_IRPTEN21_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52251   GPIO_PINCFG21_IRPTEN21_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52252                                                      on this GPIO                                                              */
52253   GPIO_PINCFG21_IRPTEN21_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52254                                                      on this GPIO                                                              */
52255   GPIO_PINCFG21_IRPTEN21_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52256                                                      GPIO                                                                      */
52257 } GPIO_PINCFG21_IRPTEN21_Enum;
52258 
52259 /* =============================================  GPIO PINCFG21 FNCSEL21 [0..3]  ============================================= */
52260 typedef enum {                                  /*!< GPIO_PINCFG21_FNCSEL21                                                    */
52261   GPIO_PINCFG21_FNCSEL21_SWDIO         = 0,     /*!< SWDIO : Serial Wire Debug data input/output                               */
52262   GPIO_PINCFG21_FNCSEL21_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
52263   GPIO_PINCFG21_FNCSEL21_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52264   GPIO_PINCFG21_FNCSEL21_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52265   GPIO_PINCFG21_FNCSEL21_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
52266   GPIO_PINCFG21_FNCSEL21_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
52267   GPIO_PINCFG21_FNCSEL21_CT21          = 6,     /*!< CT21 : Timer/Counter input or output; Selection of direction
52268                                                      is done via CTIMER register settings.                                     */
52269   GPIO_PINCFG21_FNCSEL21_NCE21         = 7,     /*!< NCE21 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52270                                                      CE_POLARITY field                                                         */
52271   GPIO_PINCFG21_FNCSEL21_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
52272   GPIO_PINCFG21_FNCSEL21_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52273   GPIO_PINCFG21_FNCSEL21_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52274   GPIO_PINCFG21_FNCSEL21_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52275   GPIO_PINCFG21_FNCSEL21_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52276   GPIO_PINCFG21_FNCSEL21_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52277   GPIO_PINCFG21_FNCSEL21_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52278   GPIO_PINCFG21_FNCSEL21_SCANSHFT      = 15,    /*!< SCANSHFT : Internal function (SCAN)                                       */
52279 } GPIO_PINCFG21_FNCSEL21_Enum;
52280 
52281 /* =======================================================  PINCFG22  ======================================================== */
52282 /* ============================================  GPIO PINCFG22 NCEPOL22 [22..22]  ============================================ */
52283 typedef enum {                                  /*!< GPIO_PINCFG22_NCEPOL22                                                    */
52284   GPIO_PINCFG22_NCEPOL22_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52285   GPIO_PINCFG22_NCEPOL22_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52286 } GPIO_PINCFG22_NCEPOL22_Enum;
52287 
52288 /* ============================================  GPIO PINCFG22 NCESRC22 [16..21]  ============================================ */
52289 typedef enum {                                  /*!< GPIO_PINCFG22_NCESRC22                                                    */
52290   GPIO_PINCFG22_NCESRC22_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52291   GPIO_PINCFG22_NCESRC22_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52292   GPIO_PINCFG22_NCESRC22_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52293   GPIO_PINCFG22_NCESRC22_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52294   GPIO_PINCFG22_NCESRC22_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52295   GPIO_PINCFG22_NCESRC22_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52296   GPIO_PINCFG22_NCESRC22_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52297   GPIO_PINCFG22_NCESRC22_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52298   GPIO_PINCFG22_NCESRC22_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52299   GPIO_PINCFG22_NCESRC22_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52300   GPIO_PINCFG22_NCESRC22_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52301   GPIO_PINCFG22_NCESRC22_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52302   GPIO_PINCFG22_NCESRC22_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52303   GPIO_PINCFG22_NCESRC22_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52304   GPIO_PINCFG22_NCESRC22_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52305   GPIO_PINCFG22_NCESRC22_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52306   GPIO_PINCFG22_NCESRC22_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52307   GPIO_PINCFG22_NCESRC22_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52308   GPIO_PINCFG22_NCESRC22_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52309   GPIO_PINCFG22_NCESRC22_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52310   GPIO_PINCFG22_NCESRC22_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52311   GPIO_PINCFG22_NCESRC22_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52312   GPIO_PINCFG22_NCESRC22_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52313   GPIO_PINCFG22_NCESRC22_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52314   GPIO_PINCFG22_NCESRC22_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52315   GPIO_PINCFG22_NCESRC22_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52316   GPIO_PINCFG22_NCESRC22_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52317   GPIO_PINCFG22_NCESRC22_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52318   GPIO_PINCFG22_NCESRC22_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52319   GPIO_PINCFG22_NCESRC22_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52320   GPIO_PINCFG22_NCESRC22_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52321   GPIO_PINCFG22_NCESRC22_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52322   GPIO_PINCFG22_NCESRC22_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52323   GPIO_PINCFG22_NCESRC22_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52324   GPIO_PINCFG22_NCESRC22_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52325   GPIO_PINCFG22_NCESRC22_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52326   GPIO_PINCFG22_NCESRC22_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52327   GPIO_PINCFG22_NCESRC22_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52328   GPIO_PINCFG22_NCESRC22_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52329   GPIO_PINCFG22_NCESRC22_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52330   GPIO_PINCFG22_NCESRC22_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52331   GPIO_PINCFG22_NCESRC22_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52332   GPIO_PINCFG22_NCESRC22_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52333 } GPIO_PINCFG22_NCESRC22_Enum;
52334 
52335 /* ===========================================  GPIO PINCFG22 PULLCFG22 [13..15]  ============================================ */
52336 typedef enum {                                  /*!< GPIO_PINCFG22_PULLCFG22                                                   */
52337   GPIO_PINCFG22_PULLCFG22_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52338   GPIO_PINCFG22_PULLCFG22_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52339   GPIO_PINCFG22_PULLCFG22_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52340   GPIO_PINCFG22_PULLCFG22_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52341   GPIO_PINCFG22_PULLCFG22_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52342   GPIO_PINCFG22_PULLCFG22_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52343   GPIO_PINCFG22_PULLCFG22_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52344   GPIO_PINCFG22_PULLCFG22_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52345 } GPIO_PINCFG22_PULLCFG22_Enum;
52346 
52347 /* ==============================================  GPIO PINCFG22 DS22 [10..11]  ============================================== */
52348 typedef enum {                                  /*!< GPIO_PINCFG22_DS22                                                        */
52349   GPIO_PINCFG22_DS22_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52350   GPIO_PINCFG22_DS22_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52351   GPIO_PINCFG22_DS22_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
52352   GPIO_PINCFG22_DS22_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
52353 } GPIO_PINCFG22_DS22_Enum;
52354 
52355 /* =============================================  GPIO PINCFG22 OUTCFG22 [8..9]  ============================================= */
52356 typedef enum {                                  /*!< GPIO_PINCFG22_OUTCFG22                                                    */
52357   GPIO_PINCFG22_OUTCFG22_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52358   GPIO_PINCFG22_OUTCFG22_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52359                                                      and 1 values on pin.                                                      */
52360   GPIO_PINCFG22_OUTCFG22_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52361                                                      low, tristate otherwise.                                                  */
52362   GPIO_PINCFG22_OUTCFG22_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52363                                                      drive 0, 1 of HiZ on pin.                                                 */
52364 } GPIO_PINCFG22_OUTCFG22_Enum;
52365 
52366 /* =============================================  GPIO PINCFG22 IRPTEN22 [6..7]  ============================================= */
52367 typedef enum {                                  /*!< GPIO_PINCFG22_IRPTEN22                                                    */
52368   GPIO_PINCFG22_IRPTEN22_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52369   GPIO_PINCFG22_IRPTEN22_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52370                                                      on this GPIO                                                              */
52371   GPIO_PINCFG22_IRPTEN22_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52372                                                      on this GPIO                                                              */
52373   GPIO_PINCFG22_IRPTEN22_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52374                                                      GPIO                                                                      */
52375 } GPIO_PINCFG22_IRPTEN22_Enum;
52376 
52377 /* =============================================  GPIO PINCFG22 FNCSEL22 [0..3]  ============================================= */
52378 typedef enum {                                  /*!< GPIO_PINCFG22_FNCSEL22                                                    */
52379   GPIO_PINCFG22_FNCSEL22_M7SCL         = 0,     /*!< M7SCL : Serial I2C Master Clock output (IOM 7)                            */
52380   GPIO_PINCFG22_FNCSEL22_M7SCK         = 1,     /*!< M7SCK : Serial SPI Master Clock output (IOM 7)                            */
52381   GPIO_PINCFG22_FNCSEL22_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
52382   GPIO_PINCFG22_FNCSEL22_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52383   GPIO_PINCFG22_FNCSEL22_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
52384   GPIO_PINCFG22_FNCSEL22_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
52385   GPIO_PINCFG22_FNCSEL22_CT22          = 6,     /*!< CT22 : Timer/Counter input or output; Selection of direction
52386                                                      is done via CTIMER register settings.                                     */
52387   GPIO_PINCFG22_FNCSEL22_NCE22         = 7,     /*!< NCE22 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52388                                                      CE_POLARITY field                                                         */
52389   GPIO_PINCFG22_FNCSEL22_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
52390   GPIO_PINCFG22_FNCSEL22_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
52391   GPIO_PINCFG22_FNCSEL22_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52392   GPIO_PINCFG22_FNCSEL22_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52393   GPIO_PINCFG22_FNCSEL22_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52394   GPIO_PINCFG22_FNCSEL22_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52395   GPIO_PINCFG22_FNCSEL22_SCANIN3       = 15,    /*!< SCANIN3 : Internal function (SCAN)                                        */
52396 } GPIO_PINCFG22_FNCSEL22_Enum;
52397 
52398 /* =======================================================  PINCFG23  ======================================================== */
52399 /* ============================================  GPIO PINCFG23 NCEPOL23 [22..22]  ============================================ */
52400 typedef enum {                                  /*!< GPIO_PINCFG23_NCEPOL23                                                    */
52401   GPIO_PINCFG23_NCEPOL23_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52402   GPIO_PINCFG23_NCEPOL23_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52403 } GPIO_PINCFG23_NCEPOL23_Enum;
52404 
52405 /* ============================================  GPIO PINCFG23 NCESRC23 [16..21]  ============================================ */
52406 typedef enum {                                  /*!< GPIO_PINCFG23_NCESRC23                                                    */
52407   GPIO_PINCFG23_NCESRC23_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52408   GPIO_PINCFG23_NCESRC23_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52409   GPIO_PINCFG23_NCESRC23_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52410   GPIO_PINCFG23_NCESRC23_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52411   GPIO_PINCFG23_NCESRC23_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52412   GPIO_PINCFG23_NCESRC23_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52413   GPIO_PINCFG23_NCESRC23_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52414   GPIO_PINCFG23_NCESRC23_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52415   GPIO_PINCFG23_NCESRC23_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52416   GPIO_PINCFG23_NCESRC23_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52417   GPIO_PINCFG23_NCESRC23_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52418   GPIO_PINCFG23_NCESRC23_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52419   GPIO_PINCFG23_NCESRC23_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52420   GPIO_PINCFG23_NCESRC23_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52421   GPIO_PINCFG23_NCESRC23_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52422   GPIO_PINCFG23_NCESRC23_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52423   GPIO_PINCFG23_NCESRC23_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52424   GPIO_PINCFG23_NCESRC23_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52425   GPIO_PINCFG23_NCESRC23_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52426   GPIO_PINCFG23_NCESRC23_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52427   GPIO_PINCFG23_NCESRC23_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52428   GPIO_PINCFG23_NCESRC23_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52429   GPIO_PINCFG23_NCESRC23_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52430   GPIO_PINCFG23_NCESRC23_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52431   GPIO_PINCFG23_NCESRC23_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52432   GPIO_PINCFG23_NCESRC23_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52433   GPIO_PINCFG23_NCESRC23_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52434   GPIO_PINCFG23_NCESRC23_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52435   GPIO_PINCFG23_NCESRC23_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52436   GPIO_PINCFG23_NCESRC23_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52437   GPIO_PINCFG23_NCESRC23_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52438   GPIO_PINCFG23_NCESRC23_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52439   GPIO_PINCFG23_NCESRC23_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52440   GPIO_PINCFG23_NCESRC23_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52441   GPIO_PINCFG23_NCESRC23_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52442   GPIO_PINCFG23_NCESRC23_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52443   GPIO_PINCFG23_NCESRC23_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52444   GPIO_PINCFG23_NCESRC23_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52445   GPIO_PINCFG23_NCESRC23_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52446   GPIO_PINCFG23_NCESRC23_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52447   GPIO_PINCFG23_NCESRC23_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52448   GPIO_PINCFG23_NCESRC23_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52449   GPIO_PINCFG23_NCESRC23_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52450 } GPIO_PINCFG23_NCESRC23_Enum;
52451 
52452 /* ===========================================  GPIO PINCFG23 PULLCFG23 [13..15]  ============================================ */
52453 typedef enum {                                  /*!< GPIO_PINCFG23_PULLCFG23                                                   */
52454   GPIO_PINCFG23_PULLCFG23_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52455   GPIO_PINCFG23_PULLCFG23_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52456   GPIO_PINCFG23_PULLCFG23_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52457   GPIO_PINCFG23_PULLCFG23_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52458   GPIO_PINCFG23_PULLCFG23_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52459   GPIO_PINCFG23_PULLCFG23_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52460   GPIO_PINCFG23_PULLCFG23_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52461   GPIO_PINCFG23_PULLCFG23_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52462 } GPIO_PINCFG23_PULLCFG23_Enum;
52463 
52464 /* ==============================================  GPIO PINCFG23 DS23 [10..11]  ============================================== */
52465 typedef enum {                                  /*!< GPIO_PINCFG23_DS23                                                        */
52466   GPIO_PINCFG23_DS23_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52467   GPIO_PINCFG23_DS23_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52468   GPIO_PINCFG23_DS23_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
52469   GPIO_PINCFG23_DS23_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
52470 } GPIO_PINCFG23_DS23_Enum;
52471 
52472 /* =============================================  GPIO PINCFG23 OUTCFG23 [8..9]  ============================================= */
52473 typedef enum {                                  /*!< GPIO_PINCFG23_OUTCFG23                                                    */
52474   GPIO_PINCFG23_OUTCFG23_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52475   GPIO_PINCFG23_OUTCFG23_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52476                                                      and 1 values on pin.                                                      */
52477   GPIO_PINCFG23_OUTCFG23_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52478                                                      low, tristate otherwise.                                                  */
52479   GPIO_PINCFG23_OUTCFG23_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52480                                                      drive 0, 1 of HiZ on pin.                                                 */
52481 } GPIO_PINCFG23_OUTCFG23_Enum;
52482 
52483 /* =============================================  GPIO PINCFG23 IRPTEN23 [6..7]  ============================================= */
52484 typedef enum {                                  /*!< GPIO_PINCFG23_IRPTEN23                                                    */
52485   GPIO_PINCFG23_IRPTEN23_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52486   GPIO_PINCFG23_IRPTEN23_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52487                                                      on this GPIO                                                              */
52488   GPIO_PINCFG23_IRPTEN23_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52489                                                      on this GPIO                                                              */
52490   GPIO_PINCFG23_IRPTEN23_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52491                                                      GPIO                                                                      */
52492 } GPIO_PINCFG23_IRPTEN23_Enum;
52493 
52494 /* =============================================  GPIO PINCFG23 FNCSEL23 [0..3]  ============================================= */
52495 typedef enum {                                  /*!< GPIO_PINCFG23_FNCSEL23                                                    */
52496   GPIO_PINCFG23_FNCSEL23_M7SDAWIR3     = 0,     /*!< M7SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
52497                                                      Master Data I/O (SPI 3 wire mode) (IOM 7)                                 */
52498   GPIO_PINCFG23_FNCSEL23_M7MOSI        = 1,     /*!< M7MOSI : Serial SPI Master MOSI output (IOM 7)                            */
52499   GPIO_PINCFG23_FNCSEL23_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
52500   GPIO_PINCFG23_FNCSEL23_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52501   GPIO_PINCFG23_FNCSEL23_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
52502   GPIO_PINCFG23_FNCSEL23_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
52503   GPIO_PINCFG23_FNCSEL23_CT23          = 6,     /*!< CT23 : Timer/Counter input or output; Selection of direction
52504                                                      is done via CTIMER register settings.                                     */
52505   GPIO_PINCFG23_FNCSEL23_NCE23         = 7,     /*!< NCE23 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52506                                                      CE_POLARITY field                                                         */
52507   GPIO_PINCFG23_FNCSEL23_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
52508   GPIO_PINCFG23_FNCSEL23_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
52509   GPIO_PINCFG23_FNCSEL23_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52510   GPIO_PINCFG23_FNCSEL23_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52511   GPIO_PINCFG23_FNCSEL23_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52512   GPIO_PINCFG23_FNCSEL23_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52513   GPIO_PINCFG23_FNCSEL23_SCANOUT6      = 15,    /*!< SCANOUT6 : Internal function (SCAN)                                       */
52514 } GPIO_PINCFG23_FNCSEL23_Enum;
52515 
52516 /* =======================================================  PINCFG24  ======================================================== */
52517 /* ============================================  GPIO PINCFG24 NCEPOL24 [22..22]  ============================================ */
52518 typedef enum {                                  /*!< GPIO_PINCFG24_NCEPOL24                                                    */
52519   GPIO_PINCFG24_NCEPOL24_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52520   GPIO_PINCFG24_NCEPOL24_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52521 } GPIO_PINCFG24_NCEPOL24_Enum;
52522 
52523 /* ============================================  GPIO PINCFG24 NCESRC24 [16..21]  ============================================ */
52524 typedef enum {                                  /*!< GPIO_PINCFG24_NCESRC24                                                    */
52525   GPIO_PINCFG24_NCESRC24_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52526   GPIO_PINCFG24_NCESRC24_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52527   GPIO_PINCFG24_NCESRC24_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52528   GPIO_PINCFG24_NCESRC24_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52529   GPIO_PINCFG24_NCESRC24_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52530   GPIO_PINCFG24_NCESRC24_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52531   GPIO_PINCFG24_NCESRC24_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52532   GPIO_PINCFG24_NCESRC24_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52533   GPIO_PINCFG24_NCESRC24_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52534   GPIO_PINCFG24_NCESRC24_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52535   GPIO_PINCFG24_NCESRC24_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52536   GPIO_PINCFG24_NCESRC24_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52537   GPIO_PINCFG24_NCESRC24_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52538   GPIO_PINCFG24_NCESRC24_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52539   GPIO_PINCFG24_NCESRC24_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52540   GPIO_PINCFG24_NCESRC24_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52541   GPIO_PINCFG24_NCESRC24_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52542   GPIO_PINCFG24_NCESRC24_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52543   GPIO_PINCFG24_NCESRC24_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52544   GPIO_PINCFG24_NCESRC24_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52545   GPIO_PINCFG24_NCESRC24_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52546   GPIO_PINCFG24_NCESRC24_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52547   GPIO_PINCFG24_NCESRC24_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52548   GPIO_PINCFG24_NCESRC24_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52549   GPIO_PINCFG24_NCESRC24_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52550   GPIO_PINCFG24_NCESRC24_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52551   GPIO_PINCFG24_NCESRC24_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52552   GPIO_PINCFG24_NCESRC24_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52553   GPIO_PINCFG24_NCESRC24_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52554   GPIO_PINCFG24_NCESRC24_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52555   GPIO_PINCFG24_NCESRC24_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52556   GPIO_PINCFG24_NCESRC24_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52557   GPIO_PINCFG24_NCESRC24_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52558   GPIO_PINCFG24_NCESRC24_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52559   GPIO_PINCFG24_NCESRC24_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52560   GPIO_PINCFG24_NCESRC24_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52561   GPIO_PINCFG24_NCESRC24_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52562   GPIO_PINCFG24_NCESRC24_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52563   GPIO_PINCFG24_NCESRC24_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52564   GPIO_PINCFG24_NCESRC24_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52565   GPIO_PINCFG24_NCESRC24_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52566   GPIO_PINCFG24_NCESRC24_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52567   GPIO_PINCFG24_NCESRC24_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52568 } GPIO_PINCFG24_NCESRC24_Enum;
52569 
52570 /* ===========================================  GPIO PINCFG24 PULLCFG24 [13..15]  ============================================ */
52571 typedef enum {                                  /*!< GPIO_PINCFG24_PULLCFG24                                                   */
52572   GPIO_PINCFG24_PULLCFG24_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52573   GPIO_PINCFG24_PULLCFG24_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52574   GPIO_PINCFG24_PULLCFG24_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52575   GPIO_PINCFG24_PULLCFG24_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52576   GPIO_PINCFG24_PULLCFG24_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52577   GPIO_PINCFG24_PULLCFG24_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52578   GPIO_PINCFG24_PULLCFG24_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52579   GPIO_PINCFG24_PULLCFG24_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52580 } GPIO_PINCFG24_PULLCFG24_Enum;
52581 
52582 /* ==============================================  GPIO PINCFG24 DS24 [10..11]  ============================================== */
52583 typedef enum {                                  /*!< GPIO_PINCFG24_DS24                                                        */
52584   GPIO_PINCFG24_DS24_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52585   GPIO_PINCFG24_DS24_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52586   GPIO_PINCFG24_DS24_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
52587   GPIO_PINCFG24_DS24_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
52588 } GPIO_PINCFG24_DS24_Enum;
52589 
52590 /* =============================================  GPIO PINCFG24 OUTCFG24 [8..9]  ============================================= */
52591 typedef enum {                                  /*!< GPIO_PINCFG24_OUTCFG24                                                    */
52592   GPIO_PINCFG24_OUTCFG24_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52593   GPIO_PINCFG24_OUTCFG24_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52594                                                      and 1 values on pin.                                                      */
52595   GPIO_PINCFG24_OUTCFG24_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52596                                                      low, tristate otherwise.                                                  */
52597   GPIO_PINCFG24_OUTCFG24_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52598                                                      drive 0, 1 of HiZ on pin.                                                 */
52599 } GPIO_PINCFG24_OUTCFG24_Enum;
52600 
52601 /* =============================================  GPIO PINCFG24 IRPTEN24 [6..7]  ============================================= */
52602 typedef enum {                                  /*!< GPIO_PINCFG24_IRPTEN24                                                    */
52603   GPIO_PINCFG24_IRPTEN24_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52604   GPIO_PINCFG24_IRPTEN24_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52605                                                      on this GPIO                                                              */
52606   GPIO_PINCFG24_IRPTEN24_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52607                                                      on this GPIO                                                              */
52608   GPIO_PINCFG24_IRPTEN24_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52609                                                      GPIO                                                                      */
52610 } GPIO_PINCFG24_IRPTEN24_Enum;
52611 
52612 /* =============================================  GPIO PINCFG24 FNCSEL24 [0..3]  ============================================= */
52613 typedef enum {                                  /*!< GPIO_PINCFG24_FNCSEL24                                                    */
52614   GPIO_PINCFG24_FNCSEL24_M7MISO        = 0,     /*!< M7MISO : Serial SPI MASTER MISO input (IOM 7)                             */
52615   GPIO_PINCFG24_FNCSEL24_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
52616   GPIO_PINCFG24_FNCSEL24_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
52617   GPIO_PINCFG24_FNCSEL24_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52618   GPIO_PINCFG24_FNCSEL24_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
52619   GPIO_PINCFG24_FNCSEL24_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
52620   GPIO_PINCFG24_FNCSEL24_CT24          = 6,     /*!< CT24 : Timer/Counter input or output; Selection of direction
52621                                                      is done via CTIMER register settings.                                     */
52622   GPIO_PINCFG24_FNCSEL24_NCE24         = 7,     /*!< NCE24 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52623                                                      CE_POLARITY field                                                         */
52624   GPIO_PINCFG24_FNCSEL24_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
52625   GPIO_PINCFG24_FNCSEL24_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52626   GPIO_PINCFG24_FNCSEL24_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52627   GPIO_PINCFG24_FNCSEL24_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52628   GPIO_PINCFG24_FNCSEL24_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52629   GPIO_PINCFG24_FNCSEL24_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52630   GPIO_PINCFG24_FNCSEL24_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52631   GPIO_PINCFG24_FNCSEL24_SCANOUT7      = 15,    /*!< SCANOUT7 : Internal function (SCAN)                                       */
52632 } GPIO_PINCFG24_FNCSEL24_Enum;
52633 
52634 /* =======================================================  PINCFG25  ======================================================== */
52635 /* ============================================  GPIO PINCFG25 NCEPOL25 [22..22]  ============================================ */
52636 typedef enum {                                  /*!< GPIO_PINCFG25_NCEPOL25                                                    */
52637   GPIO_PINCFG25_NCEPOL25_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52638   GPIO_PINCFG25_NCEPOL25_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52639 } GPIO_PINCFG25_NCEPOL25_Enum;
52640 
52641 /* ============================================  GPIO PINCFG25 NCESRC25 [16..21]  ============================================ */
52642 typedef enum {                                  /*!< GPIO_PINCFG25_NCESRC25                                                    */
52643   GPIO_PINCFG25_NCESRC25_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52644   GPIO_PINCFG25_NCESRC25_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52645   GPIO_PINCFG25_NCESRC25_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52646   GPIO_PINCFG25_NCESRC25_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52647   GPIO_PINCFG25_NCESRC25_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52648   GPIO_PINCFG25_NCESRC25_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52649   GPIO_PINCFG25_NCESRC25_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52650   GPIO_PINCFG25_NCESRC25_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52651   GPIO_PINCFG25_NCESRC25_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52652   GPIO_PINCFG25_NCESRC25_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52653   GPIO_PINCFG25_NCESRC25_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52654   GPIO_PINCFG25_NCESRC25_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52655   GPIO_PINCFG25_NCESRC25_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52656   GPIO_PINCFG25_NCESRC25_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52657   GPIO_PINCFG25_NCESRC25_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52658   GPIO_PINCFG25_NCESRC25_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52659   GPIO_PINCFG25_NCESRC25_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52660   GPIO_PINCFG25_NCESRC25_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52661   GPIO_PINCFG25_NCESRC25_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52662   GPIO_PINCFG25_NCESRC25_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52663   GPIO_PINCFG25_NCESRC25_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52664   GPIO_PINCFG25_NCESRC25_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52665   GPIO_PINCFG25_NCESRC25_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52666   GPIO_PINCFG25_NCESRC25_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52667   GPIO_PINCFG25_NCESRC25_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52668   GPIO_PINCFG25_NCESRC25_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52669   GPIO_PINCFG25_NCESRC25_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52670   GPIO_PINCFG25_NCESRC25_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52671   GPIO_PINCFG25_NCESRC25_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52672   GPIO_PINCFG25_NCESRC25_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52673   GPIO_PINCFG25_NCESRC25_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52674   GPIO_PINCFG25_NCESRC25_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52675   GPIO_PINCFG25_NCESRC25_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52676   GPIO_PINCFG25_NCESRC25_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52677   GPIO_PINCFG25_NCESRC25_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52678   GPIO_PINCFG25_NCESRC25_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52679   GPIO_PINCFG25_NCESRC25_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52680   GPIO_PINCFG25_NCESRC25_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52681   GPIO_PINCFG25_NCESRC25_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52682   GPIO_PINCFG25_NCESRC25_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52683   GPIO_PINCFG25_NCESRC25_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52684   GPIO_PINCFG25_NCESRC25_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52685   GPIO_PINCFG25_NCESRC25_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52686 } GPIO_PINCFG25_NCESRC25_Enum;
52687 
52688 /* ===========================================  GPIO PINCFG25 PULLCFG25 [13..15]  ============================================ */
52689 typedef enum {                                  /*!< GPIO_PINCFG25_PULLCFG25                                                   */
52690   GPIO_PINCFG25_PULLCFG25_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52691   GPIO_PINCFG25_PULLCFG25_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52692   GPIO_PINCFG25_PULLCFG25_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52693   GPIO_PINCFG25_PULLCFG25_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52694   GPIO_PINCFG25_PULLCFG25_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52695   GPIO_PINCFG25_PULLCFG25_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52696   GPIO_PINCFG25_PULLCFG25_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52697   GPIO_PINCFG25_PULLCFG25_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52698 } GPIO_PINCFG25_PULLCFG25_Enum;
52699 
52700 /* ==============================================  GPIO PINCFG25 DS25 [10..11]  ============================================== */
52701 typedef enum {                                  /*!< GPIO_PINCFG25_DS25                                                        */
52702   GPIO_PINCFG25_DS25_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52703   GPIO_PINCFG25_DS25_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52704   GPIO_PINCFG25_DS25_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
52705   GPIO_PINCFG25_DS25_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
52706 } GPIO_PINCFG25_DS25_Enum;
52707 
52708 /* =============================================  GPIO PINCFG25 OUTCFG25 [8..9]  ============================================= */
52709 typedef enum {                                  /*!< GPIO_PINCFG25_OUTCFG25                                                    */
52710   GPIO_PINCFG25_OUTCFG25_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52711   GPIO_PINCFG25_OUTCFG25_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52712                                                      and 1 values on pin.                                                      */
52713   GPIO_PINCFG25_OUTCFG25_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52714                                                      low, tristate otherwise.                                                  */
52715   GPIO_PINCFG25_OUTCFG25_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52716                                                      drive 0, 1 of HiZ on pin.                                                 */
52717 } GPIO_PINCFG25_OUTCFG25_Enum;
52718 
52719 /* =============================================  GPIO PINCFG25 IRPTEN25 [6..7]  ============================================= */
52720 typedef enum {                                  /*!< GPIO_PINCFG25_IRPTEN25                                                    */
52721   GPIO_PINCFG25_IRPTEN25_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52722   GPIO_PINCFG25_IRPTEN25_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52723                                                      on this GPIO                                                              */
52724   GPIO_PINCFG25_IRPTEN25_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52725                                                      on this GPIO                                                              */
52726   GPIO_PINCFG25_IRPTEN25_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52727                                                      GPIO                                                                      */
52728 } GPIO_PINCFG25_IRPTEN25_Enum;
52729 
52730 /* =============================================  GPIO PINCFG25 FNCSEL25 [0..3]  ============================================= */
52731 typedef enum {                                  /*!< GPIO_PINCFG25_FNCSEL25                                                    */
52732   GPIO_PINCFG25_FNCSEL25_M2SCL         = 0,     /*!< M2SCL : Serial I2C Master Clock output (IOM 2)                            */
52733   GPIO_PINCFG25_FNCSEL25_M2SCK         = 1,     /*!< M2SCK : Serial SPI Master Clock output (IOM 2)                            */
52734   GPIO_PINCFG25_FNCSEL25_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52735   GPIO_PINCFG25_FNCSEL25_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52736   GPIO_PINCFG25_FNCSEL25_LFRC_EXT      = 4,     /*!< LFRC_EXT : External LFRC Clock                                            */
52737   GPIO_PINCFG25_FNCSEL25_DSP_TMS       = 5,     /*!< DSP_TMS : JTAG tms input                                                  */
52738   GPIO_PINCFG25_FNCSEL25_CT25          = 6,     /*!< CT25 : Timer/Counter input or output; Selection of direction
52739                                                      is done via CTIMER register settings.                                     */
52740   GPIO_PINCFG25_FNCSEL25_NCE25         = 7,     /*!< NCE25 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52741                                                      CE_POLARITY field                                                         */
52742   GPIO_PINCFG25_FNCSEL25_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
52743   GPIO_PINCFG25_FNCSEL25_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52744   GPIO_PINCFG25_FNCSEL25_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52745   GPIO_PINCFG25_FNCSEL25_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52746   GPIO_PINCFG25_FNCSEL25_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52747   GPIO_PINCFG25_FNCSEL25_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52748   GPIO_PINCFG25_FNCSEL25_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52749   GPIO_PINCFG25_FNCSEL25_SCANIN8       = 15,    /*!< SCANIN8 : Internal function (SCAN)                                        */
52750 } GPIO_PINCFG25_FNCSEL25_Enum;
52751 
52752 /* =======================================================  PINCFG26  ======================================================== */
52753 /* ============================================  GPIO PINCFG26 NCEPOL26 [22..22]  ============================================ */
52754 typedef enum {                                  /*!< GPIO_PINCFG26_NCEPOL26                                                    */
52755   GPIO_PINCFG26_NCEPOL26_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52756   GPIO_PINCFG26_NCEPOL26_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52757 } GPIO_PINCFG26_NCEPOL26_Enum;
52758 
52759 /* ============================================  GPIO PINCFG26 NCESRC26 [16..21]  ============================================ */
52760 typedef enum {                                  /*!< GPIO_PINCFG26_NCESRC26                                                    */
52761   GPIO_PINCFG26_NCESRC26_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52762   GPIO_PINCFG26_NCESRC26_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52763   GPIO_PINCFG26_NCESRC26_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52764   GPIO_PINCFG26_NCESRC26_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52765   GPIO_PINCFG26_NCESRC26_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52766   GPIO_PINCFG26_NCESRC26_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52767   GPIO_PINCFG26_NCESRC26_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52768   GPIO_PINCFG26_NCESRC26_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52769   GPIO_PINCFG26_NCESRC26_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52770   GPIO_PINCFG26_NCESRC26_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52771   GPIO_PINCFG26_NCESRC26_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52772   GPIO_PINCFG26_NCESRC26_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52773   GPIO_PINCFG26_NCESRC26_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52774   GPIO_PINCFG26_NCESRC26_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52775   GPIO_PINCFG26_NCESRC26_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52776   GPIO_PINCFG26_NCESRC26_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52777   GPIO_PINCFG26_NCESRC26_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52778   GPIO_PINCFG26_NCESRC26_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52779   GPIO_PINCFG26_NCESRC26_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52780   GPIO_PINCFG26_NCESRC26_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52781   GPIO_PINCFG26_NCESRC26_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52782   GPIO_PINCFG26_NCESRC26_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52783   GPIO_PINCFG26_NCESRC26_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52784   GPIO_PINCFG26_NCESRC26_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52785   GPIO_PINCFG26_NCESRC26_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52786   GPIO_PINCFG26_NCESRC26_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52787   GPIO_PINCFG26_NCESRC26_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52788   GPIO_PINCFG26_NCESRC26_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52789   GPIO_PINCFG26_NCESRC26_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52790   GPIO_PINCFG26_NCESRC26_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52791   GPIO_PINCFG26_NCESRC26_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52792   GPIO_PINCFG26_NCESRC26_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52793   GPIO_PINCFG26_NCESRC26_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52794   GPIO_PINCFG26_NCESRC26_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52795   GPIO_PINCFG26_NCESRC26_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52796   GPIO_PINCFG26_NCESRC26_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52797   GPIO_PINCFG26_NCESRC26_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52798   GPIO_PINCFG26_NCESRC26_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52799   GPIO_PINCFG26_NCESRC26_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52800   GPIO_PINCFG26_NCESRC26_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52801   GPIO_PINCFG26_NCESRC26_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52802   GPIO_PINCFG26_NCESRC26_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52803   GPIO_PINCFG26_NCESRC26_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52804 } GPIO_PINCFG26_NCESRC26_Enum;
52805 
52806 /* ===========================================  GPIO PINCFG26 PULLCFG26 [13..15]  ============================================ */
52807 typedef enum {                                  /*!< GPIO_PINCFG26_PULLCFG26                                                   */
52808   GPIO_PINCFG26_PULLCFG26_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52809   GPIO_PINCFG26_PULLCFG26_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52810   GPIO_PINCFG26_PULLCFG26_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52811   GPIO_PINCFG26_PULLCFG26_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52812   GPIO_PINCFG26_PULLCFG26_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52813   GPIO_PINCFG26_PULLCFG26_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52814   GPIO_PINCFG26_PULLCFG26_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52815   GPIO_PINCFG26_PULLCFG26_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52816 } GPIO_PINCFG26_PULLCFG26_Enum;
52817 
52818 /* ==============================================  GPIO PINCFG26 DS26 [10..11]  ============================================== */
52819 typedef enum {                                  /*!< GPIO_PINCFG26_DS26                                                        */
52820   GPIO_PINCFG26_DS26_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52821   GPIO_PINCFG26_DS26_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52822   GPIO_PINCFG26_DS26_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
52823   GPIO_PINCFG26_DS26_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
52824 } GPIO_PINCFG26_DS26_Enum;
52825 
52826 /* =============================================  GPIO PINCFG26 OUTCFG26 [8..9]  ============================================= */
52827 typedef enum {                                  /*!< GPIO_PINCFG26_OUTCFG26                                                    */
52828   GPIO_PINCFG26_OUTCFG26_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52829   GPIO_PINCFG26_OUTCFG26_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52830                                                      and 1 values on pin.                                                      */
52831   GPIO_PINCFG26_OUTCFG26_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52832                                                      low, tristate otherwise.                                                  */
52833   GPIO_PINCFG26_OUTCFG26_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52834                                                      drive 0, 1 of HiZ on pin.                                                 */
52835 } GPIO_PINCFG26_OUTCFG26_Enum;
52836 
52837 /* =============================================  GPIO PINCFG26 IRPTEN26 [6..7]  ============================================= */
52838 typedef enum {                                  /*!< GPIO_PINCFG26_IRPTEN26                                                    */
52839   GPIO_PINCFG26_IRPTEN26_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52840   GPIO_PINCFG26_IRPTEN26_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52841                                                      on this GPIO                                                              */
52842   GPIO_PINCFG26_IRPTEN26_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52843                                                      on this GPIO                                                              */
52844   GPIO_PINCFG26_IRPTEN26_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52845                                                      GPIO                                                                      */
52846 } GPIO_PINCFG26_IRPTEN26_Enum;
52847 
52848 /* =============================================  GPIO PINCFG26 FNCSEL26 [0..3]  ============================================= */
52849 typedef enum {                                  /*!< GPIO_PINCFG26_FNCSEL26                                                    */
52850   GPIO_PINCFG26_FNCSEL26_M2SDAWIR3     = 0,     /*!< M2SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
52851                                                      Master Data I/O (SPI 3 wire mode) (IOM 2)                                 */
52852   GPIO_PINCFG26_FNCSEL26_M2MOSI        = 1,     /*!< M2MOSI : Serial SPI Master MOSI output (IOM 2)                            */
52853   GPIO_PINCFG26_FNCSEL26_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52854   GPIO_PINCFG26_FNCSEL26_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52855   GPIO_PINCFG26_FNCSEL26_HFRC_EXT      = 4,     /*!< HFRC_EXT : External HFRC Clock                                            */
52856   GPIO_PINCFG26_FNCSEL26_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
52857   GPIO_PINCFG26_FNCSEL26_CT26          = 6,     /*!< CT26 : Timer/Counter input or output; Selection of direction
52858                                                      is done via CTIMER register settings.                                     */
52859   GPIO_PINCFG26_FNCSEL26_NCE26         = 7,     /*!< NCE26 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52860                                                      CE_POLARITY field                                                         */
52861   GPIO_PINCFG26_FNCSEL26_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
52862   GPIO_PINCFG26_FNCSEL26_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
52863   GPIO_PINCFG26_FNCSEL26_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52864   GPIO_PINCFG26_FNCSEL26_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52865   GPIO_PINCFG26_FNCSEL26_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52866   GPIO_PINCFG26_FNCSEL26_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52867   GPIO_PINCFG26_FNCSEL26_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52868   GPIO_PINCFG26_FNCSEL26_SCANIN9       = 15,    /*!< SCANIN9 : Internal function (SCAN)                                        */
52869 } GPIO_PINCFG26_FNCSEL26_Enum;
52870 
52871 /* =======================================================  PINCFG27  ======================================================== */
52872 /* ============================================  GPIO PINCFG27 NCEPOL27 [22..22]  ============================================ */
52873 typedef enum {                                  /*!< GPIO_PINCFG27_NCEPOL27                                                    */
52874   GPIO_PINCFG27_NCEPOL27_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52875   GPIO_PINCFG27_NCEPOL27_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52876 } GPIO_PINCFG27_NCEPOL27_Enum;
52877 
52878 /* ============================================  GPIO PINCFG27 NCESRC27 [16..21]  ============================================ */
52879 typedef enum {                                  /*!< GPIO_PINCFG27_NCESRC27                                                    */
52880   GPIO_PINCFG27_NCESRC27_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52881   GPIO_PINCFG27_NCESRC27_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52882   GPIO_PINCFG27_NCESRC27_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52883   GPIO_PINCFG27_NCESRC27_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52884   GPIO_PINCFG27_NCESRC27_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52885   GPIO_PINCFG27_NCESRC27_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52886   GPIO_PINCFG27_NCESRC27_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52887   GPIO_PINCFG27_NCESRC27_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52888   GPIO_PINCFG27_NCESRC27_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52889   GPIO_PINCFG27_NCESRC27_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52890   GPIO_PINCFG27_NCESRC27_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52891   GPIO_PINCFG27_NCESRC27_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52892   GPIO_PINCFG27_NCESRC27_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52893   GPIO_PINCFG27_NCESRC27_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52894   GPIO_PINCFG27_NCESRC27_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52895   GPIO_PINCFG27_NCESRC27_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52896   GPIO_PINCFG27_NCESRC27_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52897   GPIO_PINCFG27_NCESRC27_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52898   GPIO_PINCFG27_NCESRC27_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52899   GPIO_PINCFG27_NCESRC27_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52900   GPIO_PINCFG27_NCESRC27_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52901   GPIO_PINCFG27_NCESRC27_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52902   GPIO_PINCFG27_NCESRC27_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52903   GPIO_PINCFG27_NCESRC27_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52904   GPIO_PINCFG27_NCESRC27_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52905   GPIO_PINCFG27_NCESRC27_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52906   GPIO_PINCFG27_NCESRC27_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52907   GPIO_PINCFG27_NCESRC27_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52908   GPIO_PINCFG27_NCESRC27_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52909   GPIO_PINCFG27_NCESRC27_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52910   GPIO_PINCFG27_NCESRC27_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52911   GPIO_PINCFG27_NCESRC27_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52912   GPIO_PINCFG27_NCESRC27_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52913   GPIO_PINCFG27_NCESRC27_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52914   GPIO_PINCFG27_NCESRC27_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52915   GPIO_PINCFG27_NCESRC27_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52916   GPIO_PINCFG27_NCESRC27_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52917   GPIO_PINCFG27_NCESRC27_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52918   GPIO_PINCFG27_NCESRC27_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52919   GPIO_PINCFG27_NCESRC27_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52920   GPIO_PINCFG27_NCESRC27_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52921   GPIO_PINCFG27_NCESRC27_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52922   GPIO_PINCFG27_NCESRC27_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52923 } GPIO_PINCFG27_NCESRC27_Enum;
52924 
52925 /* ===========================================  GPIO PINCFG27 PULLCFG27 [13..15]  ============================================ */
52926 typedef enum {                                  /*!< GPIO_PINCFG27_PULLCFG27                                                   */
52927   GPIO_PINCFG27_PULLCFG27_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52928   GPIO_PINCFG27_PULLCFG27_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52929   GPIO_PINCFG27_PULLCFG27_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52930   GPIO_PINCFG27_PULLCFG27_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52931   GPIO_PINCFG27_PULLCFG27_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52932   GPIO_PINCFG27_PULLCFG27_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52933   GPIO_PINCFG27_PULLCFG27_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52934   GPIO_PINCFG27_PULLCFG27_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52935 } GPIO_PINCFG27_PULLCFG27_Enum;
52936 
52937 /* ==============================================  GPIO PINCFG27 DS27 [10..11]  ============================================== */
52938 typedef enum {                                  /*!< GPIO_PINCFG27_DS27                                                        */
52939   GPIO_PINCFG27_DS27_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52940   GPIO_PINCFG27_DS27_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52941   GPIO_PINCFG27_DS27_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
52942   GPIO_PINCFG27_DS27_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
52943 } GPIO_PINCFG27_DS27_Enum;
52944 
52945 /* =============================================  GPIO PINCFG27 OUTCFG27 [8..9]  ============================================= */
52946 typedef enum {                                  /*!< GPIO_PINCFG27_OUTCFG27                                                    */
52947   GPIO_PINCFG27_OUTCFG27_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52948   GPIO_PINCFG27_OUTCFG27_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52949                                                      and 1 values on pin.                                                      */
52950   GPIO_PINCFG27_OUTCFG27_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52951                                                      low, tristate otherwise.                                                  */
52952   GPIO_PINCFG27_OUTCFG27_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52953                                                      drive 0, 1 of HiZ on pin.                                                 */
52954 } GPIO_PINCFG27_OUTCFG27_Enum;
52955 
52956 /* =============================================  GPIO PINCFG27 IRPTEN27 [6..7]  ============================================= */
52957 typedef enum {                                  /*!< GPIO_PINCFG27_IRPTEN27                                                    */
52958   GPIO_PINCFG27_IRPTEN27_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52959   GPIO_PINCFG27_IRPTEN27_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52960                                                      on this GPIO                                                              */
52961   GPIO_PINCFG27_IRPTEN27_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52962                                                      on this GPIO                                                              */
52963   GPIO_PINCFG27_IRPTEN27_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52964                                                      GPIO                                                                      */
52965 } GPIO_PINCFG27_IRPTEN27_Enum;
52966 
52967 /* =============================================  GPIO PINCFG27 FNCSEL27 [0..3]  ============================================= */
52968 typedef enum {                                  /*!< GPIO_PINCFG27_FNCSEL27                                                    */
52969   GPIO_PINCFG27_FNCSEL27_M2MISO        = 0,     /*!< M2MISO : Serial SPI MASTER MISO input (IOM 2)                             */
52970   GPIO_PINCFG27_FNCSEL27_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
52971   GPIO_PINCFG27_FNCSEL27_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52972   GPIO_PINCFG27_FNCSEL27_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52973   GPIO_PINCFG27_FNCSEL27_XT_EXT        = 4,     /*!< XT_EXT : External XT Clock                                                */
52974   GPIO_PINCFG27_FNCSEL27_DSP_TCK       = 5,     /*!< DSP_TCK : JTAG tck clock interface                                        */
52975   GPIO_PINCFG27_FNCSEL27_CT27          = 6,     /*!< CT27 : Timer/Counter input or output; Selection of direction
52976                                                      is done via CTIMER register settings.                                     */
52977   GPIO_PINCFG27_FNCSEL27_NCE27         = 7,     /*!< NCE27 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52978                                                      CE_POLARITY field                                                         */
52979   GPIO_PINCFG27_FNCSEL27_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
52980   GPIO_PINCFG27_FNCSEL27_I2S0_SDIN     = 9,     /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
52981   GPIO_PINCFG27_FNCSEL27_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52982   GPIO_PINCFG27_FNCSEL27_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52983   GPIO_PINCFG27_FNCSEL27_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52984   GPIO_PINCFG27_FNCSEL27_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52985   GPIO_PINCFG27_FNCSEL27_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52986   GPIO_PINCFG27_FNCSEL27_SCANIN10      = 15,    /*!< SCANIN10 : Internal function (SCAN)                                       */
52987 } GPIO_PINCFG27_FNCSEL27_Enum;
52988 
52989 /* =======================================================  PINCFG28  ======================================================== */
52990 /* ============================================  GPIO PINCFG28 NCEPOL28 [22..22]  ============================================ */
52991 typedef enum {                                  /*!< GPIO_PINCFG28_NCEPOL28                                                    */
52992   GPIO_PINCFG28_NCEPOL28_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52993   GPIO_PINCFG28_NCEPOL28_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52994 } GPIO_PINCFG28_NCEPOL28_Enum;
52995 
52996 /* ============================================  GPIO PINCFG28 NCESRC28 [16..21]  ============================================ */
52997 typedef enum {                                  /*!< GPIO_PINCFG28_NCESRC28                                                    */
52998   GPIO_PINCFG28_NCESRC28_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52999   GPIO_PINCFG28_NCESRC28_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53000   GPIO_PINCFG28_NCESRC28_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53001   GPIO_PINCFG28_NCESRC28_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53002   GPIO_PINCFG28_NCESRC28_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53003   GPIO_PINCFG28_NCESRC28_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53004   GPIO_PINCFG28_NCESRC28_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53005   GPIO_PINCFG28_NCESRC28_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53006   GPIO_PINCFG28_NCESRC28_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53007   GPIO_PINCFG28_NCESRC28_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53008   GPIO_PINCFG28_NCESRC28_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53009   GPIO_PINCFG28_NCESRC28_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53010   GPIO_PINCFG28_NCESRC28_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53011   GPIO_PINCFG28_NCESRC28_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53012   GPIO_PINCFG28_NCESRC28_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53013   GPIO_PINCFG28_NCESRC28_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53014   GPIO_PINCFG28_NCESRC28_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53015   GPIO_PINCFG28_NCESRC28_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53016   GPIO_PINCFG28_NCESRC28_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53017   GPIO_PINCFG28_NCESRC28_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53018   GPIO_PINCFG28_NCESRC28_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53019   GPIO_PINCFG28_NCESRC28_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53020   GPIO_PINCFG28_NCESRC28_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53021   GPIO_PINCFG28_NCESRC28_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53022   GPIO_PINCFG28_NCESRC28_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53023   GPIO_PINCFG28_NCESRC28_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53024   GPIO_PINCFG28_NCESRC28_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53025   GPIO_PINCFG28_NCESRC28_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53026   GPIO_PINCFG28_NCESRC28_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53027   GPIO_PINCFG28_NCESRC28_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53028   GPIO_PINCFG28_NCESRC28_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53029   GPIO_PINCFG28_NCESRC28_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53030   GPIO_PINCFG28_NCESRC28_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53031   GPIO_PINCFG28_NCESRC28_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53032   GPIO_PINCFG28_NCESRC28_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53033   GPIO_PINCFG28_NCESRC28_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53034   GPIO_PINCFG28_NCESRC28_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53035   GPIO_PINCFG28_NCESRC28_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53036   GPIO_PINCFG28_NCESRC28_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53037   GPIO_PINCFG28_NCESRC28_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53038   GPIO_PINCFG28_NCESRC28_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53039   GPIO_PINCFG28_NCESRC28_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53040   GPIO_PINCFG28_NCESRC28_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53041 } GPIO_PINCFG28_NCESRC28_Enum;
53042 
53043 /* ===========================================  GPIO PINCFG28 PULLCFG28 [13..15]  ============================================ */
53044 typedef enum {                                  /*!< GPIO_PINCFG28_PULLCFG28                                                   */
53045   GPIO_PINCFG28_PULLCFG28_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53046   GPIO_PINCFG28_PULLCFG28_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53047   GPIO_PINCFG28_PULLCFG28_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53048   GPIO_PINCFG28_PULLCFG28_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53049   GPIO_PINCFG28_PULLCFG28_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53050   GPIO_PINCFG28_PULLCFG28_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53051   GPIO_PINCFG28_PULLCFG28_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53052   GPIO_PINCFG28_PULLCFG28_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53053 } GPIO_PINCFG28_PULLCFG28_Enum;
53054 
53055 /* ==============================================  GPIO PINCFG28 DS28 [10..11]  ============================================== */
53056 typedef enum {                                  /*!< GPIO_PINCFG28_DS28                                                        */
53057   GPIO_PINCFG28_DS28_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53058   GPIO_PINCFG28_DS28_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53059 } GPIO_PINCFG28_DS28_Enum;
53060 
53061 /* =============================================  GPIO PINCFG28 OUTCFG28 [8..9]  ============================================= */
53062 typedef enum {                                  /*!< GPIO_PINCFG28_OUTCFG28                                                    */
53063   GPIO_PINCFG28_OUTCFG28_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53064   GPIO_PINCFG28_OUTCFG28_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53065                                                      and 1 values on pin.                                                      */
53066   GPIO_PINCFG28_OUTCFG28_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53067                                                      low, tristate otherwise.                                                  */
53068   GPIO_PINCFG28_OUTCFG28_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53069                                                      drive 0, 1 of HiZ on pin.                                                 */
53070 } GPIO_PINCFG28_OUTCFG28_Enum;
53071 
53072 /* =============================================  GPIO PINCFG28 IRPTEN28 [6..7]  ============================================= */
53073 typedef enum {                                  /*!< GPIO_PINCFG28_IRPTEN28                                                    */
53074   GPIO_PINCFG28_IRPTEN28_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53075   GPIO_PINCFG28_IRPTEN28_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53076                                                      on this GPIO                                                              */
53077   GPIO_PINCFG28_IRPTEN28_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53078                                                      on this GPIO                                                              */
53079   GPIO_PINCFG28_IRPTEN28_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53080                                                      GPIO                                                                      */
53081 } GPIO_PINCFG28_IRPTEN28_Enum;
53082 
53083 /* =============================================  GPIO PINCFG28 FNCSEL28 [0..3]  ============================================= */
53084 typedef enum {                                  /*!< GPIO_PINCFG28_FNCSEL28                                                    */
53085   GPIO_PINCFG28_FNCSEL28_SWO           = 0,     /*!< SWO : Serial Wire Output                                                  */
53086   GPIO_PINCFG28_FNCSEL28_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
53087   GPIO_PINCFG28_FNCSEL28_I2S0_CLK      = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
53088                                                      in master mode and input mode for slave mode. (I2S Master/Slave
53089                                                      2)                                                                        */
53090   GPIO_PINCFG28_FNCSEL28_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53091   GPIO_PINCFG28_FNCSEL28_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
53092   GPIO_PINCFG28_FNCSEL28_DSP_TDO       = 5,     /*!< DSP_TDO : JTAG tdo output                                                 */
53093   GPIO_PINCFG28_FNCSEL28_CT28          = 6,     /*!< CT28 : Timer/Counter input or output; Selection of direction
53094                                                      is done via CTIMER register settings.                                     */
53095   GPIO_PINCFG28_FNCSEL28_NCE28         = 7,     /*!< NCE28 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53096                                                      CE_POLARITY field                                                         */
53097   GPIO_PINCFG28_FNCSEL28_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
53098   GPIO_PINCFG28_FNCSEL28_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53099   GPIO_PINCFG28_FNCSEL28_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53100   GPIO_PINCFG28_FNCSEL28_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53101   GPIO_PINCFG28_FNCSEL28_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53102   GPIO_PINCFG28_FNCSEL28_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53103   GPIO_PINCFG28_FNCSEL28_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53104   GPIO_PINCFG28_FNCSEL28_CME           = 15,    /*!< CME : Internal function (SCAN)                                            */
53105 } GPIO_PINCFG28_FNCSEL28_Enum;
53106 
53107 /* =======================================================  PINCFG29  ======================================================== */
53108 /* ==========================================  GPIO PINCFG29 VSSPWRSWEN29 [25..25]  ========================================== */
53109 typedef enum {                                  /*!< GPIO_PINCFG29_VSSPWRSWEN29                                                */
53110   GPIO_PINCFG29_VSSPWRSWEN29_DIS       = 0,     /*!< DIS : Power switch is disabled                                            */
53111   GPIO_PINCFG29_VSSPWRSWEN29_EN        = 1,     /*!< EN : Power switch is enabled                                              */
53112 } GPIO_PINCFG29_VSSPWRSWEN29_Enum;
53113 
53114 /* ============================================  GPIO PINCFG29 NCEPOL29 [22..22]  ============================================ */
53115 typedef enum {                                  /*!< GPIO_PINCFG29_NCEPOL29                                                    */
53116   GPIO_PINCFG29_NCEPOL29_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53117   GPIO_PINCFG29_NCEPOL29_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53118 } GPIO_PINCFG29_NCEPOL29_Enum;
53119 
53120 /* ============================================  GPIO PINCFG29 NCESRC29 [16..21]  ============================================ */
53121 typedef enum {                                  /*!< GPIO_PINCFG29_NCESRC29                                                    */
53122   GPIO_PINCFG29_NCESRC29_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53123   GPIO_PINCFG29_NCESRC29_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53124   GPIO_PINCFG29_NCESRC29_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53125   GPIO_PINCFG29_NCESRC29_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53126   GPIO_PINCFG29_NCESRC29_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53127   GPIO_PINCFG29_NCESRC29_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53128   GPIO_PINCFG29_NCESRC29_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53129   GPIO_PINCFG29_NCESRC29_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53130   GPIO_PINCFG29_NCESRC29_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53131   GPIO_PINCFG29_NCESRC29_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53132   GPIO_PINCFG29_NCESRC29_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53133   GPIO_PINCFG29_NCESRC29_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53134   GPIO_PINCFG29_NCESRC29_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53135   GPIO_PINCFG29_NCESRC29_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53136   GPIO_PINCFG29_NCESRC29_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53137   GPIO_PINCFG29_NCESRC29_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53138   GPIO_PINCFG29_NCESRC29_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53139   GPIO_PINCFG29_NCESRC29_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53140   GPIO_PINCFG29_NCESRC29_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53141   GPIO_PINCFG29_NCESRC29_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53142   GPIO_PINCFG29_NCESRC29_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53143   GPIO_PINCFG29_NCESRC29_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53144   GPIO_PINCFG29_NCESRC29_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53145   GPIO_PINCFG29_NCESRC29_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53146   GPIO_PINCFG29_NCESRC29_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53147   GPIO_PINCFG29_NCESRC29_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53148   GPIO_PINCFG29_NCESRC29_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53149   GPIO_PINCFG29_NCESRC29_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53150   GPIO_PINCFG29_NCESRC29_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53151   GPIO_PINCFG29_NCESRC29_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53152   GPIO_PINCFG29_NCESRC29_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53153   GPIO_PINCFG29_NCESRC29_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53154   GPIO_PINCFG29_NCESRC29_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53155   GPIO_PINCFG29_NCESRC29_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53156   GPIO_PINCFG29_NCESRC29_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53157   GPIO_PINCFG29_NCESRC29_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53158   GPIO_PINCFG29_NCESRC29_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53159   GPIO_PINCFG29_NCESRC29_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53160   GPIO_PINCFG29_NCESRC29_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53161   GPIO_PINCFG29_NCESRC29_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53162   GPIO_PINCFG29_NCESRC29_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53163   GPIO_PINCFG29_NCESRC29_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53164   GPIO_PINCFG29_NCESRC29_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53165 } GPIO_PINCFG29_NCESRC29_Enum;
53166 
53167 /* ===========================================  GPIO PINCFG29 PULLCFG29 [13..15]  ============================================ */
53168 typedef enum {                                  /*!< GPIO_PINCFG29_PULLCFG29                                                   */
53169   GPIO_PINCFG29_PULLCFG29_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53170   GPIO_PINCFG29_PULLCFG29_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53171   GPIO_PINCFG29_PULLCFG29_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53172   GPIO_PINCFG29_PULLCFG29_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53173   GPIO_PINCFG29_PULLCFG29_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53174   GPIO_PINCFG29_PULLCFG29_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53175   GPIO_PINCFG29_PULLCFG29_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53176   GPIO_PINCFG29_PULLCFG29_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53177 } GPIO_PINCFG29_PULLCFG29_Enum;
53178 
53179 /* ==============================================  GPIO PINCFG29 DS29 [10..11]  ============================================== */
53180 typedef enum {                                  /*!< GPIO_PINCFG29_DS29                                                        */
53181   GPIO_PINCFG29_DS29_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53182   GPIO_PINCFG29_DS29_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53183 } GPIO_PINCFG29_DS29_Enum;
53184 
53185 /* =============================================  GPIO PINCFG29 OUTCFG29 [8..9]  ============================================= */
53186 typedef enum {                                  /*!< GPIO_PINCFG29_OUTCFG29                                                    */
53187   GPIO_PINCFG29_OUTCFG29_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53188   GPIO_PINCFG29_OUTCFG29_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53189                                                      and 1 values on pin.                                                      */
53190   GPIO_PINCFG29_OUTCFG29_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53191                                                      low, tristate otherwise.                                                  */
53192   GPIO_PINCFG29_OUTCFG29_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53193                                                      drive 0, 1 of HiZ on pin.                                                 */
53194 } GPIO_PINCFG29_OUTCFG29_Enum;
53195 
53196 /* =============================================  GPIO PINCFG29 IRPTEN29 [6..7]  ============================================= */
53197 typedef enum {                                  /*!< GPIO_PINCFG29_IRPTEN29                                                    */
53198   GPIO_PINCFG29_IRPTEN29_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53199   GPIO_PINCFG29_IRPTEN29_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53200                                                      on this GPIO                                                              */
53201   GPIO_PINCFG29_IRPTEN29_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53202                                                      on this GPIO                                                              */
53203   GPIO_PINCFG29_IRPTEN29_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53204                                                      GPIO                                                                      */
53205 } GPIO_PINCFG29_IRPTEN29_Enum;
53206 
53207 /* =============================================  GPIO PINCFG29 FNCSEL29 [0..3]  ============================================= */
53208 typedef enum {                                  /*!< GPIO_PINCFG29_FNCSEL29                                                    */
53209   GPIO_PINCFG29_FNCSEL29_TRIG0         = 0,     /*!< TRIG0 : ADC trigger input                                                 */
53210   GPIO_PINCFG29_FNCSEL29_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
53211   GPIO_PINCFG29_FNCSEL29_I2S0_DATA     = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
53212                                                      in master mode and input mode for slave mode. (I2S Master/Slave
53213                                                      2)                                                                        */
53214   GPIO_PINCFG29_FNCSEL29_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53215   GPIO_PINCFG29_FNCSEL29_UART1CTS      = 4,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
53216   GPIO_PINCFG29_FNCSEL29_DSP_TRSTN     = 5,     /*!< DSP_TRSTN : JTAG TRSTN input                                              */
53217   GPIO_PINCFG29_FNCSEL29_CT29          = 6,     /*!< CT29 : Timer/Counter input or output; Selection of direction
53218                                                      is done via CTIMER register settings.                                     */
53219   GPIO_PINCFG29_FNCSEL29_NCE29         = 7,     /*!< NCE29 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53220                                                      CE_POLARITY field                                                         */
53221   GPIO_PINCFG29_FNCSEL29_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
53222   GPIO_PINCFG29_FNCSEL29_I2S0_SDOUT    = 9,     /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
53223   GPIO_PINCFG29_FNCSEL29_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53224   GPIO_PINCFG29_FNCSEL29_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53225   GPIO_PINCFG29_FNCSEL29_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53226   GPIO_PINCFG29_FNCSEL29_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53227   GPIO_PINCFG29_FNCSEL29_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53228   GPIO_PINCFG29_FNCSEL29_CMLE          = 15,    /*!< CMLE : Internal function (SCAN)                                           */
53229 } GPIO_PINCFG29_FNCSEL29_Enum;
53230 
53231 /* =======================================================  PINCFG30  ======================================================== */
53232 /* ==========================================  GPIO PINCFG30 VDDPWRSWEN30 [25..25]  ========================================== */
53233 typedef enum {                                  /*!< GPIO_PINCFG30_VDDPWRSWEN30                                                */
53234   GPIO_PINCFG30_VDDPWRSWEN30_DIS       = 0,     /*!< DIS : Power switch is disabled                                            */
53235   GPIO_PINCFG30_VDDPWRSWEN30_EN        = 1,     /*!< EN : Power switch is enabled                                              */
53236 } GPIO_PINCFG30_VDDPWRSWEN30_Enum;
53237 
53238 /* ============================================  GPIO PINCFG30 NCEPOL30 [22..22]  ============================================ */
53239 typedef enum {                                  /*!< GPIO_PINCFG30_NCEPOL30                                                    */
53240   GPIO_PINCFG30_NCEPOL30_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53241   GPIO_PINCFG30_NCEPOL30_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53242 } GPIO_PINCFG30_NCEPOL30_Enum;
53243 
53244 /* ============================================  GPIO PINCFG30 NCESRC30 [16..21]  ============================================ */
53245 typedef enum {                                  /*!< GPIO_PINCFG30_NCESRC30                                                    */
53246   GPIO_PINCFG30_NCESRC30_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53247   GPIO_PINCFG30_NCESRC30_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53248   GPIO_PINCFG30_NCESRC30_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53249   GPIO_PINCFG30_NCESRC30_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53250   GPIO_PINCFG30_NCESRC30_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53251   GPIO_PINCFG30_NCESRC30_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53252   GPIO_PINCFG30_NCESRC30_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53253   GPIO_PINCFG30_NCESRC30_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53254   GPIO_PINCFG30_NCESRC30_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53255   GPIO_PINCFG30_NCESRC30_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53256   GPIO_PINCFG30_NCESRC30_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53257   GPIO_PINCFG30_NCESRC30_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53258   GPIO_PINCFG30_NCESRC30_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53259   GPIO_PINCFG30_NCESRC30_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53260   GPIO_PINCFG30_NCESRC30_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53261   GPIO_PINCFG30_NCESRC30_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53262   GPIO_PINCFG30_NCESRC30_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53263   GPIO_PINCFG30_NCESRC30_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53264   GPIO_PINCFG30_NCESRC30_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53265   GPIO_PINCFG30_NCESRC30_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53266   GPIO_PINCFG30_NCESRC30_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53267   GPIO_PINCFG30_NCESRC30_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53268   GPIO_PINCFG30_NCESRC30_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53269   GPIO_PINCFG30_NCESRC30_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53270   GPIO_PINCFG30_NCESRC30_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53271   GPIO_PINCFG30_NCESRC30_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53272   GPIO_PINCFG30_NCESRC30_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53273   GPIO_PINCFG30_NCESRC30_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53274   GPIO_PINCFG30_NCESRC30_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53275   GPIO_PINCFG30_NCESRC30_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53276   GPIO_PINCFG30_NCESRC30_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53277   GPIO_PINCFG30_NCESRC30_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53278   GPIO_PINCFG30_NCESRC30_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53279   GPIO_PINCFG30_NCESRC30_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53280   GPIO_PINCFG30_NCESRC30_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53281   GPIO_PINCFG30_NCESRC30_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53282   GPIO_PINCFG30_NCESRC30_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53283   GPIO_PINCFG30_NCESRC30_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53284   GPIO_PINCFG30_NCESRC30_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53285   GPIO_PINCFG30_NCESRC30_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53286   GPIO_PINCFG30_NCESRC30_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53287   GPIO_PINCFG30_NCESRC30_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53288   GPIO_PINCFG30_NCESRC30_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53289 } GPIO_PINCFG30_NCESRC30_Enum;
53290 
53291 /* ===========================================  GPIO PINCFG30 PULLCFG30 [13..15]  ============================================ */
53292 typedef enum {                                  /*!< GPIO_PINCFG30_PULLCFG30                                                   */
53293   GPIO_PINCFG30_PULLCFG30_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53294   GPIO_PINCFG30_PULLCFG30_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53295   GPIO_PINCFG30_PULLCFG30_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53296   GPIO_PINCFG30_PULLCFG30_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53297   GPIO_PINCFG30_PULLCFG30_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53298   GPIO_PINCFG30_PULLCFG30_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53299   GPIO_PINCFG30_PULLCFG30_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53300   GPIO_PINCFG30_PULLCFG30_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53301 } GPIO_PINCFG30_PULLCFG30_Enum;
53302 
53303 /* ==============================================  GPIO PINCFG30 DS30 [10..11]  ============================================== */
53304 typedef enum {                                  /*!< GPIO_PINCFG30_DS30                                                        */
53305   GPIO_PINCFG30_DS30_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53306   GPIO_PINCFG30_DS30_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53307 } GPIO_PINCFG30_DS30_Enum;
53308 
53309 /* =============================================  GPIO PINCFG30 OUTCFG30 [8..9]  ============================================= */
53310 typedef enum {                                  /*!< GPIO_PINCFG30_OUTCFG30                                                    */
53311   GPIO_PINCFG30_OUTCFG30_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53312   GPIO_PINCFG30_OUTCFG30_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53313                                                      and 1 values on pin.                                                      */
53314   GPIO_PINCFG30_OUTCFG30_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53315                                                      low, tristate otherwise.                                                  */
53316   GPIO_PINCFG30_OUTCFG30_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53317                                                      drive 0, 1 of HiZ on pin.                                                 */
53318 } GPIO_PINCFG30_OUTCFG30_Enum;
53319 
53320 /* =============================================  GPIO PINCFG30 IRPTEN30 [6..7]  ============================================= */
53321 typedef enum {                                  /*!< GPIO_PINCFG30_IRPTEN30                                                    */
53322   GPIO_PINCFG30_IRPTEN30_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53323   GPIO_PINCFG30_IRPTEN30_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53324                                                      on this GPIO                                                              */
53325   GPIO_PINCFG30_IRPTEN30_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53326                                                      on this GPIO                                                              */
53327   GPIO_PINCFG30_IRPTEN30_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53328                                                      GPIO                                                                      */
53329 } GPIO_PINCFG30_IRPTEN30_Enum;
53330 
53331 /* =============================================  GPIO PINCFG30 FNCSEL30 [0..3]  ============================================= */
53332 typedef enum {                                  /*!< GPIO_PINCFG30_FNCSEL30                                                    */
53333   GPIO_PINCFG30_FNCSEL30_TRIG1         = 0,     /*!< TRIG1 : ADC trigger input                                                 */
53334   GPIO_PINCFG30_FNCSEL30_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
53335   GPIO_PINCFG30_FNCSEL30_I2S0_WS       = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
53336                                                      in master mode and input mode for slave mode. (I2S Master/Slave
53337                                                      2)                                                                        */
53338   GPIO_PINCFG30_FNCSEL30_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53339   GPIO_PINCFG30_FNCSEL30_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
53340   GPIO_PINCFG30_FNCSEL30_DSP_TDI       = 5,     /*!< DSP_TDI : JTAG tdi input                                                  */
53341   GPIO_PINCFG30_FNCSEL30_CT30          = 6,     /*!< CT30 : Timer/Counter input or output; Selection of direction
53342                                                      is done via CTIMER register settings.                                     */
53343   GPIO_PINCFG30_FNCSEL30_NCE30         = 7,     /*!< NCE30 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53344                                                      CE_POLARITY field                                                         */
53345   GPIO_PINCFG30_FNCSEL30_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
53346   GPIO_PINCFG30_FNCSEL30_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53347   GPIO_PINCFG30_FNCSEL30_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53348   GPIO_PINCFG30_FNCSEL30_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53349   GPIO_PINCFG30_FNCSEL30_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53350   GPIO_PINCFG30_FNCSEL30_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53351   GPIO_PINCFG30_FNCSEL30_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53352   GPIO_PINCFG30_FNCSEL30_SCANOUT8      = 15,    /*!< SCANOUT8 : Internal function (SCAN)                                       */
53353 } GPIO_PINCFG30_FNCSEL30_Enum;
53354 
53355 /* =======================================================  PINCFG31  ======================================================== */
53356 /* ============================================  GPIO PINCFG31 NCEPOL31 [22..22]  ============================================ */
53357 typedef enum {                                  /*!< GPIO_PINCFG31_NCEPOL31                                                    */
53358   GPIO_PINCFG31_NCEPOL31_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53359   GPIO_PINCFG31_NCEPOL31_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53360 } GPIO_PINCFG31_NCEPOL31_Enum;
53361 
53362 /* ============================================  GPIO PINCFG31 NCESRC31 [16..21]  ============================================ */
53363 typedef enum {                                  /*!< GPIO_PINCFG31_NCESRC31                                                    */
53364   GPIO_PINCFG31_NCESRC31_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53365   GPIO_PINCFG31_NCESRC31_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53366   GPIO_PINCFG31_NCESRC31_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53367   GPIO_PINCFG31_NCESRC31_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53368   GPIO_PINCFG31_NCESRC31_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53369   GPIO_PINCFG31_NCESRC31_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53370   GPIO_PINCFG31_NCESRC31_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53371   GPIO_PINCFG31_NCESRC31_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53372   GPIO_PINCFG31_NCESRC31_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53373   GPIO_PINCFG31_NCESRC31_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53374   GPIO_PINCFG31_NCESRC31_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53375   GPIO_PINCFG31_NCESRC31_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53376   GPIO_PINCFG31_NCESRC31_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53377   GPIO_PINCFG31_NCESRC31_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53378   GPIO_PINCFG31_NCESRC31_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53379   GPIO_PINCFG31_NCESRC31_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53380   GPIO_PINCFG31_NCESRC31_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53381   GPIO_PINCFG31_NCESRC31_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53382   GPIO_PINCFG31_NCESRC31_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53383   GPIO_PINCFG31_NCESRC31_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53384   GPIO_PINCFG31_NCESRC31_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53385   GPIO_PINCFG31_NCESRC31_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53386   GPIO_PINCFG31_NCESRC31_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53387   GPIO_PINCFG31_NCESRC31_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53388   GPIO_PINCFG31_NCESRC31_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53389   GPIO_PINCFG31_NCESRC31_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53390   GPIO_PINCFG31_NCESRC31_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53391   GPIO_PINCFG31_NCESRC31_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53392   GPIO_PINCFG31_NCESRC31_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53393   GPIO_PINCFG31_NCESRC31_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53394   GPIO_PINCFG31_NCESRC31_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53395   GPIO_PINCFG31_NCESRC31_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53396   GPIO_PINCFG31_NCESRC31_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53397   GPIO_PINCFG31_NCESRC31_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53398   GPIO_PINCFG31_NCESRC31_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53399   GPIO_PINCFG31_NCESRC31_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53400   GPIO_PINCFG31_NCESRC31_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53401   GPIO_PINCFG31_NCESRC31_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53402   GPIO_PINCFG31_NCESRC31_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53403   GPIO_PINCFG31_NCESRC31_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53404   GPIO_PINCFG31_NCESRC31_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53405   GPIO_PINCFG31_NCESRC31_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53406   GPIO_PINCFG31_NCESRC31_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53407 } GPIO_PINCFG31_NCESRC31_Enum;
53408 
53409 /* ===========================================  GPIO PINCFG31 PULLCFG31 [13..15]  ============================================ */
53410 typedef enum {                                  /*!< GPIO_PINCFG31_PULLCFG31                                                   */
53411   GPIO_PINCFG31_PULLCFG31_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53412   GPIO_PINCFG31_PULLCFG31_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53413   GPIO_PINCFG31_PULLCFG31_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53414   GPIO_PINCFG31_PULLCFG31_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53415   GPIO_PINCFG31_PULLCFG31_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53416   GPIO_PINCFG31_PULLCFG31_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53417   GPIO_PINCFG31_PULLCFG31_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53418   GPIO_PINCFG31_PULLCFG31_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53419 } GPIO_PINCFG31_PULLCFG31_Enum;
53420 
53421 /* ==============================================  GPIO PINCFG31 DS31 [10..11]  ============================================== */
53422 typedef enum {                                  /*!< GPIO_PINCFG31_DS31                                                        */
53423   GPIO_PINCFG31_DS31_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53424   GPIO_PINCFG31_DS31_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53425   GPIO_PINCFG31_DS31_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53426   GPIO_PINCFG31_DS31_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53427 } GPIO_PINCFG31_DS31_Enum;
53428 
53429 /* =============================================  GPIO PINCFG31 OUTCFG31 [8..9]  ============================================= */
53430 typedef enum {                                  /*!< GPIO_PINCFG31_OUTCFG31                                                    */
53431   GPIO_PINCFG31_OUTCFG31_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53432   GPIO_PINCFG31_OUTCFG31_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53433                                                      and 1 values on pin.                                                      */
53434   GPIO_PINCFG31_OUTCFG31_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53435                                                      low, tristate otherwise.                                                  */
53436   GPIO_PINCFG31_OUTCFG31_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53437                                                      drive 0, 1 of HiZ on pin.                                                 */
53438 } GPIO_PINCFG31_OUTCFG31_Enum;
53439 
53440 /* =============================================  GPIO PINCFG31 IRPTEN31 [6..7]  ============================================= */
53441 typedef enum {                                  /*!< GPIO_PINCFG31_IRPTEN31                                                    */
53442   GPIO_PINCFG31_IRPTEN31_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53443   GPIO_PINCFG31_IRPTEN31_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53444                                                      on this GPIO                                                              */
53445   GPIO_PINCFG31_IRPTEN31_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53446                                                      on this GPIO                                                              */
53447   GPIO_PINCFG31_IRPTEN31_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53448                                                      GPIO                                                                      */
53449 } GPIO_PINCFG31_IRPTEN31_Enum;
53450 
53451 /* =============================================  GPIO PINCFG31 FNCSEL31 [0..3]  ============================================= */
53452 typedef enum {                                  /*!< GPIO_PINCFG31_FNCSEL31                                                    */
53453   GPIO_PINCFG31_FNCSEL31_M3SCL         = 0,     /*!< M3SCL : Serial I2C Master Clock output (IOM 3)                            */
53454   GPIO_PINCFG31_FNCSEL31_M3SCK         = 1,     /*!< M3SCK : Serial SPI Master Clock output (IOM 3)                            */
53455   GPIO_PINCFG31_FNCSEL31_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53456   GPIO_PINCFG31_FNCSEL31_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53457   GPIO_PINCFG31_FNCSEL31_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
53458   GPIO_PINCFG31_FNCSEL31_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
53459   GPIO_PINCFG31_FNCSEL31_CT31          = 6,     /*!< CT31 : Timer/Counter input or output; Selection of direction
53460                                                      is done via CTIMER register settings.                                     */
53461   GPIO_PINCFG31_FNCSEL31_NCE31         = 7,     /*!< NCE31 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53462                                                      CE_POLARITY field                                                         */
53463   GPIO_PINCFG31_FNCSEL31_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
53464   GPIO_PINCFG31_FNCSEL31_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
53465   GPIO_PINCFG31_FNCSEL31_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53466   GPIO_PINCFG31_FNCSEL31_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53467   GPIO_PINCFG31_FNCSEL31_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53468   GPIO_PINCFG31_FNCSEL31_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53469   GPIO_PINCFG31_FNCSEL31_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53470   GPIO_PINCFG31_FNCSEL31_SCANOUT9      = 15,    /*!< SCANOUT9 : Internal function (SCAN)                                       */
53471 } GPIO_PINCFG31_FNCSEL31_Enum;
53472 
53473 /* =======================================================  PINCFG32  ======================================================== */
53474 /* ============================================  GPIO PINCFG32 NCEPOL32 [22..22]  ============================================ */
53475 typedef enum {                                  /*!< GPIO_PINCFG32_NCEPOL32                                                    */
53476   GPIO_PINCFG32_NCEPOL32_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53477   GPIO_PINCFG32_NCEPOL32_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53478 } GPIO_PINCFG32_NCEPOL32_Enum;
53479 
53480 /* ============================================  GPIO PINCFG32 NCESRC32 [16..21]  ============================================ */
53481 typedef enum {                                  /*!< GPIO_PINCFG32_NCESRC32                                                    */
53482   GPIO_PINCFG32_NCESRC32_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53483   GPIO_PINCFG32_NCESRC32_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53484   GPIO_PINCFG32_NCESRC32_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53485   GPIO_PINCFG32_NCESRC32_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53486   GPIO_PINCFG32_NCESRC32_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53487   GPIO_PINCFG32_NCESRC32_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53488   GPIO_PINCFG32_NCESRC32_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53489   GPIO_PINCFG32_NCESRC32_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53490   GPIO_PINCFG32_NCESRC32_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53491   GPIO_PINCFG32_NCESRC32_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53492   GPIO_PINCFG32_NCESRC32_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53493   GPIO_PINCFG32_NCESRC32_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53494   GPIO_PINCFG32_NCESRC32_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53495   GPIO_PINCFG32_NCESRC32_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53496   GPIO_PINCFG32_NCESRC32_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53497   GPIO_PINCFG32_NCESRC32_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53498   GPIO_PINCFG32_NCESRC32_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53499   GPIO_PINCFG32_NCESRC32_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53500   GPIO_PINCFG32_NCESRC32_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53501   GPIO_PINCFG32_NCESRC32_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53502   GPIO_PINCFG32_NCESRC32_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53503   GPIO_PINCFG32_NCESRC32_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53504   GPIO_PINCFG32_NCESRC32_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53505   GPIO_PINCFG32_NCESRC32_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53506   GPIO_PINCFG32_NCESRC32_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53507   GPIO_PINCFG32_NCESRC32_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53508   GPIO_PINCFG32_NCESRC32_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53509   GPIO_PINCFG32_NCESRC32_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53510   GPIO_PINCFG32_NCESRC32_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53511   GPIO_PINCFG32_NCESRC32_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53512   GPIO_PINCFG32_NCESRC32_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53513   GPIO_PINCFG32_NCESRC32_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53514   GPIO_PINCFG32_NCESRC32_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53515   GPIO_PINCFG32_NCESRC32_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53516   GPIO_PINCFG32_NCESRC32_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53517   GPIO_PINCFG32_NCESRC32_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53518   GPIO_PINCFG32_NCESRC32_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53519   GPIO_PINCFG32_NCESRC32_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53520   GPIO_PINCFG32_NCESRC32_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53521   GPIO_PINCFG32_NCESRC32_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53522   GPIO_PINCFG32_NCESRC32_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53523   GPIO_PINCFG32_NCESRC32_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53524   GPIO_PINCFG32_NCESRC32_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53525 } GPIO_PINCFG32_NCESRC32_Enum;
53526 
53527 /* ===========================================  GPIO PINCFG32 PULLCFG32 [13..15]  ============================================ */
53528 typedef enum {                                  /*!< GPIO_PINCFG32_PULLCFG32                                                   */
53529   GPIO_PINCFG32_PULLCFG32_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53530   GPIO_PINCFG32_PULLCFG32_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53531   GPIO_PINCFG32_PULLCFG32_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53532   GPIO_PINCFG32_PULLCFG32_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53533   GPIO_PINCFG32_PULLCFG32_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53534   GPIO_PINCFG32_PULLCFG32_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53535   GPIO_PINCFG32_PULLCFG32_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53536   GPIO_PINCFG32_PULLCFG32_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53537 } GPIO_PINCFG32_PULLCFG32_Enum;
53538 
53539 /* ==============================================  GPIO PINCFG32 DS32 [10..11]  ============================================== */
53540 typedef enum {                                  /*!< GPIO_PINCFG32_DS32                                                        */
53541   GPIO_PINCFG32_DS32_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53542   GPIO_PINCFG32_DS32_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53543   GPIO_PINCFG32_DS32_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53544   GPIO_PINCFG32_DS32_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53545 } GPIO_PINCFG32_DS32_Enum;
53546 
53547 /* =============================================  GPIO PINCFG32 OUTCFG32 [8..9]  ============================================= */
53548 typedef enum {                                  /*!< GPIO_PINCFG32_OUTCFG32                                                    */
53549   GPIO_PINCFG32_OUTCFG32_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53550   GPIO_PINCFG32_OUTCFG32_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53551                                                      and 1 values on pin.                                                      */
53552   GPIO_PINCFG32_OUTCFG32_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53553                                                      low, tristate otherwise.                                                  */
53554   GPIO_PINCFG32_OUTCFG32_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53555                                                      drive 0, 1 of HiZ on pin.                                                 */
53556 } GPIO_PINCFG32_OUTCFG32_Enum;
53557 
53558 /* =============================================  GPIO PINCFG32 IRPTEN32 [6..7]  ============================================= */
53559 typedef enum {                                  /*!< GPIO_PINCFG32_IRPTEN32                                                    */
53560   GPIO_PINCFG32_IRPTEN32_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53561   GPIO_PINCFG32_IRPTEN32_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53562                                                      on this GPIO                                                              */
53563   GPIO_PINCFG32_IRPTEN32_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53564                                                      on this GPIO                                                              */
53565   GPIO_PINCFG32_IRPTEN32_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53566                                                      GPIO                                                                      */
53567 } GPIO_PINCFG32_IRPTEN32_Enum;
53568 
53569 /* =============================================  GPIO PINCFG32 FNCSEL32 [0..3]  ============================================= */
53570 typedef enum {                                  /*!< GPIO_PINCFG32_FNCSEL32                                                    */
53571   GPIO_PINCFG32_FNCSEL32_M3SDAWIR3     = 0,     /*!< M3SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
53572                                                      Master Data I/O (SPI 3 wire mode) (IOM 3)                                 */
53573   GPIO_PINCFG32_FNCSEL32_M3MOSI        = 1,     /*!< M3MOSI : Serial SPI Master MOSI output (IOM 3)                            */
53574   GPIO_PINCFG32_FNCSEL32_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53575   GPIO_PINCFG32_FNCSEL32_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53576   GPIO_PINCFG32_FNCSEL32_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
53577   GPIO_PINCFG32_FNCSEL32_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
53578   GPIO_PINCFG32_FNCSEL32_CT32          = 6,     /*!< CT32 : Timer/Counter input or output; Selection of direction
53579                                                      is done via CTIMER register settings.                                     */
53580   GPIO_PINCFG32_FNCSEL32_NCE32         = 7,     /*!< NCE32 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53581                                                      CE_POLARITY field                                                         */
53582   GPIO_PINCFG32_FNCSEL32_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
53583   GPIO_PINCFG32_FNCSEL32_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53584   GPIO_PINCFG32_FNCSEL32_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53585   GPIO_PINCFG32_FNCSEL32_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53586   GPIO_PINCFG32_FNCSEL32_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53587   GPIO_PINCFG32_FNCSEL32_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53588   GPIO_PINCFG32_FNCSEL32_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53589   GPIO_PINCFG32_FNCSEL32_SCANOUT10     = 15,    /*!< SCANOUT10 : Internal function (SCAN)                                      */
53590 } GPIO_PINCFG32_FNCSEL32_Enum;
53591 
53592 /* =======================================================  PINCFG33  ======================================================== */
53593 /* ============================================  GPIO PINCFG33 NCEPOL33 [22..22]  ============================================ */
53594 typedef enum {                                  /*!< GPIO_PINCFG33_NCEPOL33                                                    */
53595   GPIO_PINCFG33_NCEPOL33_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53596   GPIO_PINCFG33_NCEPOL33_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53597 } GPIO_PINCFG33_NCEPOL33_Enum;
53598 
53599 /* ============================================  GPIO PINCFG33 NCESRC33 [16..21]  ============================================ */
53600 typedef enum {                                  /*!< GPIO_PINCFG33_NCESRC33                                                    */
53601   GPIO_PINCFG33_NCESRC33_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53602   GPIO_PINCFG33_NCESRC33_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53603   GPIO_PINCFG33_NCESRC33_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53604   GPIO_PINCFG33_NCESRC33_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53605   GPIO_PINCFG33_NCESRC33_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53606   GPIO_PINCFG33_NCESRC33_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53607   GPIO_PINCFG33_NCESRC33_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53608   GPIO_PINCFG33_NCESRC33_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53609   GPIO_PINCFG33_NCESRC33_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53610   GPIO_PINCFG33_NCESRC33_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53611   GPIO_PINCFG33_NCESRC33_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53612   GPIO_PINCFG33_NCESRC33_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53613   GPIO_PINCFG33_NCESRC33_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53614   GPIO_PINCFG33_NCESRC33_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53615   GPIO_PINCFG33_NCESRC33_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53616   GPIO_PINCFG33_NCESRC33_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53617   GPIO_PINCFG33_NCESRC33_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53618   GPIO_PINCFG33_NCESRC33_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53619   GPIO_PINCFG33_NCESRC33_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53620   GPIO_PINCFG33_NCESRC33_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53621   GPIO_PINCFG33_NCESRC33_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53622   GPIO_PINCFG33_NCESRC33_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53623   GPIO_PINCFG33_NCESRC33_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53624   GPIO_PINCFG33_NCESRC33_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53625   GPIO_PINCFG33_NCESRC33_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53626   GPIO_PINCFG33_NCESRC33_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53627   GPIO_PINCFG33_NCESRC33_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53628   GPIO_PINCFG33_NCESRC33_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53629   GPIO_PINCFG33_NCESRC33_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53630   GPIO_PINCFG33_NCESRC33_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53631   GPIO_PINCFG33_NCESRC33_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53632   GPIO_PINCFG33_NCESRC33_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53633   GPIO_PINCFG33_NCESRC33_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53634   GPIO_PINCFG33_NCESRC33_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53635   GPIO_PINCFG33_NCESRC33_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53636   GPIO_PINCFG33_NCESRC33_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53637   GPIO_PINCFG33_NCESRC33_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53638   GPIO_PINCFG33_NCESRC33_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53639   GPIO_PINCFG33_NCESRC33_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53640   GPIO_PINCFG33_NCESRC33_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53641   GPIO_PINCFG33_NCESRC33_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53642   GPIO_PINCFG33_NCESRC33_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53643   GPIO_PINCFG33_NCESRC33_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53644 } GPIO_PINCFG33_NCESRC33_Enum;
53645 
53646 /* ===========================================  GPIO PINCFG33 PULLCFG33 [13..15]  ============================================ */
53647 typedef enum {                                  /*!< GPIO_PINCFG33_PULLCFG33                                                   */
53648   GPIO_PINCFG33_PULLCFG33_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53649   GPIO_PINCFG33_PULLCFG33_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53650   GPIO_PINCFG33_PULLCFG33_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53651   GPIO_PINCFG33_PULLCFG33_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53652   GPIO_PINCFG33_PULLCFG33_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53653   GPIO_PINCFG33_PULLCFG33_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53654   GPIO_PINCFG33_PULLCFG33_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53655   GPIO_PINCFG33_PULLCFG33_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53656 } GPIO_PINCFG33_PULLCFG33_Enum;
53657 
53658 /* ==============================================  GPIO PINCFG33 DS33 [10..11]  ============================================== */
53659 typedef enum {                                  /*!< GPIO_PINCFG33_DS33                                                        */
53660   GPIO_PINCFG33_DS33_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53661   GPIO_PINCFG33_DS33_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53662   GPIO_PINCFG33_DS33_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53663   GPIO_PINCFG33_DS33_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53664 } GPIO_PINCFG33_DS33_Enum;
53665 
53666 /* =============================================  GPIO PINCFG33 OUTCFG33 [8..9]  ============================================= */
53667 typedef enum {                                  /*!< GPIO_PINCFG33_OUTCFG33                                                    */
53668   GPIO_PINCFG33_OUTCFG33_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53669   GPIO_PINCFG33_OUTCFG33_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53670                                                      and 1 values on pin.                                                      */
53671   GPIO_PINCFG33_OUTCFG33_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53672                                                      low, tristate otherwise.                                                  */
53673   GPIO_PINCFG33_OUTCFG33_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53674                                                      drive 0, 1 of HiZ on pin.                                                 */
53675 } GPIO_PINCFG33_OUTCFG33_Enum;
53676 
53677 /* =============================================  GPIO PINCFG33 IRPTEN33 [6..7]  ============================================= */
53678 typedef enum {                                  /*!< GPIO_PINCFG33_IRPTEN33                                                    */
53679   GPIO_PINCFG33_IRPTEN33_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53680   GPIO_PINCFG33_IRPTEN33_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53681                                                      on this GPIO                                                              */
53682   GPIO_PINCFG33_IRPTEN33_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53683                                                      on this GPIO                                                              */
53684   GPIO_PINCFG33_IRPTEN33_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53685                                                      GPIO                                                                      */
53686 } GPIO_PINCFG33_IRPTEN33_Enum;
53687 
53688 /* =============================================  GPIO PINCFG33 FNCSEL33 [0..3]  ============================================= */
53689 typedef enum {                                  /*!< GPIO_PINCFG33_FNCSEL33                                                    */
53690   GPIO_PINCFG33_FNCSEL33_M3MISO        = 0,     /*!< M3MISO : Serial SPI MASTER MISO input (IOM 3)                             */
53691   GPIO_PINCFG33_FNCSEL33_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
53692   GPIO_PINCFG33_FNCSEL33_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53693   GPIO_PINCFG33_FNCSEL33_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53694   GPIO_PINCFG33_FNCSEL33_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
53695   GPIO_PINCFG33_FNCSEL33_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
53696   GPIO_PINCFG33_FNCSEL33_CT33          = 6,     /*!< CT33 : Timer/Counter input or output; Selection of direction
53697                                                      is done via CTIMER register settings.                                     */
53698   GPIO_PINCFG33_FNCSEL33_NCE33         = 7,     /*!< NCE33 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53699                                                      CE_POLARITY field                                                         */
53700   GPIO_PINCFG33_FNCSEL33_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
53701   GPIO_PINCFG33_FNCSEL33_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
53702   GPIO_PINCFG33_FNCSEL33_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53703   GPIO_PINCFG33_FNCSEL33_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53704   GPIO_PINCFG33_FNCSEL33_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53705   GPIO_PINCFG33_FNCSEL33_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53706   GPIO_PINCFG33_FNCSEL33_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53707   GPIO_PINCFG33_FNCSEL33_SCANOUT11     = 15,    /*!< SCANOUT11 : Internal function (SCAN)                                      */
53708 } GPIO_PINCFG33_FNCSEL33_Enum;
53709 
53710 /* =======================================================  PINCFG34  ======================================================== */
53711 /* ============================================  GPIO PINCFG34 NCEPOL34 [22..22]  ============================================ */
53712 typedef enum {                                  /*!< GPIO_PINCFG34_NCEPOL34                                                    */
53713   GPIO_PINCFG34_NCEPOL34_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53714   GPIO_PINCFG34_NCEPOL34_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53715 } GPIO_PINCFG34_NCEPOL34_Enum;
53716 
53717 /* ============================================  GPIO PINCFG34 NCESRC34 [16..21]  ============================================ */
53718 typedef enum {                                  /*!< GPIO_PINCFG34_NCESRC34                                                    */
53719   GPIO_PINCFG34_NCESRC34_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53720   GPIO_PINCFG34_NCESRC34_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53721   GPIO_PINCFG34_NCESRC34_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53722   GPIO_PINCFG34_NCESRC34_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53723   GPIO_PINCFG34_NCESRC34_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53724   GPIO_PINCFG34_NCESRC34_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53725   GPIO_PINCFG34_NCESRC34_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53726   GPIO_PINCFG34_NCESRC34_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53727   GPIO_PINCFG34_NCESRC34_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53728   GPIO_PINCFG34_NCESRC34_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53729   GPIO_PINCFG34_NCESRC34_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53730   GPIO_PINCFG34_NCESRC34_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53731   GPIO_PINCFG34_NCESRC34_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53732   GPIO_PINCFG34_NCESRC34_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53733   GPIO_PINCFG34_NCESRC34_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53734   GPIO_PINCFG34_NCESRC34_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53735   GPIO_PINCFG34_NCESRC34_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53736   GPIO_PINCFG34_NCESRC34_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53737   GPIO_PINCFG34_NCESRC34_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53738   GPIO_PINCFG34_NCESRC34_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53739   GPIO_PINCFG34_NCESRC34_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53740   GPIO_PINCFG34_NCESRC34_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53741   GPIO_PINCFG34_NCESRC34_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53742   GPIO_PINCFG34_NCESRC34_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53743   GPIO_PINCFG34_NCESRC34_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53744   GPIO_PINCFG34_NCESRC34_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53745   GPIO_PINCFG34_NCESRC34_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53746   GPIO_PINCFG34_NCESRC34_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53747   GPIO_PINCFG34_NCESRC34_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53748   GPIO_PINCFG34_NCESRC34_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53749   GPIO_PINCFG34_NCESRC34_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53750   GPIO_PINCFG34_NCESRC34_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53751   GPIO_PINCFG34_NCESRC34_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53752   GPIO_PINCFG34_NCESRC34_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53753   GPIO_PINCFG34_NCESRC34_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53754   GPIO_PINCFG34_NCESRC34_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53755   GPIO_PINCFG34_NCESRC34_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53756   GPIO_PINCFG34_NCESRC34_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53757   GPIO_PINCFG34_NCESRC34_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53758   GPIO_PINCFG34_NCESRC34_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53759   GPIO_PINCFG34_NCESRC34_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53760   GPIO_PINCFG34_NCESRC34_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53761   GPIO_PINCFG34_NCESRC34_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53762 } GPIO_PINCFG34_NCESRC34_Enum;
53763 
53764 /* ===========================================  GPIO PINCFG34 PULLCFG34 [13..15]  ============================================ */
53765 typedef enum {                                  /*!< GPIO_PINCFG34_PULLCFG34                                                   */
53766   GPIO_PINCFG34_PULLCFG34_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53767   GPIO_PINCFG34_PULLCFG34_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53768   GPIO_PINCFG34_PULLCFG34_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53769   GPIO_PINCFG34_PULLCFG34_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53770   GPIO_PINCFG34_PULLCFG34_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53771   GPIO_PINCFG34_PULLCFG34_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53772   GPIO_PINCFG34_PULLCFG34_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53773   GPIO_PINCFG34_PULLCFG34_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53774 } GPIO_PINCFG34_PULLCFG34_Enum;
53775 
53776 /* ==============================================  GPIO PINCFG34 DS34 [10..11]  ============================================== */
53777 typedef enum {                                  /*!< GPIO_PINCFG34_DS34                                                        */
53778   GPIO_PINCFG34_DS34_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53779   GPIO_PINCFG34_DS34_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53780   GPIO_PINCFG34_DS34_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53781   GPIO_PINCFG34_DS34_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53782 } GPIO_PINCFG34_DS34_Enum;
53783 
53784 /* =============================================  GPIO PINCFG34 OUTCFG34 [8..9]  ============================================= */
53785 typedef enum {                                  /*!< GPIO_PINCFG34_OUTCFG34                                                    */
53786   GPIO_PINCFG34_OUTCFG34_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53787   GPIO_PINCFG34_OUTCFG34_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53788                                                      and 1 values on pin.                                                      */
53789   GPIO_PINCFG34_OUTCFG34_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53790                                                      low, tristate otherwise.                                                  */
53791   GPIO_PINCFG34_OUTCFG34_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53792                                                      drive 0, 1 of HiZ on pin.                                                 */
53793 } GPIO_PINCFG34_OUTCFG34_Enum;
53794 
53795 /* =============================================  GPIO PINCFG34 IRPTEN34 [6..7]  ============================================= */
53796 typedef enum {                                  /*!< GPIO_PINCFG34_IRPTEN34                                                    */
53797   GPIO_PINCFG34_IRPTEN34_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53798   GPIO_PINCFG34_IRPTEN34_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53799                                                      on this GPIO                                                              */
53800   GPIO_PINCFG34_IRPTEN34_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53801                                                      on this GPIO                                                              */
53802   GPIO_PINCFG34_IRPTEN34_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53803                                                      GPIO                                                                      */
53804 } GPIO_PINCFG34_IRPTEN34_Enum;
53805 
53806 /* =============================================  GPIO PINCFG34 FNCSEL34 [0..3]  ============================================= */
53807 typedef enum {                                  /*!< GPIO_PINCFG34_FNCSEL34                                                    */
53808   GPIO_PINCFG34_FNCSEL34_M4SCL         = 0,     /*!< M4SCL : Serial I2C Master Clock output (IOM 4)                            */
53809   GPIO_PINCFG34_FNCSEL34_M4SCK         = 1,     /*!< M4SCK : Serial SPI Master Clock output (IOM 4)                            */
53810   GPIO_PINCFG34_FNCSEL34_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
53811   GPIO_PINCFG34_FNCSEL34_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53812   GPIO_PINCFG34_FNCSEL34_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
53813   GPIO_PINCFG34_FNCSEL34_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
53814   GPIO_PINCFG34_FNCSEL34_CT34          = 6,     /*!< CT34 : Timer/Counter input or output; Selection of direction
53815                                                      is done via CTIMER register settings.                                     */
53816   GPIO_PINCFG34_FNCSEL34_NCE34         = 7,     /*!< NCE34 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53817                                                      CE_POLARITY field                                                         */
53818   GPIO_PINCFG34_FNCSEL34_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
53819   GPIO_PINCFG34_FNCSEL34_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
53820   GPIO_PINCFG34_FNCSEL34_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53821   GPIO_PINCFG34_FNCSEL34_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53822   GPIO_PINCFG34_FNCSEL34_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53823   GPIO_PINCFG34_FNCSEL34_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53824   GPIO_PINCFG34_FNCSEL34_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53825   GPIO_PINCFG34_FNCSEL34_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
53826 } GPIO_PINCFG34_FNCSEL34_Enum;
53827 
53828 /* =======================================================  PINCFG35  ======================================================== */
53829 /* ============================================  GPIO PINCFG35 NCEPOL35 [22..22]  ============================================ */
53830 typedef enum {                                  /*!< GPIO_PINCFG35_NCEPOL35                                                    */
53831   GPIO_PINCFG35_NCEPOL35_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53832   GPIO_PINCFG35_NCEPOL35_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53833 } GPIO_PINCFG35_NCEPOL35_Enum;
53834 
53835 /* ============================================  GPIO PINCFG35 NCESRC35 [16..21]  ============================================ */
53836 typedef enum {                                  /*!< GPIO_PINCFG35_NCESRC35                                                    */
53837   GPIO_PINCFG35_NCESRC35_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53838   GPIO_PINCFG35_NCESRC35_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53839   GPIO_PINCFG35_NCESRC35_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53840   GPIO_PINCFG35_NCESRC35_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53841   GPIO_PINCFG35_NCESRC35_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53842   GPIO_PINCFG35_NCESRC35_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53843   GPIO_PINCFG35_NCESRC35_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53844   GPIO_PINCFG35_NCESRC35_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53845   GPIO_PINCFG35_NCESRC35_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53846   GPIO_PINCFG35_NCESRC35_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53847   GPIO_PINCFG35_NCESRC35_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53848   GPIO_PINCFG35_NCESRC35_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53849   GPIO_PINCFG35_NCESRC35_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53850   GPIO_PINCFG35_NCESRC35_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53851   GPIO_PINCFG35_NCESRC35_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53852   GPIO_PINCFG35_NCESRC35_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53853   GPIO_PINCFG35_NCESRC35_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53854   GPIO_PINCFG35_NCESRC35_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53855   GPIO_PINCFG35_NCESRC35_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53856   GPIO_PINCFG35_NCESRC35_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53857   GPIO_PINCFG35_NCESRC35_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53858   GPIO_PINCFG35_NCESRC35_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53859   GPIO_PINCFG35_NCESRC35_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53860   GPIO_PINCFG35_NCESRC35_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53861   GPIO_PINCFG35_NCESRC35_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53862   GPIO_PINCFG35_NCESRC35_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53863   GPIO_PINCFG35_NCESRC35_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53864   GPIO_PINCFG35_NCESRC35_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53865   GPIO_PINCFG35_NCESRC35_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53866   GPIO_PINCFG35_NCESRC35_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53867   GPIO_PINCFG35_NCESRC35_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53868   GPIO_PINCFG35_NCESRC35_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53869   GPIO_PINCFG35_NCESRC35_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53870   GPIO_PINCFG35_NCESRC35_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53871   GPIO_PINCFG35_NCESRC35_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53872   GPIO_PINCFG35_NCESRC35_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53873   GPIO_PINCFG35_NCESRC35_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53874   GPIO_PINCFG35_NCESRC35_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53875   GPIO_PINCFG35_NCESRC35_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53876   GPIO_PINCFG35_NCESRC35_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53877   GPIO_PINCFG35_NCESRC35_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53878   GPIO_PINCFG35_NCESRC35_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53879   GPIO_PINCFG35_NCESRC35_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53880 } GPIO_PINCFG35_NCESRC35_Enum;
53881 
53882 /* ===========================================  GPIO PINCFG35 PULLCFG35 [13..15]  ============================================ */
53883 typedef enum {                                  /*!< GPIO_PINCFG35_PULLCFG35                                                   */
53884   GPIO_PINCFG35_PULLCFG35_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53885   GPIO_PINCFG35_PULLCFG35_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53886   GPIO_PINCFG35_PULLCFG35_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53887   GPIO_PINCFG35_PULLCFG35_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53888   GPIO_PINCFG35_PULLCFG35_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53889   GPIO_PINCFG35_PULLCFG35_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53890   GPIO_PINCFG35_PULLCFG35_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53891   GPIO_PINCFG35_PULLCFG35_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53892 } GPIO_PINCFG35_PULLCFG35_Enum;
53893 
53894 /* ==============================================  GPIO PINCFG35 DS35 [10..11]  ============================================== */
53895 typedef enum {                                  /*!< GPIO_PINCFG35_DS35                                                        */
53896   GPIO_PINCFG35_DS35_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53897   GPIO_PINCFG35_DS35_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53898   GPIO_PINCFG35_DS35_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53899   GPIO_PINCFG35_DS35_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53900 } GPIO_PINCFG35_DS35_Enum;
53901 
53902 /* =============================================  GPIO PINCFG35 OUTCFG35 [8..9]  ============================================= */
53903 typedef enum {                                  /*!< GPIO_PINCFG35_OUTCFG35                                                    */
53904   GPIO_PINCFG35_OUTCFG35_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53905   GPIO_PINCFG35_OUTCFG35_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53906                                                      and 1 values on pin.                                                      */
53907   GPIO_PINCFG35_OUTCFG35_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53908                                                      low, tristate otherwise.                                                  */
53909   GPIO_PINCFG35_OUTCFG35_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53910                                                      drive 0, 1 of HiZ on pin.                                                 */
53911 } GPIO_PINCFG35_OUTCFG35_Enum;
53912 
53913 /* =============================================  GPIO PINCFG35 IRPTEN35 [6..7]  ============================================= */
53914 typedef enum {                                  /*!< GPIO_PINCFG35_IRPTEN35                                                    */
53915   GPIO_PINCFG35_IRPTEN35_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53916   GPIO_PINCFG35_IRPTEN35_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53917                                                      on this GPIO                                                              */
53918   GPIO_PINCFG35_IRPTEN35_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53919                                                      on this GPIO                                                              */
53920   GPIO_PINCFG35_IRPTEN35_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53921                                                      GPIO                                                                      */
53922 } GPIO_PINCFG35_IRPTEN35_Enum;
53923 
53924 /* =============================================  GPIO PINCFG35 FNCSEL35 [0..3]  ============================================= */
53925 typedef enum {                                  /*!< GPIO_PINCFG35_FNCSEL35                                                    */
53926   GPIO_PINCFG35_FNCSEL35_M4SDAWIR3     = 0,     /*!< M4SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
53927                                                      Master Data I/O (SPI 3 wire mode) (IOM 4)                                 */
53928   GPIO_PINCFG35_FNCSEL35_M4MOSI        = 1,     /*!< M4MOSI : Serial SPI Master MOSI output (IOM 4)                            */
53929   GPIO_PINCFG35_FNCSEL35_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
53930   GPIO_PINCFG35_FNCSEL35_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53931   GPIO_PINCFG35_FNCSEL35_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
53932   GPIO_PINCFG35_FNCSEL35_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
53933   GPIO_PINCFG35_FNCSEL35_CT35          = 6,     /*!< CT35 : Timer/Counter input or output; Selection of direction
53934                                                      is done via CTIMER register settings.                                     */
53935   GPIO_PINCFG35_FNCSEL35_NCE35         = 7,     /*!< NCE35 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53936                                                      CE_POLARITY field                                                         */
53937   GPIO_PINCFG35_FNCSEL35_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
53938   GPIO_PINCFG35_FNCSEL35_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
53939   GPIO_PINCFG35_FNCSEL35_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53940   GPIO_PINCFG35_FNCSEL35_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53941   GPIO_PINCFG35_FNCSEL35_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53942   GPIO_PINCFG35_FNCSEL35_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53943   GPIO_PINCFG35_FNCSEL35_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53944   GPIO_PINCFG35_FNCSEL35_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
53945 } GPIO_PINCFG35_FNCSEL35_Enum;
53946 
53947 /* =======================================================  PINCFG36  ======================================================== */
53948 /* ============================================  GPIO PINCFG36 NCEPOL36 [22..22]  ============================================ */
53949 typedef enum {                                  /*!< GPIO_PINCFG36_NCEPOL36                                                    */
53950   GPIO_PINCFG36_NCEPOL36_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53951   GPIO_PINCFG36_NCEPOL36_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53952 } GPIO_PINCFG36_NCEPOL36_Enum;
53953 
53954 /* ============================================  GPIO PINCFG36 NCESRC36 [16..21]  ============================================ */
53955 typedef enum {                                  /*!< GPIO_PINCFG36_NCESRC36                                                    */
53956   GPIO_PINCFG36_NCESRC36_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53957   GPIO_PINCFG36_NCESRC36_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53958   GPIO_PINCFG36_NCESRC36_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53959   GPIO_PINCFG36_NCESRC36_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53960   GPIO_PINCFG36_NCESRC36_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53961   GPIO_PINCFG36_NCESRC36_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53962   GPIO_PINCFG36_NCESRC36_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53963   GPIO_PINCFG36_NCESRC36_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53964   GPIO_PINCFG36_NCESRC36_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53965   GPIO_PINCFG36_NCESRC36_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53966   GPIO_PINCFG36_NCESRC36_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53967   GPIO_PINCFG36_NCESRC36_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53968   GPIO_PINCFG36_NCESRC36_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53969   GPIO_PINCFG36_NCESRC36_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53970   GPIO_PINCFG36_NCESRC36_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53971   GPIO_PINCFG36_NCESRC36_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53972   GPIO_PINCFG36_NCESRC36_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53973   GPIO_PINCFG36_NCESRC36_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53974   GPIO_PINCFG36_NCESRC36_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53975   GPIO_PINCFG36_NCESRC36_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53976   GPIO_PINCFG36_NCESRC36_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53977   GPIO_PINCFG36_NCESRC36_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53978   GPIO_PINCFG36_NCESRC36_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53979   GPIO_PINCFG36_NCESRC36_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53980   GPIO_PINCFG36_NCESRC36_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53981   GPIO_PINCFG36_NCESRC36_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53982   GPIO_PINCFG36_NCESRC36_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53983   GPIO_PINCFG36_NCESRC36_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53984   GPIO_PINCFG36_NCESRC36_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53985   GPIO_PINCFG36_NCESRC36_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53986   GPIO_PINCFG36_NCESRC36_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53987   GPIO_PINCFG36_NCESRC36_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53988   GPIO_PINCFG36_NCESRC36_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53989   GPIO_PINCFG36_NCESRC36_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53990   GPIO_PINCFG36_NCESRC36_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53991   GPIO_PINCFG36_NCESRC36_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53992   GPIO_PINCFG36_NCESRC36_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53993   GPIO_PINCFG36_NCESRC36_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53994   GPIO_PINCFG36_NCESRC36_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53995   GPIO_PINCFG36_NCESRC36_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53996   GPIO_PINCFG36_NCESRC36_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53997   GPIO_PINCFG36_NCESRC36_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53998   GPIO_PINCFG36_NCESRC36_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53999 } GPIO_PINCFG36_NCESRC36_Enum;
54000 
54001 /* ===========================================  GPIO PINCFG36 PULLCFG36 [13..15]  ============================================ */
54002 typedef enum {                                  /*!< GPIO_PINCFG36_PULLCFG36                                                   */
54003   GPIO_PINCFG36_PULLCFG36_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54004   GPIO_PINCFG36_PULLCFG36_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54005   GPIO_PINCFG36_PULLCFG36_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54006   GPIO_PINCFG36_PULLCFG36_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54007   GPIO_PINCFG36_PULLCFG36_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54008   GPIO_PINCFG36_PULLCFG36_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54009   GPIO_PINCFG36_PULLCFG36_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54010   GPIO_PINCFG36_PULLCFG36_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54011 } GPIO_PINCFG36_PULLCFG36_Enum;
54012 
54013 /* ==============================================  GPIO PINCFG36 DS36 [10..11]  ============================================== */
54014 typedef enum {                                  /*!< GPIO_PINCFG36_DS36                                                        */
54015   GPIO_PINCFG36_DS36_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54016   GPIO_PINCFG36_DS36_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54017   GPIO_PINCFG36_DS36_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54018   GPIO_PINCFG36_DS36_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54019 } GPIO_PINCFG36_DS36_Enum;
54020 
54021 /* =============================================  GPIO PINCFG36 OUTCFG36 [8..9]  ============================================= */
54022 typedef enum {                                  /*!< GPIO_PINCFG36_OUTCFG36                                                    */
54023   GPIO_PINCFG36_OUTCFG36_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54024   GPIO_PINCFG36_OUTCFG36_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54025                                                      and 1 values on pin.                                                      */
54026   GPIO_PINCFG36_OUTCFG36_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54027                                                      low, tristate otherwise.                                                  */
54028   GPIO_PINCFG36_OUTCFG36_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54029                                                      drive 0, 1 of HiZ on pin.                                                 */
54030 } GPIO_PINCFG36_OUTCFG36_Enum;
54031 
54032 /* =============================================  GPIO PINCFG36 IRPTEN36 [6..7]  ============================================= */
54033 typedef enum {                                  /*!< GPIO_PINCFG36_IRPTEN36                                                    */
54034   GPIO_PINCFG36_IRPTEN36_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54035   GPIO_PINCFG36_IRPTEN36_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54036                                                      on this GPIO                                                              */
54037   GPIO_PINCFG36_IRPTEN36_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54038                                                      on this GPIO                                                              */
54039   GPIO_PINCFG36_IRPTEN36_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54040                                                      GPIO                                                                      */
54041 } GPIO_PINCFG36_IRPTEN36_Enum;
54042 
54043 /* =============================================  GPIO PINCFG36 FNCSEL36 [0..3]  ============================================= */
54044 typedef enum {                                  /*!< GPIO_PINCFG36_FNCSEL36                                                    */
54045   GPIO_PINCFG36_FNCSEL36_M4MISO        = 0,     /*!< M4MISO : Serial SPI MASTER MISO input (IOM 4)                             */
54046   GPIO_PINCFG36_FNCSEL36_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
54047   GPIO_PINCFG36_FNCSEL36_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
54048   GPIO_PINCFG36_FNCSEL36_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54049   GPIO_PINCFG36_FNCSEL36_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
54050   GPIO_PINCFG36_FNCSEL36_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
54051   GPIO_PINCFG36_FNCSEL36_CT36          = 6,     /*!< CT36 : Timer/Counter input or output; Selection of direction
54052                                                      is done via CTIMER register settings.                                     */
54053   GPIO_PINCFG36_FNCSEL36_NCE36         = 7,     /*!< NCE36 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54054                                                      CE_POLARITY field                                                         */
54055   GPIO_PINCFG36_FNCSEL36_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
54056   GPIO_PINCFG36_FNCSEL36_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54057   GPIO_PINCFG36_FNCSEL36_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54058   GPIO_PINCFG36_FNCSEL36_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54059   GPIO_PINCFG36_FNCSEL36_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54060   GPIO_PINCFG36_FNCSEL36_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54061   GPIO_PINCFG36_FNCSEL36_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54062   GPIO_PINCFG36_FNCSEL36_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54063 } GPIO_PINCFG36_FNCSEL36_Enum;
54064 
54065 /* =======================================================  PINCFG37  ======================================================== */
54066 /* ============================================  GPIO PINCFG37 NCEPOL37 [22..22]  ============================================ */
54067 typedef enum {                                  /*!< GPIO_PINCFG37_NCEPOL37                                                    */
54068   GPIO_PINCFG37_NCEPOL37_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54069   GPIO_PINCFG37_NCEPOL37_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54070 } GPIO_PINCFG37_NCEPOL37_Enum;
54071 
54072 /* ============================================  GPIO PINCFG37 NCESRC37 [16..21]  ============================================ */
54073 typedef enum {                                  /*!< GPIO_PINCFG37_NCESRC37                                                    */
54074   GPIO_PINCFG37_NCESRC37_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54075   GPIO_PINCFG37_NCESRC37_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54076   GPIO_PINCFG37_NCESRC37_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54077   GPIO_PINCFG37_NCESRC37_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54078   GPIO_PINCFG37_NCESRC37_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54079   GPIO_PINCFG37_NCESRC37_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54080   GPIO_PINCFG37_NCESRC37_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54081   GPIO_PINCFG37_NCESRC37_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54082   GPIO_PINCFG37_NCESRC37_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54083   GPIO_PINCFG37_NCESRC37_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54084   GPIO_PINCFG37_NCESRC37_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54085   GPIO_PINCFG37_NCESRC37_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54086   GPIO_PINCFG37_NCESRC37_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54087   GPIO_PINCFG37_NCESRC37_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54088   GPIO_PINCFG37_NCESRC37_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54089   GPIO_PINCFG37_NCESRC37_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54090   GPIO_PINCFG37_NCESRC37_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54091   GPIO_PINCFG37_NCESRC37_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54092   GPIO_PINCFG37_NCESRC37_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54093   GPIO_PINCFG37_NCESRC37_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54094   GPIO_PINCFG37_NCESRC37_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54095   GPIO_PINCFG37_NCESRC37_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54096   GPIO_PINCFG37_NCESRC37_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54097   GPIO_PINCFG37_NCESRC37_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54098   GPIO_PINCFG37_NCESRC37_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54099   GPIO_PINCFG37_NCESRC37_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54100   GPIO_PINCFG37_NCESRC37_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54101   GPIO_PINCFG37_NCESRC37_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54102   GPIO_PINCFG37_NCESRC37_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54103   GPIO_PINCFG37_NCESRC37_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54104   GPIO_PINCFG37_NCESRC37_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54105   GPIO_PINCFG37_NCESRC37_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54106   GPIO_PINCFG37_NCESRC37_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54107   GPIO_PINCFG37_NCESRC37_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54108   GPIO_PINCFG37_NCESRC37_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54109   GPIO_PINCFG37_NCESRC37_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54110   GPIO_PINCFG37_NCESRC37_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54111   GPIO_PINCFG37_NCESRC37_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54112   GPIO_PINCFG37_NCESRC37_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54113   GPIO_PINCFG37_NCESRC37_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54114   GPIO_PINCFG37_NCESRC37_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54115   GPIO_PINCFG37_NCESRC37_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54116   GPIO_PINCFG37_NCESRC37_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54117 } GPIO_PINCFG37_NCESRC37_Enum;
54118 
54119 /* ===========================================  GPIO PINCFG37 PULLCFG37 [13..15]  ============================================ */
54120 typedef enum {                                  /*!< GPIO_PINCFG37_PULLCFG37                                                   */
54121   GPIO_PINCFG37_PULLCFG37_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54122   GPIO_PINCFG37_PULLCFG37_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54123   GPIO_PINCFG37_PULLCFG37_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54124   GPIO_PINCFG37_PULLCFG37_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54125   GPIO_PINCFG37_PULLCFG37_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54126   GPIO_PINCFG37_PULLCFG37_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54127   GPIO_PINCFG37_PULLCFG37_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54128   GPIO_PINCFG37_PULLCFG37_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54129 } GPIO_PINCFG37_PULLCFG37_Enum;
54130 
54131 /* ==============================================  GPIO PINCFG37 DS37 [10..11]  ============================================== */
54132 typedef enum {                                  /*!< GPIO_PINCFG37_DS37                                                        */
54133   GPIO_PINCFG37_DS37_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54134   GPIO_PINCFG37_DS37_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54135   GPIO_PINCFG37_DS37_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54136   GPIO_PINCFG37_DS37_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54137 } GPIO_PINCFG37_DS37_Enum;
54138 
54139 /* =============================================  GPIO PINCFG37 OUTCFG37 [8..9]  ============================================= */
54140 typedef enum {                                  /*!< GPIO_PINCFG37_OUTCFG37                                                    */
54141   GPIO_PINCFG37_OUTCFG37_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54142   GPIO_PINCFG37_OUTCFG37_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54143                                                      and 1 values on pin.                                                      */
54144   GPIO_PINCFG37_OUTCFG37_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54145                                                      low, tristate otherwise.                                                  */
54146   GPIO_PINCFG37_OUTCFG37_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54147                                                      drive 0, 1 of HiZ on pin.                                                 */
54148 } GPIO_PINCFG37_OUTCFG37_Enum;
54149 
54150 /* =============================================  GPIO PINCFG37 IRPTEN37 [6..7]  ============================================= */
54151 typedef enum {                                  /*!< GPIO_PINCFG37_IRPTEN37                                                    */
54152   GPIO_PINCFG37_IRPTEN37_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54153   GPIO_PINCFG37_IRPTEN37_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54154                                                      on this GPIO                                                              */
54155   GPIO_PINCFG37_IRPTEN37_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54156                                                      on this GPIO                                                              */
54157   GPIO_PINCFG37_IRPTEN37_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54158                                                      GPIO                                                                      */
54159 } GPIO_PINCFG37_IRPTEN37_Enum;
54160 
54161 /* =============================================  GPIO PINCFG37 FNCSEL37 [0..3]  ============================================= */
54162 typedef enum {                                  /*!< GPIO_PINCFG37_FNCSEL37                                                    */
54163   GPIO_PINCFG37_FNCSEL37_MSPI1_0       = 0,     /*!< MSPI1_0 : MSPI Master 1 Interface Signal                                  */
54164   GPIO_PINCFG37_FNCSEL37_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
54165   GPIO_PINCFG37_FNCSEL37_32KHzXT       = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
54166   GPIO_PINCFG37_FNCSEL37_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54167   GPIO_PINCFG37_FNCSEL37_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
54168   GPIO_PINCFG37_FNCSEL37_DISP_D15      = 5,     /*!< DISP_D15 : Display Data 15                                                */
54169   GPIO_PINCFG37_FNCSEL37_CT37          = 6,     /*!< CT37 : Timer/Counter input or output; Selection of direction
54170                                                      is done via CTIMER register settings.                                     */
54171   GPIO_PINCFG37_FNCSEL37_NCE37         = 7,     /*!< NCE37 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54172                                                      CE_POLARITY field                                                         */
54173   GPIO_PINCFG37_FNCSEL37_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
54174   GPIO_PINCFG37_FNCSEL37_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54175   GPIO_PINCFG37_FNCSEL37_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54176   GPIO_PINCFG37_FNCSEL37_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54177   GPIO_PINCFG37_FNCSEL37_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54178   GPIO_PINCFG37_FNCSEL37_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54179   GPIO_PINCFG37_FNCSEL37_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54180   GPIO_PINCFG37_FNCSEL37_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54181 } GPIO_PINCFG37_FNCSEL37_Enum;
54182 
54183 /* =======================================================  PINCFG38  ======================================================== */
54184 /* ============================================  GPIO PINCFG38 NCEPOL38 [22..22]  ============================================ */
54185 typedef enum {                                  /*!< GPIO_PINCFG38_NCEPOL38                                                    */
54186   GPIO_PINCFG38_NCEPOL38_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54187   GPIO_PINCFG38_NCEPOL38_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54188 } GPIO_PINCFG38_NCEPOL38_Enum;
54189 
54190 /* ============================================  GPIO PINCFG38 NCESRC38 [16..21]  ============================================ */
54191 typedef enum {                                  /*!< GPIO_PINCFG38_NCESRC38                                                    */
54192   GPIO_PINCFG38_NCESRC38_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54193   GPIO_PINCFG38_NCESRC38_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54194   GPIO_PINCFG38_NCESRC38_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54195   GPIO_PINCFG38_NCESRC38_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54196   GPIO_PINCFG38_NCESRC38_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54197   GPIO_PINCFG38_NCESRC38_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54198   GPIO_PINCFG38_NCESRC38_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54199   GPIO_PINCFG38_NCESRC38_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54200   GPIO_PINCFG38_NCESRC38_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54201   GPIO_PINCFG38_NCESRC38_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54202   GPIO_PINCFG38_NCESRC38_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54203   GPIO_PINCFG38_NCESRC38_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54204   GPIO_PINCFG38_NCESRC38_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54205   GPIO_PINCFG38_NCESRC38_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54206   GPIO_PINCFG38_NCESRC38_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54207   GPIO_PINCFG38_NCESRC38_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54208   GPIO_PINCFG38_NCESRC38_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54209   GPIO_PINCFG38_NCESRC38_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54210   GPIO_PINCFG38_NCESRC38_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54211   GPIO_PINCFG38_NCESRC38_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54212   GPIO_PINCFG38_NCESRC38_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54213   GPIO_PINCFG38_NCESRC38_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54214   GPIO_PINCFG38_NCESRC38_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54215   GPIO_PINCFG38_NCESRC38_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54216   GPIO_PINCFG38_NCESRC38_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54217   GPIO_PINCFG38_NCESRC38_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54218   GPIO_PINCFG38_NCESRC38_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54219   GPIO_PINCFG38_NCESRC38_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54220   GPIO_PINCFG38_NCESRC38_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54221   GPIO_PINCFG38_NCESRC38_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54222   GPIO_PINCFG38_NCESRC38_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54223   GPIO_PINCFG38_NCESRC38_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54224   GPIO_PINCFG38_NCESRC38_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54225   GPIO_PINCFG38_NCESRC38_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54226   GPIO_PINCFG38_NCESRC38_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54227   GPIO_PINCFG38_NCESRC38_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54228   GPIO_PINCFG38_NCESRC38_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54229   GPIO_PINCFG38_NCESRC38_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54230   GPIO_PINCFG38_NCESRC38_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54231   GPIO_PINCFG38_NCESRC38_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54232   GPIO_PINCFG38_NCESRC38_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54233   GPIO_PINCFG38_NCESRC38_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54234   GPIO_PINCFG38_NCESRC38_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54235 } GPIO_PINCFG38_NCESRC38_Enum;
54236 
54237 /* ===========================================  GPIO PINCFG38 PULLCFG38 [13..15]  ============================================ */
54238 typedef enum {                                  /*!< GPIO_PINCFG38_PULLCFG38                                                   */
54239   GPIO_PINCFG38_PULLCFG38_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54240   GPIO_PINCFG38_PULLCFG38_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54241   GPIO_PINCFG38_PULLCFG38_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54242   GPIO_PINCFG38_PULLCFG38_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54243   GPIO_PINCFG38_PULLCFG38_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54244   GPIO_PINCFG38_PULLCFG38_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54245   GPIO_PINCFG38_PULLCFG38_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54246   GPIO_PINCFG38_PULLCFG38_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54247 } GPIO_PINCFG38_PULLCFG38_Enum;
54248 
54249 /* ==============================================  GPIO PINCFG38 DS38 [10..11]  ============================================== */
54250 typedef enum {                                  /*!< GPIO_PINCFG38_DS38                                                        */
54251   GPIO_PINCFG38_DS38_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54252   GPIO_PINCFG38_DS38_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54253   GPIO_PINCFG38_DS38_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54254   GPIO_PINCFG38_DS38_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54255 } GPIO_PINCFG38_DS38_Enum;
54256 
54257 /* =============================================  GPIO PINCFG38 OUTCFG38 [8..9]  ============================================= */
54258 typedef enum {                                  /*!< GPIO_PINCFG38_OUTCFG38                                                    */
54259   GPIO_PINCFG38_OUTCFG38_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54260   GPIO_PINCFG38_OUTCFG38_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54261                                                      and 1 values on pin.                                                      */
54262   GPIO_PINCFG38_OUTCFG38_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54263                                                      low, tristate otherwise.                                                  */
54264   GPIO_PINCFG38_OUTCFG38_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54265                                                      drive 0, 1 of HiZ on pin.                                                 */
54266 } GPIO_PINCFG38_OUTCFG38_Enum;
54267 
54268 /* =============================================  GPIO PINCFG38 IRPTEN38 [6..7]  ============================================= */
54269 typedef enum {                                  /*!< GPIO_PINCFG38_IRPTEN38                                                    */
54270   GPIO_PINCFG38_IRPTEN38_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54271   GPIO_PINCFG38_IRPTEN38_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54272                                                      on this GPIO                                                              */
54273   GPIO_PINCFG38_IRPTEN38_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54274                                                      on this GPIO                                                              */
54275   GPIO_PINCFG38_IRPTEN38_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54276                                                      GPIO                                                                      */
54277 } GPIO_PINCFG38_IRPTEN38_Enum;
54278 
54279 /* =============================================  GPIO PINCFG38 FNCSEL38 [0..3]  ============================================= */
54280 typedef enum {                                  /*!< GPIO_PINCFG38_FNCSEL38                                                    */
54281   GPIO_PINCFG38_FNCSEL38_MSPI1_1       = 0,     /*!< MSPI1_1 : MSPI Master 1 Interface Signal                                  */
54282   GPIO_PINCFG38_FNCSEL38_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
54283   GPIO_PINCFG38_FNCSEL38_SWTRACECLK    = 2,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
54284   GPIO_PINCFG38_FNCSEL38_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54285   GPIO_PINCFG38_FNCSEL38_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
54286   GPIO_PINCFG38_FNCSEL38_DISP_D16      = 5,     /*!< DISP_D16 : Display Data 16                                                */
54287   GPIO_PINCFG38_FNCSEL38_CT38          = 6,     /*!< CT38 : Timer/Counter input or output; Selection of direction
54288                                                      is done via CTIMER register settings.                                     */
54289   GPIO_PINCFG38_FNCSEL38_NCE38         = 7,     /*!< NCE38 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54290                                                      CE_POLARITY field                                                         */
54291   GPIO_PINCFG38_FNCSEL38_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
54292   GPIO_PINCFG38_FNCSEL38_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54293   GPIO_PINCFG38_FNCSEL38_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54294   GPIO_PINCFG38_FNCSEL38_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54295   GPIO_PINCFG38_FNCSEL38_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54296   GPIO_PINCFG38_FNCSEL38_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54297   GPIO_PINCFG38_FNCSEL38_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54298   GPIO_PINCFG38_FNCSEL38_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54299 } GPIO_PINCFG38_FNCSEL38_Enum;
54300 
54301 /* =======================================================  PINCFG39  ======================================================== */
54302 /* ============================================  GPIO PINCFG39 NCEPOL39 [22..22]  ============================================ */
54303 typedef enum {                                  /*!< GPIO_PINCFG39_NCEPOL39                                                    */
54304   GPIO_PINCFG39_NCEPOL39_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54305   GPIO_PINCFG39_NCEPOL39_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54306 } GPIO_PINCFG39_NCEPOL39_Enum;
54307 
54308 /* ============================================  GPIO PINCFG39 NCESRC39 [16..21]  ============================================ */
54309 typedef enum {                                  /*!< GPIO_PINCFG39_NCESRC39                                                    */
54310   GPIO_PINCFG39_NCESRC39_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54311   GPIO_PINCFG39_NCESRC39_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54312   GPIO_PINCFG39_NCESRC39_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54313   GPIO_PINCFG39_NCESRC39_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54314   GPIO_PINCFG39_NCESRC39_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54315   GPIO_PINCFG39_NCESRC39_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54316   GPIO_PINCFG39_NCESRC39_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54317   GPIO_PINCFG39_NCESRC39_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54318   GPIO_PINCFG39_NCESRC39_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54319   GPIO_PINCFG39_NCESRC39_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54320   GPIO_PINCFG39_NCESRC39_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54321   GPIO_PINCFG39_NCESRC39_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54322   GPIO_PINCFG39_NCESRC39_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54323   GPIO_PINCFG39_NCESRC39_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54324   GPIO_PINCFG39_NCESRC39_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54325   GPIO_PINCFG39_NCESRC39_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54326   GPIO_PINCFG39_NCESRC39_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54327   GPIO_PINCFG39_NCESRC39_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54328   GPIO_PINCFG39_NCESRC39_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54329   GPIO_PINCFG39_NCESRC39_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54330   GPIO_PINCFG39_NCESRC39_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54331   GPIO_PINCFG39_NCESRC39_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54332   GPIO_PINCFG39_NCESRC39_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54333   GPIO_PINCFG39_NCESRC39_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54334   GPIO_PINCFG39_NCESRC39_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54335   GPIO_PINCFG39_NCESRC39_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54336   GPIO_PINCFG39_NCESRC39_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54337   GPIO_PINCFG39_NCESRC39_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54338   GPIO_PINCFG39_NCESRC39_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54339   GPIO_PINCFG39_NCESRC39_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54340   GPIO_PINCFG39_NCESRC39_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54341   GPIO_PINCFG39_NCESRC39_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54342   GPIO_PINCFG39_NCESRC39_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54343   GPIO_PINCFG39_NCESRC39_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54344   GPIO_PINCFG39_NCESRC39_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54345   GPIO_PINCFG39_NCESRC39_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54346   GPIO_PINCFG39_NCESRC39_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54347   GPIO_PINCFG39_NCESRC39_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54348   GPIO_PINCFG39_NCESRC39_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54349   GPIO_PINCFG39_NCESRC39_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54350   GPIO_PINCFG39_NCESRC39_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54351   GPIO_PINCFG39_NCESRC39_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54352   GPIO_PINCFG39_NCESRC39_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54353 } GPIO_PINCFG39_NCESRC39_Enum;
54354 
54355 /* ===========================================  GPIO PINCFG39 PULLCFG39 [13..15]  ============================================ */
54356 typedef enum {                                  /*!< GPIO_PINCFG39_PULLCFG39                                                   */
54357   GPIO_PINCFG39_PULLCFG39_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54358   GPIO_PINCFG39_PULLCFG39_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54359   GPIO_PINCFG39_PULLCFG39_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54360   GPIO_PINCFG39_PULLCFG39_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54361   GPIO_PINCFG39_PULLCFG39_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54362   GPIO_PINCFG39_PULLCFG39_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54363   GPIO_PINCFG39_PULLCFG39_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54364   GPIO_PINCFG39_PULLCFG39_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54365 } GPIO_PINCFG39_PULLCFG39_Enum;
54366 
54367 /* ==============================================  GPIO PINCFG39 DS39 [10..11]  ============================================== */
54368 typedef enum {                                  /*!< GPIO_PINCFG39_DS39                                                        */
54369   GPIO_PINCFG39_DS39_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54370   GPIO_PINCFG39_DS39_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54371   GPIO_PINCFG39_DS39_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54372   GPIO_PINCFG39_DS39_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54373 } GPIO_PINCFG39_DS39_Enum;
54374 
54375 /* =============================================  GPIO PINCFG39 OUTCFG39 [8..9]  ============================================= */
54376 typedef enum {                                  /*!< GPIO_PINCFG39_OUTCFG39                                                    */
54377   GPIO_PINCFG39_OUTCFG39_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54378   GPIO_PINCFG39_OUTCFG39_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54379                                                      and 1 values on pin.                                                      */
54380   GPIO_PINCFG39_OUTCFG39_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54381                                                      low, tristate otherwise.                                                  */
54382   GPIO_PINCFG39_OUTCFG39_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54383                                                      drive 0, 1 of HiZ on pin.                                                 */
54384 } GPIO_PINCFG39_OUTCFG39_Enum;
54385 
54386 /* =============================================  GPIO PINCFG39 IRPTEN39 [6..7]  ============================================= */
54387 typedef enum {                                  /*!< GPIO_PINCFG39_IRPTEN39                                                    */
54388   GPIO_PINCFG39_IRPTEN39_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54389   GPIO_PINCFG39_IRPTEN39_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54390                                                      on this GPIO                                                              */
54391   GPIO_PINCFG39_IRPTEN39_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54392                                                      on this GPIO                                                              */
54393   GPIO_PINCFG39_IRPTEN39_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54394                                                      GPIO                                                                      */
54395 } GPIO_PINCFG39_IRPTEN39_Enum;
54396 
54397 /* =============================================  GPIO PINCFG39 FNCSEL39 [0..3]  ============================================= */
54398 typedef enum {                                  /*!< GPIO_PINCFG39_FNCSEL39                                                    */
54399   GPIO_PINCFG39_FNCSEL39_MSPI1_2       = 0,     /*!< MSPI1_2 : MSPI Master 1 Interface Signal                                  */
54400   GPIO_PINCFG39_FNCSEL39_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
54401   GPIO_PINCFG39_FNCSEL39_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
54402   GPIO_PINCFG39_FNCSEL39_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54403   GPIO_PINCFG39_FNCSEL39_UART2RTS      = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
54404   GPIO_PINCFG39_FNCSEL39_DISP_D17      = 5,     /*!< DISP_D17 : Display Data 17                                                */
54405   GPIO_PINCFG39_FNCSEL39_CT39          = 6,     /*!< CT39 : Timer/Counter input or output; Selection of direction
54406                                                      is done via CTIMER register settings.                                     */
54407   GPIO_PINCFG39_FNCSEL39_NCE39         = 7,     /*!< NCE39 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54408                                                      CE_POLARITY field                                                         */
54409   GPIO_PINCFG39_FNCSEL39_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
54410   GPIO_PINCFG39_FNCSEL39_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54411   GPIO_PINCFG39_FNCSEL39_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54412   GPIO_PINCFG39_FNCSEL39_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54413   GPIO_PINCFG39_FNCSEL39_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54414   GPIO_PINCFG39_FNCSEL39_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54415   GPIO_PINCFG39_FNCSEL39_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54416   GPIO_PINCFG39_FNCSEL39_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54417 } GPIO_PINCFG39_FNCSEL39_Enum;
54418 
54419 /* =======================================================  PINCFG40  ======================================================== */
54420 /* ============================================  GPIO PINCFG40 NCEPOL40 [22..22]  ============================================ */
54421 typedef enum {                                  /*!< GPIO_PINCFG40_NCEPOL40                                                    */
54422   GPIO_PINCFG40_NCEPOL40_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54423   GPIO_PINCFG40_NCEPOL40_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54424 } GPIO_PINCFG40_NCEPOL40_Enum;
54425 
54426 /* ============================================  GPIO PINCFG40 NCESRC40 [16..21]  ============================================ */
54427 typedef enum {                                  /*!< GPIO_PINCFG40_NCESRC40                                                    */
54428   GPIO_PINCFG40_NCESRC40_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54429   GPIO_PINCFG40_NCESRC40_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54430   GPIO_PINCFG40_NCESRC40_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54431   GPIO_PINCFG40_NCESRC40_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54432   GPIO_PINCFG40_NCESRC40_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54433   GPIO_PINCFG40_NCESRC40_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54434   GPIO_PINCFG40_NCESRC40_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54435   GPIO_PINCFG40_NCESRC40_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54436   GPIO_PINCFG40_NCESRC40_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54437   GPIO_PINCFG40_NCESRC40_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54438   GPIO_PINCFG40_NCESRC40_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54439   GPIO_PINCFG40_NCESRC40_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54440   GPIO_PINCFG40_NCESRC40_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54441   GPIO_PINCFG40_NCESRC40_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54442   GPIO_PINCFG40_NCESRC40_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54443   GPIO_PINCFG40_NCESRC40_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54444   GPIO_PINCFG40_NCESRC40_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54445   GPIO_PINCFG40_NCESRC40_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54446   GPIO_PINCFG40_NCESRC40_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54447   GPIO_PINCFG40_NCESRC40_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54448   GPIO_PINCFG40_NCESRC40_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54449   GPIO_PINCFG40_NCESRC40_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54450   GPIO_PINCFG40_NCESRC40_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54451   GPIO_PINCFG40_NCESRC40_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54452   GPIO_PINCFG40_NCESRC40_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54453   GPIO_PINCFG40_NCESRC40_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54454   GPIO_PINCFG40_NCESRC40_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54455   GPIO_PINCFG40_NCESRC40_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54456   GPIO_PINCFG40_NCESRC40_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54457   GPIO_PINCFG40_NCESRC40_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54458   GPIO_PINCFG40_NCESRC40_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54459   GPIO_PINCFG40_NCESRC40_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54460   GPIO_PINCFG40_NCESRC40_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54461   GPIO_PINCFG40_NCESRC40_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54462   GPIO_PINCFG40_NCESRC40_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54463   GPIO_PINCFG40_NCESRC40_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54464   GPIO_PINCFG40_NCESRC40_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54465   GPIO_PINCFG40_NCESRC40_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54466   GPIO_PINCFG40_NCESRC40_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54467   GPIO_PINCFG40_NCESRC40_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54468   GPIO_PINCFG40_NCESRC40_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54469   GPIO_PINCFG40_NCESRC40_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54470   GPIO_PINCFG40_NCESRC40_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54471 } GPIO_PINCFG40_NCESRC40_Enum;
54472 
54473 /* ===========================================  GPIO PINCFG40 PULLCFG40 [13..15]  ============================================ */
54474 typedef enum {                                  /*!< GPIO_PINCFG40_PULLCFG40                                                   */
54475   GPIO_PINCFG40_PULLCFG40_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54476   GPIO_PINCFG40_PULLCFG40_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54477   GPIO_PINCFG40_PULLCFG40_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54478   GPIO_PINCFG40_PULLCFG40_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54479   GPIO_PINCFG40_PULLCFG40_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54480   GPIO_PINCFG40_PULLCFG40_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54481   GPIO_PINCFG40_PULLCFG40_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54482   GPIO_PINCFG40_PULLCFG40_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54483 } GPIO_PINCFG40_PULLCFG40_Enum;
54484 
54485 /* ==============================================  GPIO PINCFG40 DS40 [10..11]  ============================================== */
54486 typedef enum {                                  /*!< GPIO_PINCFG40_DS40                                                        */
54487   GPIO_PINCFG40_DS40_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54488   GPIO_PINCFG40_DS40_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54489   GPIO_PINCFG40_DS40_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54490   GPIO_PINCFG40_DS40_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54491 } GPIO_PINCFG40_DS40_Enum;
54492 
54493 /* =============================================  GPIO PINCFG40 OUTCFG40 [8..9]  ============================================= */
54494 typedef enum {                                  /*!< GPIO_PINCFG40_OUTCFG40                                                    */
54495   GPIO_PINCFG40_OUTCFG40_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54496   GPIO_PINCFG40_OUTCFG40_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54497                                                      and 1 values on pin.                                                      */
54498   GPIO_PINCFG40_OUTCFG40_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54499                                                      low, tristate otherwise.                                                  */
54500   GPIO_PINCFG40_OUTCFG40_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54501                                                      drive 0, 1 of HiZ on pin.                                                 */
54502 } GPIO_PINCFG40_OUTCFG40_Enum;
54503 
54504 /* =============================================  GPIO PINCFG40 IRPTEN40 [6..7]  ============================================= */
54505 typedef enum {                                  /*!< GPIO_PINCFG40_IRPTEN40                                                    */
54506   GPIO_PINCFG40_IRPTEN40_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54507   GPIO_PINCFG40_IRPTEN40_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54508                                                      on this GPIO                                                              */
54509   GPIO_PINCFG40_IRPTEN40_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54510                                                      on this GPIO                                                              */
54511   GPIO_PINCFG40_IRPTEN40_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54512                                                      GPIO                                                                      */
54513 } GPIO_PINCFG40_IRPTEN40_Enum;
54514 
54515 /* =============================================  GPIO PINCFG40 FNCSEL40 [0..3]  ============================================= */
54516 typedef enum {                                  /*!< GPIO_PINCFG40_FNCSEL40                                                    */
54517   GPIO_PINCFG40_FNCSEL40_MSPI1_3       = 0,     /*!< MSPI1_3 : MSPI Master 1 Interface Signal                                  */
54518   GPIO_PINCFG40_FNCSEL40_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
54519   GPIO_PINCFG40_FNCSEL40_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
54520   GPIO_PINCFG40_FNCSEL40_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54521   GPIO_PINCFG40_FNCSEL40_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
54522   GPIO_PINCFG40_FNCSEL40_DISP_D18      = 5,     /*!< DISP_D18 : Display Data 18                                                */
54523   GPIO_PINCFG40_FNCSEL40_CT40          = 6,     /*!< CT40 : Timer/Counter input or output; Selection of direction
54524                                                      is done via CTIMER register settings.                                     */
54525   GPIO_PINCFG40_FNCSEL40_NCE40         = 7,     /*!< NCE40 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54526                                                      CE_POLARITY field                                                         */
54527   GPIO_PINCFG40_FNCSEL40_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
54528   GPIO_PINCFG40_FNCSEL40_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54529   GPIO_PINCFG40_FNCSEL40_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54530   GPIO_PINCFG40_FNCSEL40_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54531   GPIO_PINCFG40_FNCSEL40_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54532   GPIO_PINCFG40_FNCSEL40_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54533   GPIO_PINCFG40_FNCSEL40_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54534   GPIO_PINCFG40_FNCSEL40_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54535 } GPIO_PINCFG40_FNCSEL40_Enum;
54536 
54537 /* =======================================================  PINCFG41  ======================================================== */
54538 /* ============================================  GPIO PINCFG41 NCEPOL41 [22..22]  ============================================ */
54539 typedef enum {                                  /*!< GPIO_PINCFG41_NCEPOL41                                                    */
54540   GPIO_PINCFG41_NCEPOL41_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54541   GPIO_PINCFG41_NCEPOL41_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54542 } GPIO_PINCFG41_NCEPOL41_Enum;
54543 
54544 /* ============================================  GPIO PINCFG41 NCESRC41 [16..21]  ============================================ */
54545 typedef enum {                                  /*!< GPIO_PINCFG41_NCESRC41                                                    */
54546   GPIO_PINCFG41_NCESRC41_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54547   GPIO_PINCFG41_NCESRC41_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54548   GPIO_PINCFG41_NCESRC41_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54549   GPIO_PINCFG41_NCESRC41_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54550   GPIO_PINCFG41_NCESRC41_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54551   GPIO_PINCFG41_NCESRC41_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54552   GPIO_PINCFG41_NCESRC41_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54553   GPIO_PINCFG41_NCESRC41_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54554   GPIO_PINCFG41_NCESRC41_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54555   GPIO_PINCFG41_NCESRC41_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54556   GPIO_PINCFG41_NCESRC41_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54557   GPIO_PINCFG41_NCESRC41_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54558   GPIO_PINCFG41_NCESRC41_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54559   GPIO_PINCFG41_NCESRC41_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54560   GPIO_PINCFG41_NCESRC41_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54561   GPIO_PINCFG41_NCESRC41_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54562   GPIO_PINCFG41_NCESRC41_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54563   GPIO_PINCFG41_NCESRC41_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54564   GPIO_PINCFG41_NCESRC41_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54565   GPIO_PINCFG41_NCESRC41_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54566   GPIO_PINCFG41_NCESRC41_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54567   GPIO_PINCFG41_NCESRC41_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54568   GPIO_PINCFG41_NCESRC41_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54569   GPIO_PINCFG41_NCESRC41_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54570   GPIO_PINCFG41_NCESRC41_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54571   GPIO_PINCFG41_NCESRC41_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54572   GPIO_PINCFG41_NCESRC41_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54573   GPIO_PINCFG41_NCESRC41_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54574   GPIO_PINCFG41_NCESRC41_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54575   GPIO_PINCFG41_NCESRC41_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54576   GPIO_PINCFG41_NCESRC41_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54577   GPIO_PINCFG41_NCESRC41_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54578   GPIO_PINCFG41_NCESRC41_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54579   GPIO_PINCFG41_NCESRC41_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54580   GPIO_PINCFG41_NCESRC41_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54581   GPIO_PINCFG41_NCESRC41_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54582   GPIO_PINCFG41_NCESRC41_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54583   GPIO_PINCFG41_NCESRC41_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54584   GPIO_PINCFG41_NCESRC41_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54585   GPIO_PINCFG41_NCESRC41_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54586   GPIO_PINCFG41_NCESRC41_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54587   GPIO_PINCFG41_NCESRC41_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54588   GPIO_PINCFG41_NCESRC41_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54589 } GPIO_PINCFG41_NCESRC41_Enum;
54590 
54591 /* ===========================================  GPIO PINCFG41 PULLCFG41 [13..15]  ============================================ */
54592 typedef enum {                                  /*!< GPIO_PINCFG41_PULLCFG41                                                   */
54593   GPIO_PINCFG41_PULLCFG41_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54594   GPIO_PINCFG41_PULLCFG41_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54595   GPIO_PINCFG41_PULLCFG41_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54596   GPIO_PINCFG41_PULLCFG41_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54597   GPIO_PINCFG41_PULLCFG41_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54598   GPIO_PINCFG41_PULLCFG41_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54599   GPIO_PINCFG41_PULLCFG41_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54600   GPIO_PINCFG41_PULLCFG41_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54601 } GPIO_PINCFG41_PULLCFG41_Enum;
54602 
54603 /* ==============================================  GPIO PINCFG41 DS41 [10..11]  ============================================== */
54604 typedef enum {                                  /*!< GPIO_PINCFG41_DS41                                                        */
54605   GPIO_PINCFG41_DS41_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54606   GPIO_PINCFG41_DS41_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54607   GPIO_PINCFG41_DS41_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54608   GPIO_PINCFG41_DS41_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54609 } GPIO_PINCFG41_DS41_Enum;
54610 
54611 /* =============================================  GPIO PINCFG41 OUTCFG41 [8..9]  ============================================= */
54612 typedef enum {                                  /*!< GPIO_PINCFG41_OUTCFG41                                                    */
54613   GPIO_PINCFG41_OUTCFG41_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54614   GPIO_PINCFG41_OUTCFG41_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54615                                                      and 1 values on pin.                                                      */
54616   GPIO_PINCFG41_OUTCFG41_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54617                                                      low, tristate otherwise.                                                  */
54618   GPIO_PINCFG41_OUTCFG41_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54619                                                      drive 0, 1 of HiZ on pin.                                                 */
54620 } GPIO_PINCFG41_OUTCFG41_Enum;
54621 
54622 /* =============================================  GPIO PINCFG41 IRPTEN41 [6..7]  ============================================= */
54623 typedef enum {                                  /*!< GPIO_PINCFG41_IRPTEN41                                                    */
54624   GPIO_PINCFG41_IRPTEN41_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54625   GPIO_PINCFG41_IRPTEN41_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54626                                                      on this GPIO                                                              */
54627   GPIO_PINCFG41_IRPTEN41_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54628                                                      on this GPIO                                                              */
54629   GPIO_PINCFG41_IRPTEN41_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54630                                                      GPIO                                                                      */
54631 } GPIO_PINCFG41_IRPTEN41_Enum;
54632 
54633 /* =============================================  GPIO PINCFG41 FNCSEL41 [0..3]  ============================================= */
54634 typedef enum {                                  /*!< GPIO_PINCFG41_FNCSEL41                                                    */
54635   GPIO_PINCFG41_FNCSEL41_MSPI1_4       = 0,     /*!< MSPI1_4 : MSPI Master 1 Interface Signal                                  */
54636   GPIO_PINCFG41_FNCSEL41_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
54637   GPIO_PINCFG41_FNCSEL41_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
54638   GPIO_PINCFG41_FNCSEL41_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54639   GPIO_PINCFG41_FNCSEL41_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
54640   GPIO_PINCFG41_FNCSEL41_DISP_D19      = 5,     /*!< DISP_D19 : Display Data 19                                                */
54641   GPIO_PINCFG41_FNCSEL41_CT41          = 6,     /*!< CT41 : Timer/Counter input or output; Selection of direction
54642                                                      is done via CTIMER register settings.                                     */
54643   GPIO_PINCFG41_FNCSEL41_NCE41         = 7,     /*!< NCE41 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54644                                                      CE_POLARITY field                                                         */
54645   GPIO_PINCFG41_FNCSEL41_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
54646   GPIO_PINCFG41_FNCSEL41_SWO           = 9,     /*!< SWO : Serial Wire Output                                                  */
54647   GPIO_PINCFG41_FNCSEL41_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54648   GPIO_PINCFG41_FNCSEL41_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54649   GPIO_PINCFG41_FNCSEL41_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54650   GPIO_PINCFG41_FNCSEL41_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54651   GPIO_PINCFG41_FNCSEL41_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54652   GPIO_PINCFG41_FNCSEL41_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54653 } GPIO_PINCFG41_FNCSEL41_Enum;
54654 
54655 /* =======================================================  PINCFG42  ======================================================== */
54656 /* ============================================  GPIO PINCFG42 NCEPOL42 [22..22]  ============================================ */
54657 typedef enum {                                  /*!< GPIO_PINCFG42_NCEPOL42                                                    */
54658   GPIO_PINCFG42_NCEPOL42_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54659   GPIO_PINCFG42_NCEPOL42_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54660 } GPIO_PINCFG42_NCEPOL42_Enum;
54661 
54662 /* ============================================  GPIO PINCFG42 NCESRC42 [16..21]  ============================================ */
54663 typedef enum {                                  /*!< GPIO_PINCFG42_NCESRC42                                                    */
54664   GPIO_PINCFG42_NCESRC42_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54665   GPIO_PINCFG42_NCESRC42_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54666   GPIO_PINCFG42_NCESRC42_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54667   GPIO_PINCFG42_NCESRC42_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54668   GPIO_PINCFG42_NCESRC42_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54669   GPIO_PINCFG42_NCESRC42_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54670   GPIO_PINCFG42_NCESRC42_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54671   GPIO_PINCFG42_NCESRC42_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54672   GPIO_PINCFG42_NCESRC42_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54673   GPIO_PINCFG42_NCESRC42_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54674   GPIO_PINCFG42_NCESRC42_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54675   GPIO_PINCFG42_NCESRC42_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54676   GPIO_PINCFG42_NCESRC42_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54677   GPIO_PINCFG42_NCESRC42_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54678   GPIO_PINCFG42_NCESRC42_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54679   GPIO_PINCFG42_NCESRC42_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54680   GPIO_PINCFG42_NCESRC42_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54681   GPIO_PINCFG42_NCESRC42_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54682   GPIO_PINCFG42_NCESRC42_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54683   GPIO_PINCFG42_NCESRC42_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54684   GPIO_PINCFG42_NCESRC42_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54685   GPIO_PINCFG42_NCESRC42_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54686   GPIO_PINCFG42_NCESRC42_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54687   GPIO_PINCFG42_NCESRC42_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54688   GPIO_PINCFG42_NCESRC42_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54689   GPIO_PINCFG42_NCESRC42_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54690   GPIO_PINCFG42_NCESRC42_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54691   GPIO_PINCFG42_NCESRC42_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54692   GPIO_PINCFG42_NCESRC42_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54693   GPIO_PINCFG42_NCESRC42_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54694   GPIO_PINCFG42_NCESRC42_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54695   GPIO_PINCFG42_NCESRC42_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54696   GPIO_PINCFG42_NCESRC42_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54697   GPIO_PINCFG42_NCESRC42_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54698   GPIO_PINCFG42_NCESRC42_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54699   GPIO_PINCFG42_NCESRC42_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54700   GPIO_PINCFG42_NCESRC42_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54701   GPIO_PINCFG42_NCESRC42_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54702   GPIO_PINCFG42_NCESRC42_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54703   GPIO_PINCFG42_NCESRC42_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54704   GPIO_PINCFG42_NCESRC42_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54705   GPIO_PINCFG42_NCESRC42_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54706   GPIO_PINCFG42_NCESRC42_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54707 } GPIO_PINCFG42_NCESRC42_Enum;
54708 
54709 /* ===========================================  GPIO PINCFG42 PULLCFG42 [13..15]  ============================================ */
54710 typedef enum {                                  /*!< GPIO_PINCFG42_PULLCFG42                                                   */
54711   GPIO_PINCFG42_PULLCFG42_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54712   GPIO_PINCFG42_PULLCFG42_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54713   GPIO_PINCFG42_PULLCFG42_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54714   GPIO_PINCFG42_PULLCFG42_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54715   GPIO_PINCFG42_PULLCFG42_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54716   GPIO_PINCFG42_PULLCFG42_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54717   GPIO_PINCFG42_PULLCFG42_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54718   GPIO_PINCFG42_PULLCFG42_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54719 } GPIO_PINCFG42_PULLCFG42_Enum;
54720 
54721 /* ==============================================  GPIO PINCFG42 DS42 [10..11]  ============================================== */
54722 typedef enum {                                  /*!< GPIO_PINCFG42_DS42                                                        */
54723   GPIO_PINCFG42_DS42_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54724   GPIO_PINCFG42_DS42_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54725   GPIO_PINCFG42_DS42_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54726   GPIO_PINCFG42_DS42_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54727 } GPIO_PINCFG42_DS42_Enum;
54728 
54729 /* =============================================  GPIO PINCFG42 OUTCFG42 [8..9]  ============================================= */
54730 typedef enum {                                  /*!< GPIO_PINCFG42_OUTCFG42                                                    */
54731   GPIO_PINCFG42_OUTCFG42_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54732   GPIO_PINCFG42_OUTCFG42_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54733                                                      and 1 values on pin.                                                      */
54734   GPIO_PINCFG42_OUTCFG42_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54735                                                      low, tristate otherwise.                                                  */
54736   GPIO_PINCFG42_OUTCFG42_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54737                                                      drive 0, 1 of HiZ on pin.                                                 */
54738 } GPIO_PINCFG42_OUTCFG42_Enum;
54739 
54740 /* =============================================  GPIO PINCFG42 IRPTEN42 [6..7]  ============================================= */
54741 typedef enum {                                  /*!< GPIO_PINCFG42_IRPTEN42                                                    */
54742   GPIO_PINCFG42_IRPTEN42_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54743   GPIO_PINCFG42_IRPTEN42_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54744                                                      on this GPIO                                                              */
54745   GPIO_PINCFG42_IRPTEN42_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54746                                                      on this GPIO                                                              */
54747   GPIO_PINCFG42_IRPTEN42_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54748                                                      GPIO                                                                      */
54749 } GPIO_PINCFG42_IRPTEN42_Enum;
54750 
54751 /* =============================================  GPIO PINCFG42 FNCSEL42 [0..3]  ============================================= */
54752 typedef enum {                                  /*!< GPIO_PINCFG42_FNCSEL42                                                    */
54753   GPIO_PINCFG42_FNCSEL42_MSPI1_5       = 0,     /*!< MSPI1_5 : MSPI Master 1 Interface Signal                                  */
54754   GPIO_PINCFG42_FNCSEL42_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
54755   GPIO_PINCFG42_FNCSEL42_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
54756   GPIO_PINCFG42_FNCSEL42_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54757   GPIO_PINCFG42_FNCSEL42_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
54758   GPIO_PINCFG42_FNCSEL42_DISP_D20      = 5,     /*!< DISP_D20 : Display Data 20                                                */
54759   GPIO_PINCFG42_FNCSEL42_CT42          = 6,     /*!< CT42 : Timer/Counter input or output; Selection of direction
54760                                                      is done via CTIMER register settings.                                     */
54761   GPIO_PINCFG42_FNCSEL42_NCE42         = 7,     /*!< NCE42 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54762                                                      CE_POLARITY field                                                         */
54763   GPIO_PINCFG42_FNCSEL42_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
54764   GPIO_PINCFG42_FNCSEL42_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54765   GPIO_PINCFG42_FNCSEL42_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54766   GPIO_PINCFG42_FNCSEL42_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54767   GPIO_PINCFG42_FNCSEL42_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54768   GPIO_PINCFG42_FNCSEL42_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54769   GPIO_PINCFG42_FNCSEL42_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54770   GPIO_PINCFG42_FNCSEL42_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54771 } GPIO_PINCFG42_FNCSEL42_Enum;
54772 
54773 /* =======================================================  PINCFG43  ======================================================== */
54774 /* ============================================  GPIO PINCFG43 NCEPOL43 [22..22]  ============================================ */
54775 typedef enum {                                  /*!< GPIO_PINCFG43_NCEPOL43                                                    */
54776   GPIO_PINCFG43_NCEPOL43_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54777   GPIO_PINCFG43_NCEPOL43_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54778 } GPIO_PINCFG43_NCEPOL43_Enum;
54779 
54780 /* ============================================  GPIO PINCFG43 NCESRC43 [16..21]  ============================================ */
54781 typedef enum {                                  /*!< GPIO_PINCFG43_NCESRC43                                                    */
54782   GPIO_PINCFG43_NCESRC43_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54783   GPIO_PINCFG43_NCESRC43_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54784   GPIO_PINCFG43_NCESRC43_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54785   GPIO_PINCFG43_NCESRC43_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54786   GPIO_PINCFG43_NCESRC43_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54787   GPIO_PINCFG43_NCESRC43_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54788   GPIO_PINCFG43_NCESRC43_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54789   GPIO_PINCFG43_NCESRC43_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54790   GPIO_PINCFG43_NCESRC43_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54791   GPIO_PINCFG43_NCESRC43_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54792   GPIO_PINCFG43_NCESRC43_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54793   GPIO_PINCFG43_NCESRC43_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54794   GPIO_PINCFG43_NCESRC43_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54795   GPIO_PINCFG43_NCESRC43_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54796   GPIO_PINCFG43_NCESRC43_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54797   GPIO_PINCFG43_NCESRC43_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54798   GPIO_PINCFG43_NCESRC43_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54799   GPIO_PINCFG43_NCESRC43_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54800   GPIO_PINCFG43_NCESRC43_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54801   GPIO_PINCFG43_NCESRC43_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54802   GPIO_PINCFG43_NCESRC43_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54803   GPIO_PINCFG43_NCESRC43_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54804   GPIO_PINCFG43_NCESRC43_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54805   GPIO_PINCFG43_NCESRC43_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54806   GPIO_PINCFG43_NCESRC43_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54807   GPIO_PINCFG43_NCESRC43_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54808   GPIO_PINCFG43_NCESRC43_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54809   GPIO_PINCFG43_NCESRC43_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54810   GPIO_PINCFG43_NCESRC43_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54811   GPIO_PINCFG43_NCESRC43_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54812   GPIO_PINCFG43_NCESRC43_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54813   GPIO_PINCFG43_NCESRC43_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54814   GPIO_PINCFG43_NCESRC43_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54815   GPIO_PINCFG43_NCESRC43_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54816   GPIO_PINCFG43_NCESRC43_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54817   GPIO_PINCFG43_NCESRC43_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54818   GPIO_PINCFG43_NCESRC43_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54819   GPIO_PINCFG43_NCESRC43_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54820   GPIO_PINCFG43_NCESRC43_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54821   GPIO_PINCFG43_NCESRC43_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54822   GPIO_PINCFG43_NCESRC43_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54823   GPIO_PINCFG43_NCESRC43_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54824   GPIO_PINCFG43_NCESRC43_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54825 } GPIO_PINCFG43_NCESRC43_Enum;
54826 
54827 /* ===========================================  GPIO PINCFG43 PULLCFG43 [13..15]  ============================================ */
54828 typedef enum {                                  /*!< GPIO_PINCFG43_PULLCFG43                                                   */
54829   GPIO_PINCFG43_PULLCFG43_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54830   GPIO_PINCFG43_PULLCFG43_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54831   GPIO_PINCFG43_PULLCFG43_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54832   GPIO_PINCFG43_PULLCFG43_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54833   GPIO_PINCFG43_PULLCFG43_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54834   GPIO_PINCFG43_PULLCFG43_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54835   GPIO_PINCFG43_PULLCFG43_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54836   GPIO_PINCFG43_PULLCFG43_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54837 } GPIO_PINCFG43_PULLCFG43_Enum;
54838 
54839 /* ==============================================  GPIO PINCFG43 DS43 [10..11]  ============================================== */
54840 typedef enum {                                  /*!< GPIO_PINCFG43_DS43                                                        */
54841   GPIO_PINCFG43_DS43_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54842   GPIO_PINCFG43_DS43_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54843   GPIO_PINCFG43_DS43_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54844   GPIO_PINCFG43_DS43_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54845 } GPIO_PINCFG43_DS43_Enum;
54846 
54847 /* =============================================  GPIO PINCFG43 OUTCFG43 [8..9]  ============================================= */
54848 typedef enum {                                  /*!< GPIO_PINCFG43_OUTCFG43                                                    */
54849   GPIO_PINCFG43_OUTCFG43_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54850   GPIO_PINCFG43_OUTCFG43_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54851                                                      and 1 values on pin.                                                      */
54852   GPIO_PINCFG43_OUTCFG43_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54853                                                      low, tristate otherwise.                                                  */
54854   GPIO_PINCFG43_OUTCFG43_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54855                                                      drive 0, 1 of HiZ on pin.                                                 */
54856 } GPIO_PINCFG43_OUTCFG43_Enum;
54857 
54858 /* =============================================  GPIO PINCFG43 IRPTEN43 [6..7]  ============================================= */
54859 typedef enum {                                  /*!< GPIO_PINCFG43_IRPTEN43                                                    */
54860   GPIO_PINCFG43_IRPTEN43_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54861   GPIO_PINCFG43_IRPTEN43_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54862                                                      on this GPIO                                                              */
54863   GPIO_PINCFG43_IRPTEN43_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54864                                                      on this GPIO                                                              */
54865   GPIO_PINCFG43_IRPTEN43_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54866                                                      GPIO                                                                      */
54867 } GPIO_PINCFG43_IRPTEN43_Enum;
54868 
54869 /* =============================================  GPIO PINCFG43 FNCSEL43 [0..3]  ============================================= */
54870 typedef enum {                                  /*!< GPIO_PINCFG43_FNCSEL43                                                    */
54871   GPIO_PINCFG43_FNCSEL43_MSPI1_6       = 0,     /*!< MSPI1_6 : MSPI Master 1 Interface Signal                                  */
54872   GPIO_PINCFG43_FNCSEL43_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
54873   GPIO_PINCFG43_FNCSEL43_SWTRACECTL    = 2,     /*!< SWTRACECTL : Serial Wire Debug Trace Control                              */
54874   GPIO_PINCFG43_FNCSEL43_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54875   GPIO_PINCFG43_FNCSEL43_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
54876   GPIO_PINCFG43_FNCSEL43_DISP_D21      = 5,     /*!< DISP_D21 : Display Data 21                                                */
54877   GPIO_PINCFG43_FNCSEL43_CT43          = 6,     /*!< CT43 : Timer/Counter input or output; Selection of direction
54878                                                      is done via CTIMER register settings.                                     */
54879   GPIO_PINCFG43_FNCSEL43_NCE43         = 7,     /*!< NCE43 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54880                                                      CE_POLARITY field                                                         */
54881   GPIO_PINCFG43_FNCSEL43_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
54882   GPIO_PINCFG43_FNCSEL43_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54883   GPIO_PINCFG43_FNCSEL43_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54884   GPIO_PINCFG43_FNCSEL43_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54885   GPIO_PINCFG43_FNCSEL43_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54886   GPIO_PINCFG43_FNCSEL43_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54887   GPIO_PINCFG43_FNCSEL43_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54888   GPIO_PINCFG43_FNCSEL43_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54889 } GPIO_PINCFG43_FNCSEL43_Enum;
54890 
54891 /* =======================================================  PINCFG44  ======================================================== */
54892 /* ============================================  GPIO PINCFG44 NCEPOL44 [22..22]  ============================================ */
54893 typedef enum {                                  /*!< GPIO_PINCFG44_NCEPOL44                                                    */
54894   GPIO_PINCFG44_NCEPOL44_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54895   GPIO_PINCFG44_NCEPOL44_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54896 } GPIO_PINCFG44_NCEPOL44_Enum;
54897 
54898 /* ============================================  GPIO PINCFG44 NCESRC44 [16..21]  ============================================ */
54899 typedef enum {                                  /*!< GPIO_PINCFG44_NCESRC44                                                    */
54900   GPIO_PINCFG44_NCESRC44_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54901   GPIO_PINCFG44_NCESRC44_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54902   GPIO_PINCFG44_NCESRC44_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54903   GPIO_PINCFG44_NCESRC44_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54904   GPIO_PINCFG44_NCESRC44_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54905   GPIO_PINCFG44_NCESRC44_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54906   GPIO_PINCFG44_NCESRC44_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54907   GPIO_PINCFG44_NCESRC44_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54908   GPIO_PINCFG44_NCESRC44_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54909   GPIO_PINCFG44_NCESRC44_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54910   GPIO_PINCFG44_NCESRC44_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54911   GPIO_PINCFG44_NCESRC44_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54912   GPIO_PINCFG44_NCESRC44_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54913   GPIO_PINCFG44_NCESRC44_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54914   GPIO_PINCFG44_NCESRC44_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54915   GPIO_PINCFG44_NCESRC44_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54916   GPIO_PINCFG44_NCESRC44_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54917   GPIO_PINCFG44_NCESRC44_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54918   GPIO_PINCFG44_NCESRC44_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54919   GPIO_PINCFG44_NCESRC44_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54920   GPIO_PINCFG44_NCESRC44_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54921   GPIO_PINCFG44_NCESRC44_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54922   GPIO_PINCFG44_NCESRC44_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54923   GPIO_PINCFG44_NCESRC44_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54924   GPIO_PINCFG44_NCESRC44_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54925   GPIO_PINCFG44_NCESRC44_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54926   GPIO_PINCFG44_NCESRC44_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54927   GPIO_PINCFG44_NCESRC44_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54928   GPIO_PINCFG44_NCESRC44_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54929   GPIO_PINCFG44_NCESRC44_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54930   GPIO_PINCFG44_NCESRC44_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54931   GPIO_PINCFG44_NCESRC44_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54932   GPIO_PINCFG44_NCESRC44_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54933   GPIO_PINCFG44_NCESRC44_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54934   GPIO_PINCFG44_NCESRC44_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54935   GPIO_PINCFG44_NCESRC44_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54936   GPIO_PINCFG44_NCESRC44_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54937   GPIO_PINCFG44_NCESRC44_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54938   GPIO_PINCFG44_NCESRC44_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54939   GPIO_PINCFG44_NCESRC44_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54940   GPIO_PINCFG44_NCESRC44_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54941   GPIO_PINCFG44_NCESRC44_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54942   GPIO_PINCFG44_NCESRC44_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54943 } GPIO_PINCFG44_NCESRC44_Enum;
54944 
54945 /* ===========================================  GPIO PINCFG44 PULLCFG44 [13..15]  ============================================ */
54946 typedef enum {                                  /*!< GPIO_PINCFG44_PULLCFG44                                                   */
54947   GPIO_PINCFG44_PULLCFG44_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54948   GPIO_PINCFG44_PULLCFG44_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54949   GPIO_PINCFG44_PULLCFG44_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54950   GPIO_PINCFG44_PULLCFG44_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54951   GPIO_PINCFG44_PULLCFG44_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54952   GPIO_PINCFG44_PULLCFG44_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54953   GPIO_PINCFG44_PULLCFG44_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54954   GPIO_PINCFG44_PULLCFG44_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54955 } GPIO_PINCFG44_PULLCFG44_Enum;
54956 
54957 /* ==============================================  GPIO PINCFG44 DS44 [10..11]  ============================================== */
54958 typedef enum {                                  /*!< GPIO_PINCFG44_DS44                                                        */
54959   GPIO_PINCFG44_DS44_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54960   GPIO_PINCFG44_DS44_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54961   GPIO_PINCFG44_DS44_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54962   GPIO_PINCFG44_DS44_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54963 } GPIO_PINCFG44_DS44_Enum;
54964 
54965 /* =============================================  GPIO PINCFG44 OUTCFG44 [8..9]  ============================================= */
54966 typedef enum {                                  /*!< GPIO_PINCFG44_OUTCFG44                                                    */
54967   GPIO_PINCFG44_OUTCFG44_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54968   GPIO_PINCFG44_OUTCFG44_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54969                                                      and 1 values on pin.                                                      */
54970   GPIO_PINCFG44_OUTCFG44_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54971                                                      low, tristate otherwise.                                                  */
54972   GPIO_PINCFG44_OUTCFG44_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54973                                                      drive 0, 1 of HiZ on pin.                                                 */
54974 } GPIO_PINCFG44_OUTCFG44_Enum;
54975 
54976 /* =============================================  GPIO PINCFG44 IRPTEN44 [6..7]  ============================================= */
54977 typedef enum {                                  /*!< GPIO_PINCFG44_IRPTEN44                                                    */
54978   GPIO_PINCFG44_IRPTEN44_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54979   GPIO_PINCFG44_IRPTEN44_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54980                                                      on this GPIO                                                              */
54981   GPIO_PINCFG44_IRPTEN44_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54982                                                      on this GPIO                                                              */
54983   GPIO_PINCFG44_IRPTEN44_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54984                                                      GPIO                                                                      */
54985 } GPIO_PINCFG44_IRPTEN44_Enum;
54986 
54987 /* =============================================  GPIO PINCFG44 FNCSEL44 [0..3]  ============================================= */
54988 typedef enum {                                  /*!< GPIO_PINCFG44_FNCSEL44                                                    */
54989   GPIO_PINCFG44_FNCSEL44_MSPI1_7       = 0,     /*!< MSPI1_7 : MSPI Master 1 Interface Signal                                  */
54990   GPIO_PINCFG44_FNCSEL44_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
54991   GPIO_PINCFG44_FNCSEL44_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
54992   GPIO_PINCFG44_FNCSEL44_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54993   GPIO_PINCFG44_FNCSEL44_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
54994   GPIO_PINCFG44_FNCSEL44_DISP_D22      = 5,     /*!< DISP_D22 : Display Data 22                                                */
54995   GPIO_PINCFG44_FNCSEL44_CT44          = 6,     /*!< CT44 : Timer/Counter input or output; Selection of direction
54996                                                      is done via CTIMER register settings.                                     */
54997   GPIO_PINCFG44_FNCSEL44_NCE44         = 7,     /*!< NCE44 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54998                                                      CE_POLARITY field                                                         */
54999   GPIO_PINCFG44_FNCSEL44_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
55000   GPIO_PINCFG44_FNCSEL44_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
55001   GPIO_PINCFG44_FNCSEL44_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55002   GPIO_PINCFG44_FNCSEL44_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55003   GPIO_PINCFG44_FNCSEL44_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55004   GPIO_PINCFG44_FNCSEL44_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55005   GPIO_PINCFG44_FNCSEL44_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55006   GPIO_PINCFG44_FNCSEL44_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55007 } GPIO_PINCFG44_FNCSEL44_Enum;
55008 
55009 /* =======================================================  PINCFG45  ======================================================== */
55010 /* ============================================  GPIO PINCFG45 NCEPOL45 [22..22]  ============================================ */
55011 typedef enum {                                  /*!< GPIO_PINCFG45_NCEPOL45                                                    */
55012   GPIO_PINCFG45_NCEPOL45_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55013   GPIO_PINCFG45_NCEPOL45_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55014 } GPIO_PINCFG45_NCEPOL45_Enum;
55015 
55016 /* ============================================  GPIO PINCFG45 NCESRC45 [16..21]  ============================================ */
55017 typedef enum {                                  /*!< GPIO_PINCFG45_NCESRC45                                                    */
55018   GPIO_PINCFG45_NCESRC45_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55019   GPIO_PINCFG45_NCESRC45_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55020   GPIO_PINCFG45_NCESRC45_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55021   GPIO_PINCFG45_NCESRC45_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55022   GPIO_PINCFG45_NCESRC45_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55023   GPIO_PINCFG45_NCESRC45_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55024   GPIO_PINCFG45_NCESRC45_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55025   GPIO_PINCFG45_NCESRC45_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55026   GPIO_PINCFG45_NCESRC45_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55027   GPIO_PINCFG45_NCESRC45_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55028   GPIO_PINCFG45_NCESRC45_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55029   GPIO_PINCFG45_NCESRC45_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55030   GPIO_PINCFG45_NCESRC45_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55031   GPIO_PINCFG45_NCESRC45_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55032   GPIO_PINCFG45_NCESRC45_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55033   GPIO_PINCFG45_NCESRC45_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55034   GPIO_PINCFG45_NCESRC45_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55035   GPIO_PINCFG45_NCESRC45_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55036   GPIO_PINCFG45_NCESRC45_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55037   GPIO_PINCFG45_NCESRC45_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55038   GPIO_PINCFG45_NCESRC45_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55039   GPIO_PINCFG45_NCESRC45_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55040   GPIO_PINCFG45_NCESRC45_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55041   GPIO_PINCFG45_NCESRC45_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55042   GPIO_PINCFG45_NCESRC45_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55043   GPIO_PINCFG45_NCESRC45_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55044   GPIO_PINCFG45_NCESRC45_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55045   GPIO_PINCFG45_NCESRC45_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55046   GPIO_PINCFG45_NCESRC45_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55047   GPIO_PINCFG45_NCESRC45_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55048   GPIO_PINCFG45_NCESRC45_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55049   GPIO_PINCFG45_NCESRC45_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55050   GPIO_PINCFG45_NCESRC45_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55051   GPIO_PINCFG45_NCESRC45_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55052   GPIO_PINCFG45_NCESRC45_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55053   GPIO_PINCFG45_NCESRC45_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55054   GPIO_PINCFG45_NCESRC45_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55055   GPIO_PINCFG45_NCESRC45_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55056   GPIO_PINCFG45_NCESRC45_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55057   GPIO_PINCFG45_NCESRC45_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55058   GPIO_PINCFG45_NCESRC45_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55059   GPIO_PINCFG45_NCESRC45_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55060   GPIO_PINCFG45_NCESRC45_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55061 } GPIO_PINCFG45_NCESRC45_Enum;
55062 
55063 /* ===========================================  GPIO PINCFG45 PULLCFG45 [13..15]  ============================================ */
55064 typedef enum {                                  /*!< GPIO_PINCFG45_PULLCFG45                                                   */
55065   GPIO_PINCFG45_PULLCFG45_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55066   GPIO_PINCFG45_PULLCFG45_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55067   GPIO_PINCFG45_PULLCFG45_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55068   GPIO_PINCFG45_PULLCFG45_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55069   GPIO_PINCFG45_PULLCFG45_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55070   GPIO_PINCFG45_PULLCFG45_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55071   GPIO_PINCFG45_PULLCFG45_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55072   GPIO_PINCFG45_PULLCFG45_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55073 } GPIO_PINCFG45_PULLCFG45_Enum;
55074 
55075 /* ==============================================  GPIO PINCFG45 DS45 [10..11]  ============================================== */
55076 typedef enum {                                  /*!< GPIO_PINCFG45_DS45                                                        */
55077   GPIO_PINCFG45_DS45_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55078   GPIO_PINCFG45_DS45_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55079   GPIO_PINCFG45_DS45_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55080   GPIO_PINCFG45_DS45_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55081 } GPIO_PINCFG45_DS45_Enum;
55082 
55083 /* =============================================  GPIO PINCFG45 OUTCFG45 [8..9]  ============================================= */
55084 typedef enum {                                  /*!< GPIO_PINCFG45_OUTCFG45                                                    */
55085   GPIO_PINCFG45_OUTCFG45_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55086   GPIO_PINCFG45_OUTCFG45_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55087                                                      and 1 values on pin.                                                      */
55088   GPIO_PINCFG45_OUTCFG45_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55089                                                      low, tristate otherwise.                                                  */
55090   GPIO_PINCFG45_OUTCFG45_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55091                                                      drive 0, 1 of HiZ on pin.                                                 */
55092 } GPIO_PINCFG45_OUTCFG45_Enum;
55093 
55094 /* =============================================  GPIO PINCFG45 IRPTEN45 [6..7]  ============================================= */
55095 typedef enum {                                  /*!< GPIO_PINCFG45_IRPTEN45                                                    */
55096   GPIO_PINCFG45_IRPTEN45_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55097   GPIO_PINCFG45_IRPTEN45_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55098                                                      on this GPIO                                                              */
55099   GPIO_PINCFG45_IRPTEN45_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55100                                                      on this GPIO                                                              */
55101   GPIO_PINCFG45_IRPTEN45_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55102                                                      GPIO                                                                      */
55103 } GPIO_PINCFG45_IRPTEN45_Enum;
55104 
55105 /* =============================================  GPIO PINCFG45 FNCSEL45 [0..3]  ============================================= */
55106 typedef enum {                                  /*!< GPIO_PINCFG45_FNCSEL45                                                    */
55107   GPIO_PINCFG45_FNCSEL45_MSPI1_8       = 0,     /*!< MSPI1_8 : MSPI Master 1 Interface Signal                                  */
55108   GPIO_PINCFG45_FNCSEL45_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
55109   GPIO_PINCFG45_FNCSEL45_32KHzXT       = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
55110   GPIO_PINCFG45_FNCSEL45_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55111   GPIO_PINCFG45_FNCSEL45_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
55112   GPIO_PINCFG45_FNCSEL45_DISP_D23      = 5,     /*!< DISP_D23 : Display Data 23                                                */
55113   GPIO_PINCFG45_FNCSEL45_CT45          = 6,     /*!< CT45 : Timer/Counter input or output; Selection of direction
55114                                                      is done via CTIMER register settings.                                     */
55115   GPIO_PINCFG45_FNCSEL45_NCE45         = 7,     /*!< NCE45 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55116                                                      CE_POLARITY field                                                         */
55117   GPIO_PINCFG45_FNCSEL45_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
55118   GPIO_PINCFG45_FNCSEL45_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55119   GPIO_PINCFG45_FNCSEL45_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55120   GPIO_PINCFG45_FNCSEL45_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55121   GPIO_PINCFG45_FNCSEL45_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55122   GPIO_PINCFG45_FNCSEL45_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55123   GPIO_PINCFG45_FNCSEL45_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55124   GPIO_PINCFG45_FNCSEL45_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55125 } GPIO_PINCFG45_FNCSEL45_Enum;
55126 
55127 /* =======================================================  PINCFG46  ======================================================== */
55128 /* ============================================  GPIO PINCFG46 NCEPOL46 [22..22]  ============================================ */
55129 typedef enum {                                  /*!< GPIO_PINCFG46_NCEPOL46                                                    */
55130   GPIO_PINCFG46_NCEPOL46_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55131   GPIO_PINCFG46_NCEPOL46_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55132 } GPIO_PINCFG46_NCEPOL46_Enum;
55133 
55134 /* ============================================  GPIO PINCFG46 NCESRC46 [16..21]  ============================================ */
55135 typedef enum {                                  /*!< GPIO_PINCFG46_NCESRC46                                                    */
55136   GPIO_PINCFG46_NCESRC46_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55137   GPIO_PINCFG46_NCESRC46_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55138   GPIO_PINCFG46_NCESRC46_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55139   GPIO_PINCFG46_NCESRC46_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55140   GPIO_PINCFG46_NCESRC46_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55141   GPIO_PINCFG46_NCESRC46_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55142   GPIO_PINCFG46_NCESRC46_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55143   GPIO_PINCFG46_NCESRC46_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55144   GPIO_PINCFG46_NCESRC46_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55145   GPIO_PINCFG46_NCESRC46_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55146   GPIO_PINCFG46_NCESRC46_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55147   GPIO_PINCFG46_NCESRC46_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55148   GPIO_PINCFG46_NCESRC46_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55149   GPIO_PINCFG46_NCESRC46_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55150   GPIO_PINCFG46_NCESRC46_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55151   GPIO_PINCFG46_NCESRC46_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55152   GPIO_PINCFG46_NCESRC46_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55153   GPIO_PINCFG46_NCESRC46_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55154   GPIO_PINCFG46_NCESRC46_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55155   GPIO_PINCFG46_NCESRC46_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55156   GPIO_PINCFG46_NCESRC46_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55157   GPIO_PINCFG46_NCESRC46_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55158   GPIO_PINCFG46_NCESRC46_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55159   GPIO_PINCFG46_NCESRC46_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55160   GPIO_PINCFG46_NCESRC46_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55161   GPIO_PINCFG46_NCESRC46_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55162   GPIO_PINCFG46_NCESRC46_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55163   GPIO_PINCFG46_NCESRC46_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55164   GPIO_PINCFG46_NCESRC46_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55165   GPIO_PINCFG46_NCESRC46_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55166   GPIO_PINCFG46_NCESRC46_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55167   GPIO_PINCFG46_NCESRC46_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55168   GPIO_PINCFG46_NCESRC46_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55169   GPIO_PINCFG46_NCESRC46_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55170   GPIO_PINCFG46_NCESRC46_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55171   GPIO_PINCFG46_NCESRC46_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55172   GPIO_PINCFG46_NCESRC46_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55173   GPIO_PINCFG46_NCESRC46_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55174   GPIO_PINCFG46_NCESRC46_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55175   GPIO_PINCFG46_NCESRC46_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55176   GPIO_PINCFG46_NCESRC46_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55177   GPIO_PINCFG46_NCESRC46_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55178   GPIO_PINCFG46_NCESRC46_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55179 } GPIO_PINCFG46_NCESRC46_Enum;
55180 
55181 /* ===========================================  GPIO PINCFG46 PULLCFG46 [13..15]  ============================================ */
55182 typedef enum {                                  /*!< GPIO_PINCFG46_PULLCFG46                                                   */
55183   GPIO_PINCFG46_PULLCFG46_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55184   GPIO_PINCFG46_PULLCFG46_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55185   GPIO_PINCFG46_PULLCFG46_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55186   GPIO_PINCFG46_PULLCFG46_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55187   GPIO_PINCFG46_PULLCFG46_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55188   GPIO_PINCFG46_PULLCFG46_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55189   GPIO_PINCFG46_PULLCFG46_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55190   GPIO_PINCFG46_PULLCFG46_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55191 } GPIO_PINCFG46_PULLCFG46_Enum;
55192 
55193 /* ==============================================  GPIO PINCFG46 DS46 [10..11]  ============================================== */
55194 typedef enum {                                  /*!< GPIO_PINCFG46_DS46                                                        */
55195   GPIO_PINCFG46_DS46_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55196   GPIO_PINCFG46_DS46_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55197   GPIO_PINCFG46_DS46_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55198   GPIO_PINCFG46_DS46_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55199 } GPIO_PINCFG46_DS46_Enum;
55200 
55201 /* =============================================  GPIO PINCFG46 OUTCFG46 [8..9]  ============================================= */
55202 typedef enum {                                  /*!< GPIO_PINCFG46_OUTCFG46                                                    */
55203   GPIO_PINCFG46_OUTCFG46_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55204   GPIO_PINCFG46_OUTCFG46_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55205                                                      and 1 values on pin.                                                      */
55206   GPIO_PINCFG46_OUTCFG46_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55207                                                      low, tristate otherwise.                                                  */
55208   GPIO_PINCFG46_OUTCFG46_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55209                                                      drive 0, 1 of HiZ on pin.                                                 */
55210 } GPIO_PINCFG46_OUTCFG46_Enum;
55211 
55212 /* =============================================  GPIO PINCFG46 IRPTEN46 [6..7]  ============================================= */
55213 typedef enum {                                  /*!< GPIO_PINCFG46_IRPTEN46                                                    */
55214   GPIO_PINCFG46_IRPTEN46_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55215   GPIO_PINCFG46_IRPTEN46_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55216                                                      on this GPIO                                                              */
55217   GPIO_PINCFG46_IRPTEN46_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55218                                                      on this GPIO                                                              */
55219   GPIO_PINCFG46_IRPTEN46_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55220                                                      GPIO                                                                      */
55221 } GPIO_PINCFG46_IRPTEN46_Enum;
55222 
55223 /* =============================================  GPIO PINCFG46 FNCSEL46 [0..3]  ============================================= */
55224 typedef enum {                                  /*!< GPIO_PINCFG46_FNCSEL46                                                    */
55225   GPIO_PINCFG46_FNCSEL46_MSPI1_9       = 0,     /*!< MSPI1_9 : MSPI Master 1 Interface Signal                                  */
55226   GPIO_PINCFG46_FNCSEL46_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
55227   GPIO_PINCFG46_FNCSEL46_CLKOUT_32M    = 2,     /*!< CLKOUT_32M : 32MHz Oscillator output clock                                */
55228   GPIO_PINCFG46_FNCSEL46_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55229   GPIO_PINCFG46_FNCSEL46_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
55230   GPIO_PINCFG46_FNCSEL46_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
55231   GPIO_PINCFG46_FNCSEL46_CT46          = 6,     /*!< CT46 : Timer/Counter input or output; Selection of direction
55232                                                      is done via CTIMER register settings.                                     */
55233   GPIO_PINCFG46_FNCSEL46_NCE46         = 7,     /*!< NCE46 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55234                                                      CE_POLARITY field                                                         */
55235   GPIO_PINCFG46_FNCSEL46_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
55236   GPIO_PINCFG46_FNCSEL46_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
55237   GPIO_PINCFG46_FNCSEL46_I2S0_SDIN     = 10,    /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
55238   GPIO_PINCFG46_FNCSEL46_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55239   GPIO_PINCFG46_FNCSEL46_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55240   GPIO_PINCFG46_FNCSEL46_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55241   GPIO_PINCFG46_FNCSEL46_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55242   GPIO_PINCFG46_FNCSEL46_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55243 } GPIO_PINCFG46_FNCSEL46_Enum;
55244 
55245 /* =======================================================  PINCFG47  ======================================================== */
55246 /* ============================================  GPIO PINCFG47 NCEPOL47 [22..22]  ============================================ */
55247 typedef enum {                                  /*!< GPIO_PINCFG47_NCEPOL47                                                    */
55248   GPIO_PINCFG47_NCEPOL47_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55249   GPIO_PINCFG47_NCEPOL47_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55250 } GPIO_PINCFG47_NCEPOL47_Enum;
55251 
55252 /* ============================================  GPIO PINCFG47 NCESRC47 [16..21]  ============================================ */
55253 typedef enum {                                  /*!< GPIO_PINCFG47_NCESRC47                                                    */
55254   GPIO_PINCFG47_NCESRC47_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55255   GPIO_PINCFG47_NCESRC47_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55256   GPIO_PINCFG47_NCESRC47_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55257   GPIO_PINCFG47_NCESRC47_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55258   GPIO_PINCFG47_NCESRC47_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55259   GPIO_PINCFG47_NCESRC47_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55260   GPIO_PINCFG47_NCESRC47_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55261   GPIO_PINCFG47_NCESRC47_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55262   GPIO_PINCFG47_NCESRC47_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55263   GPIO_PINCFG47_NCESRC47_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55264   GPIO_PINCFG47_NCESRC47_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55265   GPIO_PINCFG47_NCESRC47_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55266   GPIO_PINCFG47_NCESRC47_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55267   GPIO_PINCFG47_NCESRC47_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55268   GPIO_PINCFG47_NCESRC47_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55269   GPIO_PINCFG47_NCESRC47_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55270   GPIO_PINCFG47_NCESRC47_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55271   GPIO_PINCFG47_NCESRC47_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55272   GPIO_PINCFG47_NCESRC47_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55273   GPIO_PINCFG47_NCESRC47_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55274   GPIO_PINCFG47_NCESRC47_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55275   GPIO_PINCFG47_NCESRC47_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55276   GPIO_PINCFG47_NCESRC47_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55277   GPIO_PINCFG47_NCESRC47_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55278   GPIO_PINCFG47_NCESRC47_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55279   GPIO_PINCFG47_NCESRC47_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55280   GPIO_PINCFG47_NCESRC47_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55281   GPIO_PINCFG47_NCESRC47_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55282   GPIO_PINCFG47_NCESRC47_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55283   GPIO_PINCFG47_NCESRC47_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55284   GPIO_PINCFG47_NCESRC47_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55285   GPIO_PINCFG47_NCESRC47_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55286   GPIO_PINCFG47_NCESRC47_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55287   GPIO_PINCFG47_NCESRC47_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55288   GPIO_PINCFG47_NCESRC47_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55289   GPIO_PINCFG47_NCESRC47_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55290   GPIO_PINCFG47_NCESRC47_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55291   GPIO_PINCFG47_NCESRC47_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55292   GPIO_PINCFG47_NCESRC47_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55293   GPIO_PINCFG47_NCESRC47_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55294   GPIO_PINCFG47_NCESRC47_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55295   GPIO_PINCFG47_NCESRC47_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55296   GPIO_PINCFG47_NCESRC47_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55297 } GPIO_PINCFG47_NCESRC47_Enum;
55298 
55299 /* ===========================================  GPIO PINCFG47 PULLCFG47 [13..15]  ============================================ */
55300 typedef enum {                                  /*!< GPIO_PINCFG47_PULLCFG47                                                   */
55301   GPIO_PINCFG47_PULLCFG47_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55302   GPIO_PINCFG47_PULLCFG47_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55303   GPIO_PINCFG47_PULLCFG47_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55304   GPIO_PINCFG47_PULLCFG47_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55305   GPIO_PINCFG47_PULLCFG47_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55306   GPIO_PINCFG47_PULLCFG47_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55307   GPIO_PINCFG47_PULLCFG47_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55308   GPIO_PINCFG47_PULLCFG47_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55309 } GPIO_PINCFG47_PULLCFG47_Enum;
55310 
55311 /* ==============================================  GPIO PINCFG47 DS47 [10..11]  ============================================== */
55312 typedef enum {                                  /*!< GPIO_PINCFG47_DS47                                                        */
55313   GPIO_PINCFG47_DS47_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55314   GPIO_PINCFG47_DS47_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55315   GPIO_PINCFG47_DS47_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55316   GPIO_PINCFG47_DS47_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55317 } GPIO_PINCFG47_DS47_Enum;
55318 
55319 /* =============================================  GPIO PINCFG47 OUTCFG47 [8..9]  ============================================= */
55320 typedef enum {                                  /*!< GPIO_PINCFG47_OUTCFG47                                                    */
55321   GPIO_PINCFG47_OUTCFG47_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55322   GPIO_PINCFG47_OUTCFG47_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55323                                                      and 1 values on pin.                                                      */
55324   GPIO_PINCFG47_OUTCFG47_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55325                                                      low, tristate otherwise.                                                  */
55326   GPIO_PINCFG47_OUTCFG47_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55327                                                      drive 0, 1 of HiZ on pin.                                                 */
55328 } GPIO_PINCFG47_OUTCFG47_Enum;
55329 
55330 /* =============================================  GPIO PINCFG47 IRPTEN47 [6..7]  ============================================= */
55331 typedef enum {                                  /*!< GPIO_PINCFG47_IRPTEN47                                                    */
55332   GPIO_PINCFG47_IRPTEN47_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55333   GPIO_PINCFG47_IRPTEN47_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55334                                                      on this GPIO                                                              */
55335   GPIO_PINCFG47_IRPTEN47_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55336                                                      on this GPIO                                                              */
55337   GPIO_PINCFG47_IRPTEN47_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55338                                                      GPIO                                                                      */
55339 } GPIO_PINCFG47_IRPTEN47_Enum;
55340 
55341 /* =============================================  GPIO PINCFG47 FNCSEL47 [0..3]  ============================================= */
55342 typedef enum {                                  /*!< GPIO_PINCFG47_FNCSEL47                                                    */
55343   GPIO_PINCFG47_FNCSEL47_M5SCL         = 0,     /*!< M5SCL : Serial I2C Master Clock output (IOM 5)                            */
55344   GPIO_PINCFG47_FNCSEL47_M5SCK         = 1,     /*!< M5SCK : Serial SPI Master Clock output (IOM 5)                            */
55345   GPIO_PINCFG47_FNCSEL47_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
55346                                                      in master mode and input mode for slave mode. (I2S Master/Slave
55347                                                      2)                                                                        */
55348   GPIO_PINCFG47_FNCSEL47_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55349   GPIO_PINCFG47_FNCSEL47_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
55350   GPIO_PINCFG47_FNCSEL47_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
55351   GPIO_PINCFG47_FNCSEL47_CT47          = 6,     /*!< CT47 : Timer/Counter input or output; Selection of direction
55352                                                      is done via CTIMER register settings.                                     */
55353   GPIO_PINCFG47_FNCSEL47_NCE47         = 7,     /*!< NCE47 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55354                                                      CE_POLARITY field                                                         */
55355   GPIO_PINCFG47_FNCSEL47_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
55356   GPIO_PINCFG47_FNCSEL47_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55357   GPIO_PINCFG47_FNCSEL47_I2S0_CLK      = 10,    /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
55358                                                      in master mode and input mode for slave mode. (I2S Master/Slave
55359                                                      2)                                                                        */
55360   GPIO_PINCFG47_FNCSEL47_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55361   GPIO_PINCFG47_FNCSEL47_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55362   GPIO_PINCFG47_FNCSEL47_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55363   GPIO_PINCFG47_FNCSEL47_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55364   GPIO_PINCFG47_FNCSEL47_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55365 } GPIO_PINCFG47_FNCSEL47_Enum;
55366 
55367 /* =======================================================  PINCFG48  ======================================================== */
55368 /* ============================================  GPIO PINCFG48 NCEPOL48 [22..22]  ============================================ */
55369 typedef enum {                                  /*!< GPIO_PINCFG48_NCEPOL48                                                    */
55370   GPIO_PINCFG48_NCEPOL48_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55371   GPIO_PINCFG48_NCEPOL48_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55372 } GPIO_PINCFG48_NCEPOL48_Enum;
55373 
55374 /* ============================================  GPIO PINCFG48 NCESRC48 [16..21]  ============================================ */
55375 typedef enum {                                  /*!< GPIO_PINCFG48_NCESRC48                                                    */
55376   GPIO_PINCFG48_NCESRC48_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55377   GPIO_PINCFG48_NCESRC48_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55378   GPIO_PINCFG48_NCESRC48_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55379   GPIO_PINCFG48_NCESRC48_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55380   GPIO_PINCFG48_NCESRC48_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55381   GPIO_PINCFG48_NCESRC48_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55382   GPIO_PINCFG48_NCESRC48_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55383   GPIO_PINCFG48_NCESRC48_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55384   GPIO_PINCFG48_NCESRC48_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55385   GPIO_PINCFG48_NCESRC48_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55386   GPIO_PINCFG48_NCESRC48_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55387   GPIO_PINCFG48_NCESRC48_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55388   GPIO_PINCFG48_NCESRC48_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55389   GPIO_PINCFG48_NCESRC48_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55390   GPIO_PINCFG48_NCESRC48_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55391   GPIO_PINCFG48_NCESRC48_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55392   GPIO_PINCFG48_NCESRC48_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55393   GPIO_PINCFG48_NCESRC48_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55394   GPIO_PINCFG48_NCESRC48_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55395   GPIO_PINCFG48_NCESRC48_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55396   GPIO_PINCFG48_NCESRC48_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55397   GPIO_PINCFG48_NCESRC48_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55398   GPIO_PINCFG48_NCESRC48_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55399   GPIO_PINCFG48_NCESRC48_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55400   GPIO_PINCFG48_NCESRC48_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55401   GPIO_PINCFG48_NCESRC48_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55402   GPIO_PINCFG48_NCESRC48_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55403   GPIO_PINCFG48_NCESRC48_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55404   GPIO_PINCFG48_NCESRC48_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55405   GPIO_PINCFG48_NCESRC48_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55406   GPIO_PINCFG48_NCESRC48_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55407   GPIO_PINCFG48_NCESRC48_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55408   GPIO_PINCFG48_NCESRC48_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55409   GPIO_PINCFG48_NCESRC48_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55410   GPIO_PINCFG48_NCESRC48_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55411   GPIO_PINCFG48_NCESRC48_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55412   GPIO_PINCFG48_NCESRC48_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55413   GPIO_PINCFG48_NCESRC48_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55414   GPIO_PINCFG48_NCESRC48_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55415   GPIO_PINCFG48_NCESRC48_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55416   GPIO_PINCFG48_NCESRC48_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55417   GPIO_PINCFG48_NCESRC48_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55418   GPIO_PINCFG48_NCESRC48_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55419 } GPIO_PINCFG48_NCESRC48_Enum;
55420 
55421 /* ===========================================  GPIO PINCFG48 PULLCFG48 [13..15]  ============================================ */
55422 typedef enum {                                  /*!< GPIO_PINCFG48_PULLCFG48                                                   */
55423   GPIO_PINCFG48_PULLCFG48_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55424   GPIO_PINCFG48_PULLCFG48_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55425   GPIO_PINCFG48_PULLCFG48_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55426   GPIO_PINCFG48_PULLCFG48_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55427   GPIO_PINCFG48_PULLCFG48_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55428   GPIO_PINCFG48_PULLCFG48_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55429   GPIO_PINCFG48_PULLCFG48_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55430   GPIO_PINCFG48_PULLCFG48_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55431 } GPIO_PINCFG48_PULLCFG48_Enum;
55432 
55433 /* ==============================================  GPIO PINCFG48 DS48 [10..11]  ============================================== */
55434 typedef enum {                                  /*!< GPIO_PINCFG48_DS48                                                        */
55435   GPIO_PINCFG48_DS48_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55436   GPIO_PINCFG48_DS48_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55437   GPIO_PINCFG48_DS48_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55438   GPIO_PINCFG48_DS48_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55439 } GPIO_PINCFG48_DS48_Enum;
55440 
55441 /* =============================================  GPIO PINCFG48 OUTCFG48 [8..9]  ============================================= */
55442 typedef enum {                                  /*!< GPIO_PINCFG48_OUTCFG48                                                    */
55443   GPIO_PINCFG48_OUTCFG48_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55444   GPIO_PINCFG48_OUTCFG48_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55445                                                      and 1 values on pin.                                                      */
55446   GPIO_PINCFG48_OUTCFG48_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55447                                                      low, tristate otherwise.                                                  */
55448   GPIO_PINCFG48_OUTCFG48_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55449                                                      drive 0, 1 of HiZ on pin.                                                 */
55450 } GPIO_PINCFG48_OUTCFG48_Enum;
55451 
55452 /* =============================================  GPIO PINCFG48 IRPTEN48 [6..7]  ============================================= */
55453 typedef enum {                                  /*!< GPIO_PINCFG48_IRPTEN48                                                    */
55454   GPIO_PINCFG48_IRPTEN48_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55455   GPIO_PINCFG48_IRPTEN48_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55456                                                      on this GPIO                                                              */
55457   GPIO_PINCFG48_IRPTEN48_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55458                                                      on this GPIO                                                              */
55459   GPIO_PINCFG48_IRPTEN48_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55460                                                      GPIO                                                                      */
55461 } GPIO_PINCFG48_IRPTEN48_Enum;
55462 
55463 /* =============================================  GPIO PINCFG48 FNCSEL48 [0..3]  ============================================= */
55464 typedef enum {                                  /*!< GPIO_PINCFG48_FNCSEL48                                                    */
55465   GPIO_PINCFG48_FNCSEL48_M5SDAWIR3     = 0,     /*!< M5SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
55466                                                      Master Data I/O (SPI 3 wire mode) (IOM 5)                                 */
55467   GPIO_PINCFG48_FNCSEL48_M5MOSI        = 1,     /*!< M5MOSI : Serial SPI Master MOSI output (IOM 5)                            */
55468   GPIO_PINCFG48_FNCSEL48_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
55469                                                      in master mode and input mode for slave mode. (I2S Master/Slave
55470                                                      2)                                                                        */
55471   GPIO_PINCFG48_FNCSEL48_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55472   GPIO_PINCFG48_FNCSEL48_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
55473   GPIO_PINCFG48_FNCSEL48_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
55474   GPIO_PINCFG48_FNCSEL48_CT48          = 6,     /*!< CT48 : Timer/Counter input or output; Selection of direction
55475                                                      is done via CTIMER register settings.                                     */
55476   GPIO_PINCFG48_FNCSEL48_NCE48         = 7,     /*!< NCE48 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55477                                                      CE_POLARITY field                                                         */
55478   GPIO_PINCFG48_FNCSEL48_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
55479   GPIO_PINCFG48_FNCSEL48_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
55480   GPIO_PINCFG48_FNCSEL48_I2S0_SDOUT    = 10,    /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
55481   GPIO_PINCFG48_FNCSEL48_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55482   GPIO_PINCFG48_FNCSEL48_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55483   GPIO_PINCFG48_FNCSEL48_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55484   GPIO_PINCFG48_FNCSEL48_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55485   GPIO_PINCFG48_FNCSEL48_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55486 } GPIO_PINCFG48_FNCSEL48_Enum;
55487 
55488 /* =======================================================  PINCFG49  ======================================================== */
55489 /* ============================================  GPIO PINCFG49 NCEPOL49 [22..22]  ============================================ */
55490 typedef enum {                                  /*!< GPIO_PINCFG49_NCEPOL49                                                    */
55491   GPIO_PINCFG49_NCEPOL49_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55492   GPIO_PINCFG49_NCEPOL49_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55493 } GPIO_PINCFG49_NCEPOL49_Enum;
55494 
55495 /* ============================================  GPIO PINCFG49 NCESRC49 [16..21]  ============================================ */
55496 typedef enum {                                  /*!< GPIO_PINCFG49_NCESRC49                                                    */
55497   GPIO_PINCFG49_NCESRC49_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55498   GPIO_PINCFG49_NCESRC49_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55499   GPIO_PINCFG49_NCESRC49_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55500   GPIO_PINCFG49_NCESRC49_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55501   GPIO_PINCFG49_NCESRC49_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55502   GPIO_PINCFG49_NCESRC49_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55503   GPIO_PINCFG49_NCESRC49_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55504   GPIO_PINCFG49_NCESRC49_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55505   GPIO_PINCFG49_NCESRC49_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55506   GPIO_PINCFG49_NCESRC49_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55507   GPIO_PINCFG49_NCESRC49_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55508   GPIO_PINCFG49_NCESRC49_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55509   GPIO_PINCFG49_NCESRC49_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55510   GPIO_PINCFG49_NCESRC49_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55511   GPIO_PINCFG49_NCESRC49_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55512   GPIO_PINCFG49_NCESRC49_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55513   GPIO_PINCFG49_NCESRC49_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55514   GPIO_PINCFG49_NCESRC49_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55515   GPIO_PINCFG49_NCESRC49_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55516   GPIO_PINCFG49_NCESRC49_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55517   GPIO_PINCFG49_NCESRC49_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55518   GPIO_PINCFG49_NCESRC49_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55519   GPIO_PINCFG49_NCESRC49_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55520   GPIO_PINCFG49_NCESRC49_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55521   GPIO_PINCFG49_NCESRC49_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55522   GPIO_PINCFG49_NCESRC49_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55523   GPIO_PINCFG49_NCESRC49_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55524   GPIO_PINCFG49_NCESRC49_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55525   GPIO_PINCFG49_NCESRC49_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55526   GPIO_PINCFG49_NCESRC49_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55527   GPIO_PINCFG49_NCESRC49_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55528   GPIO_PINCFG49_NCESRC49_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55529   GPIO_PINCFG49_NCESRC49_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55530   GPIO_PINCFG49_NCESRC49_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55531   GPIO_PINCFG49_NCESRC49_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55532   GPIO_PINCFG49_NCESRC49_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55533   GPIO_PINCFG49_NCESRC49_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55534   GPIO_PINCFG49_NCESRC49_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55535   GPIO_PINCFG49_NCESRC49_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55536   GPIO_PINCFG49_NCESRC49_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55537   GPIO_PINCFG49_NCESRC49_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55538   GPIO_PINCFG49_NCESRC49_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55539   GPIO_PINCFG49_NCESRC49_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55540 } GPIO_PINCFG49_NCESRC49_Enum;
55541 
55542 /* ===========================================  GPIO PINCFG49 PULLCFG49 [13..15]  ============================================ */
55543 typedef enum {                                  /*!< GPIO_PINCFG49_PULLCFG49                                                   */
55544   GPIO_PINCFG49_PULLCFG49_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55545   GPIO_PINCFG49_PULLCFG49_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55546   GPIO_PINCFG49_PULLCFG49_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55547   GPIO_PINCFG49_PULLCFG49_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55548   GPIO_PINCFG49_PULLCFG49_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55549   GPIO_PINCFG49_PULLCFG49_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55550   GPIO_PINCFG49_PULLCFG49_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55551   GPIO_PINCFG49_PULLCFG49_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55552 } GPIO_PINCFG49_PULLCFG49_Enum;
55553 
55554 /* ==============================================  GPIO PINCFG49 DS49 [10..11]  ============================================== */
55555 typedef enum {                                  /*!< GPIO_PINCFG49_DS49                                                        */
55556   GPIO_PINCFG49_DS49_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55557   GPIO_PINCFG49_DS49_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55558   GPIO_PINCFG49_DS49_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55559   GPIO_PINCFG49_DS49_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55560 } GPIO_PINCFG49_DS49_Enum;
55561 
55562 /* =============================================  GPIO PINCFG49 OUTCFG49 [8..9]  ============================================= */
55563 typedef enum {                                  /*!< GPIO_PINCFG49_OUTCFG49                                                    */
55564   GPIO_PINCFG49_OUTCFG49_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55565   GPIO_PINCFG49_OUTCFG49_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55566                                                      and 1 values on pin.                                                      */
55567   GPIO_PINCFG49_OUTCFG49_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55568                                                      low, tristate otherwise.                                                  */
55569   GPIO_PINCFG49_OUTCFG49_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55570                                                      drive 0, 1 of HiZ on pin.                                                 */
55571 } GPIO_PINCFG49_OUTCFG49_Enum;
55572 
55573 /* =============================================  GPIO PINCFG49 IRPTEN49 [6..7]  ============================================= */
55574 typedef enum {                                  /*!< GPIO_PINCFG49_IRPTEN49                                                    */
55575   GPIO_PINCFG49_IRPTEN49_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55576   GPIO_PINCFG49_IRPTEN49_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55577                                                      on this GPIO                                                              */
55578   GPIO_PINCFG49_IRPTEN49_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55579                                                      on this GPIO                                                              */
55580   GPIO_PINCFG49_IRPTEN49_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55581                                                      GPIO                                                                      */
55582 } GPIO_PINCFG49_IRPTEN49_Enum;
55583 
55584 /* =============================================  GPIO PINCFG49 FNCSEL49 [0..3]  ============================================= */
55585 typedef enum {                                  /*!< GPIO_PINCFG49_FNCSEL49                                                    */
55586   GPIO_PINCFG49_FNCSEL49_M5MISO        = 0,     /*!< M5MISO : Serial SPI MASTER MISO input (IOM 5)                             */
55587   GPIO_PINCFG49_FNCSEL49_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
55588   GPIO_PINCFG49_FNCSEL49_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
55589                                                      in master mode and input mode for slave mode. (I2S Master/Slave
55590                                                      2)                                                                        */
55591   GPIO_PINCFG49_FNCSEL49_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55592   GPIO_PINCFG49_FNCSEL49_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
55593   GPIO_PINCFG49_FNCSEL49_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
55594   GPIO_PINCFG49_FNCSEL49_CT49          = 6,     /*!< CT49 : Timer/Counter input or output; Selection of direction
55595                                                      is done via CTIMER register settings.                                     */
55596   GPIO_PINCFG49_FNCSEL49_NCE49         = 7,     /*!< NCE49 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55597                                                      CE_POLARITY field                                                         */
55598   GPIO_PINCFG49_FNCSEL49_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
55599   GPIO_PINCFG49_FNCSEL49_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55600   GPIO_PINCFG49_FNCSEL49_I2S0_WS       = 10,    /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
55601                                                      in master mode and input mode for slave mode. (I2S Master/Slave
55602                                                      2)                                                                        */
55603   GPIO_PINCFG49_FNCSEL49_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55604   GPIO_PINCFG49_FNCSEL49_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55605   GPIO_PINCFG49_FNCSEL49_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55606   GPIO_PINCFG49_FNCSEL49_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55607   GPIO_PINCFG49_FNCSEL49_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55608 } GPIO_PINCFG49_FNCSEL49_Enum;
55609 
55610 /* =======================================================  PINCFG50  ======================================================== */
55611 /* ============================================  GPIO PINCFG50 NCEPOL50 [22..22]  ============================================ */
55612 typedef enum {                                  /*!< GPIO_PINCFG50_NCEPOL50                                                    */
55613   GPIO_PINCFG50_NCEPOL50_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55614   GPIO_PINCFG50_NCEPOL50_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55615 } GPIO_PINCFG50_NCEPOL50_Enum;
55616 
55617 /* ============================================  GPIO PINCFG50 NCESRC50 [16..21]  ============================================ */
55618 typedef enum {                                  /*!< GPIO_PINCFG50_NCESRC50                                                    */
55619   GPIO_PINCFG50_NCESRC50_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55620   GPIO_PINCFG50_NCESRC50_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55621   GPIO_PINCFG50_NCESRC50_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55622   GPIO_PINCFG50_NCESRC50_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55623   GPIO_PINCFG50_NCESRC50_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55624   GPIO_PINCFG50_NCESRC50_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55625   GPIO_PINCFG50_NCESRC50_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55626   GPIO_PINCFG50_NCESRC50_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55627   GPIO_PINCFG50_NCESRC50_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55628   GPIO_PINCFG50_NCESRC50_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55629   GPIO_PINCFG50_NCESRC50_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55630   GPIO_PINCFG50_NCESRC50_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55631   GPIO_PINCFG50_NCESRC50_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55632   GPIO_PINCFG50_NCESRC50_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55633   GPIO_PINCFG50_NCESRC50_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55634   GPIO_PINCFG50_NCESRC50_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55635   GPIO_PINCFG50_NCESRC50_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55636   GPIO_PINCFG50_NCESRC50_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55637   GPIO_PINCFG50_NCESRC50_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55638   GPIO_PINCFG50_NCESRC50_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55639   GPIO_PINCFG50_NCESRC50_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55640   GPIO_PINCFG50_NCESRC50_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55641   GPIO_PINCFG50_NCESRC50_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55642   GPIO_PINCFG50_NCESRC50_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55643   GPIO_PINCFG50_NCESRC50_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55644   GPIO_PINCFG50_NCESRC50_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55645   GPIO_PINCFG50_NCESRC50_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55646   GPIO_PINCFG50_NCESRC50_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55647   GPIO_PINCFG50_NCESRC50_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55648   GPIO_PINCFG50_NCESRC50_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55649   GPIO_PINCFG50_NCESRC50_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55650   GPIO_PINCFG50_NCESRC50_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55651   GPIO_PINCFG50_NCESRC50_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55652   GPIO_PINCFG50_NCESRC50_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55653   GPIO_PINCFG50_NCESRC50_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55654   GPIO_PINCFG50_NCESRC50_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55655   GPIO_PINCFG50_NCESRC50_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55656   GPIO_PINCFG50_NCESRC50_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55657   GPIO_PINCFG50_NCESRC50_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55658   GPIO_PINCFG50_NCESRC50_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55659   GPIO_PINCFG50_NCESRC50_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55660   GPIO_PINCFG50_NCESRC50_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55661   GPIO_PINCFG50_NCESRC50_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55662 } GPIO_PINCFG50_NCESRC50_Enum;
55663 
55664 /* ===========================================  GPIO PINCFG50 PULLCFG50 [13..15]  ============================================ */
55665 typedef enum {                                  /*!< GPIO_PINCFG50_PULLCFG50                                                   */
55666   GPIO_PINCFG50_PULLCFG50_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55667   GPIO_PINCFG50_PULLCFG50_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55668   GPIO_PINCFG50_PULLCFG50_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55669   GPIO_PINCFG50_PULLCFG50_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55670   GPIO_PINCFG50_PULLCFG50_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55671   GPIO_PINCFG50_PULLCFG50_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55672   GPIO_PINCFG50_PULLCFG50_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55673   GPIO_PINCFG50_PULLCFG50_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55674 } GPIO_PINCFG50_PULLCFG50_Enum;
55675 
55676 /* ==============================================  GPIO PINCFG50 DS50 [10..11]  ============================================== */
55677 typedef enum {                                  /*!< GPIO_PINCFG50_DS50                                                        */
55678   GPIO_PINCFG50_DS50_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55679   GPIO_PINCFG50_DS50_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55680 } GPIO_PINCFG50_DS50_Enum;
55681 
55682 /* =============================================  GPIO PINCFG50 OUTCFG50 [8..9]  ============================================= */
55683 typedef enum {                                  /*!< GPIO_PINCFG50_OUTCFG50                                                    */
55684   GPIO_PINCFG50_OUTCFG50_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55685   GPIO_PINCFG50_OUTCFG50_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55686                                                      and 1 values on pin.                                                      */
55687   GPIO_PINCFG50_OUTCFG50_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55688                                                      low, tristate otherwise.                                                  */
55689   GPIO_PINCFG50_OUTCFG50_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55690                                                      drive 0, 1 of HiZ on pin.                                                 */
55691 } GPIO_PINCFG50_OUTCFG50_Enum;
55692 
55693 /* =============================================  GPIO PINCFG50 IRPTEN50 [6..7]  ============================================= */
55694 typedef enum {                                  /*!< GPIO_PINCFG50_IRPTEN50                                                    */
55695   GPIO_PINCFG50_IRPTEN50_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55696   GPIO_PINCFG50_IRPTEN50_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55697                                                      on this GPIO                                                              */
55698   GPIO_PINCFG50_IRPTEN50_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55699                                                      on this GPIO                                                              */
55700   GPIO_PINCFG50_IRPTEN50_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55701                                                      GPIO                                                                      */
55702 } GPIO_PINCFG50_IRPTEN50_Enum;
55703 
55704 /* =============================================  GPIO PINCFG50 FNCSEL50 [0..3]  ============================================= */
55705 typedef enum {                                  /*!< GPIO_PINCFG50_FNCSEL50                                                    */
55706   GPIO_PINCFG50_FNCSEL50_PDM0_CLK      = 0,     /*!< PDM0_CLK : PDMx Clock output (I2C Master/Slave D)                         */
55707   GPIO_PINCFG50_FNCSEL50_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
55708   GPIO_PINCFG50_FNCSEL50_SWTRACECLK    = 2,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
55709   GPIO_PINCFG50_FNCSEL50_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55710   GPIO_PINCFG50_FNCSEL50_UART2RTS      = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
55711   GPIO_PINCFG50_FNCSEL50_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
55712   GPIO_PINCFG50_FNCSEL50_CT50          = 6,     /*!< CT50 : Timer/Counter input or output; Selection of direction
55713                                                      is done via CTIMER register settings.                                     */
55714   GPIO_PINCFG50_FNCSEL50_NCE50         = 7,     /*!< NCE50 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55715                                                      CE_POLARITY field                                                         */
55716   GPIO_PINCFG50_FNCSEL50_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
55717   GPIO_PINCFG50_FNCSEL50_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
55718   GPIO_PINCFG50_FNCSEL50_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55719   GPIO_PINCFG50_FNCSEL50_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55720   GPIO_PINCFG50_FNCSEL50_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55721   GPIO_PINCFG50_FNCSEL50_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55722   GPIO_PINCFG50_FNCSEL50_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55723   GPIO_PINCFG50_FNCSEL50_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55724 } GPIO_PINCFG50_FNCSEL50_Enum;
55725 
55726 /* =======================================================  PINCFG51  ======================================================== */
55727 /* ============================================  GPIO PINCFG51 NCEPOL51 [22..22]  ============================================ */
55728 typedef enum {                                  /*!< GPIO_PINCFG51_NCEPOL51                                                    */
55729   GPIO_PINCFG51_NCEPOL51_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55730   GPIO_PINCFG51_NCEPOL51_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55731 } GPIO_PINCFG51_NCEPOL51_Enum;
55732 
55733 /* ============================================  GPIO PINCFG51 NCESRC51 [16..21]  ============================================ */
55734 typedef enum {                                  /*!< GPIO_PINCFG51_NCESRC51                                                    */
55735   GPIO_PINCFG51_NCESRC51_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55736   GPIO_PINCFG51_NCESRC51_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55737   GPIO_PINCFG51_NCESRC51_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55738   GPIO_PINCFG51_NCESRC51_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55739   GPIO_PINCFG51_NCESRC51_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55740   GPIO_PINCFG51_NCESRC51_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55741   GPIO_PINCFG51_NCESRC51_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55742   GPIO_PINCFG51_NCESRC51_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55743   GPIO_PINCFG51_NCESRC51_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55744   GPIO_PINCFG51_NCESRC51_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55745   GPIO_PINCFG51_NCESRC51_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55746   GPIO_PINCFG51_NCESRC51_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55747   GPIO_PINCFG51_NCESRC51_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55748   GPIO_PINCFG51_NCESRC51_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55749   GPIO_PINCFG51_NCESRC51_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55750   GPIO_PINCFG51_NCESRC51_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55751   GPIO_PINCFG51_NCESRC51_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55752   GPIO_PINCFG51_NCESRC51_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55753   GPIO_PINCFG51_NCESRC51_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55754   GPIO_PINCFG51_NCESRC51_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55755   GPIO_PINCFG51_NCESRC51_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55756   GPIO_PINCFG51_NCESRC51_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55757   GPIO_PINCFG51_NCESRC51_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55758   GPIO_PINCFG51_NCESRC51_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55759   GPIO_PINCFG51_NCESRC51_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55760   GPIO_PINCFG51_NCESRC51_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55761   GPIO_PINCFG51_NCESRC51_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55762   GPIO_PINCFG51_NCESRC51_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55763   GPIO_PINCFG51_NCESRC51_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55764   GPIO_PINCFG51_NCESRC51_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55765   GPIO_PINCFG51_NCESRC51_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55766   GPIO_PINCFG51_NCESRC51_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55767   GPIO_PINCFG51_NCESRC51_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55768   GPIO_PINCFG51_NCESRC51_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55769   GPIO_PINCFG51_NCESRC51_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55770   GPIO_PINCFG51_NCESRC51_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55771   GPIO_PINCFG51_NCESRC51_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55772   GPIO_PINCFG51_NCESRC51_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55773   GPIO_PINCFG51_NCESRC51_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55774   GPIO_PINCFG51_NCESRC51_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55775   GPIO_PINCFG51_NCESRC51_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55776   GPIO_PINCFG51_NCESRC51_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55777   GPIO_PINCFG51_NCESRC51_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55778 } GPIO_PINCFG51_NCESRC51_Enum;
55779 
55780 /* ===========================================  GPIO PINCFG51 PULLCFG51 [13..15]  ============================================ */
55781 typedef enum {                                  /*!< GPIO_PINCFG51_PULLCFG51                                                   */
55782   GPIO_PINCFG51_PULLCFG51_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55783   GPIO_PINCFG51_PULLCFG51_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55784   GPIO_PINCFG51_PULLCFG51_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55785   GPIO_PINCFG51_PULLCFG51_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55786   GPIO_PINCFG51_PULLCFG51_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55787   GPIO_PINCFG51_PULLCFG51_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55788   GPIO_PINCFG51_PULLCFG51_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55789   GPIO_PINCFG51_PULLCFG51_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55790 } GPIO_PINCFG51_PULLCFG51_Enum;
55791 
55792 /* ==============================================  GPIO PINCFG51 DS51 [10..11]  ============================================== */
55793 typedef enum {                                  /*!< GPIO_PINCFG51_DS51                                                        */
55794   GPIO_PINCFG51_DS51_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55795   GPIO_PINCFG51_DS51_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55796   GPIO_PINCFG51_DS51_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55797   GPIO_PINCFG51_DS51_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55798 } GPIO_PINCFG51_DS51_Enum;
55799 
55800 /* =============================================  GPIO PINCFG51 OUTCFG51 [8..9]  ============================================= */
55801 typedef enum {                                  /*!< GPIO_PINCFG51_OUTCFG51                                                    */
55802   GPIO_PINCFG51_OUTCFG51_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55803   GPIO_PINCFG51_OUTCFG51_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55804                                                      and 1 values on pin.                                                      */
55805   GPIO_PINCFG51_OUTCFG51_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55806                                                      low, tristate otherwise.                                                  */
55807   GPIO_PINCFG51_OUTCFG51_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55808                                                      drive 0, 1 of HiZ on pin.                                                 */
55809 } GPIO_PINCFG51_OUTCFG51_Enum;
55810 
55811 /* =============================================  GPIO PINCFG51 IRPTEN51 [6..7]  ============================================= */
55812 typedef enum {                                  /*!< GPIO_PINCFG51_IRPTEN51                                                    */
55813   GPIO_PINCFG51_IRPTEN51_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55814   GPIO_PINCFG51_IRPTEN51_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55815                                                      on this GPIO                                                              */
55816   GPIO_PINCFG51_IRPTEN51_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55817                                                      on this GPIO                                                              */
55818   GPIO_PINCFG51_IRPTEN51_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55819                                                      GPIO                                                                      */
55820 } GPIO_PINCFG51_IRPTEN51_Enum;
55821 
55822 /* =============================================  GPIO PINCFG51 FNCSEL51 [0..3]  ============================================= */
55823 typedef enum {                                  /*!< GPIO_PINCFG51_FNCSEL51                                                    */
55824   GPIO_PINCFG51_FNCSEL51_PDM0_DATA     = 0,     /*!< PDM0_DATA : PDMx audio data input to chip (I2C Master/Slave
55825                                                      D)                                                                        */
55826   GPIO_PINCFG51_FNCSEL51_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
55827   GPIO_PINCFG51_FNCSEL51_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
55828   GPIO_PINCFG51_FNCSEL51_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55829   GPIO_PINCFG51_FNCSEL51_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
55830   GPIO_PINCFG51_FNCSEL51_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
55831   GPIO_PINCFG51_FNCSEL51_CT51          = 6,     /*!< CT51 : Timer/Counter input or output; Selection of direction
55832                                                      is done via CTIMER register settings.                                     */
55833   GPIO_PINCFG51_FNCSEL51_NCE51         = 7,     /*!< NCE51 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55834                                                      CE_POLARITY field                                                         */
55835   GPIO_PINCFG51_FNCSEL51_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
55836   GPIO_PINCFG51_FNCSEL51_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55837   GPIO_PINCFG51_FNCSEL51_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55838   GPIO_PINCFG51_FNCSEL51_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55839   GPIO_PINCFG51_FNCSEL51_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55840   GPIO_PINCFG51_FNCSEL51_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55841   GPIO_PINCFG51_FNCSEL51_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55842   GPIO_PINCFG51_FNCSEL51_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55843 } GPIO_PINCFG51_FNCSEL51_Enum;
55844 
55845 /* =======================================================  PINCFG52  ======================================================== */
55846 /* ============================================  GPIO PINCFG52 NCEPOL52 [22..22]  ============================================ */
55847 typedef enum {                                  /*!< GPIO_PINCFG52_NCEPOL52                                                    */
55848   GPIO_PINCFG52_NCEPOL52_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55849   GPIO_PINCFG52_NCEPOL52_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55850 } GPIO_PINCFG52_NCEPOL52_Enum;
55851 
55852 /* ============================================  GPIO PINCFG52 NCESRC52 [16..21]  ============================================ */
55853 typedef enum {                                  /*!< GPIO_PINCFG52_NCESRC52                                                    */
55854   GPIO_PINCFG52_NCESRC52_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55855   GPIO_PINCFG52_NCESRC52_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55856   GPIO_PINCFG52_NCESRC52_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55857   GPIO_PINCFG52_NCESRC52_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55858   GPIO_PINCFG52_NCESRC52_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55859   GPIO_PINCFG52_NCESRC52_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55860   GPIO_PINCFG52_NCESRC52_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55861   GPIO_PINCFG52_NCESRC52_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55862   GPIO_PINCFG52_NCESRC52_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55863   GPIO_PINCFG52_NCESRC52_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55864   GPIO_PINCFG52_NCESRC52_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55865   GPIO_PINCFG52_NCESRC52_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55866   GPIO_PINCFG52_NCESRC52_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55867   GPIO_PINCFG52_NCESRC52_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55868   GPIO_PINCFG52_NCESRC52_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55869   GPIO_PINCFG52_NCESRC52_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55870   GPIO_PINCFG52_NCESRC52_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55871   GPIO_PINCFG52_NCESRC52_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55872   GPIO_PINCFG52_NCESRC52_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55873   GPIO_PINCFG52_NCESRC52_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55874   GPIO_PINCFG52_NCESRC52_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55875   GPIO_PINCFG52_NCESRC52_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55876   GPIO_PINCFG52_NCESRC52_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55877   GPIO_PINCFG52_NCESRC52_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55878   GPIO_PINCFG52_NCESRC52_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55879   GPIO_PINCFG52_NCESRC52_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55880   GPIO_PINCFG52_NCESRC52_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55881   GPIO_PINCFG52_NCESRC52_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55882   GPIO_PINCFG52_NCESRC52_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55883   GPIO_PINCFG52_NCESRC52_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55884   GPIO_PINCFG52_NCESRC52_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55885   GPIO_PINCFG52_NCESRC52_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55886   GPIO_PINCFG52_NCESRC52_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55887   GPIO_PINCFG52_NCESRC52_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55888   GPIO_PINCFG52_NCESRC52_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55889   GPIO_PINCFG52_NCESRC52_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55890   GPIO_PINCFG52_NCESRC52_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55891   GPIO_PINCFG52_NCESRC52_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55892   GPIO_PINCFG52_NCESRC52_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55893   GPIO_PINCFG52_NCESRC52_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55894   GPIO_PINCFG52_NCESRC52_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55895   GPIO_PINCFG52_NCESRC52_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55896   GPIO_PINCFG52_NCESRC52_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55897 } GPIO_PINCFG52_NCESRC52_Enum;
55898 
55899 /* ===========================================  GPIO PINCFG52 PULLCFG52 [13..15]  ============================================ */
55900 typedef enum {                                  /*!< GPIO_PINCFG52_PULLCFG52                                                   */
55901   GPIO_PINCFG52_PULLCFG52_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55902   GPIO_PINCFG52_PULLCFG52_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55903   GPIO_PINCFG52_PULLCFG52_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55904   GPIO_PINCFG52_PULLCFG52_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55905   GPIO_PINCFG52_PULLCFG52_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55906   GPIO_PINCFG52_PULLCFG52_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55907   GPIO_PINCFG52_PULLCFG52_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55908   GPIO_PINCFG52_PULLCFG52_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55909 } GPIO_PINCFG52_PULLCFG52_Enum;
55910 
55911 /* ==============================================  GPIO PINCFG52 DS52 [10..11]  ============================================== */
55912 typedef enum {                                  /*!< GPIO_PINCFG52_DS52                                                        */
55913   GPIO_PINCFG52_DS52_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55914   GPIO_PINCFG52_DS52_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55915   GPIO_PINCFG52_DS52_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55916   GPIO_PINCFG52_DS52_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55917 } GPIO_PINCFG52_DS52_Enum;
55918 
55919 /* =============================================  GPIO PINCFG52 OUTCFG52 [8..9]  ============================================= */
55920 typedef enum {                                  /*!< GPIO_PINCFG52_OUTCFG52                                                    */
55921   GPIO_PINCFG52_OUTCFG52_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55922   GPIO_PINCFG52_OUTCFG52_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55923                                                      and 1 values on pin.                                                      */
55924   GPIO_PINCFG52_OUTCFG52_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55925                                                      low, tristate otherwise.                                                  */
55926   GPIO_PINCFG52_OUTCFG52_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55927                                                      drive 0, 1 of HiZ on pin.                                                 */
55928 } GPIO_PINCFG52_OUTCFG52_Enum;
55929 
55930 /* =============================================  GPIO PINCFG52 IRPTEN52 [6..7]  ============================================= */
55931 typedef enum {                                  /*!< GPIO_PINCFG52_IRPTEN52                                                    */
55932   GPIO_PINCFG52_IRPTEN52_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55933   GPIO_PINCFG52_IRPTEN52_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55934                                                      on this GPIO                                                              */
55935   GPIO_PINCFG52_IRPTEN52_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55936                                                      on this GPIO                                                              */
55937   GPIO_PINCFG52_IRPTEN52_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55938                                                      GPIO                                                                      */
55939 } GPIO_PINCFG52_IRPTEN52_Enum;
55940 
55941 /* =============================================  GPIO PINCFG52 FNCSEL52 [0..3]  ============================================= */
55942 typedef enum {                                  /*!< GPIO_PINCFG52_FNCSEL52                                                    */
55943   GPIO_PINCFG52_FNCSEL52_PDM1_CLK      = 0,     /*!< PDM1_CLK : PDMx Clock output (I2C Master/Slave D)                         */
55944   GPIO_PINCFG52_FNCSEL52_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
55945   GPIO_PINCFG52_FNCSEL52_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
55946   GPIO_PINCFG52_FNCSEL52_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55947   GPIO_PINCFG52_FNCSEL52_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
55948   GPIO_PINCFG52_FNCSEL52_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
55949   GPIO_PINCFG52_FNCSEL52_CT52          = 6,     /*!< CT52 : Timer/Counter input or output; Selection of direction
55950                                                      is done via CTIMER register settings.                                     */
55951   GPIO_PINCFG52_FNCSEL52_NCE52         = 7,     /*!< NCE52 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55952                                                      CE_POLARITY field                                                         */
55953   GPIO_PINCFG52_FNCSEL52_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
55954   GPIO_PINCFG52_FNCSEL52_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
55955   GPIO_PINCFG52_FNCSEL52_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55956   GPIO_PINCFG52_FNCSEL52_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55957   GPIO_PINCFG52_FNCSEL52_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55958   GPIO_PINCFG52_FNCSEL52_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55959   GPIO_PINCFG52_FNCSEL52_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55960   GPIO_PINCFG52_FNCSEL52_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55961 } GPIO_PINCFG52_FNCSEL52_Enum;
55962 
55963 /* =======================================================  PINCFG53  ======================================================== */
55964 /* ============================================  GPIO PINCFG53 NCEPOL53 [22..22]  ============================================ */
55965 typedef enum {                                  /*!< GPIO_PINCFG53_NCEPOL53                                                    */
55966   GPIO_PINCFG53_NCEPOL53_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55967   GPIO_PINCFG53_NCEPOL53_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55968 } GPIO_PINCFG53_NCEPOL53_Enum;
55969 
55970 /* ============================================  GPIO PINCFG53 NCESRC53 [16..21]  ============================================ */
55971 typedef enum {                                  /*!< GPIO_PINCFG53_NCESRC53                                                    */
55972   GPIO_PINCFG53_NCESRC53_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55973   GPIO_PINCFG53_NCESRC53_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55974   GPIO_PINCFG53_NCESRC53_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55975   GPIO_PINCFG53_NCESRC53_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55976   GPIO_PINCFG53_NCESRC53_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55977   GPIO_PINCFG53_NCESRC53_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55978   GPIO_PINCFG53_NCESRC53_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55979   GPIO_PINCFG53_NCESRC53_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55980   GPIO_PINCFG53_NCESRC53_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55981   GPIO_PINCFG53_NCESRC53_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55982   GPIO_PINCFG53_NCESRC53_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55983   GPIO_PINCFG53_NCESRC53_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55984   GPIO_PINCFG53_NCESRC53_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55985   GPIO_PINCFG53_NCESRC53_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55986   GPIO_PINCFG53_NCESRC53_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55987   GPIO_PINCFG53_NCESRC53_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55988   GPIO_PINCFG53_NCESRC53_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55989   GPIO_PINCFG53_NCESRC53_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55990   GPIO_PINCFG53_NCESRC53_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55991   GPIO_PINCFG53_NCESRC53_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55992   GPIO_PINCFG53_NCESRC53_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55993   GPIO_PINCFG53_NCESRC53_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55994   GPIO_PINCFG53_NCESRC53_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55995   GPIO_PINCFG53_NCESRC53_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55996   GPIO_PINCFG53_NCESRC53_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55997   GPIO_PINCFG53_NCESRC53_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55998   GPIO_PINCFG53_NCESRC53_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55999   GPIO_PINCFG53_NCESRC53_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56000   GPIO_PINCFG53_NCESRC53_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56001   GPIO_PINCFG53_NCESRC53_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56002   GPIO_PINCFG53_NCESRC53_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56003   GPIO_PINCFG53_NCESRC53_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56004   GPIO_PINCFG53_NCESRC53_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56005   GPIO_PINCFG53_NCESRC53_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56006   GPIO_PINCFG53_NCESRC53_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56007   GPIO_PINCFG53_NCESRC53_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56008   GPIO_PINCFG53_NCESRC53_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56009   GPIO_PINCFG53_NCESRC53_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56010   GPIO_PINCFG53_NCESRC53_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56011   GPIO_PINCFG53_NCESRC53_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56012   GPIO_PINCFG53_NCESRC53_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56013   GPIO_PINCFG53_NCESRC53_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56014   GPIO_PINCFG53_NCESRC53_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56015 } GPIO_PINCFG53_NCESRC53_Enum;
56016 
56017 /* ===========================================  GPIO PINCFG53 PULLCFG53 [13..15]  ============================================ */
56018 typedef enum {                                  /*!< GPIO_PINCFG53_PULLCFG53                                                   */
56019   GPIO_PINCFG53_PULLCFG53_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56020   GPIO_PINCFG53_PULLCFG53_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56021   GPIO_PINCFG53_PULLCFG53_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56022   GPIO_PINCFG53_PULLCFG53_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56023   GPIO_PINCFG53_PULLCFG53_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56024   GPIO_PINCFG53_PULLCFG53_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56025   GPIO_PINCFG53_PULLCFG53_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56026   GPIO_PINCFG53_PULLCFG53_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56027 } GPIO_PINCFG53_PULLCFG53_Enum;
56028 
56029 /* ==============================================  GPIO PINCFG53 DS53 [10..11]  ============================================== */
56030 typedef enum {                                  /*!< GPIO_PINCFG53_DS53                                                        */
56031   GPIO_PINCFG53_DS53_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56032   GPIO_PINCFG53_DS53_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56033   GPIO_PINCFG53_DS53_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56034   GPIO_PINCFG53_DS53_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56035 } GPIO_PINCFG53_DS53_Enum;
56036 
56037 /* =============================================  GPIO PINCFG53 OUTCFG53 [8..9]  ============================================= */
56038 typedef enum {                                  /*!< GPIO_PINCFG53_OUTCFG53                                                    */
56039   GPIO_PINCFG53_OUTCFG53_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56040   GPIO_PINCFG53_OUTCFG53_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56041                                                      and 1 values on pin.                                                      */
56042   GPIO_PINCFG53_OUTCFG53_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56043                                                      low, tristate otherwise.                                                  */
56044   GPIO_PINCFG53_OUTCFG53_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56045                                                      drive 0, 1 of HiZ on pin.                                                 */
56046 } GPIO_PINCFG53_OUTCFG53_Enum;
56047 
56048 /* =============================================  GPIO PINCFG53 IRPTEN53 [6..7]  ============================================= */
56049 typedef enum {                                  /*!< GPIO_PINCFG53_IRPTEN53                                                    */
56050   GPIO_PINCFG53_IRPTEN53_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56051   GPIO_PINCFG53_IRPTEN53_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56052                                                      on this GPIO                                                              */
56053   GPIO_PINCFG53_IRPTEN53_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56054                                                      on this GPIO                                                              */
56055   GPIO_PINCFG53_IRPTEN53_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56056                                                      GPIO                                                                      */
56057 } GPIO_PINCFG53_IRPTEN53_Enum;
56058 
56059 /* =============================================  GPIO PINCFG53 FNCSEL53 [0..3]  ============================================= */
56060 typedef enum {                                  /*!< GPIO_PINCFG53_FNCSEL53                                                    */
56061   GPIO_PINCFG53_FNCSEL53_PDM1_DATA     = 0,     /*!< PDM1_DATA : PDMx audio data input to chip (I2C Master/Slave
56062                                                      D)                                                                        */
56063   GPIO_PINCFG53_FNCSEL53_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
56064   GPIO_PINCFG53_FNCSEL53_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
56065   GPIO_PINCFG53_FNCSEL53_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56066   GPIO_PINCFG53_FNCSEL53_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
56067   GPIO_PINCFG53_FNCSEL53_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
56068   GPIO_PINCFG53_FNCSEL53_CT53          = 6,     /*!< CT53 : Timer/Counter input or output; Selection of direction
56069                                                      is done via CTIMER register settings.                                     */
56070   GPIO_PINCFG53_FNCSEL53_NCE53         = 7,     /*!< NCE53 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56071                                                      CE_POLARITY field                                                         */
56072   GPIO_PINCFG53_FNCSEL53_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
56073   GPIO_PINCFG53_FNCSEL53_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56074   GPIO_PINCFG53_FNCSEL53_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56075   GPIO_PINCFG53_FNCSEL53_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56076   GPIO_PINCFG53_FNCSEL53_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56077   GPIO_PINCFG53_FNCSEL53_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56078   GPIO_PINCFG53_FNCSEL53_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56079   GPIO_PINCFG53_FNCSEL53_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56080 } GPIO_PINCFG53_FNCSEL53_Enum;
56081 
56082 /* =======================================================  PINCFG54  ======================================================== */
56083 /* ============================================  GPIO PINCFG54 NCEPOL54 [22..22]  ============================================ */
56084 typedef enum {                                  /*!< GPIO_PINCFG54_NCEPOL54                                                    */
56085   GPIO_PINCFG54_NCEPOL54_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56086   GPIO_PINCFG54_NCEPOL54_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56087 } GPIO_PINCFG54_NCEPOL54_Enum;
56088 
56089 /* ============================================  GPIO PINCFG54 NCESRC54 [16..21]  ============================================ */
56090 typedef enum {                                  /*!< GPIO_PINCFG54_NCESRC54                                                    */
56091   GPIO_PINCFG54_NCESRC54_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56092   GPIO_PINCFG54_NCESRC54_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56093   GPIO_PINCFG54_NCESRC54_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56094   GPIO_PINCFG54_NCESRC54_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56095   GPIO_PINCFG54_NCESRC54_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56096   GPIO_PINCFG54_NCESRC54_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56097   GPIO_PINCFG54_NCESRC54_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56098   GPIO_PINCFG54_NCESRC54_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56099   GPIO_PINCFG54_NCESRC54_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56100   GPIO_PINCFG54_NCESRC54_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56101   GPIO_PINCFG54_NCESRC54_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56102   GPIO_PINCFG54_NCESRC54_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56103   GPIO_PINCFG54_NCESRC54_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56104   GPIO_PINCFG54_NCESRC54_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56105   GPIO_PINCFG54_NCESRC54_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56106   GPIO_PINCFG54_NCESRC54_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56107   GPIO_PINCFG54_NCESRC54_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56108   GPIO_PINCFG54_NCESRC54_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56109   GPIO_PINCFG54_NCESRC54_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56110   GPIO_PINCFG54_NCESRC54_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56111   GPIO_PINCFG54_NCESRC54_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56112   GPIO_PINCFG54_NCESRC54_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56113   GPIO_PINCFG54_NCESRC54_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56114   GPIO_PINCFG54_NCESRC54_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56115   GPIO_PINCFG54_NCESRC54_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56116   GPIO_PINCFG54_NCESRC54_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56117   GPIO_PINCFG54_NCESRC54_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56118   GPIO_PINCFG54_NCESRC54_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56119   GPIO_PINCFG54_NCESRC54_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56120   GPIO_PINCFG54_NCESRC54_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56121   GPIO_PINCFG54_NCESRC54_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56122   GPIO_PINCFG54_NCESRC54_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56123   GPIO_PINCFG54_NCESRC54_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56124   GPIO_PINCFG54_NCESRC54_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56125   GPIO_PINCFG54_NCESRC54_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56126   GPIO_PINCFG54_NCESRC54_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56127   GPIO_PINCFG54_NCESRC54_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56128   GPIO_PINCFG54_NCESRC54_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56129   GPIO_PINCFG54_NCESRC54_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56130   GPIO_PINCFG54_NCESRC54_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56131   GPIO_PINCFG54_NCESRC54_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56132   GPIO_PINCFG54_NCESRC54_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56133   GPIO_PINCFG54_NCESRC54_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56134 } GPIO_PINCFG54_NCESRC54_Enum;
56135 
56136 /* ===========================================  GPIO PINCFG54 PULLCFG54 [13..15]  ============================================ */
56137 typedef enum {                                  /*!< GPIO_PINCFG54_PULLCFG54                                                   */
56138   GPIO_PINCFG54_PULLCFG54_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56139   GPIO_PINCFG54_PULLCFG54_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56140   GPIO_PINCFG54_PULLCFG54_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56141   GPIO_PINCFG54_PULLCFG54_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56142   GPIO_PINCFG54_PULLCFG54_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56143   GPIO_PINCFG54_PULLCFG54_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56144   GPIO_PINCFG54_PULLCFG54_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56145   GPIO_PINCFG54_PULLCFG54_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56146 } GPIO_PINCFG54_PULLCFG54_Enum;
56147 
56148 /* ==============================================  GPIO PINCFG54 DS54 [10..11]  ============================================== */
56149 typedef enum {                                  /*!< GPIO_PINCFG54_DS54                                                        */
56150   GPIO_PINCFG54_DS54_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56151   GPIO_PINCFG54_DS54_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56152   GPIO_PINCFG54_DS54_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56153   GPIO_PINCFG54_DS54_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56154 } GPIO_PINCFG54_DS54_Enum;
56155 
56156 /* =============================================  GPIO PINCFG54 OUTCFG54 [8..9]  ============================================= */
56157 typedef enum {                                  /*!< GPIO_PINCFG54_OUTCFG54                                                    */
56158   GPIO_PINCFG54_OUTCFG54_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56159   GPIO_PINCFG54_OUTCFG54_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56160                                                      and 1 values on pin.                                                      */
56161   GPIO_PINCFG54_OUTCFG54_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56162                                                      low, tristate otherwise.                                                  */
56163   GPIO_PINCFG54_OUTCFG54_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56164                                                      drive 0, 1 of HiZ on pin.                                                 */
56165 } GPIO_PINCFG54_OUTCFG54_Enum;
56166 
56167 /* =============================================  GPIO PINCFG54 IRPTEN54 [6..7]  ============================================= */
56168 typedef enum {                                  /*!< GPIO_PINCFG54_IRPTEN54                                                    */
56169   GPIO_PINCFG54_IRPTEN54_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56170   GPIO_PINCFG54_IRPTEN54_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56171                                                      on this GPIO                                                              */
56172   GPIO_PINCFG54_IRPTEN54_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56173                                                      on this GPIO                                                              */
56174   GPIO_PINCFG54_IRPTEN54_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56175                                                      GPIO                                                                      */
56176 } GPIO_PINCFG54_IRPTEN54_Enum;
56177 
56178 /* =============================================  GPIO PINCFG54 FNCSEL54 [0..3]  ============================================= */
56179 typedef enum {                                  /*!< GPIO_PINCFG54_FNCSEL54                                                    */
56180   GPIO_PINCFG54_FNCSEL54_PDM2_CLK      = 0,     /*!< PDM2_CLK : PDMx Clock output (I2C Master/Slave D)                         */
56181   GPIO_PINCFG54_FNCSEL54_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
56182   GPIO_PINCFG54_FNCSEL54_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
56183   GPIO_PINCFG54_FNCSEL54_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56184   GPIO_PINCFG54_FNCSEL54_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
56185   GPIO_PINCFG54_FNCSEL54_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
56186   GPIO_PINCFG54_FNCSEL54_CT54          = 6,     /*!< CT54 : Timer/Counter input or output; Selection of direction
56187                                                      is done via CTIMER register settings.                                     */
56188   GPIO_PINCFG54_FNCSEL54_NCE54         = 7,     /*!< NCE54 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56189                                                      CE_POLARITY field                                                         */
56190   GPIO_PINCFG54_FNCSEL54_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
56191   GPIO_PINCFG54_FNCSEL54_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56192   GPIO_PINCFG54_FNCSEL54_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56193   GPIO_PINCFG54_FNCSEL54_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56194   GPIO_PINCFG54_FNCSEL54_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56195   GPIO_PINCFG54_FNCSEL54_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56196   GPIO_PINCFG54_FNCSEL54_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56197   GPIO_PINCFG54_FNCSEL54_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56198 } GPIO_PINCFG54_FNCSEL54_Enum;
56199 
56200 /* =======================================================  PINCFG55  ======================================================== */
56201 /* ============================================  GPIO PINCFG55 NCEPOL55 [22..22]  ============================================ */
56202 typedef enum {                                  /*!< GPIO_PINCFG55_NCEPOL55                                                    */
56203   GPIO_PINCFG55_NCEPOL55_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56204   GPIO_PINCFG55_NCEPOL55_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56205 } GPIO_PINCFG55_NCEPOL55_Enum;
56206 
56207 /* ============================================  GPIO PINCFG55 NCESRC55 [16..21]  ============================================ */
56208 typedef enum {                                  /*!< GPIO_PINCFG55_NCESRC55                                                    */
56209   GPIO_PINCFG55_NCESRC55_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56210   GPIO_PINCFG55_NCESRC55_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56211   GPIO_PINCFG55_NCESRC55_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56212   GPIO_PINCFG55_NCESRC55_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56213   GPIO_PINCFG55_NCESRC55_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56214   GPIO_PINCFG55_NCESRC55_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56215   GPIO_PINCFG55_NCESRC55_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56216   GPIO_PINCFG55_NCESRC55_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56217   GPIO_PINCFG55_NCESRC55_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56218   GPIO_PINCFG55_NCESRC55_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56219   GPIO_PINCFG55_NCESRC55_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56220   GPIO_PINCFG55_NCESRC55_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56221   GPIO_PINCFG55_NCESRC55_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56222   GPIO_PINCFG55_NCESRC55_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56223   GPIO_PINCFG55_NCESRC55_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56224   GPIO_PINCFG55_NCESRC55_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56225   GPIO_PINCFG55_NCESRC55_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56226   GPIO_PINCFG55_NCESRC55_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56227   GPIO_PINCFG55_NCESRC55_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56228   GPIO_PINCFG55_NCESRC55_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56229   GPIO_PINCFG55_NCESRC55_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56230   GPIO_PINCFG55_NCESRC55_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56231   GPIO_PINCFG55_NCESRC55_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56232   GPIO_PINCFG55_NCESRC55_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56233   GPIO_PINCFG55_NCESRC55_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56234   GPIO_PINCFG55_NCESRC55_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56235   GPIO_PINCFG55_NCESRC55_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56236   GPIO_PINCFG55_NCESRC55_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56237   GPIO_PINCFG55_NCESRC55_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56238   GPIO_PINCFG55_NCESRC55_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56239   GPIO_PINCFG55_NCESRC55_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56240   GPIO_PINCFG55_NCESRC55_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56241   GPIO_PINCFG55_NCESRC55_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56242   GPIO_PINCFG55_NCESRC55_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56243   GPIO_PINCFG55_NCESRC55_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56244   GPIO_PINCFG55_NCESRC55_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56245   GPIO_PINCFG55_NCESRC55_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56246   GPIO_PINCFG55_NCESRC55_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56247   GPIO_PINCFG55_NCESRC55_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56248   GPIO_PINCFG55_NCESRC55_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56249   GPIO_PINCFG55_NCESRC55_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56250   GPIO_PINCFG55_NCESRC55_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56251   GPIO_PINCFG55_NCESRC55_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56252 } GPIO_PINCFG55_NCESRC55_Enum;
56253 
56254 /* ===========================================  GPIO PINCFG55 PULLCFG55 [13..15]  ============================================ */
56255 typedef enum {                                  /*!< GPIO_PINCFG55_PULLCFG55                                                   */
56256   GPIO_PINCFG55_PULLCFG55_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56257   GPIO_PINCFG55_PULLCFG55_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56258   GPIO_PINCFG55_PULLCFG55_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56259   GPIO_PINCFG55_PULLCFG55_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56260   GPIO_PINCFG55_PULLCFG55_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56261   GPIO_PINCFG55_PULLCFG55_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56262   GPIO_PINCFG55_PULLCFG55_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56263   GPIO_PINCFG55_PULLCFG55_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56264 } GPIO_PINCFG55_PULLCFG55_Enum;
56265 
56266 /* ==============================================  GPIO PINCFG55 DS55 [10..11]  ============================================== */
56267 typedef enum {                                  /*!< GPIO_PINCFG55_DS55                                                        */
56268   GPIO_PINCFG55_DS55_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56269   GPIO_PINCFG55_DS55_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56270   GPIO_PINCFG55_DS55_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56271   GPIO_PINCFG55_DS55_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56272 } GPIO_PINCFG55_DS55_Enum;
56273 
56274 /* =============================================  GPIO PINCFG55 OUTCFG55 [8..9]  ============================================= */
56275 typedef enum {                                  /*!< GPIO_PINCFG55_OUTCFG55                                                    */
56276   GPIO_PINCFG55_OUTCFG55_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56277   GPIO_PINCFG55_OUTCFG55_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56278                                                      and 1 values on pin.                                                      */
56279   GPIO_PINCFG55_OUTCFG55_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56280                                                      low, tristate otherwise.                                                  */
56281   GPIO_PINCFG55_OUTCFG55_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56282                                                      drive 0, 1 of HiZ on pin.                                                 */
56283 } GPIO_PINCFG55_OUTCFG55_Enum;
56284 
56285 /* =============================================  GPIO PINCFG55 IRPTEN55 [6..7]  ============================================= */
56286 typedef enum {                                  /*!< GPIO_PINCFG55_IRPTEN55                                                    */
56287   GPIO_PINCFG55_IRPTEN55_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56288   GPIO_PINCFG55_IRPTEN55_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56289                                                      on this GPIO                                                              */
56290   GPIO_PINCFG55_IRPTEN55_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56291                                                      on this GPIO                                                              */
56292   GPIO_PINCFG55_IRPTEN55_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56293                                                      GPIO                                                                      */
56294 } GPIO_PINCFG55_IRPTEN55_Enum;
56295 
56296 /* =============================================  GPIO PINCFG55 FNCSEL55 [0..3]  ============================================= */
56297 typedef enum {                                  /*!< GPIO_PINCFG55_FNCSEL55                                                    */
56298   GPIO_PINCFG55_FNCSEL55_PDM2_DATA     = 0,     /*!< PDM2_DATA : PDMx audio data input to chip (I2C Master/Slave
56299                                                      D)                                                                        */
56300   GPIO_PINCFG55_FNCSEL55_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
56301   GPIO_PINCFG55_FNCSEL55_SWTRACECTL    = 2,     /*!< SWTRACECTL : Serial Wire Debug Trace Control                              */
56302   GPIO_PINCFG55_FNCSEL55_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56303   GPIO_PINCFG55_FNCSEL55_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
56304   GPIO_PINCFG55_FNCSEL55_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
56305   GPIO_PINCFG55_FNCSEL55_CT55          = 6,     /*!< CT55 : Timer/Counter input or output; Selection of direction
56306                                                      is done via CTIMER register settings.                                     */
56307   GPIO_PINCFG55_FNCSEL55_NCE55         = 7,     /*!< NCE55 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56308                                                      CE_POLARITY field                                                         */
56309   GPIO_PINCFG55_FNCSEL55_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
56310   GPIO_PINCFG55_FNCSEL55_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56311   GPIO_PINCFG55_FNCSEL55_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56312   GPIO_PINCFG55_FNCSEL55_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56313   GPIO_PINCFG55_FNCSEL55_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56314   GPIO_PINCFG55_FNCSEL55_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56315   GPIO_PINCFG55_FNCSEL55_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56316   GPIO_PINCFG55_FNCSEL55_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56317 } GPIO_PINCFG55_FNCSEL55_Enum;
56318 
56319 /* =======================================================  PINCFG56  ======================================================== */
56320 /* ============================================  GPIO PINCFG56 NCEPOL56 [22..22]  ============================================ */
56321 typedef enum {                                  /*!< GPIO_PINCFG56_NCEPOL56                                                    */
56322   GPIO_PINCFG56_NCEPOL56_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56323   GPIO_PINCFG56_NCEPOL56_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56324 } GPIO_PINCFG56_NCEPOL56_Enum;
56325 
56326 /* ============================================  GPIO PINCFG56 NCESRC56 [16..21]  ============================================ */
56327 typedef enum {                                  /*!< GPIO_PINCFG56_NCESRC56                                                    */
56328   GPIO_PINCFG56_NCESRC56_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56329   GPIO_PINCFG56_NCESRC56_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56330   GPIO_PINCFG56_NCESRC56_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56331   GPIO_PINCFG56_NCESRC56_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56332   GPIO_PINCFG56_NCESRC56_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56333   GPIO_PINCFG56_NCESRC56_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56334   GPIO_PINCFG56_NCESRC56_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56335   GPIO_PINCFG56_NCESRC56_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56336   GPIO_PINCFG56_NCESRC56_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56337   GPIO_PINCFG56_NCESRC56_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56338   GPIO_PINCFG56_NCESRC56_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56339   GPIO_PINCFG56_NCESRC56_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56340   GPIO_PINCFG56_NCESRC56_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56341   GPIO_PINCFG56_NCESRC56_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56342   GPIO_PINCFG56_NCESRC56_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56343   GPIO_PINCFG56_NCESRC56_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56344   GPIO_PINCFG56_NCESRC56_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56345   GPIO_PINCFG56_NCESRC56_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56346   GPIO_PINCFG56_NCESRC56_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56347   GPIO_PINCFG56_NCESRC56_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56348   GPIO_PINCFG56_NCESRC56_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56349   GPIO_PINCFG56_NCESRC56_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56350   GPIO_PINCFG56_NCESRC56_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56351   GPIO_PINCFG56_NCESRC56_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56352   GPIO_PINCFG56_NCESRC56_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56353   GPIO_PINCFG56_NCESRC56_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56354   GPIO_PINCFG56_NCESRC56_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56355   GPIO_PINCFG56_NCESRC56_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56356   GPIO_PINCFG56_NCESRC56_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56357   GPIO_PINCFG56_NCESRC56_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56358   GPIO_PINCFG56_NCESRC56_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56359   GPIO_PINCFG56_NCESRC56_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56360   GPIO_PINCFG56_NCESRC56_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56361   GPIO_PINCFG56_NCESRC56_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56362   GPIO_PINCFG56_NCESRC56_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56363   GPIO_PINCFG56_NCESRC56_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56364   GPIO_PINCFG56_NCESRC56_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56365   GPIO_PINCFG56_NCESRC56_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56366   GPIO_PINCFG56_NCESRC56_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56367   GPIO_PINCFG56_NCESRC56_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56368   GPIO_PINCFG56_NCESRC56_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56369   GPIO_PINCFG56_NCESRC56_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56370   GPIO_PINCFG56_NCESRC56_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56371 } GPIO_PINCFG56_NCESRC56_Enum;
56372 
56373 /* ===========================================  GPIO PINCFG56 PULLCFG56 [13..15]  ============================================ */
56374 typedef enum {                                  /*!< GPIO_PINCFG56_PULLCFG56                                                   */
56375   GPIO_PINCFG56_PULLCFG56_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56376   GPIO_PINCFG56_PULLCFG56_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56377   GPIO_PINCFG56_PULLCFG56_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56378   GPIO_PINCFG56_PULLCFG56_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56379   GPIO_PINCFG56_PULLCFG56_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56380   GPIO_PINCFG56_PULLCFG56_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56381   GPIO_PINCFG56_PULLCFG56_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56382   GPIO_PINCFG56_PULLCFG56_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56383 } GPIO_PINCFG56_PULLCFG56_Enum;
56384 
56385 /* ==============================================  GPIO PINCFG56 DS56 [10..11]  ============================================== */
56386 typedef enum {                                  /*!< GPIO_PINCFG56_DS56                                                        */
56387   GPIO_PINCFG56_DS56_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56388   GPIO_PINCFG56_DS56_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56389   GPIO_PINCFG56_DS56_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56390   GPIO_PINCFG56_DS56_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56391 } GPIO_PINCFG56_DS56_Enum;
56392 
56393 /* =============================================  GPIO PINCFG56 OUTCFG56 [8..9]  ============================================= */
56394 typedef enum {                                  /*!< GPIO_PINCFG56_OUTCFG56                                                    */
56395   GPIO_PINCFG56_OUTCFG56_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56396   GPIO_PINCFG56_OUTCFG56_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56397                                                      and 1 values on pin.                                                      */
56398   GPIO_PINCFG56_OUTCFG56_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56399                                                      low, tristate otherwise.                                                  */
56400   GPIO_PINCFG56_OUTCFG56_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56401                                                      drive 0, 1 of HiZ on pin.                                                 */
56402 } GPIO_PINCFG56_OUTCFG56_Enum;
56403 
56404 /* =============================================  GPIO PINCFG56 IRPTEN56 [6..7]  ============================================= */
56405 typedef enum {                                  /*!< GPIO_PINCFG56_IRPTEN56                                                    */
56406   GPIO_PINCFG56_IRPTEN56_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56407   GPIO_PINCFG56_IRPTEN56_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56408                                                      on this GPIO                                                              */
56409   GPIO_PINCFG56_IRPTEN56_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56410                                                      on this GPIO                                                              */
56411   GPIO_PINCFG56_IRPTEN56_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56412                                                      GPIO                                                                      */
56413 } GPIO_PINCFG56_IRPTEN56_Enum;
56414 
56415 /* =============================================  GPIO PINCFG56 FNCSEL56 [0..3]  ============================================= */
56416 typedef enum {                                  /*!< GPIO_PINCFG56_FNCSEL56                                                    */
56417   GPIO_PINCFG56_FNCSEL56_PDM3_CLK      = 0,     /*!< PDM3_CLK : PDMx Clock output (I2C Master/Slave D)                         */
56418   GPIO_PINCFG56_FNCSEL56_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
56419   GPIO_PINCFG56_FNCSEL56_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
56420   GPIO_PINCFG56_FNCSEL56_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56421   GPIO_PINCFG56_FNCSEL56_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
56422   GPIO_PINCFG56_FNCSEL56_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
56423   GPIO_PINCFG56_FNCSEL56_CT56          = 6,     /*!< CT56 : Timer/Counter input or output; Selection of direction
56424                                                      is done via CTIMER register settings.                                     */
56425   GPIO_PINCFG56_FNCSEL56_NCE56         = 7,     /*!< NCE56 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56426                                                      CE_POLARITY field                                                         */
56427   GPIO_PINCFG56_FNCSEL56_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
56428   GPIO_PINCFG56_FNCSEL56_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56429   GPIO_PINCFG56_FNCSEL56_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56430   GPIO_PINCFG56_FNCSEL56_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56431   GPIO_PINCFG56_FNCSEL56_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56432   GPIO_PINCFG56_FNCSEL56_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56433   GPIO_PINCFG56_FNCSEL56_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56434   GPIO_PINCFG56_FNCSEL56_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56435 } GPIO_PINCFG56_FNCSEL56_Enum;
56436 
56437 /* =======================================================  PINCFG57  ======================================================== */
56438 /* ============================================  GPIO PINCFG57 NCEPOL57 [22..22]  ============================================ */
56439 typedef enum {                                  /*!< GPIO_PINCFG57_NCEPOL57                                                    */
56440   GPIO_PINCFG57_NCEPOL57_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56441   GPIO_PINCFG57_NCEPOL57_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56442 } GPIO_PINCFG57_NCEPOL57_Enum;
56443 
56444 /* ============================================  GPIO PINCFG57 NCESRC57 [16..21]  ============================================ */
56445 typedef enum {                                  /*!< GPIO_PINCFG57_NCESRC57                                                    */
56446   GPIO_PINCFG57_NCESRC57_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56447   GPIO_PINCFG57_NCESRC57_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56448   GPIO_PINCFG57_NCESRC57_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56449   GPIO_PINCFG57_NCESRC57_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56450   GPIO_PINCFG57_NCESRC57_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56451   GPIO_PINCFG57_NCESRC57_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56452   GPIO_PINCFG57_NCESRC57_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56453   GPIO_PINCFG57_NCESRC57_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56454   GPIO_PINCFG57_NCESRC57_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56455   GPIO_PINCFG57_NCESRC57_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56456   GPIO_PINCFG57_NCESRC57_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56457   GPIO_PINCFG57_NCESRC57_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56458   GPIO_PINCFG57_NCESRC57_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56459   GPIO_PINCFG57_NCESRC57_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56460   GPIO_PINCFG57_NCESRC57_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56461   GPIO_PINCFG57_NCESRC57_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56462   GPIO_PINCFG57_NCESRC57_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56463   GPIO_PINCFG57_NCESRC57_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56464   GPIO_PINCFG57_NCESRC57_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56465   GPIO_PINCFG57_NCESRC57_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56466   GPIO_PINCFG57_NCESRC57_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56467   GPIO_PINCFG57_NCESRC57_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56468   GPIO_PINCFG57_NCESRC57_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56469   GPIO_PINCFG57_NCESRC57_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56470   GPIO_PINCFG57_NCESRC57_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56471   GPIO_PINCFG57_NCESRC57_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56472   GPIO_PINCFG57_NCESRC57_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56473   GPIO_PINCFG57_NCESRC57_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56474   GPIO_PINCFG57_NCESRC57_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56475   GPIO_PINCFG57_NCESRC57_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56476   GPIO_PINCFG57_NCESRC57_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56477   GPIO_PINCFG57_NCESRC57_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56478   GPIO_PINCFG57_NCESRC57_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56479   GPIO_PINCFG57_NCESRC57_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56480   GPIO_PINCFG57_NCESRC57_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56481   GPIO_PINCFG57_NCESRC57_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56482   GPIO_PINCFG57_NCESRC57_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56483   GPIO_PINCFG57_NCESRC57_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56484   GPIO_PINCFG57_NCESRC57_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56485   GPIO_PINCFG57_NCESRC57_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56486   GPIO_PINCFG57_NCESRC57_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56487   GPIO_PINCFG57_NCESRC57_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56488   GPIO_PINCFG57_NCESRC57_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56489 } GPIO_PINCFG57_NCESRC57_Enum;
56490 
56491 /* ===========================================  GPIO PINCFG57 PULLCFG57 [13..15]  ============================================ */
56492 typedef enum {                                  /*!< GPIO_PINCFG57_PULLCFG57                                                   */
56493   GPIO_PINCFG57_PULLCFG57_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56494   GPIO_PINCFG57_PULLCFG57_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56495   GPIO_PINCFG57_PULLCFG57_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56496   GPIO_PINCFG57_PULLCFG57_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56497   GPIO_PINCFG57_PULLCFG57_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56498   GPIO_PINCFG57_PULLCFG57_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56499   GPIO_PINCFG57_PULLCFG57_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56500   GPIO_PINCFG57_PULLCFG57_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56501 } GPIO_PINCFG57_PULLCFG57_Enum;
56502 
56503 /* ==============================================  GPIO PINCFG57 DS57 [10..11]  ============================================== */
56504 typedef enum {                                  /*!< GPIO_PINCFG57_DS57                                                        */
56505   GPIO_PINCFG57_DS57_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56506   GPIO_PINCFG57_DS57_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56507   GPIO_PINCFG57_DS57_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56508   GPIO_PINCFG57_DS57_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56509 } GPIO_PINCFG57_DS57_Enum;
56510 
56511 /* =============================================  GPIO PINCFG57 OUTCFG57 [8..9]  ============================================= */
56512 typedef enum {                                  /*!< GPIO_PINCFG57_OUTCFG57                                                    */
56513   GPIO_PINCFG57_OUTCFG57_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56514   GPIO_PINCFG57_OUTCFG57_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56515                                                      and 1 values on pin.                                                      */
56516   GPIO_PINCFG57_OUTCFG57_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56517                                                      low, tristate otherwise.                                                  */
56518   GPIO_PINCFG57_OUTCFG57_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56519                                                      drive 0, 1 of HiZ on pin.                                                 */
56520 } GPIO_PINCFG57_OUTCFG57_Enum;
56521 
56522 /* =============================================  GPIO PINCFG57 IRPTEN57 [6..7]  ============================================= */
56523 typedef enum {                                  /*!< GPIO_PINCFG57_IRPTEN57                                                    */
56524   GPIO_PINCFG57_IRPTEN57_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56525   GPIO_PINCFG57_IRPTEN57_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56526                                                      on this GPIO                                                              */
56527   GPIO_PINCFG57_IRPTEN57_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56528                                                      on this GPIO                                                              */
56529   GPIO_PINCFG57_IRPTEN57_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56530                                                      GPIO                                                                      */
56531 } GPIO_PINCFG57_IRPTEN57_Enum;
56532 
56533 /* =============================================  GPIO PINCFG57 FNCSEL57 [0..3]  ============================================= */
56534 typedef enum {                                  /*!< GPIO_PINCFG57_FNCSEL57                                                    */
56535   GPIO_PINCFG57_FNCSEL57_PDM3_DATA     = 0,     /*!< PDM3_DATA : PDMx audio data input to chip (I2C Master/Slave
56536                                                      D)                                                                        */
56537   GPIO_PINCFG57_FNCSEL57_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
56538   GPIO_PINCFG57_FNCSEL57_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
56539   GPIO_PINCFG57_FNCSEL57_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56540   GPIO_PINCFG57_FNCSEL57_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
56541   GPIO_PINCFG57_FNCSEL57_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
56542   GPIO_PINCFG57_FNCSEL57_CT57          = 6,     /*!< CT57 : Timer/Counter input or output; Selection of direction
56543                                                      is done via CTIMER register settings.                                     */
56544   GPIO_PINCFG57_FNCSEL57_NCE57         = 7,     /*!< NCE57 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56545                                                      CE_POLARITY field                                                         */
56546   GPIO_PINCFG57_FNCSEL57_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
56547   GPIO_PINCFG57_FNCSEL57_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
56548   GPIO_PINCFG57_FNCSEL57_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56549   GPIO_PINCFG57_FNCSEL57_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56550   GPIO_PINCFG57_FNCSEL57_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56551   GPIO_PINCFG57_FNCSEL57_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56552   GPIO_PINCFG57_FNCSEL57_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56553   GPIO_PINCFG57_FNCSEL57_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56554 } GPIO_PINCFG57_FNCSEL57_Enum;
56555 
56556 /* =======================================================  PINCFG58  ======================================================== */
56557 /* ============================================  GPIO PINCFG58 NCEPOL58 [22..22]  ============================================ */
56558 typedef enum {                                  /*!< GPIO_PINCFG58_NCEPOL58                                                    */
56559   GPIO_PINCFG58_NCEPOL58_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56560   GPIO_PINCFG58_NCEPOL58_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56561 } GPIO_PINCFG58_NCEPOL58_Enum;
56562 
56563 /* ============================================  GPIO PINCFG58 NCESRC58 [16..21]  ============================================ */
56564 typedef enum {                                  /*!< GPIO_PINCFG58_NCESRC58                                                    */
56565   GPIO_PINCFG58_NCESRC58_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56566   GPIO_PINCFG58_NCESRC58_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56567   GPIO_PINCFG58_NCESRC58_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56568   GPIO_PINCFG58_NCESRC58_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56569   GPIO_PINCFG58_NCESRC58_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56570   GPIO_PINCFG58_NCESRC58_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56571   GPIO_PINCFG58_NCESRC58_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56572   GPIO_PINCFG58_NCESRC58_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56573   GPIO_PINCFG58_NCESRC58_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56574   GPIO_PINCFG58_NCESRC58_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56575   GPIO_PINCFG58_NCESRC58_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56576   GPIO_PINCFG58_NCESRC58_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56577   GPIO_PINCFG58_NCESRC58_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56578   GPIO_PINCFG58_NCESRC58_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56579   GPIO_PINCFG58_NCESRC58_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56580   GPIO_PINCFG58_NCESRC58_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56581   GPIO_PINCFG58_NCESRC58_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56582   GPIO_PINCFG58_NCESRC58_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56583   GPIO_PINCFG58_NCESRC58_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56584   GPIO_PINCFG58_NCESRC58_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56585   GPIO_PINCFG58_NCESRC58_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56586   GPIO_PINCFG58_NCESRC58_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56587   GPIO_PINCFG58_NCESRC58_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56588   GPIO_PINCFG58_NCESRC58_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56589   GPIO_PINCFG58_NCESRC58_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56590   GPIO_PINCFG58_NCESRC58_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56591   GPIO_PINCFG58_NCESRC58_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56592   GPIO_PINCFG58_NCESRC58_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56593   GPIO_PINCFG58_NCESRC58_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56594   GPIO_PINCFG58_NCESRC58_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56595   GPIO_PINCFG58_NCESRC58_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56596   GPIO_PINCFG58_NCESRC58_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56597   GPIO_PINCFG58_NCESRC58_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56598   GPIO_PINCFG58_NCESRC58_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56599   GPIO_PINCFG58_NCESRC58_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56600   GPIO_PINCFG58_NCESRC58_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56601   GPIO_PINCFG58_NCESRC58_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56602   GPIO_PINCFG58_NCESRC58_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56603   GPIO_PINCFG58_NCESRC58_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56604   GPIO_PINCFG58_NCESRC58_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56605   GPIO_PINCFG58_NCESRC58_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56606   GPIO_PINCFG58_NCESRC58_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56607   GPIO_PINCFG58_NCESRC58_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56608 } GPIO_PINCFG58_NCESRC58_Enum;
56609 
56610 /* ===========================================  GPIO PINCFG58 PULLCFG58 [13..15]  ============================================ */
56611 typedef enum {                                  /*!< GPIO_PINCFG58_PULLCFG58                                                   */
56612   GPIO_PINCFG58_PULLCFG58_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56613   GPIO_PINCFG58_PULLCFG58_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56614   GPIO_PINCFG58_PULLCFG58_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56615   GPIO_PINCFG58_PULLCFG58_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56616   GPIO_PINCFG58_PULLCFG58_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56617   GPIO_PINCFG58_PULLCFG58_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56618   GPIO_PINCFG58_PULLCFG58_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56619   GPIO_PINCFG58_PULLCFG58_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56620 } GPIO_PINCFG58_PULLCFG58_Enum;
56621 
56622 /* ==============================================  GPIO PINCFG58 DS58 [10..11]  ============================================== */
56623 typedef enum {                                  /*!< GPIO_PINCFG58_DS58                                                        */
56624   GPIO_PINCFG58_DS58_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56625   GPIO_PINCFG58_DS58_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56626 } GPIO_PINCFG58_DS58_Enum;
56627 
56628 /* =============================================  GPIO PINCFG58 OUTCFG58 [8..9]  ============================================= */
56629 typedef enum {                                  /*!< GPIO_PINCFG58_OUTCFG58                                                    */
56630   GPIO_PINCFG58_OUTCFG58_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56631   GPIO_PINCFG58_OUTCFG58_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56632                                                      and 1 values on pin.                                                      */
56633   GPIO_PINCFG58_OUTCFG58_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56634                                                      low, tristate otherwise.                                                  */
56635   GPIO_PINCFG58_OUTCFG58_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56636                                                      drive 0, 1 of HiZ on pin.                                                 */
56637 } GPIO_PINCFG58_OUTCFG58_Enum;
56638 
56639 /* =============================================  GPIO PINCFG58 IRPTEN58 [6..7]  ============================================= */
56640 typedef enum {                                  /*!< GPIO_PINCFG58_IRPTEN58                                                    */
56641   GPIO_PINCFG58_IRPTEN58_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56642   GPIO_PINCFG58_IRPTEN58_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56643                                                      on this GPIO                                                              */
56644   GPIO_PINCFG58_IRPTEN58_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56645                                                      on this GPIO                                                              */
56646   GPIO_PINCFG58_IRPTEN58_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56647                                                      GPIO                                                                      */
56648 } GPIO_PINCFG58_IRPTEN58_Enum;
56649 
56650 /* =============================================  GPIO PINCFG58 FNCSEL58 [0..3]  ============================================= */
56651 typedef enum {                                  /*!< GPIO_PINCFG58_FNCSEL58                                                    */
56652   GPIO_PINCFG58_FNCSEL58_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
56653   GPIO_PINCFG58_FNCSEL58_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
56654   GPIO_PINCFG58_FNCSEL58_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
56655   GPIO_PINCFG58_FNCSEL58_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56656   GPIO_PINCFG58_FNCSEL58_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
56657   GPIO_PINCFG58_FNCSEL58_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
56658   GPIO_PINCFG58_FNCSEL58_CT58          = 6,     /*!< CT58 : Timer/Counter input or output; Selection of direction
56659                                                      is done via CTIMER register settings.                                     */
56660   GPIO_PINCFG58_FNCSEL58_NCE58         = 7,     /*!< NCE58 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56661                                                      CE_POLARITY field                                                         */
56662   GPIO_PINCFG58_FNCSEL58_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
56663   GPIO_PINCFG58_FNCSEL58_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56664   GPIO_PINCFG58_FNCSEL58_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56665   GPIO_PINCFG58_FNCSEL58_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56666   GPIO_PINCFG58_FNCSEL58_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56667   GPIO_PINCFG58_FNCSEL58_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56668   GPIO_PINCFG58_FNCSEL58_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56669   GPIO_PINCFG58_FNCSEL58_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56670 } GPIO_PINCFG58_FNCSEL58_Enum;
56671 
56672 /* =======================================================  PINCFG59  ======================================================== */
56673 /* ============================================  GPIO PINCFG59 NCEPOL59 [22..22]  ============================================ */
56674 typedef enum {                                  /*!< GPIO_PINCFG59_NCEPOL59                                                    */
56675   GPIO_PINCFG59_NCEPOL59_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56676   GPIO_PINCFG59_NCEPOL59_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56677 } GPIO_PINCFG59_NCEPOL59_Enum;
56678 
56679 /* ============================================  GPIO PINCFG59 NCESRC59 [16..21]  ============================================ */
56680 typedef enum {                                  /*!< GPIO_PINCFG59_NCESRC59                                                    */
56681   GPIO_PINCFG59_NCESRC59_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56682   GPIO_PINCFG59_NCESRC59_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56683   GPIO_PINCFG59_NCESRC59_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56684   GPIO_PINCFG59_NCESRC59_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56685   GPIO_PINCFG59_NCESRC59_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56686   GPIO_PINCFG59_NCESRC59_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56687   GPIO_PINCFG59_NCESRC59_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56688   GPIO_PINCFG59_NCESRC59_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56689   GPIO_PINCFG59_NCESRC59_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56690   GPIO_PINCFG59_NCESRC59_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56691   GPIO_PINCFG59_NCESRC59_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56692   GPIO_PINCFG59_NCESRC59_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56693   GPIO_PINCFG59_NCESRC59_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56694   GPIO_PINCFG59_NCESRC59_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56695   GPIO_PINCFG59_NCESRC59_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56696   GPIO_PINCFG59_NCESRC59_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56697   GPIO_PINCFG59_NCESRC59_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56698   GPIO_PINCFG59_NCESRC59_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56699   GPIO_PINCFG59_NCESRC59_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56700   GPIO_PINCFG59_NCESRC59_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56701   GPIO_PINCFG59_NCESRC59_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56702   GPIO_PINCFG59_NCESRC59_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56703   GPIO_PINCFG59_NCESRC59_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56704   GPIO_PINCFG59_NCESRC59_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56705   GPIO_PINCFG59_NCESRC59_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56706   GPIO_PINCFG59_NCESRC59_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56707   GPIO_PINCFG59_NCESRC59_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56708   GPIO_PINCFG59_NCESRC59_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56709   GPIO_PINCFG59_NCESRC59_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56710   GPIO_PINCFG59_NCESRC59_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56711   GPIO_PINCFG59_NCESRC59_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56712   GPIO_PINCFG59_NCESRC59_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56713   GPIO_PINCFG59_NCESRC59_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56714   GPIO_PINCFG59_NCESRC59_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56715   GPIO_PINCFG59_NCESRC59_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56716   GPIO_PINCFG59_NCESRC59_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56717   GPIO_PINCFG59_NCESRC59_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56718   GPIO_PINCFG59_NCESRC59_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56719   GPIO_PINCFG59_NCESRC59_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56720   GPIO_PINCFG59_NCESRC59_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56721   GPIO_PINCFG59_NCESRC59_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56722   GPIO_PINCFG59_NCESRC59_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56723   GPIO_PINCFG59_NCESRC59_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56724 } GPIO_PINCFG59_NCESRC59_Enum;
56725 
56726 /* ===========================================  GPIO PINCFG59 PULLCFG59 [13..15]  ============================================ */
56727 typedef enum {                                  /*!< GPIO_PINCFG59_PULLCFG59                                                   */
56728   GPIO_PINCFG59_PULLCFG59_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56729   GPIO_PINCFG59_PULLCFG59_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56730   GPIO_PINCFG59_PULLCFG59_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56731   GPIO_PINCFG59_PULLCFG59_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56732   GPIO_PINCFG59_PULLCFG59_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56733   GPIO_PINCFG59_PULLCFG59_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56734   GPIO_PINCFG59_PULLCFG59_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56735   GPIO_PINCFG59_PULLCFG59_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56736 } GPIO_PINCFG59_PULLCFG59_Enum;
56737 
56738 /* ==============================================  GPIO PINCFG59 DS59 [10..11]  ============================================== */
56739 typedef enum {                                  /*!< GPIO_PINCFG59_DS59                                                        */
56740   GPIO_PINCFG59_DS59_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56741   GPIO_PINCFG59_DS59_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56742 } GPIO_PINCFG59_DS59_Enum;
56743 
56744 /* =============================================  GPIO PINCFG59 OUTCFG59 [8..9]  ============================================= */
56745 typedef enum {                                  /*!< GPIO_PINCFG59_OUTCFG59                                                    */
56746   GPIO_PINCFG59_OUTCFG59_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56747   GPIO_PINCFG59_OUTCFG59_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56748                                                      and 1 values on pin.                                                      */
56749   GPIO_PINCFG59_OUTCFG59_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56750                                                      low, tristate otherwise.                                                  */
56751   GPIO_PINCFG59_OUTCFG59_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56752                                                      drive 0, 1 of HiZ on pin.                                                 */
56753 } GPIO_PINCFG59_OUTCFG59_Enum;
56754 
56755 /* =============================================  GPIO PINCFG59 IRPTEN59 [6..7]  ============================================= */
56756 typedef enum {                                  /*!< GPIO_PINCFG59_IRPTEN59                                                    */
56757   GPIO_PINCFG59_IRPTEN59_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56758   GPIO_PINCFG59_IRPTEN59_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56759                                                      on this GPIO                                                              */
56760   GPIO_PINCFG59_IRPTEN59_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56761                                                      on this GPIO                                                              */
56762   GPIO_PINCFG59_IRPTEN59_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56763                                                      GPIO                                                                      */
56764 } GPIO_PINCFG59_IRPTEN59_Enum;
56765 
56766 /* =============================================  GPIO PINCFG59 FNCSEL59 [0..3]  ============================================= */
56767 typedef enum {                                  /*!< GPIO_PINCFG59_FNCSEL59                                                    */
56768   GPIO_PINCFG59_FNCSEL59_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
56769   GPIO_PINCFG59_FNCSEL59_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
56770   GPIO_PINCFG59_FNCSEL59_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
56771   GPIO_PINCFG59_FNCSEL59_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56772   GPIO_PINCFG59_FNCSEL59_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
56773   GPIO_PINCFG59_FNCSEL59_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
56774   GPIO_PINCFG59_FNCSEL59_CT59          = 6,     /*!< CT59 : Timer/Counter input or output; Selection of direction
56775                                                      is done via CTIMER register settings.                                     */
56776   GPIO_PINCFG59_FNCSEL59_NCE59         = 7,     /*!< NCE59 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56777                                                      CE_POLARITY field                                                         */
56778   GPIO_PINCFG59_FNCSEL59_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
56779   GPIO_PINCFG59_FNCSEL59_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56780   GPIO_PINCFG59_FNCSEL59_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56781   GPIO_PINCFG59_FNCSEL59_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56782   GPIO_PINCFG59_FNCSEL59_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56783   GPIO_PINCFG59_FNCSEL59_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56784   GPIO_PINCFG59_FNCSEL59_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56785   GPIO_PINCFG59_FNCSEL59_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56786 } GPIO_PINCFG59_FNCSEL59_Enum;
56787 
56788 /* =======================================================  PINCFG60  ======================================================== */
56789 /* ============================================  GPIO PINCFG60 NCEPOL60 [22..22]  ============================================ */
56790 typedef enum {                                  /*!< GPIO_PINCFG60_NCEPOL60                                                    */
56791   GPIO_PINCFG60_NCEPOL60_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56792   GPIO_PINCFG60_NCEPOL60_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56793 } GPIO_PINCFG60_NCEPOL60_Enum;
56794 
56795 /* ============================================  GPIO PINCFG60 NCESRC60 [16..21]  ============================================ */
56796 typedef enum {                                  /*!< GPIO_PINCFG60_NCESRC60                                                    */
56797   GPIO_PINCFG60_NCESRC60_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56798   GPIO_PINCFG60_NCESRC60_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56799   GPIO_PINCFG60_NCESRC60_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56800   GPIO_PINCFG60_NCESRC60_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56801   GPIO_PINCFG60_NCESRC60_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56802   GPIO_PINCFG60_NCESRC60_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56803   GPIO_PINCFG60_NCESRC60_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56804   GPIO_PINCFG60_NCESRC60_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56805   GPIO_PINCFG60_NCESRC60_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56806   GPIO_PINCFG60_NCESRC60_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56807   GPIO_PINCFG60_NCESRC60_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56808   GPIO_PINCFG60_NCESRC60_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56809   GPIO_PINCFG60_NCESRC60_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56810   GPIO_PINCFG60_NCESRC60_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56811   GPIO_PINCFG60_NCESRC60_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56812   GPIO_PINCFG60_NCESRC60_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56813   GPIO_PINCFG60_NCESRC60_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56814   GPIO_PINCFG60_NCESRC60_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56815   GPIO_PINCFG60_NCESRC60_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56816   GPIO_PINCFG60_NCESRC60_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56817   GPIO_PINCFG60_NCESRC60_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56818   GPIO_PINCFG60_NCESRC60_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56819   GPIO_PINCFG60_NCESRC60_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56820   GPIO_PINCFG60_NCESRC60_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56821   GPIO_PINCFG60_NCESRC60_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56822   GPIO_PINCFG60_NCESRC60_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56823   GPIO_PINCFG60_NCESRC60_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56824   GPIO_PINCFG60_NCESRC60_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56825   GPIO_PINCFG60_NCESRC60_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56826   GPIO_PINCFG60_NCESRC60_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56827   GPIO_PINCFG60_NCESRC60_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56828   GPIO_PINCFG60_NCESRC60_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56829   GPIO_PINCFG60_NCESRC60_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56830   GPIO_PINCFG60_NCESRC60_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56831   GPIO_PINCFG60_NCESRC60_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56832   GPIO_PINCFG60_NCESRC60_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56833   GPIO_PINCFG60_NCESRC60_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56834   GPIO_PINCFG60_NCESRC60_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56835   GPIO_PINCFG60_NCESRC60_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56836   GPIO_PINCFG60_NCESRC60_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56837   GPIO_PINCFG60_NCESRC60_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56838   GPIO_PINCFG60_NCESRC60_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56839   GPIO_PINCFG60_NCESRC60_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56840 } GPIO_PINCFG60_NCESRC60_Enum;
56841 
56842 /* ===========================================  GPIO PINCFG60 PULLCFG60 [13..15]  ============================================ */
56843 typedef enum {                                  /*!< GPIO_PINCFG60_PULLCFG60                                                   */
56844   GPIO_PINCFG60_PULLCFG60_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56845   GPIO_PINCFG60_PULLCFG60_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56846   GPIO_PINCFG60_PULLCFG60_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56847   GPIO_PINCFG60_PULLCFG60_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56848   GPIO_PINCFG60_PULLCFG60_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56849   GPIO_PINCFG60_PULLCFG60_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56850   GPIO_PINCFG60_PULLCFG60_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56851   GPIO_PINCFG60_PULLCFG60_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56852 } GPIO_PINCFG60_PULLCFG60_Enum;
56853 
56854 /* ==============================================  GPIO PINCFG60 DS60 [10..11]  ============================================== */
56855 typedef enum {                                  /*!< GPIO_PINCFG60_DS60                                                        */
56856   GPIO_PINCFG60_DS60_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56857   GPIO_PINCFG60_DS60_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56858 } GPIO_PINCFG60_DS60_Enum;
56859 
56860 /* =============================================  GPIO PINCFG60 OUTCFG60 [8..9]  ============================================= */
56861 typedef enum {                                  /*!< GPIO_PINCFG60_OUTCFG60                                                    */
56862   GPIO_PINCFG60_OUTCFG60_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56863   GPIO_PINCFG60_OUTCFG60_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56864                                                      and 1 values on pin.                                                      */
56865   GPIO_PINCFG60_OUTCFG60_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56866                                                      low, tristate otherwise.                                                  */
56867   GPIO_PINCFG60_OUTCFG60_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56868                                                      drive 0, 1 of HiZ on pin.                                                 */
56869 } GPIO_PINCFG60_OUTCFG60_Enum;
56870 
56871 /* =============================================  GPIO PINCFG60 IRPTEN60 [6..7]  ============================================= */
56872 typedef enum {                                  /*!< GPIO_PINCFG60_IRPTEN60                                                    */
56873   GPIO_PINCFG60_IRPTEN60_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56874   GPIO_PINCFG60_IRPTEN60_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56875                                                      on this GPIO                                                              */
56876   GPIO_PINCFG60_IRPTEN60_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56877                                                      on this GPIO                                                              */
56878   GPIO_PINCFG60_IRPTEN60_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56879                                                      GPIO                                                                      */
56880 } GPIO_PINCFG60_IRPTEN60_Enum;
56881 
56882 /* =============================================  GPIO PINCFG60 FNCSEL60 [0..3]  ============================================= */
56883 typedef enum {                                  /*!< GPIO_PINCFG60_FNCSEL60                                                    */
56884   GPIO_PINCFG60_FNCSEL60_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
56885   GPIO_PINCFG60_FNCSEL60_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
56886   GPIO_PINCFG60_FNCSEL60_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
56887   GPIO_PINCFG60_FNCSEL60_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56888   GPIO_PINCFG60_FNCSEL60_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
56889   GPIO_PINCFG60_FNCSEL60_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
56890   GPIO_PINCFG60_FNCSEL60_CT60          = 6,     /*!< CT60 : Timer/Counter input or output; Selection of direction
56891                                                      is done via CTIMER register settings.                                     */
56892   GPIO_PINCFG60_FNCSEL60_NCE60         = 7,     /*!< NCE60 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56893                                                      CE_POLARITY field                                                         */
56894   GPIO_PINCFG60_FNCSEL60_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
56895   GPIO_PINCFG60_FNCSEL60_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56896   GPIO_PINCFG60_FNCSEL60_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56897   GPIO_PINCFG60_FNCSEL60_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56898   GPIO_PINCFG60_FNCSEL60_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56899   GPIO_PINCFG60_FNCSEL60_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56900   GPIO_PINCFG60_FNCSEL60_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56901   GPIO_PINCFG60_FNCSEL60_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56902 } GPIO_PINCFG60_FNCSEL60_Enum;
56903 
56904 /* =======================================================  PINCFG61  ======================================================== */
56905 /* ============================================  GPIO PINCFG61 NCEPOL61 [22..22]  ============================================ */
56906 typedef enum {                                  /*!< GPIO_PINCFG61_NCEPOL61                                                    */
56907   GPIO_PINCFG61_NCEPOL61_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56908   GPIO_PINCFG61_NCEPOL61_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56909 } GPIO_PINCFG61_NCEPOL61_Enum;
56910 
56911 /* ============================================  GPIO PINCFG61 NCESRC61 [16..21]  ============================================ */
56912 typedef enum {                                  /*!< GPIO_PINCFG61_NCESRC61                                                    */
56913   GPIO_PINCFG61_NCESRC61_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56914   GPIO_PINCFG61_NCESRC61_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56915   GPIO_PINCFG61_NCESRC61_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56916   GPIO_PINCFG61_NCESRC61_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56917   GPIO_PINCFG61_NCESRC61_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56918   GPIO_PINCFG61_NCESRC61_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56919   GPIO_PINCFG61_NCESRC61_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56920   GPIO_PINCFG61_NCESRC61_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56921   GPIO_PINCFG61_NCESRC61_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56922   GPIO_PINCFG61_NCESRC61_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56923   GPIO_PINCFG61_NCESRC61_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56924   GPIO_PINCFG61_NCESRC61_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56925   GPIO_PINCFG61_NCESRC61_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56926   GPIO_PINCFG61_NCESRC61_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56927   GPIO_PINCFG61_NCESRC61_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56928   GPIO_PINCFG61_NCESRC61_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56929   GPIO_PINCFG61_NCESRC61_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56930   GPIO_PINCFG61_NCESRC61_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56931   GPIO_PINCFG61_NCESRC61_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56932   GPIO_PINCFG61_NCESRC61_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56933   GPIO_PINCFG61_NCESRC61_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56934   GPIO_PINCFG61_NCESRC61_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56935   GPIO_PINCFG61_NCESRC61_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56936   GPIO_PINCFG61_NCESRC61_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56937   GPIO_PINCFG61_NCESRC61_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56938   GPIO_PINCFG61_NCESRC61_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56939   GPIO_PINCFG61_NCESRC61_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56940   GPIO_PINCFG61_NCESRC61_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56941   GPIO_PINCFG61_NCESRC61_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56942   GPIO_PINCFG61_NCESRC61_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56943   GPIO_PINCFG61_NCESRC61_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56944   GPIO_PINCFG61_NCESRC61_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56945   GPIO_PINCFG61_NCESRC61_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56946   GPIO_PINCFG61_NCESRC61_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56947   GPIO_PINCFG61_NCESRC61_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56948   GPIO_PINCFG61_NCESRC61_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56949   GPIO_PINCFG61_NCESRC61_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56950   GPIO_PINCFG61_NCESRC61_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56951   GPIO_PINCFG61_NCESRC61_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56952   GPIO_PINCFG61_NCESRC61_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56953   GPIO_PINCFG61_NCESRC61_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56954   GPIO_PINCFG61_NCESRC61_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56955   GPIO_PINCFG61_NCESRC61_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56956 } GPIO_PINCFG61_NCESRC61_Enum;
56957 
56958 /* ===========================================  GPIO PINCFG61 PULLCFG61 [13..15]  ============================================ */
56959 typedef enum {                                  /*!< GPIO_PINCFG61_PULLCFG61                                                   */
56960   GPIO_PINCFG61_PULLCFG61_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56961   GPIO_PINCFG61_PULLCFG61_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56962   GPIO_PINCFG61_PULLCFG61_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56963   GPIO_PINCFG61_PULLCFG61_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56964   GPIO_PINCFG61_PULLCFG61_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56965   GPIO_PINCFG61_PULLCFG61_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56966   GPIO_PINCFG61_PULLCFG61_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56967   GPIO_PINCFG61_PULLCFG61_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56968 } GPIO_PINCFG61_PULLCFG61_Enum;
56969 
56970 /* ==============================================  GPIO PINCFG61 DS61 [10..11]  ============================================== */
56971 typedef enum {                                  /*!< GPIO_PINCFG61_DS61                                                        */
56972   GPIO_PINCFG61_DS61_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56973   GPIO_PINCFG61_DS61_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56974   GPIO_PINCFG61_DS61_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56975   GPIO_PINCFG61_DS61_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56976 } GPIO_PINCFG61_DS61_Enum;
56977 
56978 /* =============================================  GPIO PINCFG61 OUTCFG61 [8..9]  ============================================= */
56979 typedef enum {                                  /*!< GPIO_PINCFG61_OUTCFG61                                                    */
56980   GPIO_PINCFG61_OUTCFG61_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56981   GPIO_PINCFG61_OUTCFG61_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56982                                                      and 1 values on pin.                                                      */
56983   GPIO_PINCFG61_OUTCFG61_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56984                                                      low, tristate otherwise.                                                  */
56985   GPIO_PINCFG61_OUTCFG61_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56986                                                      drive 0, 1 of HiZ on pin.                                                 */
56987 } GPIO_PINCFG61_OUTCFG61_Enum;
56988 
56989 /* =============================================  GPIO PINCFG61 IRPTEN61 [6..7]  ============================================= */
56990 typedef enum {                                  /*!< GPIO_PINCFG61_IRPTEN61                                                    */
56991   GPIO_PINCFG61_IRPTEN61_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56992   GPIO_PINCFG61_IRPTEN61_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56993                                                      on this GPIO                                                              */
56994   GPIO_PINCFG61_IRPTEN61_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56995                                                      on this GPIO                                                              */
56996   GPIO_PINCFG61_IRPTEN61_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56997                                                      GPIO                                                                      */
56998 } GPIO_PINCFG61_IRPTEN61_Enum;
56999 
57000 /* =============================================  GPIO PINCFG61 FNCSEL61 [0..3]  ============================================= */
57001 typedef enum {                                  /*!< GPIO_PINCFG61_FNCSEL61                                                    */
57002   GPIO_PINCFG61_FNCSEL61_M6SCL         = 0,     /*!< M6SCL : Serial I2C Master Clock output (IOM 6)                            */
57003   GPIO_PINCFG61_FNCSEL61_M6SCK         = 1,     /*!< M6SCK : Serial SPI Master Clock output (IOM 6)                            */
57004   GPIO_PINCFG61_FNCSEL61_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
57005                                                      in master mode and input mode for slave mode. (I2S Master/Slave
57006                                                      2)                                                                        */
57007   GPIO_PINCFG61_FNCSEL61_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57008   GPIO_PINCFG61_FNCSEL61_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
57009   GPIO_PINCFG61_FNCSEL61_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
57010   GPIO_PINCFG61_FNCSEL61_CT61          = 6,     /*!< CT61 : Timer/Counter input or output; Selection of direction
57011                                                      is done via CTIMER register settings.                                     */
57012   GPIO_PINCFG61_FNCSEL61_NCE61         = 7,     /*!< NCE61 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57013                                                      CE_POLARITY field                                                         */
57014   GPIO_PINCFG61_FNCSEL61_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
57015   GPIO_PINCFG61_FNCSEL61_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57016   GPIO_PINCFG61_FNCSEL61_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57017   GPIO_PINCFG61_FNCSEL61_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57018   GPIO_PINCFG61_FNCSEL61_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57019   GPIO_PINCFG61_FNCSEL61_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57020   GPIO_PINCFG61_FNCSEL61_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57021 } GPIO_PINCFG61_FNCSEL61_Enum;
57022 
57023 /* =======================================================  PINCFG62  ======================================================== */
57024 /* ============================================  GPIO PINCFG62 NCEPOL62 [22..22]  ============================================ */
57025 typedef enum {                                  /*!< GPIO_PINCFG62_NCEPOL62                                                    */
57026   GPIO_PINCFG62_NCEPOL62_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57027   GPIO_PINCFG62_NCEPOL62_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57028 } GPIO_PINCFG62_NCEPOL62_Enum;
57029 
57030 /* ============================================  GPIO PINCFG62 NCESRC62 [16..21]  ============================================ */
57031 typedef enum {                                  /*!< GPIO_PINCFG62_NCESRC62                                                    */
57032   GPIO_PINCFG62_NCESRC62_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57033   GPIO_PINCFG62_NCESRC62_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57034   GPIO_PINCFG62_NCESRC62_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57035   GPIO_PINCFG62_NCESRC62_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57036   GPIO_PINCFG62_NCESRC62_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57037   GPIO_PINCFG62_NCESRC62_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57038   GPIO_PINCFG62_NCESRC62_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57039   GPIO_PINCFG62_NCESRC62_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57040   GPIO_PINCFG62_NCESRC62_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57041   GPIO_PINCFG62_NCESRC62_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57042   GPIO_PINCFG62_NCESRC62_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57043   GPIO_PINCFG62_NCESRC62_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57044   GPIO_PINCFG62_NCESRC62_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57045   GPIO_PINCFG62_NCESRC62_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57046   GPIO_PINCFG62_NCESRC62_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57047   GPIO_PINCFG62_NCESRC62_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57048   GPIO_PINCFG62_NCESRC62_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57049   GPIO_PINCFG62_NCESRC62_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57050   GPIO_PINCFG62_NCESRC62_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57051   GPIO_PINCFG62_NCESRC62_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57052   GPIO_PINCFG62_NCESRC62_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57053   GPIO_PINCFG62_NCESRC62_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57054   GPIO_PINCFG62_NCESRC62_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57055   GPIO_PINCFG62_NCESRC62_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57056   GPIO_PINCFG62_NCESRC62_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57057   GPIO_PINCFG62_NCESRC62_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57058   GPIO_PINCFG62_NCESRC62_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57059   GPIO_PINCFG62_NCESRC62_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57060   GPIO_PINCFG62_NCESRC62_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57061   GPIO_PINCFG62_NCESRC62_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57062   GPIO_PINCFG62_NCESRC62_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57063   GPIO_PINCFG62_NCESRC62_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57064   GPIO_PINCFG62_NCESRC62_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57065   GPIO_PINCFG62_NCESRC62_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57066   GPIO_PINCFG62_NCESRC62_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57067   GPIO_PINCFG62_NCESRC62_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57068   GPIO_PINCFG62_NCESRC62_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57069   GPIO_PINCFG62_NCESRC62_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57070   GPIO_PINCFG62_NCESRC62_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57071   GPIO_PINCFG62_NCESRC62_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57072   GPIO_PINCFG62_NCESRC62_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57073   GPIO_PINCFG62_NCESRC62_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57074   GPIO_PINCFG62_NCESRC62_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57075 } GPIO_PINCFG62_NCESRC62_Enum;
57076 
57077 /* ===========================================  GPIO PINCFG62 PULLCFG62 [13..15]  ============================================ */
57078 typedef enum {                                  /*!< GPIO_PINCFG62_PULLCFG62                                                   */
57079   GPIO_PINCFG62_PULLCFG62_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57080   GPIO_PINCFG62_PULLCFG62_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57081   GPIO_PINCFG62_PULLCFG62_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57082   GPIO_PINCFG62_PULLCFG62_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57083   GPIO_PINCFG62_PULLCFG62_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57084   GPIO_PINCFG62_PULLCFG62_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57085   GPIO_PINCFG62_PULLCFG62_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57086   GPIO_PINCFG62_PULLCFG62_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57087 } GPIO_PINCFG62_PULLCFG62_Enum;
57088 
57089 /* ==============================================  GPIO PINCFG62 DS62 [10..11]  ============================================== */
57090 typedef enum {                                  /*!< GPIO_PINCFG62_DS62                                                        */
57091   GPIO_PINCFG62_DS62_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57092   GPIO_PINCFG62_DS62_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57093   GPIO_PINCFG62_DS62_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57094   GPIO_PINCFG62_DS62_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57095 } GPIO_PINCFG62_DS62_Enum;
57096 
57097 /* =============================================  GPIO PINCFG62 OUTCFG62 [8..9]  ============================================= */
57098 typedef enum {                                  /*!< GPIO_PINCFG62_OUTCFG62                                                    */
57099   GPIO_PINCFG62_OUTCFG62_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57100   GPIO_PINCFG62_OUTCFG62_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57101                                                      and 1 values on pin.                                                      */
57102   GPIO_PINCFG62_OUTCFG62_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57103                                                      low, tristate otherwise.                                                  */
57104   GPIO_PINCFG62_OUTCFG62_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57105                                                      drive 0, 1 of HiZ on pin.                                                 */
57106 } GPIO_PINCFG62_OUTCFG62_Enum;
57107 
57108 /* =============================================  GPIO PINCFG62 IRPTEN62 [6..7]  ============================================= */
57109 typedef enum {                                  /*!< GPIO_PINCFG62_IRPTEN62                                                    */
57110   GPIO_PINCFG62_IRPTEN62_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57111   GPIO_PINCFG62_IRPTEN62_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57112                                                      on this GPIO                                                              */
57113   GPIO_PINCFG62_IRPTEN62_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57114                                                      on this GPIO                                                              */
57115   GPIO_PINCFG62_IRPTEN62_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57116                                                      GPIO                                                                      */
57117 } GPIO_PINCFG62_IRPTEN62_Enum;
57118 
57119 /* =============================================  GPIO PINCFG62 FNCSEL62 [0..3]  ============================================= */
57120 typedef enum {                                  /*!< GPIO_PINCFG62_FNCSEL62                                                    */
57121   GPIO_PINCFG62_FNCSEL62_M6SDAWIR3     = 0,     /*!< M6SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
57122                                                      Master Data I/O (SPI 3 wire mode) (IOM 6)                                 */
57123   GPIO_PINCFG62_FNCSEL62_M6MOSI        = 1,     /*!< M6MOSI : Serial SPI Master MOSI output (IOM 6)                            */
57124   GPIO_PINCFG62_FNCSEL62_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
57125                                                      in master mode and input mode for slave mode. (I2S Master/Slave
57126                                                      2)                                                                        */
57127   GPIO_PINCFG62_FNCSEL62_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57128   GPIO_PINCFG62_FNCSEL62_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
57129   GPIO_PINCFG62_FNCSEL62_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
57130   GPIO_PINCFG62_FNCSEL62_CT62          = 6,     /*!< CT62 : Timer/Counter input or output; Selection of direction
57131                                                      is done via CTIMER register settings.                                     */
57132   GPIO_PINCFG62_FNCSEL62_NCE62         = 7,     /*!< NCE62 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57133                                                      CE_POLARITY field                                                         */
57134   GPIO_PINCFG62_FNCSEL62_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
57135   GPIO_PINCFG62_FNCSEL62_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
57136   GPIO_PINCFG62_FNCSEL62_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57137   GPIO_PINCFG62_FNCSEL62_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57138   GPIO_PINCFG62_FNCSEL62_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57139   GPIO_PINCFG62_FNCSEL62_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57140   GPIO_PINCFG62_FNCSEL62_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57141 } GPIO_PINCFG62_FNCSEL62_Enum;
57142 
57143 /* =======================================================  PINCFG63  ======================================================== */
57144 /* ============================================  GPIO PINCFG63 NCEPOL63 [22..22]  ============================================ */
57145 typedef enum {                                  /*!< GPIO_PINCFG63_NCEPOL63                                                    */
57146   GPIO_PINCFG63_NCEPOL63_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57147   GPIO_PINCFG63_NCEPOL63_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57148 } GPIO_PINCFG63_NCEPOL63_Enum;
57149 
57150 /* ============================================  GPIO PINCFG63 NCESRC63 [16..21]  ============================================ */
57151 typedef enum {                                  /*!< GPIO_PINCFG63_NCESRC63                                                    */
57152   GPIO_PINCFG63_NCESRC63_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57153   GPIO_PINCFG63_NCESRC63_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57154   GPIO_PINCFG63_NCESRC63_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57155   GPIO_PINCFG63_NCESRC63_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57156   GPIO_PINCFG63_NCESRC63_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57157   GPIO_PINCFG63_NCESRC63_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57158   GPIO_PINCFG63_NCESRC63_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57159   GPIO_PINCFG63_NCESRC63_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57160   GPIO_PINCFG63_NCESRC63_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57161   GPIO_PINCFG63_NCESRC63_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57162   GPIO_PINCFG63_NCESRC63_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57163   GPIO_PINCFG63_NCESRC63_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57164   GPIO_PINCFG63_NCESRC63_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57165   GPIO_PINCFG63_NCESRC63_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57166   GPIO_PINCFG63_NCESRC63_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57167   GPIO_PINCFG63_NCESRC63_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57168   GPIO_PINCFG63_NCESRC63_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57169   GPIO_PINCFG63_NCESRC63_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57170   GPIO_PINCFG63_NCESRC63_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57171   GPIO_PINCFG63_NCESRC63_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57172   GPIO_PINCFG63_NCESRC63_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57173   GPIO_PINCFG63_NCESRC63_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57174   GPIO_PINCFG63_NCESRC63_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57175   GPIO_PINCFG63_NCESRC63_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57176   GPIO_PINCFG63_NCESRC63_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57177   GPIO_PINCFG63_NCESRC63_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57178   GPIO_PINCFG63_NCESRC63_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57179   GPIO_PINCFG63_NCESRC63_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57180   GPIO_PINCFG63_NCESRC63_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57181   GPIO_PINCFG63_NCESRC63_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57182   GPIO_PINCFG63_NCESRC63_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57183   GPIO_PINCFG63_NCESRC63_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57184   GPIO_PINCFG63_NCESRC63_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57185   GPIO_PINCFG63_NCESRC63_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57186   GPIO_PINCFG63_NCESRC63_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57187   GPIO_PINCFG63_NCESRC63_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57188   GPIO_PINCFG63_NCESRC63_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57189   GPIO_PINCFG63_NCESRC63_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57190   GPIO_PINCFG63_NCESRC63_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57191   GPIO_PINCFG63_NCESRC63_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57192   GPIO_PINCFG63_NCESRC63_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57193   GPIO_PINCFG63_NCESRC63_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57194   GPIO_PINCFG63_NCESRC63_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57195 } GPIO_PINCFG63_NCESRC63_Enum;
57196 
57197 /* ===========================================  GPIO PINCFG63 PULLCFG63 [13..15]  ============================================ */
57198 typedef enum {                                  /*!< GPIO_PINCFG63_PULLCFG63                                                   */
57199   GPIO_PINCFG63_PULLCFG63_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57200   GPIO_PINCFG63_PULLCFG63_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57201   GPIO_PINCFG63_PULLCFG63_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57202   GPIO_PINCFG63_PULLCFG63_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57203   GPIO_PINCFG63_PULLCFG63_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57204   GPIO_PINCFG63_PULLCFG63_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57205   GPIO_PINCFG63_PULLCFG63_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57206   GPIO_PINCFG63_PULLCFG63_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57207 } GPIO_PINCFG63_PULLCFG63_Enum;
57208 
57209 /* ==============================================  GPIO PINCFG63 DS63 [10..11]  ============================================== */
57210 typedef enum {                                  /*!< GPIO_PINCFG63_DS63                                                        */
57211   GPIO_PINCFG63_DS63_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57212   GPIO_PINCFG63_DS63_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57213   GPIO_PINCFG63_DS63_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57214   GPIO_PINCFG63_DS63_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57215 } GPIO_PINCFG63_DS63_Enum;
57216 
57217 /* =============================================  GPIO PINCFG63 OUTCFG63 [8..9]  ============================================= */
57218 typedef enum {                                  /*!< GPIO_PINCFG63_OUTCFG63                                                    */
57219   GPIO_PINCFG63_OUTCFG63_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57220   GPIO_PINCFG63_OUTCFG63_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57221                                                      and 1 values on pin.                                                      */
57222   GPIO_PINCFG63_OUTCFG63_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57223                                                      low, tristate otherwise.                                                  */
57224   GPIO_PINCFG63_OUTCFG63_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57225                                                      drive 0, 1 of HiZ on pin.                                                 */
57226 } GPIO_PINCFG63_OUTCFG63_Enum;
57227 
57228 /* =============================================  GPIO PINCFG63 IRPTEN63 [6..7]  ============================================= */
57229 typedef enum {                                  /*!< GPIO_PINCFG63_IRPTEN63                                                    */
57230   GPIO_PINCFG63_IRPTEN63_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57231   GPIO_PINCFG63_IRPTEN63_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57232                                                      on this GPIO                                                              */
57233   GPIO_PINCFG63_IRPTEN63_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57234                                                      on this GPIO                                                              */
57235   GPIO_PINCFG63_IRPTEN63_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57236                                                      GPIO                                                                      */
57237 } GPIO_PINCFG63_IRPTEN63_Enum;
57238 
57239 /* =============================================  GPIO PINCFG63 FNCSEL63 [0..3]  ============================================= */
57240 typedef enum {                                  /*!< GPIO_PINCFG63_FNCSEL63                                                    */
57241   GPIO_PINCFG63_FNCSEL63_M6MISO        = 0,     /*!< M6MISO : Serial SPI MASTER MISO input (IOM 6)                             */
57242   GPIO_PINCFG63_FNCSEL63_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
57243   GPIO_PINCFG63_FNCSEL63_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
57244                                                      in master mode and input mode for slave mode. (I2S Master/Slave
57245                                                      2)                                                                        */
57246   GPIO_PINCFG63_FNCSEL63_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57247   GPIO_PINCFG63_FNCSEL63_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
57248   GPIO_PINCFG63_FNCSEL63_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
57249   GPIO_PINCFG63_FNCSEL63_CT63          = 6,     /*!< CT63 : Timer/Counter input or output; Selection of direction
57250                                                      is done via CTIMER register settings.                                     */
57251   GPIO_PINCFG63_FNCSEL63_NCE63         = 7,     /*!< NCE63 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57252                                                      CE_POLARITY field                                                         */
57253   GPIO_PINCFG63_FNCSEL63_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
57254   GPIO_PINCFG63_FNCSEL63_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
57255   GPIO_PINCFG63_FNCSEL63_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57256   GPIO_PINCFG63_FNCSEL63_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57257   GPIO_PINCFG63_FNCSEL63_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57258   GPIO_PINCFG63_FNCSEL63_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57259   GPIO_PINCFG63_FNCSEL63_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57260   GPIO_PINCFG63_FNCSEL63_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57261 } GPIO_PINCFG63_FNCSEL63_Enum;
57262 
57263 /* =======================================================  PINCFG64  ======================================================== */
57264 /* ============================================  GPIO PINCFG64 NCEPOL64 [22..22]  ============================================ */
57265 typedef enum {                                  /*!< GPIO_PINCFG64_NCEPOL64                                                    */
57266   GPIO_PINCFG64_NCEPOL64_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57267   GPIO_PINCFG64_NCEPOL64_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57268 } GPIO_PINCFG64_NCEPOL64_Enum;
57269 
57270 /* ============================================  GPIO PINCFG64 NCESRC64 [16..21]  ============================================ */
57271 typedef enum {                                  /*!< GPIO_PINCFG64_NCESRC64                                                    */
57272   GPIO_PINCFG64_NCESRC64_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57273   GPIO_PINCFG64_NCESRC64_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57274   GPIO_PINCFG64_NCESRC64_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57275   GPIO_PINCFG64_NCESRC64_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57276   GPIO_PINCFG64_NCESRC64_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57277   GPIO_PINCFG64_NCESRC64_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57278   GPIO_PINCFG64_NCESRC64_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57279   GPIO_PINCFG64_NCESRC64_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57280   GPIO_PINCFG64_NCESRC64_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57281   GPIO_PINCFG64_NCESRC64_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57282   GPIO_PINCFG64_NCESRC64_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57283   GPIO_PINCFG64_NCESRC64_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57284   GPIO_PINCFG64_NCESRC64_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57285   GPIO_PINCFG64_NCESRC64_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57286   GPIO_PINCFG64_NCESRC64_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57287   GPIO_PINCFG64_NCESRC64_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57288   GPIO_PINCFG64_NCESRC64_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57289   GPIO_PINCFG64_NCESRC64_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57290   GPIO_PINCFG64_NCESRC64_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57291   GPIO_PINCFG64_NCESRC64_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57292   GPIO_PINCFG64_NCESRC64_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57293   GPIO_PINCFG64_NCESRC64_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57294   GPIO_PINCFG64_NCESRC64_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57295   GPIO_PINCFG64_NCESRC64_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57296   GPIO_PINCFG64_NCESRC64_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57297   GPIO_PINCFG64_NCESRC64_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57298   GPIO_PINCFG64_NCESRC64_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57299   GPIO_PINCFG64_NCESRC64_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57300   GPIO_PINCFG64_NCESRC64_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57301   GPIO_PINCFG64_NCESRC64_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57302   GPIO_PINCFG64_NCESRC64_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57303   GPIO_PINCFG64_NCESRC64_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57304   GPIO_PINCFG64_NCESRC64_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57305   GPIO_PINCFG64_NCESRC64_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57306   GPIO_PINCFG64_NCESRC64_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57307   GPIO_PINCFG64_NCESRC64_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57308   GPIO_PINCFG64_NCESRC64_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57309   GPIO_PINCFG64_NCESRC64_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57310   GPIO_PINCFG64_NCESRC64_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57311   GPIO_PINCFG64_NCESRC64_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57312   GPIO_PINCFG64_NCESRC64_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57313   GPIO_PINCFG64_NCESRC64_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57314   GPIO_PINCFG64_NCESRC64_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57315 } GPIO_PINCFG64_NCESRC64_Enum;
57316 
57317 /* ===========================================  GPIO PINCFG64 PULLCFG64 [13..15]  ============================================ */
57318 typedef enum {                                  /*!< GPIO_PINCFG64_PULLCFG64                                                   */
57319   GPIO_PINCFG64_PULLCFG64_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57320   GPIO_PINCFG64_PULLCFG64_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57321   GPIO_PINCFG64_PULLCFG64_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57322   GPIO_PINCFG64_PULLCFG64_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57323   GPIO_PINCFG64_PULLCFG64_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57324   GPIO_PINCFG64_PULLCFG64_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57325   GPIO_PINCFG64_PULLCFG64_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57326   GPIO_PINCFG64_PULLCFG64_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57327 } GPIO_PINCFG64_PULLCFG64_Enum;
57328 
57329 /* ==============================================  GPIO PINCFG64 DS64 [10..11]  ============================================== */
57330 typedef enum {                                  /*!< GPIO_PINCFG64_DS64                                                        */
57331   GPIO_PINCFG64_DS64_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57332   GPIO_PINCFG64_DS64_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57333   GPIO_PINCFG64_DS64_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57334   GPIO_PINCFG64_DS64_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57335 } GPIO_PINCFG64_DS64_Enum;
57336 
57337 /* =============================================  GPIO PINCFG64 OUTCFG64 [8..9]  ============================================= */
57338 typedef enum {                                  /*!< GPIO_PINCFG64_OUTCFG64                                                    */
57339   GPIO_PINCFG64_OUTCFG64_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57340   GPIO_PINCFG64_OUTCFG64_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57341                                                      and 1 values on pin.                                                      */
57342   GPIO_PINCFG64_OUTCFG64_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57343                                                      low, tristate otherwise.                                                  */
57344   GPIO_PINCFG64_OUTCFG64_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57345                                                      drive 0, 1 of HiZ on pin.                                                 */
57346 } GPIO_PINCFG64_OUTCFG64_Enum;
57347 
57348 /* =============================================  GPIO PINCFG64 IRPTEN64 [6..7]  ============================================= */
57349 typedef enum {                                  /*!< GPIO_PINCFG64_IRPTEN64                                                    */
57350   GPIO_PINCFG64_IRPTEN64_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57351   GPIO_PINCFG64_IRPTEN64_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57352                                                      on this GPIO                                                              */
57353   GPIO_PINCFG64_IRPTEN64_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57354                                                      on this GPIO                                                              */
57355   GPIO_PINCFG64_IRPTEN64_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57356                                                      GPIO                                                                      */
57357 } GPIO_PINCFG64_IRPTEN64_Enum;
57358 
57359 /* =============================================  GPIO PINCFG64 FNCSEL64 [0..3]  ============================================= */
57360 typedef enum {                                  /*!< GPIO_PINCFG64_FNCSEL64                                                    */
57361   GPIO_PINCFG64_FNCSEL64_MSPI0_0       = 0,     /*!< MSPI0_0 : MSPI Master 0 Interface Signal                                  */
57362   GPIO_PINCFG64_FNCSEL64_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
57363   GPIO_PINCFG64_FNCSEL64_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
57364   GPIO_PINCFG64_FNCSEL64_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57365   GPIO_PINCFG64_FNCSEL64_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
57366   GPIO_PINCFG64_FNCSEL64_DISP_D0       = 5,     /*!< DISP_D0 : Display Data 0                                                  */
57367   GPIO_PINCFG64_FNCSEL64_CT64          = 6,     /*!< CT64 : Timer/Counter input or output; Selection of direction
57368                                                      is done via CTIMER register settings.                                     */
57369   GPIO_PINCFG64_FNCSEL64_NCE64         = 7,     /*!< NCE64 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57370                                                      CE_POLARITY field                                                         */
57371   GPIO_PINCFG64_FNCSEL64_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
57372   GPIO_PINCFG64_FNCSEL64_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
57373   GPIO_PINCFG64_FNCSEL64_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57374   GPIO_PINCFG64_FNCSEL64_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57375   GPIO_PINCFG64_FNCSEL64_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57376   GPIO_PINCFG64_FNCSEL64_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57377   GPIO_PINCFG64_FNCSEL64_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57378   GPIO_PINCFG64_FNCSEL64_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57379 } GPIO_PINCFG64_FNCSEL64_Enum;
57380 
57381 /* =======================================================  PINCFG65  ======================================================== */
57382 /* ============================================  GPIO PINCFG65 NCEPOL65 [22..22]  ============================================ */
57383 typedef enum {                                  /*!< GPIO_PINCFG65_NCEPOL65                                                    */
57384   GPIO_PINCFG65_NCEPOL65_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57385   GPIO_PINCFG65_NCEPOL65_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57386 } GPIO_PINCFG65_NCEPOL65_Enum;
57387 
57388 /* ============================================  GPIO PINCFG65 NCESRC65 [16..21]  ============================================ */
57389 typedef enum {                                  /*!< GPIO_PINCFG65_NCESRC65                                                    */
57390   GPIO_PINCFG65_NCESRC65_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57391   GPIO_PINCFG65_NCESRC65_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57392   GPIO_PINCFG65_NCESRC65_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57393   GPIO_PINCFG65_NCESRC65_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57394   GPIO_PINCFG65_NCESRC65_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57395   GPIO_PINCFG65_NCESRC65_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57396   GPIO_PINCFG65_NCESRC65_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57397   GPIO_PINCFG65_NCESRC65_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57398   GPIO_PINCFG65_NCESRC65_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57399   GPIO_PINCFG65_NCESRC65_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57400   GPIO_PINCFG65_NCESRC65_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57401   GPIO_PINCFG65_NCESRC65_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57402   GPIO_PINCFG65_NCESRC65_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57403   GPIO_PINCFG65_NCESRC65_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57404   GPIO_PINCFG65_NCESRC65_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57405   GPIO_PINCFG65_NCESRC65_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57406   GPIO_PINCFG65_NCESRC65_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57407   GPIO_PINCFG65_NCESRC65_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57408   GPIO_PINCFG65_NCESRC65_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57409   GPIO_PINCFG65_NCESRC65_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57410   GPIO_PINCFG65_NCESRC65_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57411   GPIO_PINCFG65_NCESRC65_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57412   GPIO_PINCFG65_NCESRC65_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57413   GPIO_PINCFG65_NCESRC65_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57414   GPIO_PINCFG65_NCESRC65_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57415   GPIO_PINCFG65_NCESRC65_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57416   GPIO_PINCFG65_NCESRC65_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57417   GPIO_PINCFG65_NCESRC65_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57418   GPIO_PINCFG65_NCESRC65_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57419   GPIO_PINCFG65_NCESRC65_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57420   GPIO_PINCFG65_NCESRC65_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57421   GPIO_PINCFG65_NCESRC65_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57422   GPIO_PINCFG65_NCESRC65_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57423   GPIO_PINCFG65_NCESRC65_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57424   GPIO_PINCFG65_NCESRC65_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57425   GPIO_PINCFG65_NCESRC65_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57426   GPIO_PINCFG65_NCESRC65_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57427   GPIO_PINCFG65_NCESRC65_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57428   GPIO_PINCFG65_NCESRC65_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57429   GPIO_PINCFG65_NCESRC65_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57430   GPIO_PINCFG65_NCESRC65_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57431   GPIO_PINCFG65_NCESRC65_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57432   GPIO_PINCFG65_NCESRC65_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57433 } GPIO_PINCFG65_NCESRC65_Enum;
57434 
57435 /* ===========================================  GPIO PINCFG65 PULLCFG65 [13..15]  ============================================ */
57436 typedef enum {                                  /*!< GPIO_PINCFG65_PULLCFG65                                                   */
57437   GPIO_PINCFG65_PULLCFG65_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57438   GPIO_PINCFG65_PULLCFG65_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57439   GPIO_PINCFG65_PULLCFG65_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57440   GPIO_PINCFG65_PULLCFG65_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57441   GPIO_PINCFG65_PULLCFG65_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57442   GPIO_PINCFG65_PULLCFG65_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57443   GPIO_PINCFG65_PULLCFG65_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57444   GPIO_PINCFG65_PULLCFG65_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57445 } GPIO_PINCFG65_PULLCFG65_Enum;
57446 
57447 /* ==============================================  GPIO PINCFG65 DS65 [10..11]  ============================================== */
57448 typedef enum {                                  /*!< GPIO_PINCFG65_DS65                                                        */
57449   GPIO_PINCFG65_DS65_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57450   GPIO_PINCFG65_DS65_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57451   GPIO_PINCFG65_DS65_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57452   GPIO_PINCFG65_DS65_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57453 } GPIO_PINCFG65_DS65_Enum;
57454 
57455 /* =============================================  GPIO PINCFG65 OUTCFG65 [8..9]  ============================================= */
57456 typedef enum {                                  /*!< GPIO_PINCFG65_OUTCFG65                                                    */
57457   GPIO_PINCFG65_OUTCFG65_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57458   GPIO_PINCFG65_OUTCFG65_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57459                                                      and 1 values on pin.                                                      */
57460   GPIO_PINCFG65_OUTCFG65_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57461                                                      low, tristate otherwise.                                                  */
57462   GPIO_PINCFG65_OUTCFG65_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57463                                                      drive 0, 1 of HiZ on pin.                                                 */
57464 } GPIO_PINCFG65_OUTCFG65_Enum;
57465 
57466 /* =============================================  GPIO PINCFG65 IRPTEN65 [6..7]  ============================================= */
57467 typedef enum {                                  /*!< GPIO_PINCFG65_IRPTEN65                                                    */
57468   GPIO_PINCFG65_IRPTEN65_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57469   GPIO_PINCFG65_IRPTEN65_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57470                                                      on this GPIO                                                              */
57471   GPIO_PINCFG65_IRPTEN65_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57472                                                      on this GPIO                                                              */
57473   GPIO_PINCFG65_IRPTEN65_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57474                                                      GPIO                                                                      */
57475 } GPIO_PINCFG65_IRPTEN65_Enum;
57476 
57477 /* =============================================  GPIO PINCFG65 FNCSEL65 [0..3]  ============================================= */
57478 typedef enum {                                  /*!< GPIO_PINCFG65_FNCSEL65                                                    */
57479   GPIO_PINCFG65_FNCSEL65_MSPI0_1       = 0,     /*!< MSPI0_1 : MSPI Master 0 Interface Signal                                  */
57480   GPIO_PINCFG65_FNCSEL65_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
57481   GPIO_PINCFG65_FNCSEL65_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
57482   GPIO_PINCFG65_FNCSEL65_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57483   GPIO_PINCFG65_FNCSEL65_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
57484   GPIO_PINCFG65_FNCSEL65_DISP_D1       = 5,     /*!< DISP_D1 : Display Data 1                                                  */
57485   GPIO_PINCFG65_FNCSEL65_CT65          = 6,     /*!< CT65 : Timer/Counter input or output; Selection of direction
57486                                                      is done via CTIMER register settings.                                     */
57487   GPIO_PINCFG65_FNCSEL65_NCE65         = 7,     /*!< NCE65 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57488                                                      CE_POLARITY field                                                         */
57489   GPIO_PINCFG65_FNCSEL65_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
57490   GPIO_PINCFG65_FNCSEL65_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57491   GPIO_PINCFG65_FNCSEL65_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57492   GPIO_PINCFG65_FNCSEL65_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57493   GPIO_PINCFG65_FNCSEL65_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57494   GPIO_PINCFG65_FNCSEL65_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57495   GPIO_PINCFG65_FNCSEL65_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57496   GPIO_PINCFG65_FNCSEL65_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57497 } GPIO_PINCFG65_FNCSEL65_Enum;
57498 
57499 /* =======================================================  PINCFG66  ======================================================== */
57500 /* ============================================  GPIO PINCFG66 NCEPOL66 [22..22]  ============================================ */
57501 typedef enum {                                  /*!< GPIO_PINCFG66_NCEPOL66                                                    */
57502   GPIO_PINCFG66_NCEPOL66_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57503   GPIO_PINCFG66_NCEPOL66_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57504 } GPIO_PINCFG66_NCEPOL66_Enum;
57505 
57506 /* ============================================  GPIO PINCFG66 NCESRC66 [16..21]  ============================================ */
57507 typedef enum {                                  /*!< GPIO_PINCFG66_NCESRC66                                                    */
57508   GPIO_PINCFG66_NCESRC66_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57509   GPIO_PINCFG66_NCESRC66_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57510   GPIO_PINCFG66_NCESRC66_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57511   GPIO_PINCFG66_NCESRC66_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57512   GPIO_PINCFG66_NCESRC66_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57513   GPIO_PINCFG66_NCESRC66_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57514   GPIO_PINCFG66_NCESRC66_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57515   GPIO_PINCFG66_NCESRC66_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57516   GPIO_PINCFG66_NCESRC66_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57517   GPIO_PINCFG66_NCESRC66_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57518   GPIO_PINCFG66_NCESRC66_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57519   GPIO_PINCFG66_NCESRC66_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57520   GPIO_PINCFG66_NCESRC66_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57521   GPIO_PINCFG66_NCESRC66_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57522   GPIO_PINCFG66_NCESRC66_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57523   GPIO_PINCFG66_NCESRC66_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57524   GPIO_PINCFG66_NCESRC66_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57525   GPIO_PINCFG66_NCESRC66_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57526   GPIO_PINCFG66_NCESRC66_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57527   GPIO_PINCFG66_NCESRC66_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57528   GPIO_PINCFG66_NCESRC66_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57529   GPIO_PINCFG66_NCESRC66_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57530   GPIO_PINCFG66_NCESRC66_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57531   GPIO_PINCFG66_NCESRC66_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57532   GPIO_PINCFG66_NCESRC66_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57533   GPIO_PINCFG66_NCESRC66_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57534   GPIO_PINCFG66_NCESRC66_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57535   GPIO_PINCFG66_NCESRC66_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57536   GPIO_PINCFG66_NCESRC66_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57537   GPIO_PINCFG66_NCESRC66_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57538   GPIO_PINCFG66_NCESRC66_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57539   GPIO_PINCFG66_NCESRC66_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57540   GPIO_PINCFG66_NCESRC66_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57541   GPIO_PINCFG66_NCESRC66_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57542   GPIO_PINCFG66_NCESRC66_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57543   GPIO_PINCFG66_NCESRC66_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57544   GPIO_PINCFG66_NCESRC66_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57545   GPIO_PINCFG66_NCESRC66_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57546   GPIO_PINCFG66_NCESRC66_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57547   GPIO_PINCFG66_NCESRC66_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57548   GPIO_PINCFG66_NCESRC66_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57549   GPIO_PINCFG66_NCESRC66_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57550   GPIO_PINCFG66_NCESRC66_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57551 } GPIO_PINCFG66_NCESRC66_Enum;
57552 
57553 /* ===========================================  GPIO PINCFG66 PULLCFG66 [13..15]  ============================================ */
57554 typedef enum {                                  /*!< GPIO_PINCFG66_PULLCFG66                                                   */
57555   GPIO_PINCFG66_PULLCFG66_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57556   GPIO_PINCFG66_PULLCFG66_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57557   GPIO_PINCFG66_PULLCFG66_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57558   GPIO_PINCFG66_PULLCFG66_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57559   GPIO_PINCFG66_PULLCFG66_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57560   GPIO_PINCFG66_PULLCFG66_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57561   GPIO_PINCFG66_PULLCFG66_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57562   GPIO_PINCFG66_PULLCFG66_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57563 } GPIO_PINCFG66_PULLCFG66_Enum;
57564 
57565 /* ==============================================  GPIO PINCFG66 DS66 [10..11]  ============================================== */
57566 typedef enum {                                  /*!< GPIO_PINCFG66_DS66                                                        */
57567   GPIO_PINCFG66_DS66_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57568   GPIO_PINCFG66_DS66_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57569   GPIO_PINCFG66_DS66_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57570   GPIO_PINCFG66_DS66_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57571 } GPIO_PINCFG66_DS66_Enum;
57572 
57573 /* =============================================  GPIO PINCFG66 OUTCFG66 [8..9]  ============================================= */
57574 typedef enum {                                  /*!< GPIO_PINCFG66_OUTCFG66                                                    */
57575   GPIO_PINCFG66_OUTCFG66_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57576   GPIO_PINCFG66_OUTCFG66_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57577                                                      and 1 values on pin.                                                      */
57578   GPIO_PINCFG66_OUTCFG66_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57579                                                      low, tristate otherwise.                                                  */
57580   GPIO_PINCFG66_OUTCFG66_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57581                                                      drive 0, 1 of HiZ on pin.                                                 */
57582 } GPIO_PINCFG66_OUTCFG66_Enum;
57583 
57584 /* =============================================  GPIO PINCFG66 IRPTEN66 [6..7]  ============================================= */
57585 typedef enum {                                  /*!< GPIO_PINCFG66_IRPTEN66                                                    */
57586   GPIO_PINCFG66_IRPTEN66_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57587   GPIO_PINCFG66_IRPTEN66_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57588                                                      on this GPIO                                                              */
57589   GPIO_PINCFG66_IRPTEN66_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57590                                                      on this GPIO                                                              */
57591   GPIO_PINCFG66_IRPTEN66_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57592                                                      GPIO                                                                      */
57593 } GPIO_PINCFG66_IRPTEN66_Enum;
57594 
57595 /* =============================================  GPIO PINCFG66 FNCSEL66 [0..3]  ============================================= */
57596 typedef enum {                                  /*!< GPIO_PINCFG66_FNCSEL66                                                    */
57597   GPIO_PINCFG66_FNCSEL66_MSPI0_2       = 0,     /*!< MSPI0_2 : MSPI Master 0 Interface Signal                                  */
57598   GPIO_PINCFG66_FNCSEL66_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
57599   GPIO_PINCFG66_FNCSEL66_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
57600   GPIO_PINCFG66_FNCSEL66_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57601   GPIO_PINCFG66_FNCSEL66_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
57602   GPIO_PINCFG66_FNCSEL66_DISP_D2       = 5,     /*!< DISP_D2 : Display Data 2                                                  */
57603   GPIO_PINCFG66_FNCSEL66_CT66          = 6,     /*!< CT66 : Timer/Counter input or output; Selection of direction
57604                                                      is done via CTIMER register settings.                                     */
57605   GPIO_PINCFG66_FNCSEL66_NCE66         = 7,     /*!< NCE66 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57606                                                      CE_POLARITY field                                                         */
57607   GPIO_PINCFG66_FNCSEL66_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
57608   GPIO_PINCFG66_FNCSEL66_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57609   GPIO_PINCFG66_FNCSEL66_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57610   GPIO_PINCFG66_FNCSEL66_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57611   GPIO_PINCFG66_FNCSEL66_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57612   GPIO_PINCFG66_FNCSEL66_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57613   GPIO_PINCFG66_FNCSEL66_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57614   GPIO_PINCFG66_FNCSEL66_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57615 } GPIO_PINCFG66_FNCSEL66_Enum;
57616 
57617 /* =======================================================  PINCFG67  ======================================================== */
57618 /* ============================================  GPIO PINCFG67 NCEPOL67 [22..22]  ============================================ */
57619 typedef enum {                                  /*!< GPIO_PINCFG67_NCEPOL67                                                    */
57620   GPIO_PINCFG67_NCEPOL67_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57621   GPIO_PINCFG67_NCEPOL67_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57622 } GPIO_PINCFG67_NCEPOL67_Enum;
57623 
57624 /* ============================================  GPIO PINCFG67 NCESRC67 [16..21]  ============================================ */
57625 typedef enum {                                  /*!< GPIO_PINCFG67_NCESRC67                                                    */
57626   GPIO_PINCFG67_NCESRC67_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57627   GPIO_PINCFG67_NCESRC67_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57628   GPIO_PINCFG67_NCESRC67_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57629   GPIO_PINCFG67_NCESRC67_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57630   GPIO_PINCFG67_NCESRC67_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57631   GPIO_PINCFG67_NCESRC67_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57632   GPIO_PINCFG67_NCESRC67_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57633   GPIO_PINCFG67_NCESRC67_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57634   GPIO_PINCFG67_NCESRC67_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57635   GPIO_PINCFG67_NCESRC67_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57636   GPIO_PINCFG67_NCESRC67_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57637   GPIO_PINCFG67_NCESRC67_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57638   GPIO_PINCFG67_NCESRC67_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57639   GPIO_PINCFG67_NCESRC67_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57640   GPIO_PINCFG67_NCESRC67_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57641   GPIO_PINCFG67_NCESRC67_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57642   GPIO_PINCFG67_NCESRC67_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57643   GPIO_PINCFG67_NCESRC67_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57644   GPIO_PINCFG67_NCESRC67_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57645   GPIO_PINCFG67_NCESRC67_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57646   GPIO_PINCFG67_NCESRC67_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57647   GPIO_PINCFG67_NCESRC67_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57648   GPIO_PINCFG67_NCESRC67_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57649   GPIO_PINCFG67_NCESRC67_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57650   GPIO_PINCFG67_NCESRC67_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57651   GPIO_PINCFG67_NCESRC67_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57652   GPIO_PINCFG67_NCESRC67_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57653   GPIO_PINCFG67_NCESRC67_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57654   GPIO_PINCFG67_NCESRC67_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57655   GPIO_PINCFG67_NCESRC67_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57656   GPIO_PINCFG67_NCESRC67_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57657   GPIO_PINCFG67_NCESRC67_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57658   GPIO_PINCFG67_NCESRC67_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57659   GPIO_PINCFG67_NCESRC67_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57660   GPIO_PINCFG67_NCESRC67_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57661   GPIO_PINCFG67_NCESRC67_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57662   GPIO_PINCFG67_NCESRC67_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57663   GPIO_PINCFG67_NCESRC67_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57664   GPIO_PINCFG67_NCESRC67_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57665   GPIO_PINCFG67_NCESRC67_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57666   GPIO_PINCFG67_NCESRC67_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57667   GPIO_PINCFG67_NCESRC67_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57668   GPIO_PINCFG67_NCESRC67_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57669 } GPIO_PINCFG67_NCESRC67_Enum;
57670 
57671 /* ===========================================  GPIO PINCFG67 PULLCFG67 [13..15]  ============================================ */
57672 typedef enum {                                  /*!< GPIO_PINCFG67_PULLCFG67                                                   */
57673   GPIO_PINCFG67_PULLCFG67_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57674   GPIO_PINCFG67_PULLCFG67_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57675   GPIO_PINCFG67_PULLCFG67_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57676   GPIO_PINCFG67_PULLCFG67_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57677   GPIO_PINCFG67_PULLCFG67_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57678   GPIO_PINCFG67_PULLCFG67_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57679   GPIO_PINCFG67_PULLCFG67_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57680   GPIO_PINCFG67_PULLCFG67_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57681 } GPIO_PINCFG67_PULLCFG67_Enum;
57682 
57683 /* ==============================================  GPIO PINCFG67 DS67 [10..11]  ============================================== */
57684 typedef enum {                                  /*!< GPIO_PINCFG67_DS67                                                        */
57685   GPIO_PINCFG67_DS67_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57686   GPIO_PINCFG67_DS67_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57687   GPIO_PINCFG67_DS67_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57688   GPIO_PINCFG67_DS67_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57689 } GPIO_PINCFG67_DS67_Enum;
57690 
57691 /* =============================================  GPIO PINCFG67 OUTCFG67 [8..9]  ============================================= */
57692 typedef enum {                                  /*!< GPIO_PINCFG67_OUTCFG67                                                    */
57693   GPIO_PINCFG67_OUTCFG67_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57694   GPIO_PINCFG67_OUTCFG67_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57695                                                      and 1 values on pin.                                                      */
57696   GPIO_PINCFG67_OUTCFG67_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57697                                                      low, tristate otherwise.                                                  */
57698   GPIO_PINCFG67_OUTCFG67_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57699                                                      drive 0, 1 of HiZ on pin.                                                 */
57700 } GPIO_PINCFG67_OUTCFG67_Enum;
57701 
57702 /* =============================================  GPIO PINCFG67 IRPTEN67 [6..7]  ============================================= */
57703 typedef enum {                                  /*!< GPIO_PINCFG67_IRPTEN67                                                    */
57704   GPIO_PINCFG67_IRPTEN67_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57705   GPIO_PINCFG67_IRPTEN67_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57706                                                      on this GPIO                                                              */
57707   GPIO_PINCFG67_IRPTEN67_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57708                                                      on this GPIO                                                              */
57709   GPIO_PINCFG67_IRPTEN67_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57710                                                      GPIO                                                                      */
57711 } GPIO_PINCFG67_IRPTEN67_Enum;
57712 
57713 /* =============================================  GPIO PINCFG67 FNCSEL67 [0..3]  ============================================= */
57714 typedef enum {                                  /*!< GPIO_PINCFG67_FNCSEL67                                                    */
57715   GPIO_PINCFG67_FNCSEL67_MSPI0_3       = 0,     /*!< MSPI0_3 : MSPI Master 0 Interface Signal                                  */
57716   GPIO_PINCFG67_FNCSEL67_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
57717   GPIO_PINCFG67_FNCSEL67_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
57718   GPIO_PINCFG67_FNCSEL67_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57719   GPIO_PINCFG67_FNCSEL67_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
57720   GPIO_PINCFG67_FNCSEL67_DISP_D3       = 5,     /*!< DISP_D3 : Display Data 3                                                  */
57721   GPIO_PINCFG67_FNCSEL67_CT67          = 6,     /*!< CT67 : Timer/Counter input or output; Selection of direction
57722                                                      is done via CTIMER register settings.                                     */
57723   GPIO_PINCFG67_FNCSEL67_NCE67         = 7,     /*!< NCE67 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57724                                                      CE_POLARITY field                                                         */
57725   GPIO_PINCFG67_FNCSEL67_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
57726   GPIO_PINCFG67_FNCSEL67_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57727   GPIO_PINCFG67_FNCSEL67_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57728   GPIO_PINCFG67_FNCSEL67_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57729   GPIO_PINCFG67_FNCSEL67_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57730   GPIO_PINCFG67_FNCSEL67_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57731   GPIO_PINCFG67_FNCSEL67_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57732   GPIO_PINCFG67_FNCSEL67_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57733 } GPIO_PINCFG67_FNCSEL67_Enum;
57734 
57735 /* =======================================================  PINCFG68  ======================================================== */
57736 /* ============================================  GPIO PINCFG68 NCEPOL68 [22..22]  ============================================ */
57737 typedef enum {                                  /*!< GPIO_PINCFG68_NCEPOL68                                                    */
57738   GPIO_PINCFG68_NCEPOL68_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57739   GPIO_PINCFG68_NCEPOL68_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57740 } GPIO_PINCFG68_NCEPOL68_Enum;
57741 
57742 /* ============================================  GPIO PINCFG68 NCESRC68 [16..21]  ============================================ */
57743 typedef enum {                                  /*!< GPIO_PINCFG68_NCESRC68                                                    */
57744   GPIO_PINCFG68_NCESRC68_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57745   GPIO_PINCFG68_NCESRC68_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57746   GPIO_PINCFG68_NCESRC68_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57747   GPIO_PINCFG68_NCESRC68_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57748   GPIO_PINCFG68_NCESRC68_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57749   GPIO_PINCFG68_NCESRC68_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57750   GPIO_PINCFG68_NCESRC68_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57751   GPIO_PINCFG68_NCESRC68_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57752   GPIO_PINCFG68_NCESRC68_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57753   GPIO_PINCFG68_NCESRC68_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57754   GPIO_PINCFG68_NCESRC68_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57755   GPIO_PINCFG68_NCESRC68_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57756   GPIO_PINCFG68_NCESRC68_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57757   GPIO_PINCFG68_NCESRC68_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57758   GPIO_PINCFG68_NCESRC68_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57759   GPIO_PINCFG68_NCESRC68_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57760   GPIO_PINCFG68_NCESRC68_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57761   GPIO_PINCFG68_NCESRC68_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57762   GPIO_PINCFG68_NCESRC68_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57763   GPIO_PINCFG68_NCESRC68_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57764   GPIO_PINCFG68_NCESRC68_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57765   GPIO_PINCFG68_NCESRC68_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57766   GPIO_PINCFG68_NCESRC68_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57767   GPIO_PINCFG68_NCESRC68_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57768   GPIO_PINCFG68_NCESRC68_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57769   GPIO_PINCFG68_NCESRC68_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57770   GPIO_PINCFG68_NCESRC68_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57771   GPIO_PINCFG68_NCESRC68_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57772   GPIO_PINCFG68_NCESRC68_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57773   GPIO_PINCFG68_NCESRC68_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57774   GPIO_PINCFG68_NCESRC68_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57775   GPIO_PINCFG68_NCESRC68_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57776   GPIO_PINCFG68_NCESRC68_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57777   GPIO_PINCFG68_NCESRC68_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57778   GPIO_PINCFG68_NCESRC68_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57779   GPIO_PINCFG68_NCESRC68_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57780   GPIO_PINCFG68_NCESRC68_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57781   GPIO_PINCFG68_NCESRC68_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57782   GPIO_PINCFG68_NCESRC68_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57783   GPIO_PINCFG68_NCESRC68_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57784   GPIO_PINCFG68_NCESRC68_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57785   GPIO_PINCFG68_NCESRC68_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57786   GPIO_PINCFG68_NCESRC68_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57787 } GPIO_PINCFG68_NCESRC68_Enum;
57788 
57789 /* ===========================================  GPIO PINCFG68 PULLCFG68 [13..15]  ============================================ */
57790 typedef enum {                                  /*!< GPIO_PINCFG68_PULLCFG68                                                   */
57791   GPIO_PINCFG68_PULLCFG68_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57792   GPIO_PINCFG68_PULLCFG68_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57793   GPIO_PINCFG68_PULLCFG68_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57794   GPIO_PINCFG68_PULLCFG68_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57795   GPIO_PINCFG68_PULLCFG68_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57796   GPIO_PINCFG68_PULLCFG68_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57797   GPIO_PINCFG68_PULLCFG68_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57798   GPIO_PINCFG68_PULLCFG68_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57799 } GPIO_PINCFG68_PULLCFG68_Enum;
57800 
57801 /* ==============================================  GPIO PINCFG68 DS68 [10..11]  ============================================== */
57802 typedef enum {                                  /*!< GPIO_PINCFG68_DS68                                                        */
57803   GPIO_PINCFG68_DS68_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57804   GPIO_PINCFG68_DS68_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57805   GPIO_PINCFG68_DS68_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57806   GPIO_PINCFG68_DS68_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57807 } GPIO_PINCFG68_DS68_Enum;
57808 
57809 /* =============================================  GPIO PINCFG68 OUTCFG68 [8..9]  ============================================= */
57810 typedef enum {                                  /*!< GPIO_PINCFG68_OUTCFG68                                                    */
57811   GPIO_PINCFG68_OUTCFG68_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57812   GPIO_PINCFG68_OUTCFG68_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57813                                                      and 1 values on pin.                                                      */
57814   GPIO_PINCFG68_OUTCFG68_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57815                                                      low, tristate otherwise.                                                  */
57816   GPIO_PINCFG68_OUTCFG68_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57817                                                      drive 0, 1 of HiZ on pin.                                                 */
57818 } GPIO_PINCFG68_OUTCFG68_Enum;
57819 
57820 /* =============================================  GPIO PINCFG68 IRPTEN68 [6..7]  ============================================= */
57821 typedef enum {                                  /*!< GPIO_PINCFG68_IRPTEN68                                                    */
57822   GPIO_PINCFG68_IRPTEN68_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57823   GPIO_PINCFG68_IRPTEN68_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57824                                                      on this GPIO                                                              */
57825   GPIO_PINCFG68_IRPTEN68_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57826                                                      on this GPIO                                                              */
57827   GPIO_PINCFG68_IRPTEN68_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57828                                                      GPIO                                                                      */
57829 } GPIO_PINCFG68_IRPTEN68_Enum;
57830 
57831 /* =============================================  GPIO PINCFG68 FNCSEL68 [0..3]  ============================================= */
57832 typedef enum {                                  /*!< GPIO_PINCFG68_FNCSEL68                                                    */
57833   GPIO_PINCFG68_FNCSEL68_MSPI0_4       = 0,     /*!< MSPI0_4 : MSPI Master 0 Interface Signal                                  */
57834   GPIO_PINCFG68_FNCSEL68_SWO           = 1,     /*!< SWO : Serial Wire Output                                                  */
57835   GPIO_PINCFG68_FNCSEL68_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
57836   GPIO_PINCFG68_FNCSEL68_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57837   GPIO_PINCFG68_FNCSEL68_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
57838   GPIO_PINCFG68_FNCSEL68_DISP_D4       = 5,     /*!< DISP_D4 : Display Data 4                                                  */
57839   GPIO_PINCFG68_FNCSEL68_CT68          = 6,     /*!< CT68 : Timer/Counter input or output; Selection of direction
57840                                                      is done via CTIMER register settings.                                     */
57841   GPIO_PINCFG68_FNCSEL68_NCE68         = 7,     /*!< NCE68 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57842                                                      CE_POLARITY field                                                         */
57843   GPIO_PINCFG68_FNCSEL68_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
57844   GPIO_PINCFG68_FNCSEL68_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57845   GPIO_PINCFG68_FNCSEL68_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57846   GPIO_PINCFG68_FNCSEL68_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57847   GPIO_PINCFG68_FNCSEL68_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57848   GPIO_PINCFG68_FNCSEL68_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57849   GPIO_PINCFG68_FNCSEL68_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57850   GPIO_PINCFG68_FNCSEL68_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57851 } GPIO_PINCFG68_FNCSEL68_Enum;
57852 
57853 /* =======================================================  PINCFG69  ======================================================== */
57854 /* ============================================  GPIO PINCFG69 NCEPOL69 [22..22]  ============================================ */
57855 typedef enum {                                  /*!< GPIO_PINCFG69_NCEPOL69                                                    */
57856   GPIO_PINCFG69_NCEPOL69_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57857   GPIO_PINCFG69_NCEPOL69_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57858 } GPIO_PINCFG69_NCEPOL69_Enum;
57859 
57860 /* ============================================  GPIO PINCFG69 NCESRC69 [16..21]  ============================================ */
57861 typedef enum {                                  /*!< GPIO_PINCFG69_NCESRC69                                                    */
57862   GPIO_PINCFG69_NCESRC69_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57863   GPIO_PINCFG69_NCESRC69_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57864   GPIO_PINCFG69_NCESRC69_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57865   GPIO_PINCFG69_NCESRC69_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57866   GPIO_PINCFG69_NCESRC69_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57867   GPIO_PINCFG69_NCESRC69_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57868   GPIO_PINCFG69_NCESRC69_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57869   GPIO_PINCFG69_NCESRC69_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57870   GPIO_PINCFG69_NCESRC69_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57871   GPIO_PINCFG69_NCESRC69_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57872   GPIO_PINCFG69_NCESRC69_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57873   GPIO_PINCFG69_NCESRC69_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57874   GPIO_PINCFG69_NCESRC69_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57875   GPIO_PINCFG69_NCESRC69_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57876   GPIO_PINCFG69_NCESRC69_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57877   GPIO_PINCFG69_NCESRC69_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57878   GPIO_PINCFG69_NCESRC69_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57879   GPIO_PINCFG69_NCESRC69_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57880   GPIO_PINCFG69_NCESRC69_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57881   GPIO_PINCFG69_NCESRC69_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57882   GPIO_PINCFG69_NCESRC69_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57883   GPIO_PINCFG69_NCESRC69_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57884   GPIO_PINCFG69_NCESRC69_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57885   GPIO_PINCFG69_NCESRC69_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57886   GPIO_PINCFG69_NCESRC69_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57887   GPIO_PINCFG69_NCESRC69_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57888   GPIO_PINCFG69_NCESRC69_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57889   GPIO_PINCFG69_NCESRC69_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57890   GPIO_PINCFG69_NCESRC69_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57891   GPIO_PINCFG69_NCESRC69_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57892   GPIO_PINCFG69_NCESRC69_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57893   GPIO_PINCFG69_NCESRC69_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57894   GPIO_PINCFG69_NCESRC69_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57895   GPIO_PINCFG69_NCESRC69_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57896   GPIO_PINCFG69_NCESRC69_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57897   GPIO_PINCFG69_NCESRC69_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57898   GPIO_PINCFG69_NCESRC69_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57899   GPIO_PINCFG69_NCESRC69_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57900   GPIO_PINCFG69_NCESRC69_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57901   GPIO_PINCFG69_NCESRC69_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57902   GPIO_PINCFG69_NCESRC69_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57903   GPIO_PINCFG69_NCESRC69_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57904   GPIO_PINCFG69_NCESRC69_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57905 } GPIO_PINCFG69_NCESRC69_Enum;
57906 
57907 /* ===========================================  GPIO PINCFG69 PULLCFG69 [13..15]  ============================================ */
57908 typedef enum {                                  /*!< GPIO_PINCFG69_PULLCFG69                                                   */
57909   GPIO_PINCFG69_PULLCFG69_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57910   GPIO_PINCFG69_PULLCFG69_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57911   GPIO_PINCFG69_PULLCFG69_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57912   GPIO_PINCFG69_PULLCFG69_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57913   GPIO_PINCFG69_PULLCFG69_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57914   GPIO_PINCFG69_PULLCFG69_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57915   GPIO_PINCFG69_PULLCFG69_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57916   GPIO_PINCFG69_PULLCFG69_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57917 } GPIO_PINCFG69_PULLCFG69_Enum;
57918 
57919 /* ==============================================  GPIO PINCFG69 DS69 [10..11]  ============================================== */
57920 typedef enum {                                  /*!< GPIO_PINCFG69_DS69                                                        */
57921   GPIO_PINCFG69_DS69_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57922   GPIO_PINCFG69_DS69_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57923   GPIO_PINCFG69_DS69_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57924   GPIO_PINCFG69_DS69_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57925 } GPIO_PINCFG69_DS69_Enum;
57926 
57927 /* =============================================  GPIO PINCFG69 OUTCFG69 [8..9]  ============================================= */
57928 typedef enum {                                  /*!< GPIO_PINCFG69_OUTCFG69                                                    */
57929   GPIO_PINCFG69_OUTCFG69_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57930   GPIO_PINCFG69_OUTCFG69_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57931                                                      and 1 values on pin.                                                      */
57932   GPIO_PINCFG69_OUTCFG69_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57933                                                      low, tristate otherwise.                                                  */
57934   GPIO_PINCFG69_OUTCFG69_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57935                                                      drive 0, 1 of HiZ on pin.                                                 */
57936 } GPIO_PINCFG69_OUTCFG69_Enum;
57937 
57938 /* =============================================  GPIO PINCFG69 IRPTEN69 [6..7]  ============================================= */
57939 typedef enum {                                  /*!< GPIO_PINCFG69_IRPTEN69                                                    */
57940   GPIO_PINCFG69_IRPTEN69_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57941   GPIO_PINCFG69_IRPTEN69_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57942                                                      on this GPIO                                                              */
57943   GPIO_PINCFG69_IRPTEN69_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57944                                                      on this GPIO                                                              */
57945   GPIO_PINCFG69_IRPTEN69_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57946                                                      GPIO                                                                      */
57947 } GPIO_PINCFG69_IRPTEN69_Enum;
57948 
57949 /* =============================================  GPIO PINCFG69 FNCSEL69 [0..3]  ============================================= */
57950 typedef enum {                                  /*!< GPIO_PINCFG69_FNCSEL69                                                    */
57951   GPIO_PINCFG69_FNCSEL69_MSPI0_5       = 0,     /*!< MSPI0_5 : MSPI Master 0 Interface Signal                                  */
57952   GPIO_PINCFG69_FNCSEL69_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
57953   GPIO_PINCFG69_FNCSEL69_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
57954   GPIO_PINCFG69_FNCSEL69_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57955   GPIO_PINCFG69_FNCSEL69_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
57956   GPIO_PINCFG69_FNCSEL69_DISP_D5       = 5,     /*!< DISP_D5 : Display Data 5                                                  */
57957   GPIO_PINCFG69_FNCSEL69_CT69          = 6,     /*!< CT69 : Timer/Counter input or output; Selection of direction
57958                                                      is done via CTIMER register settings.                                     */
57959   GPIO_PINCFG69_FNCSEL69_NCE69         = 7,     /*!< NCE69 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57960                                                      CE_POLARITY field                                                         */
57961   GPIO_PINCFG69_FNCSEL69_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
57962   GPIO_PINCFG69_FNCSEL69_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57963   GPIO_PINCFG69_FNCSEL69_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57964   GPIO_PINCFG69_FNCSEL69_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57965   GPIO_PINCFG69_FNCSEL69_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57966   GPIO_PINCFG69_FNCSEL69_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57967   GPIO_PINCFG69_FNCSEL69_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57968   GPIO_PINCFG69_FNCSEL69_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57969 } GPIO_PINCFG69_FNCSEL69_Enum;
57970 
57971 /* =======================================================  PINCFG70  ======================================================== */
57972 /* ============================================  GPIO PINCFG70 NCEPOL70 [22..22]  ============================================ */
57973 typedef enum {                                  /*!< GPIO_PINCFG70_NCEPOL70                                                    */
57974   GPIO_PINCFG70_NCEPOL70_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57975   GPIO_PINCFG70_NCEPOL70_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57976 } GPIO_PINCFG70_NCEPOL70_Enum;
57977 
57978 /* ============================================  GPIO PINCFG70 NCESRC70 [16..21]  ============================================ */
57979 typedef enum {                                  /*!< GPIO_PINCFG70_NCESRC70                                                    */
57980   GPIO_PINCFG70_NCESRC70_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57981   GPIO_PINCFG70_NCESRC70_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57982   GPIO_PINCFG70_NCESRC70_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57983   GPIO_PINCFG70_NCESRC70_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57984   GPIO_PINCFG70_NCESRC70_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57985   GPIO_PINCFG70_NCESRC70_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57986   GPIO_PINCFG70_NCESRC70_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57987   GPIO_PINCFG70_NCESRC70_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57988   GPIO_PINCFG70_NCESRC70_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57989   GPIO_PINCFG70_NCESRC70_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57990   GPIO_PINCFG70_NCESRC70_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57991   GPIO_PINCFG70_NCESRC70_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57992   GPIO_PINCFG70_NCESRC70_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57993   GPIO_PINCFG70_NCESRC70_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57994   GPIO_PINCFG70_NCESRC70_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57995   GPIO_PINCFG70_NCESRC70_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57996   GPIO_PINCFG70_NCESRC70_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57997   GPIO_PINCFG70_NCESRC70_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57998   GPIO_PINCFG70_NCESRC70_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57999   GPIO_PINCFG70_NCESRC70_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58000   GPIO_PINCFG70_NCESRC70_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58001   GPIO_PINCFG70_NCESRC70_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58002   GPIO_PINCFG70_NCESRC70_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58003   GPIO_PINCFG70_NCESRC70_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58004   GPIO_PINCFG70_NCESRC70_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58005   GPIO_PINCFG70_NCESRC70_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58006   GPIO_PINCFG70_NCESRC70_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58007   GPIO_PINCFG70_NCESRC70_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58008   GPIO_PINCFG70_NCESRC70_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58009   GPIO_PINCFG70_NCESRC70_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58010   GPIO_PINCFG70_NCESRC70_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58011   GPIO_PINCFG70_NCESRC70_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58012   GPIO_PINCFG70_NCESRC70_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58013   GPIO_PINCFG70_NCESRC70_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58014   GPIO_PINCFG70_NCESRC70_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58015   GPIO_PINCFG70_NCESRC70_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58016   GPIO_PINCFG70_NCESRC70_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58017   GPIO_PINCFG70_NCESRC70_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58018   GPIO_PINCFG70_NCESRC70_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58019   GPIO_PINCFG70_NCESRC70_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58020   GPIO_PINCFG70_NCESRC70_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58021   GPIO_PINCFG70_NCESRC70_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58022   GPIO_PINCFG70_NCESRC70_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58023 } GPIO_PINCFG70_NCESRC70_Enum;
58024 
58025 /* ===========================================  GPIO PINCFG70 PULLCFG70 [13..15]  ============================================ */
58026 typedef enum {                                  /*!< GPIO_PINCFG70_PULLCFG70                                                   */
58027   GPIO_PINCFG70_PULLCFG70_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58028   GPIO_PINCFG70_PULLCFG70_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58029   GPIO_PINCFG70_PULLCFG70_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58030   GPIO_PINCFG70_PULLCFG70_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58031   GPIO_PINCFG70_PULLCFG70_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58032   GPIO_PINCFG70_PULLCFG70_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58033   GPIO_PINCFG70_PULLCFG70_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58034   GPIO_PINCFG70_PULLCFG70_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58035 } GPIO_PINCFG70_PULLCFG70_Enum;
58036 
58037 /* ==============================================  GPIO PINCFG70 DS70 [10..11]  ============================================== */
58038 typedef enum {                                  /*!< GPIO_PINCFG70_DS70                                                        */
58039   GPIO_PINCFG70_DS70_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58040   GPIO_PINCFG70_DS70_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58041   GPIO_PINCFG70_DS70_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58042   GPIO_PINCFG70_DS70_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58043 } GPIO_PINCFG70_DS70_Enum;
58044 
58045 /* =============================================  GPIO PINCFG70 OUTCFG70 [8..9]  ============================================= */
58046 typedef enum {                                  /*!< GPIO_PINCFG70_OUTCFG70                                                    */
58047   GPIO_PINCFG70_OUTCFG70_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58048   GPIO_PINCFG70_OUTCFG70_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58049                                                      and 1 values on pin.                                                      */
58050   GPIO_PINCFG70_OUTCFG70_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58051                                                      low, tristate otherwise.                                                  */
58052   GPIO_PINCFG70_OUTCFG70_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58053                                                      drive 0, 1 of HiZ on pin.                                                 */
58054 } GPIO_PINCFG70_OUTCFG70_Enum;
58055 
58056 /* =============================================  GPIO PINCFG70 IRPTEN70 [6..7]  ============================================= */
58057 typedef enum {                                  /*!< GPIO_PINCFG70_IRPTEN70                                                    */
58058   GPIO_PINCFG70_IRPTEN70_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58059   GPIO_PINCFG70_IRPTEN70_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58060                                                      on this GPIO                                                              */
58061   GPIO_PINCFG70_IRPTEN70_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58062                                                      on this GPIO                                                              */
58063   GPIO_PINCFG70_IRPTEN70_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58064                                                      GPIO                                                                      */
58065 } GPIO_PINCFG70_IRPTEN70_Enum;
58066 
58067 /* =============================================  GPIO PINCFG70 FNCSEL70 [0..3]  ============================================= */
58068 typedef enum {                                  /*!< GPIO_PINCFG70_FNCSEL70                                                    */
58069   GPIO_PINCFG70_FNCSEL70_MSPI0_6       = 0,     /*!< MSPI0_6 : MSPI Master 0 Interface Signal                                  */
58070   GPIO_PINCFG70_FNCSEL70_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
58071   GPIO_PINCFG70_FNCSEL70_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
58072   GPIO_PINCFG70_FNCSEL70_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58073   GPIO_PINCFG70_FNCSEL70_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
58074   GPIO_PINCFG70_FNCSEL70_DISP_D6       = 5,     /*!< DISP_D6 : Display Data 6                                                  */
58075   GPIO_PINCFG70_FNCSEL70_CT70          = 6,     /*!< CT70 : Timer/Counter input or output; Selection of direction
58076                                                      is done via CTIMER register settings.                                     */
58077   GPIO_PINCFG70_FNCSEL70_NCE70         = 7,     /*!< NCE70 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58078                                                      CE_POLARITY field                                                         */
58079   GPIO_PINCFG70_FNCSEL70_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
58080   GPIO_PINCFG70_FNCSEL70_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58081   GPIO_PINCFG70_FNCSEL70_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58082   GPIO_PINCFG70_FNCSEL70_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58083   GPIO_PINCFG70_FNCSEL70_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58084   GPIO_PINCFG70_FNCSEL70_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58085   GPIO_PINCFG70_FNCSEL70_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58086   GPIO_PINCFG70_FNCSEL70_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58087 } GPIO_PINCFG70_FNCSEL70_Enum;
58088 
58089 /* =======================================================  PINCFG71  ======================================================== */
58090 /* ============================================  GPIO PINCFG71 NCEPOL71 [22..22]  ============================================ */
58091 typedef enum {                                  /*!< GPIO_PINCFG71_NCEPOL71                                                    */
58092   GPIO_PINCFG71_NCEPOL71_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58093   GPIO_PINCFG71_NCEPOL71_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58094 } GPIO_PINCFG71_NCEPOL71_Enum;
58095 
58096 /* ============================================  GPIO PINCFG71 NCESRC71 [16..21]  ============================================ */
58097 typedef enum {                                  /*!< GPIO_PINCFG71_NCESRC71                                                    */
58098   GPIO_PINCFG71_NCESRC71_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58099   GPIO_PINCFG71_NCESRC71_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58100   GPIO_PINCFG71_NCESRC71_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58101   GPIO_PINCFG71_NCESRC71_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58102   GPIO_PINCFG71_NCESRC71_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58103   GPIO_PINCFG71_NCESRC71_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58104   GPIO_PINCFG71_NCESRC71_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58105   GPIO_PINCFG71_NCESRC71_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58106   GPIO_PINCFG71_NCESRC71_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58107   GPIO_PINCFG71_NCESRC71_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58108   GPIO_PINCFG71_NCESRC71_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58109   GPIO_PINCFG71_NCESRC71_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58110   GPIO_PINCFG71_NCESRC71_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58111   GPIO_PINCFG71_NCESRC71_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58112   GPIO_PINCFG71_NCESRC71_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58113   GPIO_PINCFG71_NCESRC71_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58114   GPIO_PINCFG71_NCESRC71_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58115   GPIO_PINCFG71_NCESRC71_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58116   GPIO_PINCFG71_NCESRC71_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58117   GPIO_PINCFG71_NCESRC71_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58118   GPIO_PINCFG71_NCESRC71_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58119   GPIO_PINCFG71_NCESRC71_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58120   GPIO_PINCFG71_NCESRC71_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58121   GPIO_PINCFG71_NCESRC71_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58122   GPIO_PINCFG71_NCESRC71_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58123   GPIO_PINCFG71_NCESRC71_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58124   GPIO_PINCFG71_NCESRC71_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58125   GPIO_PINCFG71_NCESRC71_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58126   GPIO_PINCFG71_NCESRC71_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58127   GPIO_PINCFG71_NCESRC71_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58128   GPIO_PINCFG71_NCESRC71_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58129   GPIO_PINCFG71_NCESRC71_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58130   GPIO_PINCFG71_NCESRC71_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58131   GPIO_PINCFG71_NCESRC71_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58132   GPIO_PINCFG71_NCESRC71_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58133   GPIO_PINCFG71_NCESRC71_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58134   GPIO_PINCFG71_NCESRC71_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58135   GPIO_PINCFG71_NCESRC71_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58136   GPIO_PINCFG71_NCESRC71_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58137   GPIO_PINCFG71_NCESRC71_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58138   GPIO_PINCFG71_NCESRC71_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58139   GPIO_PINCFG71_NCESRC71_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58140   GPIO_PINCFG71_NCESRC71_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58141 } GPIO_PINCFG71_NCESRC71_Enum;
58142 
58143 /* ===========================================  GPIO PINCFG71 PULLCFG71 [13..15]  ============================================ */
58144 typedef enum {                                  /*!< GPIO_PINCFG71_PULLCFG71                                                   */
58145   GPIO_PINCFG71_PULLCFG71_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58146   GPIO_PINCFG71_PULLCFG71_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58147   GPIO_PINCFG71_PULLCFG71_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58148   GPIO_PINCFG71_PULLCFG71_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58149   GPIO_PINCFG71_PULLCFG71_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58150   GPIO_PINCFG71_PULLCFG71_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58151   GPIO_PINCFG71_PULLCFG71_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58152   GPIO_PINCFG71_PULLCFG71_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58153 } GPIO_PINCFG71_PULLCFG71_Enum;
58154 
58155 /* ==============================================  GPIO PINCFG71 DS71 [10..11]  ============================================== */
58156 typedef enum {                                  /*!< GPIO_PINCFG71_DS71                                                        */
58157   GPIO_PINCFG71_DS71_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58158   GPIO_PINCFG71_DS71_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58159   GPIO_PINCFG71_DS71_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58160   GPIO_PINCFG71_DS71_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58161 } GPIO_PINCFG71_DS71_Enum;
58162 
58163 /* =============================================  GPIO PINCFG71 OUTCFG71 [8..9]  ============================================= */
58164 typedef enum {                                  /*!< GPIO_PINCFG71_OUTCFG71                                                    */
58165   GPIO_PINCFG71_OUTCFG71_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58166   GPIO_PINCFG71_OUTCFG71_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58167                                                      and 1 values on pin.                                                      */
58168   GPIO_PINCFG71_OUTCFG71_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58169                                                      low, tristate otherwise.                                                  */
58170   GPIO_PINCFG71_OUTCFG71_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58171                                                      drive 0, 1 of HiZ on pin.                                                 */
58172 } GPIO_PINCFG71_OUTCFG71_Enum;
58173 
58174 /* =============================================  GPIO PINCFG71 IRPTEN71 [6..7]  ============================================= */
58175 typedef enum {                                  /*!< GPIO_PINCFG71_IRPTEN71                                                    */
58176   GPIO_PINCFG71_IRPTEN71_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58177   GPIO_PINCFG71_IRPTEN71_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58178                                                      on this GPIO                                                              */
58179   GPIO_PINCFG71_IRPTEN71_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58180                                                      on this GPIO                                                              */
58181   GPIO_PINCFG71_IRPTEN71_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58182                                                      GPIO                                                                      */
58183 } GPIO_PINCFG71_IRPTEN71_Enum;
58184 
58185 /* =============================================  GPIO PINCFG71 FNCSEL71 [0..3]  ============================================= */
58186 typedef enum {                                  /*!< GPIO_PINCFG71_FNCSEL71                                                    */
58187   GPIO_PINCFG71_FNCSEL71_MSPI0_7       = 0,     /*!< MSPI0_7 : MSPI Master 0 Interface Signal                                  */
58188   GPIO_PINCFG71_FNCSEL71_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
58189   GPIO_PINCFG71_FNCSEL71_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
58190   GPIO_PINCFG71_FNCSEL71_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58191   GPIO_PINCFG71_FNCSEL71_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
58192   GPIO_PINCFG71_FNCSEL71_DISP_D7       = 5,     /*!< DISP_D7 : Display Data 7                                                  */
58193   GPIO_PINCFG71_FNCSEL71_CT71          = 6,     /*!< CT71 : Timer/Counter input or output; Selection of direction
58194                                                      is done via CTIMER register settings.                                     */
58195   GPIO_PINCFG71_FNCSEL71_NCE71         = 7,     /*!< NCE71 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58196                                                      CE_POLARITY field                                                         */
58197   GPIO_PINCFG71_FNCSEL71_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
58198   GPIO_PINCFG71_FNCSEL71_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58199   GPIO_PINCFG71_FNCSEL71_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58200   GPIO_PINCFG71_FNCSEL71_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58201   GPIO_PINCFG71_FNCSEL71_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58202   GPIO_PINCFG71_FNCSEL71_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58203   GPIO_PINCFG71_FNCSEL71_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58204   GPIO_PINCFG71_FNCSEL71_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58205 } GPIO_PINCFG71_FNCSEL71_Enum;
58206 
58207 /* =======================================================  PINCFG72  ======================================================== */
58208 /* ============================================  GPIO PINCFG72 NCEPOL72 [22..22]  ============================================ */
58209 typedef enum {                                  /*!< GPIO_PINCFG72_NCEPOL72                                                    */
58210   GPIO_PINCFG72_NCEPOL72_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58211   GPIO_PINCFG72_NCEPOL72_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58212 } GPIO_PINCFG72_NCEPOL72_Enum;
58213 
58214 /* ============================================  GPIO PINCFG72 NCESRC72 [16..21]  ============================================ */
58215 typedef enum {                                  /*!< GPIO_PINCFG72_NCESRC72                                                    */
58216   GPIO_PINCFG72_NCESRC72_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58217   GPIO_PINCFG72_NCESRC72_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58218   GPIO_PINCFG72_NCESRC72_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58219   GPIO_PINCFG72_NCESRC72_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58220   GPIO_PINCFG72_NCESRC72_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58221   GPIO_PINCFG72_NCESRC72_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58222   GPIO_PINCFG72_NCESRC72_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58223   GPIO_PINCFG72_NCESRC72_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58224   GPIO_PINCFG72_NCESRC72_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58225   GPIO_PINCFG72_NCESRC72_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58226   GPIO_PINCFG72_NCESRC72_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58227   GPIO_PINCFG72_NCESRC72_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58228   GPIO_PINCFG72_NCESRC72_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58229   GPIO_PINCFG72_NCESRC72_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58230   GPIO_PINCFG72_NCESRC72_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58231   GPIO_PINCFG72_NCESRC72_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58232   GPIO_PINCFG72_NCESRC72_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58233   GPIO_PINCFG72_NCESRC72_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58234   GPIO_PINCFG72_NCESRC72_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58235   GPIO_PINCFG72_NCESRC72_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58236   GPIO_PINCFG72_NCESRC72_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58237   GPIO_PINCFG72_NCESRC72_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58238   GPIO_PINCFG72_NCESRC72_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58239   GPIO_PINCFG72_NCESRC72_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58240   GPIO_PINCFG72_NCESRC72_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58241   GPIO_PINCFG72_NCESRC72_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58242   GPIO_PINCFG72_NCESRC72_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58243   GPIO_PINCFG72_NCESRC72_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58244   GPIO_PINCFG72_NCESRC72_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58245   GPIO_PINCFG72_NCESRC72_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58246   GPIO_PINCFG72_NCESRC72_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58247   GPIO_PINCFG72_NCESRC72_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58248   GPIO_PINCFG72_NCESRC72_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58249   GPIO_PINCFG72_NCESRC72_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58250   GPIO_PINCFG72_NCESRC72_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58251   GPIO_PINCFG72_NCESRC72_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58252   GPIO_PINCFG72_NCESRC72_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58253   GPIO_PINCFG72_NCESRC72_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58254   GPIO_PINCFG72_NCESRC72_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58255   GPIO_PINCFG72_NCESRC72_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58256   GPIO_PINCFG72_NCESRC72_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58257   GPIO_PINCFG72_NCESRC72_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58258   GPIO_PINCFG72_NCESRC72_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58259 } GPIO_PINCFG72_NCESRC72_Enum;
58260 
58261 /* ===========================================  GPIO PINCFG72 PULLCFG72 [13..15]  ============================================ */
58262 typedef enum {                                  /*!< GPIO_PINCFG72_PULLCFG72                                                   */
58263   GPIO_PINCFG72_PULLCFG72_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58264   GPIO_PINCFG72_PULLCFG72_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58265   GPIO_PINCFG72_PULLCFG72_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58266   GPIO_PINCFG72_PULLCFG72_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58267   GPIO_PINCFG72_PULLCFG72_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58268   GPIO_PINCFG72_PULLCFG72_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58269   GPIO_PINCFG72_PULLCFG72_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58270   GPIO_PINCFG72_PULLCFG72_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58271 } GPIO_PINCFG72_PULLCFG72_Enum;
58272 
58273 /* ==============================================  GPIO PINCFG72 DS72 [10..11]  ============================================== */
58274 typedef enum {                                  /*!< GPIO_PINCFG72_DS72                                                        */
58275   GPIO_PINCFG72_DS72_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58276   GPIO_PINCFG72_DS72_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58277   GPIO_PINCFG72_DS72_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58278   GPIO_PINCFG72_DS72_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58279 } GPIO_PINCFG72_DS72_Enum;
58280 
58281 /* =============================================  GPIO PINCFG72 OUTCFG72 [8..9]  ============================================= */
58282 typedef enum {                                  /*!< GPIO_PINCFG72_OUTCFG72                                                    */
58283   GPIO_PINCFG72_OUTCFG72_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58284   GPIO_PINCFG72_OUTCFG72_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58285                                                      and 1 values on pin.                                                      */
58286   GPIO_PINCFG72_OUTCFG72_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58287                                                      low, tristate otherwise.                                                  */
58288   GPIO_PINCFG72_OUTCFG72_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58289                                                      drive 0, 1 of HiZ on pin.                                                 */
58290 } GPIO_PINCFG72_OUTCFG72_Enum;
58291 
58292 /* =============================================  GPIO PINCFG72 IRPTEN72 [6..7]  ============================================= */
58293 typedef enum {                                  /*!< GPIO_PINCFG72_IRPTEN72                                                    */
58294   GPIO_PINCFG72_IRPTEN72_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58295   GPIO_PINCFG72_IRPTEN72_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58296                                                      on this GPIO                                                              */
58297   GPIO_PINCFG72_IRPTEN72_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58298                                                      on this GPIO                                                              */
58299   GPIO_PINCFG72_IRPTEN72_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58300                                                      GPIO                                                                      */
58301 } GPIO_PINCFG72_IRPTEN72_Enum;
58302 
58303 /* =============================================  GPIO PINCFG72 FNCSEL72 [0..3]  ============================================= */
58304 typedef enum {                                  /*!< GPIO_PINCFG72_FNCSEL72                                                    */
58305   GPIO_PINCFG72_FNCSEL72_MSPI0_8       = 0,     /*!< MSPI0_8 : MSPI Master 0 Interface Signal                                  */
58306   GPIO_PINCFG72_FNCSEL72_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
58307   GPIO_PINCFG72_FNCSEL72_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
58308   GPIO_PINCFG72_FNCSEL72_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58309   GPIO_PINCFG72_FNCSEL72_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
58310   GPIO_PINCFG72_FNCSEL72_DISP_D8       = 5,     /*!< DISP_D8 : Display Data 8                                                  */
58311   GPIO_PINCFG72_FNCSEL72_CT72          = 6,     /*!< CT72 : Timer/Counter input or output; Selection of direction
58312                                                      is done via CTIMER register settings.                                     */
58313   GPIO_PINCFG72_FNCSEL72_NCE72         = 7,     /*!< NCE72 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58314                                                      CE_POLARITY field                                                         */
58315   GPIO_PINCFG72_FNCSEL72_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
58316   GPIO_PINCFG72_FNCSEL72_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
58317   GPIO_PINCFG72_FNCSEL72_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58318   GPIO_PINCFG72_FNCSEL72_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58319   GPIO_PINCFG72_FNCSEL72_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58320   GPIO_PINCFG72_FNCSEL72_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58321   GPIO_PINCFG72_FNCSEL72_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58322   GPIO_PINCFG72_FNCSEL72_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58323 } GPIO_PINCFG72_FNCSEL72_Enum;
58324 
58325 /* =======================================================  PINCFG73  ======================================================== */
58326 /* ============================================  GPIO PINCFG73 NCEPOL73 [22..22]  ============================================ */
58327 typedef enum {                                  /*!< GPIO_PINCFG73_NCEPOL73                                                    */
58328   GPIO_PINCFG73_NCEPOL73_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58329   GPIO_PINCFG73_NCEPOL73_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58330 } GPIO_PINCFG73_NCEPOL73_Enum;
58331 
58332 /* ============================================  GPIO PINCFG73 NCESRC73 [16..21]  ============================================ */
58333 typedef enum {                                  /*!< GPIO_PINCFG73_NCESRC73                                                    */
58334   GPIO_PINCFG73_NCESRC73_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58335   GPIO_PINCFG73_NCESRC73_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58336   GPIO_PINCFG73_NCESRC73_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58337   GPIO_PINCFG73_NCESRC73_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58338   GPIO_PINCFG73_NCESRC73_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58339   GPIO_PINCFG73_NCESRC73_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58340   GPIO_PINCFG73_NCESRC73_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58341   GPIO_PINCFG73_NCESRC73_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58342   GPIO_PINCFG73_NCESRC73_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58343   GPIO_PINCFG73_NCESRC73_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58344   GPIO_PINCFG73_NCESRC73_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58345   GPIO_PINCFG73_NCESRC73_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58346   GPIO_PINCFG73_NCESRC73_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58347   GPIO_PINCFG73_NCESRC73_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58348   GPIO_PINCFG73_NCESRC73_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58349   GPIO_PINCFG73_NCESRC73_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58350   GPIO_PINCFG73_NCESRC73_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58351   GPIO_PINCFG73_NCESRC73_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58352   GPIO_PINCFG73_NCESRC73_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58353   GPIO_PINCFG73_NCESRC73_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58354   GPIO_PINCFG73_NCESRC73_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58355   GPIO_PINCFG73_NCESRC73_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58356   GPIO_PINCFG73_NCESRC73_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58357   GPIO_PINCFG73_NCESRC73_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58358   GPIO_PINCFG73_NCESRC73_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58359   GPIO_PINCFG73_NCESRC73_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58360   GPIO_PINCFG73_NCESRC73_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58361   GPIO_PINCFG73_NCESRC73_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58362   GPIO_PINCFG73_NCESRC73_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58363   GPIO_PINCFG73_NCESRC73_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58364   GPIO_PINCFG73_NCESRC73_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58365   GPIO_PINCFG73_NCESRC73_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58366   GPIO_PINCFG73_NCESRC73_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58367   GPIO_PINCFG73_NCESRC73_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58368   GPIO_PINCFG73_NCESRC73_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58369   GPIO_PINCFG73_NCESRC73_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58370   GPIO_PINCFG73_NCESRC73_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58371   GPIO_PINCFG73_NCESRC73_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58372   GPIO_PINCFG73_NCESRC73_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58373   GPIO_PINCFG73_NCESRC73_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58374   GPIO_PINCFG73_NCESRC73_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58375   GPIO_PINCFG73_NCESRC73_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58376   GPIO_PINCFG73_NCESRC73_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58377 } GPIO_PINCFG73_NCESRC73_Enum;
58378 
58379 /* ===========================================  GPIO PINCFG73 PULLCFG73 [13..15]  ============================================ */
58380 typedef enum {                                  /*!< GPIO_PINCFG73_PULLCFG73                                                   */
58381   GPIO_PINCFG73_PULLCFG73_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58382   GPIO_PINCFG73_PULLCFG73_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58383   GPIO_PINCFG73_PULLCFG73_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58384   GPIO_PINCFG73_PULLCFG73_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58385   GPIO_PINCFG73_PULLCFG73_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58386   GPIO_PINCFG73_PULLCFG73_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58387   GPIO_PINCFG73_PULLCFG73_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58388   GPIO_PINCFG73_PULLCFG73_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58389 } GPIO_PINCFG73_PULLCFG73_Enum;
58390 
58391 /* ==============================================  GPIO PINCFG73 DS73 [10..11]  ============================================== */
58392 typedef enum {                                  /*!< GPIO_PINCFG73_DS73                                                        */
58393   GPIO_PINCFG73_DS73_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58394   GPIO_PINCFG73_DS73_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58395   GPIO_PINCFG73_DS73_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58396   GPIO_PINCFG73_DS73_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58397 } GPIO_PINCFG73_DS73_Enum;
58398 
58399 /* =============================================  GPIO PINCFG73 OUTCFG73 [8..9]  ============================================= */
58400 typedef enum {                                  /*!< GPIO_PINCFG73_OUTCFG73                                                    */
58401   GPIO_PINCFG73_OUTCFG73_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58402   GPIO_PINCFG73_OUTCFG73_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58403                                                      and 1 values on pin.                                                      */
58404   GPIO_PINCFG73_OUTCFG73_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58405                                                      low, tristate otherwise.                                                  */
58406   GPIO_PINCFG73_OUTCFG73_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58407                                                      drive 0, 1 of HiZ on pin.                                                 */
58408 } GPIO_PINCFG73_OUTCFG73_Enum;
58409 
58410 /* =============================================  GPIO PINCFG73 IRPTEN73 [6..7]  ============================================= */
58411 typedef enum {                                  /*!< GPIO_PINCFG73_IRPTEN73                                                    */
58412   GPIO_PINCFG73_IRPTEN73_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58413   GPIO_PINCFG73_IRPTEN73_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58414                                                      on this GPIO                                                              */
58415   GPIO_PINCFG73_IRPTEN73_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58416                                                      on this GPIO                                                              */
58417   GPIO_PINCFG73_IRPTEN73_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58418                                                      GPIO                                                                      */
58419 } GPIO_PINCFG73_IRPTEN73_Enum;
58420 
58421 /* =============================================  GPIO PINCFG73 FNCSEL73 [0..3]  ============================================= */
58422 typedef enum {                                  /*!< GPIO_PINCFG73_FNCSEL73                                                    */
58423   GPIO_PINCFG73_FNCSEL73_MSPI0_9       = 0,     /*!< MSPI0_9 : MSPI Master 0 Interface Signal                                  */
58424   GPIO_PINCFG73_FNCSEL73_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
58425   GPIO_PINCFG73_FNCSEL73_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
58426   GPIO_PINCFG73_FNCSEL73_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58427   GPIO_PINCFG73_FNCSEL73_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
58428   GPIO_PINCFG73_FNCSEL73_DISP_D9       = 5,     /*!< DISP_D9 : Display Data 9                                                  */
58429   GPIO_PINCFG73_FNCSEL73_CT73          = 6,     /*!< CT73 : Timer/Counter input or output; Selection of direction
58430                                                      is done via CTIMER register settings.                                     */
58431   GPIO_PINCFG73_FNCSEL73_NCE73         = 7,     /*!< NCE73 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58432                                                      CE_POLARITY field                                                         */
58433   GPIO_PINCFG73_FNCSEL73_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
58434   GPIO_PINCFG73_FNCSEL73_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58435   GPIO_PINCFG73_FNCSEL73_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58436   GPIO_PINCFG73_FNCSEL73_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58437   GPIO_PINCFG73_FNCSEL73_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58438   GPIO_PINCFG73_FNCSEL73_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58439   GPIO_PINCFG73_FNCSEL73_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58440   GPIO_PINCFG73_FNCSEL73_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58441 } GPIO_PINCFG73_FNCSEL73_Enum;
58442 
58443 /* =======================================================  PINCFG74  ======================================================== */
58444 /* ============================================  GPIO PINCFG74 NCEPOL74 [22..22]  ============================================ */
58445 typedef enum {                                  /*!< GPIO_PINCFG74_NCEPOL74                                                    */
58446   GPIO_PINCFG74_NCEPOL74_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58447   GPIO_PINCFG74_NCEPOL74_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58448 } GPIO_PINCFG74_NCEPOL74_Enum;
58449 
58450 /* ============================================  GPIO PINCFG74 NCESRC74 [16..21]  ============================================ */
58451 typedef enum {                                  /*!< GPIO_PINCFG74_NCESRC74                                                    */
58452   GPIO_PINCFG74_NCESRC74_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58453   GPIO_PINCFG74_NCESRC74_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58454   GPIO_PINCFG74_NCESRC74_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58455   GPIO_PINCFG74_NCESRC74_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58456   GPIO_PINCFG74_NCESRC74_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58457   GPIO_PINCFG74_NCESRC74_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58458   GPIO_PINCFG74_NCESRC74_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58459   GPIO_PINCFG74_NCESRC74_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58460   GPIO_PINCFG74_NCESRC74_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58461   GPIO_PINCFG74_NCESRC74_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58462   GPIO_PINCFG74_NCESRC74_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58463   GPIO_PINCFG74_NCESRC74_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58464   GPIO_PINCFG74_NCESRC74_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58465   GPIO_PINCFG74_NCESRC74_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58466   GPIO_PINCFG74_NCESRC74_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58467   GPIO_PINCFG74_NCESRC74_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58468   GPIO_PINCFG74_NCESRC74_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58469   GPIO_PINCFG74_NCESRC74_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58470   GPIO_PINCFG74_NCESRC74_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58471   GPIO_PINCFG74_NCESRC74_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58472   GPIO_PINCFG74_NCESRC74_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58473   GPIO_PINCFG74_NCESRC74_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58474   GPIO_PINCFG74_NCESRC74_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58475   GPIO_PINCFG74_NCESRC74_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58476   GPIO_PINCFG74_NCESRC74_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58477   GPIO_PINCFG74_NCESRC74_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58478   GPIO_PINCFG74_NCESRC74_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58479   GPIO_PINCFG74_NCESRC74_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58480   GPIO_PINCFG74_NCESRC74_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58481   GPIO_PINCFG74_NCESRC74_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58482   GPIO_PINCFG74_NCESRC74_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58483   GPIO_PINCFG74_NCESRC74_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58484   GPIO_PINCFG74_NCESRC74_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58485   GPIO_PINCFG74_NCESRC74_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58486   GPIO_PINCFG74_NCESRC74_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58487   GPIO_PINCFG74_NCESRC74_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58488   GPIO_PINCFG74_NCESRC74_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58489   GPIO_PINCFG74_NCESRC74_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58490   GPIO_PINCFG74_NCESRC74_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58491   GPIO_PINCFG74_NCESRC74_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58492   GPIO_PINCFG74_NCESRC74_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58493   GPIO_PINCFG74_NCESRC74_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58494   GPIO_PINCFG74_NCESRC74_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58495 } GPIO_PINCFG74_NCESRC74_Enum;
58496 
58497 /* ===========================================  GPIO PINCFG74 PULLCFG74 [13..15]  ============================================ */
58498 typedef enum {                                  /*!< GPIO_PINCFG74_PULLCFG74                                                   */
58499   GPIO_PINCFG74_PULLCFG74_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58500   GPIO_PINCFG74_PULLCFG74_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58501   GPIO_PINCFG74_PULLCFG74_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58502   GPIO_PINCFG74_PULLCFG74_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58503   GPIO_PINCFG74_PULLCFG74_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58504   GPIO_PINCFG74_PULLCFG74_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58505   GPIO_PINCFG74_PULLCFG74_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58506   GPIO_PINCFG74_PULLCFG74_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58507 } GPIO_PINCFG74_PULLCFG74_Enum;
58508 
58509 /* ==============================================  GPIO PINCFG74 DS74 [10..11]  ============================================== */
58510 typedef enum {                                  /*!< GPIO_PINCFG74_DS74                                                        */
58511   GPIO_PINCFG74_DS74_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58512   GPIO_PINCFG74_DS74_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58513   GPIO_PINCFG74_DS74_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58514   GPIO_PINCFG74_DS74_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58515 } GPIO_PINCFG74_DS74_Enum;
58516 
58517 /* =============================================  GPIO PINCFG74 OUTCFG74 [8..9]  ============================================= */
58518 typedef enum {                                  /*!< GPIO_PINCFG74_OUTCFG74                                                    */
58519   GPIO_PINCFG74_OUTCFG74_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58520   GPIO_PINCFG74_OUTCFG74_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58521                                                      and 1 values on pin.                                                      */
58522   GPIO_PINCFG74_OUTCFG74_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58523                                                      low, tristate otherwise.                                                  */
58524   GPIO_PINCFG74_OUTCFG74_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58525                                                      drive 0, 1 of HiZ on pin.                                                 */
58526 } GPIO_PINCFG74_OUTCFG74_Enum;
58527 
58528 /* =============================================  GPIO PINCFG74 IRPTEN74 [6..7]  ============================================= */
58529 typedef enum {                                  /*!< GPIO_PINCFG74_IRPTEN74                                                    */
58530   GPIO_PINCFG74_IRPTEN74_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58531   GPIO_PINCFG74_IRPTEN74_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58532                                                      on this GPIO                                                              */
58533   GPIO_PINCFG74_IRPTEN74_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58534                                                      on this GPIO                                                              */
58535   GPIO_PINCFG74_IRPTEN74_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58536                                                      GPIO                                                                      */
58537 } GPIO_PINCFG74_IRPTEN74_Enum;
58538 
58539 /* =============================================  GPIO PINCFG74 FNCSEL74 [0..3]  ============================================= */
58540 typedef enum {                                  /*!< GPIO_PINCFG74_FNCSEL74                                                    */
58541   GPIO_PINCFG74_FNCSEL74_MSPI2_0       = 0,     /*!< MSPI2_0 : MSPI Master 2 Interface Signal                                  */
58542   GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0_OUT = 1,  /*!< DISP_QSPI_D0_OUT : Display SPI Data0                                      */
58543   GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0  = 2,     /*!< DISP_QSPI_D0 : Display SPI Data0                                          */
58544   GPIO_PINCFG74_FNCSEL74_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58545   GPIO_PINCFG74_FNCSEL74_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
58546   GPIO_PINCFG74_FNCSEL74_DISP_D10      = 5,     /*!< DISP_D10 : Display Data 10                                                */
58547   GPIO_PINCFG74_FNCSEL74_CT74          = 6,     /*!< CT74 : Timer/Counter input or output; Selection of direction
58548                                                      is done via CTIMER register settings.                                     */
58549   GPIO_PINCFG74_FNCSEL74_NCE74         = 7,     /*!< NCE74 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58550                                                      CE_POLARITY field                                                         */
58551   GPIO_PINCFG74_FNCSEL74_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
58552   GPIO_PINCFG74_FNCSEL74_DISP_SPI_SD   = 9,     /*!< DISP_SPI_SD : Display SPI Data Out                                        */
58553   GPIO_PINCFG74_FNCSEL74_DISP_SPI_SDO  = 10,    /*!< DISP_SPI_SDO : Display SPI Data Out                                       */
58554   GPIO_PINCFG74_FNCSEL74_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58555   GPIO_PINCFG74_FNCSEL74_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58556   GPIO_PINCFG74_FNCSEL74_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58557   GPIO_PINCFG74_FNCSEL74_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58558   GPIO_PINCFG74_FNCSEL74_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58559 } GPIO_PINCFG74_FNCSEL74_Enum;
58560 
58561 /* =======================================================  PINCFG75  ======================================================== */
58562 /* ============================================  GPIO PINCFG75 NCEPOL75 [22..22]  ============================================ */
58563 typedef enum {                                  /*!< GPIO_PINCFG75_NCEPOL75                                                    */
58564   GPIO_PINCFG75_NCEPOL75_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58565   GPIO_PINCFG75_NCEPOL75_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58566 } GPIO_PINCFG75_NCEPOL75_Enum;
58567 
58568 /* ============================================  GPIO PINCFG75 NCESRC75 [16..21]  ============================================ */
58569 typedef enum {                                  /*!< GPIO_PINCFG75_NCESRC75                                                    */
58570   GPIO_PINCFG75_NCESRC75_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58571   GPIO_PINCFG75_NCESRC75_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58572   GPIO_PINCFG75_NCESRC75_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58573   GPIO_PINCFG75_NCESRC75_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58574   GPIO_PINCFG75_NCESRC75_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58575   GPIO_PINCFG75_NCESRC75_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58576   GPIO_PINCFG75_NCESRC75_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58577   GPIO_PINCFG75_NCESRC75_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58578   GPIO_PINCFG75_NCESRC75_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58579   GPIO_PINCFG75_NCESRC75_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58580   GPIO_PINCFG75_NCESRC75_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58581   GPIO_PINCFG75_NCESRC75_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58582   GPIO_PINCFG75_NCESRC75_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58583   GPIO_PINCFG75_NCESRC75_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58584   GPIO_PINCFG75_NCESRC75_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58585   GPIO_PINCFG75_NCESRC75_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58586   GPIO_PINCFG75_NCESRC75_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58587   GPIO_PINCFG75_NCESRC75_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58588   GPIO_PINCFG75_NCESRC75_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58589   GPIO_PINCFG75_NCESRC75_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58590   GPIO_PINCFG75_NCESRC75_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58591   GPIO_PINCFG75_NCESRC75_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58592   GPIO_PINCFG75_NCESRC75_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58593   GPIO_PINCFG75_NCESRC75_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58594   GPIO_PINCFG75_NCESRC75_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58595   GPIO_PINCFG75_NCESRC75_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58596   GPIO_PINCFG75_NCESRC75_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58597   GPIO_PINCFG75_NCESRC75_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58598   GPIO_PINCFG75_NCESRC75_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58599   GPIO_PINCFG75_NCESRC75_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58600   GPIO_PINCFG75_NCESRC75_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58601   GPIO_PINCFG75_NCESRC75_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58602   GPIO_PINCFG75_NCESRC75_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58603   GPIO_PINCFG75_NCESRC75_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58604   GPIO_PINCFG75_NCESRC75_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58605   GPIO_PINCFG75_NCESRC75_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58606   GPIO_PINCFG75_NCESRC75_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58607   GPIO_PINCFG75_NCESRC75_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58608   GPIO_PINCFG75_NCESRC75_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58609   GPIO_PINCFG75_NCESRC75_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58610   GPIO_PINCFG75_NCESRC75_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58611   GPIO_PINCFG75_NCESRC75_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58612   GPIO_PINCFG75_NCESRC75_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58613 } GPIO_PINCFG75_NCESRC75_Enum;
58614 
58615 /* ===========================================  GPIO PINCFG75 PULLCFG75 [13..15]  ============================================ */
58616 typedef enum {                                  /*!< GPIO_PINCFG75_PULLCFG75                                                   */
58617   GPIO_PINCFG75_PULLCFG75_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58618   GPIO_PINCFG75_PULLCFG75_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58619   GPIO_PINCFG75_PULLCFG75_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58620   GPIO_PINCFG75_PULLCFG75_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58621   GPIO_PINCFG75_PULLCFG75_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58622   GPIO_PINCFG75_PULLCFG75_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58623   GPIO_PINCFG75_PULLCFG75_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58624   GPIO_PINCFG75_PULLCFG75_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58625 } GPIO_PINCFG75_PULLCFG75_Enum;
58626 
58627 /* ==============================================  GPIO PINCFG75 DS75 [10..11]  ============================================== */
58628 typedef enum {                                  /*!< GPIO_PINCFG75_DS75                                                        */
58629   GPIO_PINCFG75_DS75_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58630   GPIO_PINCFG75_DS75_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58631   GPIO_PINCFG75_DS75_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58632   GPIO_PINCFG75_DS75_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58633 } GPIO_PINCFG75_DS75_Enum;
58634 
58635 /* =============================================  GPIO PINCFG75 OUTCFG75 [8..9]  ============================================= */
58636 typedef enum {                                  /*!< GPIO_PINCFG75_OUTCFG75                                                    */
58637   GPIO_PINCFG75_OUTCFG75_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58638   GPIO_PINCFG75_OUTCFG75_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58639                                                      and 1 values on pin.                                                      */
58640   GPIO_PINCFG75_OUTCFG75_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58641                                                      low, tristate otherwise.                                                  */
58642   GPIO_PINCFG75_OUTCFG75_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58643                                                      drive 0, 1 of HiZ on pin.                                                 */
58644 } GPIO_PINCFG75_OUTCFG75_Enum;
58645 
58646 /* =============================================  GPIO PINCFG75 IRPTEN75 [6..7]  ============================================= */
58647 typedef enum {                                  /*!< GPIO_PINCFG75_IRPTEN75                                                    */
58648   GPIO_PINCFG75_IRPTEN75_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58649   GPIO_PINCFG75_IRPTEN75_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58650                                                      on this GPIO                                                              */
58651   GPIO_PINCFG75_IRPTEN75_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58652                                                      on this GPIO                                                              */
58653   GPIO_PINCFG75_IRPTEN75_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58654                                                      GPIO                                                                      */
58655 } GPIO_PINCFG75_IRPTEN75_Enum;
58656 
58657 /* =============================================  GPIO PINCFG75 FNCSEL75 [0..3]  ============================================= */
58658 typedef enum {                                  /*!< GPIO_PINCFG75_FNCSEL75                                                    */
58659   GPIO_PINCFG75_FNCSEL75_MSPI2_1       = 0,     /*!< MSPI2_1 : MSPI Master 2 Interface Signal                                  */
58660   GPIO_PINCFG75_FNCSEL75_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
58661   GPIO_PINCFG75_FNCSEL75_DISP_QSPI_D1  = 2,     /*!< DISP_QSPI_D1 : Display SPI Data1                                          */
58662   GPIO_PINCFG75_FNCSEL75_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58663   GPIO_PINCFG75_FNCSEL75_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
58664   GPIO_PINCFG75_FNCSEL75_DISP_D11      = 5,     /*!< DISP_D11 : Display Data 11                                                */
58665   GPIO_PINCFG75_FNCSEL75_CT75          = 6,     /*!< CT75 : Timer/Counter input or output; Selection of direction
58666                                                      is done via CTIMER register settings.                                     */
58667   GPIO_PINCFG75_FNCSEL75_NCE75         = 7,     /*!< NCE75 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58668                                                      CE_POLARITY field                                                         */
58669   GPIO_PINCFG75_FNCSEL75_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
58670   GPIO_PINCFG75_FNCSEL75_DISP_SPI_DCX  = 9,     /*!< DISP_SPI_DCX : Display SPI DCx                                            */
58671   GPIO_PINCFG75_FNCSEL75_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58672   GPIO_PINCFG75_FNCSEL75_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58673   GPIO_PINCFG75_FNCSEL75_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58674   GPIO_PINCFG75_FNCSEL75_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58675   GPIO_PINCFG75_FNCSEL75_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58676   GPIO_PINCFG75_FNCSEL75_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58677 } GPIO_PINCFG75_FNCSEL75_Enum;
58678 
58679 /* =======================================================  PINCFG76  ======================================================== */
58680 /* ============================================  GPIO PINCFG76 NCEPOL76 [22..22]  ============================================ */
58681 typedef enum {                                  /*!< GPIO_PINCFG76_NCEPOL76                                                    */
58682   GPIO_PINCFG76_NCEPOL76_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58683   GPIO_PINCFG76_NCEPOL76_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58684 } GPIO_PINCFG76_NCEPOL76_Enum;
58685 
58686 /* ============================================  GPIO PINCFG76 NCESRC76 [16..21]  ============================================ */
58687 typedef enum {                                  /*!< GPIO_PINCFG76_NCESRC76                                                    */
58688   GPIO_PINCFG76_NCESRC76_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58689   GPIO_PINCFG76_NCESRC76_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58690   GPIO_PINCFG76_NCESRC76_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58691   GPIO_PINCFG76_NCESRC76_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58692   GPIO_PINCFG76_NCESRC76_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58693   GPIO_PINCFG76_NCESRC76_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58694   GPIO_PINCFG76_NCESRC76_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58695   GPIO_PINCFG76_NCESRC76_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58696   GPIO_PINCFG76_NCESRC76_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58697   GPIO_PINCFG76_NCESRC76_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58698   GPIO_PINCFG76_NCESRC76_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58699   GPIO_PINCFG76_NCESRC76_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58700   GPIO_PINCFG76_NCESRC76_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58701   GPIO_PINCFG76_NCESRC76_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58702   GPIO_PINCFG76_NCESRC76_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58703   GPIO_PINCFG76_NCESRC76_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58704   GPIO_PINCFG76_NCESRC76_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58705   GPIO_PINCFG76_NCESRC76_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58706   GPIO_PINCFG76_NCESRC76_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58707   GPIO_PINCFG76_NCESRC76_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58708   GPIO_PINCFG76_NCESRC76_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58709   GPIO_PINCFG76_NCESRC76_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58710   GPIO_PINCFG76_NCESRC76_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58711   GPIO_PINCFG76_NCESRC76_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58712   GPIO_PINCFG76_NCESRC76_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58713   GPIO_PINCFG76_NCESRC76_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58714   GPIO_PINCFG76_NCESRC76_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58715   GPIO_PINCFG76_NCESRC76_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58716   GPIO_PINCFG76_NCESRC76_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58717   GPIO_PINCFG76_NCESRC76_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58718   GPIO_PINCFG76_NCESRC76_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58719   GPIO_PINCFG76_NCESRC76_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58720   GPIO_PINCFG76_NCESRC76_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58721   GPIO_PINCFG76_NCESRC76_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58722   GPIO_PINCFG76_NCESRC76_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58723   GPIO_PINCFG76_NCESRC76_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58724   GPIO_PINCFG76_NCESRC76_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58725   GPIO_PINCFG76_NCESRC76_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58726   GPIO_PINCFG76_NCESRC76_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58727   GPIO_PINCFG76_NCESRC76_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58728   GPIO_PINCFG76_NCESRC76_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58729   GPIO_PINCFG76_NCESRC76_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58730   GPIO_PINCFG76_NCESRC76_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58731 } GPIO_PINCFG76_NCESRC76_Enum;
58732 
58733 /* ===========================================  GPIO PINCFG76 PULLCFG76 [13..15]  ============================================ */
58734 typedef enum {                                  /*!< GPIO_PINCFG76_PULLCFG76                                                   */
58735   GPIO_PINCFG76_PULLCFG76_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58736   GPIO_PINCFG76_PULLCFG76_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58737   GPIO_PINCFG76_PULLCFG76_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58738   GPIO_PINCFG76_PULLCFG76_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58739   GPIO_PINCFG76_PULLCFG76_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58740   GPIO_PINCFG76_PULLCFG76_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58741   GPIO_PINCFG76_PULLCFG76_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58742   GPIO_PINCFG76_PULLCFG76_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58743 } GPIO_PINCFG76_PULLCFG76_Enum;
58744 
58745 /* ==============================================  GPIO PINCFG76 DS76 [10..11]  ============================================== */
58746 typedef enum {                                  /*!< GPIO_PINCFG76_DS76                                                        */
58747   GPIO_PINCFG76_DS76_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58748   GPIO_PINCFG76_DS76_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58749   GPIO_PINCFG76_DS76_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58750   GPIO_PINCFG76_DS76_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58751 } GPIO_PINCFG76_DS76_Enum;
58752 
58753 /* =============================================  GPIO PINCFG76 OUTCFG76 [8..9]  ============================================= */
58754 typedef enum {                                  /*!< GPIO_PINCFG76_OUTCFG76                                                    */
58755   GPIO_PINCFG76_OUTCFG76_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58756   GPIO_PINCFG76_OUTCFG76_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58757                                                      and 1 values on pin.                                                      */
58758   GPIO_PINCFG76_OUTCFG76_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58759                                                      low, tristate otherwise.                                                  */
58760   GPIO_PINCFG76_OUTCFG76_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58761                                                      drive 0, 1 of HiZ on pin.                                                 */
58762 } GPIO_PINCFG76_OUTCFG76_Enum;
58763 
58764 /* =============================================  GPIO PINCFG76 IRPTEN76 [6..7]  ============================================= */
58765 typedef enum {                                  /*!< GPIO_PINCFG76_IRPTEN76                                                    */
58766   GPIO_PINCFG76_IRPTEN76_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58767   GPIO_PINCFG76_IRPTEN76_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58768                                                      on this GPIO                                                              */
58769   GPIO_PINCFG76_IRPTEN76_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58770                                                      on this GPIO                                                              */
58771   GPIO_PINCFG76_IRPTEN76_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58772                                                      GPIO                                                                      */
58773 } GPIO_PINCFG76_IRPTEN76_Enum;
58774 
58775 /* =============================================  GPIO PINCFG76 FNCSEL76 [0..3]  ============================================= */
58776 typedef enum {                                  /*!< GPIO_PINCFG76_FNCSEL76                                                    */
58777   GPIO_PINCFG76_FNCSEL76_MSPI2_2       = 0,     /*!< MSPI2_2 : MSPI Master 2 Interface Signal                                  */
58778   GPIO_PINCFG76_FNCSEL76_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
58779   GPIO_PINCFG76_FNCSEL76_DISP_QSPI_D2  = 2,     /*!< DISP_QSPI_D2 : Display SPI Data2                                          */
58780   GPIO_PINCFG76_FNCSEL76_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58781   GPIO_PINCFG76_FNCSEL76_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
58782   GPIO_PINCFG76_FNCSEL76_DISP_D12      = 5,     /*!< DISP_D12 : Display Data 12                                                */
58783   GPIO_PINCFG76_FNCSEL76_CT76          = 6,     /*!< CT76 : Timer/Counter input or output; Selection of direction
58784                                                      is done via CTIMER register settings.                                     */
58785   GPIO_PINCFG76_FNCSEL76_NCE76         = 7,     /*!< NCE76 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58786                                                      CE_POLARITY field                                                         */
58787   GPIO_PINCFG76_FNCSEL76_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
58788   GPIO_PINCFG76_FNCSEL76_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58789   GPIO_PINCFG76_FNCSEL76_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58790   GPIO_PINCFG76_FNCSEL76_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58791   GPIO_PINCFG76_FNCSEL76_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58792   GPIO_PINCFG76_FNCSEL76_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58793   GPIO_PINCFG76_FNCSEL76_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58794   GPIO_PINCFG76_FNCSEL76_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58795 } GPIO_PINCFG76_FNCSEL76_Enum;
58796 
58797 /* =======================================================  PINCFG77  ======================================================== */
58798 /* ============================================  GPIO PINCFG77 NCEPOL77 [22..22]  ============================================ */
58799 typedef enum {                                  /*!< GPIO_PINCFG77_NCEPOL77                                                    */
58800   GPIO_PINCFG77_NCEPOL77_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58801   GPIO_PINCFG77_NCEPOL77_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58802 } GPIO_PINCFG77_NCEPOL77_Enum;
58803 
58804 /* ============================================  GPIO PINCFG77 NCESRC77 [16..21]  ============================================ */
58805 typedef enum {                                  /*!< GPIO_PINCFG77_NCESRC77                                                    */
58806   GPIO_PINCFG77_NCESRC77_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58807   GPIO_PINCFG77_NCESRC77_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58808   GPIO_PINCFG77_NCESRC77_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58809   GPIO_PINCFG77_NCESRC77_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58810   GPIO_PINCFG77_NCESRC77_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58811   GPIO_PINCFG77_NCESRC77_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58812   GPIO_PINCFG77_NCESRC77_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58813   GPIO_PINCFG77_NCESRC77_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58814   GPIO_PINCFG77_NCESRC77_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58815   GPIO_PINCFG77_NCESRC77_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58816   GPIO_PINCFG77_NCESRC77_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58817   GPIO_PINCFG77_NCESRC77_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58818   GPIO_PINCFG77_NCESRC77_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58819   GPIO_PINCFG77_NCESRC77_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58820   GPIO_PINCFG77_NCESRC77_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58821   GPIO_PINCFG77_NCESRC77_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58822   GPIO_PINCFG77_NCESRC77_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58823   GPIO_PINCFG77_NCESRC77_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58824   GPIO_PINCFG77_NCESRC77_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58825   GPIO_PINCFG77_NCESRC77_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58826   GPIO_PINCFG77_NCESRC77_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58827   GPIO_PINCFG77_NCESRC77_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58828   GPIO_PINCFG77_NCESRC77_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58829   GPIO_PINCFG77_NCESRC77_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58830   GPIO_PINCFG77_NCESRC77_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58831   GPIO_PINCFG77_NCESRC77_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58832   GPIO_PINCFG77_NCESRC77_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58833   GPIO_PINCFG77_NCESRC77_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58834   GPIO_PINCFG77_NCESRC77_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58835   GPIO_PINCFG77_NCESRC77_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58836   GPIO_PINCFG77_NCESRC77_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58837   GPIO_PINCFG77_NCESRC77_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58838   GPIO_PINCFG77_NCESRC77_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58839   GPIO_PINCFG77_NCESRC77_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58840   GPIO_PINCFG77_NCESRC77_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58841   GPIO_PINCFG77_NCESRC77_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58842   GPIO_PINCFG77_NCESRC77_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58843   GPIO_PINCFG77_NCESRC77_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58844   GPIO_PINCFG77_NCESRC77_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58845   GPIO_PINCFG77_NCESRC77_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58846   GPIO_PINCFG77_NCESRC77_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58847   GPIO_PINCFG77_NCESRC77_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58848   GPIO_PINCFG77_NCESRC77_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58849 } GPIO_PINCFG77_NCESRC77_Enum;
58850 
58851 /* ===========================================  GPIO PINCFG77 PULLCFG77 [13..15]  ============================================ */
58852 typedef enum {                                  /*!< GPIO_PINCFG77_PULLCFG77                                                   */
58853   GPIO_PINCFG77_PULLCFG77_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58854   GPIO_PINCFG77_PULLCFG77_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58855   GPIO_PINCFG77_PULLCFG77_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58856   GPIO_PINCFG77_PULLCFG77_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58857   GPIO_PINCFG77_PULLCFG77_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58858   GPIO_PINCFG77_PULLCFG77_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58859   GPIO_PINCFG77_PULLCFG77_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58860   GPIO_PINCFG77_PULLCFG77_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58861 } GPIO_PINCFG77_PULLCFG77_Enum;
58862 
58863 /* ==============================================  GPIO PINCFG77 DS77 [10..11]  ============================================== */
58864 typedef enum {                                  /*!< GPIO_PINCFG77_DS77                                                        */
58865   GPIO_PINCFG77_DS77_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58866   GPIO_PINCFG77_DS77_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58867   GPIO_PINCFG77_DS77_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58868   GPIO_PINCFG77_DS77_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58869 } GPIO_PINCFG77_DS77_Enum;
58870 
58871 /* =============================================  GPIO PINCFG77 OUTCFG77 [8..9]  ============================================= */
58872 typedef enum {                                  /*!< GPIO_PINCFG77_OUTCFG77                                                    */
58873   GPIO_PINCFG77_OUTCFG77_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58874   GPIO_PINCFG77_OUTCFG77_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58875                                                      and 1 values on pin.                                                      */
58876   GPIO_PINCFG77_OUTCFG77_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58877                                                      low, tristate otherwise.                                                  */
58878   GPIO_PINCFG77_OUTCFG77_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58879                                                      drive 0, 1 of HiZ on pin.                                                 */
58880 } GPIO_PINCFG77_OUTCFG77_Enum;
58881 
58882 /* =============================================  GPIO PINCFG77 IRPTEN77 [6..7]  ============================================= */
58883 typedef enum {                                  /*!< GPIO_PINCFG77_IRPTEN77                                                    */
58884   GPIO_PINCFG77_IRPTEN77_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58885   GPIO_PINCFG77_IRPTEN77_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58886                                                      on this GPIO                                                              */
58887   GPIO_PINCFG77_IRPTEN77_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58888                                                      on this GPIO                                                              */
58889   GPIO_PINCFG77_IRPTEN77_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58890                                                      GPIO                                                                      */
58891 } GPIO_PINCFG77_IRPTEN77_Enum;
58892 
58893 /* =============================================  GPIO PINCFG77 FNCSEL77 [0..3]  ============================================= */
58894 typedef enum {                                  /*!< GPIO_PINCFG77_FNCSEL77                                                    */
58895   GPIO_PINCFG77_FNCSEL77_MSPI2_3       = 0,     /*!< MSPI2_3 : MSPI Master 2 Interface Signal                                  */
58896   GPIO_PINCFG77_FNCSEL77_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
58897   GPIO_PINCFG77_FNCSEL77_DISP_QSPI_D3  = 2,     /*!< DISP_QSPI_D3 : Display SPI Data3                                          */
58898   GPIO_PINCFG77_FNCSEL77_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58899   GPIO_PINCFG77_FNCSEL77_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
58900   GPIO_PINCFG77_FNCSEL77_DISP_D13      = 5,     /*!< DISP_D13 : Display Data 13                                                */
58901   GPIO_PINCFG77_FNCSEL77_CT77          = 6,     /*!< CT77 : Timer/Counter input or output; Selection of direction
58902                                                      is done via CTIMER register settings.                                     */
58903   GPIO_PINCFG77_FNCSEL77_NCE77         = 7,     /*!< NCE77 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58904                                                      CE_POLARITY field                                                         */
58905   GPIO_PINCFG77_FNCSEL77_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
58906   GPIO_PINCFG77_FNCSEL77_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58907   GPIO_PINCFG77_FNCSEL77_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58908   GPIO_PINCFG77_FNCSEL77_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58909   GPIO_PINCFG77_FNCSEL77_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58910   GPIO_PINCFG77_FNCSEL77_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58911   GPIO_PINCFG77_FNCSEL77_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58912   GPIO_PINCFG77_FNCSEL77_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58913 } GPIO_PINCFG77_FNCSEL77_Enum;
58914 
58915 /* =======================================================  PINCFG78  ======================================================== */
58916 /* ============================================  GPIO PINCFG78 NCEPOL78 [22..22]  ============================================ */
58917 typedef enum {                                  /*!< GPIO_PINCFG78_NCEPOL78                                                    */
58918   GPIO_PINCFG78_NCEPOL78_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58919   GPIO_PINCFG78_NCEPOL78_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58920 } GPIO_PINCFG78_NCEPOL78_Enum;
58921 
58922 /* ============================================  GPIO PINCFG78 NCESRC78 [16..21]  ============================================ */
58923 typedef enum {                                  /*!< GPIO_PINCFG78_NCESRC78                                                    */
58924   GPIO_PINCFG78_NCESRC78_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58925   GPIO_PINCFG78_NCESRC78_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58926   GPIO_PINCFG78_NCESRC78_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58927   GPIO_PINCFG78_NCESRC78_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58928   GPIO_PINCFG78_NCESRC78_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58929   GPIO_PINCFG78_NCESRC78_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58930   GPIO_PINCFG78_NCESRC78_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58931   GPIO_PINCFG78_NCESRC78_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58932   GPIO_PINCFG78_NCESRC78_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58933   GPIO_PINCFG78_NCESRC78_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58934   GPIO_PINCFG78_NCESRC78_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58935   GPIO_PINCFG78_NCESRC78_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58936   GPIO_PINCFG78_NCESRC78_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58937   GPIO_PINCFG78_NCESRC78_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58938   GPIO_PINCFG78_NCESRC78_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58939   GPIO_PINCFG78_NCESRC78_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58940   GPIO_PINCFG78_NCESRC78_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58941   GPIO_PINCFG78_NCESRC78_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58942   GPIO_PINCFG78_NCESRC78_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58943   GPIO_PINCFG78_NCESRC78_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58944   GPIO_PINCFG78_NCESRC78_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58945   GPIO_PINCFG78_NCESRC78_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58946   GPIO_PINCFG78_NCESRC78_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58947   GPIO_PINCFG78_NCESRC78_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58948   GPIO_PINCFG78_NCESRC78_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58949   GPIO_PINCFG78_NCESRC78_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58950   GPIO_PINCFG78_NCESRC78_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58951   GPIO_PINCFG78_NCESRC78_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58952   GPIO_PINCFG78_NCESRC78_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58953   GPIO_PINCFG78_NCESRC78_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58954   GPIO_PINCFG78_NCESRC78_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58955   GPIO_PINCFG78_NCESRC78_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58956   GPIO_PINCFG78_NCESRC78_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58957   GPIO_PINCFG78_NCESRC78_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58958   GPIO_PINCFG78_NCESRC78_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58959   GPIO_PINCFG78_NCESRC78_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58960   GPIO_PINCFG78_NCESRC78_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58961   GPIO_PINCFG78_NCESRC78_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58962   GPIO_PINCFG78_NCESRC78_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58963   GPIO_PINCFG78_NCESRC78_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58964   GPIO_PINCFG78_NCESRC78_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58965   GPIO_PINCFG78_NCESRC78_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58966   GPIO_PINCFG78_NCESRC78_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58967 } GPIO_PINCFG78_NCESRC78_Enum;
58968 
58969 /* ===========================================  GPIO PINCFG78 PULLCFG78 [13..15]  ============================================ */
58970 typedef enum {                                  /*!< GPIO_PINCFG78_PULLCFG78                                                   */
58971   GPIO_PINCFG78_PULLCFG78_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58972   GPIO_PINCFG78_PULLCFG78_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58973   GPIO_PINCFG78_PULLCFG78_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58974   GPIO_PINCFG78_PULLCFG78_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58975   GPIO_PINCFG78_PULLCFG78_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58976   GPIO_PINCFG78_PULLCFG78_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58977   GPIO_PINCFG78_PULLCFG78_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58978   GPIO_PINCFG78_PULLCFG78_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58979 } GPIO_PINCFG78_PULLCFG78_Enum;
58980 
58981 /* ==============================================  GPIO PINCFG78 DS78 [10..11]  ============================================== */
58982 typedef enum {                                  /*!< GPIO_PINCFG78_DS78                                                        */
58983   GPIO_PINCFG78_DS78_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58984   GPIO_PINCFG78_DS78_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58985   GPIO_PINCFG78_DS78_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58986   GPIO_PINCFG78_DS78_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58987 } GPIO_PINCFG78_DS78_Enum;
58988 
58989 /* =============================================  GPIO PINCFG78 OUTCFG78 [8..9]  ============================================= */
58990 typedef enum {                                  /*!< GPIO_PINCFG78_OUTCFG78                                                    */
58991   GPIO_PINCFG78_OUTCFG78_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58992   GPIO_PINCFG78_OUTCFG78_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58993                                                      and 1 values on pin.                                                      */
58994   GPIO_PINCFG78_OUTCFG78_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58995                                                      low, tristate otherwise.                                                  */
58996   GPIO_PINCFG78_OUTCFG78_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58997                                                      drive 0, 1 of HiZ on pin.                                                 */
58998 } GPIO_PINCFG78_OUTCFG78_Enum;
58999 
59000 /* =============================================  GPIO PINCFG78 IRPTEN78 [6..7]  ============================================= */
59001 typedef enum {                                  /*!< GPIO_PINCFG78_IRPTEN78                                                    */
59002   GPIO_PINCFG78_IRPTEN78_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59003   GPIO_PINCFG78_IRPTEN78_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59004                                                      on this GPIO                                                              */
59005   GPIO_PINCFG78_IRPTEN78_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59006                                                      on this GPIO                                                              */
59007   GPIO_PINCFG78_IRPTEN78_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59008                                                      GPIO                                                                      */
59009 } GPIO_PINCFG78_IRPTEN78_Enum;
59010 
59011 /* =============================================  GPIO PINCFG78 FNCSEL78 [0..3]  ============================================= */
59012 typedef enum {                                  /*!< GPIO_PINCFG78_FNCSEL78                                                    */
59013   GPIO_PINCFG78_FNCSEL78_MSPI2_4       = 0,     /*!< MSPI2_4 : MSPI Master 2 Interface Signal                                  */
59014   GPIO_PINCFG78_FNCSEL78_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
59015   GPIO_PINCFG78_FNCSEL78_DISP_QSPI_SCK = 2,     /*!< DISP_QSPI_SCK : Display SPI CLK                                           */
59016   GPIO_PINCFG78_FNCSEL78_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59017   GPIO_PINCFG78_FNCSEL78_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
59018   GPIO_PINCFG78_FNCSEL78_DISP_D14      = 5,     /*!< DISP_D14 : Display Data 14                                                */
59019   GPIO_PINCFG78_FNCSEL78_CT78          = 6,     /*!< CT78 : Timer/Counter input or output; Selection of direction
59020                                                      is done via CTIMER register settings.                                     */
59021   GPIO_PINCFG78_FNCSEL78_NCE78         = 7,     /*!< NCE78 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59022                                                      CE_POLARITY field                                                         */
59023   GPIO_PINCFG78_FNCSEL78_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
59024   GPIO_PINCFG78_FNCSEL78_DISP_SPI_SCK  = 9,     /*!< DISP_SPI_SCK : Display SPI Clock                                          */
59025   GPIO_PINCFG78_FNCSEL78_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59026   GPIO_PINCFG78_FNCSEL78_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59027   GPIO_PINCFG78_FNCSEL78_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59028   GPIO_PINCFG78_FNCSEL78_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59029   GPIO_PINCFG78_FNCSEL78_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59030   GPIO_PINCFG78_FNCSEL78_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59031 } GPIO_PINCFG78_FNCSEL78_Enum;
59032 
59033 /* =======================================================  PINCFG79  ======================================================== */
59034 /* ============================================  GPIO PINCFG79 NCEPOL79 [22..22]  ============================================ */
59035 typedef enum {                                  /*!< GPIO_PINCFG79_NCEPOL79                                                    */
59036   GPIO_PINCFG79_NCEPOL79_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59037   GPIO_PINCFG79_NCEPOL79_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59038 } GPIO_PINCFG79_NCEPOL79_Enum;
59039 
59040 /* ============================================  GPIO PINCFG79 NCESRC79 [16..21]  ============================================ */
59041 typedef enum {                                  /*!< GPIO_PINCFG79_NCESRC79                                                    */
59042   GPIO_PINCFG79_NCESRC79_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59043   GPIO_PINCFG79_NCESRC79_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59044   GPIO_PINCFG79_NCESRC79_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59045   GPIO_PINCFG79_NCESRC79_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59046   GPIO_PINCFG79_NCESRC79_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59047   GPIO_PINCFG79_NCESRC79_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59048   GPIO_PINCFG79_NCESRC79_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59049   GPIO_PINCFG79_NCESRC79_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59050   GPIO_PINCFG79_NCESRC79_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59051   GPIO_PINCFG79_NCESRC79_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59052   GPIO_PINCFG79_NCESRC79_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59053   GPIO_PINCFG79_NCESRC79_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59054   GPIO_PINCFG79_NCESRC79_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59055   GPIO_PINCFG79_NCESRC79_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59056   GPIO_PINCFG79_NCESRC79_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59057   GPIO_PINCFG79_NCESRC79_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59058   GPIO_PINCFG79_NCESRC79_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59059   GPIO_PINCFG79_NCESRC79_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59060   GPIO_PINCFG79_NCESRC79_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59061   GPIO_PINCFG79_NCESRC79_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59062   GPIO_PINCFG79_NCESRC79_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59063   GPIO_PINCFG79_NCESRC79_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59064   GPIO_PINCFG79_NCESRC79_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59065   GPIO_PINCFG79_NCESRC79_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59066   GPIO_PINCFG79_NCESRC79_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59067   GPIO_PINCFG79_NCESRC79_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59068   GPIO_PINCFG79_NCESRC79_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59069   GPIO_PINCFG79_NCESRC79_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59070   GPIO_PINCFG79_NCESRC79_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59071   GPIO_PINCFG79_NCESRC79_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59072   GPIO_PINCFG79_NCESRC79_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59073   GPIO_PINCFG79_NCESRC79_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59074   GPIO_PINCFG79_NCESRC79_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59075   GPIO_PINCFG79_NCESRC79_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59076   GPIO_PINCFG79_NCESRC79_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59077   GPIO_PINCFG79_NCESRC79_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59078   GPIO_PINCFG79_NCESRC79_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59079   GPIO_PINCFG79_NCESRC79_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59080   GPIO_PINCFG79_NCESRC79_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59081   GPIO_PINCFG79_NCESRC79_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59082   GPIO_PINCFG79_NCESRC79_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59083   GPIO_PINCFG79_NCESRC79_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59084   GPIO_PINCFG79_NCESRC79_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59085 } GPIO_PINCFG79_NCESRC79_Enum;
59086 
59087 /* ===========================================  GPIO PINCFG79 PULLCFG79 [13..15]  ============================================ */
59088 typedef enum {                                  /*!< GPIO_PINCFG79_PULLCFG79                                                   */
59089   GPIO_PINCFG79_PULLCFG79_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59090   GPIO_PINCFG79_PULLCFG79_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59091   GPIO_PINCFG79_PULLCFG79_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59092   GPIO_PINCFG79_PULLCFG79_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59093   GPIO_PINCFG79_PULLCFG79_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59094   GPIO_PINCFG79_PULLCFG79_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59095   GPIO_PINCFG79_PULLCFG79_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59096   GPIO_PINCFG79_PULLCFG79_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59097 } GPIO_PINCFG79_PULLCFG79_Enum;
59098 
59099 /* ==============================================  GPIO PINCFG79 DS79 [10..11]  ============================================== */
59100 typedef enum {                                  /*!< GPIO_PINCFG79_DS79                                                        */
59101   GPIO_PINCFG79_DS79_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59102   GPIO_PINCFG79_DS79_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59103   GPIO_PINCFG79_DS79_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59104   GPIO_PINCFG79_DS79_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59105 } GPIO_PINCFG79_DS79_Enum;
59106 
59107 /* =============================================  GPIO PINCFG79 OUTCFG79 [8..9]  ============================================= */
59108 typedef enum {                                  /*!< GPIO_PINCFG79_OUTCFG79                                                    */
59109   GPIO_PINCFG79_OUTCFG79_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59110   GPIO_PINCFG79_OUTCFG79_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59111                                                      and 1 values on pin.                                                      */
59112   GPIO_PINCFG79_OUTCFG79_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59113                                                      low, tristate otherwise.                                                  */
59114   GPIO_PINCFG79_OUTCFG79_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59115                                                      drive 0, 1 of HiZ on pin.                                                 */
59116 } GPIO_PINCFG79_OUTCFG79_Enum;
59117 
59118 /* =============================================  GPIO PINCFG79 IRPTEN79 [6..7]  ============================================= */
59119 typedef enum {                                  /*!< GPIO_PINCFG79_IRPTEN79                                                    */
59120   GPIO_PINCFG79_IRPTEN79_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59121   GPIO_PINCFG79_IRPTEN79_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59122                                                      on this GPIO                                                              */
59123   GPIO_PINCFG79_IRPTEN79_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59124                                                      on this GPIO                                                              */
59125   GPIO_PINCFG79_IRPTEN79_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59126                                                      GPIO                                                                      */
59127 } GPIO_PINCFG79_IRPTEN79_Enum;
59128 
59129 /* =============================================  GPIO PINCFG79 FNCSEL79 [0..3]  ============================================= */
59130 typedef enum {                                  /*!< GPIO_PINCFG79_FNCSEL79                                                    */
59131   GPIO_PINCFG79_FNCSEL79_MSPI2_5       = 0,     /*!< MSPI2_5 : MSPI Master 2 Interface Signal                                  */
59132   GPIO_PINCFG79_FNCSEL79_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
59133   GPIO_PINCFG79_FNCSEL79_SDIF_DAT4     = 2,     /*!< SDIF_DAT4 : SD/SDIO/MMC Data4 pin                                         */
59134   GPIO_PINCFG79_FNCSEL79_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59135   GPIO_PINCFG79_FNCSEL79_SWO           = 4,     /*!< SWO : Serial Wire Output                                                  */
59136   GPIO_PINCFG79_FNCSEL79_DISP_VS       = 5,     /*!< DISP_VS : Display RGB VSYNC                                               */
59137   GPIO_PINCFG79_FNCSEL79_CT79          = 6,     /*!< CT79 : Timer/Counter input or output; Selection of direction
59138                                                      is done via CTIMER register settings.                                     */
59139   GPIO_PINCFG79_FNCSEL79_NCE79         = 7,     /*!< NCE79 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59140                                                      CE_POLARITY field                                                         */
59141   GPIO_PINCFG79_FNCSEL79_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
59142   GPIO_PINCFG79_FNCSEL79_DISP_SPI_SDI  = 9,     /*!< DISP_SPI_SDI : Display SPI Data IN                                        */
59143   GPIO_PINCFG79_FNCSEL79_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59144   GPIO_PINCFG79_FNCSEL79_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59145   GPIO_PINCFG79_FNCSEL79_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59146   GPIO_PINCFG79_FNCSEL79_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59147   GPIO_PINCFG79_FNCSEL79_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59148   GPIO_PINCFG79_FNCSEL79_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59149 } GPIO_PINCFG79_FNCSEL79_Enum;
59150 
59151 /* =======================================================  PINCFG80  ======================================================== */
59152 /* ============================================  GPIO PINCFG80 NCEPOL80 [22..22]  ============================================ */
59153 typedef enum {                                  /*!< GPIO_PINCFG80_NCEPOL80                                                    */
59154   GPIO_PINCFG80_NCEPOL80_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59155   GPIO_PINCFG80_NCEPOL80_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59156 } GPIO_PINCFG80_NCEPOL80_Enum;
59157 
59158 /* ============================================  GPIO PINCFG80 NCESRC80 [16..21]  ============================================ */
59159 typedef enum {                                  /*!< GPIO_PINCFG80_NCESRC80                                                    */
59160   GPIO_PINCFG80_NCESRC80_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59161   GPIO_PINCFG80_NCESRC80_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59162   GPIO_PINCFG80_NCESRC80_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59163   GPIO_PINCFG80_NCESRC80_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59164   GPIO_PINCFG80_NCESRC80_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59165   GPIO_PINCFG80_NCESRC80_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59166   GPIO_PINCFG80_NCESRC80_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59167   GPIO_PINCFG80_NCESRC80_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59168   GPIO_PINCFG80_NCESRC80_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59169   GPIO_PINCFG80_NCESRC80_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59170   GPIO_PINCFG80_NCESRC80_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59171   GPIO_PINCFG80_NCESRC80_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59172   GPIO_PINCFG80_NCESRC80_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59173   GPIO_PINCFG80_NCESRC80_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59174   GPIO_PINCFG80_NCESRC80_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59175   GPIO_PINCFG80_NCESRC80_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59176   GPIO_PINCFG80_NCESRC80_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59177   GPIO_PINCFG80_NCESRC80_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59178   GPIO_PINCFG80_NCESRC80_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59179   GPIO_PINCFG80_NCESRC80_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59180   GPIO_PINCFG80_NCESRC80_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59181   GPIO_PINCFG80_NCESRC80_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59182   GPIO_PINCFG80_NCESRC80_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59183   GPIO_PINCFG80_NCESRC80_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59184   GPIO_PINCFG80_NCESRC80_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59185   GPIO_PINCFG80_NCESRC80_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59186   GPIO_PINCFG80_NCESRC80_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59187   GPIO_PINCFG80_NCESRC80_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59188   GPIO_PINCFG80_NCESRC80_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59189   GPIO_PINCFG80_NCESRC80_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59190   GPIO_PINCFG80_NCESRC80_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59191   GPIO_PINCFG80_NCESRC80_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59192   GPIO_PINCFG80_NCESRC80_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59193   GPIO_PINCFG80_NCESRC80_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59194   GPIO_PINCFG80_NCESRC80_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59195   GPIO_PINCFG80_NCESRC80_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59196   GPIO_PINCFG80_NCESRC80_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59197   GPIO_PINCFG80_NCESRC80_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59198   GPIO_PINCFG80_NCESRC80_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59199   GPIO_PINCFG80_NCESRC80_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59200   GPIO_PINCFG80_NCESRC80_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59201   GPIO_PINCFG80_NCESRC80_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59202   GPIO_PINCFG80_NCESRC80_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59203 } GPIO_PINCFG80_NCESRC80_Enum;
59204 
59205 /* ===========================================  GPIO PINCFG80 PULLCFG80 [13..15]  ============================================ */
59206 typedef enum {                                  /*!< GPIO_PINCFG80_PULLCFG80                                                   */
59207   GPIO_PINCFG80_PULLCFG80_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59208   GPIO_PINCFG80_PULLCFG80_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59209   GPIO_PINCFG80_PULLCFG80_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59210   GPIO_PINCFG80_PULLCFG80_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59211   GPIO_PINCFG80_PULLCFG80_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59212   GPIO_PINCFG80_PULLCFG80_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59213   GPIO_PINCFG80_PULLCFG80_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59214   GPIO_PINCFG80_PULLCFG80_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59215 } GPIO_PINCFG80_PULLCFG80_Enum;
59216 
59217 /* ==============================================  GPIO PINCFG80 DS80 [10..11]  ============================================== */
59218 typedef enum {                                  /*!< GPIO_PINCFG80_DS80                                                        */
59219   GPIO_PINCFG80_DS80_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59220   GPIO_PINCFG80_DS80_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59221   GPIO_PINCFG80_DS80_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59222   GPIO_PINCFG80_DS80_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59223 } GPIO_PINCFG80_DS80_Enum;
59224 
59225 /* =============================================  GPIO PINCFG80 OUTCFG80 [8..9]  ============================================= */
59226 typedef enum {                                  /*!< GPIO_PINCFG80_OUTCFG80                                                    */
59227   GPIO_PINCFG80_OUTCFG80_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59228   GPIO_PINCFG80_OUTCFG80_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59229                                                      and 1 values on pin.                                                      */
59230   GPIO_PINCFG80_OUTCFG80_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59231                                                      low, tristate otherwise.                                                  */
59232   GPIO_PINCFG80_OUTCFG80_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59233                                                      drive 0, 1 of HiZ on pin.                                                 */
59234 } GPIO_PINCFG80_OUTCFG80_Enum;
59235 
59236 /* =============================================  GPIO PINCFG80 IRPTEN80 [6..7]  ============================================= */
59237 typedef enum {                                  /*!< GPIO_PINCFG80_IRPTEN80                                                    */
59238   GPIO_PINCFG80_IRPTEN80_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59239   GPIO_PINCFG80_IRPTEN80_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59240                                                      on this GPIO                                                              */
59241   GPIO_PINCFG80_IRPTEN80_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59242                                                      on this GPIO                                                              */
59243   GPIO_PINCFG80_IRPTEN80_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59244                                                      GPIO                                                                      */
59245 } GPIO_PINCFG80_IRPTEN80_Enum;
59246 
59247 /* =============================================  GPIO PINCFG80 FNCSEL80 [0..3]  ============================================= */
59248 typedef enum {                                  /*!< GPIO_PINCFG80_FNCSEL80                                                    */
59249   GPIO_PINCFG80_FNCSEL80_MSPI2_6       = 0,     /*!< MSPI2_6 : MSPI Master 2 Interface Signal                                  */
59250   GPIO_PINCFG80_FNCSEL80_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
59251   GPIO_PINCFG80_FNCSEL80_SDIF_DAT5     = 2,     /*!< SDIF_DAT5 : SD/SDIO/MMC Data5 pin                                         */
59252   GPIO_PINCFG80_FNCSEL80_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59253   GPIO_PINCFG80_FNCSEL80_SWTRACE0      = 4,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
59254   GPIO_PINCFG80_FNCSEL80_DISP_HS       = 5,     /*!< DISP_HS : Display RGB HSYNC                                               */
59255   GPIO_PINCFG80_FNCSEL80_CT80          = 6,     /*!< CT80 : Timer/Counter input or output; Selection of direction
59256                                                      is done via CTIMER register settings.                                     */
59257   GPIO_PINCFG80_FNCSEL80_NCE80         = 7,     /*!< NCE80 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59258                                                      CE_POLARITY field                                                         */
59259   GPIO_PINCFG80_FNCSEL80_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
59260   GPIO_PINCFG80_FNCSEL80_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59261   GPIO_PINCFG80_FNCSEL80_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59262   GPIO_PINCFG80_FNCSEL80_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59263   GPIO_PINCFG80_FNCSEL80_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59264   GPIO_PINCFG80_FNCSEL80_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59265   GPIO_PINCFG80_FNCSEL80_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59266   GPIO_PINCFG80_FNCSEL80_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59267 } GPIO_PINCFG80_FNCSEL80_Enum;
59268 
59269 /* =======================================================  PINCFG81  ======================================================== */
59270 /* ============================================  GPIO PINCFG81 NCEPOL81 [22..22]  ============================================ */
59271 typedef enum {                                  /*!< GPIO_PINCFG81_NCEPOL81                                                    */
59272   GPIO_PINCFG81_NCEPOL81_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59273   GPIO_PINCFG81_NCEPOL81_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59274 } GPIO_PINCFG81_NCEPOL81_Enum;
59275 
59276 /* ============================================  GPIO PINCFG81 NCESRC81 [16..21]  ============================================ */
59277 typedef enum {                                  /*!< GPIO_PINCFG81_NCESRC81                                                    */
59278   GPIO_PINCFG81_NCESRC81_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59279   GPIO_PINCFG81_NCESRC81_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59280   GPIO_PINCFG81_NCESRC81_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59281   GPIO_PINCFG81_NCESRC81_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59282   GPIO_PINCFG81_NCESRC81_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59283   GPIO_PINCFG81_NCESRC81_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59284   GPIO_PINCFG81_NCESRC81_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59285   GPIO_PINCFG81_NCESRC81_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59286   GPIO_PINCFG81_NCESRC81_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59287   GPIO_PINCFG81_NCESRC81_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59288   GPIO_PINCFG81_NCESRC81_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59289   GPIO_PINCFG81_NCESRC81_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59290   GPIO_PINCFG81_NCESRC81_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59291   GPIO_PINCFG81_NCESRC81_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59292   GPIO_PINCFG81_NCESRC81_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59293   GPIO_PINCFG81_NCESRC81_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59294   GPIO_PINCFG81_NCESRC81_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59295   GPIO_PINCFG81_NCESRC81_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59296   GPIO_PINCFG81_NCESRC81_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59297   GPIO_PINCFG81_NCESRC81_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59298   GPIO_PINCFG81_NCESRC81_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59299   GPIO_PINCFG81_NCESRC81_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59300   GPIO_PINCFG81_NCESRC81_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59301   GPIO_PINCFG81_NCESRC81_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59302   GPIO_PINCFG81_NCESRC81_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59303   GPIO_PINCFG81_NCESRC81_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59304   GPIO_PINCFG81_NCESRC81_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59305   GPIO_PINCFG81_NCESRC81_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59306   GPIO_PINCFG81_NCESRC81_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59307   GPIO_PINCFG81_NCESRC81_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59308   GPIO_PINCFG81_NCESRC81_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59309   GPIO_PINCFG81_NCESRC81_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59310   GPIO_PINCFG81_NCESRC81_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59311   GPIO_PINCFG81_NCESRC81_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59312   GPIO_PINCFG81_NCESRC81_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59313   GPIO_PINCFG81_NCESRC81_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59314   GPIO_PINCFG81_NCESRC81_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59315   GPIO_PINCFG81_NCESRC81_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59316   GPIO_PINCFG81_NCESRC81_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59317   GPIO_PINCFG81_NCESRC81_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59318   GPIO_PINCFG81_NCESRC81_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59319   GPIO_PINCFG81_NCESRC81_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59320   GPIO_PINCFG81_NCESRC81_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59321 } GPIO_PINCFG81_NCESRC81_Enum;
59322 
59323 /* ===========================================  GPIO PINCFG81 PULLCFG81 [13..15]  ============================================ */
59324 typedef enum {                                  /*!< GPIO_PINCFG81_PULLCFG81                                                   */
59325   GPIO_PINCFG81_PULLCFG81_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59326   GPIO_PINCFG81_PULLCFG81_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59327   GPIO_PINCFG81_PULLCFG81_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59328   GPIO_PINCFG81_PULLCFG81_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59329   GPIO_PINCFG81_PULLCFG81_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59330   GPIO_PINCFG81_PULLCFG81_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59331   GPIO_PINCFG81_PULLCFG81_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59332   GPIO_PINCFG81_PULLCFG81_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59333 } GPIO_PINCFG81_PULLCFG81_Enum;
59334 
59335 /* ==============================================  GPIO PINCFG81 DS81 [10..11]  ============================================== */
59336 typedef enum {                                  /*!< GPIO_PINCFG81_DS81                                                        */
59337   GPIO_PINCFG81_DS81_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59338   GPIO_PINCFG81_DS81_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59339   GPIO_PINCFG81_DS81_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59340   GPIO_PINCFG81_DS81_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59341 } GPIO_PINCFG81_DS81_Enum;
59342 
59343 /* =============================================  GPIO PINCFG81 OUTCFG81 [8..9]  ============================================= */
59344 typedef enum {                                  /*!< GPIO_PINCFG81_OUTCFG81                                                    */
59345   GPIO_PINCFG81_OUTCFG81_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59346   GPIO_PINCFG81_OUTCFG81_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59347                                                      and 1 values on pin.                                                      */
59348   GPIO_PINCFG81_OUTCFG81_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59349                                                      low, tristate otherwise.                                                  */
59350   GPIO_PINCFG81_OUTCFG81_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59351                                                      drive 0, 1 of HiZ on pin.                                                 */
59352 } GPIO_PINCFG81_OUTCFG81_Enum;
59353 
59354 /* =============================================  GPIO PINCFG81 IRPTEN81 [6..7]  ============================================= */
59355 typedef enum {                                  /*!< GPIO_PINCFG81_IRPTEN81                                                    */
59356   GPIO_PINCFG81_IRPTEN81_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59357   GPIO_PINCFG81_IRPTEN81_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59358                                                      on this GPIO                                                              */
59359   GPIO_PINCFG81_IRPTEN81_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59360                                                      on this GPIO                                                              */
59361   GPIO_PINCFG81_IRPTEN81_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59362                                                      GPIO                                                                      */
59363 } GPIO_PINCFG81_IRPTEN81_Enum;
59364 
59365 /* =============================================  GPIO PINCFG81 FNCSEL81 [0..3]  ============================================= */
59366 typedef enum {                                  /*!< GPIO_PINCFG81_FNCSEL81                                                    */
59367   GPIO_PINCFG81_FNCSEL81_MSPI2_7       = 0,     /*!< MSPI2_7 : MSPI Master 2 Interface Signal                                  */
59368   GPIO_PINCFG81_FNCSEL81_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
59369   GPIO_PINCFG81_FNCSEL81_SDIF_DAT6     = 2,     /*!< SDIF_DAT6 : SD/SDIO/MMC Data6 pin                                         */
59370   GPIO_PINCFG81_FNCSEL81_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59371   GPIO_PINCFG81_FNCSEL81_SWTRACE1      = 4,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
59372   GPIO_PINCFG81_FNCSEL81_DISP_DE       = 5,     /*!< DISP_DE : Display RGB Data Enable                                         */
59373   GPIO_PINCFG81_FNCSEL81_CT81          = 6,     /*!< CT81 : Timer/Counter input or output; Selection of direction
59374                                                      is done via CTIMER register settings.                                     */
59375   GPIO_PINCFG81_FNCSEL81_NCE81         = 7,     /*!< NCE81 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59376                                                      CE_POLARITY field                                                         */
59377   GPIO_PINCFG81_FNCSEL81_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
59378   GPIO_PINCFG81_FNCSEL81_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59379   GPIO_PINCFG81_FNCSEL81_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59380   GPIO_PINCFG81_FNCSEL81_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59381   GPIO_PINCFG81_FNCSEL81_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59382   GPIO_PINCFG81_FNCSEL81_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59383   GPIO_PINCFG81_FNCSEL81_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59384   GPIO_PINCFG81_FNCSEL81_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59385 } GPIO_PINCFG81_FNCSEL81_Enum;
59386 
59387 /* =======================================================  PINCFG82  ======================================================== */
59388 /* ============================================  GPIO PINCFG82 NCEPOL82 [22..22]  ============================================ */
59389 typedef enum {                                  /*!< GPIO_PINCFG82_NCEPOL82                                                    */
59390   GPIO_PINCFG82_NCEPOL82_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59391   GPIO_PINCFG82_NCEPOL82_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59392 } GPIO_PINCFG82_NCEPOL82_Enum;
59393 
59394 /* ============================================  GPIO PINCFG82 NCESRC82 [16..21]  ============================================ */
59395 typedef enum {                                  /*!< GPIO_PINCFG82_NCESRC82                                                    */
59396   GPIO_PINCFG82_NCESRC82_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59397   GPIO_PINCFG82_NCESRC82_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59398   GPIO_PINCFG82_NCESRC82_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59399   GPIO_PINCFG82_NCESRC82_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59400   GPIO_PINCFG82_NCESRC82_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59401   GPIO_PINCFG82_NCESRC82_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59402   GPIO_PINCFG82_NCESRC82_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59403   GPIO_PINCFG82_NCESRC82_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59404   GPIO_PINCFG82_NCESRC82_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59405   GPIO_PINCFG82_NCESRC82_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59406   GPIO_PINCFG82_NCESRC82_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59407   GPIO_PINCFG82_NCESRC82_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59408   GPIO_PINCFG82_NCESRC82_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59409   GPIO_PINCFG82_NCESRC82_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59410   GPIO_PINCFG82_NCESRC82_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59411   GPIO_PINCFG82_NCESRC82_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59412   GPIO_PINCFG82_NCESRC82_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59413   GPIO_PINCFG82_NCESRC82_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59414   GPIO_PINCFG82_NCESRC82_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59415   GPIO_PINCFG82_NCESRC82_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59416   GPIO_PINCFG82_NCESRC82_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59417   GPIO_PINCFG82_NCESRC82_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59418   GPIO_PINCFG82_NCESRC82_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59419   GPIO_PINCFG82_NCESRC82_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59420   GPIO_PINCFG82_NCESRC82_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59421   GPIO_PINCFG82_NCESRC82_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59422   GPIO_PINCFG82_NCESRC82_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59423   GPIO_PINCFG82_NCESRC82_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59424   GPIO_PINCFG82_NCESRC82_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59425   GPIO_PINCFG82_NCESRC82_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59426   GPIO_PINCFG82_NCESRC82_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59427   GPIO_PINCFG82_NCESRC82_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59428   GPIO_PINCFG82_NCESRC82_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59429   GPIO_PINCFG82_NCESRC82_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59430   GPIO_PINCFG82_NCESRC82_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59431   GPIO_PINCFG82_NCESRC82_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59432   GPIO_PINCFG82_NCESRC82_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59433   GPIO_PINCFG82_NCESRC82_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59434   GPIO_PINCFG82_NCESRC82_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59435   GPIO_PINCFG82_NCESRC82_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59436   GPIO_PINCFG82_NCESRC82_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59437   GPIO_PINCFG82_NCESRC82_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59438   GPIO_PINCFG82_NCESRC82_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59439 } GPIO_PINCFG82_NCESRC82_Enum;
59440 
59441 /* ===========================================  GPIO PINCFG82 PULLCFG82 [13..15]  ============================================ */
59442 typedef enum {                                  /*!< GPIO_PINCFG82_PULLCFG82                                                   */
59443   GPIO_PINCFG82_PULLCFG82_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59444   GPIO_PINCFG82_PULLCFG82_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59445   GPIO_PINCFG82_PULLCFG82_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59446   GPIO_PINCFG82_PULLCFG82_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59447   GPIO_PINCFG82_PULLCFG82_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59448   GPIO_PINCFG82_PULLCFG82_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59449   GPIO_PINCFG82_PULLCFG82_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59450   GPIO_PINCFG82_PULLCFG82_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59451 } GPIO_PINCFG82_PULLCFG82_Enum;
59452 
59453 /* ==============================================  GPIO PINCFG82 DS82 [10..11]  ============================================== */
59454 typedef enum {                                  /*!< GPIO_PINCFG82_DS82                                                        */
59455   GPIO_PINCFG82_DS82_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59456   GPIO_PINCFG82_DS82_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59457   GPIO_PINCFG82_DS82_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59458   GPIO_PINCFG82_DS82_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59459 } GPIO_PINCFG82_DS82_Enum;
59460 
59461 /* =============================================  GPIO PINCFG82 OUTCFG82 [8..9]  ============================================= */
59462 typedef enum {                                  /*!< GPIO_PINCFG82_OUTCFG82                                                    */
59463   GPIO_PINCFG82_OUTCFG82_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59464   GPIO_PINCFG82_OUTCFG82_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59465                                                      and 1 values on pin.                                                      */
59466   GPIO_PINCFG82_OUTCFG82_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59467                                                      low, tristate otherwise.                                                  */
59468   GPIO_PINCFG82_OUTCFG82_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59469                                                      drive 0, 1 of HiZ on pin.                                                 */
59470 } GPIO_PINCFG82_OUTCFG82_Enum;
59471 
59472 /* =============================================  GPIO PINCFG82 IRPTEN82 [6..7]  ============================================= */
59473 typedef enum {                                  /*!< GPIO_PINCFG82_IRPTEN82                                                    */
59474   GPIO_PINCFG82_IRPTEN82_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59475   GPIO_PINCFG82_IRPTEN82_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59476                                                      on this GPIO                                                              */
59477   GPIO_PINCFG82_IRPTEN82_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59478                                                      on this GPIO                                                              */
59479   GPIO_PINCFG82_IRPTEN82_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59480                                                      GPIO                                                                      */
59481 } GPIO_PINCFG82_IRPTEN82_Enum;
59482 
59483 /* =============================================  GPIO PINCFG82 FNCSEL82 [0..3]  ============================================= */
59484 typedef enum {                                  /*!< GPIO_PINCFG82_FNCSEL82                                                    */
59485   GPIO_PINCFG82_FNCSEL82_MSPI2_8       = 0,     /*!< MSPI2_8 : MSPI Master 2 Interface Signal                                  */
59486   GPIO_PINCFG82_FNCSEL82_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
59487   GPIO_PINCFG82_FNCSEL82_SDIF_DAT7     = 2,     /*!< SDIF_DAT7 : SD/SDIO/MMC Data7 pin                                         */
59488   GPIO_PINCFG82_FNCSEL82_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59489   GPIO_PINCFG82_FNCSEL82_SWTRACE2      = 4,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
59490   GPIO_PINCFG82_FNCSEL82_DISP_PCLK     = 5,     /*!< DISP_PCLK : Display RGB Pixel Clock                                       */
59491   GPIO_PINCFG82_FNCSEL82_CT82          = 6,     /*!< CT82 : Timer/Counter input or output; Selection of direction
59492                                                      is done via CTIMER register settings.                                     */
59493   GPIO_PINCFG82_FNCSEL82_NCE82         = 7,     /*!< NCE82 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59494                                                      CE_POLARITY field                                                         */
59495   GPIO_PINCFG82_FNCSEL82_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
59496   GPIO_PINCFG82_FNCSEL82_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59497   GPIO_PINCFG82_FNCSEL82_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59498   GPIO_PINCFG82_FNCSEL82_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59499   GPIO_PINCFG82_FNCSEL82_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59500   GPIO_PINCFG82_FNCSEL82_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59501   GPIO_PINCFG82_FNCSEL82_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59502   GPIO_PINCFG82_FNCSEL82_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59503 } GPIO_PINCFG82_FNCSEL82_Enum;
59504 
59505 /* =======================================================  PINCFG83  ======================================================== */
59506 /* ============================================  GPIO PINCFG83 NCEPOL83 [22..22]  ============================================ */
59507 typedef enum {                                  /*!< GPIO_PINCFG83_NCEPOL83                                                    */
59508   GPIO_PINCFG83_NCEPOL83_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59509   GPIO_PINCFG83_NCEPOL83_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59510 } GPIO_PINCFG83_NCEPOL83_Enum;
59511 
59512 /* ============================================  GPIO PINCFG83 NCESRC83 [16..21]  ============================================ */
59513 typedef enum {                                  /*!< GPIO_PINCFG83_NCESRC83                                                    */
59514   GPIO_PINCFG83_NCESRC83_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59515   GPIO_PINCFG83_NCESRC83_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59516   GPIO_PINCFG83_NCESRC83_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59517   GPIO_PINCFG83_NCESRC83_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59518   GPIO_PINCFG83_NCESRC83_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59519   GPIO_PINCFG83_NCESRC83_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59520   GPIO_PINCFG83_NCESRC83_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59521   GPIO_PINCFG83_NCESRC83_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59522   GPIO_PINCFG83_NCESRC83_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59523   GPIO_PINCFG83_NCESRC83_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59524   GPIO_PINCFG83_NCESRC83_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59525   GPIO_PINCFG83_NCESRC83_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59526   GPIO_PINCFG83_NCESRC83_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59527   GPIO_PINCFG83_NCESRC83_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59528   GPIO_PINCFG83_NCESRC83_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59529   GPIO_PINCFG83_NCESRC83_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59530   GPIO_PINCFG83_NCESRC83_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59531   GPIO_PINCFG83_NCESRC83_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59532   GPIO_PINCFG83_NCESRC83_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59533   GPIO_PINCFG83_NCESRC83_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59534   GPIO_PINCFG83_NCESRC83_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59535   GPIO_PINCFG83_NCESRC83_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59536   GPIO_PINCFG83_NCESRC83_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59537   GPIO_PINCFG83_NCESRC83_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59538   GPIO_PINCFG83_NCESRC83_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59539   GPIO_PINCFG83_NCESRC83_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59540   GPIO_PINCFG83_NCESRC83_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59541   GPIO_PINCFG83_NCESRC83_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59542   GPIO_PINCFG83_NCESRC83_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59543   GPIO_PINCFG83_NCESRC83_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59544   GPIO_PINCFG83_NCESRC83_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59545   GPIO_PINCFG83_NCESRC83_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59546   GPIO_PINCFG83_NCESRC83_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59547   GPIO_PINCFG83_NCESRC83_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59548   GPIO_PINCFG83_NCESRC83_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59549   GPIO_PINCFG83_NCESRC83_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59550   GPIO_PINCFG83_NCESRC83_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59551   GPIO_PINCFG83_NCESRC83_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59552   GPIO_PINCFG83_NCESRC83_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59553   GPIO_PINCFG83_NCESRC83_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59554   GPIO_PINCFG83_NCESRC83_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59555   GPIO_PINCFG83_NCESRC83_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59556   GPIO_PINCFG83_NCESRC83_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59557 } GPIO_PINCFG83_NCESRC83_Enum;
59558 
59559 /* ===========================================  GPIO PINCFG83 PULLCFG83 [13..15]  ============================================ */
59560 typedef enum {                                  /*!< GPIO_PINCFG83_PULLCFG83                                                   */
59561   GPIO_PINCFG83_PULLCFG83_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59562   GPIO_PINCFG83_PULLCFG83_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59563   GPIO_PINCFG83_PULLCFG83_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59564   GPIO_PINCFG83_PULLCFG83_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59565   GPIO_PINCFG83_PULLCFG83_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59566   GPIO_PINCFG83_PULLCFG83_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59567   GPIO_PINCFG83_PULLCFG83_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59568   GPIO_PINCFG83_PULLCFG83_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59569 } GPIO_PINCFG83_PULLCFG83_Enum;
59570 
59571 /* ==============================================  GPIO PINCFG83 DS83 [10..11]  ============================================== */
59572 typedef enum {                                  /*!< GPIO_PINCFG83_DS83                                                        */
59573   GPIO_PINCFG83_DS83_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59574   GPIO_PINCFG83_DS83_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59575   GPIO_PINCFG83_DS83_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59576   GPIO_PINCFG83_DS83_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59577 } GPIO_PINCFG83_DS83_Enum;
59578 
59579 /* =============================================  GPIO PINCFG83 OUTCFG83 [8..9]  ============================================= */
59580 typedef enum {                                  /*!< GPIO_PINCFG83_OUTCFG83                                                    */
59581   GPIO_PINCFG83_OUTCFG83_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59582   GPIO_PINCFG83_OUTCFG83_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59583                                                      and 1 values on pin.                                                      */
59584   GPIO_PINCFG83_OUTCFG83_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59585                                                      low, tristate otherwise.                                                  */
59586   GPIO_PINCFG83_OUTCFG83_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59587                                                      drive 0, 1 of HiZ on pin.                                                 */
59588 } GPIO_PINCFG83_OUTCFG83_Enum;
59589 
59590 /* =============================================  GPIO PINCFG83 IRPTEN83 [6..7]  ============================================= */
59591 typedef enum {                                  /*!< GPIO_PINCFG83_IRPTEN83                                                    */
59592   GPIO_PINCFG83_IRPTEN83_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59593   GPIO_PINCFG83_IRPTEN83_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59594                                                      on this GPIO                                                              */
59595   GPIO_PINCFG83_IRPTEN83_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59596                                                      on this GPIO                                                              */
59597   GPIO_PINCFG83_IRPTEN83_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59598                                                      GPIO                                                                      */
59599 } GPIO_PINCFG83_IRPTEN83_Enum;
59600 
59601 /* =============================================  GPIO PINCFG83 FNCSEL83 [0..3]  ============================================= */
59602 typedef enum {                                  /*!< GPIO_PINCFG83_FNCSEL83                                                    */
59603   GPIO_PINCFG83_FNCSEL83_MSPI2_9       = 0,     /*!< MSPI2_9 : MSPI Master 2 Interface Signal                                  */
59604   GPIO_PINCFG83_FNCSEL83_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
59605   GPIO_PINCFG83_FNCSEL83_SDIF_CMD      = 2,     /*!< SDIF_CMD : SD1/SD4/MMC Command pin                                        */
59606   GPIO_PINCFG83_FNCSEL83_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59607   GPIO_PINCFG83_FNCSEL83_SWTRACE3      = 4,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
59608   GPIO_PINCFG83_FNCSEL83_DISP_SD       = 5,     /*!< DISP_SD : Display RGB Shutdown                                            */
59609   GPIO_PINCFG83_FNCSEL83_CT83          = 6,     /*!< CT83 : Timer/Counter input or output; Selection of direction
59610                                                      is done via CTIMER register settings.                                     */
59611   GPIO_PINCFG83_FNCSEL83_NCE83         = 7,     /*!< NCE83 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59612                                                      CE_POLARITY field                                                         */
59613   GPIO_PINCFG83_FNCSEL83_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
59614   GPIO_PINCFG83_FNCSEL83_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59615   GPIO_PINCFG83_FNCSEL83_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59616   GPIO_PINCFG83_FNCSEL83_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59617   GPIO_PINCFG83_FNCSEL83_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59618   GPIO_PINCFG83_FNCSEL83_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59619   GPIO_PINCFG83_FNCSEL83_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59620   GPIO_PINCFG83_FNCSEL83_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59621 } GPIO_PINCFG83_FNCSEL83_Enum;
59622 
59623 /* =======================================================  PINCFG84  ======================================================== */
59624 /* ============================================  GPIO PINCFG84 NCEPOL84 [22..22]  ============================================ */
59625 typedef enum {                                  /*!< GPIO_PINCFG84_NCEPOL84                                                    */
59626   GPIO_PINCFG84_NCEPOL84_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59627   GPIO_PINCFG84_NCEPOL84_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59628 } GPIO_PINCFG84_NCEPOL84_Enum;
59629 
59630 /* ============================================  GPIO PINCFG84 NCESRC84 [16..21]  ============================================ */
59631 typedef enum {                                  /*!< GPIO_PINCFG84_NCESRC84                                                    */
59632   GPIO_PINCFG84_NCESRC84_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59633   GPIO_PINCFG84_NCESRC84_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59634   GPIO_PINCFG84_NCESRC84_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59635   GPIO_PINCFG84_NCESRC84_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59636   GPIO_PINCFG84_NCESRC84_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59637   GPIO_PINCFG84_NCESRC84_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59638   GPIO_PINCFG84_NCESRC84_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59639   GPIO_PINCFG84_NCESRC84_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59640   GPIO_PINCFG84_NCESRC84_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59641   GPIO_PINCFG84_NCESRC84_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59642   GPIO_PINCFG84_NCESRC84_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59643   GPIO_PINCFG84_NCESRC84_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59644   GPIO_PINCFG84_NCESRC84_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59645   GPIO_PINCFG84_NCESRC84_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59646   GPIO_PINCFG84_NCESRC84_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59647   GPIO_PINCFG84_NCESRC84_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59648   GPIO_PINCFG84_NCESRC84_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59649   GPIO_PINCFG84_NCESRC84_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59650   GPIO_PINCFG84_NCESRC84_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59651   GPIO_PINCFG84_NCESRC84_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59652   GPIO_PINCFG84_NCESRC84_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59653   GPIO_PINCFG84_NCESRC84_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59654   GPIO_PINCFG84_NCESRC84_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59655   GPIO_PINCFG84_NCESRC84_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59656   GPIO_PINCFG84_NCESRC84_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59657   GPIO_PINCFG84_NCESRC84_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59658   GPIO_PINCFG84_NCESRC84_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59659   GPIO_PINCFG84_NCESRC84_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59660   GPIO_PINCFG84_NCESRC84_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59661   GPIO_PINCFG84_NCESRC84_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59662   GPIO_PINCFG84_NCESRC84_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59663   GPIO_PINCFG84_NCESRC84_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59664   GPIO_PINCFG84_NCESRC84_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59665   GPIO_PINCFG84_NCESRC84_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59666   GPIO_PINCFG84_NCESRC84_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59667   GPIO_PINCFG84_NCESRC84_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59668   GPIO_PINCFG84_NCESRC84_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59669   GPIO_PINCFG84_NCESRC84_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59670   GPIO_PINCFG84_NCESRC84_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59671   GPIO_PINCFG84_NCESRC84_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59672   GPIO_PINCFG84_NCESRC84_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59673   GPIO_PINCFG84_NCESRC84_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59674   GPIO_PINCFG84_NCESRC84_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59675 } GPIO_PINCFG84_NCESRC84_Enum;
59676 
59677 /* ===========================================  GPIO PINCFG84 PULLCFG84 [13..15]  ============================================ */
59678 typedef enum {                                  /*!< GPIO_PINCFG84_PULLCFG84                                                   */
59679   GPIO_PINCFG84_PULLCFG84_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59680   GPIO_PINCFG84_PULLCFG84_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59681   GPIO_PINCFG84_PULLCFG84_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59682   GPIO_PINCFG84_PULLCFG84_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59683   GPIO_PINCFG84_PULLCFG84_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59684   GPIO_PINCFG84_PULLCFG84_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59685   GPIO_PINCFG84_PULLCFG84_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59686   GPIO_PINCFG84_PULLCFG84_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59687 } GPIO_PINCFG84_PULLCFG84_Enum;
59688 
59689 /* ==============================================  GPIO PINCFG84 DS84 [10..11]  ============================================== */
59690 typedef enum {                                  /*!< GPIO_PINCFG84_DS84                                                        */
59691   GPIO_PINCFG84_DS84_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59692   GPIO_PINCFG84_DS84_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59693   GPIO_PINCFG84_DS84_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59694   GPIO_PINCFG84_DS84_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59695 } GPIO_PINCFG84_DS84_Enum;
59696 
59697 /* =============================================  GPIO PINCFG84 OUTCFG84 [8..9]  ============================================= */
59698 typedef enum {                                  /*!< GPIO_PINCFG84_OUTCFG84                                                    */
59699   GPIO_PINCFG84_OUTCFG84_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59700   GPIO_PINCFG84_OUTCFG84_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59701                                                      and 1 values on pin.                                                      */
59702   GPIO_PINCFG84_OUTCFG84_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59703                                                      low, tristate otherwise.                                                  */
59704   GPIO_PINCFG84_OUTCFG84_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59705                                                      drive 0, 1 of HiZ on pin.                                                 */
59706 } GPIO_PINCFG84_OUTCFG84_Enum;
59707 
59708 /* =============================================  GPIO PINCFG84 IRPTEN84 [6..7]  ============================================= */
59709 typedef enum {                                  /*!< GPIO_PINCFG84_IRPTEN84                                                    */
59710   GPIO_PINCFG84_IRPTEN84_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59711   GPIO_PINCFG84_IRPTEN84_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59712                                                      on this GPIO                                                              */
59713   GPIO_PINCFG84_IRPTEN84_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59714                                                      on this GPIO                                                              */
59715   GPIO_PINCFG84_IRPTEN84_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59716                                                      GPIO                                                                      */
59717 } GPIO_PINCFG84_IRPTEN84_Enum;
59718 
59719 /* =============================================  GPIO PINCFG84 FNCSEL84 [0..3]  ============================================= */
59720 typedef enum {                                  /*!< GPIO_PINCFG84_FNCSEL84                                                    */
59721   GPIO_PINCFG84_FNCSEL84_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
59722   GPIO_PINCFG84_FNCSEL84_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
59723   GPIO_PINCFG84_FNCSEL84_SDIF_DAT0     = 2,     /*!< SDIF_DAT0 : SD/SDIO/MMC Data0 pin                                         */
59724   GPIO_PINCFG84_FNCSEL84_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59725   GPIO_PINCFG84_FNCSEL84_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
59726   GPIO_PINCFG84_FNCSEL84_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
59727   GPIO_PINCFG84_FNCSEL84_CT84          = 6,     /*!< CT84 : Timer/Counter input or output; Selection of direction
59728                                                      is done via CTIMER register settings.                                     */
59729   GPIO_PINCFG84_FNCSEL84_NCE84         = 7,     /*!< NCE84 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59730                                                      CE_POLARITY field                                                         */
59731   GPIO_PINCFG84_FNCSEL84_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
59732   GPIO_PINCFG84_FNCSEL84_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59733   GPIO_PINCFG84_FNCSEL84_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59734   GPIO_PINCFG84_FNCSEL84_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59735   GPIO_PINCFG84_FNCSEL84_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59736   GPIO_PINCFG84_FNCSEL84_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59737   GPIO_PINCFG84_FNCSEL84_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59738   GPIO_PINCFG84_FNCSEL84_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59739 } GPIO_PINCFG84_FNCSEL84_Enum;
59740 
59741 /* =======================================================  PINCFG85  ======================================================== */
59742 /* ============================================  GPIO PINCFG85 NCEPOL85 [22..22]  ============================================ */
59743 typedef enum {                                  /*!< GPIO_PINCFG85_NCEPOL85                                                    */
59744   GPIO_PINCFG85_NCEPOL85_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59745   GPIO_PINCFG85_NCEPOL85_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59746 } GPIO_PINCFG85_NCEPOL85_Enum;
59747 
59748 /* ============================================  GPIO PINCFG85 NCESRC85 [16..21]  ============================================ */
59749 typedef enum {                                  /*!< GPIO_PINCFG85_NCESRC85                                                    */
59750   GPIO_PINCFG85_NCESRC85_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59751   GPIO_PINCFG85_NCESRC85_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59752   GPIO_PINCFG85_NCESRC85_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59753   GPIO_PINCFG85_NCESRC85_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59754   GPIO_PINCFG85_NCESRC85_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59755   GPIO_PINCFG85_NCESRC85_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59756   GPIO_PINCFG85_NCESRC85_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59757   GPIO_PINCFG85_NCESRC85_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59758   GPIO_PINCFG85_NCESRC85_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59759   GPIO_PINCFG85_NCESRC85_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59760   GPIO_PINCFG85_NCESRC85_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59761   GPIO_PINCFG85_NCESRC85_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59762   GPIO_PINCFG85_NCESRC85_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59763   GPIO_PINCFG85_NCESRC85_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59764   GPIO_PINCFG85_NCESRC85_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59765   GPIO_PINCFG85_NCESRC85_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59766   GPIO_PINCFG85_NCESRC85_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59767   GPIO_PINCFG85_NCESRC85_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59768   GPIO_PINCFG85_NCESRC85_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59769   GPIO_PINCFG85_NCESRC85_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59770   GPIO_PINCFG85_NCESRC85_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59771   GPIO_PINCFG85_NCESRC85_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59772   GPIO_PINCFG85_NCESRC85_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59773   GPIO_PINCFG85_NCESRC85_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59774   GPIO_PINCFG85_NCESRC85_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59775   GPIO_PINCFG85_NCESRC85_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59776   GPIO_PINCFG85_NCESRC85_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59777   GPIO_PINCFG85_NCESRC85_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59778   GPIO_PINCFG85_NCESRC85_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59779   GPIO_PINCFG85_NCESRC85_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59780   GPIO_PINCFG85_NCESRC85_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59781   GPIO_PINCFG85_NCESRC85_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59782   GPIO_PINCFG85_NCESRC85_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59783   GPIO_PINCFG85_NCESRC85_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59784   GPIO_PINCFG85_NCESRC85_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59785   GPIO_PINCFG85_NCESRC85_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59786   GPIO_PINCFG85_NCESRC85_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59787   GPIO_PINCFG85_NCESRC85_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59788   GPIO_PINCFG85_NCESRC85_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59789   GPIO_PINCFG85_NCESRC85_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59790   GPIO_PINCFG85_NCESRC85_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59791   GPIO_PINCFG85_NCESRC85_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59792   GPIO_PINCFG85_NCESRC85_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59793 } GPIO_PINCFG85_NCESRC85_Enum;
59794 
59795 /* ===========================================  GPIO PINCFG85 PULLCFG85 [13..15]  ============================================ */
59796 typedef enum {                                  /*!< GPIO_PINCFG85_PULLCFG85                                                   */
59797   GPIO_PINCFG85_PULLCFG85_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59798   GPIO_PINCFG85_PULLCFG85_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59799   GPIO_PINCFG85_PULLCFG85_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59800   GPIO_PINCFG85_PULLCFG85_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59801   GPIO_PINCFG85_PULLCFG85_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59802   GPIO_PINCFG85_PULLCFG85_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59803   GPIO_PINCFG85_PULLCFG85_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59804   GPIO_PINCFG85_PULLCFG85_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59805 } GPIO_PINCFG85_PULLCFG85_Enum;
59806 
59807 /* ==============================================  GPIO PINCFG85 DS85 [10..11]  ============================================== */
59808 typedef enum {                                  /*!< GPIO_PINCFG85_DS85                                                        */
59809   GPIO_PINCFG85_DS85_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59810   GPIO_PINCFG85_DS85_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59811   GPIO_PINCFG85_DS85_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59812   GPIO_PINCFG85_DS85_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59813 } GPIO_PINCFG85_DS85_Enum;
59814 
59815 /* =============================================  GPIO PINCFG85 OUTCFG85 [8..9]  ============================================= */
59816 typedef enum {                                  /*!< GPIO_PINCFG85_OUTCFG85                                                    */
59817   GPIO_PINCFG85_OUTCFG85_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59818   GPIO_PINCFG85_OUTCFG85_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59819                                                      and 1 values on pin.                                                      */
59820   GPIO_PINCFG85_OUTCFG85_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59821                                                      low, tristate otherwise.                                                  */
59822   GPIO_PINCFG85_OUTCFG85_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59823                                                      drive 0, 1 of HiZ on pin.                                                 */
59824 } GPIO_PINCFG85_OUTCFG85_Enum;
59825 
59826 /* =============================================  GPIO PINCFG85 IRPTEN85 [6..7]  ============================================= */
59827 typedef enum {                                  /*!< GPIO_PINCFG85_IRPTEN85                                                    */
59828   GPIO_PINCFG85_IRPTEN85_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59829   GPIO_PINCFG85_IRPTEN85_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59830                                                      on this GPIO                                                              */
59831   GPIO_PINCFG85_IRPTEN85_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59832                                                      on this GPIO                                                              */
59833   GPIO_PINCFG85_IRPTEN85_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59834                                                      GPIO                                                                      */
59835 } GPIO_PINCFG85_IRPTEN85_Enum;
59836 
59837 /* =============================================  GPIO PINCFG85 FNCSEL85 [0..3]  ============================================= */
59838 typedef enum {                                  /*!< GPIO_PINCFG85_FNCSEL85                                                    */
59839   GPIO_PINCFG85_FNCSEL85_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
59840   GPIO_PINCFG85_FNCSEL85_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
59841   GPIO_PINCFG85_FNCSEL85_SDIF_DAT1     = 2,     /*!< SDIF_DAT1 : SD/SDIO/MMC Data1 pin                                         */
59842   GPIO_PINCFG85_FNCSEL85_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59843   GPIO_PINCFG85_FNCSEL85_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
59844   GPIO_PINCFG85_FNCSEL85_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
59845   GPIO_PINCFG85_FNCSEL85_CT85          = 6,     /*!< CT85 : Timer/Counter input or output; Selection of direction
59846                                                      is done via CTIMER register settings.                                     */
59847   GPIO_PINCFG85_FNCSEL85_NCE85         = 7,     /*!< NCE85 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59848                                                      CE_POLARITY field                                                         */
59849   GPIO_PINCFG85_FNCSEL85_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
59850   GPIO_PINCFG85_FNCSEL85_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59851   GPIO_PINCFG85_FNCSEL85_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59852   GPIO_PINCFG85_FNCSEL85_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59853   GPIO_PINCFG85_FNCSEL85_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59854   GPIO_PINCFG85_FNCSEL85_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59855   GPIO_PINCFG85_FNCSEL85_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59856   GPIO_PINCFG85_FNCSEL85_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59857 } GPIO_PINCFG85_FNCSEL85_Enum;
59858 
59859 /* =======================================================  PINCFG86  ======================================================== */
59860 /* ============================================  GPIO PINCFG86 NCEPOL86 [22..22]  ============================================ */
59861 typedef enum {                                  /*!< GPIO_PINCFG86_NCEPOL86                                                    */
59862   GPIO_PINCFG86_NCEPOL86_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59863   GPIO_PINCFG86_NCEPOL86_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59864 } GPIO_PINCFG86_NCEPOL86_Enum;
59865 
59866 /* ============================================  GPIO PINCFG86 NCESRC86 [16..21]  ============================================ */
59867 typedef enum {                                  /*!< GPIO_PINCFG86_NCESRC86                                                    */
59868   GPIO_PINCFG86_NCESRC86_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59869   GPIO_PINCFG86_NCESRC86_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59870   GPIO_PINCFG86_NCESRC86_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59871   GPIO_PINCFG86_NCESRC86_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59872   GPIO_PINCFG86_NCESRC86_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59873   GPIO_PINCFG86_NCESRC86_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59874   GPIO_PINCFG86_NCESRC86_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59875   GPIO_PINCFG86_NCESRC86_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59876   GPIO_PINCFG86_NCESRC86_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59877   GPIO_PINCFG86_NCESRC86_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59878   GPIO_PINCFG86_NCESRC86_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59879   GPIO_PINCFG86_NCESRC86_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59880   GPIO_PINCFG86_NCESRC86_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59881   GPIO_PINCFG86_NCESRC86_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59882   GPIO_PINCFG86_NCESRC86_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59883   GPIO_PINCFG86_NCESRC86_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59884   GPIO_PINCFG86_NCESRC86_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59885   GPIO_PINCFG86_NCESRC86_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59886   GPIO_PINCFG86_NCESRC86_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59887   GPIO_PINCFG86_NCESRC86_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59888   GPIO_PINCFG86_NCESRC86_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59889   GPIO_PINCFG86_NCESRC86_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59890   GPIO_PINCFG86_NCESRC86_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59891   GPIO_PINCFG86_NCESRC86_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59892   GPIO_PINCFG86_NCESRC86_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59893   GPIO_PINCFG86_NCESRC86_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59894   GPIO_PINCFG86_NCESRC86_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59895   GPIO_PINCFG86_NCESRC86_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59896   GPIO_PINCFG86_NCESRC86_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59897   GPIO_PINCFG86_NCESRC86_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59898   GPIO_PINCFG86_NCESRC86_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59899   GPIO_PINCFG86_NCESRC86_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59900   GPIO_PINCFG86_NCESRC86_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59901   GPIO_PINCFG86_NCESRC86_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59902   GPIO_PINCFG86_NCESRC86_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59903   GPIO_PINCFG86_NCESRC86_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59904   GPIO_PINCFG86_NCESRC86_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59905   GPIO_PINCFG86_NCESRC86_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59906   GPIO_PINCFG86_NCESRC86_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59907   GPIO_PINCFG86_NCESRC86_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59908   GPIO_PINCFG86_NCESRC86_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59909   GPIO_PINCFG86_NCESRC86_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59910   GPIO_PINCFG86_NCESRC86_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59911 } GPIO_PINCFG86_NCESRC86_Enum;
59912 
59913 /* ===========================================  GPIO PINCFG86 PULLCFG86 [13..15]  ============================================ */
59914 typedef enum {                                  /*!< GPIO_PINCFG86_PULLCFG86                                                   */
59915   GPIO_PINCFG86_PULLCFG86_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59916   GPIO_PINCFG86_PULLCFG86_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59917   GPIO_PINCFG86_PULLCFG86_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59918   GPIO_PINCFG86_PULLCFG86_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59919   GPIO_PINCFG86_PULLCFG86_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59920   GPIO_PINCFG86_PULLCFG86_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59921   GPIO_PINCFG86_PULLCFG86_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59922   GPIO_PINCFG86_PULLCFG86_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59923 } GPIO_PINCFG86_PULLCFG86_Enum;
59924 
59925 /* ==============================================  GPIO PINCFG86 DS86 [10..11]  ============================================== */
59926 typedef enum {                                  /*!< GPIO_PINCFG86_DS86                                                        */
59927   GPIO_PINCFG86_DS86_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59928   GPIO_PINCFG86_DS86_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59929   GPIO_PINCFG86_DS86_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59930   GPIO_PINCFG86_DS86_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59931 } GPIO_PINCFG86_DS86_Enum;
59932 
59933 /* =============================================  GPIO PINCFG86 OUTCFG86 [8..9]  ============================================= */
59934 typedef enum {                                  /*!< GPIO_PINCFG86_OUTCFG86                                                    */
59935   GPIO_PINCFG86_OUTCFG86_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59936   GPIO_PINCFG86_OUTCFG86_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59937                                                      and 1 values on pin.                                                      */
59938   GPIO_PINCFG86_OUTCFG86_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59939                                                      low, tristate otherwise.                                                  */
59940   GPIO_PINCFG86_OUTCFG86_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59941                                                      drive 0, 1 of HiZ on pin.                                                 */
59942 } GPIO_PINCFG86_OUTCFG86_Enum;
59943 
59944 /* =============================================  GPIO PINCFG86 IRPTEN86 [6..7]  ============================================= */
59945 typedef enum {                                  /*!< GPIO_PINCFG86_IRPTEN86                                                    */
59946   GPIO_PINCFG86_IRPTEN86_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59947   GPIO_PINCFG86_IRPTEN86_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59948                                                      on this GPIO                                                              */
59949   GPIO_PINCFG86_IRPTEN86_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59950                                                      on this GPIO                                                              */
59951   GPIO_PINCFG86_IRPTEN86_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59952                                                      GPIO                                                                      */
59953 } GPIO_PINCFG86_IRPTEN86_Enum;
59954 
59955 /* =============================================  GPIO PINCFG86 FNCSEL86 [0..3]  ============================================= */
59956 typedef enum {                                  /*!< GPIO_PINCFG86_FNCSEL86                                                    */
59957   GPIO_PINCFG86_FNCSEL86_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
59958   GPIO_PINCFG86_FNCSEL86_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
59959   GPIO_PINCFG86_FNCSEL86_SDIF_DAT2     = 2,     /*!< SDIF_DAT2 : SD/SDIO/MMC Data2 pin                                         */
59960   GPIO_PINCFG86_FNCSEL86_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59961   GPIO_PINCFG86_FNCSEL86_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
59962   GPIO_PINCFG86_FNCSEL86_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
59963   GPIO_PINCFG86_FNCSEL86_CT86          = 6,     /*!< CT86 : Timer/Counter input or output; Selection of direction
59964                                                      is done via CTIMER register settings.                                     */
59965   GPIO_PINCFG86_FNCSEL86_NCE86         = 7,     /*!< NCE86 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59966                                                      CE_POLARITY field                                                         */
59967   GPIO_PINCFG86_FNCSEL86_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
59968   GPIO_PINCFG86_FNCSEL86_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59969   GPIO_PINCFG86_FNCSEL86_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59970   GPIO_PINCFG86_FNCSEL86_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59971   GPIO_PINCFG86_FNCSEL86_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59972   GPIO_PINCFG86_FNCSEL86_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59973   GPIO_PINCFG86_FNCSEL86_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59974   GPIO_PINCFG86_FNCSEL86_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59975 } GPIO_PINCFG86_FNCSEL86_Enum;
59976 
59977 /* =======================================================  PINCFG87  ======================================================== */
59978 /* ============================================  GPIO PINCFG87 NCEPOL87 [22..22]  ============================================ */
59979 typedef enum {                                  /*!< GPIO_PINCFG87_NCEPOL87                                                    */
59980   GPIO_PINCFG87_NCEPOL87_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59981   GPIO_PINCFG87_NCEPOL87_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59982 } GPIO_PINCFG87_NCEPOL87_Enum;
59983 
59984 /* ============================================  GPIO PINCFG87 NCESRC87 [16..21]  ============================================ */
59985 typedef enum {                                  /*!< GPIO_PINCFG87_NCESRC87                                                    */
59986   GPIO_PINCFG87_NCESRC87_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59987   GPIO_PINCFG87_NCESRC87_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59988   GPIO_PINCFG87_NCESRC87_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59989   GPIO_PINCFG87_NCESRC87_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59990   GPIO_PINCFG87_NCESRC87_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59991   GPIO_PINCFG87_NCESRC87_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59992   GPIO_PINCFG87_NCESRC87_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59993   GPIO_PINCFG87_NCESRC87_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59994   GPIO_PINCFG87_NCESRC87_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59995   GPIO_PINCFG87_NCESRC87_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59996   GPIO_PINCFG87_NCESRC87_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59997   GPIO_PINCFG87_NCESRC87_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59998   GPIO_PINCFG87_NCESRC87_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59999   GPIO_PINCFG87_NCESRC87_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60000   GPIO_PINCFG87_NCESRC87_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60001   GPIO_PINCFG87_NCESRC87_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60002   GPIO_PINCFG87_NCESRC87_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60003   GPIO_PINCFG87_NCESRC87_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60004   GPIO_PINCFG87_NCESRC87_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60005   GPIO_PINCFG87_NCESRC87_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60006   GPIO_PINCFG87_NCESRC87_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60007   GPIO_PINCFG87_NCESRC87_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60008   GPIO_PINCFG87_NCESRC87_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60009   GPIO_PINCFG87_NCESRC87_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60010   GPIO_PINCFG87_NCESRC87_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60011   GPIO_PINCFG87_NCESRC87_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60012   GPIO_PINCFG87_NCESRC87_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60013   GPIO_PINCFG87_NCESRC87_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60014   GPIO_PINCFG87_NCESRC87_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60015   GPIO_PINCFG87_NCESRC87_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60016   GPIO_PINCFG87_NCESRC87_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60017   GPIO_PINCFG87_NCESRC87_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60018   GPIO_PINCFG87_NCESRC87_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60019   GPIO_PINCFG87_NCESRC87_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60020   GPIO_PINCFG87_NCESRC87_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60021   GPIO_PINCFG87_NCESRC87_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60022   GPIO_PINCFG87_NCESRC87_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60023   GPIO_PINCFG87_NCESRC87_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60024   GPIO_PINCFG87_NCESRC87_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60025   GPIO_PINCFG87_NCESRC87_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60026   GPIO_PINCFG87_NCESRC87_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60027   GPIO_PINCFG87_NCESRC87_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60028   GPIO_PINCFG87_NCESRC87_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60029 } GPIO_PINCFG87_NCESRC87_Enum;
60030 
60031 /* ===========================================  GPIO PINCFG87 PULLCFG87 [13..15]  ============================================ */
60032 typedef enum {                                  /*!< GPIO_PINCFG87_PULLCFG87                                                   */
60033   GPIO_PINCFG87_PULLCFG87_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60034   GPIO_PINCFG87_PULLCFG87_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60035   GPIO_PINCFG87_PULLCFG87_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60036   GPIO_PINCFG87_PULLCFG87_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60037   GPIO_PINCFG87_PULLCFG87_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60038   GPIO_PINCFG87_PULLCFG87_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60039   GPIO_PINCFG87_PULLCFG87_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60040   GPIO_PINCFG87_PULLCFG87_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60041 } GPIO_PINCFG87_PULLCFG87_Enum;
60042 
60043 /* ==============================================  GPIO PINCFG87 DS87 [10..11]  ============================================== */
60044 typedef enum {                                  /*!< GPIO_PINCFG87_DS87                                                        */
60045   GPIO_PINCFG87_DS87_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60046   GPIO_PINCFG87_DS87_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60047   GPIO_PINCFG87_DS87_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60048   GPIO_PINCFG87_DS87_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60049 } GPIO_PINCFG87_DS87_Enum;
60050 
60051 /* =============================================  GPIO PINCFG87 OUTCFG87 [8..9]  ============================================= */
60052 typedef enum {                                  /*!< GPIO_PINCFG87_OUTCFG87                                                    */
60053   GPIO_PINCFG87_OUTCFG87_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60054   GPIO_PINCFG87_OUTCFG87_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60055                                                      and 1 values on pin.                                                      */
60056   GPIO_PINCFG87_OUTCFG87_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60057                                                      low, tristate otherwise.                                                  */
60058   GPIO_PINCFG87_OUTCFG87_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60059                                                      drive 0, 1 of HiZ on pin.                                                 */
60060 } GPIO_PINCFG87_OUTCFG87_Enum;
60061 
60062 /* =============================================  GPIO PINCFG87 IRPTEN87 [6..7]  ============================================= */
60063 typedef enum {                                  /*!< GPIO_PINCFG87_IRPTEN87                                                    */
60064   GPIO_PINCFG87_IRPTEN87_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60065   GPIO_PINCFG87_IRPTEN87_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60066                                                      on this GPIO                                                              */
60067   GPIO_PINCFG87_IRPTEN87_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60068                                                      on this GPIO                                                              */
60069   GPIO_PINCFG87_IRPTEN87_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60070                                                      GPIO                                                                      */
60071 } GPIO_PINCFG87_IRPTEN87_Enum;
60072 
60073 /* =============================================  GPIO PINCFG87 FNCSEL87 [0..3]  ============================================= */
60074 typedef enum {                                  /*!< GPIO_PINCFG87_FNCSEL87                                                    */
60075   GPIO_PINCFG87_FNCSEL87_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60076   GPIO_PINCFG87_FNCSEL87_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60077   GPIO_PINCFG87_FNCSEL87_SDIF_DAT3     = 2,     /*!< SDIF_DAT3 : SD/SDIO/MMC Data3 pin                                         */
60078   GPIO_PINCFG87_FNCSEL87_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60079   GPIO_PINCFG87_FNCSEL87_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60080   GPIO_PINCFG87_FNCSEL87_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60081   GPIO_PINCFG87_FNCSEL87_CT87          = 6,     /*!< CT87 : Timer/Counter input or output; Selection of direction
60082                                                      is done via CTIMER register settings.                                     */
60083   GPIO_PINCFG87_FNCSEL87_NCE87         = 7,     /*!< NCE87 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60084                                                      CE_POLARITY field                                                         */
60085   GPIO_PINCFG87_FNCSEL87_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
60086   GPIO_PINCFG87_FNCSEL87_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
60087   GPIO_PINCFG87_FNCSEL87_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60088   GPIO_PINCFG87_FNCSEL87_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60089   GPIO_PINCFG87_FNCSEL87_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60090   GPIO_PINCFG87_FNCSEL87_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60091   GPIO_PINCFG87_FNCSEL87_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60092   GPIO_PINCFG87_FNCSEL87_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60093 } GPIO_PINCFG87_FNCSEL87_Enum;
60094 
60095 /* =======================================================  PINCFG88  ======================================================== */
60096 /* ============================================  GPIO PINCFG88 NCEPOL88 [22..22]  ============================================ */
60097 typedef enum {                                  /*!< GPIO_PINCFG88_NCEPOL88                                                    */
60098   GPIO_PINCFG88_NCEPOL88_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60099   GPIO_PINCFG88_NCEPOL88_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60100 } GPIO_PINCFG88_NCEPOL88_Enum;
60101 
60102 /* ============================================  GPIO PINCFG88 NCESRC88 [16..21]  ============================================ */
60103 typedef enum {                                  /*!< GPIO_PINCFG88_NCESRC88                                                    */
60104   GPIO_PINCFG88_NCESRC88_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60105   GPIO_PINCFG88_NCESRC88_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60106   GPIO_PINCFG88_NCESRC88_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60107   GPIO_PINCFG88_NCESRC88_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60108   GPIO_PINCFG88_NCESRC88_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60109   GPIO_PINCFG88_NCESRC88_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60110   GPIO_PINCFG88_NCESRC88_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60111   GPIO_PINCFG88_NCESRC88_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60112   GPIO_PINCFG88_NCESRC88_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60113   GPIO_PINCFG88_NCESRC88_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60114   GPIO_PINCFG88_NCESRC88_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60115   GPIO_PINCFG88_NCESRC88_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60116   GPIO_PINCFG88_NCESRC88_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60117   GPIO_PINCFG88_NCESRC88_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60118   GPIO_PINCFG88_NCESRC88_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60119   GPIO_PINCFG88_NCESRC88_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60120   GPIO_PINCFG88_NCESRC88_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60121   GPIO_PINCFG88_NCESRC88_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60122   GPIO_PINCFG88_NCESRC88_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60123   GPIO_PINCFG88_NCESRC88_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60124   GPIO_PINCFG88_NCESRC88_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60125   GPIO_PINCFG88_NCESRC88_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60126   GPIO_PINCFG88_NCESRC88_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60127   GPIO_PINCFG88_NCESRC88_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60128   GPIO_PINCFG88_NCESRC88_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60129   GPIO_PINCFG88_NCESRC88_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60130   GPIO_PINCFG88_NCESRC88_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60131   GPIO_PINCFG88_NCESRC88_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60132   GPIO_PINCFG88_NCESRC88_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60133   GPIO_PINCFG88_NCESRC88_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60134   GPIO_PINCFG88_NCESRC88_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60135   GPIO_PINCFG88_NCESRC88_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60136   GPIO_PINCFG88_NCESRC88_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60137   GPIO_PINCFG88_NCESRC88_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60138   GPIO_PINCFG88_NCESRC88_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60139   GPIO_PINCFG88_NCESRC88_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60140   GPIO_PINCFG88_NCESRC88_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60141   GPIO_PINCFG88_NCESRC88_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60142   GPIO_PINCFG88_NCESRC88_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60143   GPIO_PINCFG88_NCESRC88_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60144   GPIO_PINCFG88_NCESRC88_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60145   GPIO_PINCFG88_NCESRC88_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60146   GPIO_PINCFG88_NCESRC88_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60147 } GPIO_PINCFG88_NCESRC88_Enum;
60148 
60149 /* ===========================================  GPIO PINCFG88 PULLCFG88 [13..15]  ============================================ */
60150 typedef enum {                                  /*!< GPIO_PINCFG88_PULLCFG88                                                   */
60151   GPIO_PINCFG88_PULLCFG88_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60152   GPIO_PINCFG88_PULLCFG88_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60153   GPIO_PINCFG88_PULLCFG88_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60154   GPIO_PINCFG88_PULLCFG88_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60155   GPIO_PINCFG88_PULLCFG88_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60156   GPIO_PINCFG88_PULLCFG88_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60157   GPIO_PINCFG88_PULLCFG88_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60158   GPIO_PINCFG88_PULLCFG88_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60159 } GPIO_PINCFG88_PULLCFG88_Enum;
60160 
60161 /* ==============================================  GPIO PINCFG88 DS88 [10..11]  ============================================== */
60162 typedef enum {                                  /*!< GPIO_PINCFG88_DS88                                                        */
60163   GPIO_PINCFG88_DS88_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60164   GPIO_PINCFG88_DS88_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60165   GPIO_PINCFG88_DS88_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60166   GPIO_PINCFG88_DS88_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60167 } GPIO_PINCFG88_DS88_Enum;
60168 
60169 /* =============================================  GPIO PINCFG88 OUTCFG88 [8..9]  ============================================= */
60170 typedef enum {                                  /*!< GPIO_PINCFG88_OUTCFG88                                                    */
60171   GPIO_PINCFG88_OUTCFG88_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60172   GPIO_PINCFG88_OUTCFG88_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60173                                                      and 1 values on pin.                                                      */
60174   GPIO_PINCFG88_OUTCFG88_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60175                                                      low, tristate otherwise.                                                  */
60176   GPIO_PINCFG88_OUTCFG88_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60177                                                      drive 0, 1 of HiZ on pin.                                                 */
60178 } GPIO_PINCFG88_OUTCFG88_Enum;
60179 
60180 /* =============================================  GPIO PINCFG88 IRPTEN88 [6..7]  ============================================= */
60181 typedef enum {                                  /*!< GPIO_PINCFG88_IRPTEN88                                                    */
60182   GPIO_PINCFG88_IRPTEN88_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60183   GPIO_PINCFG88_IRPTEN88_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60184                                                      on this GPIO                                                              */
60185   GPIO_PINCFG88_IRPTEN88_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60186                                                      on this GPIO                                                              */
60187   GPIO_PINCFG88_IRPTEN88_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60188                                                      GPIO                                                                      */
60189 } GPIO_PINCFG88_IRPTEN88_Enum;
60190 
60191 /* =============================================  GPIO PINCFG88 FNCSEL88 [0..3]  ============================================= */
60192 typedef enum {                                  /*!< GPIO_PINCFG88_FNCSEL88                                                    */
60193   GPIO_PINCFG88_FNCSEL88_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60194   GPIO_PINCFG88_FNCSEL88_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60195   GPIO_PINCFG88_FNCSEL88_SDIF_CLKOUT   = 2,     /*!< SDIF_CLKOUT : SD/SDIO/MMC Clock to Card (CLK)                             */
60196   GPIO_PINCFG88_FNCSEL88_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60197   GPIO_PINCFG88_FNCSEL88_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60198   GPIO_PINCFG88_FNCSEL88_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60199   GPIO_PINCFG88_FNCSEL88_CT88          = 6,     /*!< CT88 : Timer/Counter input or output; Selection of direction
60200                                                      is done via CTIMER register settings.                                     */
60201   GPIO_PINCFG88_FNCSEL88_NCE88         = 7,     /*!< NCE88 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60202                                                      CE_POLARITY field                                                         */
60203   GPIO_PINCFG88_FNCSEL88_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
60204   GPIO_PINCFG88_FNCSEL88_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60205   GPIO_PINCFG88_FNCSEL88_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60206   GPIO_PINCFG88_FNCSEL88_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60207   GPIO_PINCFG88_FNCSEL88_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60208   GPIO_PINCFG88_FNCSEL88_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60209   GPIO_PINCFG88_FNCSEL88_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60210   GPIO_PINCFG88_FNCSEL88_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60211 } GPIO_PINCFG88_FNCSEL88_Enum;
60212 
60213 /* =======================================================  PINCFG89  ======================================================== */
60214 /* ============================================  GPIO PINCFG89 NCEPOL89 [22..22]  ============================================ */
60215 typedef enum {                                  /*!< GPIO_PINCFG89_NCEPOL89                                                    */
60216   GPIO_PINCFG89_NCEPOL89_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60217   GPIO_PINCFG89_NCEPOL89_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60218 } GPIO_PINCFG89_NCEPOL89_Enum;
60219 
60220 /* ============================================  GPIO PINCFG89 NCESRC89 [16..21]  ============================================ */
60221 typedef enum {                                  /*!< GPIO_PINCFG89_NCESRC89                                                    */
60222   GPIO_PINCFG89_NCESRC89_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60223   GPIO_PINCFG89_NCESRC89_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60224   GPIO_PINCFG89_NCESRC89_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60225   GPIO_PINCFG89_NCESRC89_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60226   GPIO_PINCFG89_NCESRC89_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60227   GPIO_PINCFG89_NCESRC89_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60228   GPIO_PINCFG89_NCESRC89_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60229   GPIO_PINCFG89_NCESRC89_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60230   GPIO_PINCFG89_NCESRC89_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60231   GPIO_PINCFG89_NCESRC89_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60232   GPIO_PINCFG89_NCESRC89_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60233   GPIO_PINCFG89_NCESRC89_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60234   GPIO_PINCFG89_NCESRC89_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60235   GPIO_PINCFG89_NCESRC89_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60236   GPIO_PINCFG89_NCESRC89_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60237   GPIO_PINCFG89_NCESRC89_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60238   GPIO_PINCFG89_NCESRC89_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60239   GPIO_PINCFG89_NCESRC89_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60240   GPIO_PINCFG89_NCESRC89_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60241   GPIO_PINCFG89_NCESRC89_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60242   GPIO_PINCFG89_NCESRC89_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60243   GPIO_PINCFG89_NCESRC89_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60244   GPIO_PINCFG89_NCESRC89_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60245   GPIO_PINCFG89_NCESRC89_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60246   GPIO_PINCFG89_NCESRC89_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60247   GPIO_PINCFG89_NCESRC89_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60248   GPIO_PINCFG89_NCESRC89_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60249   GPIO_PINCFG89_NCESRC89_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60250   GPIO_PINCFG89_NCESRC89_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60251   GPIO_PINCFG89_NCESRC89_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60252   GPIO_PINCFG89_NCESRC89_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60253   GPIO_PINCFG89_NCESRC89_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60254   GPIO_PINCFG89_NCESRC89_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60255   GPIO_PINCFG89_NCESRC89_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60256   GPIO_PINCFG89_NCESRC89_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60257   GPIO_PINCFG89_NCESRC89_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60258   GPIO_PINCFG89_NCESRC89_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60259   GPIO_PINCFG89_NCESRC89_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60260   GPIO_PINCFG89_NCESRC89_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60261   GPIO_PINCFG89_NCESRC89_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60262   GPIO_PINCFG89_NCESRC89_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60263   GPIO_PINCFG89_NCESRC89_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60264   GPIO_PINCFG89_NCESRC89_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60265 } GPIO_PINCFG89_NCESRC89_Enum;
60266 
60267 /* ===========================================  GPIO PINCFG89 PULLCFG89 [13..15]  ============================================ */
60268 typedef enum {                                  /*!< GPIO_PINCFG89_PULLCFG89                                                   */
60269   GPIO_PINCFG89_PULLCFG89_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60270   GPIO_PINCFG89_PULLCFG89_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60271   GPIO_PINCFG89_PULLCFG89_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60272   GPIO_PINCFG89_PULLCFG89_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60273   GPIO_PINCFG89_PULLCFG89_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60274   GPIO_PINCFG89_PULLCFG89_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60275   GPIO_PINCFG89_PULLCFG89_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60276   GPIO_PINCFG89_PULLCFG89_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60277 } GPIO_PINCFG89_PULLCFG89_Enum;
60278 
60279 /* ==============================================  GPIO PINCFG89 DS89 [10..11]  ============================================== */
60280 typedef enum {                                  /*!< GPIO_PINCFG89_DS89                                                        */
60281   GPIO_PINCFG89_DS89_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60282   GPIO_PINCFG89_DS89_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60283 } GPIO_PINCFG89_DS89_Enum;
60284 
60285 /* =============================================  GPIO PINCFG89 OUTCFG89 [8..9]  ============================================= */
60286 typedef enum {                                  /*!< GPIO_PINCFG89_OUTCFG89                                                    */
60287   GPIO_PINCFG89_OUTCFG89_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60288   GPIO_PINCFG89_OUTCFG89_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60289                                                      and 1 values on pin.                                                      */
60290   GPIO_PINCFG89_OUTCFG89_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60291                                                      low, tristate otherwise.                                                  */
60292   GPIO_PINCFG89_OUTCFG89_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60293                                                      drive 0, 1 of HiZ on pin.                                                 */
60294 } GPIO_PINCFG89_OUTCFG89_Enum;
60295 
60296 /* =============================================  GPIO PINCFG89 IRPTEN89 [6..7]  ============================================= */
60297 typedef enum {                                  /*!< GPIO_PINCFG89_IRPTEN89                                                    */
60298   GPIO_PINCFG89_IRPTEN89_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60299   GPIO_PINCFG89_IRPTEN89_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60300                                                      on this GPIO                                                              */
60301   GPIO_PINCFG89_IRPTEN89_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60302                                                      on this GPIO                                                              */
60303   GPIO_PINCFG89_IRPTEN89_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60304                                                      GPIO                                                                      */
60305 } GPIO_PINCFG89_IRPTEN89_Enum;
60306 
60307 /* =============================================  GPIO PINCFG89 FNCSEL89 [0..3]  ============================================= */
60308 typedef enum {                                  /*!< GPIO_PINCFG89_FNCSEL89                                                    */
60309   GPIO_PINCFG89_FNCSEL89_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60310   GPIO_PINCFG89_FNCSEL89_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60311   GPIO_PINCFG89_FNCSEL89_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
60312   GPIO_PINCFG89_FNCSEL89_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60313   GPIO_PINCFG89_FNCSEL89_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60314   GPIO_PINCFG89_FNCSEL89_DISP_CM       = 5,     /*!< DISP_CM : Display RGB Color Mode                                          */
60315   GPIO_PINCFG89_FNCSEL89_CT89          = 6,     /*!< CT89 : Timer/Counter input or output; Selection of direction
60316                                                      is done via CTIMER register settings.                                     */
60317   GPIO_PINCFG89_FNCSEL89_NCE89         = 7,     /*!< NCE89 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60318                                                      CE_POLARITY field                                                         */
60319   GPIO_PINCFG89_FNCSEL89_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
60320   GPIO_PINCFG89_FNCSEL89_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60321   GPIO_PINCFG89_FNCSEL89_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60322   GPIO_PINCFG89_FNCSEL89_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60323   GPIO_PINCFG89_FNCSEL89_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60324   GPIO_PINCFG89_FNCSEL89_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60325   GPIO_PINCFG89_FNCSEL89_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60326   GPIO_PINCFG89_FNCSEL89_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60327 } GPIO_PINCFG89_FNCSEL89_Enum;
60328 
60329 /* =======================================================  PINCFG90  ======================================================== */
60330 /* ============================================  GPIO PINCFG90 NCEPOL90 [22..22]  ============================================ */
60331 typedef enum {                                  /*!< GPIO_PINCFG90_NCEPOL90                                                    */
60332   GPIO_PINCFG90_NCEPOL90_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60333   GPIO_PINCFG90_NCEPOL90_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60334 } GPIO_PINCFG90_NCEPOL90_Enum;
60335 
60336 /* ============================================  GPIO PINCFG90 NCESRC90 [16..21]  ============================================ */
60337 typedef enum {                                  /*!< GPIO_PINCFG90_NCESRC90                                                    */
60338   GPIO_PINCFG90_NCESRC90_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60339   GPIO_PINCFG90_NCESRC90_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60340   GPIO_PINCFG90_NCESRC90_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60341   GPIO_PINCFG90_NCESRC90_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60342   GPIO_PINCFG90_NCESRC90_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60343   GPIO_PINCFG90_NCESRC90_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60344   GPIO_PINCFG90_NCESRC90_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60345   GPIO_PINCFG90_NCESRC90_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60346   GPIO_PINCFG90_NCESRC90_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60347   GPIO_PINCFG90_NCESRC90_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60348   GPIO_PINCFG90_NCESRC90_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60349   GPIO_PINCFG90_NCESRC90_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60350   GPIO_PINCFG90_NCESRC90_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60351   GPIO_PINCFG90_NCESRC90_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60352   GPIO_PINCFG90_NCESRC90_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60353   GPIO_PINCFG90_NCESRC90_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60354   GPIO_PINCFG90_NCESRC90_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60355   GPIO_PINCFG90_NCESRC90_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60356   GPIO_PINCFG90_NCESRC90_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60357   GPIO_PINCFG90_NCESRC90_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60358   GPIO_PINCFG90_NCESRC90_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60359   GPIO_PINCFG90_NCESRC90_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60360   GPIO_PINCFG90_NCESRC90_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60361   GPIO_PINCFG90_NCESRC90_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60362   GPIO_PINCFG90_NCESRC90_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60363   GPIO_PINCFG90_NCESRC90_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60364   GPIO_PINCFG90_NCESRC90_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60365   GPIO_PINCFG90_NCESRC90_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60366   GPIO_PINCFG90_NCESRC90_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60367   GPIO_PINCFG90_NCESRC90_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60368   GPIO_PINCFG90_NCESRC90_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60369   GPIO_PINCFG90_NCESRC90_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60370   GPIO_PINCFG90_NCESRC90_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60371   GPIO_PINCFG90_NCESRC90_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60372   GPIO_PINCFG90_NCESRC90_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60373   GPIO_PINCFG90_NCESRC90_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60374   GPIO_PINCFG90_NCESRC90_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60375   GPIO_PINCFG90_NCESRC90_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60376   GPIO_PINCFG90_NCESRC90_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60377   GPIO_PINCFG90_NCESRC90_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60378   GPIO_PINCFG90_NCESRC90_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60379   GPIO_PINCFG90_NCESRC90_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60380   GPIO_PINCFG90_NCESRC90_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60381 } GPIO_PINCFG90_NCESRC90_Enum;
60382 
60383 /* ===========================================  GPIO PINCFG90 PULLCFG90 [13..15]  ============================================ */
60384 typedef enum {                                  /*!< GPIO_PINCFG90_PULLCFG90                                                   */
60385   GPIO_PINCFG90_PULLCFG90_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60386   GPIO_PINCFG90_PULLCFG90_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60387   GPIO_PINCFG90_PULLCFG90_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60388   GPIO_PINCFG90_PULLCFG90_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60389   GPIO_PINCFG90_PULLCFG90_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60390   GPIO_PINCFG90_PULLCFG90_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60391   GPIO_PINCFG90_PULLCFG90_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60392   GPIO_PINCFG90_PULLCFG90_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60393 } GPIO_PINCFG90_PULLCFG90_Enum;
60394 
60395 /* ==============================================  GPIO PINCFG90 DS90 [10..11]  ============================================== */
60396 typedef enum {                                  /*!< GPIO_PINCFG90_DS90                                                        */
60397   GPIO_PINCFG90_DS90_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60398   GPIO_PINCFG90_DS90_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60399 } GPIO_PINCFG90_DS90_Enum;
60400 
60401 /* =============================================  GPIO PINCFG90 OUTCFG90 [8..9]  ============================================= */
60402 typedef enum {                                  /*!< GPIO_PINCFG90_OUTCFG90                                                    */
60403   GPIO_PINCFG90_OUTCFG90_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60404   GPIO_PINCFG90_OUTCFG90_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60405                                                      and 1 values on pin.                                                      */
60406   GPIO_PINCFG90_OUTCFG90_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60407                                                      low, tristate otherwise.                                                  */
60408   GPIO_PINCFG90_OUTCFG90_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60409                                                      drive 0, 1 of HiZ on pin.                                                 */
60410 } GPIO_PINCFG90_OUTCFG90_Enum;
60411 
60412 /* =============================================  GPIO PINCFG90 IRPTEN90 [6..7]  ============================================= */
60413 typedef enum {                                  /*!< GPIO_PINCFG90_IRPTEN90                                                    */
60414   GPIO_PINCFG90_IRPTEN90_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60415   GPIO_PINCFG90_IRPTEN90_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60416                                                      on this GPIO                                                              */
60417   GPIO_PINCFG90_IRPTEN90_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60418                                                      on this GPIO                                                              */
60419   GPIO_PINCFG90_IRPTEN90_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60420                                                      GPIO                                                                      */
60421 } GPIO_PINCFG90_IRPTEN90_Enum;
60422 
60423 /* =============================================  GPIO PINCFG90 FNCSEL90 [0..3]  ============================================= */
60424 typedef enum {                                  /*!< GPIO_PINCFG90_FNCSEL90                                                    */
60425   GPIO_PINCFG90_FNCSEL90_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60426   GPIO_PINCFG90_FNCSEL90_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60427   GPIO_PINCFG90_FNCSEL90_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
60428   GPIO_PINCFG90_FNCSEL90_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60429   GPIO_PINCFG90_FNCSEL90_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60430   GPIO_PINCFG90_FNCSEL90_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60431   GPIO_PINCFG90_FNCSEL90_CT90          = 6,     /*!< CT90 : Timer/Counter input or output; Selection of direction
60432                                                      is done via CTIMER register settings.                                     */
60433   GPIO_PINCFG90_FNCSEL90_NCE90         = 7,     /*!< NCE90 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60434                                                      CE_POLARITY field                                                         */
60435   GPIO_PINCFG90_FNCSEL90_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
60436   GPIO_PINCFG90_FNCSEL90_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
60437   GPIO_PINCFG90_FNCSEL90_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60438   GPIO_PINCFG90_FNCSEL90_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60439   GPIO_PINCFG90_FNCSEL90_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60440   GPIO_PINCFG90_FNCSEL90_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60441   GPIO_PINCFG90_FNCSEL90_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60442   GPIO_PINCFG90_FNCSEL90_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60443 } GPIO_PINCFG90_FNCSEL90_Enum;
60444 
60445 /* =======================================================  PINCFG91  ======================================================== */
60446 /* ============================================  GPIO PINCFG91 NCEPOL91 [22..22]  ============================================ */
60447 typedef enum {                                  /*!< GPIO_PINCFG91_NCEPOL91                                                    */
60448   GPIO_PINCFG91_NCEPOL91_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60449   GPIO_PINCFG91_NCEPOL91_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60450 } GPIO_PINCFG91_NCEPOL91_Enum;
60451 
60452 /* ============================================  GPIO PINCFG91 NCESRC91 [16..21]  ============================================ */
60453 typedef enum {                                  /*!< GPIO_PINCFG91_NCESRC91                                                    */
60454   GPIO_PINCFG91_NCESRC91_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60455   GPIO_PINCFG91_NCESRC91_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60456   GPIO_PINCFG91_NCESRC91_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60457   GPIO_PINCFG91_NCESRC91_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60458   GPIO_PINCFG91_NCESRC91_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60459   GPIO_PINCFG91_NCESRC91_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60460   GPIO_PINCFG91_NCESRC91_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60461   GPIO_PINCFG91_NCESRC91_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60462   GPIO_PINCFG91_NCESRC91_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60463   GPIO_PINCFG91_NCESRC91_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60464   GPIO_PINCFG91_NCESRC91_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60465   GPIO_PINCFG91_NCESRC91_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60466   GPIO_PINCFG91_NCESRC91_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60467   GPIO_PINCFG91_NCESRC91_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60468   GPIO_PINCFG91_NCESRC91_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60469   GPIO_PINCFG91_NCESRC91_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60470   GPIO_PINCFG91_NCESRC91_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60471   GPIO_PINCFG91_NCESRC91_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60472   GPIO_PINCFG91_NCESRC91_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60473   GPIO_PINCFG91_NCESRC91_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60474   GPIO_PINCFG91_NCESRC91_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60475   GPIO_PINCFG91_NCESRC91_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60476   GPIO_PINCFG91_NCESRC91_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60477   GPIO_PINCFG91_NCESRC91_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60478   GPIO_PINCFG91_NCESRC91_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60479   GPIO_PINCFG91_NCESRC91_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60480   GPIO_PINCFG91_NCESRC91_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60481   GPIO_PINCFG91_NCESRC91_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60482   GPIO_PINCFG91_NCESRC91_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60483   GPIO_PINCFG91_NCESRC91_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60484   GPIO_PINCFG91_NCESRC91_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60485   GPIO_PINCFG91_NCESRC91_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60486   GPIO_PINCFG91_NCESRC91_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60487   GPIO_PINCFG91_NCESRC91_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60488   GPIO_PINCFG91_NCESRC91_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60489   GPIO_PINCFG91_NCESRC91_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60490   GPIO_PINCFG91_NCESRC91_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60491   GPIO_PINCFG91_NCESRC91_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60492   GPIO_PINCFG91_NCESRC91_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60493   GPIO_PINCFG91_NCESRC91_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60494   GPIO_PINCFG91_NCESRC91_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60495   GPIO_PINCFG91_NCESRC91_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60496   GPIO_PINCFG91_NCESRC91_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60497 } GPIO_PINCFG91_NCESRC91_Enum;
60498 
60499 /* ===========================================  GPIO PINCFG91 PULLCFG91 [13..15]  ============================================ */
60500 typedef enum {                                  /*!< GPIO_PINCFG91_PULLCFG91                                                   */
60501   GPIO_PINCFG91_PULLCFG91_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60502   GPIO_PINCFG91_PULLCFG91_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60503   GPIO_PINCFG91_PULLCFG91_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60504   GPIO_PINCFG91_PULLCFG91_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60505   GPIO_PINCFG91_PULLCFG91_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60506   GPIO_PINCFG91_PULLCFG91_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60507   GPIO_PINCFG91_PULLCFG91_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60508   GPIO_PINCFG91_PULLCFG91_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60509 } GPIO_PINCFG91_PULLCFG91_Enum;
60510 
60511 /* ==============================================  GPIO PINCFG91 DS91 [10..11]  ============================================== */
60512 typedef enum {                                  /*!< GPIO_PINCFG91_DS91                                                        */
60513   GPIO_PINCFG91_DS91_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60514   GPIO_PINCFG91_DS91_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60515 } GPIO_PINCFG91_DS91_Enum;
60516 
60517 /* =============================================  GPIO PINCFG91 OUTCFG91 [8..9]  ============================================= */
60518 typedef enum {                                  /*!< GPIO_PINCFG91_OUTCFG91                                                    */
60519   GPIO_PINCFG91_OUTCFG91_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60520   GPIO_PINCFG91_OUTCFG91_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60521                                                      and 1 values on pin.                                                      */
60522   GPIO_PINCFG91_OUTCFG91_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60523                                                      low, tristate otherwise.                                                  */
60524   GPIO_PINCFG91_OUTCFG91_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60525                                                      drive 0, 1 of HiZ on pin.                                                 */
60526 } GPIO_PINCFG91_OUTCFG91_Enum;
60527 
60528 /* =============================================  GPIO PINCFG91 IRPTEN91 [6..7]  ============================================= */
60529 typedef enum {                                  /*!< GPIO_PINCFG91_IRPTEN91                                                    */
60530   GPIO_PINCFG91_IRPTEN91_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60531   GPIO_PINCFG91_IRPTEN91_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60532                                                      on this GPIO                                                              */
60533   GPIO_PINCFG91_IRPTEN91_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60534                                                      on this GPIO                                                              */
60535   GPIO_PINCFG91_IRPTEN91_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60536                                                      GPIO                                                                      */
60537 } GPIO_PINCFG91_IRPTEN91_Enum;
60538 
60539 /* =============================================  GPIO PINCFG91 FNCSEL91 [0..3]  ============================================= */
60540 typedef enum {                                  /*!< GPIO_PINCFG91_FNCSEL91                                                    */
60541   GPIO_PINCFG91_FNCSEL91_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60542   GPIO_PINCFG91_FNCSEL91_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60543   GPIO_PINCFG91_FNCSEL91_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
60544   GPIO_PINCFG91_FNCSEL91_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60545   GPIO_PINCFG91_FNCSEL91_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60546   GPIO_PINCFG91_FNCSEL91_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60547   GPIO_PINCFG91_FNCSEL91_CT91          = 6,     /*!< CT91 : Timer/Counter input or output; Selection of direction
60548                                                      is done via CTIMER register settings.                                     */
60549   GPIO_PINCFG91_FNCSEL91_NCE91         = 7,     /*!< NCE91 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60550                                                      CE_POLARITY field                                                         */
60551   GPIO_PINCFG91_FNCSEL91_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
60552   GPIO_PINCFG91_FNCSEL91_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
60553   GPIO_PINCFG91_FNCSEL91_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60554   GPIO_PINCFG91_FNCSEL91_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60555   GPIO_PINCFG91_FNCSEL91_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60556   GPIO_PINCFG91_FNCSEL91_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60557   GPIO_PINCFG91_FNCSEL91_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60558   GPIO_PINCFG91_FNCSEL91_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60559 } GPIO_PINCFG91_FNCSEL91_Enum;
60560 
60561 /* =======================================================  PINCFG92  ======================================================== */
60562 /* ============================================  GPIO PINCFG92 NCEPOL92 [22..22]  ============================================ */
60563 typedef enum {                                  /*!< GPIO_PINCFG92_NCEPOL92                                                    */
60564   GPIO_PINCFG92_NCEPOL92_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60565   GPIO_PINCFG92_NCEPOL92_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60566 } GPIO_PINCFG92_NCEPOL92_Enum;
60567 
60568 /* ============================================  GPIO PINCFG92 NCESRC92 [16..21]  ============================================ */
60569 typedef enum {                                  /*!< GPIO_PINCFG92_NCESRC92                                                    */
60570   GPIO_PINCFG92_NCESRC92_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60571   GPIO_PINCFG92_NCESRC92_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60572   GPIO_PINCFG92_NCESRC92_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60573   GPIO_PINCFG92_NCESRC92_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60574   GPIO_PINCFG92_NCESRC92_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60575   GPIO_PINCFG92_NCESRC92_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60576   GPIO_PINCFG92_NCESRC92_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60577   GPIO_PINCFG92_NCESRC92_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60578   GPIO_PINCFG92_NCESRC92_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60579   GPIO_PINCFG92_NCESRC92_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60580   GPIO_PINCFG92_NCESRC92_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60581   GPIO_PINCFG92_NCESRC92_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60582   GPIO_PINCFG92_NCESRC92_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60583   GPIO_PINCFG92_NCESRC92_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60584   GPIO_PINCFG92_NCESRC92_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60585   GPIO_PINCFG92_NCESRC92_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60586   GPIO_PINCFG92_NCESRC92_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60587   GPIO_PINCFG92_NCESRC92_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60588   GPIO_PINCFG92_NCESRC92_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60589   GPIO_PINCFG92_NCESRC92_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60590   GPIO_PINCFG92_NCESRC92_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60591   GPIO_PINCFG92_NCESRC92_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60592   GPIO_PINCFG92_NCESRC92_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60593   GPIO_PINCFG92_NCESRC92_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60594   GPIO_PINCFG92_NCESRC92_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60595   GPIO_PINCFG92_NCESRC92_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60596   GPIO_PINCFG92_NCESRC92_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60597   GPIO_PINCFG92_NCESRC92_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60598   GPIO_PINCFG92_NCESRC92_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60599   GPIO_PINCFG92_NCESRC92_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60600   GPIO_PINCFG92_NCESRC92_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60601   GPIO_PINCFG92_NCESRC92_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60602   GPIO_PINCFG92_NCESRC92_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60603   GPIO_PINCFG92_NCESRC92_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60604   GPIO_PINCFG92_NCESRC92_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60605   GPIO_PINCFG92_NCESRC92_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60606   GPIO_PINCFG92_NCESRC92_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60607   GPIO_PINCFG92_NCESRC92_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60608   GPIO_PINCFG92_NCESRC92_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60609   GPIO_PINCFG92_NCESRC92_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60610   GPIO_PINCFG92_NCESRC92_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60611   GPIO_PINCFG92_NCESRC92_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60612   GPIO_PINCFG92_NCESRC92_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60613 } GPIO_PINCFG92_NCESRC92_Enum;
60614 
60615 /* ===========================================  GPIO PINCFG92 PULLCFG92 [13..15]  ============================================ */
60616 typedef enum {                                  /*!< GPIO_PINCFG92_PULLCFG92                                                   */
60617   GPIO_PINCFG92_PULLCFG92_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60618   GPIO_PINCFG92_PULLCFG92_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60619   GPIO_PINCFG92_PULLCFG92_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60620   GPIO_PINCFG92_PULLCFG92_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60621   GPIO_PINCFG92_PULLCFG92_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60622   GPIO_PINCFG92_PULLCFG92_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60623   GPIO_PINCFG92_PULLCFG92_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60624   GPIO_PINCFG92_PULLCFG92_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60625 } GPIO_PINCFG92_PULLCFG92_Enum;
60626 
60627 /* ==============================================  GPIO PINCFG92 DS92 [10..11]  ============================================== */
60628 typedef enum {                                  /*!< GPIO_PINCFG92_DS92                                                        */
60629   GPIO_PINCFG92_DS92_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60630   GPIO_PINCFG92_DS92_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60631 } GPIO_PINCFG92_DS92_Enum;
60632 
60633 /* =============================================  GPIO PINCFG92 OUTCFG92 [8..9]  ============================================= */
60634 typedef enum {                                  /*!< GPIO_PINCFG92_OUTCFG92                                                    */
60635   GPIO_PINCFG92_OUTCFG92_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60636   GPIO_PINCFG92_OUTCFG92_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60637                                                      and 1 values on pin.                                                      */
60638   GPIO_PINCFG92_OUTCFG92_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60639                                                      low, tristate otherwise.                                                  */
60640   GPIO_PINCFG92_OUTCFG92_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60641                                                      drive 0, 1 of HiZ on pin.                                                 */
60642 } GPIO_PINCFG92_OUTCFG92_Enum;
60643 
60644 /* =============================================  GPIO PINCFG92 IRPTEN92 [6..7]  ============================================= */
60645 typedef enum {                                  /*!< GPIO_PINCFG92_IRPTEN92                                                    */
60646   GPIO_PINCFG92_IRPTEN92_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60647   GPIO_PINCFG92_IRPTEN92_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60648                                                      on this GPIO                                                              */
60649   GPIO_PINCFG92_IRPTEN92_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60650                                                      on this GPIO                                                              */
60651   GPIO_PINCFG92_IRPTEN92_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60652                                                      GPIO                                                                      */
60653 } GPIO_PINCFG92_IRPTEN92_Enum;
60654 
60655 /* =============================================  GPIO PINCFG92 FNCSEL92 [0..3]  ============================================= */
60656 typedef enum {                                  /*!< GPIO_PINCFG92_FNCSEL92                                                    */
60657   GPIO_PINCFG92_FNCSEL92_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60658   GPIO_PINCFG92_FNCSEL92_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60659   GPIO_PINCFG92_FNCSEL92_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
60660   GPIO_PINCFG92_FNCSEL92_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60661   GPIO_PINCFG92_FNCSEL92_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60662   GPIO_PINCFG92_FNCSEL92_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60663   GPIO_PINCFG92_FNCSEL92_CT92          = 6,     /*!< CT92 : Timer/Counter input or output; Selection of direction
60664                                                      is done via CTIMER register settings.                                     */
60665   GPIO_PINCFG92_FNCSEL92_NCE92         = 7,     /*!< NCE92 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60666                                                      CE_POLARITY field                                                         */
60667   GPIO_PINCFG92_FNCSEL92_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
60668   GPIO_PINCFG92_FNCSEL92_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
60669   GPIO_PINCFG92_FNCSEL92_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60670   GPIO_PINCFG92_FNCSEL92_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60671   GPIO_PINCFG92_FNCSEL92_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60672   GPIO_PINCFG92_FNCSEL92_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60673   GPIO_PINCFG92_FNCSEL92_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60674   GPIO_PINCFG92_FNCSEL92_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60675 } GPIO_PINCFG92_FNCSEL92_Enum;
60676 
60677 /* =======================================================  PINCFG93  ======================================================== */
60678 /* ============================================  GPIO PINCFG93 NCEPOL93 [22..22]  ============================================ */
60679 typedef enum {                                  /*!< GPIO_PINCFG93_NCEPOL93                                                    */
60680   GPIO_PINCFG93_NCEPOL93_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60681   GPIO_PINCFG93_NCEPOL93_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60682 } GPIO_PINCFG93_NCEPOL93_Enum;
60683 
60684 /* ============================================  GPIO PINCFG93 NCESRC93 [16..21]  ============================================ */
60685 typedef enum {                                  /*!< GPIO_PINCFG93_NCESRC93                                                    */
60686   GPIO_PINCFG93_NCESRC93_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60687   GPIO_PINCFG93_NCESRC93_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60688   GPIO_PINCFG93_NCESRC93_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60689   GPIO_PINCFG93_NCESRC93_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60690   GPIO_PINCFG93_NCESRC93_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60691   GPIO_PINCFG93_NCESRC93_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60692   GPIO_PINCFG93_NCESRC93_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60693   GPIO_PINCFG93_NCESRC93_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60694   GPIO_PINCFG93_NCESRC93_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60695   GPIO_PINCFG93_NCESRC93_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60696   GPIO_PINCFG93_NCESRC93_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60697   GPIO_PINCFG93_NCESRC93_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60698   GPIO_PINCFG93_NCESRC93_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60699   GPIO_PINCFG93_NCESRC93_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60700   GPIO_PINCFG93_NCESRC93_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60701   GPIO_PINCFG93_NCESRC93_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60702   GPIO_PINCFG93_NCESRC93_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60703   GPIO_PINCFG93_NCESRC93_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60704   GPIO_PINCFG93_NCESRC93_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60705   GPIO_PINCFG93_NCESRC93_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60706   GPIO_PINCFG93_NCESRC93_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60707   GPIO_PINCFG93_NCESRC93_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60708   GPIO_PINCFG93_NCESRC93_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60709   GPIO_PINCFG93_NCESRC93_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60710   GPIO_PINCFG93_NCESRC93_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60711   GPIO_PINCFG93_NCESRC93_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60712   GPIO_PINCFG93_NCESRC93_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60713   GPIO_PINCFG93_NCESRC93_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60714   GPIO_PINCFG93_NCESRC93_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60715   GPIO_PINCFG93_NCESRC93_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60716   GPIO_PINCFG93_NCESRC93_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60717   GPIO_PINCFG93_NCESRC93_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60718   GPIO_PINCFG93_NCESRC93_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60719   GPIO_PINCFG93_NCESRC93_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60720   GPIO_PINCFG93_NCESRC93_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60721   GPIO_PINCFG93_NCESRC93_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60722   GPIO_PINCFG93_NCESRC93_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60723   GPIO_PINCFG93_NCESRC93_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60724   GPIO_PINCFG93_NCESRC93_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60725   GPIO_PINCFG93_NCESRC93_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60726   GPIO_PINCFG93_NCESRC93_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60727   GPIO_PINCFG93_NCESRC93_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60728   GPIO_PINCFG93_NCESRC93_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60729 } GPIO_PINCFG93_NCESRC93_Enum;
60730 
60731 /* ===========================================  GPIO PINCFG93 PULLCFG93 [13..15]  ============================================ */
60732 typedef enum {                                  /*!< GPIO_PINCFG93_PULLCFG93                                                   */
60733   GPIO_PINCFG93_PULLCFG93_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60734   GPIO_PINCFG93_PULLCFG93_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60735   GPIO_PINCFG93_PULLCFG93_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60736   GPIO_PINCFG93_PULLCFG93_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60737   GPIO_PINCFG93_PULLCFG93_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60738   GPIO_PINCFG93_PULLCFG93_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60739   GPIO_PINCFG93_PULLCFG93_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60740   GPIO_PINCFG93_PULLCFG93_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60741 } GPIO_PINCFG93_PULLCFG93_Enum;
60742 
60743 /* ==============================================  GPIO PINCFG93 DS93 [10..11]  ============================================== */
60744 typedef enum {                                  /*!< GPIO_PINCFG93_DS93                                                        */
60745   GPIO_PINCFG93_DS93_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60746   GPIO_PINCFG93_DS93_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60747 } GPIO_PINCFG93_DS93_Enum;
60748 
60749 /* =============================================  GPIO PINCFG93 OUTCFG93 [8..9]  ============================================= */
60750 typedef enum {                                  /*!< GPIO_PINCFG93_OUTCFG93                                                    */
60751   GPIO_PINCFG93_OUTCFG93_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60752   GPIO_PINCFG93_OUTCFG93_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60753                                                      and 1 values on pin.                                                      */
60754   GPIO_PINCFG93_OUTCFG93_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60755                                                      low, tristate otherwise.                                                  */
60756   GPIO_PINCFG93_OUTCFG93_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60757                                                      drive 0, 1 of HiZ on pin.                                                 */
60758 } GPIO_PINCFG93_OUTCFG93_Enum;
60759 
60760 /* =============================================  GPIO PINCFG93 IRPTEN93 [6..7]  ============================================= */
60761 typedef enum {                                  /*!< GPIO_PINCFG93_IRPTEN93                                                    */
60762   GPIO_PINCFG93_IRPTEN93_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60763   GPIO_PINCFG93_IRPTEN93_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60764                                                      on this GPIO                                                              */
60765   GPIO_PINCFG93_IRPTEN93_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60766                                                      on this GPIO                                                              */
60767   GPIO_PINCFG93_IRPTEN93_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60768                                                      GPIO                                                                      */
60769 } GPIO_PINCFG93_IRPTEN93_Enum;
60770 
60771 /* =============================================  GPIO PINCFG93 FNCSEL93 [0..3]  ============================================= */
60772 typedef enum {                                  /*!< GPIO_PINCFG93_FNCSEL93                                                    */
60773   GPIO_PINCFG93_FNCSEL93_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60774   GPIO_PINCFG93_FNCSEL93_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60775   GPIO_PINCFG93_FNCSEL93_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
60776   GPIO_PINCFG93_FNCSEL93_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60777   GPIO_PINCFG93_FNCSEL93_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60778   GPIO_PINCFG93_FNCSEL93_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60779   GPIO_PINCFG93_FNCSEL93_CT93          = 6,     /*!< CT93 : Timer/Counter input or output; Selection of direction
60780                                                      is done via CTIMER register settings.                                     */
60781   GPIO_PINCFG93_FNCSEL93_NCE93         = 7,     /*!< NCE93 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60782                                                      CE_POLARITY field                                                         */
60783   GPIO_PINCFG93_FNCSEL93_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
60784   GPIO_PINCFG93_FNCSEL93_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
60785   GPIO_PINCFG93_FNCSEL93_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60786   GPIO_PINCFG93_FNCSEL93_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60787   GPIO_PINCFG93_FNCSEL93_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60788   GPIO_PINCFG93_FNCSEL93_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60789   GPIO_PINCFG93_FNCSEL93_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60790   GPIO_PINCFG93_FNCSEL93_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60791 } GPIO_PINCFG93_FNCSEL93_Enum;
60792 
60793 /* =======================================================  PINCFG94  ======================================================== */
60794 /* ============================================  GPIO PINCFG94 NCEPOL94 [22..22]  ============================================ */
60795 typedef enum {                                  /*!< GPIO_PINCFG94_NCEPOL94                                                    */
60796   GPIO_PINCFG94_NCEPOL94_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60797   GPIO_PINCFG94_NCEPOL94_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60798 } GPIO_PINCFG94_NCEPOL94_Enum;
60799 
60800 /* ============================================  GPIO PINCFG94 NCESRC94 [16..21]  ============================================ */
60801 typedef enum {                                  /*!< GPIO_PINCFG94_NCESRC94                                                    */
60802   GPIO_PINCFG94_NCESRC94_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60803   GPIO_PINCFG94_NCESRC94_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60804   GPIO_PINCFG94_NCESRC94_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60805   GPIO_PINCFG94_NCESRC94_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60806   GPIO_PINCFG94_NCESRC94_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60807   GPIO_PINCFG94_NCESRC94_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60808   GPIO_PINCFG94_NCESRC94_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60809   GPIO_PINCFG94_NCESRC94_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60810   GPIO_PINCFG94_NCESRC94_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60811   GPIO_PINCFG94_NCESRC94_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60812   GPIO_PINCFG94_NCESRC94_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60813   GPIO_PINCFG94_NCESRC94_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60814   GPIO_PINCFG94_NCESRC94_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60815   GPIO_PINCFG94_NCESRC94_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60816   GPIO_PINCFG94_NCESRC94_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60817   GPIO_PINCFG94_NCESRC94_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60818   GPIO_PINCFG94_NCESRC94_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60819   GPIO_PINCFG94_NCESRC94_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60820   GPIO_PINCFG94_NCESRC94_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60821   GPIO_PINCFG94_NCESRC94_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60822   GPIO_PINCFG94_NCESRC94_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60823   GPIO_PINCFG94_NCESRC94_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60824   GPIO_PINCFG94_NCESRC94_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60825   GPIO_PINCFG94_NCESRC94_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60826   GPIO_PINCFG94_NCESRC94_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60827   GPIO_PINCFG94_NCESRC94_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60828   GPIO_PINCFG94_NCESRC94_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60829   GPIO_PINCFG94_NCESRC94_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60830   GPIO_PINCFG94_NCESRC94_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60831   GPIO_PINCFG94_NCESRC94_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60832   GPIO_PINCFG94_NCESRC94_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60833   GPIO_PINCFG94_NCESRC94_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60834   GPIO_PINCFG94_NCESRC94_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60835   GPIO_PINCFG94_NCESRC94_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60836   GPIO_PINCFG94_NCESRC94_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60837   GPIO_PINCFG94_NCESRC94_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60838   GPIO_PINCFG94_NCESRC94_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60839   GPIO_PINCFG94_NCESRC94_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60840   GPIO_PINCFG94_NCESRC94_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60841   GPIO_PINCFG94_NCESRC94_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60842   GPIO_PINCFG94_NCESRC94_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60843   GPIO_PINCFG94_NCESRC94_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60844   GPIO_PINCFG94_NCESRC94_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60845 } GPIO_PINCFG94_NCESRC94_Enum;
60846 
60847 /* ===========================================  GPIO PINCFG94 PULLCFG94 [13..15]  ============================================ */
60848 typedef enum {                                  /*!< GPIO_PINCFG94_PULLCFG94                                                   */
60849   GPIO_PINCFG94_PULLCFG94_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60850   GPIO_PINCFG94_PULLCFG94_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60851   GPIO_PINCFG94_PULLCFG94_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60852   GPIO_PINCFG94_PULLCFG94_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60853   GPIO_PINCFG94_PULLCFG94_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60854   GPIO_PINCFG94_PULLCFG94_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60855   GPIO_PINCFG94_PULLCFG94_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60856   GPIO_PINCFG94_PULLCFG94_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60857 } GPIO_PINCFG94_PULLCFG94_Enum;
60858 
60859 /* ==============================================  GPIO PINCFG94 DS94 [10..11]  ============================================== */
60860 typedef enum {                                  /*!< GPIO_PINCFG94_DS94                                                        */
60861   GPIO_PINCFG94_DS94_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60862   GPIO_PINCFG94_DS94_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60863 } GPIO_PINCFG94_DS94_Enum;
60864 
60865 /* =============================================  GPIO PINCFG94 OUTCFG94 [8..9]  ============================================= */
60866 typedef enum {                                  /*!< GPIO_PINCFG94_OUTCFG94                                                    */
60867   GPIO_PINCFG94_OUTCFG94_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60868   GPIO_PINCFG94_OUTCFG94_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60869                                                      and 1 values on pin.                                                      */
60870   GPIO_PINCFG94_OUTCFG94_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60871                                                      low, tristate otherwise.                                                  */
60872   GPIO_PINCFG94_OUTCFG94_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60873                                                      drive 0, 1 of HiZ on pin.                                                 */
60874 } GPIO_PINCFG94_OUTCFG94_Enum;
60875 
60876 /* =============================================  GPIO PINCFG94 IRPTEN94 [6..7]  ============================================= */
60877 typedef enum {                                  /*!< GPIO_PINCFG94_IRPTEN94                                                    */
60878   GPIO_PINCFG94_IRPTEN94_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60879   GPIO_PINCFG94_IRPTEN94_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60880                                                      on this GPIO                                                              */
60881   GPIO_PINCFG94_IRPTEN94_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60882                                                      on this GPIO                                                              */
60883   GPIO_PINCFG94_IRPTEN94_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60884                                                      GPIO                                                                      */
60885 } GPIO_PINCFG94_IRPTEN94_Enum;
60886 
60887 /* =============================================  GPIO PINCFG94 FNCSEL94 [0..3]  ============================================= */
60888 typedef enum {                                  /*!< GPIO_PINCFG94_FNCSEL94                                                    */
60889   GPIO_PINCFG94_FNCSEL94_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60890   GPIO_PINCFG94_FNCSEL94_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60891   GPIO_PINCFG94_FNCSEL94_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
60892   GPIO_PINCFG94_FNCSEL94_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60893   GPIO_PINCFG94_FNCSEL94_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60894   GPIO_PINCFG94_FNCSEL94_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60895   GPIO_PINCFG94_FNCSEL94_CT94          = 6,     /*!< CT94 : Timer/Counter input or output; Selection of direction
60896                                                      is done via CTIMER register settings.                                     */
60897   GPIO_PINCFG94_FNCSEL94_NCE94         = 7,     /*!< NCE94 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60898                                                      CE_POLARITY field                                                         */
60899   GPIO_PINCFG94_FNCSEL94_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
60900   GPIO_PINCFG94_FNCSEL94_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
60901   GPIO_PINCFG94_FNCSEL94_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60902   GPIO_PINCFG94_FNCSEL94_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60903   GPIO_PINCFG94_FNCSEL94_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60904   GPIO_PINCFG94_FNCSEL94_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60905   GPIO_PINCFG94_FNCSEL94_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60906   GPIO_PINCFG94_FNCSEL94_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60907 } GPIO_PINCFG94_FNCSEL94_Enum;
60908 
60909 /* =======================================================  PINCFG95  ======================================================== */
60910 /* ============================================  GPIO PINCFG95 NCEPOL95 [22..22]  ============================================ */
60911 typedef enum {                                  /*!< GPIO_PINCFG95_NCEPOL95                                                    */
60912   GPIO_PINCFG95_NCEPOL95_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60913   GPIO_PINCFG95_NCEPOL95_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60914 } GPIO_PINCFG95_NCEPOL95_Enum;
60915 
60916 /* ============================================  GPIO PINCFG95 NCESRC95 [16..21]  ============================================ */
60917 typedef enum {                                  /*!< GPIO_PINCFG95_NCESRC95                                                    */
60918   GPIO_PINCFG95_NCESRC95_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60919   GPIO_PINCFG95_NCESRC95_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60920   GPIO_PINCFG95_NCESRC95_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60921   GPIO_PINCFG95_NCESRC95_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60922   GPIO_PINCFG95_NCESRC95_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60923   GPIO_PINCFG95_NCESRC95_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60924   GPIO_PINCFG95_NCESRC95_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60925   GPIO_PINCFG95_NCESRC95_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60926   GPIO_PINCFG95_NCESRC95_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60927   GPIO_PINCFG95_NCESRC95_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60928   GPIO_PINCFG95_NCESRC95_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60929   GPIO_PINCFG95_NCESRC95_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60930   GPIO_PINCFG95_NCESRC95_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60931   GPIO_PINCFG95_NCESRC95_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60932   GPIO_PINCFG95_NCESRC95_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60933   GPIO_PINCFG95_NCESRC95_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60934   GPIO_PINCFG95_NCESRC95_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60935   GPIO_PINCFG95_NCESRC95_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60936   GPIO_PINCFG95_NCESRC95_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60937   GPIO_PINCFG95_NCESRC95_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60938   GPIO_PINCFG95_NCESRC95_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60939   GPIO_PINCFG95_NCESRC95_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60940   GPIO_PINCFG95_NCESRC95_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60941   GPIO_PINCFG95_NCESRC95_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60942   GPIO_PINCFG95_NCESRC95_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60943   GPIO_PINCFG95_NCESRC95_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60944   GPIO_PINCFG95_NCESRC95_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60945   GPIO_PINCFG95_NCESRC95_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60946   GPIO_PINCFG95_NCESRC95_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60947   GPIO_PINCFG95_NCESRC95_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60948   GPIO_PINCFG95_NCESRC95_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60949   GPIO_PINCFG95_NCESRC95_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60950   GPIO_PINCFG95_NCESRC95_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60951   GPIO_PINCFG95_NCESRC95_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60952   GPIO_PINCFG95_NCESRC95_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60953   GPIO_PINCFG95_NCESRC95_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60954   GPIO_PINCFG95_NCESRC95_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60955   GPIO_PINCFG95_NCESRC95_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60956   GPIO_PINCFG95_NCESRC95_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60957   GPIO_PINCFG95_NCESRC95_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60958   GPIO_PINCFG95_NCESRC95_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60959   GPIO_PINCFG95_NCESRC95_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60960   GPIO_PINCFG95_NCESRC95_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60961 } GPIO_PINCFG95_NCESRC95_Enum;
60962 
60963 /* ===========================================  GPIO PINCFG95 PULLCFG95 [13..15]  ============================================ */
60964 typedef enum {                                  /*!< GPIO_PINCFG95_PULLCFG95                                                   */
60965   GPIO_PINCFG95_PULLCFG95_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60966   GPIO_PINCFG95_PULLCFG95_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60967   GPIO_PINCFG95_PULLCFG95_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60968   GPIO_PINCFG95_PULLCFG95_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60969   GPIO_PINCFG95_PULLCFG95_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60970   GPIO_PINCFG95_PULLCFG95_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60971   GPIO_PINCFG95_PULLCFG95_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60972   GPIO_PINCFG95_PULLCFG95_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60973 } GPIO_PINCFG95_PULLCFG95_Enum;
60974 
60975 /* ==============================================  GPIO PINCFG95 DS95 [10..11]  ============================================== */
60976 typedef enum {                                  /*!< GPIO_PINCFG95_DS95                                                        */
60977   GPIO_PINCFG95_DS95_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60978   GPIO_PINCFG95_DS95_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60979 } GPIO_PINCFG95_DS95_Enum;
60980 
60981 /* =============================================  GPIO PINCFG95 OUTCFG95 [8..9]  ============================================= */
60982 typedef enum {                                  /*!< GPIO_PINCFG95_OUTCFG95                                                    */
60983   GPIO_PINCFG95_OUTCFG95_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60984   GPIO_PINCFG95_OUTCFG95_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60985                                                      and 1 values on pin.                                                      */
60986   GPIO_PINCFG95_OUTCFG95_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60987                                                      low, tristate otherwise.                                                  */
60988   GPIO_PINCFG95_OUTCFG95_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60989                                                      drive 0, 1 of HiZ on pin.                                                 */
60990 } GPIO_PINCFG95_OUTCFG95_Enum;
60991 
60992 /* =============================================  GPIO PINCFG95 IRPTEN95 [6..7]  ============================================= */
60993 typedef enum {                                  /*!< GPIO_PINCFG95_IRPTEN95                                                    */
60994   GPIO_PINCFG95_IRPTEN95_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60995   GPIO_PINCFG95_IRPTEN95_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60996                                                      on this GPIO                                                              */
60997   GPIO_PINCFG95_IRPTEN95_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60998                                                      on this GPIO                                                              */
60999   GPIO_PINCFG95_IRPTEN95_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61000                                                      GPIO                                                                      */
61001 } GPIO_PINCFG95_IRPTEN95_Enum;
61002 
61003 /* =============================================  GPIO PINCFG95 FNCSEL95 [0..3]  ============================================= */
61004 typedef enum {                                  /*!< GPIO_PINCFG95_FNCSEL95                                                    */
61005   GPIO_PINCFG95_FNCSEL95_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61006   GPIO_PINCFG95_FNCSEL95_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61007   GPIO_PINCFG95_FNCSEL95_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61008   GPIO_PINCFG95_FNCSEL95_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61009   GPIO_PINCFG95_FNCSEL95_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61010   GPIO_PINCFG95_FNCSEL95_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61011   GPIO_PINCFG95_FNCSEL95_CT95          = 6,     /*!< CT95 : Timer/Counter input or output; Selection of direction
61012                                                      is done via CTIMER register settings.                                     */
61013   GPIO_PINCFG95_FNCSEL95_NCE95         = 7,     /*!< NCE95 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61014                                                      CE_POLARITY field                                                         */
61015   GPIO_PINCFG95_FNCSEL95_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
61016   GPIO_PINCFG95_FNCSEL95_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61017   GPIO_PINCFG95_FNCSEL95_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61018   GPIO_PINCFG95_FNCSEL95_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61019   GPIO_PINCFG95_FNCSEL95_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61020   GPIO_PINCFG95_FNCSEL95_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61021   GPIO_PINCFG95_FNCSEL95_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61022   GPIO_PINCFG95_FNCSEL95_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61023 } GPIO_PINCFG95_FNCSEL95_Enum;
61024 
61025 /* =======================================================  PINCFG96  ======================================================== */
61026 /* ============================================  GPIO PINCFG96 NCEPOL96 [22..22]  ============================================ */
61027 typedef enum {                                  /*!< GPIO_PINCFG96_NCEPOL96                                                    */
61028   GPIO_PINCFG96_NCEPOL96_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61029   GPIO_PINCFG96_NCEPOL96_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61030 } GPIO_PINCFG96_NCEPOL96_Enum;
61031 
61032 /* ============================================  GPIO PINCFG96 NCESRC96 [16..21]  ============================================ */
61033 typedef enum {                                  /*!< GPIO_PINCFG96_NCESRC96                                                    */
61034   GPIO_PINCFG96_NCESRC96_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61035   GPIO_PINCFG96_NCESRC96_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61036   GPIO_PINCFG96_NCESRC96_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61037   GPIO_PINCFG96_NCESRC96_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61038   GPIO_PINCFG96_NCESRC96_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61039   GPIO_PINCFG96_NCESRC96_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61040   GPIO_PINCFG96_NCESRC96_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61041   GPIO_PINCFG96_NCESRC96_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61042   GPIO_PINCFG96_NCESRC96_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61043   GPIO_PINCFG96_NCESRC96_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61044   GPIO_PINCFG96_NCESRC96_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61045   GPIO_PINCFG96_NCESRC96_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61046   GPIO_PINCFG96_NCESRC96_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61047   GPIO_PINCFG96_NCESRC96_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61048   GPIO_PINCFG96_NCESRC96_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61049   GPIO_PINCFG96_NCESRC96_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61050   GPIO_PINCFG96_NCESRC96_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61051   GPIO_PINCFG96_NCESRC96_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61052   GPIO_PINCFG96_NCESRC96_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61053   GPIO_PINCFG96_NCESRC96_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61054   GPIO_PINCFG96_NCESRC96_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61055   GPIO_PINCFG96_NCESRC96_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61056   GPIO_PINCFG96_NCESRC96_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61057   GPIO_PINCFG96_NCESRC96_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61058   GPIO_PINCFG96_NCESRC96_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61059   GPIO_PINCFG96_NCESRC96_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61060   GPIO_PINCFG96_NCESRC96_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61061   GPIO_PINCFG96_NCESRC96_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61062   GPIO_PINCFG96_NCESRC96_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61063   GPIO_PINCFG96_NCESRC96_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61064   GPIO_PINCFG96_NCESRC96_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61065   GPIO_PINCFG96_NCESRC96_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61066   GPIO_PINCFG96_NCESRC96_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61067   GPIO_PINCFG96_NCESRC96_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61068   GPIO_PINCFG96_NCESRC96_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61069   GPIO_PINCFG96_NCESRC96_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61070   GPIO_PINCFG96_NCESRC96_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61071   GPIO_PINCFG96_NCESRC96_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61072   GPIO_PINCFG96_NCESRC96_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61073   GPIO_PINCFG96_NCESRC96_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61074   GPIO_PINCFG96_NCESRC96_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61075   GPIO_PINCFG96_NCESRC96_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61076   GPIO_PINCFG96_NCESRC96_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61077 } GPIO_PINCFG96_NCESRC96_Enum;
61078 
61079 /* ===========================================  GPIO PINCFG96 PULLCFG96 [13..15]  ============================================ */
61080 typedef enum {                                  /*!< GPIO_PINCFG96_PULLCFG96                                                   */
61081   GPIO_PINCFG96_PULLCFG96_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61082   GPIO_PINCFG96_PULLCFG96_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61083   GPIO_PINCFG96_PULLCFG96_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61084   GPIO_PINCFG96_PULLCFG96_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61085   GPIO_PINCFG96_PULLCFG96_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61086   GPIO_PINCFG96_PULLCFG96_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61087   GPIO_PINCFG96_PULLCFG96_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61088   GPIO_PINCFG96_PULLCFG96_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61089 } GPIO_PINCFG96_PULLCFG96_Enum;
61090 
61091 /* ==============================================  GPIO PINCFG96 DS96 [10..11]  ============================================== */
61092 typedef enum {                                  /*!< GPIO_PINCFG96_DS96                                                        */
61093   GPIO_PINCFG96_DS96_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61094   GPIO_PINCFG96_DS96_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61095 } GPIO_PINCFG96_DS96_Enum;
61096 
61097 /* =============================================  GPIO PINCFG96 OUTCFG96 [8..9]  ============================================= */
61098 typedef enum {                                  /*!< GPIO_PINCFG96_OUTCFG96                                                    */
61099   GPIO_PINCFG96_OUTCFG96_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61100   GPIO_PINCFG96_OUTCFG96_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61101                                                      and 1 values on pin.                                                      */
61102   GPIO_PINCFG96_OUTCFG96_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61103                                                      low, tristate otherwise.                                                  */
61104   GPIO_PINCFG96_OUTCFG96_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61105                                                      drive 0, 1 of HiZ on pin.                                                 */
61106 } GPIO_PINCFG96_OUTCFG96_Enum;
61107 
61108 /* =============================================  GPIO PINCFG96 IRPTEN96 [6..7]  ============================================= */
61109 typedef enum {                                  /*!< GPIO_PINCFG96_IRPTEN96                                                    */
61110   GPIO_PINCFG96_IRPTEN96_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61111   GPIO_PINCFG96_IRPTEN96_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61112                                                      on this GPIO                                                              */
61113   GPIO_PINCFG96_IRPTEN96_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61114                                                      on this GPIO                                                              */
61115   GPIO_PINCFG96_IRPTEN96_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61116                                                      GPIO                                                                      */
61117 } GPIO_PINCFG96_IRPTEN96_Enum;
61118 
61119 /* =============================================  GPIO PINCFG96 FNCSEL96 [0..3]  ============================================= */
61120 typedef enum {                                  /*!< GPIO_PINCFG96_FNCSEL96                                                    */
61121   GPIO_PINCFG96_FNCSEL96_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61122   GPIO_PINCFG96_FNCSEL96_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61123   GPIO_PINCFG96_FNCSEL96_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61124   GPIO_PINCFG96_FNCSEL96_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61125   GPIO_PINCFG96_FNCSEL96_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61126   GPIO_PINCFG96_FNCSEL96_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61127   GPIO_PINCFG96_FNCSEL96_CT96          = 6,     /*!< CT96 : Timer/Counter input or output; Selection of direction
61128                                                      is done via CTIMER register settings.                                     */
61129   GPIO_PINCFG96_FNCSEL96_NCE96         = 7,     /*!< NCE96 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61130                                                      CE_POLARITY field                                                         */
61131   GPIO_PINCFG96_FNCSEL96_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
61132   GPIO_PINCFG96_FNCSEL96_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61133   GPIO_PINCFG96_FNCSEL96_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61134   GPIO_PINCFG96_FNCSEL96_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61135   GPIO_PINCFG96_FNCSEL96_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61136   GPIO_PINCFG96_FNCSEL96_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61137   GPIO_PINCFG96_FNCSEL96_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61138   GPIO_PINCFG96_FNCSEL96_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61139 } GPIO_PINCFG96_FNCSEL96_Enum;
61140 
61141 /* =======================================================  PINCFG97  ======================================================== */
61142 /* ============================================  GPIO PINCFG97 NCEPOL97 [22..22]  ============================================ */
61143 typedef enum {                                  /*!< GPIO_PINCFG97_NCEPOL97                                                    */
61144   GPIO_PINCFG97_NCEPOL97_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61145   GPIO_PINCFG97_NCEPOL97_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61146 } GPIO_PINCFG97_NCEPOL97_Enum;
61147 
61148 /* ============================================  GPIO PINCFG97 NCESRC97 [16..21]  ============================================ */
61149 typedef enum {                                  /*!< GPIO_PINCFG97_NCESRC97                                                    */
61150   GPIO_PINCFG97_NCESRC97_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61151   GPIO_PINCFG97_NCESRC97_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61152   GPIO_PINCFG97_NCESRC97_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61153   GPIO_PINCFG97_NCESRC97_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61154   GPIO_PINCFG97_NCESRC97_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61155   GPIO_PINCFG97_NCESRC97_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61156   GPIO_PINCFG97_NCESRC97_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61157   GPIO_PINCFG97_NCESRC97_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61158   GPIO_PINCFG97_NCESRC97_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61159   GPIO_PINCFG97_NCESRC97_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61160   GPIO_PINCFG97_NCESRC97_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61161   GPIO_PINCFG97_NCESRC97_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61162   GPIO_PINCFG97_NCESRC97_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61163   GPIO_PINCFG97_NCESRC97_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61164   GPIO_PINCFG97_NCESRC97_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61165   GPIO_PINCFG97_NCESRC97_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61166   GPIO_PINCFG97_NCESRC97_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61167   GPIO_PINCFG97_NCESRC97_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61168   GPIO_PINCFG97_NCESRC97_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61169   GPIO_PINCFG97_NCESRC97_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61170   GPIO_PINCFG97_NCESRC97_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61171   GPIO_PINCFG97_NCESRC97_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61172   GPIO_PINCFG97_NCESRC97_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61173   GPIO_PINCFG97_NCESRC97_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61174   GPIO_PINCFG97_NCESRC97_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61175   GPIO_PINCFG97_NCESRC97_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61176   GPIO_PINCFG97_NCESRC97_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61177   GPIO_PINCFG97_NCESRC97_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61178   GPIO_PINCFG97_NCESRC97_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61179   GPIO_PINCFG97_NCESRC97_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61180   GPIO_PINCFG97_NCESRC97_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61181   GPIO_PINCFG97_NCESRC97_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61182   GPIO_PINCFG97_NCESRC97_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61183   GPIO_PINCFG97_NCESRC97_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61184   GPIO_PINCFG97_NCESRC97_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61185   GPIO_PINCFG97_NCESRC97_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61186   GPIO_PINCFG97_NCESRC97_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61187   GPIO_PINCFG97_NCESRC97_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61188   GPIO_PINCFG97_NCESRC97_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61189   GPIO_PINCFG97_NCESRC97_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61190   GPIO_PINCFG97_NCESRC97_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61191   GPIO_PINCFG97_NCESRC97_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61192   GPIO_PINCFG97_NCESRC97_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61193 } GPIO_PINCFG97_NCESRC97_Enum;
61194 
61195 /* ===========================================  GPIO PINCFG97 PULLCFG97 [13..15]  ============================================ */
61196 typedef enum {                                  /*!< GPIO_PINCFG97_PULLCFG97                                                   */
61197   GPIO_PINCFG97_PULLCFG97_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61198   GPIO_PINCFG97_PULLCFG97_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61199   GPIO_PINCFG97_PULLCFG97_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61200   GPIO_PINCFG97_PULLCFG97_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61201   GPIO_PINCFG97_PULLCFG97_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61202   GPIO_PINCFG97_PULLCFG97_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61203   GPIO_PINCFG97_PULLCFG97_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61204   GPIO_PINCFG97_PULLCFG97_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61205 } GPIO_PINCFG97_PULLCFG97_Enum;
61206 
61207 /* ==============================================  GPIO PINCFG97 DS97 [10..11]  ============================================== */
61208 typedef enum {                                  /*!< GPIO_PINCFG97_DS97                                                        */
61209   GPIO_PINCFG97_DS97_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61210   GPIO_PINCFG97_DS97_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61211 } GPIO_PINCFG97_DS97_Enum;
61212 
61213 /* =============================================  GPIO PINCFG97 OUTCFG97 [8..9]  ============================================= */
61214 typedef enum {                                  /*!< GPIO_PINCFG97_OUTCFG97                                                    */
61215   GPIO_PINCFG97_OUTCFG97_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61216   GPIO_PINCFG97_OUTCFG97_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61217                                                      and 1 values on pin.                                                      */
61218   GPIO_PINCFG97_OUTCFG97_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61219                                                      low, tristate otherwise.                                                  */
61220   GPIO_PINCFG97_OUTCFG97_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61221                                                      drive 0, 1 of HiZ on pin.                                                 */
61222 } GPIO_PINCFG97_OUTCFG97_Enum;
61223 
61224 /* =============================================  GPIO PINCFG97 IRPTEN97 [6..7]  ============================================= */
61225 typedef enum {                                  /*!< GPIO_PINCFG97_IRPTEN97                                                    */
61226   GPIO_PINCFG97_IRPTEN97_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61227   GPIO_PINCFG97_IRPTEN97_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61228                                                      on this GPIO                                                              */
61229   GPIO_PINCFG97_IRPTEN97_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61230                                                      on this GPIO                                                              */
61231   GPIO_PINCFG97_IRPTEN97_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61232                                                      GPIO                                                                      */
61233 } GPIO_PINCFG97_IRPTEN97_Enum;
61234 
61235 /* =============================================  GPIO PINCFG97 FNCSEL97 [0..3]  ============================================= */
61236 typedef enum {                                  /*!< GPIO_PINCFG97_FNCSEL97                                                    */
61237   GPIO_PINCFG97_FNCSEL97_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61238   GPIO_PINCFG97_FNCSEL97_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61239   GPIO_PINCFG97_FNCSEL97_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61240   GPIO_PINCFG97_FNCSEL97_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61241   GPIO_PINCFG97_FNCSEL97_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61242   GPIO_PINCFG97_FNCSEL97_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61243   GPIO_PINCFG97_FNCSEL97_CT97          = 6,     /*!< CT97 : Timer/Counter input or output; Selection of direction
61244                                                      is done via CTIMER register settings.                                     */
61245   GPIO_PINCFG97_FNCSEL97_NCE97         = 7,     /*!< NCE97 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61246                                                      CE_POLARITY field                                                         */
61247   GPIO_PINCFG97_FNCSEL97_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
61248   GPIO_PINCFG97_FNCSEL97_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61249   GPIO_PINCFG97_FNCSEL97_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61250   GPIO_PINCFG97_FNCSEL97_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61251   GPIO_PINCFG97_FNCSEL97_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61252   GPIO_PINCFG97_FNCSEL97_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61253   GPIO_PINCFG97_FNCSEL97_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61254   GPIO_PINCFG97_FNCSEL97_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61255 } GPIO_PINCFG97_FNCSEL97_Enum;
61256 
61257 /* =======================================================  PINCFG98  ======================================================== */
61258 /* ============================================  GPIO PINCFG98 NCEPOL98 [22..22]  ============================================ */
61259 typedef enum {                                  /*!< GPIO_PINCFG98_NCEPOL98                                                    */
61260   GPIO_PINCFG98_NCEPOL98_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61261   GPIO_PINCFG98_NCEPOL98_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61262 } GPIO_PINCFG98_NCEPOL98_Enum;
61263 
61264 /* ============================================  GPIO PINCFG98 NCESRC98 [16..21]  ============================================ */
61265 typedef enum {                                  /*!< GPIO_PINCFG98_NCESRC98                                                    */
61266   GPIO_PINCFG98_NCESRC98_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61267   GPIO_PINCFG98_NCESRC98_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61268   GPIO_PINCFG98_NCESRC98_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61269   GPIO_PINCFG98_NCESRC98_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61270   GPIO_PINCFG98_NCESRC98_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61271   GPIO_PINCFG98_NCESRC98_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61272   GPIO_PINCFG98_NCESRC98_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61273   GPIO_PINCFG98_NCESRC98_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61274   GPIO_PINCFG98_NCESRC98_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61275   GPIO_PINCFG98_NCESRC98_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61276   GPIO_PINCFG98_NCESRC98_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61277   GPIO_PINCFG98_NCESRC98_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61278   GPIO_PINCFG98_NCESRC98_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61279   GPIO_PINCFG98_NCESRC98_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61280   GPIO_PINCFG98_NCESRC98_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61281   GPIO_PINCFG98_NCESRC98_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61282   GPIO_PINCFG98_NCESRC98_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61283   GPIO_PINCFG98_NCESRC98_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61284   GPIO_PINCFG98_NCESRC98_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61285   GPIO_PINCFG98_NCESRC98_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61286   GPIO_PINCFG98_NCESRC98_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61287   GPIO_PINCFG98_NCESRC98_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61288   GPIO_PINCFG98_NCESRC98_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61289   GPIO_PINCFG98_NCESRC98_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61290   GPIO_PINCFG98_NCESRC98_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61291   GPIO_PINCFG98_NCESRC98_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61292   GPIO_PINCFG98_NCESRC98_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61293   GPIO_PINCFG98_NCESRC98_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61294   GPIO_PINCFG98_NCESRC98_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61295   GPIO_PINCFG98_NCESRC98_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61296   GPIO_PINCFG98_NCESRC98_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61297   GPIO_PINCFG98_NCESRC98_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61298   GPIO_PINCFG98_NCESRC98_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61299   GPIO_PINCFG98_NCESRC98_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61300   GPIO_PINCFG98_NCESRC98_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61301   GPIO_PINCFG98_NCESRC98_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61302   GPIO_PINCFG98_NCESRC98_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61303   GPIO_PINCFG98_NCESRC98_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61304   GPIO_PINCFG98_NCESRC98_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61305   GPIO_PINCFG98_NCESRC98_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61306   GPIO_PINCFG98_NCESRC98_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61307   GPIO_PINCFG98_NCESRC98_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61308   GPIO_PINCFG98_NCESRC98_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61309 } GPIO_PINCFG98_NCESRC98_Enum;
61310 
61311 /* ===========================================  GPIO PINCFG98 PULLCFG98 [13..15]  ============================================ */
61312 typedef enum {                                  /*!< GPIO_PINCFG98_PULLCFG98                                                   */
61313   GPIO_PINCFG98_PULLCFG98_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61314   GPIO_PINCFG98_PULLCFG98_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61315   GPIO_PINCFG98_PULLCFG98_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61316   GPIO_PINCFG98_PULLCFG98_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61317   GPIO_PINCFG98_PULLCFG98_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61318   GPIO_PINCFG98_PULLCFG98_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61319   GPIO_PINCFG98_PULLCFG98_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61320   GPIO_PINCFG98_PULLCFG98_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61321 } GPIO_PINCFG98_PULLCFG98_Enum;
61322 
61323 /* ==============================================  GPIO PINCFG98 DS98 [10..11]  ============================================== */
61324 typedef enum {                                  /*!< GPIO_PINCFG98_DS98                                                        */
61325   GPIO_PINCFG98_DS98_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61326   GPIO_PINCFG98_DS98_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61327 } GPIO_PINCFG98_DS98_Enum;
61328 
61329 /* =============================================  GPIO PINCFG98 OUTCFG98 [8..9]  ============================================= */
61330 typedef enum {                                  /*!< GPIO_PINCFG98_OUTCFG98                                                    */
61331   GPIO_PINCFG98_OUTCFG98_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61332   GPIO_PINCFG98_OUTCFG98_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61333                                                      and 1 values on pin.                                                      */
61334   GPIO_PINCFG98_OUTCFG98_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61335                                                      low, tristate otherwise.                                                  */
61336   GPIO_PINCFG98_OUTCFG98_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61337                                                      drive 0, 1 of HiZ on pin.                                                 */
61338 } GPIO_PINCFG98_OUTCFG98_Enum;
61339 
61340 /* =============================================  GPIO PINCFG98 IRPTEN98 [6..7]  ============================================= */
61341 typedef enum {                                  /*!< GPIO_PINCFG98_IRPTEN98                                                    */
61342   GPIO_PINCFG98_IRPTEN98_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61343   GPIO_PINCFG98_IRPTEN98_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61344                                                      on this GPIO                                                              */
61345   GPIO_PINCFG98_IRPTEN98_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61346                                                      on this GPIO                                                              */
61347   GPIO_PINCFG98_IRPTEN98_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61348                                                      GPIO                                                                      */
61349 } GPIO_PINCFG98_IRPTEN98_Enum;
61350 
61351 /* =============================================  GPIO PINCFG98 FNCSEL98 [0..3]  ============================================= */
61352 typedef enum {                                  /*!< GPIO_PINCFG98_FNCSEL98                                                    */
61353   GPIO_PINCFG98_FNCSEL98_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61354   GPIO_PINCFG98_FNCSEL98_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61355   GPIO_PINCFG98_FNCSEL98_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61356   GPIO_PINCFG98_FNCSEL98_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61357   GPIO_PINCFG98_FNCSEL98_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61358   GPIO_PINCFG98_FNCSEL98_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61359   GPIO_PINCFG98_FNCSEL98_CT98          = 6,     /*!< CT98 : Timer/Counter input or output; Selection of direction
61360                                                      is done via CTIMER register settings.                                     */
61361   GPIO_PINCFG98_FNCSEL98_NCE98         = 7,     /*!< NCE98 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61362                                                      CE_POLARITY field                                                         */
61363   GPIO_PINCFG98_FNCSEL98_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
61364   GPIO_PINCFG98_FNCSEL98_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61365   GPIO_PINCFG98_FNCSEL98_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61366   GPIO_PINCFG98_FNCSEL98_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61367   GPIO_PINCFG98_FNCSEL98_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61368   GPIO_PINCFG98_FNCSEL98_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61369   GPIO_PINCFG98_FNCSEL98_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61370   GPIO_PINCFG98_FNCSEL98_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61371 } GPIO_PINCFG98_FNCSEL98_Enum;
61372 
61373 /* =======================================================  PINCFG99  ======================================================== */
61374 /* ============================================  GPIO PINCFG99 NCEPOL99 [22..22]  ============================================ */
61375 typedef enum {                                  /*!< GPIO_PINCFG99_NCEPOL99                                                    */
61376   GPIO_PINCFG99_NCEPOL99_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61377   GPIO_PINCFG99_NCEPOL99_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61378 } GPIO_PINCFG99_NCEPOL99_Enum;
61379 
61380 /* ============================================  GPIO PINCFG99 NCESRC99 [16..21]  ============================================ */
61381 typedef enum {                                  /*!< GPIO_PINCFG99_NCESRC99                                                    */
61382   GPIO_PINCFG99_NCESRC99_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61383   GPIO_PINCFG99_NCESRC99_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61384   GPIO_PINCFG99_NCESRC99_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61385   GPIO_PINCFG99_NCESRC99_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61386   GPIO_PINCFG99_NCESRC99_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61387   GPIO_PINCFG99_NCESRC99_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61388   GPIO_PINCFG99_NCESRC99_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61389   GPIO_PINCFG99_NCESRC99_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61390   GPIO_PINCFG99_NCESRC99_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61391   GPIO_PINCFG99_NCESRC99_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61392   GPIO_PINCFG99_NCESRC99_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61393   GPIO_PINCFG99_NCESRC99_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61394   GPIO_PINCFG99_NCESRC99_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61395   GPIO_PINCFG99_NCESRC99_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61396   GPIO_PINCFG99_NCESRC99_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61397   GPIO_PINCFG99_NCESRC99_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61398   GPIO_PINCFG99_NCESRC99_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61399   GPIO_PINCFG99_NCESRC99_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61400   GPIO_PINCFG99_NCESRC99_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61401   GPIO_PINCFG99_NCESRC99_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61402   GPIO_PINCFG99_NCESRC99_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61403   GPIO_PINCFG99_NCESRC99_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61404   GPIO_PINCFG99_NCESRC99_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61405   GPIO_PINCFG99_NCESRC99_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61406   GPIO_PINCFG99_NCESRC99_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61407   GPIO_PINCFG99_NCESRC99_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61408   GPIO_PINCFG99_NCESRC99_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61409   GPIO_PINCFG99_NCESRC99_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61410   GPIO_PINCFG99_NCESRC99_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61411   GPIO_PINCFG99_NCESRC99_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61412   GPIO_PINCFG99_NCESRC99_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61413   GPIO_PINCFG99_NCESRC99_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61414   GPIO_PINCFG99_NCESRC99_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61415   GPIO_PINCFG99_NCESRC99_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61416   GPIO_PINCFG99_NCESRC99_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61417   GPIO_PINCFG99_NCESRC99_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61418   GPIO_PINCFG99_NCESRC99_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61419   GPIO_PINCFG99_NCESRC99_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61420   GPIO_PINCFG99_NCESRC99_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61421   GPIO_PINCFG99_NCESRC99_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61422   GPIO_PINCFG99_NCESRC99_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61423   GPIO_PINCFG99_NCESRC99_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61424   GPIO_PINCFG99_NCESRC99_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61425 } GPIO_PINCFG99_NCESRC99_Enum;
61426 
61427 /* ===========================================  GPIO PINCFG99 PULLCFG99 [13..15]  ============================================ */
61428 typedef enum {                                  /*!< GPIO_PINCFG99_PULLCFG99                                                   */
61429   GPIO_PINCFG99_PULLCFG99_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61430   GPIO_PINCFG99_PULLCFG99_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61431   GPIO_PINCFG99_PULLCFG99_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61432   GPIO_PINCFG99_PULLCFG99_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61433   GPIO_PINCFG99_PULLCFG99_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61434   GPIO_PINCFG99_PULLCFG99_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61435   GPIO_PINCFG99_PULLCFG99_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61436   GPIO_PINCFG99_PULLCFG99_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61437 } GPIO_PINCFG99_PULLCFG99_Enum;
61438 
61439 /* ==============================================  GPIO PINCFG99 DS99 [10..11]  ============================================== */
61440 typedef enum {                                  /*!< GPIO_PINCFG99_DS99                                                        */
61441   GPIO_PINCFG99_DS99_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61442   GPIO_PINCFG99_DS99_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61443 } GPIO_PINCFG99_DS99_Enum;
61444 
61445 /* =============================================  GPIO PINCFG99 OUTCFG99 [8..9]  ============================================= */
61446 typedef enum {                                  /*!< GPIO_PINCFG99_OUTCFG99                                                    */
61447   GPIO_PINCFG99_OUTCFG99_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61448   GPIO_PINCFG99_OUTCFG99_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61449                                                      and 1 values on pin.                                                      */
61450   GPIO_PINCFG99_OUTCFG99_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61451                                                      low, tristate otherwise.                                                  */
61452   GPIO_PINCFG99_OUTCFG99_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61453                                                      drive 0, 1 of HiZ on pin.                                                 */
61454 } GPIO_PINCFG99_OUTCFG99_Enum;
61455 
61456 /* =============================================  GPIO PINCFG99 IRPTEN99 [6..7]  ============================================= */
61457 typedef enum {                                  /*!< GPIO_PINCFG99_IRPTEN99                                                    */
61458   GPIO_PINCFG99_IRPTEN99_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61459   GPIO_PINCFG99_IRPTEN99_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61460                                                      on this GPIO                                                              */
61461   GPIO_PINCFG99_IRPTEN99_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61462                                                      on this GPIO                                                              */
61463   GPIO_PINCFG99_IRPTEN99_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61464                                                      GPIO                                                                      */
61465 } GPIO_PINCFG99_IRPTEN99_Enum;
61466 
61467 /* =============================================  GPIO PINCFG99 FNCSEL99 [0..3]  ============================================= */
61468 typedef enum {                                  /*!< GPIO_PINCFG99_FNCSEL99                                                    */
61469   GPIO_PINCFG99_FNCSEL99_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61470   GPIO_PINCFG99_FNCSEL99_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61471   GPIO_PINCFG99_FNCSEL99_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61472   GPIO_PINCFG99_FNCSEL99_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61473   GPIO_PINCFG99_FNCSEL99_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61474   GPIO_PINCFG99_FNCSEL99_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61475   GPIO_PINCFG99_FNCSEL99_CT99          = 6,     /*!< CT99 : Timer/Counter input or output; Selection of direction
61476                                                      is done via CTIMER register settings.                                     */
61477   GPIO_PINCFG99_FNCSEL99_NCE99         = 7,     /*!< NCE99 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61478                                                      CE_POLARITY field                                                         */
61479   GPIO_PINCFG99_FNCSEL99_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
61480   GPIO_PINCFG99_FNCSEL99_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61481   GPIO_PINCFG99_FNCSEL99_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61482   GPIO_PINCFG99_FNCSEL99_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61483   GPIO_PINCFG99_FNCSEL99_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61484   GPIO_PINCFG99_FNCSEL99_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61485   GPIO_PINCFG99_FNCSEL99_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61486   GPIO_PINCFG99_FNCSEL99_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61487 } GPIO_PINCFG99_FNCSEL99_Enum;
61488 
61489 /* =======================================================  PINCFG100  ======================================================= */
61490 /* ===========================================  GPIO PINCFG100 NCEPOL100 [22..22]  =========================================== */
61491 typedef enum {                                  /*!< GPIO_PINCFG100_NCEPOL100                                                  */
61492   GPIO_PINCFG100_NCEPOL100_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
61493   GPIO_PINCFG100_NCEPOL100_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
61494 } GPIO_PINCFG100_NCEPOL100_Enum;
61495 
61496 /* ===========================================  GPIO PINCFG100 NCESRC100 [16..21]  =========================================== */
61497 typedef enum {                                  /*!< GPIO_PINCFG100_NCESRC100                                                  */
61498   GPIO_PINCFG100_NCESRC100_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61499   GPIO_PINCFG100_NCESRC100_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61500   GPIO_PINCFG100_NCESRC100_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61501   GPIO_PINCFG100_NCESRC100_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61502   GPIO_PINCFG100_NCESRC100_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61503   GPIO_PINCFG100_NCESRC100_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61504   GPIO_PINCFG100_NCESRC100_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61505   GPIO_PINCFG100_NCESRC100_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61506   GPIO_PINCFG100_NCESRC100_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61507   GPIO_PINCFG100_NCESRC100_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61508   GPIO_PINCFG100_NCESRC100_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61509   GPIO_PINCFG100_NCESRC100_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61510   GPIO_PINCFG100_NCESRC100_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61511   GPIO_PINCFG100_NCESRC100_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61512   GPIO_PINCFG100_NCESRC100_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61513   GPIO_PINCFG100_NCESRC100_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61514   GPIO_PINCFG100_NCESRC100_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61515   GPIO_PINCFG100_NCESRC100_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61516   GPIO_PINCFG100_NCESRC100_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61517   GPIO_PINCFG100_NCESRC100_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61518   GPIO_PINCFG100_NCESRC100_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61519   GPIO_PINCFG100_NCESRC100_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61520   GPIO_PINCFG100_NCESRC100_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61521   GPIO_PINCFG100_NCESRC100_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61522   GPIO_PINCFG100_NCESRC100_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61523   GPIO_PINCFG100_NCESRC100_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61524   GPIO_PINCFG100_NCESRC100_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61525   GPIO_PINCFG100_NCESRC100_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61526   GPIO_PINCFG100_NCESRC100_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61527   GPIO_PINCFG100_NCESRC100_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61528   GPIO_PINCFG100_NCESRC100_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61529   GPIO_PINCFG100_NCESRC100_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61530   GPIO_PINCFG100_NCESRC100_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61531   GPIO_PINCFG100_NCESRC100_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61532   GPIO_PINCFG100_NCESRC100_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61533   GPIO_PINCFG100_NCESRC100_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61534   GPIO_PINCFG100_NCESRC100_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61535   GPIO_PINCFG100_NCESRC100_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61536   GPIO_PINCFG100_NCESRC100_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61537   GPIO_PINCFG100_NCESRC100_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61538   GPIO_PINCFG100_NCESRC100_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61539   GPIO_PINCFG100_NCESRC100_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61540   GPIO_PINCFG100_NCESRC100_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
61541 } GPIO_PINCFG100_NCESRC100_Enum;
61542 
61543 /* ==========================================  GPIO PINCFG100 PULLCFG100 [13..15]  =========================================== */
61544 typedef enum {                                  /*!< GPIO_PINCFG100_PULLCFG100                                                 */
61545   GPIO_PINCFG100_PULLCFG100_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61546   GPIO_PINCFG100_PULLCFG100_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61547   GPIO_PINCFG100_PULLCFG100_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61548   GPIO_PINCFG100_PULLCFG100_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61549   GPIO_PINCFG100_PULLCFG100_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
61550   GPIO_PINCFG100_PULLCFG100_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
61551   GPIO_PINCFG100_PULLCFG100_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
61552   GPIO_PINCFG100_PULLCFG100_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
61553 } GPIO_PINCFG100_PULLCFG100_Enum;
61554 
61555 /* =============================================  GPIO PINCFG100 DS100 [10..11]  ============================================= */
61556 typedef enum {                                  /*!< GPIO_PINCFG100_DS100                                                      */
61557   GPIO_PINCFG100_DS100_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61558   GPIO_PINCFG100_DS100_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61559 } GPIO_PINCFG100_DS100_Enum;
61560 
61561 /* ============================================  GPIO PINCFG100 OUTCFG100 [8..9]  ============================================ */
61562 typedef enum {                                  /*!< GPIO_PINCFG100_OUTCFG100                                                  */
61563   GPIO_PINCFG100_OUTCFG100_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
61564   GPIO_PINCFG100_OUTCFG100_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61565                                                      and 1 values on pin.                                                      */
61566   GPIO_PINCFG100_OUTCFG100_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61567                                                      low, tristate otherwise.                                                  */
61568   GPIO_PINCFG100_OUTCFG100_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61569                                                      drive 0, 1 of HiZ on pin.                                                 */
61570 } GPIO_PINCFG100_OUTCFG100_Enum;
61571 
61572 /* ============================================  GPIO PINCFG100 IRPTEN100 [6..7]  ============================================ */
61573 typedef enum {                                  /*!< GPIO_PINCFG100_IRPTEN100                                                  */
61574   GPIO_PINCFG100_IRPTEN100_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61575   GPIO_PINCFG100_IRPTEN100_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61576                                                      on this GPIO                                                              */
61577   GPIO_PINCFG100_IRPTEN100_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61578                                                      on this GPIO                                                              */
61579   GPIO_PINCFG100_IRPTEN100_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61580                                                      GPIO                                                                      */
61581 } GPIO_PINCFG100_IRPTEN100_Enum;
61582 
61583 /* ============================================  GPIO PINCFG100 FNCSEL100 [0..3]  ============================================ */
61584 typedef enum {                                  /*!< GPIO_PINCFG100_FNCSEL100                                                  */
61585   GPIO_PINCFG100_FNCSEL100_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61586   GPIO_PINCFG100_FNCSEL100_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61587   GPIO_PINCFG100_FNCSEL100_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61588   GPIO_PINCFG100_FNCSEL100_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
61589   GPIO_PINCFG100_FNCSEL100_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61590   GPIO_PINCFG100_FNCSEL100_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61591   GPIO_PINCFG100_FNCSEL100_CT100       = 6,     /*!< CT100 : Timer/Counter input or output; Selection of direction
61592                                                      is done via CTIMER register settings.                                     */
61593   GPIO_PINCFG100_FNCSEL100_NCE100      = 7,     /*!< NCE100 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61594                                                      CE_POLARITY field                                                         */
61595   GPIO_PINCFG100_FNCSEL100_OBSBUS4     = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
61596   GPIO_PINCFG100_FNCSEL100_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61597   GPIO_PINCFG100_FNCSEL100_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61598   GPIO_PINCFG100_FNCSEL100_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
61599   GPIO_PINCFG100_FNCSEL100_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61600   GPIO_PINCFG100_FNCSEL100_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61601   GPIO_PINCFG100_FNCSEL100_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61602   GPIO_PINCFG100_FNCSEL100_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61603 } GPIO_PINCFG100_FNCSEL100_Enum;
61604 
61605 /* =======================================================  PINCFG101  ======================================================= */
61606 /* ===========================================  GPIO PINCFG101 NCEPOL101 [22..22]  =========================================== */
61607 typedef enum {                                  /*!< GPIO_PINCFG101_NCEPOL101                                                  */
61608   GPIO_PINCFG101_NCEPOL101_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
61609   GPIO_PINCFG101_NCEPOL101_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
61610 } GPIO_PINCFG101_NCEPOL101_Enum;
61611 
61612 /* ===========================================  GPIO PINCFG101 NCESRC101 [16..21]  =========================================== */
61613 typedef enum {                                  /*!< GPIO_PINCFG101_NCESRC101                                                  */
61614   GPIO_PINCFG101_NCESRC101_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61615   GPIO_PINCFG101_NCESRC101_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61616   GPIO_PINCFG101_NCESRC101_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61617   GPIO_PINCFG101_NCESRC101_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61618   GPIO_PINCFG101_NCESRC101_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61619   GPIO_PINCFG101_NCESRC101_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61620   GPIO_PINCFG101_NCESRC101_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61621   GPIO_PINCFG101_NCESRC101_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61622   GPIO_PINCFG101_NCESRC101_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61623   GPIO_PINCFG101_NCESRC101_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61624   GPIO_PINCFG101_NCESRC101_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61625   GPIO_PINCFG101_NCESRC101_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61626   GPIO_PINCFG101_NCESRC101_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61627   GPIO_PINCFG101_NCESRC101_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61628   GPIO_PINCFG101_NCESRC101_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61629   GPIO_PINCFG101_NCESRC101_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61630   GPIO_PINCFG101_NCESRC101_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61631   GPIO_PINCFG101_NCESRC101_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61632   GPIO_PINCFG101_NCESRC101_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61633   GPIO_PINCFG101_NCESRC101_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61634   GPIO_PINCFG101_NCESRC101_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61635   GPIO_PINCFG101_NCESRC101_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61636   GPIO_PINCFG101_NCESRC101_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61637   GPIO_PINCFG101_NCESRC101_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61638   GPIO_PINCFG101_NCESRC101_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61639   GPIO_PINCFG101_NCESRC101_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61640   GPIO_PINCFG101_NCESRC101_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61641   GPIO_PINCFG101_NCESRC101_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61642   GPIO_PINCFG101_NCESRC101_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61643   GPIO_PINCFG101_NCESRC101_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61644   GPIO_PINCFG101_NCESRC101_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61645   GPIO_PINCFG101_NCESRC101_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61646   GPIO_PINCFG101_NCESRC101_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61647   GPIO_PINCFG101_NCESRC101_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61648   GPIO_PINCFG101_NCESRC101_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61649   GPIO_PINCFG101_NCESRC101_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61650   GPIO_PINCFG101_NCESRC101_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61651   GPIO_PINCFG101_NCESRC101_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61652   GPIO_PINCFG101_NCESRC101_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61653   GPIO_PINCFG101_NCESRC101_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61654   GPIO_PINCFG101_NCESRC101_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61655   GPIO_PINCFG101_NCESRC101_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61656   GPIO_PINCFG101_NCESRC101_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
61657 } GPIO_PINCFG101_NCESRC101_Enum;
61658 
61659 /* ==========================================  GPIO PINCFG101 PULLCFG101 [13..15]  =========================================== */
61660 typedef enum {                                  /*!< GPIO_PINCFG101_PULLCFG101                                                 */
61661   GPIO_PINCFG101_PULLCFG101_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61662   GPIO_PINCFG101_PULLCFG101_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61663   GPIO_PINCFG101_PULLCFG101_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61664   GPIO_PINCFG101_PULLCFG101_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61665   GPIO_PINCFG101_PULLCFG101_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
61666   GPIO_PINCFG101_PULLCFG101_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
61667   GPIO_PINCFG101_PULLCFG101_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
61668   GPIO_PINCFG101_PULLCFG101_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
61669 } GPIO_PINCFG101_PULLCFG101_Enum;
61670 
61671 /* =============================================  GPIO PINCFG101 DS101 [10..11]  ============================================= */
61672 typedef enum {                                  /*!< GPIO_PINCFG101_DS101                                                      */
61673   GPIO_PINCFG101_DS101_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61674   GPIO_PINCFG101_DS101_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61675 } GPIO_PINCFG101_DS101_Enum;
61676 
61677 /* ============================================  GPIO PINCFG101 OUTCFG101 [8..9]  ============================================ */
61678 typedef enum {                                  /*!< GPIO_PINCFG101_OUTCFG101                                                  */
61679   GPIO_PINCFG101_OUTCFG101_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
61680   GPIO_PINCFG101_OUTCFG101_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61681                                                      and 1 values on pin.                                                      */
61682   GPIO_PINCFG101_OUTCFG101_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61683                                                      low, tristate otherwise.                                                  */
61684   GPIO_PINCFG101_OUTCFG101_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61685                                                      drive 0, 1 of HiZ on pin.                                                 */
61686 } GPIO_PINCFG101_OUTCFG101_Enum;
61687 
61688 /* ============================================  GPIO PINCFG101 IRPTEN101 [6..7]  ============================================ */
61689 typedef enum {                                  /*!< GPIO_PINCFG101_IRPTEN101                                                  */
61690   GPIO_PINCFG101_IRPTEN101_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61691   GPIO_PINCFG101_IRPTEN101_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61692                                                      on this GPIO                                                              */
61693   GPIO_PINCFG101_IRPTEN101_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61694                                                      on this GPIO                                                              */
61695   GPIO_PINCFG101_IRPTEN101_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61696                                                      GPIO                                                                      */
61697 } GPIO_PINCFG101_IRPTEN101_Enum;
61698 
61699 /* ============================================  GPIO PINCFG101 FNCSEL101 [0..3]  ============================================ */
61700 typedef enum {                                  /*!< GPIO_PINCFG101_FNCSEL101                                                  */
61701   GPIO_PINCFG101_FNCSEL101_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61702   GPIO_PINCFG101_FNCSEL101_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61703   GPIO_PINCFG101_FNCSEL101_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61704   GPIO_PINCFG101_FNCSEL101_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
61705   GPIO_PINCFG101_FNCSEL101_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61706   GPIO_PINCFG101_FNCSEL101_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61707   GPIO_PINCFG101_FNCSEL101_CT101       = 6,     /*!< CT101 : Timer/Counter input or output; Selection of direction
61708                                                      is done via CTIMER register settings.                                     */
61709   GPIO_PINCFG101_FNCSEL101_NCE101      = 7,     /*!< NCE101 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61710                                                      CE_POLARITY field                                                         */
61711   GPIO_PINCFG101_FNCSEL101_OBSBUS5     = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
61712   GPIO_PINCFG101_FNCSEL101_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61713   GPIO_PINCFG101_FNCSEL101_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61714   GPIO_PINCFG101_FNCSEL101_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
61715   GPIO_PINCFG101_FNCSEL101_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61716   GPIO_PINCFG101_FNCSEL101_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61717   GPIO_PINCFG101_FNCSEL101_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61718   GPIO_PINCFG101_FNCSEL101_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61719 } GPIO_PINCFG101_FNCSEL101_Enum;
61720 
61721 /* =======================================================  PINCFG102  ======================================================= */
61722 /* ===========================================  GPIO PINCFG102 NCEPOL102 [22..22]  =========================================== */
61723 typedef enum {                                  /*!< GPIO_PINCFG102_NCEPOL102                                                  */
61724   GPIO_PINCFG102_NCEPOL102_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
61725   GPIO_PINCFG102_NCEPOL102_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
61726 } GPIO_PINCFG102_NCEPOL102_Enum;
61727 
61728 /* ===========================================  GPIO PINCFG102 NCESRC102 [16..21]  =========================================== */
61729 typedef enum {                                  /*!< GPIO_PINCFG102_NCESRC102                                                  */
61730   GPIO_PINCFG102_NCESRC102_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61731   GPIO_PINCFG102_NCESRC102_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61732   GPIO_PINCFG102_NCESRC102_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61733   GPIO_PINCFG102_NCESRC102_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61734   GPIO_PINCFG102_NCESRC102_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61735   GPIO_PINCFG102_NCESRC102_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61736   GPIO_PINCFG102_NCESRC102_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61737   GPIO_PINCFG102_NCESRC102_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61738   GPIO_PINCFG102_NCESRC102_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61739   GPIO_PINCFG102_NCESRC102_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61740   GPIO_PINCFG102_NCESRC102_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61741   GPIO_PINCFG102_NCESRC102_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61742   GPIO_PINCFG102_NCESRC102_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61743   GPIO_PINCFG102_NCESRC102_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61744   GPIO_PINCFG102_NCESRC102_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61745   GPIO_PINCFG102_NCESRC102_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61746   GPIO_PINCFG102_NCESRC102_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61747   GPIO_PINCFG102_NCESRC102_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61748   GPIO_PINCFG102_NCESRC102_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61749   GPIO_PINCFG102_NCESRC102_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61750   GPIO_PINCFG102_NCESRC102_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61751   GPIO_PINCFG102_NCESRC102_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61752   GPIO_PINCFG102_NCESRC102_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61753   GPIO_PINCFG102_NCESRC102_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61754   GPIO_PINCFG102_NCESRC102_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61755   GPIO_PINCFG102_NCESRC102_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61756   GPIO_PINCFG102_NCESRC102_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61757   GPIO_PINCFG102_NCESRC102_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61758   GPIO_PINCFG102_NCESRC102_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61759   GPIO_PINCFG102_NCESRC102_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61760   GPIO_PINCFG102_NCESRC102_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61761   GPIO_PINCFG102_NCESRC102_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61762   GPIO_PINCFG102_NCESRC102_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61763   GPIO_PINCFG102_NCESRC102_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61764   GPIO_PINCFG102_NCESRC102_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61765   GPIO_PINCFG102_NCESRC102_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61766   GPIO_PINCFG102_NCESRC102_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61767   GPIO_PINCFG102_NCESRC102_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61768   GPIO_PINCFG102_NCESRC102_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61769   GPIO_PINCFG102_NCESRC102_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61770   GPIO_PINCFG102_NCESRC102_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61771   GPIO_PINCFG102_NCESRC102_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61772   GPIO_PINCFG102_NCESRC102_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
61773 } GPIO_PINCFG102_NCESRC102_Enum;
61774 
61775 /* ==========================================  GPIO PINCFG102 PULLCFG102 [13..15]  =========================================== */
61776 typedef enum {                                  /*!< GPIO_PINCFG102_PULLCFG102                                                 */
61777   GPIO_PINCFG102_PULLCFG102_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61778   GPIO_PINCFG102_PULLCFG102_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61779   GPIO_PINCFG102_PULLCFG102_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61780   GPIO_PINCFG102_PULLCFG102_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61781   GPIO_PINCFG102_PULLCFG102_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
61782   GPIO_PINCFG102_PULLCFG102_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
61783   GPIO_PINCFG102_PULLCFG102_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
61784   GPIO_PINCFG102_PULLCFG102_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
61785 } GPIO_PINCFG102_PULLCFG102_Enum;
61786 
61787 /* =============================================  GPIO PINCFG102 DS102 [10..11]  ============================================= */
61788 typedef enum {                                  /*!< GPIO_PINCFG102_DS102                                                      */
61789   GPIO_PINCFG102_DS102_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61790   GPIO_PINCFG102_DS102_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61791 } GPIO_PINCFG102_DS102_Enum;
61792 
61793 /* ============================================  GPIO PINCFG102 OUTCFG102 [8..9]  ============================================ */
61794 typedef enum {                                  /*!< GPIO_PINCFG102_OUTCFG102                                                  */
61795   GPIO_PINCFG102_OUTCFG102_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
61796   GPIO_PINCFG102_OUTCFG102_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61797                                                      and 1 values on pin.                                                      */
61798   GPIO_PINCFG102_OUTCFG102_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61799                                                      low, tristate otherwise.                                                  */
61800   GPIO_PINCFG102_OUTCFG102_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61801                                                      drive 0, 1 of HiZ on pin.                                                 */
61802 } GPIO_PINCFG102_OUTCFG102_Enum;
61803 
61804 /* ============================================  GPIO PINCFG102 IRPTEN102 [6..7]  ============================================ */
61805 typedef enum {                                  /*!< GPIO_PINCFG102_IRPTEN102                                                  */
61806   GPIO_PINCFG102_IRPTEN102_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61807   GPIO_PINCFG102_IRPTEN102_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61808                                                      on this GPIO                                                              */
61809   GPIO_PINCFG102_IRPTEN102_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61810                                                      on this GPIO                                                              */
61811   GPIO_PINCFG102_IRPTEN102_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61812                                                      GPIO                                                                      */
61813 } GPIO_PINCFG102_IRPTEN102_Enum;
61814 
61815 /* ============================================  GPIO PINCFG102 FNCSEL102 [0..3]  ============================================ */
61816 typedef enum {                                  /*!< GPIO_PINCFG102_FNCSEL102                                                  */
61817   GPIO_PINCFG102_FNCSEL102_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61818   GPIO_PINCFG102_FNCSEL102_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61819   GPIO_PINCFG102_FNCSEL102_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61820   GPIO_PINCFG102_FNCSEL102_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
61821   GPIO_PINCFG102_FNCSEL102_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61822   GPIO_PINCFG102_FNCSEL102_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61823   GPIO_PINCFG102_FNCSEL102_CT102       = 6,     /*!< CT102 : Timer/Counter input or output; Selection of direction
61824                                                      is done via CTIMER register settings.                                     */
61825   GPIO_PINCFG102_FNCSEL102_NCE102      = 7,     /*!< NCE102 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61826                                                      CE_POLARITY field                                                         */
61827   GPIO_PINCFG102_FNCSEL102_OBSBUS6     = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
61828   GPIO_PINCFG102_FNCSEL102_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61829   GPIO_PINCFG102_FNCSEL102_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61830   GPIO_PINCFG102_FNCSEL102_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
61831   GPIO_PINCFG102_FNCSEL102_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61832   GPIO_PINCFG102_FNCSEL102_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61833   GPIO_PINCFG102_FNCSEL102_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61834   GPIO_PINCFG102_FNCSEL102_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61835 } GPIO_PINCFG102_FNCSEL102_Enum;
61836 
61837 /* =======================================================  PINCFG103  ======================================================= */
61838 /* ===========================================  GPIO PINCFG103 NCEPOL103 [22..22]  =========================================== */
61839 typedef enum {                                  /*!< GPIO_PINCFG103_NCEPOL103                                                  */
61840   GPIO_PINCFG103_NCEPOL103_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
61841   GPIO_PINCFG103_NCEPOL103_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
61842 } GPIO_PINCFG103_NCEPOL103_Enum;
61843 
61844 /* ===========================================  GPIO PINCFG103 NCESRC103 [16..21]  =========================================== */
61845 typedef enum {                                  /*!< GPIO_PINCFG103_NCESRC103                                                  */
61846   GPIO_PINCFG103_NCESRC103_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61847   GPIO_PINCFG103_NCESRC103_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61848   GPIO_PINCFG103_NCESRC103_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61849   GPIO_PINCFG103_NCESRC103_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61850   GPIO_PINCFG103_NCESRC103_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61851   GPIO_PINCFG103_NCESRC103_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61852   GPIO_PINCFG103_NCESRC103_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61853   GPIO_PINCFG103_NCESRC103_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61854   GPIO_PINCFG103_NCESRC103_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61855   GPIO_PINCFG103_NCESRC103_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61856   GPIO_PINCFG103_NCESRC103_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61857   GPIO_PINCFG103_NCESRC103_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61858   GPIO_PINCFG103_NCESRC103_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61859   GPIO_PINCFG103_NCESRC103_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61860   GPIO_PINCFG103_NCESRC103_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61861   GPIO_PINCFG103_NCESRC103_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61862   GPIO_PINCFG103_NCESRC103_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61863   GPIO_PINCFG103_NCESRC103_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61864   GPIO_PINCFG103_NCESRC103_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61865   GPIO_PINCFG103_NCESRC103_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61866   GPIO_PINCFG103_NCESRC103_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61867   GPIO_PINCFG103_NCESRC103_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61868   GPIO_PINCFG103_NCESRC103_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61869   GPIO_PINCFG103_NCESRC103_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61870   GPIO_PINCFG103_NCESRC103_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61871   GPIO_PINCFG103_NCESRC103_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61872   GPIO_PINCFG103_NCESRC103_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61873   GPIO_PINCFG103_NCESRC103_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61874   GPIO_PINCFG103_NCESRC103_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61875   GPIO_PINCFG103_NCESRC103_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61876   GPIO_PINCFG103_NCESRC103_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61877   GPIO_PINCFG103_NCESRC103_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61878   GPIO_PINCFG103_NCESRC103_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61879   GPIO_PINCFG103_NCESRC103_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61880   GPIO_PINCFG103_NCESRC103_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61881   GPIO_PINCFG103_NCESRC103_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61882   GPIO_PINCFG103_NCESRC103_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61883   GPIO_PINCFG103_NCESRC103_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61884   GPIO_PINCFG103_NCESRC103_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61885   GPIO_PINCFG103_NCESRC103_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61886   GPIO_PINCFG103_NCESRC103_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61887   GPIO_PINCFG103_NCESRC103_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61888   GPIO_PINCFG103_NCESRC103_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
61889 } GPIO_PINCFG103_NCESRC103_Enum;
61890 
61891 /* ==========================================  GPIO PINCFG103 PULLCFG103 [13..15]  =========================================== */
61892 typedef enum {                                  /*!< GPIO_PINCFG103_PULLCFG103                                                 */
61893   GPIO_PINCFG103_PULLCFG103_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61894   GPIO_PINCFG103_PULLCFG103_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61895   GPIO_PINCFG103_PULLCFG103_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61896   GPIO_PINCFG103_PULLCFG103_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61897   GPIO_PINCFG103_PULLCFG103_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
61898   GPIO_PINCFG103_PULLCFG103_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
61899   GPIO_PINCFG103_PULLCFG103_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
61900   GPIO_PINCFG103_PULLCFG103_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
61901 } GPIO_PINCFG103_PULLCFG103_Enum;
61902 
61903 /* =============================================  GPIO PINCFG103 DS103 [10..11]  ============================================= */
61904 typedef enum {                                  /*!< GPIO_PINCFG103_DS103                                                      */
61905   GPIO_PINCFG103_DS103_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61906   GPIO_PINCFG103_DS103_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61907 } GPIO_PINCFG103_DS103_Enum;
61908 
61909 /* ============================================  GPIO PINCFG103 OUTCFG103 [8..9]  ============================================ */
61910 typedef enum {                                  /*!< GPIO_PINCFG103_OUTCFG103                                                  */
61911   GPIO_PINCFG103_OUTCFG103_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
61912   GPIO_PINCFG103_OUTCFG103_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61913                                                      and 1 values on pin.                                                      */
61914   GPIO_PINCFG103_OUTCFG103_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61915                                                      low, tristate otherwise.                                                  */
61916   GPIO_PINCFG103_OUTCFG103_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61917                                                      drive 0, 1 of HiZ on pin.                                                 */
61918 } GPIO_PINCFG103_OUTCFG103_Enum;
61919 
61920 /* ============================================  GPIO PINCFG103 IRPTEN103 [6..7]  ============================================ */
61921 typedef enum {                                  /*!< GPIO_PINCFG103_IRPTEN103                                                  */
61922   GPIO_PINCFG103_IRPTEN103_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61923   GPIO_PINCFG103_IRPTEN103_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61924                                                      on this GPIO                                                              */
61925   GPIO_PINCFG103_IRPTEN103_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61926                                                      on this GPIO                                                              */
61927   GPIO_PINCFG103_IRPTEN103_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61928                                                      GPIO                                                                      */
61929 } GPIO_PINCFG103_IRPTEN103_Enum;
61930 
61931 /* ============================================  GPIO PINCFG103 FNCSEL103 [0..3]  ============================================ */
61932 typedef enum {                                  /*!< GPIO_PINCFG103_FNCSEL103                                                  */
61933   GPIO_PINCFG103_FNCSEL103_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61934   GPIO_PINCFG103_FNCSEL103_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61935   GPIO_PINCFG103_FNCSEL103_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61936   GPIO_PINCFG103_FNCSEL103_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
61937   GPIO_PINCFG103_FNCSEL103_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61938   GPIO_PINCFG103_FNCSEL103_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61939   GPIO_PINCFG103_FNCSEL103_CT103       = 6,     /*!< CT103 : Timer/Counter input or output; Selection of direction
61940                                                      is done via CTIMER register settings.                                     */
61941   GPIO_PINCFG103_FNCSEL103_NCE103      = 7,     /*!< NCE103 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61942                                                      CE_POLARITY field                                                         */
61943   GPIO_PINCFG103_FNCSEL103_OBSBUS7     = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
61944   GPIO_PINCFG103_FNCSEL103_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61945   GPIO_PINCFG103_FNCSEL103_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61946   GPIO_PINCFG103_FNCSEL103_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
61947   GPIO_PINCFG103_FNCSEL103_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61948   GPIO_PINCFG103_FNCSEL103_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61949   GPIO_PINCFG103_FNCSEL103_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61950   GPIO_PINCFG103_FNCSEL103_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61951 } GPIO_PINCFG103_FNCSEL103_Enum;
61952 
61953 /* =======================================================  PINCFG104  ======================================================= */
61954 /* ===========================================  GPIO PINCFG104 NCEPOL104 [22..22]  =========================================== */
61955 typedef enum {                                  /*!< GPIO_PINCFG104_NCEPOL104                                                  */
61956   GPIO_PINCFG104_NCEPOL104_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
61957   GPIO_PINCFG104_NCEPOL104_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
61958 } GPIO_PINCFG104_NCEPOL104_Enum;
61959 
61960 /* ===========================================  GPIO PINCFG104 NCESRC104 [16..21]  =========================================== */
61961 typedef enum {                                  /*!< GPIO_PINCFG104_NCESRC104                                                  */
61962   GPIO_PINCFG104_NCESRC104_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61963   GPIO_PINCFG104_NCESRC104_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61964   GPIO_PINCFG104_NCESRC104_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61965   GPIO_PINCFG104_NCESRC104_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61966   GPIO_PINCFG104_NCESRC104_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61967   GPIO_PINCFG104_NCESRC104_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61968   GPIO_PINCFG104_NCESRC104_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61969   GPIO_PINCFG104_NCESRC104_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61970   GPIO_PINCFG104_NCESRC104_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61971   GPIO_PINCFG104_NCESRC104_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61972   GPIO_PINCFG104_NCESRC104_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61973   GPIO_PINCFG104_NCESRC104_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61974   GPIO_PINCFG104_NCESRC104_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61975   GPIO_PINCFG104_NCESRC104_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61976   GPIO_PINCFG104_NCESRC104_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61977   GPIO_PINCFG104_NCESRC104_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61978   GPIO_PINCFG104_NCESRC104_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61979   GPIO_PINCFG104_NCESRC104_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61980   GPIO_PINCFG104_NCESRC104_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61981   GPIO_PINCFG104_NCESRC104_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61982   GPIO_PINCFG104_NCESRC104_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61983   GPIO_PINCFG104_NCESRC104_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61984   GPIO_PINCFG104_NCESRC104_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61985   GPIO_PINCFG104_NCESRC104_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61986   GPIO_PINCFG104_NCESRC104_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61987   GPIO_PINCFG104_NCESRC104_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61988   GPIO_PINCFG104_NCESRC104_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61989   GPIO_PINCFG104_NCESRC104_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61990   GPIO_PINCFG104_NCESRC104_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61991   GPIO_PINCFG104_NCESRC104_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61992   GPIO_PINCFG104_NCESRC104_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61993   GPIO_PINCFG104_NCESRC104_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61994   GPIO_PINCFG104_NCESRC104_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61995   GPIO_PINCFG104_NCESRC104_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61996   GPIO_PINCFG104_NCESRC104_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61997   GPIO_PINCFG104_NCESRC104_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61998   GPIO_PINCFG104_NCESRC104_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61999   GPIO_PINCFG104_NCESRC104_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62000   GPIO_PINCFG104_NCESRC104_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62001   GPIO_PINCFG104_NCESRC104_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62002   GPIO_PINCFG104_NCESRC104_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62003   GPIO_PINCFG104_NCESRC104_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62004   GPIO_PINCFG104_NCESRC104_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
62005 } GPIO_PINCFG104_NCESRC104_Enum;
62006 
62007 /* ==========================================  GPIO PINCFG104 PULLCFG104 [13..15]  =========================================== */
62008 typedef enum {                                  /*!< GPIO_PINCFG104_PULLCFG104                                                 */
62009   GPIO_PINCFG104_PULLCFG104_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62010   GPIO_PINCFG104_PULLCFG104_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62011   GPIO_PINCFG104_PULLCFG104_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62012   GPIO_PINCFG104_PULLCFG104_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62013   GPIO_PINCFG104_PULLCFG104_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
62014   GPIO_PINCFG104_PULLCFG104_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
62015   GPIO_PINCFG104_PULLCFG104_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
62016   GPIO_PINCFG104_PULLCFG104_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
62017 } GPIO_PINCFG104_PULLCFG104_Enum;
62018 
62019 /* =============================================  GPIO PINCFG104 DS104 [10..11]  ============================================= */
62020 typedef enum {                                  /*!< GPIO_PINCFG104_DS104                                                      */
62021   GPIO_PINCFG104_DS104_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62022   GPIO_PINCFG104_DS104_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62023 } GPIO_PINCFG104_DS104_Enum;
62024 
62025 /* ============================================  GPIO PINCFG104 OUTCFG104 [8..9]  ============================================ */
62026 typedef enum {                                  /*!< GPIO_PINCFG104_OUTCFG104                                                  */
62027   GPIO_PINCFG104_OUTCFG104_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62028   GPIO_PINCFG104_OUTCFG104_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62029                                                      and 1 values on pin.                                                      */
62030   GPIO_PINCFG104_OUTCFG104_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62031                                                      low, tristate otherwise.                                                  */
62032   GPIO_PINCFG104_OUTCFG104_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62033                                                      drive 0, 1 of HiZ on pin.                                                 */
62034 } GPIO_PINCFG104_OUTCFG104_Enum;
62035 
62036 /* ============================================  GPIO PINCFG104 IRPTEN104 [6..7]  ============================================ */
62037 typedef enum {                                  /*!< GPIO_PINCFG104_IRPTEN104                                                  */
62038   GPIO_PINCFG104_IRPTEN104_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62039   GPIO_PINCFG104_IRPTEN104_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62040                                                      on this GPIO                                                              */
62041   GPIO_PINCFG104_IRPTEN104_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62042                                                      on this GPIO                                                              */
62043   GPIO_PINCFG104_IRPTEN104_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62044                                                      GPIO                                                                      */
62045 } GPIO_PINCFG104_IRPTEN104_Enum;
62046 
62047 /* ============================================  GPIO PINCFG104 FNCSEL104 [0..3]  ============================================ */
62048 typedef enum {                                  /*!< GPIO_PINCFG104_FNCSEL104                                                  */
62049   GPIO_PINCFG104_FNCSEL104_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62050   GPIO_PINCFG104_FNCSEL104_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62051   GPIO_PINCFG104_FNCSEL104_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62052   GPIO_PINCFG104_FNCSEL104_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62053   GPIO_PINCFG104_FNCSEL104_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62054   GPIO_PINCFG104_FNCSEL104_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62055   GPIO_PINCFG104_FNCSEL104_CT104       = 6,     /*!< CT104 : Timer/Counter input or output; Selection of direction
62056                                                      is done via CTIMER register settings.                                     */
62057   GPIO_PINCFG104_FNCSEL104_NCE104      = 7,     /*!< NCE104 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62058                                                      CE_POLARITY field                                                         */
62059   GPIO_PINCFG104_FNCSEL104_OBSBUS8     = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
62060   GPIO_PINCFG104_FNCSEL104_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62061   GPIO_PINCFG104_FNCSEL104_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62062   GPIO_PINCFG104_FNCSEL104_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
62063   GPIO_PINCFG104_FNCSEL104_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62064   GPIO_PINCFG104_FNCSEL104_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62065   GPIO_PINCFG104_FNCSEL104_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62066   GPIO_PINCFG104_FNCSEL104_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62067 } GPIO_PINCFG104_FNCSEL104_Enum;
62068 
62069 /* =======================================================  PINCFG105  ======================================================= */
62070 /* ============================================  GPIO PINCFG105 OUTCFG105 [8..9]  ============================================ */
62071 typedef enum {                                  /*!< GPIO_PINCFG105_OUTCFG105                                                  */
62072   GPIO_PINCFG105_OUTCFG105_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62073   GPIO_PINCFG105_OUTCFG105_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62074                                                      and 1 values on pin.                                                      */
62075   GPIO_PINCFG105_OUTCFG105_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62076                                                      low, tristate otherwise.                                                  */
62077   GPIO_PINCFG105_OUTCFG105_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62078                                                      drive 0, 1 of HiZ on pin.                                                 */
62079 } GPIO_PINCFG105_OUTCFG105_Enum;
62080 
62081 /* ============================================  GPIO PINCFG105 IRPTEN105 [6..7]  ============================================ */
62082 typedef enum {                                  /*!< GPIO_PINCFG105_IRPTEN105                                                  */
62083   GPIO_PINCFG105_IRPTEN105_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62084   GPIO_PINCFG105_IRPTEN105_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62085                                                      on this GPIO                                                              */
62086   GPIO_PINCFG105_IRPTEN105_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62087                                                      on this GPIO                                                              */
62088   GPIO_PINCFG105_IRPTEN105_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62089                                                      GPIO                                                                      */
62090 } GPIO_PINCFG105_IRPTEN105_Enum;
62091 
62092 /* ============================================  GPIO PINCFG105 FNCSEL105 [0..3]  ============================================ */
62093 typedef enum {                                  /*!< GPIO_PINCFG105_FNCSEL105                                                  */
62094   GPIO_PINCFG105_FNCSEL105_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62095   GPIO_PINCFG105_FNCSEL105_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62096   GPIO_PINCFG105_FNCSEL105_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62097   GPIO_PINCFG105_FNCSEL105_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62098   GPIO_PINCFG105_FNCSEL105_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62099   GPIO_PINCFG105_FNCSEL105_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62100   GPIO_PINCFG105_FNCSEL105_CT105       = 6,     /*!< CT105 : Timer/Counter input or output; Selection of direction
62101                                                      is done via CTIMER register settings.                                     */
62102   GPIO_PINCFG105_FNCSEL105_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62103   GPIO_PINCFG105_FNCSEL105_OBSBUS9     = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
62104   GPIO_PINCFG105_FNCSEL105_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62105   GPIO_PINCFG105_FNCSEL105_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62106   GPIO_PINCFG105_FNCSEL105_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62107   GPIO_PINCFG105_FNCSEL105_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62108   GPIO_PINCFG105_FNCSEL105_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62109   GPIO_PINCFG105_FNCSEL105_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62110   GPIO_PINCFG105_FNCSEL105_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62111 } GPIO_PINCFG105_FNCSEL105_Enum;
62112 
62113 /* =======================================================  PINCFG106  ======================================================= */
62114 /* ============================================  GPIO PINCFG106 OUTCFG106 [8..9]  ============================================ */
62115 typedef enum {                                  /*!< GPIO_PINCFG106_OUTCFG106                                                  */
62116   GPIO_PINCFG106_OUTCFG106_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62117   GPIO_PINCFG106_OUTCFG106_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62118                                                      and 1 values on pin.                                                      */
62119   GPIO_PINCFG106_OUTCFG106_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62120                                                      low, tristate otherwise.                                                  */
62121   GPIO_PINCFG106_OUTCFG106_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62122                                                      drive 0, 1 of HiZ on pin.                                                 */
62123 } GPIO_PINCFG106_OUTCFG106_Enum;
62124 
62125 /* ============================================  GPIO PINCFG106 IRPTEN106 [6..7]  ============================================ */
62126 typedef enum {                                  /*!< GPIO_PINCFG106_IRPTEN106                                                  */
62127   GPIO_PINCFG106_IRPTEN106_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62128   GPIO_PINCFG106_IRPTEN106_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62129                                                      on this GPIO                                                              */
62130   GPIO_PINCFG106_IRPTEN106_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62131                                                      on this GPIO                                                              */
62132   GPIO_PINCFG106_IRPTEN106_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62133                                                      GPIO                                                                      */
62134 } GPIO_PINCFG106_IRPTEN106_Enum;
62135 
62136 /* ============================================  GPIO PINCFG106 FNCSEL106 [0..3]  ============================================ */
62137 typedef enum {                                  /*!< GPIO_PINCFG106_FNCSEL106                                                  */
62138   GPIO_PINCFG106_FNCSEL106_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62139   GPIO_PINCFG106_FNCSEL106_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62140   GPIO_PINCFG106_FNCSEL106_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62141   GPIO_PINCFG106_FNCSEL106_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62142   GPIO_PINCFG106_FNCSEL106_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62143   GPIO_PINCFG106_FNCSEL106_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62144   GPIO_PINCFG106_FNCSEL106_CT106       = 6,     /*!< CT106 : Timer/Counter input or output; Selection of direction
62145                                                      is done via CTIMER register settings.                                     */
62146   GPIO_PINCFG106_FNCSEL106_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62147   GPIO_PINCFG106_FNCSEL106_OBSBUS10    = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
62148   GPIO_PINCFG106_FNCSEL106_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62149   GPIO_PINCFG106_FNCSEL106_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62150   GPIO_PINCFG106_FNCSEL106_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62151   GPIO_PINCFG106_FNCSEL106_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62152   GPIO_PINCFG106_FNCSEL106_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62153   GPIO_PINCFG106_FNCSEL106_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62154   GPIO_PINCFG106_FNCSEL106_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62155 } GPIO_PINCFG106_FNCSEL106_Enum;
62156 
62157 /* =======================================================  PINCFG107  ======================================================= */
62158 /* ============================================  GPIO PINCFG107 OUTCFG107 [8..9]  ============================================ */
62159 typedef enum {                                  /*!< GPIO_PINCFG107_OUTCFG107                                                  */
62160   GPIO_PINCFG107_OUTCFG107_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62161   GPIO_PINCFG107_OUTCFG107_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62162                                                      and 1 values on pin.                                                      */
62163   GPIO_PINCFG107_OUTCFG107_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62164                                                      low, tristate otherwise.                                                  */
62165   GPIO_PINCFG107_OUTCFG107_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62166                                                      drive 0, 1 of HiZ on pin.                                                 */
62167 } GPIO_PINCFG107_OUTCFG107_Enum;
62168 
62169 /* ============================================  GPIO PINCFG107 IRPTEN107 [6..7]  ============================================ */
62170 typedef enum {                                  /*!< GPIO_PINCFG107_IRPTEN107                                                  */
62171   GPIO_PINCFG107_IRPTEN107_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62172   GPIO_PINCFG107_IRPTEN107_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62173                                                      on this GPIO                                                              */
62174   GPIO_PINCFG107_IRPTEN107_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62175                                                      on this GPIO                                                              */
62176   GPIO_PINCFG107_IRPTEN107_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62177                                                      GPIO                                                                      */
62178 } GPIO_PINCFG107_IRPTEN107_Enum;
62179 
62180 /* ============================================  GPIO PINCFG107 FNCSEL107 [0..3]  ============================================ */
62181 typedef enum {                                  /*!< GPIO_PINCFG107_FNCSEL107                                                  */
62182   GPIO_PINCFG107_FNCSEL107_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62183   GPIO_PINCFG107_FNCSEL107_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62184   GPIO_PINCFG107_FNCSEL107_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62185   GPIO_PINCFG107_FNCSEL107_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62186   GPIO_PINCFG107_FNCSEL107_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62187   GPIO_PINCFG107_FNCSEL107_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62188   GPIO_PINCFG107_FNCSEL107_CT107       = 6,     /*!< CT107 : Timer/Counter input or output; Selection of direction
62189                                                      is done via CTIMER register settings.                                     */
62190   GPIO_PINCFG107_FNCSEL107_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62191   GPIO_PINCFG107_FNCSEL107_OBSBUS11    = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
62192   GPIO_PINCFG107_FNCSEL107_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62193   GPIO_PINCFG107_FNCSEL107_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62194   GPIO_PINCFG107_FNCSEL107_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62195   GPIO_PINCFG107_FNCSEL107_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62196   GPIO_PINCFG107_FNCSEL107_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62197   GPIO_PINCFG107_FNCSEL107_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62198   GPIO_PINCFG107_FNCSEL107_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62199 } GPIO_PINCFG107_FNCSEL107_Enum;
62200 
62201 /* =======================================================  PINCFG108  ======================================================= */
62202 /* ============================================  GPIO PINCFG108 OUTCFG108 [8..9]  ============================================ */
62203 typedef enum {                                  /*!< GPIO_PINCFG108_OUTCFG108                                                  */
62204   GPIO_PINCFG108_OUTCFG108_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62205   GPIO_PINCFG108_OUTCFG108_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62206                                                      and 1 values on pin.                                                      */
62207   GPIO_PINCFG108_OUTCFG108_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62208                                                      low, tristate otherwise.                                                  */
62209   GPIO_PINCFG108_OUTCFG108_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62210                                                      drive 0, 1 of HiZ on pin.                                                 */
62211 } GPIO_PINCFG108_OUTCFG108_Enum;
62212 
62213 /* ============================================  GPIO PINCFG108 IRPTEN108 [6..7]  ============================================ */
62214 typedef enum {                                  /*!< GPIO_PINCFG108_IRPTEN108                                                  */
62215   GPIO_PINCFG108_IRPTEN108_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62216   GPIO_PINCFG108_IRPTEN108_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62217                                                      on this GPIO                                                              */
62218   GPIO_PINCFG108_IRPTEN108_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62219                                                      on this GPIO                                                              */
62220   GPIO_PINCFG108_IRPTEN108_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62221                                                      GPIO                                                                      */
62222 } GPIO_PINCFG108_IRPTEN108_Enum;
62223 
62224 /* ============================================  GPIO PINCFG108 FNCSEL108 [0..3]  ============================================ */
62225 typedef enum {                                  /*!< GPIO_PINCFG108_FNCSEL108                                                  */
62226   GPIO_PINCFG108_FNCSEL108_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62227   GPIO_PINCFG108_FNCSEL108_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62228   GPIO_PINCFG108_FNCSEL108_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62229   GPIO_PINCFG108_FNCSEL108_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62230   GPIO_PINCFG108_FNCSEL108_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62231   GPIO_PINCFG108_FNCSEL108_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62232   GPIO_PINCFG108_FNCSEL108_CT108       = 6,     /*!< CT108 : Timer/Counter input or output; Selection of direction
62233                                                      is done via CTIMER register settings.                                     */
62234   GPIO_PINCFG108_FNCSEL108_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62235   GPIO_PINCFG108_FNCSEL108_OBSBUS12    = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
62236   GPIO_PINCFG108_FNCSEL108_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62237   GPIO_PINCFG108_FNCSEL108_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62238   GPIO_PINCFG108_FNCSEL108_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62239   GPIO_PINCFG108_FNCSEL108_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62240   GPIO_PINCFG108_FNCSEL108_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62241   GPIO_PINCFG108_FNCSEL108_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62242   GPIO_PINCFG108_FNCSEL108_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62243 } GPIO_PINCFG108_FNCSEL108_Enum;
62244 
62245 /* =======================================================  PINCFG109  ======================================================= */
62246 /* ============================================  GPIO PINCFG109 OUTCFG109 [8..9]  ============================================ */
62247 typedef enum {                                  /*!< GPIO_PINCFG109_OUTCFG109                                                  */
62248   GPIO_PINCFG109_OUTCFG109_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62249   GPIO_PINCFG109_OUTCFG109_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62250                                                      and 1 values on pin.                                                      */
62251   GPIO_PINCFG109_OUTCFG109_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62252                                                      low, tristate otherwise.                                                  */
62253   GPIO_PINCFG109_OUTCFG109_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62254                                                      drive 0, 1 of HiZ on pin.                                                 */
62255 } GPIO_PINCFG109_OUTCFG109_Enum;
62256 
62257 /* ============================================  GPIO PINCFG109 IRPTEN109 [6..7]  ============================================ */
62258 typedef enum {                                  /*!< GPIO_PINCFG109_IRPTEN109                                                  */
62259   GPIO_PINCFG109_IRPTEN109_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62260   GPIO_PINCFG109_IRPTEN109_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62261                                                      on this GPIO                                                              */
62262   GPIO_PINCFG109_IRPTEN109_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62263                                                      on this GPIO                                                              */
62264   GPIO_PINCFG109_IRPTEN109_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62265                                                      GPIO                                                                      */
62266 } GPIO_PINCFG109_IRPTEN109_Enum;
62267 
62268 /* ============================================  GPIO PINCFG109 FNCSEL109 [0..3]  ============================================ */
62269 typedef enum {                                  /*!< GPIO_PINCFG109_FNCSEL109                                                  */
62270   GPIO_PINCFG109_FNCSEL109_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62271   GPIO_PINCFG109_FNCSEL109_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62272   GPIO_PINCFG109_FNCSEL109_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62273   GPIO_PINCFG109_FNCSEL109_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62274   GPIO_PINCFG109_FNCSEL109_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62275   GPIO_PINCFG109_FNCSEL109_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62276   GPIO_PINCFG109_FNCSEL109_CT109       = 6,     /*!< CT109 : Timer/Counter input or output; Selection of direction
62277                                                      is done via CTIMER register settings.                                     */
62278   GPIO_PINCFG109_FNCSEL109_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62279   GPIO_PINCFG109_FNCSEL109_OBSBUS13    = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
62280   GPIO_PINCFG109_FNCSEL109_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62281   GPIO_PINCFG109_FNCSEL109_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62282   GPIO_PINCFG109_FNCSEL109_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62283   GPIO_PINCFG109_FNCSEL109_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62284   GPIO_PINCFG109_FNCSEL109_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62285   GPIO_PINCFG109_FNCSEL109_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62286   GPIO_PINCFG109_FNCSEL109_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62287 } GPIO_PINCFG109_FNCSEL109_Enum;
62288 
62289 /* =======================================================  PINCFG110  ======================================================= */
62290 /* ============================================  GPIO PINCFG110 OUTCFG110 [8..9]  ============================================ */
62291 typedef enum {                                  /*!< GPIO_PINCFG110_OUTCFG110                                                  */
62292   GPIO_PINCFG110_OUTCFG110_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62293   GPIO_PINCFG110_OUTCFG110_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62294                                                      and 1 values on pin.                                                      */
62295   GPIO_PINCFG110_OUTCFG110_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62296                                                      low, tristate otherwise.                                                  */
62297   GPIO_PINCFG110_OUTCFG110_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62298                                                      drive 0, 1 of HiZ on pin.                                                 */
62299 } GPIO_PINCFG110_OUTCFG110_Enum;
62300 
62301 /* ============================================  GPIO PINCFG110 IRPTEN110 [6..7]  ============================================ */
62302 typedef enum {                                  /*!< GPIO_PINCFG110_IRPTEN110                                                  */
62303   GPIO_PINCFG110_IRPTEN110_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62304   GPIO_PINCFG110_IRPTEN110_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62305                                                      on this GPIO                                                              */
62306   GPIO_PINCFG110_IRPTEN110_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62307                                                      on this GPIO                                                              */
62308   GPIO_PINCFG110_IRPTEN110_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62309                                                      GPIO                                                                      */
62310 } GPIO_PINCFG110_IRPTEN110_Enum;
62311 
62312 /* ============================================  GPIO PINCFG110 FNCSEL110 [0..3]  ============================================ */
62313 typedef enum {                                  /*!< GPIO_PINCFG110_FNCSEL110                                                  */
62314   GPIO_PINCFG110_FNCSEL110_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62315   GPIO_PINCFG110_FNCSEL110_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62316   GPIO_PINCFG110_FNCSEL110_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62317   GPIO_PINCFG110_FNCSEL110_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62318   GPIO_PINCFG110_FNCSEL110_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62319   GPIO_PINCFG110_FNCSEL110_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62320   GPIO_PINCFG110_FNCSEL110_CT110       = 6,     /*!< CT110 : Timer/Counter input or output; Selection of direction
62321                                                      is done via CTIMER register settings.                                     */
62322   GPIO_PINCFG110_FNCSEL110_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62323   GPIO_PINCFG110_FNCSEL110_OBSBUS14    = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
62324   GPIO_PINCFG110_FNCSEL110_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62325   GPIO_PINCFG110_FNCSEL110_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62326   GPIO_PINCFG110_FNCSEL110_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62327   GPIO_PINCFG110_FNCSEL110_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62328   GPIO_PINCFG110_FNCSEL110_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62329   GPIO_PINCFG110_FNCSEL110_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62330   GPIO_PINCFG110_FNCSEL110_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62331 } GPIO_PINCFG110_FNCSEL110_Enum;
62332 
62333 /* =======================================================  PINCFG111  ======================================================= */
62334 /* ============================================  GPIO PINCFG111 OUTCFG111 [8..9]  ============================================ */
62335 typedef enum {                                  /*!< GPIO_PINCFG111_OUTCFG111                                                  */
62336   GPIO_PINCFG111_OUTCFG111_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62337   GPIO_PINCFG111_OUTCFG111_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62338                                                      and 1 values on pin.                                                      */
62339   GPIO_PINCFG111_OUTCFG111_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62340                                                      low, tristate otherwise.                                                  */
62341   GPIO_PINCFG111_OUTCFG111_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62342                                                      drive 0, 1 of HiZ on pin.                                                 */
62343 } GPIO_PINCFG111_OUTCFG111_Enum;
62344 
62345 /* ============================================  GPIO PINCFG111 IRPTEN111 [6..7]  ============================================ */
62346 typedef enum {                                  /*!< GPIO_PINCFG111_IRPTEN111                                                  */
62347   GPIO_PINCFG111_IRPTEN111_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62348   GPIO_PINCFG111_IRPTEN111_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62349                                                      on this GPIO                                                              */
62350   GPIO_PINCFG111_IRPTEN111_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62351                                                      on this GPIO                                                              */
62352   GPIO_PINCFG111_IRPTEN111_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62353                                                      GPIO                                                                      */
62354 } GPIO_PINCFG111_IRPTEN111_Enum;
62355 
62356 /* ============================================  GPIO PINCFG111 FNCSEL111 [0..3]  ============================================ */
62357 typedef enum {                                  /*!< GPIO_PINCFG111_FNCSEL111                                                  */
62358   GPIO_PINCFG111_FNCSEL111_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62359   GPIO_PINCFG111_FNCSEL111_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62360   GPIO_PINCFG111_FNCSEL111_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62361   GPIO_PINCFG111_FNCSEL111_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62362   GPIO_PINCFG111_FNCSEL111_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62363   GPIO_PINCFG111_FNCSEL111_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62364   GPIO_PINCFG111_FNCSEL111_CT111       = 6,     /*!< CT111 : Timer/Counter input or output; Selection of direction
62365                                                      is done via CTIMER register settings.                                     */
62366   GPIO_PINCFG111_FNCSEL111_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62367   GPIO_PINCFG111_FNCSEL111_OBSBUS15    = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
62368   GPIO_PINCFG111_FNCSEL111_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62369   GPIO_PINCFG111_FNCSEL111_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62370   GPIO_PINCFG111_FNCSEL111_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62371   GPIO_PINCFG111_FNCSEL111_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62372   GPIO_PINCFG111_FNCSEL111_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62373   GPIO_PINCFG111_FNCSEL111_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62374   GPIO_PINCFG111_FNCSEL111_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62375 } GPIO_PINCFG111_FNCSEL111_Enum;
62376 
62377 /* =======================================================  PINCFG112  ======================================================= */
62378 /* ============================================  GPIO PINCFG112 OUTCFG112 [8..9]  ============================================ */
62379 typedef enum {                                  /*!< GPIO_PINCFG112_OUTCFG112                                                  */
62380   GPIO_PINCFG112_OUTCFG112_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62381   GPIO_PINCFG112_OUTCFG112_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62382                                                      and 1 values on pin.                                                      */
62383   GPIO_PINCFG112_OUTCFG112_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62384                                                      low, tristate otherwise.                                                  */
62385   GPIO_PINCFG112_OUTCFG112_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62386                                                      drive 0, 1 of HiZ on pin.                                                 */
62387 } GPIO_PINCFG112_OUTCFG112_Enum;
62388 
62389 /* ============================================  GPIO PINCFG112 IRPTEN112 [6..7]  ============================================ */
62390 typedef enum {                                  /*!< GPIO_PINCFG112_IRPTEN112                                                  */
62391   GPIO_PINCFG112_IRPTEN112_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62392   GPIO_PINCFG112_IRPTEN112_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62393                                                      on this GPIO                                                              */
62394   GPIO_PINCFG112_IRPTEN112_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62395                                                      on this GPIO                                                              */
62396   GPIO_PINCFG112_IRPTEN112_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62397                                                      GPIO                                                                      */
62398 } GPIO_PINCFG112_IRPTEN112_Enum;
62399 
62400 /* ============================================  GPIO PINCFG112 FNCSEL112 [0..3]  ============================================ */
62401 typedef enum {                                  /*!< GPIO_PINCFG112_FNCSEL112                                                  */
62402   GPIO_PINCFG112_FNCSEL112_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62403   GPIO_PINCFG112_FNCSEL112_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62404   GPIO_PINCFG112_FNCSEL112_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62405   GPIO_PINCFG112_FNCSEL112_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62406   GPIO_PINCFG112_FNCSEL112_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62407   GPIO_PINCFG112_FNCSEL112_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62408   GPIO_PINCFG112_FNCSEL112_CT112       = 6,     /*!< CT112 : Timer/Counter input or output; Selection of direction
62409                                                      is done via CTIMER register settings.                                     */
62410   GPIO_PINCFG112_FNCSEL112_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62411   GPIO_PINCFG112_FNCSEL112_OBSBUS0     = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
62412   GPIO_PINCFG112_FNCSEL112_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62413   GPIO_PINCFG112_FNCSEL112_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62414   GPIO_PINCFG112_FNCSEL112_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62415   GPIO_PINCFG112_FNCSEL112_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62416   GPIO_PINCFG112_FNCSEL112_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62417   GPIO_PINCFG112_FNCSEL112_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62418   GPIO_PINCFG112_FNCSEL112_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62419 } GPIO_PINCFG112_FNCSEL112_Enum;
62420 
62421 /* =======================================================  PINCFG113  ======================================================= */
62422 /* ============================================  GPIO PINCFG113 OUTCFG113 [8..9]  ============================================ */
62423 typedef enum {                                  /*!< GPIO_PINCFG113_OUTCFG113                                                  */
62424   GPIO_PINCFG113_OUTCFG113_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62425   GPIO_PINCFG113_OUTCFG113_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62426                                                      and 1 values on pin.                                                      */
62427   GPIO_PINCFG113_OUTCFG113_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62428                                                      low, tristate otherwise.                                                  */
62429   GPIO_PINCFG113_OUTCFG113_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62430                                                      drive 0, 1 of HiZ on pin.                                                 */
62431 } GPIO_PINCFG113_OUTCFG113_Enum;
62432 
62433 /* ============================================  GPIO PINCFG113 IRPTEN113 [6..7]  ============================================ */
62434 typedef enum {                                  /*!< GPIO_PINCFG113_IRPTEN113                                                  */
62435   GPIO_PINCFG113_IRPTEN113_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62436   GPIO_PINCFG113_IRPTEN113_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62437                                                      on this GPIO                                                              */
62438   GPIO_PINCFG113_IRPTEN113_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62439                                                      on this GPIO                                                              */
62440   GPIO_PINCFG113_IRPTEN113_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62441                                                      GPIO                                                                      */
62442 } GPIO_PINCFG113_IRPTEN113_Enum;
62443 
62444 /* ============================================  GPIO PINCFG113 FNCSEL113 [0..3]  ============================================ */
62445 typedef enum {                                  /*!< GPIO_PINCFG113_FNCSEL113                                                  */
62446   GPIO_PINCFG113_FNCSEL113_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62447   GPIO_PINCFG113_FNCSEL113_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62448   GPIO_PINCFG113_FNCSEL113_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62449   GPIO_PINCFG113_FNCSEL113_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62450   GPIO_PINCFG113_FNCSEL113_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62451   GPIO_PINCFG113_FNCSEL113_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62452   GPIO_PINCFG113_FNCSEL113_CT113       = 6,     /*!< CT113 : Timer/Counter input or output; Selection of direction
62453                                                      is done via CTIMER register settings.                                     */
62454   GPIO_PINCFG113_FNCSEL113_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62455   GPIO_PINCFG113_FNCSEL113_OBSBUS1     = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
62456   GPIO_PINCFG113_FNCSEL113_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62457   GPIO_PINCFG113_FNCSEL113_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62458   GPIO_PINCFG113_FNCSEL113_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62459   GPIO_PINCFG113_FNCSEL113_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62460   GPIO_PINCFG113_FNCSEL113_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62461   GPIO_PINCFG113_FNCSEL113_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62462   GPIO_PINCFG113_FNCSEL113_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62463 } GPIO_PINCFG113_FNCSEL113_Enum;
62464 
62465 /* =======================================================  PINCFG114  ======================================================= */
62466 /* ============================================  GPIO PINCFG114 OUTCFG114 [8..9]  ============================================ */
62467 typedef enum {                                  /*!< GPIO_PINCFG114_OUTCFG114                                                  */
62468   GPIO_PINCFG114_OUTCFG114_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62469   GPIO_PINCFG114_OUTCFG114_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62470                                                      and 1 values on pin.                                                      */
62471   GPIO_PINCFG114_OUTCFG114_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62472                                                      low, tristate otherwise.                                                  */
62473   GPIO_PINCFG114_OUTCFG114_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62474                                                      drive 0, 1 of HiZ on pin.                                                 */
62475 } GPIO_PINCFG114_OUTCFG114_Enum;
62476 
62477 /* ============================================  GPIO PINCFG114 IRPTEN114 [6..7]  ============================================ */
62478 typedef enum {                                  /*!< GPIO_PINCFG114_IRPTEN114                                                  */
62479   GPIO_PINCFG114_IRPTEN114_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62480   GPIO_PINCFG114_IRPTEN114_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62481                                                      on this GPIO                                                              */
62482   GPIO_PINCFG114_IRPTEN114_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62483                                                      on this GPIO                                                              */
62484   GPIO_PINCFG114_IRPTEN114_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62485                                                      GPIO                                                                      */
62486 } GPIO_PINCFG114_IRPTEN114_Enum;
62487 
62488 /* ============================================  GPIO PINCFG114 FNCSEL114 [0..3]  ============================================ */
62489 typedef enum {                                  /*!< GPIO_PINCFG114_FNCSEL114                                                  */
62490   GPIO_PINCFG114_FNCSEL114_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62491   GPIO_PINCFG114_FNCSEL114_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62492   GPIO_PINCFG114_FNCSEL114_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62493   GPIO_PINCFG114_FNCSEL114_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62494   GPIO_PINCFG114_FNCSEL114_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62495   GPIO_PINCFG114_FNCSEL114_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62496   GPIO_PINCFG114_FNCSEL114_CT114       = 6,     /*!< CT114 : Timer/Counter input or output; Selection of direction
62497                                                      is done via CTIMER register settings.                                     */
62498   GPIO_PINCFG114_FNCSEL114_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62499   GPIO_PINCFG114_FNCSEL114_OBSBUS2     = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
62500   GPIO_PINCFG114_FNCSEL114_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62501   GPIO_PINCFG114_FNCSEL114_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62502   GPIO_PINCFG114_FNCSEL114_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62503   GPIO_PINCFG114_FNCSEL114_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62504   GPIO_PINCFG114_FNCSEL114_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62505   GPIO_PINCFG114_FNCSEL114_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62506   GPIO_PINCFG114_FNCSEL114_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62507 } GPIO_PINCFG114_FNCSEL114_Enum;
62508 
62509 /* =======================================================  PINCFG115  ======================================================= */
62510 /* ============================================  GPIO PINCFG115 OUTCFG115 [8..9]  ============================================ */
62511 typedef enum {                                  /*!< GPIO_PINCFG115_OUTCFG115                                                  */
62512   GPIO_PINCFG115_OUTCFG115_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62513   GPIO_PINCFG115_OUTCFG115_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62514                                                      and 1 values on pin.                                                      */
62515   GPIO_PINCFG115_OUTCFG115_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62516                                                      low, tristate otherwise.                                                  */
62517   GPIO_PINCFG115_OUTCFG115_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62518                                                      drive 0, 1 of HiZ on pin.                                                 */
62519 } GPIO_PINCFG115_OUTCFG115_Enum;
62520 
62521 /* ============================================  GPIO PINCFG115 IRPTEN115 [6..7]  ============================================ */
62522 typedef enum {                                  /*!< GPIO_PINCFG115_IRPTEN115                                                  */
62523   GPIO_PINCFG115_IRPTEN115_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62524   GPIO_PINCFG115_IRPTEN115_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62525                                                      on this GPIO                                                              */
62526   GPIO_PINCFG115_IRPTEN115_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62527                                                      on this GPIO                                                              */
62528   GPIO_PINCFG115_IRPTEN115_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62529                                                      GPIO                                                                      */
62530 } GPIO_PINCFG115_IRPTEN115_Enum;
62531 
62532 /* ============================================  GPIO PINCFG115 FNCSEL115 [0..3]  ============================================ */
62533 typedef enum {                                  /*!< GPIO_PINCFG115_FNCSEL115                                                  */
62534   GPIO_PINCFG115_FNCSEL115_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62535   GPIO_PINCFG115_FNCSEL115_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62536   GPIO_PINCFG115_FNCSEL115_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62537   GPIO_PINCFG115_FNCSEL115_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62538   GPIO_PINCFG115_FNCSEL115_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62539   GPIO_PINCFG115_FNCSEL115_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62540   GPIO_PINCFG115_FNCSEL115_CT115       = 6,     /*!< CT115 : Timer/Counter input or output; Selection of direction
62541                                                      is done via CTIMER register settings.                                     */
62542   GPIO_PINCFG115_FNCSEL115_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62543   GPIO_PINCFG115_FNCSEL115_OBSBUS3     = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
62544   GPIO_PINCFG115_FNCSEL115_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62545   GPIO_PINCFG115_FNCSEL115_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62546   GPIO_PINCFG115_FNCSEL115_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62547   GPIO_PINCFG115_FNCSEL115_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62548   GPIO_PINCFG115_FNCSEL115_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62549   GPIO_PINCFG115_FNCSEL115_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62550   GPIO_PINCFG115_FNCSEL115_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62551 } GPIO_PINCFG115_FNCSEL115_Enum;
62552 
62553 /* =======================================================  PINCFG116  ======================================================= */
62554 /* ============================================  GPIO PINCFG116 OUTCFG116 [8..9]  ============================================ */
62555 typedef enum {                                  /*!< GPIO_PINCFG116_OUTCFG116                                                  */
62556   GPIO_PINCFG116_OUTCFG116_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62557   GPIO_PINCFG116_OUTCFG116_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62558                                                      and 1 values on pin.                                                      */
62559   GPIO_PINCFG116_OUTCFG116_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62560                                                      low, tristate otherwise.                                                  */
62561   GPIO_PINCFG116_OUTCFG116_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62562                                                      drive 0, 1 of HiZ on pin.                                                 */
62563 } GPIO_PINCFG116_OUTCFG116_Enum;
62564 
62565 /* ============================================  GPIO PINCFG116 IRPTEN116 [6..7]  ============================================ */
62566 typedef enum {                                  /*!< GPIO_PINCFG116_IRPTEN116                                                  */
62567   GPIO_PINCFG116_IRPTEN116_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62568   GPIO_PINCFG116_IRPTEN116_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62569                                                      on this GPIO                                                              */
62570   GPIO_PINCFG116_IRPTEN116_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62571                                                      on this GPIO                                                              */
62572   GPIO_PINCFG116_IRPTEN116_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62573                                                      GPIO                                                                      */
62574 } GPIO_PINCFG116_IRPTEN116_Enum;
62575 
62576 /* ============================================  GPIO PINCFG116 FNCSEL116 [0..3]  ============================================ */
62577 typedef enum {                                  /*!< GPIO_PINCFG116_FNCSEL116                                                  */
62578   GPIO_PINCFG116_FNCSEL116_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62579   GPIO_PINCFG116_FNCSEL116_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62580   GPIO_PINCFG116_FNCSEL116_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62581   GPIO_PINCFG116_FNCSEL116_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62582   GPIO_PINCFG116_FNCSEL116_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62583   GPIO_PINCFG116_FNCSEL116_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62584   GPIO_PINCFG116_FNCSEL116_CT116       = 6,     /*!< CT116 : Timer/Counter input or output; Selection of direction
62585                                                      is done via CTIMER register settings.                                     */
62586   GPIO_PINCFG116_FNCSEL116_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62587   GPIO_PINCFG116_FNCSEL116_OBSBUS4     = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
62588   GPIO_PINCFG116_FNCSEL116_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62589   GPIO_PINCFG116_FNCSEL116_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62590   GPIO_PINCFG116_FNCSEL116_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62591   GPIO_PINCFG116_FNCSEL116_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62592   GPIO_PINCFG116_FNCSEL116_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62593   GPIO_PINCFG116_FNCSEL116_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62594   GPIO_PINCFG116_FNCSEL116_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62595 } GPIO_PINCFG116_FNCSEL116_Enum;
62596 
62597 /* =======================================================  PINCFG117  ======================================================= */
62598 /* ============================================  GPIO PINCFG117 OUTCFG117 [8..9]  ============================================ */
62599 typedef enum {                                  /*!< GPIO_PINCFG117_OUTCFG117                                                  */
62600   GPIO_PINCFG117_OUTCFG117_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62601   GPIO_PINCFG117_OUTCFG117_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62602                                                      and 1 values on pin.                                                      */
62603   GPIO_PINCFG117_OUTCFG117_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62604                                                      low, tristate otherwise.                                                  */
62605   GPIO_PINCFG117_OUTCFG117_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62606                                                      drive 0, 1 of HiZ on pin.                                                 */
62607 } GPIO_PINCFG117_OUTCFG117_Enum;
62608 
62609 /* ============================================  GPIO PINCFG117 IRPTEN117 [6..7]  ============================================ */
62610 typedef enum {                                  /*!< GPIO_PINCFG117_IRPTEN117                                                  */
62611   GPIO_PINCFG117_IRPTEN117_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62612   GPIO_PINCFG117_IRPTEN117_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62613                                                      on this GPIO                                                              */
62614   GPIO_PINCFG117_IRPTEN117_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62615                                                      on this GPIO                                                              */
62616   GPIO_PINCFG117_IRPTEN117_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62617                                                      GPIO                                                                      */
62618 } GPIO_PINCFG117_IRPTEN117_Enum;
62619 
62620 /* ============================================  GPIO PINCFG117 FNCSEL117 [0..3]  ============================================ */
62621 typedef enum {                                  /*!< GPIO_PINCFG117_FNCSEL117                                                  */
62622   GPIO_PINCFG117_FNCSEL117_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62623   GPIO_PINCFG117_FNCSEL117_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62624   GPIO_PINCFG117_FNCSEL117_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62625   GPIO_PINCFG117_FNCSEL117_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62626   GPIO_PINCFG117_FNCSEL117_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62627   GPIO_PINCFG117_FNCSEL117_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62628   GPIO_PINCFG117_FNCSEL117_CT117       = 6,     /*!< CT117 : Timer/Counter input or output; Selection of direction
62629                                                      is done via CTIMER register settings.                                     */
62630   GPIO_PINCFG117_FNCSEL117_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62631   GPIO_PINCFG117_FNCSEL117_OBSBUS5     = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
62632   GPIO_PINCFG117_FNCSEL117_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62633   GPIO_PINCFG117_FNCSEL117_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62634   GPIO_PINCFG117_FNCSEL117_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62635   GPIO_PINCFG117_FNCSEL117_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62636   GPIO_PINCFG117_FNCSEL117_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62637   GPIO_PINCFG117_FNCSEL117_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62638   GPIO_PINCFG117_FNCSEL117_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62639 } GPIO_PINCFG117_FNCSEL117_Enum;
62640 
62641 /* =======================================================  PINCFG118  ======================================================= */
62642 /* ============================================  GPIO PINCFG118 OUTCFG118 [8..9]  ============================================ */
62643 typedef enum {                                  /*!< GPIO_PINCFG118_OUTCFG118                                                  */
62644   GPIO_PINCFG118_OUTCFG118_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62645   GPIO_PINCFG118_OUTCFG118_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62646                                                      and 1 values on pin.                                                      */
62647   GPIO_PINCFG118_OUTCFG118_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62648                                                      low, tristate otherwise.                                                  */
62649   GPIO_PINCFG118_OUTCFG118_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62650                                                      drive 0, 1 of HiZ on pin.                                                 */
62651 } GPIO_PINCFG118_OUTCFG118_Enum;
62652 
62653 /* ============================================  GPIO PINCFG118 IRPTEN118 [6..7]  ============================================ */
62654 typedef enum {                                  /*!< GPIO_PINCFG118_IRPTEN118                                                  */
62655   GPIO_PINCFG118_IRPTEN118_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62656   GPIO_PINCFG118_IRPTEN118_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62657                                                      on this GPIO                                                              */
62658   GPIO_PINCFG118_IRPTEN118_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62659                                                      on this GPIO                                                              */
62660   GPIO_PINCFG118_IRPTEN118_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62661                                                      GPIO                                                                      */
62662 } GPIO_PINCFG118_IRPTEN118_Enum;
62663 
62664 /* ============================================  GPIO PINCFG118 FNCSEL118 [0..3]  ============================================ */
62665 typedef enum {                                  /*!< GPIO_PINCFG118_FNCSEL118                                                  */
62666   GPIO_PINCFG118_FNCSEL118_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62667   GPIO_PINCFG118_FNCSEL118_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62668   GPIO_PINCFG118_FNCSEL118_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62669   GPIO_PINCFG118_FNCSEL118_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62670   GPIO_PINCFG118_FNCSEL118_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62671   GPIO_PINCFG118_FNCSEL118_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62672   GPIO_PINCFG118_FNCSEL118_CT118       = 6,     /*!< CT118 : Timer/Counter input or output; Selection of direction
62673                                                      is done via CTIMER register settings.                                     */
62674   GPIO_PINCFG118_FNCSEL118_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62675   GPIO_PINCFG118_FNCSEL118_OBSBUS6     = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
62676   GPIO_PINCFG118_FNCSEL118_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62677   GPIO_PINCFG118_FNCSEL118_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62678   GPIO_PINCFG118_FNCSEL118_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62679   GPIO_PINCFG118_FNCSEL118_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62680   GPIO_PINCFG118_FNCSEL118_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62681   GPIO_PINCFG118_FNCSEL118_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62682   GPIO_PINCFG118_FNCSEL118_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62683 } GPIO_PINCFG118_FNCSEL118_Enum;
62684 
62685 /* =======================================================  PINCFG119  ======================================================= */
62686 /* ============================================  GPIO PINCFG119 OUTCFG119 [8..9]  ============================================ */
62687 typedef enum {                                  /*!< GPIO_PINCFG119_OUTCFG119                                                  */
62688   GPIO_PINCFG119_OUTCFG119_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62689   GPIO_PINCFG119_OUTCFG119_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62690                                                      and 1 values on pin.                                                      */
62691   GPIO_PINCFG119_OUTCFG119_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62692                                                      low, tristate otherwise.                                                  */
62693   GPIO_PINCFG119_OUTCFG119_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62694                                                      drive 0, 1 of HiZ on pin.                                                 */
62695 } GPIO_PINCFG119_OUTCFG119_Enum;
62696 
62697 /* ============================================  GPIO PINCFG119 IRPTEN119 [6..7]  ============================================ */
62698 typedef enum {                                  /*!< GPIO_PINCFG119_IRPTEN119                                                  */
62699   GPIO_PINCFG119_IRPTEN119_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62700   GPIO_PINCFG119_IRPTEN119_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62701                                                      on this GPIO                                                              */
62702   GPIO_PINCFG119_IRPTEN119_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62703                                                      on this GPIO                                                              */
62704   GPIO_PINCFG119_IRPTEN119_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62705                                                      GPIO                                                                      */
62706 } GPIO_PINCFG119_IRPTEN119_Enum;
62707 
62708 /* ============================================  GPIO PINCFG119 FNCSEL119 [0..3]  ============================================ */
62709 typedef enum {                                  /*!< GPIO_PINCFG119_FNCSEL119                                                  */
62710   GPIO_PINCFG119_FNCSEL119_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62711   GPIO_PINCFG119_FNCSEL119_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62712   GPIO_PINCFG119_FNCSEL119_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62713   GPIO_PINCFG119_FNCSEL119_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62714   GPIO_PINCFG119_FNCSEL119_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62715   GPIO_PINCFG119_FNCSEL119_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62716   GPIO_PINCFG119_FNCSEL119_CT119       = 6,     /*!< CT119 : Timer/Counter input or output; Selection of direction
62717                                                      is done via CTIMER register settings.                                     */
62718   GPIO_PINCFG119_FNCSEL119_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62719   GPIO_PINCFG119_FNCSEL119_OBSBUS7     = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
62720   GPIO_PINCFG119_FNCSEL119_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62721   GPIO_PINCFG119_FNCSEL119_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62722   GPIO_PINCFG119_FNCSEL119_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62723   GPIO_PINCFG119_FNCSEL119_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62724   GPIO_PINCFG119_FNCSEL119_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62725   GPIO_PINCFG119_FNCSEL119_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62726   GPIO_PINCFG119_FNCSEL119_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62727 } GPIO_PINCFG119_FNCSEL119_Enum;
62728 
62729 /* =======================================================  PINCFG120  ======================================================= */
62730 /* ============================================  GPIO PINCFG120 OUTCFG120 [8..9]  ============================================ */
62731 typedef enum {                                  /*!< GPIO_PINCFG120_OUTCFG120                                                  */
62732   GPIO_PINCFG120_OUTCFG120_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62733   GPIO_PINCFG120_OUTCFG120_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62734                                                      and 1 values on pin.                                                      */
62735   GPIO_PINCFG120_OUTCFG120_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62736                                                      low, tristate otherwise.                                                  */
62737   GPIO_PINCFG120_OUTCFG120_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62738                                                      drive 0, 1 of HiZ on pin.                                                 */
62739 } GPIO_PINCFG120_OUTCFG120_Enum;
62740 
62741 /* ============================================  GPIO PINCFG120 IRPTEN120 [6..7]  ============================================ */
62742 typedef enum {                                  /*!< GPIO_PINCFG120_IRPTEN120                                                  */
62743   GPIO_PINCFG120_IRPTEN120_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62744   GPIO_PINCFG120_IRPTEN120_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62745                                                      on this GPIO                                                              */
62746   GPIO_PINCFG120_IRPTEN120_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62747                                                      on this GPIO                                                              */
62748   GPIO_PINCFG120_IRPTEN120_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62749                                                      GPIO                                                                      */
62750 } GPIO_PINCFG120_IRPTEN120_Enum;
62751 
62752 /* ============================================  GPIO PINCFG120 FNCSEL120 [0..3]  ============================================ */
62753 typedef enum {                                  /*!< GPIO_PINCFG120_FNCSEL120                                                  */
62754   GPIO_PINCFG120_FNCSEL120_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62755   GPIO_PINCFG120_FNCSEL120_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62756   GPIO_PINCFG120_FNCSEL120_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62757   GPIO_PINCFG120_FNCSEL120_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62758   GPIO_PINCFG120_FNCSEL120_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62759   GPIO_PINCFG120_FNCSEL120_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62760   GPIO_PINCFG120_FNCSEL120_CT120       = 6,     /*!< CT120 : Timer/Counter input or output; Selection of direction
62761                                                      is done via CTIMER register settings.                                     */
62762   GPIO_PINCFG120_FNCSEL120_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62763   GPIO_PINCFG120_FNCSEL120_OBSBUS8     = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
62764   GPIO_PINCFG120_FNCSEL120_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62765   GPIO_PINCFG120_FNCSEL120_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62766   GPIO_PINCFG120_FNCSEL120_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62767   GPIO_PINCFG120_FNCSEL120_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62768   GPIO_PINCFG120_FNCSEL120_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62769   GPIO_PINCFG120_FNCSEL120_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62770   GPIO_PINCFG120_FNCSEL120_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62771 } GPIO_PINCFG120_FNCSEL120_Enum;
62772 
62773 /* =======================================================  PINCFG121  ======================================================= */
62774 /* ============================================  GPIO PINCFG121 OUTCFG121 [8..9]  ============================================ */
62775 typedef enum {                                  /*!< GPIO_PINCFG121_OUTCFG121                                                  */
62776   GPIO_PINCFG121_OUTCFG121_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62777   GPIO_PINCFG121_OUTCFG121_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62778                                                      and 1 values on pin.                                                      */
62779   GPIO_PINCFG121_OUTCFG121_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62780                                                      low, tristate otherwise.                                                  */
62781   GPIO_PINCFG121_OUTCFG121_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62782                                                      drive 0, 1 of HiZ on pin.                                                 */
62783 } GPIO_PINCFG121_OUTCFG121_Enum;
62784 
62785 /* ============================================  GPIO PINCFG121 IRPTEN121 [6..7]  ============================================ */
62786 typedef enum {                                  /*!< GPIO_PINCFG121_IRPTEN121                                                  */
62787   GPIO_PINCFG121_IRPTEN121_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62788   GPIO_PINCFG121_IRPTEN121_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62789                                                      on this GPIO                                                              */
62790   GPIO_PINCFG121_IRPTEN121_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62791                                                      on this GPIO                                                              */
62792   GPIO_PINCFG121_IRPTEN121_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62793                                                      GPIO                                                                      */
62794 } GPIO_PINCFG121_IRPTEN121_Enum;
62795 
62796 /* ============================================  GPIO PINCFG121 FNCSEL121 [0..3]  ============================================ */
62797 typedef enum {                                  /*!< GPIO_PINCFG121_FNCSEL121                                                  */
62798   GPIO_PINCFG121_FNCSEL121_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62799   GPIO_PINCFG121_FNCSEL121_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62800   GPIO_PINCFG121_FNCSEL121_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62801   GPIO_PINCFG121_FNCSEL121_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62802   GPIO_PINCFG121_FNCSEL121_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62803   GPIO_PINCFG121_FNCSEL121_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62804   GPIO_PINCFG121_FNCSEL121_CT121       = 6,     /*!< CT121 : Timer/Counter input or output; Selection of direction
62805                                                      is done via CTIMER register settings.                                     */
62806   GPIO_PINCFG121_FNCSEL121_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62807   GPIO_PINCFG121_FNCSEL121_OBSBUS9     = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
62808   GPIO_PINCFG121_FNCSEL121_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62809   GPIO_PINCFG121_FNCSEL121_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62810   GPIO_PINCFG121_FNCSEL121_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62811   GPIO_PINCFG121_FNCSEL121_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62812   GPIO_PINCFG121_FNCSEL121_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62813   GPIO_PINCFG121_FNCSEL121_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62814   GPIO_PINCFG121_FNCSEL121_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62815 } GPIO_PINCFG121_FNCSEL121_Enum;
62816 
62817 /* =======================================================  PINCFG122  ======================================================= */
62818 /* ============================================  GPIO PINCFG122 OUTCFG122 [8..9]  ============================================ */
62819 typedef enum {                                  /*!< GPIO_PINCFG122_OUTCFG122                                                  */
62820   GPIO_PINCFG122_OUTCFG122_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62821   GPIO_PINCFG122_OUTCFG122_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62822                                                      and 1 values on pin.                                                      */
62823   GPIO_PINCFG122_OUTCFG122_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62824                                                      low, tristate otherwise.                                                  */
62825   GPIO_PINCFG122_OUTCFG122_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62826                                                      drive 0, 1 of HiZ on pin.                                                 */
62827 } GPIO_PINCFG122_OUTCFG122_Enum;
62828 
62829 /* ============================================  GPIO PINCFG122 IRPTEN122 [6..7]  ============================================ */
62830 typedef enum {                                  /*!< GPIO_PINCFG122_IRPTEN122                                                  */
62831   GPIO_PINCFG122_IRPTEN122_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62832   GPIO_PINCFG122_IRPTEN122_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62833                                                      on this GPIO                                                              */
62834   GPIO_PINCFG122_IRPTEN122_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62835                                                      on this GPIO                                                              */
62836   GPIO_PINCFG122_IRPTEN122_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62837                                                      GPIO                                                                      */
62838 } GPIO_PINCFG122_IRPTEN122_Enum;
62839 
62840 /* ============================================  GPIO PINCFG122 FNCSEL122 [0..3]  ============================================ */
62841 typedef enum {                                  /*!< GPIO_PINCFG122_FNCSEL122                                                  */
62842   GPIO_PINCFG122_FNCSEL122_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62843   GPIO_PINCFG122_FNCSEL122_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62844   GPIO_PINCFG122_FNCSEL122_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62845   GPIO_PINCFG122_FNCSEL122_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62846   GPIO_PINCFG122_FNCSEL122_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62847   GPIO_PINCFG122_FNCSEL122_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62848   GPIO_PINCFG122_FNCSEL122_CT122       = 6,     /*!< CT122 : Timer/Counter input or output; Selection of direction
62849                                                      is done via CTIMER register settings.                                     */
62850   GPIO_PINCFG122_FNCSEL122_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62851   GPIO_PINCFG122_FNCSEL122_OBSBUS10    = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
62852   GPIO_PINCFG122_FNCSEL122_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62853   GPIO_PINCFG122_FNCSEL122_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62854   GPIO_PINCFG122_FNCSEL122_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62855   GPIO_PINCFG122_FNCSEL122_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62856   GPIO_PINCFG122_FNCSEL122_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62857   GPIO_PINCFG122_FNCSEL122_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62858   GPIO_PINCFG122_FNCSEL122_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62859 } GPIO_PINCFG122_FNCSEL122_Enum;
62860 
62861 /* =======================================================  PINCFG123  ======================================================= */
62862 /* ============================================  GPIO PINCFG123 OUTCFG123 [8..9]  ============================================ */
62863 typedef enum {                                  /*!< GPIO_PINCFG123_OUTCFG123                                                  */
62864   GPIO_PINCFG123_OUTCFG123_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62865   GPIO_PINCFG123_OUTCFG123_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62866                                                      and 1 values on pin.                                                      */
62867   GPIO_PINCFG123_OUTCFG123_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62868                                                      low, tristate otherwise.                                                  */
62869   GPIO_PINCFG123_OUTCFG123_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62870                                                      drive 0, 1 of HiZ on pin.                                                 */
62871 } GPIO_PINCFG123_OUTCFG123_Enum;
62872 
62873 /* ============================================  GPIO PINCFG123 IRPTEN123 [6..7]  ============================================ */
62874 typedef enum {                                  /*!< GPIO_PINCFG123_IRPTEN123                                                  */
62875   GPIO_PINCFG123_IRPTEN123_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62876   GPIO_PINCFG123_IRPTEN123_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62877                                                      on this GPIO                                                              */
62878   GPIO_PINCFG123_IRPTEN123_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62879                                                      on this GPIO                                                              */
62880   GPIO_PINCFG123_IRPTEN123_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62881                                                      GPIO                                                                      */
62882 } GPIO_PINCFG123_IRPTEN123_Enum;
62883 
62884 /* ============================================  GPIO PINCFG123 FNCSEL123 [0..3]  ============================================ */
62885 typedef enum {                                  /*!< GPIO_PINCFG123_FNCSEL123                                                  */
62886   GPIO_PINCFG123_FNCSEL123_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62887   GPIO_PINCFG123_FNCSEL123_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62888   GPIO_PINCFG123_FNCSEL123_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62889   GPIO_PINCFG123_FNCSEL123_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62890   GPIO_PINCFG123_FNCSEL123_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62891   GPIO_PINCFG123_FNCSEL123_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62892   GPIO_PINCFG123_FNCSEL123_CT123       = 6,     /*!< CT123 : Timer/Counter input or output; Selection of direction
62893                                                      is done via CTIMER register settings.                                     */
62894   GPIO_PINCFG123_FNCSEL123_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62895   GPIO_PINCFG123_FNCSEL123_OBSBUS11    = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
62896   GPIO_PINCFG123_FNCSEL123_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62897   GPIO_PINCFG123_FNCSEL123_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62898   GPIO_PINCFG123_FNCSEL123_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62899   GPIO_PINCFG123_FNCSEL123_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62900   GPIO_PINCFG123_FNCSEL123_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62901   GPIO_PINCFG123_FNCSEL123_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62902   GPIO_PINCFG123_FNCSEL123_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62903 } GPIO_PINCFG123_FNCSEL123_Enum;
62904 
62905 /* =======================================================  PINCFG124  ======================================================= */
62906 /* ============================================  GPIO PINCFG124 OUTCFG124 [8..9]  ============================================ */
62907 typedef enum {                                  /*!< GPIO_PINCFG124_OUTCFG124                                                  */
62908   GPIO_PINCFG124_OUTCFG124_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62909   GPIO_PINCFG124_OUTCFG124_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62910                                                      and 1 values on pin.                                                      */
62911   GPIO_PINCFG124_OUTCFG124_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62912                                                      low, tristate otherwise.                                                  */
62913   GPIO_PINCFG124_OUTCFG124_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62914                                                      drive 0, 1 of HiZ on pin.                                                 */
62915 } GPIO_PINCFG124_OUTCFG124_Enum;
62916 
62917 /* ============================================  GPIO PINCFG124 IRPTEN124 [6..7]  ============================================ */
62918 typedef enum {                                  /*!< GPIO_PINCFG124_IRPTEN124                                                  */
62919   GPIO_PINCFG124_IRPTEN124_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62920   GPIO_PINCFG124_IRPTEN124_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62921                                                      on this GPIO                                                              */
62922   GPIO_PINCFG124_IRPTEN124_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62923                                                      on this GPIO                                                              */
62924   GPIO_PINCFG124_IRPTEN124_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62925                                                      GPIO                                                                      */
62926 } GPIO_PINCFG124_IRPTEN124_Enum;
62927 
62928 /* ============================================  GPIO PINCFG124 FNCSEL124 [0..3]  ============================================ */
62929 typedef enum {                                  /*!< GPIO_PINCFG124_FNCSEL124                                                  */
62930   GPIO_PINCFG124_FNCSEL124_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62931   GPIO_PINCFG124_FNCSEL124_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62932   GPIO_PINCFG124_FNCSEL124_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62933   GPIO_PINCFG124_FNCSEL124_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62934   GPIO_PINCFG124_FNCSEL124_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62935   GPIO_PINCFG124_FNCSEL124_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62936   GPIO_PINCFG124_FNCSEL124_CT124       = 6,     /*!< CT124 : Timer/Counter input or output; Selection of direction
62937                                                      is done via CTIMER register settings.                                     */
62938   GPIO_PINCFG124_FNCSEL124_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62939   GPIO_PINCFG124_FNCSEL124_OBSBUS12    = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
62940   GPIO_PINCFG124_FNCSEL124_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62941   GPIO_PINCFG124_FNCSEL124_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62942   GPIO_PINCFG124_FNCSEL124_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62943   GPIO_PINCFG124_FNCSEL124_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62944   GPIO_PINCFG124_FNCSEL124_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62945   GPIO_PINCFG124_FNCSEL124_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62946   GPIO_PINCFG124_FNCSEL124_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62947 } GPIO_PINCFG124_FNCSEL124_Enum;
62948 
62949 /* =======================================================  PINCFG125  ======================================================= */
62950 /* ============================================  GPIO PINCFG125 OUTCFG125 [8..9]  ============================================ */
62951 typedef enum {                                  /*!< GPIO_PINCFG125_OUTCFG125                                                  */
62952   GPIO_PINCFG125_OUTCFG125_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62953   GPIO_PINCFG125_OUTCFG125_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62954                                                      and 1 values on pin.                                                      */
62955   GPIO_PINCFG125_OUTCFG125_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62956                                                      low, tristate otherwise.                                                  */
62957   GPIO_PINCFG125_OUTCFG125_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62958                                                      drive 0, 1 of HiZ on pin.                                                 */
62959 } GPIO_PINCFG125_OUTCFG125_Enum;
62960 
62961 /* ============================================  GPIO PINCFG125 IRPTEN125 [6..7]  ============================================ */
62962 typedef enum {                                  /*!< GPIO_PINCFG125_IRPTEN125                                                  */
62963   GPIO_PINCFG125_IRPTEN125_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62964   GPIO_PINCFG125_IRPTEN125_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62965                                                      on this GPIO                                                              */
62966   GPIO_PINCFG125_IRPTEN125_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62967                                                      on this GPIO                                                              */
62968   GPIO_PINCFG125_IRPTEN125_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62969                                                      GPIO                                                                      */
62970 } GPIO_PINCFG125_IRPTEN125_Enum;
62971 
62972 /* ============================================  GPIO PINCFG125 FNCSEL125 [0..3]  ============================================ */
62973 typedef enum {                                  /*!< GPIO_PINCFG125_FNCSEL125                                                  */
62974   GPIO_PINCFG125_FNCSEL125_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
62975   GPIO_PINCFG125_FNCSEL125_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62976   GPIO_PINCFG125_FNCSEL125_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62977   GPIO_PINCFG125_FNCSEL125_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62978   GPIO_PINCFG125_FNCSEL125_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62979   GPIO_PINCFG125_FNCSEL125_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62980   GPIO_PINCFG125_FNCSEL125_CT125       = 6,     /*!< CT125 : Timer/Counter input or output; Selection of direction
62981                                                      is done via CTIMER register settings.                                     */
62982   GPIO_PINCFG125_FNCSEL125_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
62983   GPIO_PINCFG125_FNCSEL125_OBSBUS13    = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
62984   GPIO_PINCFG125_FNCSEL125_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62985   GPIO_PINCFG125_FNCSEL125_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62986   GPIO_PINCFG125_FNCSEL125_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
62987   GPIO_PINCFG125_FNCSEL125_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62988   GPIO_PINCFG125_FNCSEL125_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62989   GPIO_PINCFG125_FNCSEL125_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62990   GPIO_PINCFG125_FNCSEL125_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62991 } GPIO_PINCFG125_FNCSEL125_Enum;
62992 
62993 /* =======================================================  PINCFG126  ======================================================= */
62994 /* ============================================  GPIO PINCFG126 OUTCFG126 [8..9]  ============================================ */
62995 typedef enum {                                  /*!< GPIO_PINCFG126_OUTCFG126                                                  */
62996   GPIO_PINCFG126_OUTCFG126_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62997   GPIO_PINCFG126_OUTCFG126_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62998                                                      and 1 values on pin.                                                      */
62999   GPIO_PINCFG126_OUTCFG126_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63000                                                      low, tristate otherwise.                                                  */
63001   GPIO_PINCFG126_OUTCFG126_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63002                                                      drive 0, 1 of HiZ on pin.                                                 */
63003 } GPIO_PINCFG126_OUTCFG126_Enum;
63004 
63005 /* ============================================  GPIO PINCFG126 IRPTEN126 [6..7]  ============================================ */
63006 typedef enum {                                  /*!< GPIO_PINCFG126_IRPTEN126                                                  */
63007   GPIO_PINCFG126_IRPTEN126_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63008   GPIO_PINCFG126_IRPTEN126_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63009                                                      on this GPIO                                                              */
63010   GPIO_PINCFG126_IRPTEN126_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63011                                                      on this GPIO                                                              */
63012   GPIO_PINCFG126_IRPTEN126_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63013                                                      GPIO                                                                      */
63014 } GPIO_PINCFG126_IRPTEN126_Enum;
63015 
63016 /* ============================================  GPIO PINCFG126 FNCSEL126 [0..3]  ============================================ */
63017 typedef enum {                                  /*!< GPIO_PINCFG126_FNCSEL126                                                  */
63018   GPIO_PINCFG126_FNCSEL126_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63019   GPIO_PINCFG126_FNCSEL126_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63020   GPIO_PINCFG126_FNCSEL126_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63021   GPIO_PINCFG126_FNCSEL126_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63022   GPIO_PINCFG126_FNCSEL126_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63023   GPIO_PINCFG126_FNCSEL126_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63024   GPIO_PINCFG126_FNCSEL126_CT126       = 6,     /*!< CT126 : Timer/Counter input or output; Selection of direction
63025                                                      is done via CTIMER register settings.                                     */
63026   GPIO_PINCFG126_FNCSEL126_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63027   GPIO_PINCFG126_FNCSEL126_OBSBUS14    = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
63028   GPIO_PINCFG126_FNCSEL126_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63029   GPIO_PINCFG126_FNCSEL126_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63030   GPIO_PINCFG126_FNCSEL126_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63031   GPIO_PINCFG126_FNCSEL126_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63032   GPIO_PINCFG126_FNCSEL126_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63033   GPIO_PINCFG126_FNCSEL126_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63034   GPIO_PINCFG126_FNCSEL126_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63035 } GPIO_PINCFG126_FNCSEL126_Enum;
63036 
63037 /* =======================================================  PINCFG127  ======================================================= */
63038 /* ============================================  GPIO PINCFG127 OUTCFG127 [8..9]  ============================================ */
63039 typedef enum {                                  /*!< GPIO_PINCFG127_OUTCFG127                                                  */
63040   GPIO_PINCFG127_OUTCFG127_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63041   GPIO_PINCFG127_OUTCFG127_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63042                                                      and 1 values on pin.                                                      */
63043   GPIO_PINCFG127_OUTCFG127_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63044                                                      low, tristate otherwise.                                                  */
63045   GPIO_PINCFG127_OUTCFG127_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63046                                                      drive 0, 1 of HiZ on pin.                                                 */
63047 } GPIO_PINCFG127_OUTCFG127_Enum;
63048 
63049 /* ============================================  GPIO PINCFG127 IRPTEN127 [6..7]  ============================================ */
63050 typedef enum {                                  /*!< GPIO_PINCFG127_IRPTEN127                                                  */
63051   GPIO_PINCFG127_IRPTEN127_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63052   GPIO_PINCFG127_IRPTEN127_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63053                                                      on this GPIO                                                              */
63054   GPIO_PINCFG127_IRPTEN127_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63055                                                      on this GPIO                                                              */
63056   GPIO_PINCFG127_IRPTEN127_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63057                                                      GPIO                                                                      */
63058 } GPIO_PINCFG127_IRPTEN127_Enum;
63059 
63060 /* ============================================  GPIO PINCFG127 FNCSEL127 [0..3]  ============================================ */
63061 typedef enum {                                  /*!< GPIO_PINCFG127_FNCSEL127                                                  */
63062   GPIO_PINCFG127_FNCSEL127_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63063   GPIO_PINCFG127_FNCSEL127_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63064   GPIO_PINCFG127_FNCSEL127_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63065   GPIO_PINCFG127_FNCSEL127_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63066   GPIO_PINCFG127_FNCSEL127_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63067   GPIO_PINCFG127_FNCSEL127_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63068   GPIO_PINCFG127_FNCSEL127_CT127       = 6,     /*!< CT127 : Timer/Counter input or output; Selection of direction
63069                                                      is done via CTIMER register settings.                                     */
63070   GPIO_PINCFG127_FNCSEL127_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63071   GPIO_PINCFG127_FNCSEL127_OBSBUS15    = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
63072   GPIO_PINCFG127_FNCSEL127_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63073   GPIO_PINCFG127_FNCSEL127_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63074   GPIO_PINCFG127_FNCSEL127_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63075   GPIO_PINCFG127_FNCSEL127_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63076   GPIO_PINCFG127_FNCSEL127_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63077   GPIO_PINCFG127_FNCSEL127_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63078   GPIO_PINCFG127_FNCSEL127_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63079 } GPIO_PINCFG127_FNCSEL127_Enum;
63080 
63081 /* ========================================================  PADKEY  ========================================================= */
63082 /* ==============================================  GPIO PADKEY PADKEY [0..31]  =============================================== */
63083 typedef enum {                                  /*!< GPIO_PADKEY_PADKEY                                                        */
63084   GPIO_PADKEY_PADKEY_Key               = 115,   /*!< Key : Key value to unlock the register.                                   */
63085 } GPIO_PADKEY_PADKEY_Enum;
63086 
63087 /* ==========================================================  RD0  ========================================================== */
63088 /* ==========================================================  RD1  ========================================================== */
63089 /* ==========================================================  RD2  ========================================================== */
63090 /* ==========================================================  RD3  ========================================================== */
63091 /* ==========================================================  WT0  ========================================================== */
63092 /* ==========================================================  WT1  ========================================================== */
63093 /* ==========================================================  WT2  ========================================================== */
63094 /* ==========================================================  WT3  ========================================================== */
63095 /* =========================================================  WTS0  ========================================================== */
63096 /* =========================================================  WTS1  ========================================================== */
63097 /* =========================================================  WTS2  ========================================================== */
63098 /* =========================================================  WTS3  ========================================================== */
63099 /* =========================================================  WTC0  ========================================================== */
63100 /* =========================================================  WTC1  ========================================================== */
63101 /* =========================================================  WTC2  ========================================================== */
63102 /* =========================================================  WTC3  ========================================================== */
63103 /* ==========================================================  EN0  ========================================================== */
63104 /* ==========================================================  EN1  ========================================================== */
63105 /* ==========================================================  EN2  ========================================================== */
63106 /* ==========================================================  EN3  ========================================================== */
63107 /* =========================================================  ENS0  ========================================================== */
63108 /* =========================================================  ENS1  ========================================================== */
63109 /* =========================================================  ENS2  ========================================================== */
63110 /* =========================================================  ENS3  ========================================================== */
63111 /* =========================================================  ENC0  ========================================================== */
63112 /* =========================================================  ENC1  ========================================================== */
63113 /* =========================================================  ENC2  ========================================================== */
63114 /* =========================================================  ENC3  ========================================================== */
63115 /* ========================================================  IOM0IRQ  ======================================================== */
63116 /* ========================================================  IOM1IRQ  ======================================================== */
63117 /* ========================================================  IOM2IRQ  ======================================================== */
63118 /* ========================================================  IOM3IRQ  ======================================================== */
63119 /* ========================================================  IOM4IRQ  ======================================================== */
63120 /* ========================================================  IOM5IRQ  ======================================================== */
63121 /* ========================================================  IOM6IRQ  ======================================================== */
63122 /* ========================================================  IOM7IRQ  ======================================================== */
63123 /* =======================================================  SDIFCDWP  ======================================================== */
63124 /* ========================================================  OBSDATA  ======================================================== */
63125 /* ========================================================  IEOBS0  ========================================================= */
63126 /* ========================================================  IEOBS1  ========================================================= */
63127 /* ========================================================  IEOBS2  ========================================================= */
63128 /* ========================================================  IEOBS3  ========================================================= */
63129 /* ========================================================  OEOBS0  ========================================================= */
63130 /* ========================================================  OEOBS1  ========================================================= */
63131 /* ========================================================  OEOBS2  ========================================================= */
63132 /* ========================================================  OEOBS3  ========================================================= */
63133 /* ======================================================  MCUN0INT0EN  ====================================================== */
63134 /* =====================================================  MCUN0INT0STAT  ===================================================== */
63135 /* =====================================================  MCUN0INT0CLR  ====================================================== */
63136 /* =====================================================  MCUN0INT0SET  ====================================================== */
63137 /* ======================================================  MCUN0INT1EN  ====================================================== */
63138 /* =====================================================  MCUN0INT1STAT  ===================================================== */
63139 /* =====================================================  MCUN0INT1CLR  ====================================================== */
63140 /* =====================================================  MCUN0INT1SET  ====================================================== */
63141 /* ======================================================  MCUN0INT2EN  ====================================================== */
63142 /* =====================================================  MCUN0INT2STAT  ===================================================== */
63143 /* =====================================================  MCUN0INT2CLR  ====================================================== */
63144 /* =====================================================  MCUN0INT2SET  ====================================================== */
63145 /* ======================================================  MCUN0INT3EN  ====================================================== */
63146 /* =====================================================  MCUN0INT3STAT  ===================================================== */
63147 /* =====================================================  MCUN0INT3CLR  ====================================================== */
63148 /* =====================================================  MCUN0INT3SET  ====================================================== */
63149 /* ======================================================  MCUN1INT0EN  ====================================================== */
63150 /* =====================================================  MCUN1INT0STAT  ===================================================== */
63151 /* =====================================================  MCUN1INT0CLR  ====================================================== */
63152 /* =====================================================  MCUN1INT0SET  ====================================================== */
63153 /* ======================================================  MCUN1INT1EN  ====================================================== */
63154 /* =====================================================  MCUN1INT1STAT  ===================================================== */
63155 /* =====================================================  MCUN1INT1CLR  ====================================================== */
63156 /* =====================================================  MCUN1INT1SET  ====================================================== */
63157 /* ======================================================  MCUN1INT2EN  ====================================================== */
63158 /* =====================================================  MCUN1INT2STAT  ===================================================== */
63159 /* =====================================================  MCUN1INT2CLR  ====================================================== */
63160 /* =====================================================  MCUN1INT2SET  ====================================================== */
63161 /* ======================================================  MCUN1INT3EN  ====================================================== */
63162 /* =====================================================  MCUN1INT3STAT  ===================================================== */
63163 /* =====================================================  MCUN1INT3CLR  ====================================================== */
63164 /* =====================================================  MCUN1INT3SET  ====================================================== */
63165 /* =====================================================  DSP0N0INT0EN  ====================================================== */
63166 /* ====================================================  DSP0N0INT0STAT  ===================================================== */
63167 /* =====================================================  DSP0N0INT0CLR  ===================================================== */
63168 /* =====================================================  DSP0N0INT0SET  ===================================================== */
63169 /* =====================================================  DSP0N0INT1EN  ====================================================== */
63170 /* ====================================================  DSP0N0INT1STAT  ===================================================== */
63171 /* =====================================================  DSP0N0INT1CLR  ===================================================== */
63172 /* =====================================================  DSP0N0INT1SET  ===================================================== */
63173 /* =====================================================  DSP0N0INT2EN  ====================================================== */
63174 /* ====================================================  DSP0N0INT2STAT  ===================================================== */
63175 /* =====================================================  DSP0N0INT2CLR  ===================================================== */
63176 /* =====================================================  DSP0N0INT2SET  ===================================================== */
63177 /* =====================================================  DSP0N0INT3EN  ====================================================== */
63178 /* ====================================================  DSP0N0INT3STAT  ===================================================== */
63179 /* =====================================================  DSP0N0INT3CLR  ===================================================== */
63180 /* =====================================================  DSP0N0INT3SET  ===================================================== */
63181 /* =====================================================  DSP0N1INT0EN  ====================================================== */
63182 /* ====================================================  DSP0N1INT0STAT  ===================================================== */
63183 /* =====================================================  DSP0N1INT0CLR  ===================================================== */
63184 /* =====================================================  DSP0N1INT0SET  ===================================================== */
63185 /* =====================================================  DSP0N1INT1EN  ====================================================== */
63186 /* ====================================================  DSP0N1INT1STAT  ===================================================== */
63187 /* =====================================================  DSP0N1INT1CLR  ===================================================== */
63188 /* =====================================================  DSP0N1INT1SET  ===================================================== */
63189 /* =====================================================  DSP0N1INT2EN  ====================================================== */
63190 /* ====================================================  DSP0N1INT2STAT  ===================================================== */
63191 /* =====================================================  DSP0N1INT2CLR  ===================================================== */
63192 /* =====================================================  DSP0N1INT2SET  ===================================================== */
63193 /* =====================================================  DSP0N1INT3EN  ====================================================== */
63194 /* ====================================================  DSP0N1INT3STAT  ===================================================== */
63195 /* =====================================================  DSP0N1INT3CLR  ===================================================== */
63196 /* =====================================================  DSP0N1INT3SET  ===================================================== */
63197 /* =====================================================  DSP1N0INT0EN  ====================================================== */
63198 /* ====================================================  DSP1N0INT0STAT  ===================================================== */
63199 /* =====================================================  DSP1N0INT0CLR  ===================================================== */
63200 /* =====================================================  DSP1N0INT0SET  ===================================================== */
63201 /* =====================================================  DSP1N0INT1EN  ====================================================== */
63202 /* ====================================================  DSP1N0INT1STAT  ===================================================== */
63203 /* =====================================================  DSP1N0INT1CLR  ===================================================== */
63204 /* =====================================================  DSP1N0INT1SET  ===================================================== */
63205 /* =====================================================  DSP1N0INT2EN  ====================================================== */
63206 /* ====================================================  DSP1N0INT2STAT  ===================================================== */
63207 /* =====================================================  DSP1N0INT2CLR  ===================================================== */
63208 /* =====================================================  DSP1N0INT2SET  ===================================================== */
63209 /* =====================================================  DSP1N0INT3EN  ====================================================== */
63210 /* ====================================================  DSP1N0INT3STAT  ===================================================== */
63211 /* =====================================================  DSP1N0INT3CLR  ===================================================== */
63212 /* =====================================================  DSP1N0INT3SET  ===================================================== */
63213 /* =====================================================  DSP1N1INT0EN  ====================================================== */
63214 /* ====================================================  DSP1N1INT0STAT  ===================================================== */
63215 /* =====================================================  DSP1N1INT0CLR  ===================================================== */
63216 /* =====================================================  DSP1N1INT0SET  ===================================================== */
63217 /* =====================================================  DSP1N1INT1EN  ====================================================== */
63218 /* ====================================================  DSP1N1INT1STAT  ===================================================== */
63219 /* =====================================================  DSP1N1INT1CLR  ===================================================== */
63220 /* =====================================================  DSP1N1INT1SET  ===================================================== */
63221 /* =====================================================  DSP1N1INT2EN  ====================================================== */
63222 /* ====================================================  DSP1N1INT2STAT  ===================================================== */
63223 /* =====================================================  DSP1N1INT2CLR  ===================================================== */
63224 /* =====================================================  DSP1N1INT2SET  ===================================================== */
63225 /* =====================================================  DSP1N1INT3EN  ====================================================== */
63226 /* ====================================================  DSP1N1INT3STAT  ===================================================== */
63227 /* =====================================================  DSP1N1INT3CLR  ===================================================== */
63228 /* =====================================================  DSP1N1INT3SET  ===================================================== */
63229 
63230 
63231 /* =========================================================================================================================== */
63232 /* ================                                            GPU                                            ================ */
63233 /* =========================================================================================================================== */
63234 
63235 /* =======================================================  TEX0BASE  ======================================================== */
63236 /* ======================================================  TEX0STRIDE  ======================================================= */
63237 /* ============================================  GPU TEX0STRIDE IMGFMT [24..31]  ============================================= */
63238 typedef enum {                                  /*!< GPU_TEX0STRIDE_IMGFMT                                                     */
63239   GPU_TEX0STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
63240                                                      has an alpha channel, but it is ignored, and is always
63241                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
63242                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
63243                                                      bits.                                                                     */
63244   GPU_TEX0STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
63245                                                      is always on: 32-bit)                                                     */
63246   GPU_TEX0STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
63247   GPU_TEX0STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
63248                                                      intensity of each channel sample is defined by 8 bits,
63249                                                      and are arranged in memory in such manner that a single
63250                                                      32-bit unsigned integer has the alpha sample in the highest
63251                                                      8 bits, followed by the red sample, green sample and finally
63252                                                      the blue sample in the lowest 8 bits                                      */
63253   GPU_TEX0STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
63254   GPU_TEX0STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
63255   GPU_TEX0STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
63256   GPU_TEX0STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
63257   GPU_TEX0STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
63258   GPU_TEX0STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
63259 } GPU_TEX0STRIDE_IMGFMT_Enum;
63260 
63261 /* ============================================  GPU TEX0STRIDE IMGMODE [16..23]  ============================================ */
63262 typedef enum {                                  /*!< GPU_TEX0STRIDE_IMGMODE                                                    */
63263   GPU_TEX0STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
63264                                                      bitmap image. Nearest neighbor sampling.                                  */
63265   GPU_TEX0STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
63266                                                      a bitmap image. A method used to smooth textures when displayed
63267                                                      larger or smaller than they actually are.                                 */
63268 } GPU_TEX0STRIDE_IMGMODE_Enum;
63269 
63270 /* ========================================================  TEX0RES  ======================================================== */
63271 /* =======================================================  TEX1BASE  ======================================================== */
63272 /* ======================================================  TEX1STRIDE  ======================================================= */
63273 /* ============================================  GPU TEX1STRIDE IMGFMT [24..31]  ============================================= */
63274 typedef enum {                                  /*!< GPU_TEX1STRIDE_IMGFMT                                                     */
63275   GPU_TEX1STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
63276                                                      has an alpha channel, but it is ignored, and is always
63277                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
63278                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
63279                                                      bits.                                                                     */
63280   GPU_TEX1STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
63281                                                      is always on: 32-bit)                                                     */
63282   GPU_TEX1STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
63283   GPU_TEX1STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
63284                                                      intensity of each channel sample is defined by 8 bits,
63285                                                      and are arranged in memory in such manner that a single
63286                                                      32-bit unsigned integer has the alpha sample in the highest
63287                                                      8 bits, followed by the red sample, green sample and finally
63288                                                      the blue sample in the lowest 8 bits                                      */
63289   GPU_TEX1STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
63290   GPU_TEX1STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
63291   GPU_TEX1STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
63292   GPU_TEX1STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
63293   GPU_TEX1STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
63294   GPU_TEX1STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
63295 } GPU_TEX1STRIDE_IMGFMT_Enum;
63296 
63297 /* ============================================  GPU TEX1STRIDE IMGMODE [16..23]  ============================================ */
63298 typedef enum {                                  /*!< GPU_TEX1STRIDE_IMGMODE                                                    */
63299   GPU_TEX1STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
63300                                                      bitmap image. Nearest neighbor sampling.                                  */
63301   GPU_TEX1STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
63302                                                      a bitmap image. A method used to smooth textures when displayed
63303                                                      larger or smaller than they actually are.                                 */
63304 } GPU_TEX1STRIDE_IMGMODE_Enum;
63305 
63306 /* ========================================================  TEX1RES  ======================================================== */
63307 /* =======================================================  TEX1COLOR  ======================================================= */
63308 /* =======================================================  TEX2BASE  ======================================================== */
63309 /* ======================================================  TEX2STRIDE  ======================================================= */
63310 /* ============================================  GPU TEX2STRIDE IMGFMT [24..31]  ============================================= */
63311 typedef enum {                                  /*!< GPU_TEX2STRIDE_IMGFMT                                                     */
63312   GPU_TEX2STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
63313                                                      has an alpha channel, but it is ignored, and is always
63314                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
63315                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
63316                                                      bits.                                                                     */
63317   GPU_TEX2STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
63318                                                      is always on: 32-bit)                                                     */
63319   GPU_TEX2STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
63320   GPU_TEX2STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
63321                                                      intensity of each channel sample is defined by 8 bits,
63322                                                      and are arranged in memory in such manner that a single
63323                                                      32-bit unsigned integer has the alpha sample in the highest
63324                                                      8 bits, followed by the red sample, green sample and finally
63325                                                      the blue sample in the lowest 8 bits                                      */
63326   GPU_TEX2STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
63327   GPU_TEX2STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
63328   GPU_TEX2STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
63329   GPU_TEX2STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
63330   GPU_TEX2STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
63331   GPU_TEX2STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
63332 } GPU_TEX2STRIDE_IMGFMT_Enum;
63333 
63334 /* ============================================  GPU TEX2STRIDE IMGMODE [16..23]  ============================================ */
63335 typedef enum {                                  /*!< GPU_TEX2STRIDE_IMGMODE                                                    */
63336   GPU_TEX2STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
63337                                                      bitmap image. Nearest neighbor sampling.                                  */
63338   GPU_TEX2STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
63339                                                      a bitmap image. A method used to smooth textures when displayed
63340                                                      larger or smaller than they actually are.                                 */
63341 } GPU_TEX2STRIDE_IMGMODE_Enum;
63342 
63343 /* ========================================================  TEX2RES  ======================================================== */
63344 /* =======================================================  TEX3BASE  ======================================================== */
63345 /* ======================================================  TEX3STRIDE  ======================================================= */
63346 /* ============================================  GPU TEX3STRIDE IMGFMT [24..31]  ============================================= */
63347 typedef enum {                                  /*!< GPU_TEX3STRIDE_IMGFMT                                                     */
63348   GPU_TEX3STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
63349                                                      has an alpha channel, but it is ignored, and is always
63350                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
63351                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
63352                                                      bits.                                                                     */
63353   GPU_TEX3STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
63354                                                      is always on: 32-bit)                                                     */
63355   GPU_TEX3STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
63356   GPU_TEX3STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
63357                                                      intensity of each channel sample is defined by 8 bits,
63358                                                      and are arranged in memory in such manner that a single
63359                                                      32-bit unsigned integer has the alpha sample in the highest
63360                                                      8 bits, followed by the red sample, green sample and finally
63361                                                      the blue sample in the lowest 8 bits                                      */
63362   GPU_TEX3STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
63363   GPU_TEX3STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
63364   GPU_TEX3STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
63365   GPU_TEX3STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
63366   GPU_TEX3STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
63367   GPU_TEX3STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
63368 } GPU_TEX3STRIDE_IMGFMT_Enum;
63369 
63370 /* ============================================  GPU TEX3STRIDE IMGMODE [16..23]  ============================================ */
63371 typedef enum {                                  /*!< GPU_TEX3STRIDE_IMGMODE                                                    */
63372   GPU_TEX3STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
63373                                                      bitmap image.                                                             */
63374   GPU_TEX3STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
63375                                                      a bitmap image. A method used to smooth textures when displayed
63376                                                      larger or smaller than they actually are.                                 */
63377 } GPU_TEX3STRIDE_IMGMODE_Enum;
63378 
63379 /* ========================================================  TEX3RES  ======================================================== */
63380 /* =========================================================  CGCMD  ========================================================= */
63381 /* ========================================================  CGCTRL  ========================================================= */
63382 /* =====================================================  DIRTYTRIGMIN  ====================================================== */
63383 /* =====================================================  DIRTYTRIGMAX  ====================================================== */
63384 /* ========================================================  STATUS  ========================================================= */
63385 /* ========================================================  BUSCTRL  ======================================================== */
63386 /* ======================================================  IMEMLDIADDR  ====================================================== */
63387 /* =====================================================  IMEMLDIDATAHL  ===================================================== */
63388 /* =====================================================  IMEMLDIDATAHH  ===================================================== */
63389 /* =====================================================  CMDLISTSTATUS  ===================================================== */
63390 /* ====================================================  CMDLISTRINGSTOP  ==================================================== */
63391 /* ======================================================  CMDLISTADDR  ====================================================== */
63392 /* ======================================================  CMDLISTSIZE  ====================================================== */
63393 /* =====================================================  INTERRUPTCTRL  ===================================================== */
63394 /* =======================================================  SYSCLEAR  ======================================================== */
63395 /* ========================================================  DRAWCMD  ======================================================== */
63396 /* ===============================================  GPU DRAWCMD START [0..2]  ================================================ */
63397 typedef enum {                                  /*!< GPU_DRAWCMD_START                                                         */
63398   GPU_DRAWCMD_START_PIXEL              = 0,     /*!< PIXEL : draw pixel using STARTXY                                          */
63399   GPU_DRAWCMD_START_LINE               = 1,     /*!< LINE : draw line from STARTXY to ENDXY                                    */
63400   GPU_DRAWCMD_START_RECT               = 2,     /*!< RECT : fill rectangle from STARTXY to ENDXY                               */
63401   GPU_DRAWCMD_START_TRI                = 3,     /*!< TRI : draw triangle (if enabled)                                          */
63402   GPU_DRAWCMD_START_QUAD               = 4,     /*!< QUAD : draw quadrilateral (if enabled)                                    */
63403 } GPU_DRAWCMD_START_Enum;
63404 
63405 /* ========================================================  DRAWPT0  ======================================================== */
63406 /* ========================================================  DRAWPT1  ======================================================== */
63407 /* ========================================================  CLIPMIN  ======================================================== */
63408 /* ========================================================  CLIPMAX  ======================================================== */
63409 /* =======================================================  RASTCTRL  ======================================================== */
63410 /* ======================================================  DRAWCODEPTR  ====================================================== */
63411 /* =======================================================  DRAWPT0X  ======================================================== */
63412 /* =======================================================  DRAWPT0Y  ======================================================== */
63413 /* =======================================================  DRAWPT0Z  ======================================================== */
63414 /* =======================================================  DRAWCOLOR  ======================================================= */
63415 /* =======================================================  DRAWPT1X  ======================================================== */
63416 /* =======================================================  DRAWPT1Y  ======================================================== */
63417 /* =======================================================  DRAWPT1Z  ======================================================== */
63418 /* =======================================================  DRAWPT2X  ======================================================== */
63419 /* =======================================================  DRAWPT2Y  ======================================================== */
63420 /* =======================================================  DRAWPT2Z  ======================================================== */
63421 /* =======================================================  DRAWPT3X  ======================================================== */
63422 /* =======================================================  DRAWPT3Y  ======================================================== */
63423 /* =======================================================  DRAWPT3Z  ======================================================== */
63424 /* =========================================================  MM00  ========================================================== */
63425 /* =========================================================  MM01  ========================================================== */
63426 /* =========================================================  MM02  ========================================================== */
63427 /* =========================================================  MM10  ========================================================== */
63428 /* =========================================================  MM11  ========================================================== */
63429 /* =========================================================  MM12  ========================================================== */
63430 /* =========================================================  MM20  ========================================================== */
63431 /* =========================================================  MM21  ========================================================== */
63432 /* =========================================================  MM22  ========================================================== */
63433 /* ======================================================  DEPTHSTARTL  ====================================================== */
63434 /* ======================================================  DEPTHSTARTH  ====================================================== */
63435 /* =======================================================  DEPTHDXL  ======================================================== */
63436 /* =======================================================  DEPTHDXH  ======================================================== */
63437 /* =======================================================  DEPTHDYL  ======================================================== */
63438 /* =======================================================  DEPTHDYH  ======================================================== */
63439 /* =========================================================  REDX  ========================================================== */
63440 /* =========================================================  REDY  ========================================================== */
63441 /* ========================================================  GREENX  ========================================================= */
63442 /* ========================================================  GREENY  ========================================================= */
63443 /* =========================================================  BLUEX  ========================================================= */
63444 /* =========================================================  BLUEY  ========================================================= */
63445 /* =========================================================  ALFX  ========================================================== */
63446 /* =========================================================  ALFY  ========================================================== */
63447 /* ========================================================  REDINIT  ======================================================== */
63448 /* ========================================================  GREINIT  ======================================================== */
63449 /* ========================================================  BLUINIT  ======================================================== */
63450 /* ========================================================  ALFINIT  ======================================================== */
63451 /* =========================================================  IDREG  ========================================================= */
63452 /* =======================================================  LOADCTRL  ======================================================== */
63453 /* =========================================================  C0REG  ========================================================= */
63454 /* =========================================================  C1REG  ========================================================= */
63455 /* =========================================================  C2REG  ========================================================= */
63456 /* =========================================================  C3REG  ========================================================= */
63457 /* =========================================================  IRQID  ========================================================= */
63458 
63459 
63460 /* =========================================================================================================================== */
63461 /* ================                                           I2S0                                            ================ */
63462 /* =========================================================================================================================== */
63463 
63464 /* ========================================================  RXDATA  ========================================================= */
63465 /* =======================================================  RXCHANID  ======================================================== */
63466 /* =====================================================  RXFIFOSTATUS  ====================================================== */
63467 /* ======================================================  RXFIFOSIZE  ======================================================= */
63468 /* =====================================================  RXUPPERLIMIT  ====================================================== */
63469 /* ========================================================  TXDATA  ========================================================= */
63470 /* =======================================================  TXCHANID  ======================================================== */
63471 /* =====================================================  TXFIFOSTATUS  ====================================================== */
63472 /* ======================================================  TXFIFOSIZE  ======================================================= */
63473 /* =====================================================  TXLOWERLIMIT  ====================================================== */
63474 /* ======================================================  I2SDATACFG  ======================================================= */
63475 /* ============================================  I2S0 I2SDATACFG FRLEN2 [24..30]  ============================================ */
63476 typedef enum {                                  /*!< I2S0_I2SDATACFG_FRLEN2                                                    */
63477   I2S0_I2SDATACFG_FRLEN2_1CHLS         = 0,     /*!< 1CHLS : One channel in phase 2.                                           */
63478   I2S0_I2SDATACFG_FRLEN2_2CHLS         = 1,     /*!< 2CHLS : Two channels in phase 2.                                          */
63479   I2S0_I2SDATACFG_FRLEN2_3CHLS         = 2,     /*!< 3CHLS : Three channels in phase 2.                                        */
63480   I2S0_I2SDATACFG_FRLEN2_4CHLS         = 3,     /*!< 4CHLS : Four channels in phase 2.                                         */
63481   I2S0_I2SDATACFG_FRLEN2_5CHLS         = 4,     /*!< 5CHLS : Five channels in phase 2.                                         */
63482   I2S0_I2SDATACFG_FRLEN2_6CHLS         = 5,     /*!< 6CHLS : Six channels in phase 2.                                          */
63483   I2S0_I2SDATACFG_FRLEN2_7CHLS         = 6,     /*!< 7CHLS : Seven channels in phase 2.                                        */
63484   I2S0_I2SDATACFG_FRLEN2_8CHLS         = 7,     /*!< 8CHLS : Eight channels in phase 2.                                        */
63485 } I2S0_I2SDATACFG_FRLEN2_Enum;
63486 
63487 /* ============================================  I2S0 I2SDATACFG WDLEN2 [21..23]  ============================================ */
63488 typedef enum {                                  /*!< I2S0_I2SDATACFG_WDLEN2                                                    */
63489   I2S0_I2SDATACFG_WDLEN2_8b            = 0,     /*!< 8b : Receive channel length is 8 bits for phase 2.                        */
63490   I2S0_I2SDATACFG_WDLEN2_16b           = 2,     /*!< 16b : Receive channel length is 16 bits for phase 2.                      */
63491   I2S0_I2SDATACFG_WDLEN2_24b           = 4,     /*!< 24b : Receive channel length is 24 bits for phase 2.                      */
63492   I2S0_I2SDATACFG_WDLEN2_32b           = 5,     /*!< 32b : Receive channel length is 32 bits for phase 2.                      */
63493 } I2S0_I2SDATACFG_WDLEN2_Enum;
63494 
63495 /* =============================================  I2S0 I2SDATACFG SSZ2 [16..18]  ============================================= */
63496 typedef enum {                                  /*!< I2S0_I2SDATACFG_SSZ2                                                      */
63497   I2S0_I2SDATACFG_SSZ2_8b              = 0,     /*!< 8b : Receive audio sample length is 8 bits for phase 2.                   */
63498   I2S0_I2SDATACFG_SSZ2_16b             = 2,     /*!< 16b : Receive audio sample length is 16 bits for phase 2.                 */
63499   I2S0_I2SDATACFG_SSZ2_24b             = 4,     /*!< 24b : Receive audio sample length is 24 bits for phase 2.                 */
63500   I2S0_I2SDATACFG_SSZ2_32b             = 5,     /*!< 32b : Receive audio sample length is 32 bits for phase 2.                 */
63501 } I2S0_I2SDATACFG_SSZ2_Enum;
63502 
63503 /* ============================================  I2S0 I2SDATACFG FRLEN1 [8..14]  ============================================= */
63504 typedef enum {                                  /*!< I2S0_I2SDATACFG_FRLEN1                                                    */
63505   I2S0_I2SDATACFG_FRLEN1_1CHLS         = 0,     /*!< 1CHLS : One channel in phase 1.                                           */
63506   I2S0_I2SDATACFG_FRLEN1_2CHLS         = 1,     /*!< 2CHLS : Two channels in phase 1.                                          */
63507   I2S0_I2SDATACFG_FRLEN1_3CHLS         = 2,     /*!< 3CHLS : Three channels in phase 1.                                        */
63508   I2S0_I2SDATACFG_FRLEN1_4CHLS         = 3,     /*!< 4CHLS : Four channels in phase 1.                                         */
63509   I2S0_I2SDATACFG_FRLEN1_5CHLS         = 4,     /*!< 5CHLS : Five channels in phase 1.                                         */
63510   I2S0_I2SDATACFG_FRLEN1_6CHLS         = 5,     /*!< 6CHLS : Six channels in phase 1.                                          */
63511   I2S0_I2SDATACFG_FRLEN1_7CHLS         = 6,     /*!< 7CHLS : Seven channels in phase 1.                                        */
63512   I2S0_I2SDATACFG_FRLEN1_8CHLS         = 7,     /*!< 8CHLS : Eight channels in phase 1.                                        */
63513 } I2S0_I2SDATACFG_FRLEN1_Enum;
63514 
63515 /* =============================================  I2S0 I2SDATACFG WDLEN1 [5..7]  ============================================= */
63516 typedef enum {                                  /*!< I2S0_I2SDATACFG_WDLEN1                                                    */
63517   I2S0_I2SDATACFG_WDLEN1_8b            = 0,     /*!< 8b : Receive channel length is 8 bits for phase 1.                        */
63518   I2S0_I2SDATACFG_WDLEN1_16b           = 2,     /*!< 16b : Receive channel length is 16 bits for phase 1.                      */
63519   I2S0_I2SDATACFG_WDLEN1_24b           = 4,     /*!< 24b : Receive channel length is 24 bits for phase 1.                      */
63520   I2S0_I2SDATACFG_WDLEN1_32b           = 5,     /*!< 32b : Receive channel length is 32 bits for phase 1.                      */
63521 } I2S0_I2SDATACFG_WDLEN1_Enum;
63522 
63523 /* ==============================================  I2S0 I2SDATACFG SSZ1 [0..2]  ============================================== */
63524 typedef enum {                                  /*!< I2S0_I2SDATACFG_SSZ1                                                      */
63525   I2S0_I2SDATACFG_SSZ1_8b              = 0,     /*!< 8b : Receive audio sample length is 8 bits for phase 1.                   */
63526   I2S0_I2SDATACFG_SSZ1_16b             = 2,     /*!< 16b : Receive audio sample length is 16 bits for phase 1.                 */
63527   I2S0_I2SDATACFG_SSZ1_24b             = 4,     /*!< 24b : Receive audio sample length is 24 bits for phase 1.                 */
63528   I2S0_I2SDATACFG_SSZ1_32b             = 5,     /*!< 32b : Receive audio sample length is 32 bits for phase 1.                 */
63529 } I2S0_I2SDATACFG_SSZ1_Enum;
63530 
63531 /* =======================================================  I2SIOCFG  ======================================================== */
63532 /* ========================================================  I2SCTL  ========================================================= */
63533 /* ========================================================  IPBIRPT  ======================================================== */
63534 /* =======================================================  IPCOREID  ======================================================== */
63535 /* ========================================================  AMQCFG  ========================================================= */
63536 /* ========================================================  INTDIV  ========================================================= */
63537 /* ========================================================  FRACDIV  ======================================================== */
63538 /* ========================================================  CLKCFG  ========================================================= */
63539 /* ========================================================  DMACFG  ========================================================= */
63540 /* ==============================================  I2S0 DMACFG TXDMAPRI [5..5]  ============================================== */
63541 typedef enum {                                  /*!< I2S0_DMACFG_TXDMAPRI                                                      */
63542   I2S0_DMACFG_TXDMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
63543   I2S0_DMACFG_TXDMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
63544 } I2S0_DMACFG_TXDMAPRI_Enum;
63545 
63546 /* ==============================================  I2S0 DMACFG TXDMAEN [4..4]  =============================================== */
63547 typedef enum {                                  /*!< I2S0_DMACFG_TXDMAEN                                                       */
63548   I2S0_DMACFG_TXDMAEN_DIS              = 0,     /*!< DIS : Disable TXDMA Function                                              */
63549   I2S0_DMACFG_TXDMAEN_EN               = 1,     /*!< EN : Enable TXDMA Function                                                */
63550 } I2S0_DMACFG_TXDMAEN_Enum;
63551 
63552 /* ==============================================  I2S0 DMACFG RXDMAPRI [1..1]  ============================================== */
63553 typedef enum {                                  /*!< I2S0_DMACFG_RXDMAPRI                                                      */
63554   I2S0_DMACFG_RXDMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
63555   I2S0_DMACFG_RXDMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
63556 } I2S0_DMACFG_RXDMAPRI_Enum;
63557 
63558 /* ==============================================  I2S0 DMACFG RXDMAEN [0..0]  =============================================== */
63559 typedef enum {                                  /*!< I2S0_DMACFG_RXDMAEN                                                       */
63560   I2S0_DMACFG_RXDMAEN_DIS              = 0,     /*!< DIS : Disable RXDMA Function                                              */
63561   I2S0_DMACFG_RXDMAEN_EN               = 1,     /*!< EN : Enable RXDMA Function                                                */
63562 } I2S0_DMACFG_RXDMAEN_Enum;
63563 
63564 /* ======================================================  RXDMATOTCNT  ====================================================== */
63565 /* =======================================================  RXDMAADDR  ======================================================= */
63566 /* =======================================================  RXDMASTAT  ======================================================= */
63567 /* ======================================================  TXDMATOTCNT  ====================================================== */
63568 /* =======================================================  TXDMAADDR  ======================================================= */
63569 /* =======================================================  TXDMASTAT  ======================================================= */
63570 /* ========================================================  STATUS  ========================================================= */
63571 /* =========================================================  INTEN  ========================================================= */
63572 /* ========================================================  INTSTAT  ======================================================== */
63573 /* ========================================================  INTCLR  ========================================================= */
63574 /* ========================================================  INTSET  ========================================================= */
63575 /* ========================================================  I2SDBG  ========================================================= */
63576 
63577 
63578 /* =========================================================================================================================== */
63579 /* ================                                           IOM0                                            ================ */
63580 /* =========================================================================================================================== */
63581 
63582 /* =========================================================  FIFO  ========================================================== */
63583 /* ========================================================  FIFOPTR  ======================================================== */
63584 /* ========================================================  FIFOTHR  ======================================================== */
63585 /* ========================================================  FIFOPOP  ======================================================== */
63586 /* =======================================================  FIFOPUSH  ======================================================== */
63587 /* =======================================================  FIFOCTRL  ======================================================== */
63588 /* ========================================================  FIFOLOC  ======================================================== */
63589 /* ========================================================  CLKCFG  ========================================================= */
63590 /* ==============================================  IOM0 CLKCFG DIVEN [12..12]  =============================================== */
63591 typedef enum {                                  /*!< IOM0_CLKCFG_DIVEN                                                         */
63592   IOM0_CLKCFG_DIVEN_DIS                = 0,     /*!< DIS : Disable TOTPER division.                                            */
63593   IOM0_CLKCFG_DIVEN_EN                 = 1,     /*!< EN : Enable TOTPER division.                                              */
63594 } IOM0_CLKCFG_DIVEN_Enum;
63595 
63596 /* ===============================================  IOM0 CLKCFG DIV3 [11..11]  =============================================== */
63597 typedef enum {                                  /*!< IOM0_CLKCFG_DIV3                                                          */
63598   IOM0_CLKCFG_DIV3_DIS                 = 0,     /*!< DIS : Select divide by 1.                                                 */
63599   IOM0_CLKCFG_DIV3_EN                  = 1,     /*!< EN : Select divide by 3.                                                  */
63600 } IOM0_CLKCFG_DIV3_Enum;
63601 
63602 /* ===============================================  IOM0 CLKCFG FSEL [8..10]  ================================================ */
63603 typedef enum {                                  /*!< IOM0_CLKCFG_FSEL                                                          */
63604   IOM0_CLKCFG_FSEL_MIN_PWR             = 0,     /*!< MIN_PWR : Selects the minimum power clock. This setting should
63605                                                      be used whenever the IOM is not active.                                   */
63606   IOM0_CLKCFG_FSEL_OFF                 = 1,     /*!< OFF : Selects static 0 as the input clock. Previously 96Mhz
63607                                                      setting                                                                   */
63608   IOM0_CLKCFG_FSEL_HFRC48MHZ           = 2,     /*!< HFRC48MHZ : Selects the HFRC 48MHz as the input clock.                    */
63609   IOM0_CLKCFG_FSEL_HFRC24MHZ           = 3,     /*!< HFRC24MHZ : Selects the HFRC 24MHz as the input clock.                    */
63610   IOM0_CLKCFG_FSEL_HFRC12MHZ           = 4,     /*!< HFRC12MHZ : Selects the HFRC 12MHz as the input clock.                    */
63611   IOM0_CLKCFG_FSEL_HFRC6MHZ            = 5,     /*!< HFRC6MHZ : Selects the HFRC 6MHz as the input clock.                      */
63612   IOM0_CLKCFG_FSEL_HFRC3MHZ            = 6,     /*!< HFRC3MHZ : Selects the HFRC 3MHz as the input clock.                      */
63613   IOM0_CLKCFG_FSEL_HFRC1p5MHZ          = 7,     /*!< HFRC1p5MHZ : Selects the HFRC 1.5MHz as the input clock.                  */
63614 } IOM0_CLKCFG_FSEL_Enum;
63615 
63616 /* ======================================================  SUBMODCTRL  ======================================================= */
63617 /* ===========================================  IOM0 SUBMODCTRL SMOD2TYPE [9..11]  =========================================== */
63618 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD2TYPE                                                 */
63619   IOM0_SUBMODCTRL_SMOD2TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
63620   IOM0_SUBMODCTRL_SMOD2TYPE_MI2C       = 1,     /*!< MI2C : MI2C submodule                                                     */
63621   IOM0_SUBMODCTRL_SMOD2TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
63622   IOM0_SUBMODCTRL_SMOD2TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
63623   IOM0_SUBMODCTRL_SMOD2TYPE_MSI2S      = 4,     /*!< MSI2S : Master/Slave submodule                                            */
63624   IOM0_SUBMODCTRL_SMOD2TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
63625 } IOM0_SUBMODCTRL_SMOD2TYPE_Enum;
63626 
63627 /* ===========================================  IOM0 SUBMODCTRL SMOD1TYPE [5..7]  ============================================ */
63628 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD1TYPE                                                 */
63629   IOM0_SUBMODCTRL_SMOD1TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
63630   IOM0_SUBMODCTRL_SMOD1TYPE_MI2C       = 1,     /*!< MI2C : MI2C submodule                                                     */
63631   IOM0_SUBMODCTRL_SMOD1TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
63632   IOM0_SUBMODCTRL_SMOD1TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
63633   IOM0_SUBMODCTRL_SMOD1TYPE_MSI2S      = 4,     /*!< MSI2S : Master/Slave submodule                                            */
63634   IOM0_SUBMODCTRL_SMOD1TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
63635 } IOM0_SUBMODCTRL_SMOD1TYPE_Enum;
63636 
63637 /* ===========================================  IOM0 SUBMODCTRL SMOD0TYPE [1..3]  ============================================ */
63638 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD0TYPE                                                 */
63639   IOM0_SUBMODCTRL_SMOD0TYPE_MSPI       = 0,     /*!< MSPI : MSPI submodule                                                     */
63640   IOM0_SUBMODCTRL_SMOD0TYPE_MI2C       = 1,     /*!< MI2C : I2C Master submodule                                               */
63641   IOM0_SUBMODCTRL_SMOD0TYPE_MSI2S      = 2,     /*!< MSI2S : I2S Master/Slave Module                                           */
63642   IOM0_SUBMODCTRL_SMOD0TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
63643 } IOM0_SUBMODCTRL_SMOD0TYPE_Enum;
63644 
63645 /* ==========================================================  CMD  ========================================================== */
63646 /* ==================================================  IOM0 CMD CMD [0..3]  ================================================== */
63647 typedef enum {                                  /*!< IOM0_CMD_CMD                                                              */
63648   IOM0_CMD_CMD_WRITE                   = 1,     /*!< WRITE : Write command using count of offset bytes specified
63649                                                      in the OFFSETCNT field                                                    */
63650   IOM0_CMD_CMD_READ                    = 2,     /*!< READ : Read command using count of offset bytes specified in
63651                                                      the OFFSETCNT field                                                       */
63652   IOM0_CMD_CMD_TMW                     = 3,     /*!< TMW : SPI only. Test mode to do constant write operations. Useful
63653                                                      for debug and power measurements. Will continually send
63654                                                      data in OFFSET field                                                      */
63655   IOM0_CMD_CMD_TMR                     = 4,     /*!< TMR : SPI Only. Test mode to do constant read operations. Useful
63656                                                      for debug and power measurements. Will continually read
63657                                                      data from external input                                                  */
63658 } IOM0_CMD_CMD_Enum;
63659 
63660 /* ========================================================  DCXCTRL  ======================================================== */
63661 /* =======================================================  OFFSETHI  ======================================================== */
63662 /* ========================================================  CMDSTAT  ======================================================== */
63663 /* ==============================================  IOM0 CMDSTAT CMDSTAT [5..7]  ============================================== */
63664 typedef enum {                                  /*!< IOM0_CMDSTAT_CMDSTAT                                                      */
63665   IOM0_CMDSTAT_CMDSTAT_ERR             = 1,     /*!< ERR : Error encountered with command                                      */
63666   IOM0_CMDSTAT_CMDSTAT_ACTIVE          = 2,     /*!< ACTIVE : Actively processing command                                      */
63667   IOM0_CMDSTAT_CMDSTAT_IDLE            = 4,     /*!< IDLE : Idle state, no active command, no error                            */
63668   IOM0_CMDSTAT_CMDSTAT_WAIT            = 6,     /*!< WAIT : Command in progress, but waiting on data from host                 */
63669 } IOM0_CMDSTAT_CMDSTAT_Enum;
63670 
63671 /* =========================================================  INTEN  ========================================================= */
63672 /* ========================================================  INTSTAT  ======================================================== */
63673 /* ========================================================  INTCLR  ========================================================= */
63674 /* ========================================================  INTSET  ========================================================= */
63675 /* =======================================================  DMATRIGEN  ======================================================= */
63676 /* ======================================================  DMATRIGSTAT  ====================================================== */
63677 /* ========================================================  DMACFG  ========================================================= */
63678 /* ==============================================  IOM0 DMACFG DPWROFF [9..9]  =============================================== */
63679 typedef enum {                                  /*!< IOM0_DMACFG_DPWROFF                                                       */
63680   IOM0_DMACFG_DPWROFF_DIS              = 0,     /*!< DIS : Power off disabled                                                  */
63681   IOM0_DMACFG_DPWROFF_EN               = 1,     /*!< EN : Power off enabled                                                    */
63682 } IOM0_DMACFG_DPWROFF_Enum;
63683 
63684 /* ===============================================  IOM0 DMACFG DMAPRI [8..8]  =============================================== */
63685 typedef enum {                                  /*!< IOM0_DMACFG_DMAPRI                                                        */
63686   IOM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
63687   IOM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
63688 } IOM0_DMACFG_DMAPRI_Enum;
63689 
63690 /* ===============================================  IOM0 DMACFG DMADIR [1..1]  =============================================== */
63691 typedef enum {                                  /*!< IOM0_DMACFG_DMADIR                                                        */
63692   IOM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
63693                                                      doing IOM read operations, ie reading data from external
63694                                                      devices.                                                                  */
63695   IOM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. To be set when doing
63696                                                      IOM write operations, ie writing data to external devices.                */
63697 } IOM0_DMACFG_DMADIR_Enum;
63698 
63699 /* ===============================================  IOM0 DMACFG DMAEN [0..0]  ================================================ */
63700 typedef enum {                                  /*!< IOM0_DMACFG_DMAEN                                                         */
63701   IOM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
63702   IOM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
63703 } IOM0_DMACFG_DMAEN_Enum;
63704 
63705 /* ======================================================  DMATOTCOUNT  ====================================================== */
63706 /* ======================================================  DMATARGADDR  ====================================================== */
63707 /* ========================================================  DMASTAT  ======================================================== */
63708 /* =========================================================  CQCFG  ========================================================= */
63709 /* =============================================  IOM0 CQCFG MSPIFLGSEL [2..3]  ============================================== */
63710 typedef enum {                                  /*!< IOM0_CQCFG_MSPIFLGSEL                                                     */
63711   IOM0_CQCFG_MSPIFLGSEL_MSPI0FLGSEL    = 0,     /*!< MSPI0FLGSEL : Selects MPSI0 as source of signals used in CGFLAG[11:8].    */
63712   IOM0_CQCFG_MSPIFLGSEL_MSPI1FLGSEL    = 1,     /*!< MSPI1FLGSEL : Selects MPSI1 as source of signals used in CGFLAG[11:8].    */
63713   IOM0_CQCFG_MSPIFLGSEL_MSPI2FLGSEL    = 2,     /*!< MSPI2FLGSEL : Selects MPSI2 as source of signals used in CGFLAG[11:8].    */
63714 } IOM0_CQCFG_MSPIFLGSEL_Enum;
63715 
63716 /* ================================================  IOM0 CQCFG CQPRI [1..1]  ================================================ */
63717 typedef enum {                                  /*!< IOM0_CQCFG_CQPRI                                                          */
63718   IOM0_CQCFG_CQPRI_LOW                 = 0,     /*!< LOW : Low Priority (service as best effort)                               */
63719   IOM0_CQCFG_CQPRI_HIGH                = 1,     /*!< HIGH : High Priority (service immediately)                                */
63720 } IOM0_CQCFG_CQPRI_Enum;
63721 
63722 /* ================================================  IOM0 CQCFG CQEN [0..0]  ================================================= */
63723 typedef enum {                                  /*!< IOM0_CQCFG_CQEN                                                           */
63724   IOM0_CQCFG_CQEN_DIS                  = 0,     /*!< DIS : Disable CQ Function                                                 */
63725   IOM0_CQCFG_CQEN_EN                   = 1,     /*!< EN : Enable CQ Function                                                   */
63726 } IOM0_CQCFG_CQEN_Enum;
63727 
63728 /* ========================================================  CQADDR  ========================================================= */
63729 /* ========================================================  CQSTAT  ========================================================= */
63730 /* ========================================================  CQFLAGS  ======================================================== */
63731 /* ======================================================  CQSETCLEAR  ======================================================= */
63732 /* =======================================================  CQPAUSEEN  ======================================================= */
63733 /* =============================================  IOM0 CQPAUSEEN CQPEN [0..15]  ============================================== */
63734 typedef enum {                                  /*!< IOM0_CQPAUSEEN_CQPEN                                                      */
63735   IOM0_CQPAUSEEN_CQPEN_IDXEQ           = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches
63736                                                      the last index                                                            */
63737   IOM0_CQPAUSEEN_CQPEN_BLEXOREN        = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
63738                                                      SWFLAG4 is '1'                                                            */
63739   IOM0_CQPAUSEEN_CQPEN_IOMXOREN        = 8192,  /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
63740                                                      SWFLAG3 is '1'                                                            */
63741   IOM0_CQPAUSEEN_CQPEN_GPIOXOREN       = 4096,  /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
63742                                                      with SWFLAG2 is '1'                                                       */
63743   IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN     = 2048,  /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
63744                                                      with SWFLAG1 is '1'                                                       */
63745   IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN     = 1024,  /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
63746                                                      with SWFLAG0 is '1'                                                       */
63747   IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN      = 512,   /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
63748                                                      with SWFLAG1 is '1'                                                       */
63749   IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN      = 256,   /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
63750                                                      with SWFLAG0 is '1'                                                       */
63751   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7       = 128,   /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
63752                                                      is '1'.                                                                   */
63753   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6       = 64,    /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6
63754                                                      is '1'                                                                    */
63755   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5       = 32,    /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5
63756                                                      is '1'                                                                    */
63757   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4       = 16,    /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4
63758                                                      is '1'                                                                    */
63759   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3       = 8,     /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3
63760                                                      is '1'                                                                    */
63761   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2       = 4,     /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2
63762                                                      is '1'                                                                    */
63763   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1       = 2,     /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1
63764                                                      is '1'                                                                    */
63765   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0       = 1,     /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0
63766                                                      is '1'                                                                    */
63767 } IOM0_CQPAUSEEN_CQPEN_Enum;
63768 
63769 /* =======================================================  CQCURIDX  ======================================================== */
63770 /* =======================================================  CQENDIDX  ======================================================== */
63771 /* ========================================================  STATUS  ========================================================= */
63772 /* ===============================================  IOM0 STATUS IDLEST [2..2]  =============================================== */
63773 typedef enum {                                  /*!< IOM0_STATUS_IDLEST                                                        */
63774   IOM0_STATUS_IDLEST_IDLE              = 1,     /*!< IDLE : The I/O state machine is in the idle state.                        */
63775 } IOM0_STATUS_IDLEST_Enum;
63776 
63777 /* ===============================================  IOM0 STATUS CMDACT [1..1]  =============================================== */
63778 typedef enum {                                  /*!< IOM0_STATUS_CMDACT                                                        */
63779   IOM0_STATUS_CMDACT_ACTIVE            = 1,     /*!< ACTIVE : An I/O command is active. Indicates the active module
63780                                                      has an active command and is processing this. De-asserted
63781                                                      when the command is completed.                                            */
63782 } IOM0_STATUS_CMDACT_Enum;
63783 
63784 /* ================================================  IOM0 STATUS ERR [0..0]  ================================================= */
63785 typedef enum {                                  /*!< IOM0_STATUS_ERR                                                           */
63786   IOM0_STATUS_ERR_ERROR                = 1,     /*!< ERROR : Bit has been deprecated and will always return 0.                 */
63787 } IOM0_STATUS_ERR_Enum;
63788 
63789 /* ========================================================  MSPICFG  ======================================================== */
63790 /* =============================================  IOM0 MSPICFG SPILSB [23..23]  ============================================== */
63791 typedef enum {                                  /*!< IOM0_MSPICFG_SPILSB                                                       */
63792   IOM0_MSPICFG_SPILSB_MSB              = 0,     /*!< MSB : Send and receive MSB bit first                                      */
63793   IOM0_MSPICFG_SPILSB_LSB              = 1,     /*!< LSB : Send and receive LSB bit first                                      */
63794 } IOM0_MSPICFG_SPILSB_Enum;
63795 
63796 /* =============================================  IOM0 MSPICFG RDFCPOL [22..22]  ============================================= */
63797 typedef enum {                                  /*!< IOM0_MSPICFG_RDFCPOL                                                      */
63798   IOM0_MSPICFG_RDFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high creates flow control.                     */
63799   IOM0_MSPICFG_RDFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low creates flow control.                       */
63800 } IOM0_MSPICFG_RDFCPOL_Enum;
63801 
63802 /* =============================================  IOM0 MSPICFG WTFCPOL [21..21]  ============================================= */
63803 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCPOL                                                      */
63804   IOM0_MSPICFG_WTFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high(1) creates flow control and
63805                                                      byte transfers will stop until the flow control signal
63806                                                      goes low.                                                                 */
63807   IOM0_MSPICFG_WTFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low(0) creates flow control and byte
63808                                                      transfers will stop until the flow control signal goes
63809                                                      high(1).                                                                  */
63810 } IOM0_MSPICFG_WTFCPOL_Enum;
63811 
63812 /* =============================================  IOM0 MSPICFG WTFCIRQ [20..20]  ============================================= */
63813 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCIRQ                                                      */
63814   IOM0_MSPICFG_WTFCIRQ_MISO            = 0,     /*!< MISO : MISO is used as the write mode flow control signal.                */
63815   IOM0_MSPICFG_WTFCIRQ_IRQ             = 1,     /*!< IRQ : IRQ is used as the write mode flow control signal.                  */
63816 } IOM0_MSPICFG_WTFCIRQ_Enum;
63817 
63818 /* =============================================  IOM0 MSPICFG MOSIINV [18..18]  ============================================= */
63819 typedef enum {                                  /*!< IOM0_MSPICFG_MOSIINV                                                      */
63820   IOM0_MSPICFG_MOSIINV_NORMAL          = 0,     /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode.               */
63821   IOM0_MSPICFG_MOSIINV_INVERT          = 1,     /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode.               */
63822 } IOM0_MSPICFG_MOSIINV_Enum;
63823 
63824 /* ==============================================  IOM0 MSPICFG RDFC [17..17]  =============================================== */
63825 typedef enum {                                  /*!< IOM0_MSPICFG_RDFC                                                         */
63826   IOM0_MSPICFG_RDFC_DIS                = 0,     /*!< DIS : Read mode flow control disabled.                                    */
63827   IOM0_MSPICFG_RDFC_EN                 = 1,     /*!< EN : Read mode flow control enabled.                                      */
63828 } IOM0_MSPICFG_RDFC_Enum;
63829 
63830 /* ==============================================  IOM0 MSPICFG WTFC [16..16]  =============================================== */
63831 typedef enum {                                  /*!< IOM0_MSPICFG_WTFC                                                         */
63832   IOM0_MSPICFG_WTFC_DIS                = 0,     /*!< DIS : Write mode flow control disabled.                                   */
63833   IOM0_MSPICFG_WTFC_EN                 = 1,     /*!< EN : Write mode flow control enabled.                                     */
63834 } IOM0_MSPICFG_WTFC_Enum;
63835 
63836 /* ===============================================  IOM0 MSPICFG SPHA [1..1]  ================================================ */
63837 typedef enum {                                  /*!< IOM0_MSPICFG_SPHA                                                         */
63838   IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0,    /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge.           */
63839   IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1,   /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
63840                                                      edge.                                                                     */
63841 } IOM0_MSPICFG_SPHA_Enum;
63842 
63843 /* ===============================================  IOM0 MSPICFG SPOL [0..0]  ================================================ */
63844 typedef enum {                                  /*!< IOM0_MSPICFG_SPOL                                                         */
63845   IOM0_MSPICFG_SPOL_CLK_BASE_0         = 0,     /*!< CLK_BASE_0 : The base value of the clock is 0.                            */
63846   IOM0_MSPICFG_SPOL_CLK_BASE_1         = 1,     /*!< CLK_BASE_1 : The base value of the clock is 1.                            */
63847 } IOM0_MSPICFG_SPOL_Enum;
63848 
63849 /* ========================================================  MI2CCFG  ======================================================== */
63850 /* ===============================================  IOM0 MI2CCFG ARBEN [2..2]  =============================================== */
63851 typedef enum {                                  /*!< IOM0_MI2CCFG_ARBEN                                                        */
63852   IOM0_MI2CCFG_ARBEN_ARBENABLE         = 1,     /*!< ARBENABLE : Enable multi-master bus arbitration support for
63853                                                      this i2c master                                                           */
63854   IOM0_MI2CCFG_ARBEN_ARBDISABLE        = 0,     /*!< ARBDISABLE : Disable multi-master bus arbitration support for
63855                                                      this i2c master                                                           */
63856 } IOM0_MI2CCFG_ARBEN_Enum;
63857 
63858 /* ==============================================  IOM0 MI2CCFG I2CLSB [1..1]  =============================================== */
63859 typedef enum {                                  /*!< IOM0_MI2CCFG_I2CLSB                                                       */
63860   IOM0_MI2CCFG_I2CLSB_MSBFIRST         = 0,     /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read
63861                                                      from the bus                                                              */
63862   IOM0_MI2CCFG_I2CLSB_LSBFIRST         = 1,     /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read
63863                                                      from the bus                                                              */
63864 } IOM0_MI2CCFG_I2CLSB_Enum;
63865 
63866 /* ==============================================  IOM0 MI2CCFG ADDRSZ [0..0]  =============================================== */
63867 typedef enum {                                  /*!< IOM0_MI2CCFG_ADDRSZ                                                       */
63868   IOM0_MI2CCFG_ADDRSZ_ADDRSZ7          = 0,     /*!< ADDRSZ7 : Use 7b addressing for I2C master transactions                   */
63869   IOM0_MI2CCFG_ADDRSZ_ADDRSZ10         = 1,     /*!< ADDRSZ10 : Use 10b addressing for I2C master transactions                 */
63870 } IOM0_MI2CCFG_ADDRSZ_Enum;
63871 
63872 /* ========================================================  DEVCFG  ========================================================= */
63873 /* ========================================================  IOMDBG  ========================================================= */
63874 
63875 
63876 /* =========================================================================================================================== */
63877 /* ================                                          IOSLAVE                                          ================ */
63878 /* =========================================================================================================================== */
63879 
63880 /* ========================================================  FIFOPTR  ======================================================== */
63881 /* ========================================================  FIFOCFG  ======================================================== */
63882 /* ========================================================  FIFOTHR  ======================================================== */
63883 /* =========================================================  FUPD  ========================================================== */
63884 /* ========================================================  FIFOCTR  ======================================================== */
63885 /* ========================================================  FIFOINC  ======================================================== */
63886 /* ==========================================================  CFG  ========================================================== */
63887 /* ==============================================  IOSLAVE CFG IFCEN [31..31]  =============================================== */
63888 typedef enum {                                  /*!< IOSLAVE_CFG_IFCEN                                                         */
63889   IOSLAVE_CFG_IFCEN_DIS                = 0,     /*!< DIS : Disable the IOSLAVE                                                 */
63890   IOSLAVE_CFG_IFCEN_EN                 = 1,     /*!< EN : Enable the IOSLAVE                                                   */
63891 } IOSLAVE_CFG_IFCEN_Enum;
63892 
63893 /* =============================================  IOSLAVE CFG WRAPPTR [20..20]  ============================================== */
63894 typedef enum {                                  /*!< IOSLAVE_CFG_WRAPPTR                                                       */
63895   IOSLAVE_CFG_WRAPPTR_NOWRAP           = 0,     /*!< NOWRAP : Address pointer does not wrap around to FIFOBASE*8
63896                                                      after it reaches FIFOMAX*8-1. Additionally, the address
63897                                                      pointer does not automatically skip Direct Area locations
63898                                                      0x78 to 0x7F, so care must be taken that the host does
63899                                                      not inadvertently write to the Host Registers during a
63900                                                      data transfer.                                                            */
63901   IOSLAVE_CFG_WRAPPTR_WRAP             = 1,     /*!< WRAP : Address pointer wraps around to FIFOBASE*8 after it reaches
63902                                                      FIFOMAX*8-1 to accommodate any length transfers. In addition,
63903                                                      the address pointer automatically skips Direct Area locations
63904                                                      0x78 to 0x7F (if the FIFO Area encompasses these locations)
63905                                                      to avoid writing to the Host Registers.                                   */
63906 } IOSLAVE_CFG_WRAPPTR_Enum;
63907 
63908 /* ==============================================  IOSLAVE CFG STARTRD [4..4]  =============================================== */
63909 typedef enum {                                  /*!< IOSLAVE_CFG_STARTRD                                                       */
63910   IOSLAVE_CFG_STARTRD_LATE             = 0,     /*!< LATE : Initiate I/O RAM read late in each transferred byte.               */
63911   IOSLAVE_CFG_STARTRD_EARLY            = 1,     /*!< EARLY : Initiate I/O RAM read early in each transferred byte.             */
63912 } IOSLAVE_CFG_STARTRD_Enum;
63913 
63914 /* ================================================  IOSLAVE CFG LSB [2..2]  ================================================= */
63915 typedef enum {                                  /*!< IOSLAVE_CFG_LSB                                                           */
63916   IOSLAVE_CFG_LSB_MSB_FIRST            = 0,     /*!< MSB_FIRST : Data is assumed to be sent and received with MSB
63917                                                      first.                                                                    */
63918   IOSLAVE_CFG_LSB_LSB_FIRST            = 1,     /*!< LSB_FIRST : Data is assumed to be sent and received with LSB
63919                                                      first.                                                                    */
63920 } IOSLAVE_CFG_LSB_Enum;
63921 
63922 /* ================================================  IOSLAVE CFG SPOL [1..1]  ================================================ */
63923 typedef enum {                                  /*!< IOSLAVE_CFG_SPOL                                                          */
63924   IOSLAVE_CFG_SPOL_SPI_MODES_0_3       = 0,     /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3.                    */
63925   IOSLAVE_CFG_SPOL_SPI_MODES_1_2       = 1,     /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2.                    */
63926 } IOSLAVE_CFG_SPOL_Enum;
63927 
63928 /* ===============================================  IOSLAVE CFG IFCSEL [0..0]  =============================================== */
63929 typedef enum {                                  /*!< IOSLAVE_CFG_IFCSEL                                                        */
63930   IOSLAVE_CFG_IFCSEL_I2C               = 0,     /*!< I2C : Selects I2C interface for the IO Slave.                             */
63931   IOSLAVE_CFG_IFCSEL_SPI               = 1,     /*!< SPI : Selects SPI interface for the IO Slave.                             */
63932 } IOSLAVE_CFG_IFCSEL_Enum;
63933 
63934 /* =========================================================  PRENC  ========================================================= */
63935 /* =======================================================  IOINTCTL  ======================================================== */
63936 /* ========================================================  GENADD  ========================================================= */
63937 /* ========================================================  ADDPTR  ========================================================= */
63938 /* =========================================================  INTEN  ========================================================= */
63939 /* ========================================================  INTSTAT  ======================================================== */
63940 /* ========================================================  INTCLR  ========================================================= */
63941 /* ========================================================  INTSET  ========================================================= */
63942 /* ======================================================  REGACCINTEN  ====================================================== */
63943 /* =====================================================  REGACCINTSTAT  ===================================================== */
63944 /* =====================================================  REGACCINTCLR  ====================================================== */
63945 /* =====================================================  REGACCINTSET  ====================================================== */
63946 
63947 
63948 /* =========================================================================================================================== */
63949 /* ================                                          MCUCTRL                                          ================ */
63950 /* =========================================================================================================================== */
63951 
63952 /* ========================================================  CHIPPN  ========================================================= */
63953 /* ============================================  MCUCTRL CHIPPN PARTNUM [0..31]  ============================================= */
63954 typedef enum {                                  /*!< MCUCTRL_CHIPPN_PARTNUM                                                    */
63955   MCUCTRL_CHIPPN_PARTNUM_APOLLO4       = 134217728,/*!< APOLLO4 : Apollo4 part number is 0x08xxxxxx.                           */
63956   MCUCTRL_CHIPPN_PARTNUM_APOLLO3P      = 117440512,/*!< APOLLO3P : Apollo3P part number is 0x07xxxxxx.                         */
63957   MCUCTRL_CHIPPN_PARTNUM_APOLLO3       = 100663296,/*!< APOLLO3 : Apollo3 part number is 0x06xxxxxx.                           */
63958   MCUCTRL_CHIPPN_PARTNUM_APOLLO2       = 50331648,/*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx.                            */
63959   MCUCTRL_CHIPPN_PARTNUM_APOLLO        = 16777216,/*!< APOLLO : Apollo part number is 0x01xxxxxx.                              */
63960   MCUCTRL_CHIPPN_PARTNUM_PN_M          = 0xFF000000,/*!< PN_M : Mask for the part number field.                                 */
63961   MCUCTRL_CHIPPN_PARTNUM_PN_S          = 24,    /*!< PN_S : Bit position for the part number field.                            */
63962   MCUCTRL_CHIPPN_PARTNUM_MRAMSIZE_M    = 15728640,/*!< MRAMSIZE_M : Mask for the MRAM_SIZE field.Values:0: 0.5MB1:
63963                                                      1.0MB2: 1.5MB3: 2.0MB                                                     */
63964   MCUCTRL_CHIPPN_PARTNUM_MRAMSIZE_S    = 20,    /*!< MRAMSIZE_S : Bit position for the MRAM_SIZE field.                        */
63965   MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M    = 983040,/*!< SRAMSIZE_M : Mask for the SRAM_SIZE field.Values:0: 384KB+512KB1:
63966                                                      384KB+1MB2: 384KB+1MB+384KB+96KB                                          */
63967   MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S    = 16,    /*!< SRAMSIZE_S : Bit position for the SRAM_SIZE field.                        */
63968   MCUCTRL_CHIPPN_PARTNUM_REV_M         = 65280, /*!< REV_M : Mask for the revision field. Bits [15:12] are major
63969                                                      rev, [11:8] are minor rev.Values:0: Major Rev A, Minor
63970                                                      Rev 01: Major Rev B, Minor Rev 1                                          */
63971   MCUCTRL_CHIPPN_PARTNUM_REV_S         = 8,     /*!< REV_S : Bit position for the revision field.                              */
63972   MCUCTRL_CHIPPN_PARTNUM_PKG_M         = 192,   /*!< PKG_M : Mask for the package field.Values:0: SIP1: QFN2: BGA3:
63973                                                      CSP                                                                       */
63974   MCUCTRL_CHIPPN_PARTNUM_PKG_S         = 6,     /*!< PKG_S : Bit position for the package field.                               */
63975   MCUCTRL_CHIPPN_PARTNUM_PINS_M        = 56,    /*!< PINS_M : Mask for the pins field.Values:0: 25 pins1: 49 pins2:
63976                                                      64 pins3: 81 pins                                                         */
63977   MCUCTRL_CHIPPN_PARTNUM_PINS_S        = 3,     /*!< PINS_S : Bit position for the pins field.                                 */
63978   MCUCTRL_CHIPPN_PARTNUM_TEMP_S        = 1,     /*!< TEMP_S : Bit position for the temperature field.                          */
63979 } MCUCTRL_CHIPPN_PARTNUM_Enum;
63980 
63981 /* ========================================================  CHIPID0  ======================================================== */
63982 /* ========================================================  CHIPID1  ======================================================== */
63983 /* ========================================================  CHIPREV  ======================================================== */
63984 /* =============================================  MCUCTRL CHIPREV REVMAJ [4..7]  ============================================= */
63985 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMAJ                                                    */
63986   MCUCTRL_CHIPREV_REVMAJ_B             = 2,     /*!< B : Apollo4 revision B                                                    */
63987   MCUCTRL_CHIPREV_REVMAJ_A             = 1,     /*!< A : Apollo4 revision A                                                    */
63988 } MCUCTRL_CHIPREV_REVMAJ_Enum;
63989 
63990 /* =============================================  MCUCTRL CHIPREV REVMIN [0..3]  ============================================= */
63991 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMIN                                                    */
63992   MCUCTRL_CHIPREV_REVMIN_REV2          = 3,     /*!< REV2 : Apollo4 minor rev 2.                                               */
63993   MCUCTRL_CHIPREV_REVMIN_REV1          = 2,     /*!< REV1 : Apollo4 minor rev 1.                                               */
63994   MCUCTRL_CHIPREV_REVMIN_REV0          = 1,     /*!< REV0 : Apollo4 minor rev 0. Minor revision value, succeeding
63995                                                      minor revisions will increment from this value.                           */
63996 } MCUCTRL_CHIPREV_REVMIN_Enum;
63997 
63998 /* =======================================================  VENDORID  ======================================================== */
63999 /* ===========================================  MCUCTRL VENDORID VENDORID [0..31]  =========================================== */
64000 typedef enum {                                  /*!< MCUCTRL_VENDORID_VENDORID                                                 */
64001   MCUCTRL_VENDORID_VENDORID_AMBIQ      = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ'                                        */
64002 } MCUCTRL_VENDORID_VENDORID_Enum;
64003 
64004 /* ==========================================================  SKU  ========================================================== */
64005 /* =======================================================  DEBUGGER  ======================================================== */
64006 /* =========================================================  ACRG  ========================================================== */
64007 /* ===========================================  MCUCTRL ACRG ACRGIBIASSEL [2..2]  ============================================ */
64008 typedef enum {                                  /*!< MCUCTRL_ACRG_ACRGIBIASSEL                                                 */
64009   MCUCTRL_ACRG_ACRGIBIASSEL_BGSEL      = 0,     /*!< BGSEL : Selects the bandgap                                               */
64010   MCUCTRL_ACRG_ACRGIBIASSEL_CCRGSEL    = 1,     /*!< CCRGSEL : Selects the CCRG                                                */
64011 } MCUCTRL_ACRG_ACRGIBIASSEL_Enum;
64012 
64013 /* ==============================================  MCUCTRL ACRG ACRGPWD [1..1]  ============================================== */
64014 typedef enum {                                  /*!< MCUCTRL_ACRG_ACRGPWD                                                      */
64015   MCUCTRL_ACRG_ACRGPWD_ACRG_PWR_DN     = 1,     /*!< ACRG_PWR_DN : Powers down the ACRG trim.                                  */
64016 } MCUCTRL_ACRG_ACRGPWD_Enum;
64017 
64018 /* =======================================================  VREFGEN2  ======================================================== */
64019 /* ==========================================  MCUCTRL VREFGEN2 TVRG2PWD [19..19]  =========================================== */
64020 typedef enum {                                  /*!< MCUCTRL_VREFGEN2_TVRG2PWD                                                 */
64021   MCUCTRL_VREFGEN2_TVRG2PWD_PWR_DN     = 1,     /*!< PWR_DN : Powers down the CVRG.                                            */
64022 } MCUCTRL_VREFGEN2_TVRG2PWD_Enum;
64023 
64024 /* ============================================  MCUCTRL VREFGEN2 TVRGPWD [5..5]  ============================================ */
64025 typedef enum {                                  /*!< MCUCTRL_VREFGEN2_TVRGPWD                                                  */
64026   MCUCTRL_VREFGEN2_TVRGPWD_PWR_DN      = 1,     /*!< PWR_DN : Powers down the CVRG.                                            */
64027 } MCUCTRL_VREFGEN2_TVRGPWD_Enum;
64028 
64029 /* ========================================================  VRCTRL  ========================================================= */
64030 /* ========================================================  LDOREG1  ======================================================== */
64031 /* ========================================================  LDOREG2  ======================================================== */
64032 /* =========================================================  LFRC  ========================================================== */
64033 /* =========================================  MCUCTRL LFRC LFRCSIMOCLKDIV [10..12]  ========================================== */
64034 typedef enum {                                  /*!< MCUCTRL_LFRC_LFRCSIMOCLKDIV                                               */
64035   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV1     = 0,     /*!< DIV1 : Divide by 1                                                        */
64036   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV2     = 1,     /*!< DIV2 : Divide by 2                                                        */
64037   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV4     = 2,     /*!< DIV4 : Divide by 4                                                        */
64038   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV8     = 3,     /*!< DIV8 : Divide by 8                                                        */
64039   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV16    = 4,     /*!< DIV16 : Divide by 16                                                      */
64040   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV32    = 5,     /*!< DIV32 : Divide by 32                                                      */
64041 } MCUCTRL_LFRC_LFRCSIMOCLKDIV_Enum;
64042 
64043 /* =============================================  MCUCTRL LFRC RESETLFRC [7..7]  ============================================= */
64044 typedef enum {                                  /*!< MCUCTRL_LFRC_RESETLFRC                                                    */
64045   MCUCTRL_LFRC_RESETLFRC_EN            = 0,     /*!< EN : Enable LFRC.                                                         */
64046   MCUCTRL_LFRC_RESETLFRC_RESET         = 1,     /*!< RESET : Reset LFRC.                                                       */
64047 } MCUCTRL_LFRC_RESETLFRC_Enum;
64048 
64049 /* ==============================================  MCUCTRL LFRC PWDLFRC [6..6]  ============================================== */
64050 typedef enum {                                  /*!< MCUCTRL_LFRC_PWDLFRC                                                      */
64051   MCUCTRL_LFRC_PWDLFRC_PWRUP           = 0,     /*!< PWRUP : Power up LFRC.                                                    */
64052   MCUCTRL_LFRC_PWDLFRC_PWRDN           = 1,     /*!< PWRDN : Power down LFRC.                                                  */
64053 } MCUCTRL_LFRC_PWDLFRC_Enum;
64054 
64055 /* ==============================================  MCUCTRL LFRC LFRCSWE [0..0]  ============================================== */
64056 typedef enum {                                  /*!< MCUCTRL_LFRC_LFRCSWE                                                      */
64057   MCUCTRL_LFRC_LFRCSWE_OVERRIDE_DIS    = 0,     /*!< OVERRIDE_DIS : LFRC Software Override Disable.                            */
64058   MCUCTRL_LFRC_LFRCSWE_OVERRIDE_EN     = 1,     /*!< OVERRIDE_EN : LFRC Software Override Enable.                              */
64059 } MCUCTRL_LFRC_LFRCSWE_Enum;
64060 
64061 /* ========================================================  BODCTRL  ======================================================== */
64062 /* =======================================================  ADCPWRDLY  ======================================================= */
64063 /* ======================================================  ADCPWRCTRL  ======================================================= */
64064 /* ========================================  MCUCTRL ADCPWRCTRL VDDADCRESETN [9..9]  ========================================= */
64065 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCRESETN                                           */
64066   MCUCTRL_ADCPWRCTRL_VDDADCRESETN_ASSERT = 0,   /*!< ASSERT : Resetn is asserted                                               */
64067   MCUCTRL_ADCPWRCTRL_VDDADCRESETN_DEASSERT = 1, /*!< DEASSERT : Resetn is de-asserted                                          */
64068 } MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Enum;
64069 
64070 /* ======================================  MCUCTRL ADCPWRCTRL VDDADCDIGISOLATE [8..8]  ======================================= */
64071 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE                                       */
64072   MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_DIS = 0,  /*!< DIS : No Isolation                                                        */
64073   MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_EN = 1,   /*!< EN : Isolate                                                              */
64074 } MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Enum;
64075 
64076 /* ======================================  MCUCTRL ADCPWRCTRL VDDADCSARISOLATE [7..7]  ======================================= */
64077 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE                                       */
64078   MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_DIS = 0,  /*!< DIS : No Isolation                                                        */
64079   MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_EN = 1,   /*!< EN : Isolate                                                              */
64080 } MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Enum;
64081 
64082 /* =========================================  MCUCTRL ADCPWRCTRL REFKEEPPEN [6..6]  ========================================== */
64083 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_REFKEEPPEN                                             */
64084   MCUCTRL_ADCPWRCTRL_REFKEEPPEN_DIS    = 0,     /*!< DIS : Reference Buffer Keeper Power Switch disable.                       */
64085   MCUCTRL_ADCPWRCTRL_REFKEEPPEN_EN     = 1,     /*!< EN : Reference Buffer Keeper Power Switch enable.                         */
64086 } MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Enum;
64087 
64088 /* ==========================================  MCUCTRL ADCPWRCTRL REFBUFPEN [5..5]  ========================================== */
64089 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_REFBUFPEN                                              */
64090   MCUCTRL_ADCPWRCTRL_REFBUFPEN_DIS     = 0,     /*!< DIS : Reference Buffer Power Switch disable.                              */
64091   MCUCTRL_ADCPWRCTRL_REFBUFPEN_EN      = 1,     /*!< EN : Reference Buffer Power Switch enable.                                */
64092 } MCUCTRL_ADCPWRCTRL_REFBUFPEN_Enum;
64093 
64094 /* ==========================================  MCUCTRL ADCPWRCTRL BGTLPPEN [4..4]  =========================================== */
64095 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_BGTLPPEN                                               */
64096   MCUCTRL_ADCPWRCTRL_BGTLPPEN_DIS      = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
64097   MCUCTRL_ADCPWRCTRL_BGTLPPEN_EN       = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
64098 } MCUCTRL_ADCPWRCTRL_BGTLPPEN_Enum;
64099 
64100 /* ===========================================  MCUCTRL ADCPWRCTRL BGTPEN [3..3]  ============================================ */
64101 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_BGTPEN                                                 */
64102   MCUCTRL_ADCPWRCTRL_BGTPEN_DIS        = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
64103   MCUCTRL_ADCPWRCTRL_BGTPEN_EN         = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
64104 } MCUCTRL_ADCPWRCTRL_BGTPEN_Enum;
64105 
64106 /* ==========================================  MCUCTRL ADCPWRCTRL ADCBPSEN [2..2]  =========================================== */
64107 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCBPSEN                                               */
64108   MCUCTRL_ADCPWRCTRL_ADCBPSEN_DIS      = 0,     /*!< DIS : ADC power switch software power disable.                            */
64109   MCUCTRL_ADCPWRCTRL_ADCBPSEN_EN       = 1,     /*!< EN : ADC power switch software power enable.                              */
64110 } MCUCTRL_ADCPWRCTRL_ADCBPSEN_Enum;
64111 
64112 /* ==========================================  MCUCTRL ADCPWRCTRL ADCAPSEN [1..1]  =========================================== */
64113 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCAPSEN                                               */
64114   MCUCTRL_ADCPWRCTRL_ADCAPSEN_DIS      = 0,     /*!< DIS : ADC power switch software power disable.                            */
64115   MCUCTRL_ADCPWRCTRL_ADCAPSEN_EN       = 1,     /*!< EN : ADC power switch software power enable.                              */
64116 } MCUCTRL_ADCPWRCTRL_ADCAPSEN_Enum;
64117 
64118 /* ========================================  MCUCTRL ADCPWRCTRL ADCPWRCTRLSWE [0..0]  ======================================== */
64119 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE                                          */
64120   MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_DIS = 0,/*!< OVERRIDE_DIS : ADC temperature sensor and bandgap Software Override
64121                                                      Disable.                                                                  */
64122   MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_EN = 1,/*!< OVERRIDE_EN : ADC temperature sensor and bandgap Software Override
64123                                                      Enable.                                                                   */
64124 } MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Enum;
64125 
64126 /* ========================================================  ADCCAL  ========================================================= */
64127 /* ==========================================  MCUCTRL ADCCAL ADCCALIBRATED [1..1]  ========================================== */
64128 typedef enum {                                  /*!< MCUCTRL_ADCCAL_ADCCALIBRATED                                              */
64129   MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE   = 0,     /*!< FALSE : ADC is not calibrated                                             */
64130   MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE    = 1,     /*!< TRUE : ADC is calibrated                                                  */
64131 } MCUCTRL_ADCCAL_ADCCALIBRATED_Enum;
64132 
64133 /* ===========================================  MCUCTRL ADCCAL CALONPWRUP [0..0]  ============================================ */
64134 typedef enum {                                  /*!< MCUCTRL_ADCCAL_CALONPWRUP                                                 */
64135   MCUCTRL_ADCCAL_CALONPWRUP_DIS        = 0,     /*!< DIS : Disable automatic calibration on initial power up                   */
64136   MCUCTRL_ADCCAL_CALONPWRUP_EN         = 1,     /*!< EN : Enable automatic calibration on initial power up                     */
64137 } MCUCTRL_ADCCAL_CALONPWRUP_Enum;
64138 
64139 /* ======================================================  ADCBATTLOAD  ====================================================== */
64140 /* ==========================================  MCUCTRL ADCBATTLOAD BATTLOAD [0..0]  ========================================== */
64141 typedef enum {                                  /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD                                              */
64142   MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS     = 0,     /*!< DIS : Battery load is disconnected                                        */
64143   MCUCTRL_ADCBATTLOAD_BATTLOAD_EN      = 1,     /*!< EN : Battery load is enabled                                              */
64144 } MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum;
64145 
64146 /* =======================================================  XTALCTRL  ======================================================== */
64147 /* =========================================  MCUCTRL XTALCTRL XTALCOMPPDNB [4..4]  ========================================== */
64148 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOMPPDNB                                             */
64149   MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRUPCOMP = 1,  /*!< PWRUPCOMP : Power up XTAL oscillator comparator.                          */
64150   MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRDNCOMP = 0,  /*!< PWRDNCOMP : Power down XTAL oscillator comparator.                        */
64151 } MCUCTRL_XTALCTRL_XTALCOMPPDNB_Enum;
64152 
64153 /* ===========================================  MCUCTRL XTALCTRL XTALPDNB [3..3]  ============================================ */
64154 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALPDNB                                                 */
64155   MCUCTRL_XTALCTRL_XTALPDNB_PWRUPCORE  = 1,     /*!< PWRUPCORE : Power up XTAL oscillator core.                                */
64156   MCUCTRL_XTALCTRL_XTALPDNB_PWRDNCORE  = 0,     /*!< PWRDNCORE : Power down XTAL oscillator core.                              */
64157 } MCUCTRL_XTALCTRL_XTALPDNB_Enum;
64158 
64159 /* ========================================  MCUCTRL XTALCTRL XTALCOMPBYPASS [2..2]  ========================================= */
64160 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOMPBYPASS                                           */
64161   MCUCTRL_XTALCTRL_XTALCOMPBYPASS_USECOMP = 0,  /*!< USECOMP : Use the XTAL oscillator comparator.                             */
64162   MCUCTRL_XTALCTRL_XTALCOMPBYPASS_BYPCOMP = 1,  /*!< BYPCOMP : Bypass the XTAL oscillator comparator.                          */
64163 } MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Enum;
64164 
64165 /* =========================================  MCUCTRL XTALCTRL XTALCOREDISFB [1..1]  ========================================= */
64166 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOREDISFB                                            */
64167   MCUCTRL_XTALCTRL_XTALCOREDISFB_EN    = 0,     /*!< EN : Enable XTAL oscillator comparator.                                   */
64168   MCUCTRL_XTALCTRL_XTALCOREDISFB_DIS   = 1,     /*!< DIS : Disable XTAL oscillator comparator.                                 */
64169 } MCUCTRL_XTALCTRL_XTALCOREDISFB_Enum;
64170 
64171 /* ============================================  MCUCTRL XTALCTRL XTALSWE [0..0]  ============================================ */
64172 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALSWE                                                  */
64173   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0,    /*!< OVERRIDE_DIS : XTAL Software Override Disable.                            */
64174   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1,     /*!< OVERRIDE_EN : XTAL Software Override Enable.                              */
64175 } MCUCTRL_XTALCTRL_XTALSWE_Enum;
64176 
64177 /* ======================================================  XTALGENCTRL  ====================================================== */
64178 /* ==========================================  MCUCTRL XTALGENCTRL ACWARMUP [0..1]  ========================================== */
64179 typedef enum {                                  /*!< MCUCTRL_XTALGENCTRL_ACWARMUP                                              */
64180   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1    = 0,     /*!< SEC1 : Warmup period of 1-2 seconds                                       */
64181   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2    = 1,     /*!< SEC2 : Warmup period of 2-4 seconds                                       */
64182   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4    = 2,     /*!< SEC4 : Warmup period of 4-8 seconds                                       */
64183   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8    = 3,     /*!< SEC8 : Warmup period of 8-16 seconds                                      */
64184 } MCUCTRL_XTALGENCTRL_ACWARMUP_Enum;
64185 
64186 /* ======================================================  XTALHSTRIMS  ====================================================== */
64187 /* ======================================================  XTALHSCTRL  ======================================================= */
64188 /* ======================================================  MRAMPWRCTRL  ====================================================== */
64189 /* =======================================================  BODISABLE  ======================================================= */
64190 /* ==========================================  MCUCTRL BODISABLE BODCLVREN [4..4]  =========================================== */
64191 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODCLVREN                                               */
64192   MCUCTRL_BODISABLE_BODCLVREN_EN       = 1,     /*!< EN : Enable VDDC_LV Brown Out reset.                                      */
64193   MCUCTRL_BODISABLE_BODCLVREN_DIS      = 0,     /*!< DIS : Disable VDDC_LV Brown Out reset.                                    */
64194 } MCUCTRL_BODISABLE_BODCLVREN_Enum;
64195 
64196 /* ===========================================  MCUCTRL BODISABLE BODSREN [3..3]  ============================================ */
64197 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODSREN                                                 */
64198   MCUCTRL_BODISABLE_BODSREN_EN         = 1,     /*!< EN : Enable VDDS Brown Out reset.                                         */
64199   MCUCTRL_BODISABLE_BODSREN_DIS        = 0,     /*!< DIS : Disable VDDS Brown Out reset.                                       */
64200 } MCUCTRL_BODISABLE_BODSREN_Enum;
64201 
64202 /* ===========================================  MCUCTRL BODISABLE BODFREN [2..2]  ============================================ */
64203 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODFREN                                                 */
64204   MCUCTRL_BODISABLE_BODFREN_EN         = 1,     /*!< EN : Enable VDDF Brown Out reset.                                         */
64205   MCUCTRL_BODISABLE_BODFREN_DIS        = 0,     /*!< DIS : Disable VDDF Brown Out reset.                                       */
64206 } MCUCTRL_BODISABLE_BODFREN_Enum;
64207 
64208 /* ===========================================  MCUCTRL BODISABLE BODCREN [1..1]  ============================================ */
64209 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODCREN                                                 */
64210   MCUCTRL_BODISABLE_BODCREN_EN         = 1,     /*!< EN : Enable VDDC Brown Out reset.                                         */
64211   MCUCTRL_BODISABLE_BODCREN_DIS        = 0,     /*!< DIS : Disable VDDC Brown Out reset.                                       */
64212 } MCUCTRL_BODISABLE_BODCREN_Enum;
64213 
64214 /* ===========================================  MCUCTRL BODISABLE BODLRDE [0..0]  ============================================ */
64215 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODLRDE                                                 */
64216   MCUCTRL_BODISABLE_BODLRDE_EN         = 0,     /*!< EN : Enable Unregulated 1.8v brown out reset.                             */
64217   MCUCTRL_BODISABLE_BODLRDE_DIS        = 1,     /*!< DIS : Disable Unregulated 1.8v brown out reset.                           */
64218 } MCUCTRL_BODISABLE_BODLRDE_Enum;
64219 
64220 /* ======================================================  BOOTLOADER  ======================================================= */
64221 /* =======================================  MCUCTRL BOOTLOADER SECBOOTONRST [30..31]  ======================================== */
64222 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST                                           */
64223   MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled                                           */
64224   MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1,  /*!< ENABLED : Secure boot enabled                                             */
64225   MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2,    /*!< ERROR : Error in secure boot configuration                                */
64226 } MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum;
64227 
64228 /* ==========================================  MCUCTRL BOOTLOADER SECBOOT [28..29]  ========================================== */
64229 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOT                                                */
64230   MCUCTRL_BOOTLOADER_SECBOOT_DISABLED  = 0,     /*!< DISABLED : Secure boot disabled                                           */
64231   MCUCTRL_BOOTLOADER_SECBOOT_ENABLED   = 1,     /*!< ENABLED : Secure boot enabled                                             */
64232   MCUCTRL_BOOTLOADER_SECBOOT_ERROR     = 2,     /*!< ERROR : Error in secure boot configuration                                */
64233 } MCUCTRL_BOOTLOADER_SECBOOT_Enum;
64234 
64235 /* ======================================  MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27]  ======================================= */
64236 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE                                         */
64237   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled                                          */
64238   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled                                             */
64239   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2,  /*!< ERROR : Error in secure boot configuration                                */
64240 } MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum;
64241 
64242 /* ===========================================  MCUCTRL BOOTLOADER SBLLOCK [3..3]  =========================================== */
64243 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBLLOCK                                                */
64244   MCUCTRL_BOOTLOADER_SBLLOCK_LOCK      = 1,     /*!< LOCK : Enable the secure boot lock                                        */
64245 } MCUCTRL_BOOTLOADER_SBLLOCK_Enum;
64246 
64247 /* ==========================================  MCUCTRL BOOTLOADER PROTLOCK [2..2]  =========================================== */
64248 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_PROTLOCK                                               */
64249   MCUCTRL_BOOTLOADER_PROTLOCK_LOCK     = 1,     /*!< LOCK : Enable the secure boot lock                                        */
64250 } MCUCTRL_BOOTLOADER_PROTLOCK_Enum;
64251 
64252 /* ===========================================  MCUCTRL BOOTLOADER SBRLOCK [1..1]  =========================================== */
64253 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBRLOCK                                                */
64254   MCUCTRL_BOOTLOADER_SBRLOCK_LOCK      = 1,     /*!< LOCK : Enable the secure boot lock                                        */
64255 } MCUCTRL_BOOTLOADER_SBRLOCK_Enum;
64256 
64257 /* ========================================  MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0]  ======================================== */
64258 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW                                          */
64259   MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1,   /*!< ADDR0 : Bootloader code at 0x00000000.                                    */
64260 } MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum;
64261 
64262 /* ======================================================  SHADOWVALID  ====================================================== */
64263 /* =========================================  MCUCTRL SHADOWVALID INFO0VALID [2..2]  ========================================= */
64264 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_INFO0VALID                                            */
64265   MCUCTRL_SHADOWVALID_INFO0VALID_VALID = 1,     /*!< VALID : Flash info0 (customer) space contains valid data.                 */
64266 } MCUCTRL_SHADOWVALID_INFO0VALID_Enum;
64267 
64268 /* ==========================================  MCUCTRL SHADOWVALID BLDSLEEP [1..1]  ========================================== */
64269 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_BLDSLEEP                                              */
64270   MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1,   /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image
64271                                                      loaded                                                                    */
64272 } MCUCTRL_SHADOWVALID_BLDSLEEP_Enum;
64273 
64274 /* ===========================================  MCUCTRL SHADOWVALID VALID [0..0]  ============================================ */
64275 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_VALID                                                 */
64276   MCUCTRL_SHADOWVALID_VALID_VALID      = 1,     /*!< VALID : Flash information space contains valid data.                      */
64277 } MCUCTRL_SHADOWVALID_VALID_Enum;
64278 
64279 /* =======================================================  SCRATCH0  ======================================================== */
64280 /* =========================================================  DBGR1  ========================================================= */
64281 /* =========================================================  DBGR2  ========================================================= */
64282 /* =======================================================  PMUENABLE  ======================================================= */
64283 /* ============================================  MCUCTRL PMUENABLE ENABLE [0..0]  ============================================ */
64284 typedef enum {                                  /*!< MCUCTRL_PMUENABLE_ENABLE                                                  */
64285   MCUCTRL_PMUENABLE_ENABLE_DIS         = 0,     /*!< DIS : Disable MCU power management.                                       */
64286   MCUCTRL_PMUENABLE_ENABLE_EN          = 1,     /*!< EN : Enable MCU power management.                                         */
64287 } MCUCTRL_PMUENABLE_ENABLE_Enum;
64288 
64289 /* ========================================================  DBGCTRL  ======================================================== */
64290 /* =====================================  MCUCTRL DBGCTRL DBGDSP1OCDHALTONRST [17..17]  ====================================== */
64291 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST                                       */
64292   MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_DIS = 0,  /*!< DIS : Disable DSP1 OCD Halt on Reset.                                     */
64293   MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_EN = 1,   /*!< EN : Enable DSP1 OCD Halt on Reset.                                       */
64294 } MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Enum;
64295 
64296 /* =====================================  MCUCTRL DBGCTRL DBGDSP0OCDHALTONRST [16..16]  ====================================== */
64297 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST                                       */
64298   MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_DIS = 0,  /*!< DIS : Disable DSP0 OCD Halt on Reset.                                     */
64299   MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_EN = 1,   /*!< EN : Enable DSP0 OCD Halt on Reset.                                       */
64300 } MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Enum;
64301 
64302 /* =========================================  MCUCTRL DBGCTRL DBGTSCLKSEL [12..14]  ========================================== */
64303 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGTSCLKSEL                                               */
64304   MCUCTRL_DBGCTRL_DBGTSCLKSEL_LOWPWR   = 0,     /*!< LOWPWR : Low power state.                                                 */
64305   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV2 = 1,     /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source dbg ts clk             */
64306   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV8 = 2,     /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source dbg ts clk             */
64307   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV16 = 3,    /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source dbg ts
64308                                                      clk                                                                       */
64309   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV32 = 4,    /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source dbg ts
64310                                                      clk                                                                       */
64311 } MCUCTRL_DBGCTRL_DBGTSCLKSEL_Enum;
64312 
64313 /* ========================================  MCUCTRL DBGCTRL DBGDSP1TRACEEN [11..11]  ======================================== */
64314 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP1TRACEEN                                            */
64315   MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_DIS   = 0,     /*!< DIS : Disable DSP1 trace.                                                 */
64316   MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_EN    = 1,     /*!< EN : Enable DSP1 trace.                                                   */
64317 } MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Enum;
64318 
64319 /* ========================================  MCUCTRL DBGCTRL DBGDSP0TRACEEN [10..10]  ======================================== */
64320 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP0TRACEEN                                            */
64321   MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_DIS   = 0,     /*!< DIS : Disable DSP0 trace.                                                 */
64322   MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_EN    = 1,     /*!< EN : Enable DSP0 trace.                                                   */
64323 } MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Enum;
64324 
64325 /* =========================================  MCUCTRL DBGCTRL DBGETMTRACEEN [9..9]  ========================================== */
64326 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGETMTRACEEN                                             */
64327   MCUCTRL_DBGCTRL_DBGETMTRACEEN_DIS    = 0,     /*!< DIS : Disable ETM trace.                                                  */
64328   MCUCTRL_DBGCTRL_DBGETMTRACEEN_EN     = 1,     /*!< EN : Enable ETM trace.                                                    */
64329 } MCUCTRL_DBGCTRL_DBGETMTRACEEN_Enum;
64330 
64331 /* ==========================================  MCUCTRL DBGCTRL DBGETBENABLE [8..8]  ========================================== */
64332 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGETBENABLE                                              */
64333   MCUCTRL_DBGCTRL_DBGETBENABLE_DIS     = 0,     /*!< DIS : Disable ETB.                                                        */
64334   MCUCTRL_DBGCTRL_DBGETBENABLE_EN      = 1,     /*!< EN : Enable ETB.                                                          */
64335 } MCUCTRL_DBGCTRL_DBGETBENABLE_Enum;
64336 
64337 /* ===========================================  MCUCTRL DBGCTRL DBGCLKSEL [5..7]  ============================================ */
64338 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGCLKSEL                                                 */
64339   MCUCTRL_DBGCTRL_DBGCLKSEL_LOWPWR     = 0,     /*!< LOWPWR : Low power state.                                                 */
64340   MCUCTRL_DBGCTRL_DBGCLKSEL_HFRC96     = 1,     /*!< HFRC96 : Selects HFRC 96Mhz as the source TPIU clk                        */
64341   MCUCTRL_DBGCTRL_DBGCLKSEL_HFRC48     = 2,     /*!< HFRC48 : Selects HFRC 48Mhz as the source TPIU clk                        */
64342   MCUCTRL_DBGCTRL_DBGCLKSEL_HFRC24     = 3,     /*!< HFRC24 : Selects HFRC 24Mhz as the source TPIU clk                        */
64343   MCUCTRL_DBGCTRL_DBGCLKSEL_HFRC6      = 4,     /*!< HFRC6 : Selects HFRC 6Mhz as the source TPIU clk                          */
64344   MCUCTRL_DBGCTRL_DBGCLKSEL_HFRC3      = 5,     /*!< HFRC3 : Selects HFRC 3Mhz as the source TPIU clk                          */
64345   MCUCTRL_DBGCTRL_DBGCLKSEL_HFRC1_5    = 6,     /*!< HFRC1_5 : Selects HFRC 1.5Mhz as the source TPIU clk                      */
64346 } MCUCTRL_DBGCTRL_DBGCLKSEL_Enum;
64347 
64348 /* =========================================  MCUCTRL DBGCTRL DBGTPIUENABLE [4..4]  ========================================== */
64349 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGTPIUENABLE                                             */
64350   MCUCTRL_DBGCTRL_DBGTPIUENABLE_DIS    = 0,     /*!< DIS : Disable the TPIU.                                                   */
64351   MCUCTRL_DBGCTRL_DBGTPIUENABLE_EN     = 1,     /*!< EN : Enable the TPIU.                                                     */
64352 } MCUCTRL_DBGCTRL_DBGTPIUENABLE_Enum;
64353 
64354 /* ===========================================  MCUCTRL DBGCTRL CM4CLKSEL [1..3]  ============================================ */
64355 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_CM4CLKSEL                                                 */
64356   MCUCTRL_DBGCTRL_CM4CLKSEL_LOWPWR     = 0,     /*!< LOWPWR : Low power state.                                                 */
64357   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRCDIV4   = 1,     /*!< HFRCDIV4 : Selects HFRC divided by 4 as the source TPIU clk
64358                                                      (24 MHz).                                                                 */
64359   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRCDIV16  = 2,     /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source TPIU clk
64360                                                      (6 MHz).                                                                  */
64361   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRCDIV32  = 3,     /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source TPIU clk
64362                                                      (3 MHz).                                                                  */
64363   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRCDIV64  = 4,     /*!< HFRCDIV64 : Selects HFRC divided by 64 as the source TPIU clk
64364                                                      (1.5 MHz).                                                                */
64365 } MCUCTRL_DBGCTRL_CM4CLKSEL_Enum;
64366 
64367 /* =========================================  MCUCTRL DBGCTRL CM4TPIUENABLE [0..0]  ========================================== */
64368 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_CM4TPIUENABLE                                             */
64369   MCUCTRL_DBGCTRL_CM4TPIUENABLE_DIS    = 0,     /*!< DIS : Disable the TPIU.                                                   */
64370   MCUCTRL_DBGCTRL_CM4TPIUENABLE_EN     = 1,     /*!< EN : Enable the TPIU.                                                     */
64371 } MCUCTRL_DBGCTRL_CM4TPIUENABLE_Enum;
64372 
64373 /* ======================================================  OTAPOINTER  ======================================================= */
64374 /* ======================================================  APBDMACTRL  ======================================================= */
64375 /* =========================================  MCUCTRL APBDMACTRL DECODEABORT [1..1]  ========================================= */
64376 typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DECODEABORT                                            */
64377   MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0,   /*!< DISABLE : Bus operations to powered down peripherals are quietly
64378                                                      discarded                                                                 */
64379   MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1,    /*!< ENABLE : Bus operations to powered down peripherals result in
64380                                                      a bus fault.                                                              */
64381 } MCUCTRL_APBDMACTRL_DECODEABORT_Enum;
64382 
64383 /* ==========================================  MCUCTRL APBDMACTRL DMAENABLE [0..0]  ========================================== */
64384 typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DMAENABLE                                              */
64385   MCUCTRL_APBDMACTRL_DMAENABLE_DISABLE = 0,     /*!< DISABLE : DMA operations disabled                                         */
64386   MCUCTRL_APBDMACTRL_DMAENABLE_ENABLE  = 1,     /*!< ENABLE : DMA operations enabled                                           */
64387 } MCUCTRL_APBDMACTRL_DMAENABLE_Enum;
64388 
64389 /* ======================================================  KEXTCLKSEL  ======================================================= */
64390 /* =========================================  MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31]  ========================================= */
64391 typedef enum {                                  /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL                                             */
64392   MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key    = 83,    /*!< Key : Key value to unlock the register.                                   */
64393 } MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum;
64394 
64395 /* =======================================================  SIMOBUCK0  ======================================================= */
64396 /* =======================================================  SIMOBUCK1  ======================================================= */
64397 /* =======================================================  SIMOBUCK2  ======================================================= */
64398 /* =======================================================  SIMOBUCK3  ======================================================= */
64399 /* =======================================================  SIMOBUCK4  ======================================================= */
64400 /* =======================================================  SIMOBUCK6  ======================================================= */
64401 /* =======================================================  SIMOBUCK7  ======================================================= */
64402 /* =======================================================  SIMOBUCK8  ======================================================= */
64403 /* =======================================================  SIMOBUCK9  ======================================================= */
64404 /* ======================================================  SIMOBUCK12  ======================================================= */
64405 /* ======================================================  SIMOBUCK13  ======================================================= */
64406 /* ======================================================  SIMOBUCK15  ======================================================= */
64407 /* ========================================================  PWRSW0  ========================================================= */
64408 /* ======================================  MCUCTRL PWRSW0 PWRSWVDDRCPUSTATSEL [30..30]  ====================================== */
64409 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL                                        */
64410   MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDC = 1,  /*!< VDDC : Select VDDC rail                                                   */
64411   MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDFLP = 0,/*!< VDDFLP : Select VDDFLP rail                                               */
64412 } MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Enum;
64413 
64414 /* =====================================  MCUCTRL PWRSW0 PWRSWVDDMDSP1STATSEL [22..22]  ====================================== */
64415 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL                                       */
64416   MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDC = 0, /*!< VDDC : Select VDDC rail                                                   */
64417   MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDF = 1, /*!< VDDF : Select VDDF rail                                                   */
64418 } MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Enum;
64419 
64420 /* =====================================  MCUCTRL PWRSW0 PWRSWVDDMDSP0STATSEL [19..19]  ====================================== */
64421 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL                                       */
64422   MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDC = 0, /*!< VDDC : Select VDDC rail                                                   */
64423   MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDF = 1, /*!< VDDF : Select VDDF rail                                                   */
64424 } MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Enum;
64425 
64426 /* ======================================  MCUCTRL PWRSW0 PWRSWVDDMCPUSTATSEL [16..16]  ====================================== */
64427 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL                                        */
64428   MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDC = 0,  /*!< VDDC : Select VDDC rail                                                   */
64429   MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDF = 1,  /*!< VDDF : Select VDDF rail                                                   */
64430 } MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Enum;
64431 
64432 /* ========================================================  PWRSW1  ========================================================= */
64433 /* ======================================================  FLASHWPROT0  ====================================================== */
64434 /* ======================================================  FLASHWPROT1  ====================================================== */
64435 /* ======================================================  FLASHWPROT2  ====================================================== */
64436 /* ======================================================  FLASHWPROT3  ====================================================== */
64437 /* ======================================================  FLASHRPROT0  ====================================================== */
64438 /* ======================================================  FLASHRPROT1  ====================================================== */
64439 /* ======================================================  FLASHRPROT2  ====================================================== */
64440 /* ======================================================  FLASHRPROT3  ====================================================== */
64441 /* =====================================================  DMASRAMWPROT0  ===================================================== */
64442 /* =====================================================  DMASRAMWPROT1  ===================================================== */
64443 /* =====================================================  DMASRAMRPROT0  ===================================================== */
64444 /* =====================================================  DMASRAMRPROT1  ===================================================== */
64445 /* ======================================================  USBPHYRESET  ====================================================== */
64446 /* =====================================================  AUDADCPWRCTRL  ===================================================== */
64447 /* ====================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCRESETN [10..10]  ===================================== */
64448 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN                                     */
64449   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_ASSERT = 0,/*!< ASSERT : Resetn is asserted                                            */
64450   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_DEASSERT = 1,/*!< DEASSERT : Resetn is de-asserted                                     */
64451 } MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Enum;
64452 
64453 /* ===================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCDIGISOLATE [9..9]  ==================================== */
64454 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE                                 */
64455   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_DIS = 0,/*!< DIS : No Isolation                                                    */
64456   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_EN = 1,/*!< EN : Isolate                                                           */
64457 } MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Enum;
64458 
64459 /* ===================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCSARISOLATE [8..8]  ==================================== */
64460 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE                                 */
64461   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_DIS = 0,/*!< DIS : No Isolation                                                    */
64462   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_EN = 1,/*!< EN : Isolate                                                           */
64463 } MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Enum;
64464 
64465 /* ======================================  MCUCTRL AUDADCPWRCTRL AUDREFKEEPPEN [5..5]  ======================================= */
64466 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN                                       */
64467   MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_DIS = 0,  /*!< DIS : Reference Buffer Keeper Power Switch disable.                       */
64468   MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_EN = 1,   /*!< EN : Reference Buffer Keeper Power Switch enable.                         */
64469 } MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Enum;
64470 
64471 /* =======================================  MCUCTRL AUDADCPWRCTRL AUDREFBUFPEN [4..4]  ======================================= */
64472 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN                                        */
64473   MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_DIS = 0,   /*!< DIS : Reference Buffer Power Switch disable.                              */
64474   MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_EN = 1,    /*!< EN : Reference Buffer Power Switch enable.                                */
64475 } MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Enum;
64476 
64477 /* ========================================  MCUCTRL AUDADCPWRCTRL AUDBGTPEN [3..3]  ========================================= */
64478 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN                                           */
64479   MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_DIS  = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
64480   MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_EN   = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
64481 } MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Enum;
64482 
64483 /* =======================================  MCUCTRL AUDADCPWRCTRL AUDADCBPSEN [2..2]  ======================================== */
64484 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN                                         */
64485   MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_DIS = 0,    /*!< DIS : AUDADC power switch software power disable.                         */
64486   MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_EN = 1,     /*!< EN : AUDADC power switch software power enable.                           */
64487 } MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Enum;
64488 
64489 /* =======================================  MCUCTRL AUDADCPWRCTRL AUDADCAPSEN [1..1]  ======================================== */
64490 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN                                         */
64491   MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_DIS = 0,    /*!< DIS : AUDADC power switch software power disable.                         */
64492   MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_EN = 1,     /*!< EN : AUDADC power switch software power enable.                           */
64493 } MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Enum;
64494 
64495 /* =====================================  MCUCTRL AUDADCPWRCTRL AUDADCPWRCTRLSWE [0..0]  ===================================== */
64496 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE                                    */
64497   MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_DIS = 0,/*!< OVERRIDE_DIS : Audio ADC temperature sensor and bandgap Software
64498                                                      Override Disable.                                                         */
64499   MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_EN = 1,/*!< OVERRIDE_EN : Audio ADC temperature sensor and bandgap Software
64500                                                      Override Enable.                                                          */
64501 } MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Enum;
64502 
64503 /* ========================================================  AUDIO1  ========================================================= */
64504 /* =====================================================  PGAADCIFCTRL  ====================================================== */
64505 /* =======================================================  PGACTRL1  ======================================================== */
64506 /* =======================================================  PGACTRL2  ======================================================== */
64507 /* =====================================================  AUDADCPWRDLY  ====================================================== */
64508 /* =======================================================  SDIOCTRL  ======================================================== */
64509 /* ========================================================  PDMCTRL  ======================================================== */
64510 
64511 
64512 /* =========================================================================================================================== */
64513 /* ================                                           MSPI0                                           ================ */
64514 /* =========================================================================================================================== */
64515 
64516 /* =========================================================  CTRL  ========================================================== */
64517 /* =============================================  MSPI0 CTRL PIOMIXED [13..15]  ============================================== */
64518 typedef enum {                                  /*!< MSPI0_CTRL_PIOMIXED                                                       */
64519   MSPI0_CTRL_PIOMIXED_NORMAL           = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
64520                                                      register (everything in the same data rate)                               */
64521   MSPI0_CTRL_PIOMIXED_D2               = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
64522   MSPI0_CTRL_PIOMIXED_AD2              = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
64523   MSPI0_CTRL_PIOMIXED_D4               = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
64524   MSPI0_CTRL_PIOMIXED_AD4              = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
64525 } MSPI0_CTRL_PIOMIXED_Enum;
64526 
64527 /* ===============================================  MSPI0 CTRL PIODEV [4..4]  ================================================ */
64528 typedef enum {                                  /*!< MSPI0_CTRL_PIODEV                                                         */
64529   MSPI0_CTRL_PIODEV_DEVICE0            = 0,     /*!< DEVICE0 : Use DEVICE0 Configuration                                       */
64530   MSPI0_CTRL_PIODEV_DEVICE1            = 1,     /*!< DEVICE1 : Use DEVICE1 CONFIGURATION                                       */
64531 } MSPI0_CTRL_PIODEV_Enum;
64532 
64533 /* =========================================================  ADDR  ========================================================== */
64534 /* =========================================================  INSTR  ========================================================= */
64535 /* ========================================================  TXFIFO  ========================================================= */
64536 /* ========================================================  RXFIFO  ========================================================= */
64537 /* =======================================================  TXENTRIES  ======================================================= */
64538 /* =======================================================  RXENTRIES  ======================================================= */
64539 /* =======================================================  THRESHOLD  ======================================================= */
64540 /* ========================================================  MSPICFG  ======================================================== */
64541 /* ==============================================  MSPI0 MSPICFG IOMSEL [4..7]  ============================================== */
64542 typedef enum {                                  /*!< MSPI0_MSPICFG_IOMSEL                                                      */
64543   MSPI0_MSPICFG_IOMSEL_IOM0            = 0,     /*!< IOM0 : ERROR: desc VALUE MISSING                                          */
64544   MSPI0_MSPICFG_IOMSEL_IOM1            = 1,     /*!< IOM1 : ERROR: desc VALUE MISSING                                          */
64545   MSPI0_MSPICFG_IOMSEL_IOM2            = 2,     /*!< IOM2 : ERROR: desc VALUE MISSING                                          */
64546   MSPI0_MSPICFG_IOMSEL_IOM3            = 3,     /*!< IOM3 : ERROR: desc VALUE MISSING                                          */
64547   MSPI0_MSPICFG_IOMSEL_IOM4            = 4,     /*!< IOM4 : ERROR: desc VALUE MISSING                                          */
64548   MSPI0_MSPICFG_IOMSEL_IOM5            = 5,     /*!< IOM5 : ERROR: desc VALUE MISSING                                          */
64549   MSPI0_MSPICFG_IOMSEL_IOM6            = 6,     /*!< IOM6 : ERROR: desc VALUE MISSING                                          */
64550   MSPI0_MSPICFG_IOMSEL_IOM7            = 7,     /*!< IOM7 : ERROR: desc VALUE MISSING                                          */
64551   MSPI0_MSPICFG_IOMSEL_MSPI0           = 8,     /*!< MSPI0 : ERROR: desc VALUE MISSING                                         */
64552   MSPI0_MSPICFG_IOMSEL_MSPI1           = 9,     /*!< MSPI1 : ERROR: desc VALUE MISSING                                         */
64553   MSPI0_MSPICFG_IOMSEL_MSPI2           = 10,    /*!< MSPI2 : ERROR: desc VALUE MISSING                                         */
64554 } MSPI0_MSPICFG_IOMSEL_Enum;
64555 
64556 /* ==============================================  MSPI0 MSPICFG APBCLK [0..0]  ============================================== */
64557 typedef enum {                                  /*!< MSPI0_MSPICFG_APBCLK                                                      */
64558   MSPI0_MSPICFG_APBCLK_DIS             = 0,     /*!< DIS : Disable continuous clock.                                           */
64559   MSPI0_MSPICFG_APBCLK_EN              = 1,     /*!< EN : Enable continuous clock.                                             */
64560 } MSPI0_MSPICFG_APBCLK_Enum;
64561 
64562 /* =======================================================  PADOUTEN  ======================================================== */
64563 /* ==============================================  MSPI0 PADOUTEN OUTEN [0..9]  ============================================== */
64564 typedef enum {                                  /*!< MSPI0_PADOUTEN_OUTEN                                                      */
64565   MSPI0_PADOUTEN_OUTEN_QUAD0           = 271,   /*!< QUAD0 : Quad0 (4 data + 1 clock)                                          */
64566   MSPI0_PADOUTEN_OUTEN_QUAD1           = 496,   /*!< QUAD1 : Quad1 (4 data + 1 clock)                                          */
64567   MSPI0_PADOUTEN_OUTEN_OCTAL           = 1023,  /*!< OCTAL : Octal (8 data + 1 clock)                                          */
64568   MSPI0_PADOUTEN_OUTEN_SERIAL0         = 259,   /*!< SERIAL0 : Serial (2 data + 1 clock)                                       */
64569   MSPI0_PADOUTEN_OUTEN_SERIAL1         = 304,   /*!< SERIAL1 : Serial (2 data + 1 clock)                                       */
64570 } MSPI0_PADOUTEN_OUTEN_Enum;
64571 
64572 /* =======================================================  PADOVEREN  ======================================================= */
64573 /* ========================================================  PADOVER  ======================================================== */
64574 /* ========================================================  DEV0AXI  ======================================================== */
64575 /* ============================================  MSPI0 DEV0AXI READONLY0 [4..4]  ============================================= */
64576 typedef enum {                                  /*!< MSPI0_DEV0AXI_READONLY0                                                   */
64577   MSPI0_DEV0AXI_READONLY0_READONLY     = 1,     /*!< READONLY : Indicates AXI aperture only supports read operations           */
64578   MSPI0_DEV0AXI_READONLY0_READWRITE    = 0,     /*!< READWRITE : Indicates AXI aperture supports read and write operations     */
64579 } MSPI0_DEV0AXI_READONLY0_Enum;
64580 
64581 /* ==============================================  MSPI0 DEV0AXI SIZE0 [0..3]  =============================================== */
64582 typedef enum {                                  /*!< MSPI0_DEV0AXI_SIZE0                                                       */
64583   MSPI0_DEV0AXI_SIZE0_SIZE64K          = 0,     /*!< SIZE64K : 64KB Aperture                                                   */
64584   MSPI0_DEV0AXI_SIZE0_SIZE128K         = 1,     /*!< SIZE128K : 128KB Aperture                                                 */
64585   MSPI0_DEV0AXI_SIZE0_SIZE256K         = 2,     /*!< SIZE256K : 256KB Aperture                                                 */
64586   MSPI0_DEV0AXI_SIZE0_SIZE512K         = 3,     /*!< SIZE512K : 512KB Aperture                                                 */
64587   MSPI0_DEV0AXI_SIZE0_SIZE1M           = 4,     /*!< SIZE1M : 1MB Aperture                                                     */
64588   MSPI0_DEV0AXI_SIZE0_SIZE2M           = 5,     /*!< SIZE2M : 2MB Aperture                                                     */
64589   MSPI0_DEV0AXI_SIZE0_SIZE4M           = 6,     /*!< SIZE4M : 4MB Aperture                                                     */
64590   MSPI0_DEV0AXI_SIZE0_SIZE8M           = 7,     /*!< SIZE8M : 8MB Aperture                                                     */
64591   MSPI0_DEV0AXI_SIZE0_SIZE16M          = 8,     /*!< SIZE16M : 16MB Aperture                                                   */
64592   MSPI0_DEV0AXI_SIZE0_SIZE32M          = 9,     /*!< SIZE32M : 32MB Aperture                                                   */
64593   MSPI0_DEV0AXI_SIZE0_SIZE64M          = 10,    /*!< SIZE64M : 64MB Aperture                                                   */
64594 } MSPI0_DEV0AXI_SIZE0_Enum;
64595 
64596 /* ========================================================  DEV0CFG  ======================================================== */
64597 /* =============================================  MSPI0 DEV0CFG TXNEG0 [24..24]  ============================================= */
64598 typedef enum {                                  /*!< MSPI0_DEV0CFG_TXNEG0                                                      */
64599   MSPI0_DEV0CFG_TXNEG0_NORMAL          = 0,     /*!< NORMAL : TX launched from posedge internal clock                          */
64600   MSPI0_DEV0CFG_TXNEG0_NEGEDGE         = 1,     /*!< NEGEDGE : TX data launched from negedge of internal clock                 */
64601 } MSPI0_DEV0CFG_TXNEG0_Enum;
64602 
64603 /* =============================================  MSPI0 DEV0CFG RXNEG0 [23..23]  ============================================= */
64604 typedef enum {                                  /*!< MSPI0_DEV0CFG_RXNEG0                                                      */
64605   MSPI0_DEV0CFG_RXNEG0_NORMAL          = 0,     /*!< NORMAL : RX data sampled on posedge of internal clock                     */
64606   MSPI0_DEV0CFG_RXNEG0_NEGEDGE         = 1,     /*!< NEGEDGE : RX data sampled on negedge of internal clock                    */
64607 } MSPI0_DEV0CFG_RXNEG0_Enum;
64608 
64609 /* =============================================  MSPI0 DEV0CFG RXCAP0 [22..22]  ============================================= */
64610 typedef enum {                                  /*!< MSPI0_DEV0CFG_RXCAP0                                                      */
64611   MSPI0_DEV0CFG_RXCAP0_NORMAL          = 0,     /*!< NORMAL : RX Capture phase aligns with CPHA setting                        */
64612   MSPI0_DEV0CFG_RXCAP0_DELAY           = 1,     /*!< DELAY : RX Capture phase is delayed from CPHA setting by one
64613                                                      clock edge                                                                */
64614 } MSPI0_DEV0CFG_RXCAP0_Enum;
64615 
64616 /* ============================================  MSPI0 DEV0CFG CLKDIV0 [16..21]  ============================================= */
64617 typedef enum {                                  /*!< MSPI0_DEV0CFG_CLKDIV0                                                     */
64618   MSPI0_DEV0CFG_CLKDIV0_CLK96          = 1,     /*!< CLK96 : 96 MHz MSPI clock                                                 */
64619   MSPI0_DEV0CFG_CLKDIV0_CLK48          = 2,     /*!< CLK48 : 48 MHz MSPI clock                                                 */
64620   MSPI0_DEV0CFG_CLKDIV0_CLK32          = 3,     /*!< CLK32 : 32 MHz MSPI clock                                                 */
64621   MSPI0_DEV0CFG_CLKDIV0_CLK24          = 4,     /*!< CLK24 : 24 MHz MSPI clock                                                 */
64622   MSPI0_DEV0CFG_CLKDIV0_CLK16          = 6,     /*!< CLK16 : 16 MHz MSPI clock                                                 */
64623   MSPI0_DEV0CFG_CLKDIV0_CLK12          = 8,     /*!< CLK12 : 12 MHz MSPI clock                                                 */
64624   MSPI0_DEV0CFG_CLKDIV0_CLK8           = 12,    /*!< CLK8 : 8 MHz MSPI clock                                                   */
64625   MSPI0_DEV0CFG_CLKDIV0_CLK6           = 16,    /*!< CLK6 : 6 MHz MSPI clock                                                   */
64626   MSPI0_DEV0CFG_CLKDIV0_CLK4           = 24,    /*!< CLK4 : 4 MHz MSPI clock                                                   */
64627   MSPI0_DEV0CFG_CLKDIV0_CLK3           = 32,    /*!< CLK3 : 3 MHz MSPI clock                                                   */
64628 } MSPI0_DEV0CFG_CLKDIV0_Enum;
64629 
64630 /* =============================================  MSPI0 DEV0CFG CPOL0 [15..15]  ============================================== */
64631 typedef enum {                                  /*!< MSPI0_DEV0CFG_CPOL0                                                       */
64632   MSPI0_DEV0CFG_CPOL0_LOW              = 0,     /*!< LOW : Clock inactive state is low.                                        */
64633   MSPI0_DEV0CFG_CPOL0_HIGH             = 1,     /*!< HIGH : Clock inactive state is high.                                      */
64634 } MSPI0_DEV0CFG_CPOL0_Enum;
64635 
64636 /* =============================================  MSPI0 DEV0CFG CPHA0 [14..14]  ============================================== */
64637 typedef enum {                                  /*!< MSPI0_DEV0CFG_CPHA0                                                       */
64638   MSPI0_DEV0CFG_CPHA0_MIDDLE           = 0,     /*!< MIDDLE : Clock toggles in middle of data bit.                             */
64639   MSPI0_DEV0CFG_CPHA0_START            = 1,     /*!< START : Clock toggles at start of data bit.                               */
64640 } MSPI0_DEV0CFG_CPHA0_Enum;
64641 
64642 /* ==============================================  MSPI0 DEV0CFG ISIZE0 [6..6]  ============================================== */
64643 typedef enum {                                  /*!< MSPI0_DEV0CFG_ISIZE0                                                      */
64644   MSPI0_DEV0CFG_ISIZE0_I8              = 0,     /*!< I8 : Instruction is 1 byte                                                */
64645   MSPI0_DEV0CFG_ISIZE0_I16             = 1,     /*!< I16 : Instruction is 2 bytes                                              */
64646 } MSPI0_DEV0CFG_ISIZE0_Enum;
64647 
64648 /* ==============================================  MSPI0 DEV0CFG ASIZE0 [4..5]  ============================================== */
64649 typedef enum {                                  /*!< MSPI0_DEV0CFG_ASIZE0                                                      */
64650   MSPI0_DEV0CFG_ASIZE0_A1              = 0,     /*!< A1 : Send one address byte                                                */
64651   MSPI0_DEV0CFG_ASIZE0_A2              = 1,     /*!< A2 : Send two address bytes                                               */
64652   MSPI0_DEV0CFG_ASIZE0_A3              = 2,     /*!< A3 : Send three address bytes                                             */
64653   MSPI0_DEV0CFG_ASIZE0_A4              = 3,     /*!< A4 : Send four address bytes                                              */
64654 } MSPI0_DEV0CFG_ASIZE0_Enum;
64655 
64656 /* =============================================  MSPI0 DEV0CFG DEVCFG0 [0..3]  ============================================== */
64657 typedef enum {                                  /*!< MSPI0_DEV0CFG_DEVCFG0                                                     */
64658   MSPI0_DEV0CFG_DEVCFG0_SERIAL0        = 1,     /*!< SERIAL0 : Single bit SPI flash on chip select 0                           */
64659   MSPI0_DEV0CFG_DEVCFG0_SERIAL1        = 2,     /*!< SERIAL1 : Single bit SPI flash on chip select 1                           */
64660   MSPI0_DEV0CFG_DEVCFG0_DUAL0          = 5,     /*!< DUAL0 : Dual SPI flash on chip select 0                                   */
64661   MSPI0_DEV0CFG_DEVCFG0_DUAL1          = 6,     /*!< DUAL1 : Dual bit SPI flash on chip select 1                               */
64662   MSPI0_DEV0CFG_DEVCFG0_QUAD0          = 9,     /*!< QUAD0 : Quad SPI flash on chip select 0                                   */
64663   MSPI0_DEV0CFG_DEVCFG0_QUAD1          = 10,    /*!< QUAD1 : Quad SPI flash on chip select 1                                   */
64664   MSPI0_DEV0CFG_DEVCFG0_OCTAL0         = 13,    /*!< OCTAL0 : Octal SPI flash on chip select 0                                 */
64665   MSPI0_DEV0CFG_DEVCFG0_OCTAL1         = 14,    /*!< OCTAL1 : Octal SPI flash on chip select 1                                 */
64666   MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED     = 15,    /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1.                     */
64667   MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED_SERIAL = 3,  /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1,
64668                                                      but transmit in serial mode for initialization operations                 */
64669 } MSPI0_DEV0CFG_DEVCFG0_Enum;
64670 
64671 /* ========================================================  DEV0DDR  ======================================================== */
64672 /* ========================================================  DEV0XIP  ======================================================== */
64673 /* ============================================  MSPI0 DEV0XIP XIPMIXED0 [8..10]  ============================================ */
64674 typedef enum {                                  /*!< MSPI0_DEV0XIP_XIPMIXED0                                                   */
64675   MSPI0_DEV0XIP_XIPMIXED0_NORMAL       = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
64676                                                      register (everything in the same data rate)                               */
64677   MSPI0_DEV0XIP_XIPMIXED0_D2           = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
64678   MSPI0_DEV0XIP_XIPMIXED0_AD2          = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
64679   MSPI0_DEV0XIP_XIPMIXED0_D4           = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
64680   MSPI0_DEV0XIP_XIPMIXED0_AD4          = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
64681 } MSPI0_DEV0XIP_XIPMIXED0_Enum;
64682 
64683 /* =============================================  MSPI0 DEV0XIP XIPACK0 [2..3]  ============================================== */
64684 typedef enum {                                  /*!< MSPI0_DEV0XIP_XIPACK0                                                     */
64685   MSPI0_DEV0XIP_XIPACK0_NOACK          = 0,     /*!< NOACK : No acknowledege sent. Data IOs are tristated the first
64686                                                      turnaround cycle                                                          */
64687   MSPI0_DEV0XIP_XIPACK0_ACK            = 2,     /*!< ACK : Positive acknowledege sent. Data IOs are driven to 0 the
64688                                                      first turnaround cycle to acknowledge XIP mode                            */
64689   MSPI0_DEV0XIP_XIPACK0_TERMINATE      = 3,     /*!< TERMINATE : Negative acknowledege sent. Data IOs are driven
64690                                                      to 1 the first turnaround cycle to terminate XIP mode.
64691                                                      XIPSENDI should be reenabled for the next transfer                        */
64692 } MSPI0_DEV0XIP_XIPACK0_Enum;
64693 
64694 /* =======================================================  DEV0INSTR  ======================================================= */
64695 /* =====================================================  DEV0BOUNDARY  ====================================================== */
64696 /* =========================================  MSPI0 DEV0BOUNDARY DMABOUND0 [12..15]  ========================================= */
64697 typedef enum {                                  /*!< MSPI0_DEV0BOUNDARY_DMABOUND0                                              */
64698   MSPI0_DEV0BOUNDARY_DMABOUND0_NONE    = 0,     /*!< NONE : Disable DMA address boundary breaks                                */
64699   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK32 = 1,     /*!< BREAK32 : Break at 32 byte boundary (0x20 increments)                     */
64700   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK64 = 2,     /*!< BREAK64 : Break at 64 byte boundary (0x40 increments)                     */
64701   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK128 = 3,    /*!< BREAK128 : Break at 128 byte boundary (0x80 increments)                   */
64702   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK256 = 4,    /*!< BREAK256 : Break at 256 byte boundary (0x100 increments)                  */
64703   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK512 = 5,    /*!< BREAK512 : Break at 512 byte boundary (0x200 increments)                  */
64704   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK1K = 6,     /*!< BREAK1K : Break at 1KB boundary (0x400 increments)                        */
64705   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK2K = 7,     /*!< BREAK2K : Break at 2KB boundary (0x800 increments)                        */
64706   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK4K = 8,     /*!< BREAK4K : Break at 4KB boundary (0x1000 increments)                       */
64707   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK8K = 9,     /*!< BREAK8K : Break at 8KB boundary (0x2000 increments)                       */
64708   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK16K = 10,   /*!< BREAK16K : Break at 16KB boundary (0x4000 increments)                     */
64709 } MSPI0_DEV0BOUNDARY_DMABOUND0_Enum;
64710 
64711 /* ====================================================  DEV0SCRAMBLING  ===================================================== */
64712 /* ======================================================  DEV0XIPMISC  ====================================================== */
64713 /* ==========================================  MSPI0 DEV0XIPMISC APNDODD0 [21..21]  ========================================== */
64714 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_APNDODD0                                                */
64715   MSPI0_DEV0XIPMISC_APNDODD0_DIS       = 0,     /*!< DIS : No appending byte                                                   */
64716   MSPI0_DEV0XIPMISC_APNDODD0_EN        = 1,     /*!< EN : Append one dummy byte                                                */
64717 } MSPI0_DEV0XIPMISC_APNDODD0_Enum;
64718 
64719 /* ========================================  MSPI0 DEV0XIPMISC XIPBOUNDARY0 [15..15]  ======================================== */
64720 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_XIPBOUNDARY0                                            */
64721   MSPI0_DEV0XIPMISC_XIPBOUNDARY0_DIS   = 0,     /*!< DIS : ERROR: desc VALUE MISSING                                           */
64722   MSPI0_DEV0XIPMISC_XIPBOUNDARY0_EN    = 1,     /*!< EN : ERROR: desc VALUE MISSING                                            */
64723 } MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Enum;
64724 
64725 /* ===========================================  MSPI0 DEV0XIPMISC BEON0 [14..14]  ============================================ */
64726 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_BEON0                                                   */
64727   MSPI0_DEV0XIPMISC_BEON0_DIS          = 0,     /*!< DIS : Byte enable is calculated on the fly                                */
64728   MSPI0_DEV0XIPMISC_BEON0_EN           = 1,     /*!< EN : Byte enable of all bytes are always on                               */
64729 } MSPI0_DEV0XIPMISC_BEON0_Enum;
64730 
64731 /* ==========================================  MSPI0 DEV0XIPMISC XIPODD0 [12..12]  =========================================== */
64732 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_XIPODD0                                                 */
64733   MSPI0_DEV0XIPMISC_XIPODD0_DIS        = 0,     /*!< DIS : No conversion                                                       */
64734   MSPI0_DEV0XIPMISC_XIPODD0_EN         = 1,     /*!< EN : Enable the conversion                                                */
64735 } MSPI0_DEV0XIPMISC_XIPODD0_Enum;
64736 
64737 /* ========================================================  DMACFG  ========================================================= */
64738 /* ==============================================  MSPI0 DMACFG DMAPRI [4..5]  =============================================== */
64739 typedef enum {                                  /*!< MSPI0_DMACFG_DMAPRI                                                       */
64740   MSPI0_DMACFG_DMAPRI_LOW              = 0,     /*!< LOW : Low Priority (service as best effort)                               */
64741   MSPI0_DMACFG_DMAPRI_HIGH             = 1,     /*!< HIGH : High Priority (service immediately)                                */
64742   MSPI0_DMACFG_DMAPRI_AUTO             = 2,     /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or
64743                                                      RX FIFO fills)                                                            */
64744 } MSPI0_DMACFG_DMAPRI_Enum;
64745 
64746 /* ==============================================  MSPI0 DMACFG DMADEV [3..3]  =============================================== */
64747 typedef enum {                                  /*!< MSPI0_DMACFG_DMADEV                                                       */
64748   MSPI0_DMACFG_DMADEV_DEV0             = 0,     /*!< DEV0 : Select Device 0 for DMA                                            */
64749 } MSPI0_DMACFG_DMADEV_Enum;
64750 
64751 /* ==============================================  MSPI0 DMACFG DMADIR [2..2]  =============================================== */
64752 typedef enum {                                  /*!< MSPI0_DMACFG_DMADIR                                                       */
64753   MSPI0_DMACFG_DMADIR_P2M              = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
64754   MSPI0_DMACFG_DMADIR_M2P              = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
64755 } MSPI0_DMACFG_DMADIR_Enum;
64756 
64757 /* ===============================================  MSPI0 DMACFG DMAEN [0..1]  =============================================== */
64758 typedef enum {                                  /*!< MSPI0_DMACFG_DMAEN                                                        */
64759   MSPI0_DMACFG_DMAEN_DIS               = 0,     /*!< DIS : Disable DMA Function                                                */
64760   MSPI0_DMACFG_DMAEN_EN                = 3,     /*!< EN : Enable HW controlled DMA Function to manage DMA to flash
64761                                                      devices. HW will automatically handle issuance of instruction/address
64762                                                      bytes based on settings in the FLASH register.                            */
64763 } MSPI0_DMACFG_DMAEN_Enum;
64764 
64765 /* ========================================================  DMASTAT  ======================================================== */
64766 /* ======================================================  DMATARGADDR  ====================================================== */
64767 /* ======================================================  DMADEVADDR  ======================================================= */
64768 /* ======================================================  DMATOTCOUNT  ====================================================== */
64769 /* =======================================================  DMABCOUNT  ======================================================= */
64770 /* =======================================================  DMATHRESH  ======================================================= */
64771 /* =========================================================  INTEN  ========================================================= */
64772 /* ========================================================  INTSTAT  ======================================================== */
64773 /* ========================================================  INTCLR  ========================================================= */
64774 /* ========================================================  INTSET  ========================================================= */
64775 /* =========================================================  CQCFG  ========================================================= */
64776 /* ===============================================  MSPI0 CQCFG CQPRI [1..1]  ================================================ */
64777 typedef enum {                                  /*!< MSPI0_CQCFG_CQPRI                                                         */
64778   MSPI0_CQCFG_CQPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
64779   MSPI0_CQCFG_CQPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
64780 } MSPI0_CQCFG_CQPRI_Enum;
64781 
64782 /* ================================================  MSPI0 CQCFG CQEN [0..0]  ================================================ */
64783 typedef enum {                                  /*!< MSPI0_CQCFG_CQEN                                                          */
64784   MSPI0_CQCFG_CQEN_DIS                 = 0,     /*!< DIS : Disable CQ Function                                                 */
64785   MSPI0_CQCFG_CQEN_EN                  = 1,     /*!< EN : Enable CQ Function                                                   */
64786 } MSPI0_CQCFG_CQEN_Enum;
64787 
64788 /* ========================================================  CQADDR  ========================================================= */
64789 /* ========================================================  CQSTAT  ========================================================= */
64790 /* ========================================================  CQFLAGS  ======================================================== */
64791 /* =============================================  MSPI0 CQFLAGS CQFLAGS [0..15]  ============================================= */
64792 typedef enum {                                  /*!< MSPI0_CQFLAGS_CQFLAGS                                                     */
64793   MSPI0_CQFLAGS_CQFLAGS_STOP           = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
64794   MSPI0_CQFLAGS_CQFLAGS_CQIDX          = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
64795   MSPI0_CQFLAGS_CQFLAGS_BUF1XOREN      = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
64796                                                      This status is the result of XOR'ing the IOM1START with
64797                                                      the incoming status from the IOM. When high, MSPI can transfer
64798                                                      the buffer.                                                               */
64799   MSPI0_CQFLAGS_CQFLAGS_BUF0XOREN      = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
64800                                                      This status is the result of XOR'ing the IOM0START with
64801                                                      the incoming status from the IOM. When high, MSPI can transfer
64802                                                      the buffer.                                                               */
64803   MSPI0_CQFLAGS_CQFLAGS_DMACPL         = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
64804   MSPI0_CQFLAGS_CQFLAGS_CMDCPL         = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
64805   MSPI0_CQFLAGS_CQFLAGS_IOM1READY      = 512,   /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
64806                                                      status is the result of XNOR'ing the IOM0START with the
64807                                                      incoming status from the IOM. When high, MSPI can send
64808                                                      to the buffer.                                                            */
64809   MSPI0_CQFLAGS_CQFLAGS_IOM0READY      = 256,   /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
64810                                                      status is the result of XNOR'ing the IOM0START with the
64811                                                      incoming status from the IOM. When high, MSPI can send
64812                                                      to the buffer.                                                            */
64813   MSPI0_CQFLAGS_CQFLAGS_SWFLAG7        = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
64814                                                      operations.                                                               */
64815   MSPI0_CQFLAGS_CQFLAGS_SWFLAG6        = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
64816                                                      operations.                                                               */
64817   MSPI0_CQFLAGS_CQFLAGS_SWFLAG5        = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
64818                                                      operations.                                                               */
64819   MSPI0_CQFLAGS_CQFLAGS_SWFLAG4        = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
64820                                                      operations.                                                               */
64821   MSPI0_CQFLAGS_CQFLAGS_SWFLAG3        = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
64822                                                      operations.                                                               */
64823   MSPI0_CQFLAGS_CQFLAGS_SWFLAG2        = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
64824                                                      operations.                                                               */
64825   MSPI0_CQFLAGS_CQFLAGS_SWFLAG1        = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
64826                                                      operations.                                                               */
64827   MSPI0_CQFLAGS_CQFLAGS_SWFLAG0        = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
64828                                                      operations.                                                               */
64829 } MSPI0_CQFLAGS_CQFLAGS_Enum;
64830 
64831 /* ======================================================  CQSETCLEAR  ======================================================= */
64832 /* ========================================================  CQPAUSE  ======================================================== */
64833 /* =============================================  MSPI0 CQPAUSE CQMASK [0..15]  ============================================== */
64834 typedef enum {                                  /*!< MSPI0_CQPAUSE_CQMASK                                                      */
64835   MSPI0_CQPAUSE_CQMASK_STOP            = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
64836   MSPI0_CQPAUSE_CQMASK_CQIDX           = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
64837   MSPI0_CQPAUSE_CQMASK_BUF1XOREN       = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
64838                                                      This status is the result of XOR'ing the IOM1START with
64839                                                      the incoming status from the IOM. When high, MSPI can transfer
64840                                                      the buffer.                                                               */
64841   MSPI0_CQPAUSE_CQMASK_BUF0XOREN       = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
64842                                                      This status is the result of XOR'ing the IOM0START with
64843                                                      the incoming status from the IOM. When high, MSPI can transfer
64844                                                      the buffer.                                                               */
64845   MSPI0_CQPAUSE_CQMASK_DMACPL          = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
64846   MSPI0_CQPAUSE_CQMASK_CMDCPL          = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
64847   MSPI0_CQPAUSE_CQMASK_IOM1READY       = 512,   /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
64848                                                      status is the result of XNOR'ing the IOM0START with the
64849                                                      incoming status from the IOM. When high, MSPI can send
64850                                                      to the buffer.                                                            */
64851   MSPI0_CQPAUSE_CQMASK_IOM0READY       = 256,   /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
64852                                                      status is the result of XNOR'ing the IOM0START with the
64853                                                      incoming status from the IOM. When high, MSPI can send
64854                                                      to the buffer.                                                            */
64855   MSPI0_CQPAUSE_CQMASK_SWFLAG7         = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
64856                                                      operations.                                                               */
64857   MSPI0_CQPAUSE_CQMASK_SWFLAG6         = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
64858                                                      operations.                                                               */
64859   MSPI0_CQPAUSE_CQMASK_SWFLAG5         = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
64860                                                      operations.                                                               */
64861   MSPI0_CQPAUSE_CQMASK_SWFLAG4         = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
64862                                                      operations.                                                               */
64863   MSPI0_CQPAUSE_CQMASK_SWFLAG3         = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
64864                                                      operations.                                                               */
64865   MSPI0_CQPAUSE_CQMASK_SWFLAG2         = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
64866                                                      operations.                                                               */
64867   MSPI0_CQPAUSE_CQMASK_SWFLAG1         = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
64868                                                      operations.                                                               */
64869   MSPI0_CQPAUSE_CQMASK_SWFLAG0         = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
64870                                                      operations.                                                               */
64871 } MSPI0_CQPAUSE_CQMASK_Enum;
64872 
64873 /* =======================================================  CQCURIDX  ======================================================== */
64874 /* =======================================================  CQENDIDX  ======================================================== */
64875 
64876 
64877 /* =========================================================================================================================== */
64878 /* ================                                           PDM0                                            ================ */
64879 /* =========================================================================================================================== */
64880 
64881 /* =========================================================  CTRL  ========================================================== */
64882 /* ==================================================  PDM0 CTRL EN [6..6]  ================================================== */
64883 typedef enum {                                  /*!< PDM0_CTRL_EN                                                              */
64884   PDM0_CTRL_EN_DIS                     = 0,     /*!< DIS : Disable PDM.                                                        */
64885   PDM0_CTRL_EN_EN                      = 1,     /*!< EN : Enable PDM.                                                          */
64886 } PDM0_CTRL_EN_Enum;
64887 
64888 /* ===============================================  PDM0 CTRL PCMPACK [5..5]  ================================================ */
64889 typedef enum {                                  /*!< PDM0_CTRL_PCMPACK                                                         */
64890   PDM0_CTRL_PCMPACK_DIS                = 0,     /*!< DIS : Disable PCM packing.                                                */
64891   PDM0_CTRL_PCMPACK_EN                 = 1,     /*!< EN : Enable PCM packing.                                                  */
64892 } PDM0_CTRL_PCMPACK_Enum;
64893 
64894 /* =================================================  PDM0 CTRL RSTB [4..4]  ================================================= */
64895 typedef enum {                                  /*!< PDM0_CTRL_RSTB                                                            */
64896   PDM0_CTRL_RSTB_RESET                 = 0,     /*!< RESET : Put the core in reset.                                            */
64897   PDM0_CTRL_RSTB_NORMAL                = 1,     /*!< NORMAL : Core not in reset.                                               */
64898 } PDM0_CTRL_RSTB_Enum;
64899 
64900 /* ================================================  PDM0 CTRL CLKEN [0..0]  ================================================= */
64901 typedef enum {                                  /*!< PDM0_CTRL_CLKEN                                                           */
64902   PDM0_CTRL_CLKEN_DIS                  = 0,     /*!< DIS : Disable serial clock                                                */
64903   PDM0_CTRL_CLKEN_EN                   = 1,     /*!< EN : Enable serial clock                                                  */
64904 } PDM0_CTRL_CLKEN_Enum;
64905 
64906 /* =======================================================  CORECFG0  ======================================================== */
64907 /* ==============================================  PDM0 CORECFG0 PGAR [26..30]  ============================================== */
64908 typedef enum {                                  /*!< PDM0_CORECFG0_PGAR                                                        */
64909   PDM0_CORECFG0_PGAR_M12_0DB           = 0,     /*!< M12_0DB : Right channel PGA gain = -12.0 dB                               */
64910   PDM0_CORECFG0_PGAR_M10_5DB           = 1,     /*!< M10_5DB : Right channel PGA gain = -10.5 dB                               */
64911   PDM0_CORECFG0_PGAR_M9_0DB            = 2,     /*!< M9_0DB : Right channel PGA gain = -9.0 dB                                 */
64912   PDM0_CORECFG0_PGAR_M7_5DB            = 3,     /*!< M7_5DB : Right channel PGA gain = -7.5 dB                                 */
64913   PDM0_CORECFG0_PGAR_M6_0DB            = 4,     /*!< M6_0DB : Right channel PGA gain = -6.0 dB                                 */
64914   PDM0_CORECFG0_PGAR_M4_5DB            = 5,     /*!< M4_5DB : Right channel PGA gain = -4.5 dB                                 */
64915   PDM0_CORECFG0_PGAR_M3_0DB            = 6,     /*!< M3_0DB : Right channel PGA gain = -3.0 dB                                 */
64916   PDM0_CORECFG0_PGAR_M1_5DB            = 7,     /*!< M1_5DB : Right channel PGA gain = -1.5 dB                                 */
64917   PDM0_CORECFG0_PGAR_0DB               = 8,     /*!< 0DB : Right channel PGA gain = 0 DB                                       */
64918   PDM0_CORECFG0_PGAR_P1_5DB            = 9,     /*!< P1_5DB : Right channel PGA gain = 1.5 dB                                  */
64919   PDM0_CORECFG0_PGAR_P3_0DB            = 10,    /*!< P3_0DB : Right channel PGA gain = 3.0 dB                                  */
64920   PDM0_CORECFG0_PGAR_P4_5DB            = 11,    /*!< P4_5DB : Right channel PGA gain = 4.5 dB                                  */
64921   PDM0_CORECFG0_PGAR_P6_0DB            = 12,    /*!< P6_0DB : Right channel PGA gain = 6.0 DB                                  */
64922   PDM0_CORECFG0_PGAR_P7_5DB            = 13,    /*!< P7_5DB : Right channel PGA gain = 7.5 dB                                  */
64923   PDM0_CORECFG0_PGAR_P9_0DB            = 14,    /*!< P9_0DB : Right channel PGA gain = 9.0 dB                                  */
64924   PDM0_CORECFG0_PGAR_P10_5DB           = 15,    /*!< P10_5DB : Right channel PGA gain = 10.5 dB                                */
64925   PDM0_CORECFG0_PGAR_P12_0DB           = 16,    /*!< P12_0DB : Right channel PGA gain = 12.0 DB                                */
64926   PDM0_CORECFG0_PGAR_P13_5DB           = 17,    /*!< P13_5DB : Right channel PGA gain = 13.5 dB                                */
64927   PDM0_CORECFG0_PGAR_P15_0DB           = 18,    /*!< P15_0DB : Right channel PGA gain = 15.0 dB                                */
64928   PDM0_CORECFG0_PGAR_P16_5DB           = 19,    /*!< P16_5DB : Right channel PGA gain = 16.5 dB                                */
64929   PDM0_CORECFG0_PGAR_P18_0DB           = 20,    /*!< P18_0DB : Right channel PGA gain = 18.0 DB                                */
64930   PDM0_CORECFG0_PGAR_P19_5DB           = 21,    /*!< P19_5DB : Right channel PGA gain = 19.5 dB                                */
64931   PDM0_CORECFG0_PGAR_P21_0DB           = 22,    /*!< P21_0DB : Right channel PGA gain = 21.0 dB                                */
64932   PDM0_CORECFG0_PGAR_P22_5DB           = 23,    /*!< P22_5DB : Right channel PGA gain = 22.5 dB                                */
64933   PDM0_CORECFG0_PGAR_P24_0DB           = 24,    /*!< P24_0DB : Right channel PGA gain = 24.0 DB                                */
64934   PDM0_CORECFG0_PGAR_P25_5DB           = 25,    /*!< P25_5DB : Right channel PGA gain = 25.5 dB                                */
64935   PDM0_CORECFG0_PGAR_P27_0DB           = 26,    /*!< P27_0DB : Right channel PGA gain = 27.0 dB                                */
64936   PDM0_CORECFG0_PGAR_P28_5DB           = 27,    /*!< P28_5DB : Right channel PGA gain = 28.5 dB                                */
64937   PDM0_CORECFG0_PGAR_P30_0DB           = 28,    /*!< P30_0DB : Right channel PGA gain = 30.0 DB                                */
64938   PDM0_CORECFG0_PGAR_P31_5DB           = 29,    /*!< P31_5DB : Right channel PGA gain = 31.5 dB                                */
64939   PDM0_CORECFG0_PGAR_P33_0DB           = 30,    /*!< P33_0DB : Right channel PGA gain = 33.0 dB                                */
64940   PDM0_CORECFG0_PGAR_P34_5DB           = 31,    /*!< P34_5DB : Right channel PGA gain = 34.5 dB                                */
64941 } PDM0_CORECFG0_PGAR_Enum;
64942 
64943 /* ==============================================  PDM0 CORECFG0 PGAL [21..25]  ============================================== */
64944 typedef enum {                                  /*!< PDM0_CORECFG0_PGAL                                                        */
64945   PDM0_CORECFG0_PGAL_M10_5DB           = 1,     /*!< M10_5DB : Left channel PGA gain = -10.5 dB                                */
64946   PDM0_CORECFG0_PGAL_M9_0DB            = 2,     /*!< M9_0DB : Left channel PGA gain = -9.0 dB                                  */
64947   PDM0_CORECFG0_PGAL_M7_5DB            = 3,     /*!< M7_5DB : Left channel PGA gain = -7.5 dB                                  */
64948   PDM0_CORECFG0_PGAL_M6_0DB            = 4,     /*!< M6_0DB : Left channel PGA gain = -6.0 dB                                  */
64949   PDM0_CORECFG0_PGAL_M4_5DB            = 5,     /*!< M4_5DB : Left channel PGA gain = -4.5 dB                                  */
64950   PDM0_CORECFG0_PGAL_M3_0DB            = 6,     /*!< M3_0DB : Left channel PGA gain = -3.0 dB                                  */
64951   PDM0_CORECFG0_PGAL_M1_5DB            = 7,     /*!< M1_5DB : Left channel PGA gain = -1.5 dB                                  */
64952   PDM0_CORECFG0_PGAL_0DB               = 8,     /*!< 0DB : Left channel PGA gain = 0 DB                                        */
64953   PDM0_CORECFG0_PGAL_P1_5DB            = 9,     /*!< P1_5DB : Left channel PGA gain = 1.5 dB                                   */
64954   PDM0_CORECFG0_PGAL_P3_0DB            = 10,    /*!< P3_0DB : Left channel PGA gain = 3.0 dB                                   */
64955   PDM0_CORECFG0_PGAL_P4_5DB            = 11,    /*!< P4_5DB : Left channel PGA gain = 4.5 dB                                   */
64956   PDM0_CORECFG0_PGAL_P6_0DB            = 12,    /*!< P6_0DB : Left channel PGA gain = 6.0 DB                                   */
64957   PDM0_CORECFG0_PGAL_P7_5DB            = 13,    /*!< P7_5DB : Left channel PGA gain = 7.5 dB                                   */
64958   PDM0_CORECFG0_PGAL_P9_0DB            = 14,    /*!< P9_0DB : Left channel PGA gain = 9.0 dB                                   */
64959   PDM0_CORECFG0_PGAL_P10_5DB           = 15,    /*!< P10_5DB : Left channel PGA gain = 10.5 dB                                 */
64960   PDM0_CORECFG0_PGAL_P12_0DB           = 16,    /*!< P12_0DB : Left channel PGA gain = 12.0 DB                                 */
64961   PDM0_CORECFG0_PGAL_P13_5DB           = 17,    /*!< P13_5DB : Left channel PGA gain = 13.5 dB                                 */
64962   PDM0_CORECFG0_PGAL_P15_0DB           = 18,    /*!< P15_0DB : Left channel PGA gain = 15.0 dB                                 */
64963   PDM0_CORECFG0_PGAL_P16_5DB           = 19,    /*!< P16_5DB : Left channel PGA gain = 16.5 dB                                 */
64964   PDM0_CORECFG0_PGAL_P18_0DB           = 20,    /*!< P18_0DB : Left channel PGA gain = 18.0 DB                                 */
64965   PDM0_CORECFG0_PGAL_P19_5DB           = 21,    /*!< P19_5DB : Left channel PGA gain = 19.5 dB                                 */
64966   PDM0_CORECFG0_PGAL_P21_0DB           = 22,    /*!< P21_0DB : Left channel PGA gain = 21.0 dB                                 */
64967   PDM0_CORECFG0_PGAL_P22_5DB           = 23,    /*!< P22_5DB : Left channel PGA gain = 22.5 dB                                 */
64968   PDM0_CORECFG0_PGAL_P24_0DB           = 24,    /*!< P24_0DB : Left channel PGA gain = 24.0 DB                                 */
64969   PDM0_CORECFG0_PGAL_P25_5DB           = 25,    /*!< P25_5DB : Left channel PGA gain = 25.5 dB                                 */
64970   PDM0_CORECFG0_PGAL_P27_0DB           = 26,    /*!< P27_0DB : Left channel PGA gain = 27.0 dB                                 */
64971   PDM0_CORECFG0_PGAL_P28_5DB           = 27,    /*!< P28_5DB : Left channel PGA gain = 28.5 dB                                 */
64972   PDM0_CORECFG0_PGAL_P30_0DB           = 28,    /*!< P30_0DB : Left channel PGA gain = 30.0 DB                                 */
64973   PDM0_CORECFG0_PGAL_P31_5DB           = 29,    /*!< P31_5DB : Left channel PGA gain = 31.5 dB                                 */
64974   PDM0_CORECFG0_PGAL_P33_0DB           = 30,    /*!< P33_0DB : Left channel PGA gain = 33.0 dB                                 */
64975   PDM0_CORECFG0_PGAL_P34_5DB           = 31,    /*!< P34_5DB : Left channel PGA gain = 34.5 dB                                 */
64976 } PDM0_CORECFG0_PGAL_Enum;
64977 
64978 /* ==============================================  PDM0 CORECFG0 ADCHPD [9..9]  ============================================== */
64979 typedef enum {                                  /*!< PDM0_CORECFG0_ADCHPD                                                      */
64980   PDM0_CORECFG0_ADCHPD_DIS             = 0,     /*!< DIS : Disable high pass filter.                                           */
64981   PDM0_CORECFG0_ADCHPD_EN              = 1,     /*!< EN : Enable high pass filter.                                             */
64982 } PDM0_CORECFG0_ADCHPD_Enum;
64983 
64984 /* =============================================  PDM0 CORECFG0 SCYCLES [2..4]  ============================================== */
64985 typedef enum {                                  /*!< PDM0_CORECFG0_SCYCLES                                                     */
64986   PDM0_CORECFG0_SCYCLES_0CYCLES        = 0,     /*!< 0CYCLES : Zero PDMA_CK0 clock cycles during gain setting changes
64987                                                      or soft mute.                                                             */
64988   PDM0_CORECFG0_SCYCLES_1CYCLES        = 1,     /*!< 1CYCLES : One PDMA_CK0 clock cycle during gain setting changes
64989                                                      or soft mute.                                                             */
64990   PDM0_CORECFG0_SCYCLES_2CYCLES        = 2,     /*!< 2CYCLES : Two PDMA_CK0 clock cycles during gain setting changes
64991                                                      or soft mute.                                                             */
64992   PDM0_CORECFG0_SCYCLES_3CYCLES        = 3,     /*!< 3CYCLES : Three PDMA_CK0 clock cycles during gain setting changes
64993                                                      or soft mute.                                                             */
64994   PDM0_CORECFG0_SCYCLES_4CYCLES        = 4,     /*!< 4CYCLES : Four PDMA_CK0 clock cycles during gain setting changes
64995                                                      or soft mute.                                                             */
64996   PDM0_CORECFG0_SCYCLES_5CYCLES        = 5,     /*!< 5CYCLES : Five PDMA_CK0 clock cycles during gain setting changes
64997                                                      or soft mute.                                                             */
64998   PDM0_CORECFG0_SCYCLES_6CYCLES        = 6,     /*!< 6CYCLES : Six PDMA_CK0 clock cycles during gain setting changes
64999                                                      or soft mute.                                                             */
65000   PDM0_CORECFG0_SCYCLES_7CYCLES        = 7,     /*!< 7CYCLES : Seven PDMA_CK0 clock cycles during gain setting changes
65001                                                      or soft mute.                                                             */
65002 } PDM0_CORECFG0_SCYCLES_Enum;
65003 
65004 /* ==============================================  PDM0 CORECFG0 LRSWAP [0..0]  ============================================== */
65005 typedef enum {                                  /*!< PDM0_CORECFG0_LRSWAP                                                      */
65006   PDM0_CORECFG0_LRSWAP_DIS             = 0,     /*!< DIS : Disable left/right channel swapping.                                */
65007   PDM0_CORECFG0_LRSWAP_EN              = 1,     /*!< EN : Enable left/right channel swapping.                                  */
65008 } PDM0_CORECFG0_LRSWAP_Enum;
65009 
65010 /* =======================================================  CORECFG1  ======================================================== */
65011 /* =============================================  PDM0 CORECFG1 SELSTEP [7..7]  ============================================== */
65012 typedef enum {                                  /*!< PDM0_CORECFG1_SELSTEP                                                     */
65013   PDM0_CORECFG1_SELSTEP_0_13DB         = 0,     /*!< 0_13DB : 0.13dB fine grain step size.                                     */
65014   PDM0_CORECFG1_SELSTEP_0_26DB         = 1,     /*!< 0_26DB : 0.26dB fine grain step size.                                     */
65015 } PDM0_CORECFG1_SELSTEP_Enum;
65016 
65017 /* ==============================================  PDM0 CORECFG1 CKODLY [4..6]  ============================================== */
65018 typedef enum {                                  /*!< PDM0_CORECFG1_CKODLY                                                      */
65019   PDM0_CORECFG1_CKODLY_0CYCLES         = 0,     /*!< 0CYCLES : No extra PDMCLK cycle delays.                                   */
65020   PDM0_CORECFG1_CKODLY_1CYCLES         = 1,     /*!< 1CYCLES : One xtra PDMCLK cycle delay.                                    */
65021   PDM0_CORECFG1_CKODLY_2CYCLES         = 2,     /*!< 2CYCLES : Two extra PDMCLK cycle delays.                                  */
65022   PDM0_CORECFG1_CKODLY_3CYCLES         = 3,     /*!< 3CYCLES : Three extra PDMCLK cycle delays.                                */
65023   PDM0_CORECFG1_CKODLY_4CYCLES         = 4,     /*!< 4CYCLES : Four extra PDMCLK cycle delays.                                 */
65024   PDM0_CORECFG1_CKODLY_5CYCLES         = 5,     /*!< 5CYCLES : Five extra PDMCLK cycle delays.                                 */
65025   PDM0_CORECFG1_CKODLY_6CYCLES         = 6,     /*!< 6CYCLES : Six extra PDMCLK cycle delays.                                  */
65026   PDM0_CORECFG1_CKODLY_7CYCLES         = 7,     /*!< 7CYCLES : Seven extra PDMCLK cycle delays.                                */
65027 } PDM0_CORECFG1_CKODLY_Enum;
65028 
65029 /* =============================================  PDM0 CORECFG1 PCMCHSET [0..1]  ============================================= */
65030 typedef enum {                                  /*!< PDM0_CORECFG1_PCMCHSET                                                    */
65031   PDM0_CORECFG1_PCMCHSET_CHANDIS       = 0,     /*!< CHANDIS : Channel Disabled                                                */
65032   PDM0_CORECFG1_PCMCHSET_MONOL         = 1,     /*!< MONOL : MONO Left                                                         */
65033   PDM0_CORECFG1_PCMCHSET_MONOR         = 2,     /*!< MONOR : MONO right                                                        */
65034   PDM0_CORECFG1_PCMCHSET_STEREO        = 3,     /*!< STEREO : Stereo                                                           */
65035 } PDM0_CORECFG1_PCMCHSET_Enum;
65036 
65037 /* =======================================================  CORECTRL  ======================================================== */
65038 /* ========================================================  FIFOCNT  ======================================================== */
65039 /* =======================================================  FIFOREAD  ======================================================== */
65040 /* =======================================================  FIFOFLUSH  ======================================================= */
65041 /* ========================================================  FIFOTHR  ======================================================== */
65042 /* =========================================================  INTEN  ========================================================= */
65043 /* ========================================================  INTSTAT  ======================================================== */
65044 /* ========================================================  INTCLR  ========================================================= */
65045 /* ========================================================  INTSET  ========================================================= */
65046 /* =======================================================  DMATRIGEN  ======================================================= */
65047 /* ======================================================  DMATRIGSTAT  ====================================================== */
65048 /* ========================================================  DMACFG  ========================================================= */
65049 /* ===============================================  PDM0 DMACFG DMAPRI [8..8]  =============================================== */
65050 typedef enum {                                  /*!< PDM0_DMACFG_DMAPRI                                                        */
65051   PDM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
65052   PDM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
65053 } PDM0_DMACFG_DMAPRI_Enum;
65054 
65055 /* ===============================================  PDM0 DMACFG DMADIR [2..2]  =============================================== */
65056 typedef enum {                                  /*!< PDM0_DMACFG_DMADIR                                                        */
65057   PDM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module
65058                                                      will only DMA to memory.                                                  */
65059   PDM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. Not available for PDM
65060                                                      module                                                                    */
65061 } PDM0_DMACFG_DMADIR_Enum;
65062 
65063 /* ===============================================  PDM0 DMACFG DMAEN [0..0]  ================================================ */
65064 typedef enum {                                  /*!< PDM0_DMACFG_DMAEN                                                         */
65065   PDM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
65066   PDM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
65067 } PDM0_DMACFG_DMAEN_Enum;
65068 
65069 /* ======================================================  DMATARGADDR  ====================================================== */
65070 /* ========================================================  DMASTAT  ======================================================== */
65071 /* ======================================================  DMATOTCOUNT  ====================================================== */
65072 
65073 
65074 /* =========================================================================================================================== */
65075 /* ================                                          PWRCTRL                                          ================ */
65076 /* =========================================================================================================================== */
65077 
65078 /* ======================================================  MCUPERFREQ  ======================================================= */
65079 /* ========================================  PWRCTRL MCUPERFREQ MCUPERFSTATUS [3..4]  ======================================== */
65080 typedef enum {                                  /*!< PWRCTRL_MCUPERFREQ_MCUPERFSTATUS                                          */
65081   PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_ULP = 0,     /*!< ULP : MCU is in ULP mode (freq=24MHz)                                     */
65082   PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_LP  = 1,     /*!< LP : MCU is in LP mode (freq=96MHz)                                       */
65083   PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_HP  = 2,     /*!< HP : MCU is in HP mode (freq=192MHz)                                      */
65084 } PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Enum;
65085 
65086 /* =========================================  PWRCTRL MCUPERFREQ MCUPERFREQ [0..1]  ========================================== */
65087 typedef enum {                                  /*!< PWRCTRL_MCUPERFREQ_MCUPERFREQ                                             */
65088   PWRCTRL_MCUPERFREQ_MCUPERFREQ_ULP    = 0,     /*!< ULP : MCU to be run in ULP mode (freq=24MHz)                              */
65089   PWRCTRL_MCUPERFREQ_MCUPERFREQ_LP     = 1,     /*!< LP : MCU to be run in LP mode (freq=96MHz)                                */
65090   PWRCTRL_MCUPERFREQ_MCUPERFREQ_HP     = 2,     /*!< HP : MCU to be run in HP mode (freq=192MHz)                               */
65091 } PWRCTRL_MCUPERFREQ_MCUPERFREQ_Enum;
65092 
65093 /* =======================================================  DEVPWREN  ======================================================== */
65094 /* ==========================================  PWRCTRL DEVPWREN PWRENDBG [24..24]  =========================================== */
65095 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENDBG                                                 */
65096   PWRCTRL_DEVPWREN_PWRENDBG_EN         = 1,     /*!< EN : Enable                                                               */
65097   PWRCTRL_DEVPWREN_PWRENDBG_DIS        = 0,     /*!< DIS : Disable                                                             */
65098 } PWRCTRL_DEVPWREN_PWRENDBG_Enum;
65099 
65100 /* =========================================  PWRCTRL DEVPWREN PWRENUSBPHY [23..23]  ========================================= */
65101 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUSBPHY                                              */
65102   PWRCTRL_DEVPWREN_PWRENUSBPHY_EN      = 1,     /*!< EN : Power up USB PHY                                                     */
65103   PWRCTRL_DEVPWREN_PWRENUSBPHY_DIS     = 0,     /*!< DIS : Power down USB PHY                                                  */
65104 } PWRCTRL_DEVPWREN_PWRENUSBPHY_Enum;
65105 
65106 /* ==========================================  PWRCTRL DEVPWREN PWRENUSB [22..22]  =========================================== */
65107 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUSB                                                 */
65108   PWRCTRL_DEVPWREN_PWRENUSB_EN         = 1,     /*!< EN : Power up USB                                                         */
65109   PWRCTRL_DEVPWREN_PWRENUSB_DIS        = 0,     /*!< DIS : Power down USB                                                      */
65110 } PWRCTRL_DEVPWREN_PWRENUSB_Enum;
65111 
65112 /* ==========================================  PWRCTRL DEVPWREN PWRENSDIO [21..21]  ========================================== */
65113 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENSDIO                                                */
65114   PWRCTRL_DEVPWREN_PWRENSDIO_EN        = 1,     /*!< EN : Power up SDIO                                                        */
65115   PWRCTRL_DEVPWREN_PWRENSDIO_DIS       = 0,     /*!< DIS : Power down SDIO                                                     */
65116 } PWRCTRL_DEVPWREN_PWRENSDIO_Enum;
65117 
65118 /* =========================================  PWRCTRL DEVPWREN PWRENCRYPTO [20..20]  ========================================= */
65119 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENCRYPTO                                              */
65120   PWRCTRL_DEVPWREN_PWRENCRYPTO_EN      = 1,     /*!< EN : Power up CRYPTO                                                      */
65121   PWRCTRL_DEVPWREN_PWRENCRYPTO_DIS     = 0,     /*!< DIS : Power down CRYPTO                                                   */
65122 } PWRCTRL_DEVPWREN_PWRENCRYPTO_Enum;
65123 
65124 /* ========================================  PWRCTRL DEVPWREN PWRENDISPPHY [19..19]  ========================================= */
65125 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENDISPPHY                                             */
65126   PWRCTRL_DEVPWREN_PWRENDISPPHY_EN     = 1,     /*!< EN : Power up DISP PHY                                                    */
65127   PWRCTRL_DEVPWREN_PWRENDISPPHY_DIS    = 0,     /*!< DIS : Power down DISP PHY                                                 */
65128 } PWRCTRL_DEVPWREN_PWRENDISPPHY_Enum;
65129 
65130 /* ==========================================  PWRCTRL DEVPWREN PWRENDISP [18..18]  ========================================== */
65131 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENDISP                                                */
65132   PWRCTRL_DEVPWREN_PWRENDISP_EN        = 1,     /*!< EN : Power up DISP                                                        */
65133   PWRCTRL_DEVPWREN_PWRENDISP_DIS       = 0,     /*!< DIS : Power down DISP                                                     */
65134 } PWRCTRL_DEVPWREN_PWRENDISP_Enum;
65135 
65136 /* ==========================================  PWRCTRL DEVPWREN PWRENGFX [17..17]  =========================================== */
65137 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENGFX                                                 */
65138   PWRCTRL_DEVPWREN_PWRENGFX_EN         = 1,     /*!< EN : Power up GFX                                                         */
65139   PWRCTRL_DEVPWREN_PWRENGFX_DIS        = 0,     /*!< DIS : Power down GFX                                                      */
65140 } PWRCTRL_DEVPWREN_PWRENGFX_Enum;
65141 
65142 /* =========================================  PWRCTRL DEVPWREN PWRENMSPI2 [16..16]  ========================================== */
65143 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI2                                               */
65144   PWRCTRL_DEVPWREN_PWRENMSPI2_EN       = 1,     /*!< EN : Power up MSPI2                                                       */
65145   PWRCTRL_DEVPWREN_PWRENMSPI2_DIS      = 0,     /*!< DIS : Power down MSPI2                                                    */
65146 } PWRCTRL_DEVPWREN_PWRENMSPI2_Enum;
65147 
65148 /* =========================================  PWRCTRL DEVPWREN PWRENMSPI1 [15..15]  ========================================== */
65149 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI1                                               */
65150   PWRCTRL_DEVPWREN_PWRENMSPI1_EN       = 1,     /*!< EN : Power up MSPI1                                                       */
65151   PWRCTRL_DEVPWREN_PWRENMSPI1_DIS      = 0,     /*!< DIS : Power down MSPI1                                                    */
65152 } PWRCTRL_DEVPWREN_PWRENMSPI1_Enum;
65153 
65154 /* =========================================  PWRCTRL DEVPWREN PWRENMSPI0 [14..14]  ========================================== */
65155 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI0                                               */
65156   PWRCTRL_DEVPWREN_PWRENMSPI0_EN       = 1,     /*!< EN : Power up MSPI0                                                       */
65157   PWRCTRL_DEVPWREN_PWRENMSPI0_DIS      = 0,     /*!< DIS : Power down MSPI0                                                    */
65158 } PWRCTRL_DEVPWREN_PWRENMSPI0_Enum;
65159 
65160 /* ==========================================  PWRCTRL DEVPWREN PWRENADC [13..13]  =========================================== */
65161 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENADC                                                 */
65162   PWRCTRL_DEVPWREN_PWRENADC_EN         = 1,     /*!< EN : Power up ADC                                                         */
65163   PWRCTRL_DEVPWREN_PWRENADC_DIS        = 0,     /*!< DIS : Power Down ADC                                                      */
65164 } PWRCTRL_DEVPWREN_PWRENADC_Enum;
65165 
65166 /* =========================================  PWRCTRL DEVPWREN PWRENUART3 [12..12]  ========================================== */
65167 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART3                                               */
65168   PWRCTRL_DEVPWREN_PWRENUART3_EN       = 1,     /*!< EN : Power up UART 3                                                      */
65169   PWRCTRL_DEVPWREN_PWRENUART3_DIS      = 0,     /*!< DIS : Power down UART 3                                                   */
65170 } PWRCTRL_DEVPWREN_PWRENUART3_Enum;
65171 
65172 /* =========================================  PWRCTRL DEVPWREN PWRENUART2 [11..11]  ========================================== */
65173 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART2                                               */
65174   PWRCTRL_DEVPWREN_PWRENUART2_EN       = 1,     /*!< EN : Power up UART 2                                                      */
65175   PWRCTRL_DEVPWREN_PWRENUART2_DIS      = 0,     /*!< DIS : Power down UART 2                                                   */
65176 } PWRCTRL_DEVPWREN_PWRENUART2_Enum;
65177 
65178 /* =========================================  PWRCTRL DEVPWREN PWRENUART1 [10..10]  ========================================== */
65179 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART1                                               */
65180   PWRCTRL_DEVPWREN_PWRENUART1_EN       = 1,     /*!< EN : Power up UART 1                                                      */
65181   PWRCTRL_DEVPWREN_PWRENUART1_DIS      = 0,     /*!< DIS : Power down UART 1                                                   */
65182 } PWRCTRL_DEVPWREN_PWRENUART1_Enum;
65183 
65184 /* ==========================================  PWRCTRL DEVPWREN PWRENUART0 [9..9]  =========================================== */
65185 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART0                                               */
65186   PWRCTRL_DEVPWREN_PWRENUART0_EN       = 1,     /*!< EN : Power up UART 0                                                      */
65187   PWRCTRL_DEVPWREN_PWRENUART0_DIS      = 0,     /*!< DIS : Power down UART 0                                                   */
65188 } PWRCTRL_DEVPWREN_PWRENUART0_Enum;
65189 
65190 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM7 [8..8]  =========================================== */
65191 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM7                                                */
65192   PWRCTRL_DEVPWREN_PWRENIOM7_EN        = 1,     /*!< EN : Power up IO Master 7                                                 */
65193   PWRCTRL_DEVPWREN_PWRENIOM7_DIS       = 0,     /*!< DIS : Power down IO Master 7                                              */
65194 } PWRCTRL_DEVPWREN_PWRENIOM7_Enum;
65195 
65196 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM6 [7..7]  =========================================== */
65197 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM6                                                */
65198   PWRCTRL_DEVPWREN_PWRENIOM6_EN        = 1,     /*!< EN : Power up IO Master 6                                                 */
65199   PWRCTRL_DEVPWREN_PWRENIOM6_DIS       = 0,     /*!< DIS : Power down IO Master 6                                              */
65200 } PWRCTRL_DEVPWREN_PWRENIOM6_Enum;
65201 
65202 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM5 [6..6]  =========================================== */
65203 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM5                                                */
65204   PWRCTRL_DEVPWREN_PWRENIOM5_EN        = 1,     /*!< EN : Power up IO Master 5                                                 */
65205   PWRCTRL_DEVPWREN_PWRENIOM5_DIS       = 0,     /*!< DIS : Power down IO Master 5                                              */
65206 } PWRCTRL_DEVPWREN_PWRENIOM5_Enum;
65207 
65208 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM4 [5..5]  =========================================== */
65209 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM4                                                */
65210   PWRCTRL_DEVPWREN_PWRENIOM4_EN        = 1,     /*!< EN : Power up IO Master 4                                                 */
65211   PWRCTRL_DEVPWREN_PWRENIOM4_DIS       = 0,     /*!< DIS : Power down IO Master 4                                              */
65212 } PWRCTRL_DEVPWREN_PWRENIOM4_Enum;
65213 
65214 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM3 [4..4]  =========================================== */
65215 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM3                                                */
65216   PWRCTRL_DEVPWREN_PWRENIOM3_EN        = 1,     /*!< EN : Power up IO Master 3                                                 */
65217   PWRCTRL_DEVPWREN_PWRENIOM3_DIS       = 0,     /*!< DIS : Power down IO Master 3                                              */
65218 } PWRCTRL_DEVPWREN_PWRENIOM3_Enum;
65219 
65220 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM2 [3..3]  =========================================== */
65221 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM2                                                */
65222   PWRCTRL_DEVPWREN_PWRENIOM2_EN        = 1,     /*!< EN : Power up IO Master 2                                                 */
65223   PWRCTRL_DEVPWREN_PWRENIOM2_DIS       = 0,     /*!< DIS : Power down IO Master 2                                              */
65224 } PWRCTRL_DEVPWREN_PWRENIOM2_Enum;
65225 
65226 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM1 [2..2]  =========================================== */
65227 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM1                                                */
65228   PWRCTRL_DEVPWREN_PWRENIOM1_EN        = 1,     /*!< EN : Power up IO Master 1                                                 */
65229   PWRCTRL_DEVPWREN_PWRENIOM1_DIS       = 0,     /*!< DIS : Power down IO Master 1                                              */
65230 } PWRCTRL_DEVPWREN_PWRENIOM1_Enum;
65231 
65232 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM0 [1..1]  =========================================== */
65233 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM0                                                */
65234   PWRCTRL_DEVPWREN_PWRENIOM0_EN        = 1,     /*!< EN : Power up IO Master 0                                                 */
65235   PWRCTRL_DEVPWREN_PWRENIOM0_DIS       = 0,     /*!< DIS : Power down IO Master 0                                              */
65236 } PWRCTRL_DEVPWREN_PWRENIOM0_Enum;
65237 
65238 /* ===========================================  PWRCTRL DEVPWREN PWRENIOS [0..0]  ============================================ */
65239 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOS                                                 */
65240   PWRCTRL_DEVPWREN_PWRENIOS_EN         = 1,     /*!< EN : Power up IO slave                                                    */
65241   PWRCTRL_DEVPWREN_PWRENIOS_DIS        = 0,     /*!< DIS : Power down IO slave                                                 */
65242 } PWRCTRL_DEVPWREN_PWRENIOS_Enum;
65243 
65244 /* =====================================================  DEVPWRSTATUS  ====================================================== */
65245 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTDBG [24..24]  ========================================= */
65246 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTDBG                                             */
65247   PWRCTRL_DEVPWRSTATUS_PWRSTDBG_ON     = 1,     /*!< ON : Domain powered on                                                    */
65248   PWRCTRL_DEVPWRSTATUS_PWRSTDBG_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
65249 } PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Enum;
65250 
65251 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUSBPHY [23..23]  ======================================= */
65252 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY                                          */
65253   PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_ON  = 1,     /*!< ON : Domain powered on                                                    */
65254   PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65255 } PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_Enum;
65256 
65257 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTUSB [22..22]  ========================================= */
65258 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUSB                                             */
65259   PWRCTRL_DEVPWRSTATUS_PWRSTUSB_ON     = 1,     /*!< ON : Domain powered on                                                    */
65260   PWRCTRL_DEVPWRSTATUS_PWRSTUSB_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
65261 } PWRCTRL_DEVPWRSTATUS_PWRSTUSB_Enum;
65262 
65263 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTSDIO [21..21]  ======================================== */
65264 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTSDIO                                            */
65265   PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_ON    = 1,     /*!< ON : Domain powered on                                                    */
65266   PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65267 } PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Enum;
65268 
65269 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTCRYPTO [20..20]  ======================================= */
65270 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO                                          */
65271   PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_ON  = 1,     /*!< ON : Domain powered on                                                    */
65272   PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65273 } PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Enum;
65274 
65275 /* ======================================  PWRCTRL DEVPWRSTATUS PWRSTDISPPHY [19..19]  ======================================= */
65276 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY                                         */
65277   PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_ON = 1,     /*!< ON : Domain powered on                                                    */
65278   PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_OFF = 0,    /*!< OFF : Domain powered off                                                  */
65279 } PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_Enum;
65280 
65281 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTDISP [18..18]  ======================================== */
65282 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTDISP                                            */
65283   PWRCTRL_DEVPWRSTATUS_PWRSTDISP_ON    = 1,     /*!< ON : Domain powered on                                                    */
65284   PWRCTRL_DEVPWRSTATUS_PWRSTDISP_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65285 } PWRCTRL_DEVPWRSTATUS_PWRSTDISP_Enum;
65286 
65287 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTGFX [17..17]  ========================================= */
65288 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTGFX                                             */
65289   PWRCTRL_DEVPWRSTATUS_PWRSTGFX_ON     = 1,     /*!< ON : Domain powered on                                                    */
65290   PWRCTRL_DEVPWRSTATUS_PWRSTGFX_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
65291 } PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Enum;
65292 
65293 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI2 [16..16]  ======================================== */
65294 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2                                           */
65295   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_ON   = 1,     /*!< ON : Domain powered on                                                    */
65296   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
65297 } PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Enum;
65298 
65299 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI1 [15..15]  ======================================== */
65300 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1                                           */
65301   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_ON   = 1,     /*!< ON : Domain powered on                                                    */
65302   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
65303 } PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Enum;
65304 
65305 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI0 [14..14]  ======================================== */
65306 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0                                           */
65307   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_ON   = 1,     /*!< ON : Domain powered on                                                    */
65308   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
65309 } PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Enum;
65310 
65311 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTADC [13..13]  ========================================= */
65312 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTADC                                             */
65313   PWRCTRL_DEVPWRSTATUS_PWRSTADC_ON     = 1,     /*!< ON : Domain powered on                                                    */
65314   PWRCTRL_DEVPWRSTATUS_PWRSTADC_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
65315 } PWRCTRL_DEVPWRSTATUS_PWRSTADC_Enum;
65316 
65317 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART3 [12..12]  ======================================== */
65318 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART3                                           */
65319   PWRCTRL_DEVPWRSTATUS_PWRSTUART3_ON   = 1,     /*!< ON : Domain powered on                                                    */
65320   PWRCTRL_DEVPWRSTATUS_PWRSTUART3_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
65321 } PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Enum;
65322 
65323 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART2 [11..11]  ======================================== */
65324 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART2                                           */
65325   PWRCTRL_DEVPWRSTATUS_PWRSTUART2_ON   = 1,     /*!< ON : Domain powered on                                                    */
65326   PWRCTRL_DEVPWRSTATUS_PWRSTUART2_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
65327 } PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Enum;
65328 
65329 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART1 [10..10]  ======================================== */
65330 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART1                                           */
65331   PWRCTRL_DEVPWRSTATUS_PWRSTUART1_ON   = 1,     /*!< ON : Domain powered on                                                    */
65332   PWRCTRL_DEVPWRSTATUS_PWRSTUART1_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
65333 } PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Enum;
65334 
65335 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTUART0 [9..9]  ========================================= */
65336 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART0                                           */
65337   PWRCTRL_DEVPWRSTATUS_PWRSTUART0_ON   = 1,     /*!< ON : Domain powered on                                                    */
65338   PWRCTRL_DEVPWRSTATUS_PWRSTUART0_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
65339 } PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Enum;
65340 
65341 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM7 [8..8]  ========================================= */
65342 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM7                                            */
65343   PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_ON    = 1,     /*!< ON : Domain powered on                                                    */
65344   PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65345 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Enum;
65346 
65347 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM6 [7..7]  ========================================= */
65348 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM6                                            */
65349   PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_ON    = 1,     /*!< ON : Domain powered on                                                    */
65350   PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65351 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Enum;
65352 
65353 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM5 [6..6]  ========================================= */
65354 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM5                                            */
65355   PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_ON    = 1,     /*!< ON : Domain powered on                                                    */
65356   PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65357 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Enum;
65358 
65359 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM4 [5..5]  ========================================= */
65360 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM4                                            */
65361   PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_ON    = 1,     /*!< ON : Domain powered on                                                    */
65362   PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65363 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Enum;
65364 
65365 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM3 [4..4]  ========================================= */
65366 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM3                                            */
65367   PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_ON    = 1,     /*!< ON : Domain powered on                                                    */
65368   PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65369 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Enum;
65370 
65371 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM2 [3..3]  ========================================= */
65372 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM2                                            */
65373   PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_ON    = 1,     /*!< ON : Domain powered on                                                    */
65374   PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65375 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Enum;
65376 
65377 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM1 [2..2]  ========================================= */
65378 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM1                                            */
65379   PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_ON    = 1,     /*!< ON : Domain powered on                                                    */
65380   PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65381 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Enum;
65382 
65383 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM0 [1..1]  ========================================= */
65384 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM0                                            */
65385   PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_ON    = 1,     /*!< ON : Domain powered on                                                    */
65386   PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
65387 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Enum;
65388 
65389 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOS [0..0]  ========================================== */
65390 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOS                                             */
65391   PWRCTRL_DEVPWRSTATUS_PWRSTIOS_ON     = 1,     /*!< ON : Domain powered on                                                    */
65392   PWRCTRL_DEVPWRSTATUS_PWRSTIOS_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
65393 } PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Enum;
65394 
65395 /* ======================================================  AUDSSPWREN  ======================================================= */
65396 /* =========================================  PWRCTRL AUDSSPWREN PWRENDSPA [11..11]  ========================================= */
65397 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENDSPA                                              */
65398   PWRCTRL_AUDSSPWREN_PWRENDSPA_EN      = 1,     /*!< EN : Enable                                                               */
65399   PWRCTRL_AUDSSPWREN_PWRENDSPA_DIS     = 0,     /*!< DIS : Disable                                                             */
65400 } PWRCTRL_AUDSSPWREN_PWRENDSPA_Enum;
65401 
65402 /* ========================================  PWRCTRL AUDSSPWREN PWRENAUDADC [10..10]  ======================================== */
65403 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDADC                                            */
65404   PWRCTRL_AUDSSPWREN_PWRENAUDADC_EN    = 1,     /*!< EN : Power up AUDADC                                                      */
65405   PWRCTRL_AUDSSPWREN_PWRENAUDADC_DIS   = 0,     /*!< DIS : Power down AUDADC                                                   */
65406 } PWRCTRL_AUDSSPWREN_PWRENAUDADC_Enum;
65407 
65408 /* ==========================================  PWRCTRL AUDSSPWREN PWRENI2S1 [7..7]  ========================================== */
65409 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENI2S1                                              */
65410   PWRCTRL_AUDSSPWREN_PWRENI2S1_EN      = 1,     /*!< EN : Power up I2S1                                                        */
65411   PWRCTRL_AUDSSPWREN_PWRENI2S1_DIS     = 0,     /*!< DIS : Power down I2S1                                                     */
65412 } PWRCTRL_AUDSSPWREN_PWRENI2S1_Enum;
65413 
65414 /* ==========================================  PWRCTRL AUDSSPWREN PWRENI2S0 [6..6]  ========================================== */
65415 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENI2S0                                              */
65416   PWRCTRL_AUDSSPWREN_PWRENI2S0_EN      = 1,     /*!< EN : Power up I2S0                                                        */
65417   PWRCTRL_AUDSSPWREN_PWRENI2S0_DIS     = 0,     /*!< DIS : Power down I2S0                                                     */
65418 } PWRCTRL_AUDSSPWREN_PWRENI2S0_Enum;
65419 
65420 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM3 [5..5]  ========================================== */
65421 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM3                                              */
65422   PWRCTRL_AUDSSPWREN_PWRENPDM3_EN      = 1,     /*!< EN : Power up PDM3                                                        */
65423   PWRCTRL_AUDSSPWREN_PWRENPDM3_DIS     = 0,     /*!< DIS : Power down PDM3                                                     */
65424 } PWRCTRL_AUDSSPWREN_PWRENPDM3_Enum;
65425 
65426 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM2 [4..4]  ========================================== */
65427 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM2                                              */
65428   PWRCTRL_AUDSSPWREN_PWRENPDM2_EN      = 1,     /*!< EN : Power up PDM2                                                        */
65429   PWRCTRL_AUDSSPWREN_PWRENPDM2_DIS     = 0,     /*!< DIS : Power down PDM2                                                     */
65430 } PWRCTRL_AUDSSPWREN_PWRENPDM2_Enum;
65431 
65432 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM1 [3..3]  ========================================== */
65433 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM1                                              */
65434   PWRCTRL_AUDSSPWREN_PWRENPDM1_EN      = 1,     /*!< EN : Power up PDM1                                                        */
65435   PWRCTRL_AUDSSPWREN_PWRENPDM1_DIS     = 0,     /*!< DIS : Power down PDM1                                                     */
65436 } PWRCTRL_AUDSSPWREN_PWRENPDM1_Enum;
65437 
65438 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM0 [2..2]  ========================================== */
65439 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM0                                              */
65440   PWRCTRL_AUDSSPWREN_PWRENPDM0_EN      = 1,     /*!< EN : Power up PDM0                                                        */
65441   PWRCTRL_AUDSSPWREN_PWRENPDM0_DIS     = 0,     /*!< DIS : Power down PDM0                                                     */
65442 } PWRCTRL_AUDSSPWREN_PWRENPDM0_Enum;
65443 
65444 /* =========================================  PWRCTRL AUDSSPWREN PWRENAUDPB [1..1]  ========================================== */
65445 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDPB                                             */
65446   PWRCTRL_AUDSSPWREN_PWRENAUDPB_EN     = 1,     /*!< EN : Power up AUDPB                                                       */
65447   PWRCTRL_AUDSSPWREN_PWRENAUDPB_DIS    = 0,     /*!< DIS : Power down AUDPB                                                    */
65448 } PWRCTRL_AUDSSPWREN_PWRENAUDPB_Enum;
65449 
65450 /* =========================================  PWRCTRL AUDSSPWREN PWRENAUDREC [0..0]  ========================================= */
65451 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDREC                                            */
65452   PWRCTRL_AUDSSPWREN_PWRENAUDREC_EN    = 1,     /*!< EN : Power up AUDREC                                                      */
65453   PWRCTRL_AUDSSPWREN_PWRENAUDREC_DIS   = 0,     /*!< DIS : Power down AUDREC                                                   */
65454 } PWRCTRL_AUDSSPWREN_PWRENAUDREC_Enum;
65455 
65456 /* ====================================================  AUDSSPWRSTATUS  ===================================================== */
65457 /* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTDSPA [11..11]  ======================================= */
65458 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA                                          */
65459   PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_ON  = 1,     /*!< ON : Domain powered on                                                    */
65460   PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65461 } PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_Enum;
65462 
65463 /* ======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDADC [10..10]  ====================================== */
65464 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC                                        */
65465   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_ON = 1,    /*!< ON : Domain powered on                                                    */
65466   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_OFF = 0,   /*!< OFF : Domain powered off                                                  */
65467 } PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_Enum;
65468 
65469 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTI2S1 [7..7]  ======================================== */
65470 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1                                          */
65471   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_ON  = 1,     /*!< ON : Domain powered on                                                    */
65472   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65473 } PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Enum;
65474 
65475 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTI2S0 [6..6]  ======================================== */
65476 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0                                          */
65477   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_ON  = 1,     /*!< ON : Domain powered on                                                    */
65478   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65479 } PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Enum;
65480 
65481 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM3 [5..5]  ======================================== */
65482 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3                                          */
65483   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_ON  = 1,     /*!< ON : Domain powered on                                                    */
65484   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65485 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_Enum;
65486 
65487 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM2 [4..4]  ======================================== */
65488 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2                                          */
65489   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_ON  = 1,     /*!< ON : Domain powered on                                                    */
65490   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65491 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_Enum;
65492 
65493 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM1 [3..3]  ======================================== */
65494 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1                                          */
65495   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_ON  = 1,     /*!< ON : Domain powered on                                                    */
65496   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65497 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_Enum;
65498 
65499 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM0 [2..2]  ======================================== */
65500 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0                                          */
65501   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_ON  = 1,     /*!< ON : Domain powered on                                                    */
65502   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_OFF = 0,     /*!< OFF : Domain powered off                                                  */
65503 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Enum;
65504 
65505 /* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDPB [1..1]  ======================================== */
65506 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB                                         */
65507   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_ON = 1,     /*!< ON : Domain powered on                                                    */
65508   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_OFF = 0,    /*!< OFF : Domain powered off                                                  */
65509 } PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Enum;
65510 
65511 /* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDREC [0..0]  ======================================= */
65512 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC                                        */
65513   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_ON = 1,    /*!< ON : Domain powered on                                                    */
65514   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_OFF = 0,   /*!< OFF : Domain powered off                                                  */
65515 } PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Enum;
65516 
65517 /* =======================================================  MEMPWREN  ======================================================== */
65518 /* =========================================  PWRCTRL MEMPWREN PWRENCACHEB2 [5..5]  ========================================== */
65519 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENCACHEB2                                             */
65520   PWRCTRL_MEMPWREN_PWRENCACHEB2_EN     = 1,     /*!< EN : Power up Cache Bank 2                                                */
65521   PWRCTRL_MEMPWREN_PWRENCACHEB2_DIS    = 0,     /*!< DIS : Power down Cache Bank 2                                             */
65522 } PWRCTRL_MEMPWREN_PWRENCACHEB2_Enum;
65523 
65524 /* =========================================  PWRCTRL MEMPWREN PWRENCACHEB0 [4..4]  ========================================== */
65525 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENCACHEB0                                             */
65526   PWRCTRL_MEMPWREN_PWRENCACHEB0_EN     = 1,     /*!< EN : Power up Cache Bank 0                                                */
65527   PWRCTRL_MEMPWREN_PWRENCACHEB0_DIS    = 0,     /*!< DIS : Power down Cache Bank 0                                             */
65528 } PWRCTRL_MEMPWREN_PWRENCACHEB0_Enum;
65529 
65530 /* ===========================================  PWRCTRL MEMPWREN PWRENNVM0 [3..3]  =========================================== */
65531 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENNVM0                                                */
65532   PWRCTRL_MEMPWREN_PWRENNVM0_EN        = 1,     /*!< EN : Power up NVM0                                                        */
65533   PWRCTRL_MEMPWREN_PWRENNVM0_DIS       = 0,     /*!< DIS : Power down NVM0                                                     */
65534 } PWRCTRL_MEMPWREN_PWRENNVM0_Enum;
65535 
65536 /* ===========================================  PWRCTRL MEMPWREN PWRENDTCM [0..2]  =========================================== */
65537 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENDTCM                                                */
65538   PWRCTRL_MEMPWREN_PWRENDTCM_NONE      = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
65539   PWRCTRL_MEMPWREN_PWRENDTCM_TCM8K     = 1,     /*!< TCM8K : Power ON only lower 8k                                            */
65540   PWRCTRL_MEMPWREN_PWRENDTCM_TCM128K   = 3,     /*!< TCM128K : Power ON only lower 128k                                        */
65541   PWRCTRL_MEMPWREN_PWRENDTCM_TCM384K   = 7,     /*!< TCM384K : Power ON 384k                                                   */
65542 } PWRCTRL_MEMPWREN_PWRENDTCM_Enum;
65543 
65544 /* =====================================================  MEMPWRSTATUS  ====================================================== */
65545 /* =========================================  PWRCTRL MEMPWRSTATUS PWRSTDTCM [0..2]  ========================================= */
65546 typedef enum {                                  /*!< PWRCTRL_MEMPWRSTATUS_PWRSTDTCM                                            */
65547   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_NONE  = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
65548   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM8K = 1,     /*!< TCM8K : Only lower 8k is powered up                                       */
65549   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM128K = 3,   /*!< TCM128K : Only lower 128k is powered up                                   */
65550   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM384K = 7,   /*!< TCM384K : All 384k is powered up                                          */
65551 } PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Enum;
65552 
65553 /* =======================================================  MEMRETCFG  ======================================================= */
65554 /* =========================================  PWRCTRL MEMRETCFG CACHEPWDSLP [4..4]  ========================================== */
65555 typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_CACHEPWDSLP                                             */
65556   PWRCTRL_MEMRETCFG_CACHEPWDSLP_EN     = 1,     /*!< EN : Power down cache in deep sleep                                       */
65557   PWRCTRL_MEMRETCFG_CACHEPWDSLP_DIS    = 0,     /*!< DIS : Retain cache in deep sleep                                          */
65558 } PWRCTRL_MEMRETCFG_CACHEPWDSLP_Enum;
65559 
65560 /* ==========================================  PWRCTRL MEMRETCFG NVM0PWDSLP [3..3]  ========================================== */
65561 typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_NVM0PWDSLP                                              */
65562   PWRCTRL_MEMRETCFG_NVM0PWDSLP_EN      = 1,     /*!< EN : NVM0 is powered down during deepsleep                                */
65563   PWRCTRL_MEMRETCFG_NVM0PWDSLP_DIS     = 0,     /*!< DIS : NVM0 is kept powered on during deepsleep                            */
65564 } PWRCTRL_MEMRETCFG_NVM0PWDSLP_Enum;
65565 
65566 /* ==========================================  PWRCTRL MEMRETCFG DTCMPWDSLP [0..2]  ========================================== */
65567 typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_DTCMPWDSLP                                              */
65568   PWRCTRL_MEMRETCFG_DTCMPWDSLP_NONE    = 0,     /*!< NONE : All DTCM retained                                                  */
65569   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM0 = 1, /*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB)           */
65570   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM1 = 2, /*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-128KB)         */
65571   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0  = 3,     /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep
65572                                                      (0KB-128KB)                                                               */
65573   PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down
65574                                                      in deep sleep (8KB-384KB)                                                 */
65575   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP1  = 4,     /*!< GROUP1 : Group1 DTCM powered down in deep sleep (128KB-384KB)             */
65576   PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALL     = 7,     /*!< ALL : All DTCMs powered down in deep sleep (0KB-384KB)                    */
65577 } PWRCTRL_MEMRETCFG_DTCMPWDSLP_Enum;
65578 
65579 /* =====================================================  SYSPWRSTATUS  ====================================================== */
65580 /* ======================================================  SSRAMPWREN  ======================================================= */
65581 /* =========================================  PWRCTRL SSRAMPWREN PWRENSSRAM [0..1]  ========================================== */
65582 typedef enum {                                  /*!< PWRCTRL_SSRAMPWREN_PWRENSSRAM                                             */
65583   PWRCTRL_SSRAMPWREN_PWRENSSRAM_NONE   = 0,     /*!< NONE : Do not power ON any of the SRAM banks                              */
65584   PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP0 = 1,     /*!< GROUP0 : Power ON only SRAM group0 (512k)                                 */
65585   PWRCTRL_SSRAMPWREN_PWRENSSRAM_ALL    = 3,     /*!< ALL : All shared SRAM banks (1M) powered ON                               */
65586 } PWRCTRL_SSRAMPWREN_PWRENSSRAM_Enum;
65587 
65588 /* ======================================================  SSRAMPWRST  ======================================================= */
65589 /* ======================================================  SSRAMRETCFG  ====================================================== */
65590 /* ========================================  PWRCTRL SSRAMRETCFG SSRAMPWDSLP [0..1]  ========================================= */
65591 typedef enum {                                  /*!< PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP                                           */
65592   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_NONE = 0,     /*!< NONE : All banks retained                                                 */
65593   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP0 = 1,   /*!< GROUP0 : Power down only SRAM group0                                      */
65594   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP1 = 2,   /*!< GROUP1 : Power down only SRAM group1                                      */
65595   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_ALL  = 3,     /*!< ALL : All shared SRAM banks powered down                                  */
65596 } PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Enum;
65597 
65598 /* =====================================================  DEVPWREVENTEN  ===================================================== */
65599 /* =========================================  PWRCTRL DEVPWREVENTEN AUDEVEN [7..7]  ========================================== */
65600 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_AUDEVEN                                             */
65601   PWRCTRL_DEVPWREVENTEN_AUDEVEN_EN     = 1,     /*!< EN : Enable AUD power-on status event                                     */
65602   PWRCTRL_DEVPWREVENTEN_AUDEVEN_DIS    = 0,     /*!< DIS : Disable AUD power-on status event                                   */
65603 } PWRCTRL_DEVPWREVENTEN_AUDEVEN_Enum;
65604 
65605 /* =========================================  PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6]  ========================================= */
65606 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN                                            */
65607   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN    = 1,     /*!< EN : Enable MSPI power-on status event                                    */
65608   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS   = 0,     /*!< DIS : Disable MSPI power-on status event                                  */
65609 } PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum;
65610 
65611 /* =========================================  PWRCTRL DEVPWREVENTEN ADCEVEN [5..5]  ========================================== */
65612 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN                                             */
65613   PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN     = 1,     /*!< EN : Enable ADC power-on status event                                     */
65614   PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS    = 0,     /*!< DIS : Disable ADC power-on status event                                   */
65615 } PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum;
65616 
65617 /* =========================================  PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4]  ========================================= */
65618 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN                                            */
65619   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN    = 1,     /*!< EN : Enable HCPC power-on status event                                    */
65620   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS   = 0,     /*!< DIS : Disable HCPC power-on status event                                  */
65621 } PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum;
65622 
65623 /* =========================================  PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3]  ========================================= */
65624 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN                                            */
65625   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN    = 1,     /*!< EN : Enable HCPB power-on status event                                    */
65626   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS   = 0,     /*!< DIS : Disable HCPB power-on status event                                  */
65627 } PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum;
65628 
65629 /* =========================================  PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2]  ========================================= */
65630 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN                                            */
65631   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN    = 1,     /*!< EN : Enable HCPA power-on status event                                    */
65632   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS   = 0,     /*!< DIS : Disable HCPA power-on status event                                  */
65633 } PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum;
65634 
65635 /* =========================================  PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1]  ========================================= */
65636 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN                                            */
65637   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN    = 1,     /*!< EN : Enable MCHU power-on status event                                    */
65638   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS   = 0,     /*!< DIS : Disable MCUH power-on status event                                  */
65639 } PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum;
65640 
65641 /* =========================================  PWRCTRL DEVPWREVENTEN MCULEVEN [0..0]  ========================================= */
65642 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN                                            */
65643   PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN    = 1,     /*!< EN : Enable MCUL power-on status event                                    */
65644   PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS   = 0,     /*!< DIS : Disable MCUL power-on status event                                  */
65645 } PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum;
65646 
65647 /* =====================================================  MEMPWREVENTEN  ===================================================== */
65648 /* ========================================  PWRCTRL MEMPWREVENTEN CACHEB2EN [5..5]  ========================================= */
65649 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN                                           */
65650   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN   = 1,     /*!< EN : Enable CACHE BANK 2 status event                                     */
65651   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 2 status event                                   */
65652 } PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum;
65653 
65654 /* ========================================  PWRCTRL MEMPWREVENTEN CACHEB0EN [4..4]  ========================================= */
65655 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN                                           */
65656   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN   = 1,     /*!< EN : Enable CACHE BANK 0 status event                                     */
65657   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 0 status event                                   */
65658 } PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum;
65659 
65660 /* ==========================================  PWRCTRL MEMPWREVENTEN NVM0EN [3..3]  ========================================== */
65661 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_NVM0EN                                              */
65662   PWRCTRL_MEMPWREVENTEN_NVM0EN_EN      = 1,     /*!< EN : Enable NVM status event                                              */
65663   PWRCTRL_MEMPWREVENTEN_NVM0EN_DIS     = 0,     /*!< DIS : Disables NVM status event                                           */
65664 } PWRCTRL_MEMPWREVENTEN_NVM0EN_Enum;
65665 
65666 /* ==========================================  PWRCTRL MEMPWREVENTEN DTCMEN [0..2]  ========================================== */
65667 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN                                              */
65668   PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE    = 0,     /*!< NONE : Do not enable DTCM power-on status event                           */
65669   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event                */
65670   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event                */
65671   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3,    /*!< GROUP0EN : Enable DTCMs in group0 power on status event                   */
65672   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4,    /*!< GROUP1EN : Enable DTCMs in group1 power on status event                   */
65673   PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL     = 7,     /*!< ALL : Enable all DTCM power on status event                               */
65674 } PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum;
65675 
65676 /* ======================================================  MMSOVERRIDE  ====================================================== */
65677 /* ====================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMRETGFX [10..11]  ===================================== */
65678 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX                                     */
65679   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_ALWAYSON = 1,/*!< ALWAYSON : When PD_GFX is off, retention is always okay for
65680                                                      PD_GFX domain.                                                            */
65681   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_PGSTATE = 0,/*!< PGSTATE : When PD_GFX is off, retention is okay based on the
65682                                                      state of PD_GFX domain and SSRAMRETCFG.                                   */
65683 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Enum;
65684 
65685 /* =====================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMRETDISP [8..9]  ===================================== */
65686 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP                                    */
65687   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_ALWAYSON = 1,/*!< ALWAYSON : When PD_DISP is off, retention is always okay for
65688                                                      PD_DISP domain.                                                           */
65689   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_PGSTATE = 0,/*!< PGSTATE : When PD_DISP is off, retention is okay based on the
65690                                                      state of PD_DISP domain and SSRAMRETCFG.                                  */
65691 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Enum;
65692 
65693 /* =====================================  PWRCTRL MMSOVERRIDE MMSOVRDSPRAMRETGFX [6..7]  ===================================== */
65694 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX                                    */
65695   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_ALWAYSON = 1,/*!< ALWAYSON : When PD_GFX is off, retention is always okay for
65696                                                      PD_GFX domain.                                                            */
65697   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_PGSTATE = 0,/*!< PGSTATE : When PD_GFX is off, retention is okay based on the
65698                                                      state of PD_GFX domain and DSP[1|0]MEMRETCFG.                             */
65699 } PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Enum;
65700 
65701 /* ====================================  PWRCTRL MMSOVERRIDE MMSOVRDSPRAMRETDISP [4..5]  ===================================== */
65702 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP                                   */
65703   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_ALWAYSON = 1,/*!< ALWAYSON : When PD_DISP is off, retention is always okay for
65704                                                      PD_DISP domain.                                                           */
65705   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_PGSTATE = 0,/*!< PGSTATE : When PD_DISP is off, retention is okay based on the
65706                                                      state of PD_DISP domain and DSP[1|0]MEMRETCFG.                            */
65707 } PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Enum;
65708 
65709 /* =======================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMGFX [3..3]  ======================================= */
65710 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX                                        */
65711   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_NOGFX = 1, /*!< NOGFX : SSRAM power state is not affected by PD_GFX setting.              */
65712   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_PD_GFX = 0,/*!< PD_GFX : SSRAM power state set by SSRAMPWREN_PWRENSSRAM is overridden
65713                                                      by PD_GFX setting.                                                        */
65714 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Enum;
65715 
65716 /* ======================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMDISP [2..2]  ======================================= */
65717 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP                                       */
65718   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_NODISP = 1,/*!< NODISP : SSRAM power state is not affected by PD_DISP setting.           */
65719   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_PD_DISP = 0,/*!< PD_DISP : SSRAM power state set by SSRAMPWREN_PWRENSSRAM is
65720                                                      overridden by PD_DISP setting.                                            */
65721 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Enum;
65722 
65723 /* =======================================  PWRCTRL MMSOVERRIDE MMSOVRMCULGFX [1..1]  ======================================== */
65724 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX                                         */
65725   PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULON = 0, /*!< MCULON : When PD_GFX is on, MCUL is on.                                   */
65726   PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULOFF = 1,/*!< MCULOFF : When PD_GFX is on, MCUL is still off.                           */
65727 } PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Enum;
65728 
65729 /* =======================================  PWRCTRL MMSOVERRIDE MMSOVRMCULDISP [0..0]  ======================================= */
65730 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP                                        */
65731   PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULON = 0,/*!< MCULON : When PD_DISP is on, MCUL is on.                                  */
65732   PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULOFF = 1,/*!< MCULOFF : When PD_DISP is on, MCUL is still off.                         */
65733 } PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Enum;
65734 
65735 /* ======================================================  DSP0PWRCTRL  ====================================================== */
65736 /* ========================================  PWRCTRL DSP0PWRCTRL DSP0PCMRSTOR [4..4]  ======================================== */
65737 typedef enum {                                  /*!< PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR                                          */
65738   PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_EN  = 1,     /*!< EN : Keep DSP0 PCM in Reset                                               */
65739   PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_DIS = 0,     /*!< DIS : Remove DSP0 PCM Reset override                                      */
65740 } PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Enum;
65741 
65742 /* ======================================================  DSP0PERFREQ  ====================================================== */
65743 /* =======================================  PWRCTRL DSP0PERFREQ DSP0PERFSTATUS [3..4]  ======================================= */
65744 typedef enum {                                  /*!< PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS                                        */
65745   PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_ULP = 0,   /*!< ULP : DSP0 is in ULP mode (freq=48MHz)                                    */
65746   PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_LP = 1,    /*!< LP : DSP0 is in LP mode (freq=192MHz)                                     */
65747   PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_HP = 2,    /*!< HP : DSP0 is in HP mode (freq=384MHz)                                     */
65748 } PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Enum;
65749 
65750 /* ========================================  PWRCTRL DSP0PERFREQ DSP0PERFREQ [0..1]  ========================================= */
65751 typedef enum {                                  /*!< PWRCTRL_DSP0PERFREQ_DSP0PERFREQ                                           */
65752   PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_ULP  = 0,     /*!< ULP : DSP0 to be run in ULP mode (freq=48MHz)                             */
65753   PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_LP   = 1,     /*!< LP : DSP0 to be run in LP mode (freq=192MHz)                              */
65754   PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_HP   = 2,     /*!< HP : DSP0 to be run in HP mode (freq=384MHz)                              */
65755 } PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Enum;
65756 
65757 /* =====================================================  DSP0MEMPWREN  ====================================================== */
65758 /* ======================================  PWRCTRL DSP0MEMPWREN PWRENDSP0ICACHE [1..1]  ====================================== */
65759 typedef enum {                                  /*!< PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE                                      */
65760   PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_OFF = 0, /*!< OFF : Do not power up ICACHE                                              */
65761   PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_ON = 1,  /*!< ON : Power up ICACHE                                                      */
65762 } PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Enum;
65763 
65764 /* =======================================  PWRCTRL DSP0MEMPWREN PWRENDSP0RAM [0..0]  ======================================== */
65765 typedef enum {                                  /*!< PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM                                         */
65766   PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_OFF = 0,    /*!< OFF : Do not power ON any of the IRAM/DRAM                                */
65767   PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_ON = 1,     /*!< ON : Power up all IRAM (128K) and DRAM (256K)                             */
65768 } PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Enum;
65769 
65770 /* =====================================================  DSP0MEMPWRST  ====================================================== */
65771 /* =====================================================  DSP0MEMRETCFG  ===================================================== */
65772 /* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTGFX [4..4]  ======================================= */
65773 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX                                       */
65774   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
65775   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of GFX state                          */
65776 } PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Enum;
65777 
65778 /* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTDISP [3..3]  ====================================== */
65779 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP                                      */
65780   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                   */
65781   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_ACT = 1, /*!< ACT : Keep RAMs active irrespective of DISP state                         */
65782 } PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Enum;
65783 
65784 /* =====================================  PWRCTRL DSP0MEMRETCFG ICACHEPWDDSP0OFF [2..2]  ===================================== */
65785 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF                                    */
65786   PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_RET = 0,/*!< RET : ICACHE retained                                                    */
65787   PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_PWD = 1,/*!< PWD : Power down ICACHE                                                  */
65788 } PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Enum;
65789 
65790 /* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTMCU [1..1]  ======================================= */
65791 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU                                       */
65792   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
65793   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of MCU state                          */
65794 } PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Enum;
65795 
65796 /* ======================================  PWRCTRL DSP0MEMRETCFG RAMPWDDSP0OFF [0..0]  ======================================= */
65797 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF                                       */
65798   PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_RET = 0,  /*!< RET : IRAM and DRAM retained                                              */
65799   PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_PWD = 1,  /*!< PWD : Power down all IRAM and DRAM                                        */
65800 } PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Enum;
65801 
65802 /* ======================================================  DSP1PWRCTRL  ====================================================== */
65803 /* ========================================  PWRCTRL DSP1PWRCTRL DSP1PCMRSTOR [4..4]  ======================================== */
65804 typedef enum {                                  /*!< PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR                                          */
65805   PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_EN  = 1,     /*!< EN : Keep DSP1 PCM in Reset                                               */
65806   PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_DIS = 0,     /*!< DIS : Remove DSP1 PCM Reset override                                      */
65807 } PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Enum;
65808 
65809 /* ======================================================  DSP1PERFREQ  ====================================================== */
65810 /* =======================================  PWRCTRL DSP1PERFREQ DSP1PERFSTATUS [3..4]  ======================================= */
65811 typedef enum {                                  /*!< PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS                                        */
65812   PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_ULP = 0,   /*!< ULP : DSP1 is in ULP mode (freq=48MHz)                                    */
65813   PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_LP = 1,    /*!< LP : DSP1 is in LP mode (freq=192MHz)                                     */
65814   PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_HP = 2,    /*!< HP : DSP1 is in HP mode (freq=384MHz)                                     */
65815 } PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Enum;
65816 
65817 /* ========================================  PWRCTRL DSP1PERFREQ DSP1PERFREQ [0..1]  ========================================= */
65818 typedef enum {                                  /*!< PWRCTRL_DSP1PERFREQ_DSP1PERFREQ                                           */
65819   PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_ULP  = 0,     /*!< ULP : DSP1 to be run in ULP mode (freq=48MHz)                             */
65820   PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_LP   = 1,     /*!< LP : DSP1 to be run in LP mode (freq=192MHz)                              */
65821   PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_HP   = 2,     /*!< HP : DSP1 to be run in HP mode (freq=384MHz)                              */
65822 } PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Enum;
65823 
65824 /* =====================================================  DSP1MEMPWREN  ====================================================== */
65825 /* ======================================  PWRCTRL DSP1MEMPWREN PWRENDSP1ICACHE [1..1]  ====================================== */
65826 typedef enum {                                  /*!< PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE                                      */
65827   PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_OFF = 0, /*!< OFF : Do not power up ICACHE                                              */
65828   PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_ON = 1,  /*!< ON : Power up ICACHE                                                      */
65829 } PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Enum;
65830 
65831 /* =======================================  PWRCTRL DSP1MEMPWREN PWRENDSP1RAM [0..0]  ======================================== */
65832 typedef enum {                                  /*!< PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM                                         */
65833   PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_OFF = 0,    /*!< OFF : Do not power ON any of the IRAM/DRAM                                */
65834   PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_ON = 1,     /*!< ON : Power up all IRAM (32K) and DRAM (64K)                               */
65835 } PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Enum;
65836 
65837 /* =====================================================  DSP1MEMPWRST  ====================================================== */
65838 /* =====================================================  DSP1MEMRETCFG  ===================================================== */
65839 /* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTGFX [4..4]  ======================================= */
65840 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX                                       */
65841   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
65842   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of GFX state                          */
65843 } PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Enum;
65844 
65845 /* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTDISP [3..3]  ====================================== */
65846 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP                                      */
65847   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                   */
65848   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_ACT = 1, /*!< ACT : Keep RAMs active irrespective of DISP state                         */
65849 } PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Enum;
65850 
65851 /* =====================================  PWRCTRL DSP1MEMRETCFG ICACHEPWDDSP1OFF [2..2]  ===================================== */
65852 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF                                    */
65853   PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_RET = 0,/*!< RET : ICACHE retained                                                    */
65854   PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_PWD = 1,/*!< PWD : Power down ICACHE                                                  */
65855 } PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Enum;
65856 
65857 /* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTMCU [1..1]  ======================================= */
65858 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU                                       */
65859   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
65860   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of MCU state                          */
65861 } PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Enum;
65862 
65863 /* ======================================  PWRCTRL DSP1MEMRETCFG RAMPWDDSP1OFF [0..0]  ======================================= */
65864 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF                                       */
65865   PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_RET = 0,  /*!< RET : IRAM and DRAM retained                                              */
65866   PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_PWD = 1,  /*!< PWD : Power down all IRAM and DRAM                                        */
65867 } PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Enum;
65868 
65869 /* ========================================================  VRCTRL  ========================================================= */
65870 /* ===========================================  PWRCTRL VRCTRL SIMOBUCKEN [0..0]  ============================================ */
65871 typedef enum {                                  /*!< PWRCTRL_VRCTRL_SIMOBUCKEN                                                 */
65872   PWRCTRL_VRCTRL_SIMOBUCKEN_EN         = 1,     /*!< EN : Enable the SIMO Buck                                                 */
65873   PWRCTRL_VRCTRL_SIMOBUCKEN_DIS        = 0,     /*!< DIS : Disable the SIMO Buck                                               */
65874 } PWRCTRL_VRCTRL_SIMOBUCKEN_Enum;
65875 
65876 /* =====================================================  LEGACYVRLPOVR  ===================================================== */
65877 /* =======================================================  VRSTATUS  ======================================================== */
65878 /* ==========================================  PWRCTRL VRSTATUS SIMOBUCKST [4..5]  =========================================== */
65879 typedef enum {                                  /*!< PWRCTRL_VRSTATUS_SIMOBUCKST                                               */
65880   PWRCTRL_VRSTATUS_SIMOBUCKST_OFF      = 0,     /*!< OFF : Indicates the the SIMO BUCK is OFF.                                 */
65881   PWRCTRL_VRSTATUS_SIMOBUCKST_LP       = 2,     /*!< LP : Indicates the the SIMO BUCK is ON and in LP mode.                    */
65882   PWRCTRL_VRSTATUS_SIMOBUCKST_ACT      = 3,     /*!< ACT : Indicates the the SIMO BUCK is ON and in ACT mode.                  */
65883 } PWRCTRL_VRSTATUS_SIMOBUCKST_Enum;
65884 
65885 /* ===========================================  PWRCTRL VRSTATUS MEMLDOST [2..3]  ============================================ */
65886 typedef enum {                                  /*!< PWRCTRL_VRSTATUS_MEMLDOST                                                 */
65887   PWRCTRL_VRSTATUS_MEMLDOST_OFF        = 1,     /*!< OFF : Indicates the the MEMLDO is OFF.                                    */
65888   PWRCTRL_VRSTATUS_MEMLDOST_LP         = 2,     /*!< LP : Indicates the the MEMLDO is ON and in LP mode.                       */
65889   PWRCTRL_VRSTATUS_MEMLDOST_ACT        = 3,     /*!< ACT : Indicates the the MEMLDO is ON and in ACT mode.                     */
65890 } PWRCTRL_VRSTATUS_MEMLDOST_Enum;
65891 
65892 /* ===========================================  PWRCTRL VRSTATUS CORELDOST [0..1]  =========================================== */
65893 typedef enum {                                  /*!< PWRCTRL_VRSTATUS_CORELDOST                                                */
65894   PWRCTRL_VRSTATUS_CORELDOST_OFF       = 1,     /*!< OFF : Indicates the the CORELDO is OFF.                                   */
65895   PWRCTRL_VRSTATUS_CORELDOST_LP        = 2,     /*!< LP : Indicates the the CORELDO is ON and in LP mode.                      */
65896   PWRCTRL_VRSTATUS_CORELDOST_ACT       = 3,     /*!< ACT : Indicates the the CORELDO is ON and in ACT mode.                    */
65897 } PWRCTRL_VRSTATUS_CORELDOST_Enum;
65898 
65899 /* =====================================================  PWRWEIGHTULP0  ===================================================== */
65900 /* =====================================================  PWRWEIGHTULP1  ===================================================== */
65901 /* =====================================================  PWRWEIGHTULP2  ===================================================== */
65902 /* =====================================================  PWRWEIGHTULP3  ===================================================== */
65903 /* =====================================================  PWRWEIGHTULP4  ===================================================== */
65904 /* =====================================================  PWRWEIGHTULP5  ===================================================== */
65905 /* =====================================================  PWRWEIGHTLP0  ====================================================== */
65906 /* =====================================================  PWRWEIGHTLP1  ====================================================== */
65907 /* =====================================================  PWRWEIGHTLP2  ====================================================== */
65908 /* =====================================================  PWRWEIGHTLP3  ====================================================== */
65909 /* =====================================================  PWRWEIGHTLP4  ====================================================== */
65910 /* =====================================================  PWRWEIGHTLP5  ====================================================== */
65911 /* =====================================================  PWRWEIGHTHP0  ====================================================== */
65912 /* =====================================================  PWRWEIGHTHP1  ====================================================== */
65913 /* =====================================================  PWRWEIGHTHP2  ====================================================== */
65914 /* =====================================================  PWRWEIGHTHP3  ====================================================== */
65915 /* =====================================================  PWRWEIGHTHP4  ====================================================== */
65916 /* =====================================================  PWRWEIGHTHP5  ====================================================== */
65917 /* =====================================================  PWRWEIGHTSLP  ====================================================== */
65918 /* =====================================================  VRDEMOTIONTHR  ===================================================== */
65919 /* =======================================================  SRAMCTRL  ======================================================== */
65920 /* ========================================  PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19]  ======================================== */
65921 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP                                           */
65922   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL  = 255,   /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs                                    */
65923   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS  = 0,     /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs                                  */
65924 } PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum;
65925 
65926 /* =======================================  PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2]  ======================================= */
65927 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE                                        */
65928   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1,    /*!< EN : Enable Master SRAM Clock Gate                                        */
65929   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0,   /*!< DIS : Disables Master SRAM Clock Gating                                   */
65930 } PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum;
65931 
65932 /* ==========================================  PWRCTRL SRAMCTRL SRAMCLKGATE [1..1]  ========================================== */
65933 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE                                              */
65934   PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN      = 1,     /*!< EN : Enable Individual SRAM Clock Gating                                  */
65935   PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS     = 0,     /*!< DIS : Disables Individual SRAM Clock Gating                               */
65936 } PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum;
65937 
65938 /* =======================================================  ADCSTATUS  ======================================================= */
65939 /* =====================================================  AUDADCSTATUS  ====================================================== */
65940 /* =======================================================  EMONCTRL  ======================================================== */
65941 /* =======================================================  EMONCFG0  ======================================================== */
65942 /* ===========================================  PWRCTRL EMONCFG0 EMONSEL0 [0..7]  ============================================ */
65943 typedef enum {                                  /*!< PWRCTRL_EMONCFG0_EMONSEL0                                                 */
65944   PWRCTRL_EMONCFG0_EMONSEL0_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
65945   PWRCTRL_EMONCFG0_EMONSEL0_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
65946   PWRCTRL_EMONCFG0_EMONSEL0_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
65947   PWRCTRL_EMONCFG0_EMONSEL0_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
65948   PWRCTRL_EMONCFG0_EMONSEL0_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
65949   PWRCTRL_EMONCFG0_EMONSEL0_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
65950   PWRCTRL_EMONCFG0_EMONSEL0_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
65951   PWRCTRL_EMONCFG0_EMONSEL0_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
65952   PWRCTRL_EMONCFG0_EMONSEL0_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
65953   PWRCTRL_EMONCFG0_EMONSEL0_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
65954   PWRCTRL_EMONCFG0_EMONSEL0_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
65955   PWRCTRL_EMONCFG0_EMONSEL0_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
65956   PWRCTRL_EMONCFG0_EMONSEL0_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
65957   PWRCTRL_EMONCFG0_EMONSEL0_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
65958   PWRCTRL_EMONCFG0_EMONSEL0_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
65959   PWRCTRL_EMONCFG0_EMONSEL0_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
65960   PWRCTRL_EMONCFG0_EMONSEL0_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
65961   PWRCTRL_EMONCFG0_EMONSEL0_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
65962   PWRCTRL_EMONCFG0_EMONSEL0_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
65963   PWRCTRL_EMONCFG0_EMONSEL0_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
65964   PWRCTRL_EMONCFG0_EMONSEL0_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
65965   PWRCTRL_EMONCFG0_EMONSEL0_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
65966   PWRCTRL_EMONCFG0_EMONSEL0_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
65967   PWRCTRL_EMONCFG0_EMONSEL0_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
65968   PWRCTRL_EMONCFG0_EMONSEL0_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
65969   PWRCTRL_EMONCFG0_EMONSEL0_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
65970   PWRCTRL_EMONCFG0_EMONSEL0_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
65971   PWRCTRL_EMONCFG0_EMONSEL0_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
65972   PWRCTRL_EMONCFG0_EMONSEL0_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
65973   PWRCTRL_EMONCFG0_EMONSEL0_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
65974   PWRCTRL_EMONCFG0_EMONSEL0_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
65975   PWRCTRL_EMONCFG0_EMONSEL0_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
65976   PWRCTRL_EMONCFG0_EMONSEL0_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
65977   PWRCTRL_EMONCFG0_EMONSEL0_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
65978   PWRCTRL_EMONCFG0_EMONSEL0_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
65979   PWRCTRL_EMONCFG0_EMONSEL0_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
65980   PWRCTRL_EMONCFG0_EMONSEL0_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
65981   PWRCTRL_EMONCFG0_EMONSEL0_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
65982   PWRCTRL_EMONCFG0_EMONSEL0_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
65983   PWRCTRL_EMONCFG0_EMONSEL0_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
65984   PWRCTRL_EMONCFG0_EMONSEL0_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
65985 } PWRCTRL_EMONCFG0_EMONSEL0_Enum;
65986 
65987 /* =======================================================  EMONCFG1  ======================================================== */
65988 /* ===========================================  PWRCTRL EMONCFG1 EMONSEL1 [0..7]  ============================================ */
65989 typedef enum {                                  /*!< PWRCTRL_EMONCFG1_EMONSEL1                                                 */
65990   PWRCTRL_EMONCFG1_EMONSEL1_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
65991   PWRCTRL_EMONCFG1_EMONSEL1_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
65992   PWRCTRL_EMONCFG1_EMONSEL1_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
65993   PWRCTRL_EMONCFG1_EMONSEL1_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
65994   PWRCTRL_EMONCFG1_EMONSEL1_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
65995   PWRCTRL_EMONCFG1_EMONSEL1_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
65996   PWRCTRL_EMONCFG1_EMONSEL1_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
65997   PWRCTRL_EMONCFG1_EMONSEL1_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
65998   PWRCTRL_EMONCFG1_EMONSEL1_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
65999   PWRCTRL_EMONCFG1_EMONSEL1_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
66000   PWRCTRL_EMONCFG1_EMONSEL1_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
66001   PWRCTRL_EMONCFG1_EMONSEL1_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
66002   PWRCTRL_EMONCFG1_EMONSEL1_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
66003   PWRCTRL_EMONCFG1_EMONSEL1_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
66004   PWRCTRL_EMONCFG1_EMONSEL1_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
66005   PWRCTRL_EMONCFG1_EMONSEL1_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
66006   PWRCTRL_EMONCFG1_EMONSEL1_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
66007   PWRCTRL_EMONCFG1_EMONSEL1_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
66008   PWRCTRL_EMONCFG1_EMONSEL1_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
66009   PWRCTRL_EMONCFG1_EMONSEL1_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
66010   PWRCTRL_EMONCFG1_EMONSEL1_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
66011   PWRCTRL_EMONCFG1_EMONSEL1_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
66012   PWRCTRL_EMONCFG1_EMONSEL1_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
66013   PWRCTRL_EMONCFG1_EMONSEL1_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
66014   PWRCTRL_EMONCFG1_EMONSEL1_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
66015   PWRCTRL_EMONCFG1_EMONSEL1_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
66016   PWRCTRL_EMONCFG1_EMONSEL1_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
66017   PWRCTRL_EMONCFG1_EMONSEL1_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
66018   PWRCTRL_EMONCFG1_EMONSEL1_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
66019   PWRCTRL_EMONCFG1_EMONSEL1_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
66020   PWRCTRL_EMONCFG1_EMONSEL1_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
66021   PWRCTRL_EMONCFG1_EMONSEL1_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
66022   PWRCTRL_EMONCFG1_EMONSEL1_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
66023   PWRCTRL_EMONCFG1_EMONSEL1_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
66024   PWRCTRL_EMONCFG1_EMONSEL1_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
66025   PWRCTRL_EMONCFG1_EMONSEL1_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
66026   PWRCTRL_EMONCFG1_EMONSEL1_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
66027   PWRCTRL_EMONCFG1_EMONSEL1_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
66028   PWRCTRL_EMONCFG1_EMONSEL1_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
66029   PWRCTRL_EMONCFG1_EMONSEL1_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
66030   PWRCTRL_EMONCFG1_EMONSEL1_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
66031 } PWRCTRL_EMONCFG1_EMONSEL1_Enum;
66032 
66033 /* =======================================================  EMONCFG2  ======================================================== */
66034 /* ===========================================  PWRCTRL EMONCFG2 EMONSEL2 [0..7]  ============================================ */
66035 typedef enum {                                  /*!< PWRCTRL_EMONCFG2_EMONSEL2                                                 */
66036   PWRCTRL_EMONCFG2_EMONSEL2_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
66037   PWRCTRL_EMONCFG2_EMONSEL2_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
66038   PWRCTRL_EMONCFG2_EMONSEL2_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
66039   PWRCTRL_EMONCFG2_EMONSEL2_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
66040   PWRCTRL_EMONCFG2_EMONSEL2_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
66041   PWRCTRL_EMONCFG2_EMONSEL2_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
66042   PWRCTRL_EMONCFG2_EMONSEL2_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
66043   PWRCTRL_EMONCFG2_EMONSEL2_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
66044   PWRCTRL_EMONCFG2_EMONSEL2_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
66045   PWRCTRL_EMONCFG2_EMONSEL2_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
66046   PWRCTRL_EMONCFG2_EMONSEL2_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
66047   PWRCTRL_EMONCFG2_EMONSEL2_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
66048   PWRCTRL_EMONCFG2_EMONSEL2_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
66049   PWRCTRL_EMONCFG2_EMONSEL2_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
66050   PWRCTRL_EMONCFG2_EMONSEL2_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
66051   PWRCTRL_EMONCFG2_EMONSEL2_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
66052   PWRCTRL_EMONCFG2_EMONSEL2_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
66053   PWRCTRL_EMONCFG2_EMONSEL2_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
66054   PWRCTRL_EMONCFG2_EMONSEL2_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
66055   PWRCTRL_EMONCFG2_EMONSEL2_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
66056   PWRCTRL_EMONCFG2_EMONSEL2_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
66057   PWRCTRL_EMONCFG2_EMONSEL2_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
66058   PWRCTRL_EMONCFG2_EMONSEL2_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
66059   PWRCTRL_EMONCFG2_EMONSEL2_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
66060   PWRCTRL_EMONCFG2_EMONSEL2_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
66061   PWRCTRL_EMONCFG2_EMONSEL2_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
66062   PWRCTRL_EMONCFG2_EMONSEL2_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
66063   PWRCTRL_EMONCFG2_EMONSEL2_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
66064   PWRCTRL_EMONCFG2_EMONSEL2_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
66065   PWRCTRL_EMONCFG2_EMONSEL2_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
66066   PWRCTRL_EMONCFG2_EMONSEL2_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
66067   PWRCTRL_EMONCFG2_EMONSEL2_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
66068   PWRCTRL_EMONCFG2_EMONSEL2_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
66069   PWRCTRL_EMONCFG2_EMONSEL2_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
66070   PWRCTRL_EMONCFG2_EMONSEL2_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
66071   PWRCTRL_EMONCFG2_EMONSEL2_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
66072   PWRCTRL_EMONCFG2_EMONSEL2_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
66073   PWRCTRL_EMONCFG2_EMONSEL2_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
66074   PWRCTRL_EMONCFG2_EMONSEL2_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
66075   PWRCTRL_EMONCFG2_EMONSEL2_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
66076   PWRCTRL_EMONCFG2_EMONSEL2_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
66077 } PWRCTRL_EMONCFG2_EMONSEL2_Enum;
66078 
66079 /* =======================================================  EMONCFG3  ======================================================== */
66080 /* ===========================================  PWRCTRL EMONCFG3 EMONSEL3 [0..7]  ============================================ */
66081 typedef enum {                                  /*!< PWRCTRL_EMONCFG3_EMONSEL3                                                 */
66082   PWRCTRL_EMONCFG3_EMONSEL3_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
66083   PWRCTRL_EMONCFG3_EMONSEL3_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
66084   PWRCTRL_EMONCFG3_EMONSEL3_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
66085   PWRCTRL_EMONCFG3_EMONSEL3_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
66086   PWRCTRL_EMONCFG3_EMONSEL3_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
66087   PWRCTRL_EMONCFG3_EMONSEL3_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
66088   PWRCTRL_EMONCFG3_EMONSEL3_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
66089   PWRCTRL_EMONCFG3_EMONSEL3_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
66090   PWRCTRL_EMONCFG3_EMONSEL3_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
66091   PWRCTRL_EMONCFG3_EMONSEL3_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
66092   PWRCTRL_EMONCFG3_EMONSEL3_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
66093   PWRCTRL_EMONCFG3_EMONSEL3_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
66094   PWRCTRL_EMONCFG3_EMONSEL3_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
66095   PWRCTRL_EMONCFG3_EMONSEL3_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
66096   PWRCTRL_EMONCFG3_EMONSEL3_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
66097   PWRCTRL_EMONCFG3_EMONSEL3_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
66098   PWRCTRL_EMONCFG3_EMONSEL3_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
66099   PWRCTRL_EMONCFG3_EMONSEL3_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
66100   PWRCTRL_EMONCFG3_EMONSEL3_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
66101   PWRCTRL_EMONCFG3_EMONSEL3_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
66102   PWRCTRL_EMONCFG3_EMONSEL3_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
66103   PWRCTRL_EMONCFG3_EMONSEL3_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
66104   PWRCTRL_EMONCFG3_EMONSEL3_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
66105   PWRCTRL_EMONCFG3_EMONSEL3_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
66106   PWRCTRL_EMONCFG3_EMONSEL3_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
66107   PWRCTRL_EMONCFG3_EMONSEL3_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
66108   PWRCTRL_EMONCFG3_EMONSEL3_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
66109   PWRCTRL_EMONCFG3_EMONSEL3_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
66110   PWRCTRL_EMONCFG3_EMONSEL3_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
66111   PWRCTRL_EMONCFG3_EMONSEL3_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
66112   PWRCTRL_EMONCFG3_EMONSEL3_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
66113   PWRCTRL_EMONCFG3_EMONSEL3_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
66114   PWRCTRL_EMONCFG3_EMONSEL3_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
66115   PWRCTRL_EMONCFG3_EMONSEL3_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
66116   PWRCTRL_EMONCFG3_EMONSEL3_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
66117   PWRCTRL_EMONCFG3_EMONSEL3_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
66118   PWRCTRL_EMONCFG3_EMONSEL3_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
66119   PWRCTRL_EMONCFG3_EMONSEL3_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
66120   PWRCTRL_EMONCFG3_EMONSEL3_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
66121   PWRCTRL_EMONCFG3_EMONSEL3_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
66122   PWRCTRL_EMONCFG3_EMONSEL3_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
66123 } PWRCTRL_EMONCFG3_EMONSEL3_Enum;
66124 
66125 /* =======================================================  EMONCFG4  ======================================================== */
66126 /* ===========================================  PWRCTRL EMONCFG4 EMONSEL4 [0..7]  ============================================ */
66127 typedef enum {                                  /*!< PWRCTRL_EMONCFG4_EMONSEL4                                                 */
66128   PWRCTRL_EMONCFG4_EMONSEL4_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
66129   PWRCTRL_EMONCFG4_EMONSEL4_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
66130   PWRCTRL_EMONCFG4_EMONSEL4_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
66131   PWRCTRL_EMONCFG4_EMONSEL4_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
66132   PWRCTRL_EMONCFG4_EMONSEL4_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
66133   PWRCTRL_EMONCFG4_EMONSEL4_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
66134   PWRCTRL_EMONCFG4_EMONSEL4_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
66135   PWRCTRL_EMONCFG4_EMONSEL4_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
66136   PWRCTRL_EMONCFG4_EMONSEL4_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
66137   PWRCTRL_EMONCFG4_EMONSEL4_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
66138   PWRCTRL_EMONCFG4_EMONSEL4_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
66139   PWRCTRL_EMONCFG4_EMONSEL4_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
66140   PWRCTRL_EMONCFG4_EMONSEL4_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
66141   PWRCTRL_EMONCFG4_EMONSEL4_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
66142   PWRCTRL_EMONCFG4_EMONSEL4_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
66143   PWRCTRL_EMONCFG4_EMONSEL4_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
66144   PWRCTRL_EMONCFG4_EMONSEL4_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
66145   PWRCTRL_EMONCFG4_EMONSEL4_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
66146   PWRCTRL_EMONCFG4_EMONSEL4_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
66147   PWRCTRL_EMONCFG4_EMONSEL4_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
66148   PWRCTRL_EMONCFG4_EMONSEL4_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
66149   PWRCTRL_EMONCFG4_EMONSEL4_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
66150   PWRCTRL_EMONCFG4_EMONSEL4_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
66151   PWRCTRL_EMONCFG4_EMONSEL4_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
66152   PWRCTRL_EMONCFG4_EMONSEL4_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
66153   PWRCTRL_EMONCFG4_EMONSEL4_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
66154   PWRCTRL_EMONCFG4_EMONSEL4_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
66155   PWRCTRL_EMONCFG4_EMONSEL4_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
66156   PWRCTRL_EMONCFG4_EMONSEL4_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
66157   PWRCTRL_EMONCFG4_EMONSEL4_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
66158   PWRCTRL_EMONCFG4_EMONSEL4_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
66159   PWRCTRL_EMONCFG4_EMONSEL4_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
66160   PWRCTRL_EMONCFG4_EMONSEL4_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
66161   PWRCTRL_EMONCFG4_EMONSEL4_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
66162   PWRCTRL_EMONCFG4_EMONSEL4_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
66163   PWRCTRL_EMONCFG4_EMONSEL4_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
66164   PWRCTRL_EMONCFG4_EMONSEL4_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
66165   PWRCTRL_EMONCFG4_EMONSEL4_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
66166   PWRCTRL_EMONCFG4_EMONSEL4_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
66167   PWRCTRL_EMONCFG4_EMONSEL4_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
66168   PWRCTRL_EMONCFG4_EMONSEL4_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
66169 } PWRCTRL_EMONCFG4_EMONSEL4_Enum;
66170 
66171 /* =======================================================  EMONCFG5  ======================================================== */
66172 /* ===========================================  PWRCTRL EMONCFG5 EMONSEL5 [0..7]  ============================================ */
66173 typedef enum {                                  /*!< PWRCTRL_EMONCFG5_EMONSEL5                                                 */
66174   PWRCTRL_EMONCFG5_EMONSEL5_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
66175   PWRCTRL_EMONCFG5_EMONSEL5_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
66176   PWRCTRL_EMONCFG5_EMONSEL5_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
66177   PWRCTRL_EMONCFG5_EMONSEL5_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
66178   PWRCTRL_EMONCFG5_EMONSEL5_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
66179   PWRCTRL_EMONCFG5_EMONSEL5_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
66180   PWRCTRL_EMONCFG5_EMONSEL5_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
66181   PWRCTRL_EMONCFG5_EMONSEL5_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
66182   PWRCTRL_EMONCFG5_EMONSEL5_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
66183   PWRCTRL_EMONCFG5_EMONSEL5_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
66184   PWRCTRL_EMONCFG5_EMONSEL5_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
66185   PWRCTRL_EMONCFG5_EMONSEL5_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
66186   PWRCTRL_EMONCFG5_EMONSEL5_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
66187   PWRCTRL_EMONCFG5_EMONSEL5_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
66188   PWRCTRL_EMONCFG5_EMONSEL5_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
66189   PWRCTRL_EMONCFG5_EMONSEL5_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
66190   PWRCTRL_EMONCFG5_EMONSEL5_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
66191   PWRCTRL_EMONCFG5_EMONSEL5_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
66192   PWRCTRL_EMONCFG5_EMONSEL5_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
66193   PWRCTRL_EMONCFG5_EMONSEL5_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
66194   PWRCTRL_EMONCFG5_EMONSEL5_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
66195   PWRCTRL_EMONCFG5_EMONSEL5_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
66196   PWRCTRL_EMONCFG5_EMONSEL5_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
66197   PWRCTRL_EMONCFG5_EMONSEL5_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
66198   PWRCTRL_EMONCFG5_EMONSEL5_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
66199   PWRCTRL_EMONCFG5_EMONSEL5_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
66200   PWRCTRL_EMONCFG5_EMONSEL5_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
66201   PWRCTRL_EMONCFG5_EMONSEL5_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
66202   PWRCTRL_EMONCFG5_EMONSEL5_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
66203   PWRCTRL_EMONCFG5_EMONSEL5_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
66204   PWRCTRL_EMONCFG5_EMONSEL5_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
66205   PWRCTRL_EMONCFG5_EMONSEL5_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
66206   PWRCTRL_EMONCFG5_EMONSEL5_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
66207   PWRCTRL_EMONCFG5_EMONSEL5_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
66208   PWRCTRL_EMONCFG5_EMONSEL5_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
66209   PWRCTRL_EMONCFG5_EMONSEL5_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
66210   PWRCTRL_EMONCFG5_EMONSEL5_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
66211   PWRCTRL_EMONCFG5_EMONSEL5_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
66212   PWRCTRL_EMONCFG5_EMONSEL5_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
66213   PWRCTRL_EMONCFG5_EMONSEL5_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
66214   PWRCTRL_EMONCFG5_EMONSEL5_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
66215 } PWRCTRL_EMONCFG5_EMONSEL5_Enum;
66216 
66217 /* =======================================================  EMONCFG6  ======================================================== */
66218 /* ===========================================  PWRCTRL EMONCFG6 EMONSEL6 [0..7]  ============================================ */
66219 typedef enum {                                  /*!< PWRCTRL_EMONCFG6_EMONSEL6                                                 */
66220   PWRCTRL_EMONCFG6_EMONSEL6_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
66221   PWRCTRL_EMONCFG6_EMONSEL6_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
66222   PWRCTRL_EMONCFG6_EMONSEL6_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
66223   PWRCTRL_EMONCFG6_EMONSEL6_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
66224   PWRCTRL_EMONCFG6_EMONSEL6_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
66225   PWRCTRL_EMONCFG6_EMONSEL6_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
66226   PWRCTRL_EMONCFG6_EMONSEL6_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
66227   PWRCTRL_EMONCFG6_EMONSEL6_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
66228   PWRCTRL_EMONCFG6_EMONSEL6_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
66229   PWRCTRL_EMONCFG6_EMONSEL6_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
66230   PWRCTRL_EMONCFG6_EMONSEL6_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
66231   PWRCTRL_EMONCFG6_EMONSEL6_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
66232   PWRCTRL_EMONCFG6_EMONSEL6_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
66233   PWRCTRL_EMONCFG6_EMONSEL6_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
66234   PWRCTRL_EMONCFG6_EMONSEL6_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
66235   PWRCTRL_EMONCFG6_EMONSEL6_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
66236   PWRCTRL_EMONCFG6_EMONSEL6_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
66237   PWRCTRL_EMONCFG6_EMONSEL6_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
66238   PWRCTRL_EMONCFG6_EMONSEL6_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
66239   PWRCTRL_EMONCFG6_EMONSEL6_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
66240   PWRCTRL_EMONCFG6_EMONSEL6_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
66241   PWRCTRL_EMONCFG6_EMONSEL6_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
66242   PWRCTRL_EMONCFG6_EMONSEL6_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
66243   PWRCTRL_EMONCFG6_EMONSEL6_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
66244   PWRCTRL_EMONCFG6_EMONSEL6_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
66245   PWRCTRL_EMONCFG6_EMONSEL6_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
66246   PWRCTRL_EMONCFG6_EMONSEL6_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
66247   PWRCTRL_EMONCFG6_EMONSEL6_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
66248   PWRCTRL_EMONCFG6_EMONSEL6_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
66249   PWRCTRL_EMONCFG6_EMONSEL6_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
66250   PWRCTRL_EMONCFG6_EMONSEL6_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
66251   PWRCTRL_EMONCFG6_EMONSEL6_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
66252   PWRCTRL_EMONCFG6_EMONSEL6_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
66253   PWRCTRL_EMONCFG6_EMONSEL6_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
66254   PWRCTRL_EMONCFG6_EMONSEL6_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
66255   PWRCTRL_EMONCFG6_EMONSEL6_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
66256   PWRCTRL_EMONCFG6_EMONSEL6_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
66257   PWRCTRL_EMONCFG6_EMONSEL6_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
66258   PWRCTRL_EMONCFG6_EMONSEL6_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
66259   PWRCTRL_EMONCFG6_EMONSEL6_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
66260   PWRCTRL_EMONCFG6_EMONSEL6_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
66261 } PWRCTRL_EMONCFG6_EMONSEL6_Enum;
66262 
66263 /* =======================================================  EMONCFG7  ======================================================== */
66264 /* ===========================================  PWRCTRL EMONCFG7 EMONSEL7 [0..7]  ============================================ */
66265 typedef enum {                                  /*!< PWRCTRL_EMONCFG7_EMONSEL7                                                 */
66266   PWRCTRL_EMONCFG7_EMONSEL7_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
66267   PWRCTRL_EMONCFG7_EMONSEL7_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
66268   PWRCTRL_EMONCFG7_EMONSEL7_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
66269   PWRCTRL_EMONCFG7_EMONSEL7_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
66270   PWRCTRL_EMONCFG7_EMONSEL7_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
66271   PWRCTRL_EMONCFG7_EMONSEL7_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
66272   PWRCTRL_EMONCFG7_EMONSEL7_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
66273   PWRCTRL_EMONCFG7_EMONSEL7_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
66274   PWRCTRL_EMONCFG7_EMONSEL7_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
66275   PWRCTRL_EMONCFG7_EMONSEL7_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
66276   PWRCTRL_EMONCFG7_EMONSEL7_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
66277   PWRCTRL_EMONCFG7_EMONSEL7_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
66278   PWRCTRL_EMONCFG7_EMONSEL7_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
66279   PWRCTRL_EMONCFG7_EMONSEL7_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
66280   PWRCTRL_EMONCFG7_EMONSEL7_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
66281   PWRCTRL_EMONCFG7_EMONSEL7_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
66282   PWRCTRL_EMONCFG7_EMONSEL7_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
66283   PWRCTRL_EMONCFG7_EMONSEL7_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
66284   PWRCTRL_EMONCFG7_EMONSEL7_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
66285   PWRCTRL_EMONCFG7_EMONSEL7_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
66286   PWRCTRL_EMONCFG7_EMONSEL7_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
66287   PWRCTRL_EMONCFG7_EMONSEL7_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
66288   PWRCTRL_EMONCFG7_EMONSEL7_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
66289   PWRCTRL_EMONCFG7_EMONSEL7_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
66290   PWRCTRL_EMONCFG7_EMONSEL7_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
66291   PWRCTRL_EMONCFG7_EMONSEL7_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
66292   PWRCTRL_EMONCFG7_EMONSEL7_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
66293   PWRCTRL_EMONCFG7_EMONSEL7_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
66294   PWRCTRL_EMONCFG7_EMONSEL7_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
66295   PWRCTRL_EMONCFG7_EMONSEL7_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
66296   PWRCTRL_EMONCFG7_EMONSEL7_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
66297   PWRCTRL_EMONCFG7_EMONSEL7_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
66298   PWRCTRL_EMONCFG7_EMONSEL7_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
66299   PWRCTRL_EMONCFG7_EMONSEL7_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
66300   PWRCTRL_EMONCFG7_EMONSEL7_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
66301   PWRCTRL_EMONCFG7_EMONSEL7_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
66302   PWRCTRL_EMONCFG7_EMONSEL7_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
66303   PWRCTRL_EMONCFG7_EMONSEL7_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
66304   PWRCTRL_EMONCFG7_EMONSEL7_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
66305   PWRCTRL_EMONCFG7_EMONSEL7_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
66306   PWRCTRL_EMONCFG7_EMONSEL7_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
66307 } PWRCTRL_EMONCFG7_EMONSEL7_Enum;
66308 
66309 /* ======================================================  EMONCOUNT0  ======================================================= */
66310 /* ======================================================  EMONCOUNT1  ======================================================= */
66311 /* ======================================================  EMONCOUNT2  ======================================================= */
66312 /* ======================================================  EMONCOUNT3  ======================================================= */
66313 /* ======================================================  EMONCOUNT4  ======================================================= */
66314 /* ======================================================  EMONCOUNT5  ======================================================= */
66315 /* ======================================================  EMONCOUNT6  ======================================================= */
66316 /* ======================================================  EMONCOUNT7  ======================================================= */
66317 /* ======================================================  EMONSTATUS  ======================================================= */
66318 
66319 
66320 /* =========================================================================================================================== */
66321 /* ================                                          RSTGEN                                           ================ */
66322 /* =========================================================================================================================== */
66323 
66324 /* ==========================================================  CFG  ========================================================== */
66325 /* =========================================================  SWPOI  ========================================================= */
66326 /* =============================================  RSTGEN SWPOI SWPOIKEY [0..7]  ============================================== */
66327 typedef enum {                                  /*!< RSTGEN_SWPOI_SWPOIKEY                                                     */
66328   RSTGEN_SWPOI_SWPOIKEY_KEYVALUE       = 27,    /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset.         */
66329 } RSTGEN_SWPOI_SWPOIKEY_Enum;
66330 
66331 /* =========================================================  SWPOR  ========================================================= */
66332 /* =============================================  RSTGEN SWPOR SWPORKEY [0..7]  ============================================== */
66333 typedef enum {                                  /*!< RSTGEN_SWPOR_SWPORKEY                                                     */
66334   RSTGEN_SWPOR_SWPORKEY_KEYVALUE       = 212,   /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset.         */
66335 } RSTGEN_SWPOR_SWPORKEY_Enum;
66336 
66337 /* =======================================================  SIMOBODM  ======================================================== */
66338 /* ===========================================  RSTGEN SIMOBODM DIGBOECLV [3..3]  ============================================ */
66339 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOECLV                                                 */
66340   RSTGEN_SIMOBODM_DIGBOECLV_BOM        = 0,     /*!< BOM : Mask the VDDC_LV digital brownout detection into the interrupt
66341                                                      block.                                                                    */
66342   RSTGEN_SIMOBODM_DIGBOECLV_BOE        = 1,     /*!< BOE : Enable brown VDDC_LV digital brownout detection into the
66343                                                      interrupt block.                                                          */
66344 } RSTGEN_SIMOBODM_DIGBOECLV_Enum;
66345 
66346 /* ============================================  RSTGEN SIMOBODM DIGBOES [2..2]  ============================================= */
66347 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOES                                                   */
66348   RSTGEN_SIMOBODM_DIGBOES_BOM          = 0,     /*!< BOM : Mask the VDDS digital brownout detection into the interrupt
66349                                                      block.                                                                    */
66350   RSTGEN_SIMOBODM_DIGBOES_BOE          = 1,     /*!< BOE : Enable the VDDS digital brownout detection into the interrupt
66351                                                      block.                                                                    */
66352 } RSTGEN_SIMOBODM_DIGBOES_Enum;
66353 
66354 /* ============================================  RSTGEN SIMOBODM DIGBOEF [1..1]  ============================================= */
66355 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOEF                                                   */
66356   RSTGEN_SIMOBODM_DIGBOEF_BOM          = 0,     /*!< BOM : Mask the VDDF digital brownout detection into the interrupt
66357                                                      block.                                                                    */
66358   RSTGEN_SIMOBODM_DIGBOEF_BOE          = 1,     /*!< BOE : Enable the VDDF digital brownout detection into the interrupt
66359                                                      block.                                                                    */
66360 } RSTGEN_SIMOBODM_DIGBOEF_Enum;
66361 
66362 /* ============================================  RSTGEN SIMOBODM DIGBOEC [0..0]  ============================================= */
66363 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOEC                                                   */
66364   RSTGEN_SIMOBODM_DIGBOEC_BOA          = 0,     /*!< BOA : Enable brown out detection for VDDF using the analog method.        */
66365   RSTGEN_SIMOBODM_DIGBOEC_BOD          = 1,     /*!< BOD : Enable brown out detection for VDDF using the digital
66366                                                      method.                                                                   */
66367 } RSTGEN_SIMOBODM_DIGBOEC_Enum;
66368 
66369 /* =========================================================  INTEN  ========================================================= */
66370 /* ========================================================  INTSTAT  ======================================================== */
66371 /* ========================================================  INTCLR  ========================================================= */
66372 /* ========================================================  INTSET  ========================================================= */
66373 /* =========================================================  STAT  ========================================================== */
66374 
66375 
66376 /* =========================================================================================================================== */
66377 /* ================                                            RTC                                            ================ */
66378 /* =========================================================================================================================== */
66379 
66380 /* ========================================================  RTCCTL  ========================================================= */
66381 /* ================================================  RTC RTCCTL RSTOP [4..4]  ================================================ */
66382 typedef enum {                                  /*!< RTC_RTCCTL_RSTOP                                                          */
66383   RTC_RTCCTL_RSTOP_RUN                 = 0,     /*!< RUN : Allow the RTC input clock to run                                    */
66384   RTC_RTCCTL_RSTOP_STOP                = 1,     /*!< STOP : Stop the RTC input clock                                           */
66385 } RTC_RTCCTL_RSTOP_Enum;
66386 
66387 /* =================================================  RTC RTCCTL RPT [1..3]  ================================================= */
66388 typedef enum {                                  /*!< RTC_RTCCTL_RPT                                                            */
66389   RTC_RTCCTL_RPT_DIS                   = 0,     /*!< DIS : Alarm interrupt disabled                                            */
66390   RTC_RTCCTL_RPT_YEAR                  = 1,     /*!< YEAR : Interrupt every year                                               */
66391   RTC_RTCCTL_RPT_MONTH                 = 2,     /*!< MONTH : Interrupt every month                                             */
66392   RTC_RTCCTL_RPT_WEEK                  = 3,     /*!< WEEK : Interrupt every week                                               */
66393   RTC_RTCCTL_RPT_DAY                   = 4,     /*!< DAY : Interrupt every day                                                 */
66394   RTC_RTCCTL_RPT_HR                    = 5,     /*!< HR : Interrupt every hour                                                 */
66395   RTC_RTCCTL_RPT_MIN                   = 6,     /*!< MIN : Interrupt every minute                                              */
66396   RTC_RTCCTL_RPT_SEC                   = 7,     /*!< SEC : Interrupt every second/10th/100th                                   */
66397 } RTC_RTCCTL_RPT_Enum;
66398 
66399 /* ================================================  RTC RTCCTL WRTC [0..0]  ================================================= */
66400 typedef enum {                                  /*!< RTC_RTCCTL_WRTC                                                           */
66401   RTC_RTCCTL_WRTC_DIS                  = 0,     /*!< DIS : Counter writes are disabled                                         */
66402   RTC_RTCCTL_WRTC_EN                   = 1,     /*!< EN : Counter writes are enabled                                           */
66403 } RTC_RTCCTL_WRTC_Enum;
66404 
66405 /* ========================================================  RTCSTAT  ======================================================== */
66406 /* ========================================================  CTRLOW  ========================================================= */
66407 /* =========================================================  CTRUP  ========================================================= */
66408 /* ===============================================  RTC CTRUP CTERR [31..31]  ================================================ */
66409 typedef enum {                                  /*!< RTC_CTRUP_CTERR                                                           */
66410   RTC_CTRUP_CTERR_NOERR                = 0,     /*!< NOERR : No read error occurred                                            */
66411   RTC_CTRUP_CTERR_RDERR                = 1,     /*!< RDERR : Read error occurred                                               */
66412 } RTC_CTRUP_CTERR_Enum;
66413 
66414 /* ================================================  RTC CTRUP CEB [29..29]  ================================================= */
66415 typedef enum {                                  /*!< RTC_CTRUP_CEB                                                             */
66416   RTC_CTRUP_CEB_DIS                    = 0,     /*!< DIS : Disable the Century bit from changing                               */
66417   RTC_CTRUP_CEB_EN                     = 1,     /*!< EN : Enable the Century bit to change                                     */
66418 } RTC_CTRUP_CEB_Enum;
66419 
66420 /* =================================================  RTC CTRUP CB [28..28]  ================================================= */
66421 typedef enum {                                  /*!< RTC_CTRUP_CB                                                              */
66422   RTC_CTRUP_CB_2000                    = 0,     /*!< 2000 : Century is 2000s                                                   */
66423   RTC_CTRUP_CB_1900_2100               = 1,     /*!< 1900_2100 : Century is 1900s/2100s                                        */
66424 } RTC_CTRUP_CB_Enum;
66425 
66426 /* ========================================================  ALMLOW  ========================================================= */
66427 /* =========================================================  ALMUP  ========================================================= */
66428 /* =========================================================  INTEN  ========================================================= */
66429 /* ========================================================  INTSTAT  ======================================================== */
66430 /* ========================================================  INTCLR  ========================================================= */
66431 /* ========================================================  INTSET  ========================================================= */
66432 
66433 
66434 /* =========================================================================================================================== */
66435 /* ================                                           SDIO                                            ================ */
66436 /* =========================================================================================================================== */
66437 
66438 /* =========================================================  SDMA  ========================================================== */
66439 /* =========================================================  BLOCK  ========================================================= */
66440 /* ==============================================  SDIO BLOCK BLKCNT [16..31]  =============================================== */
66441 typedef enum {                                  /*!< SDIO_BLOCK_BLKCNT                                                         */
66442   SDIO_BLOCK_BLKCNT_STOPCNT            = 0,     /*!< STOPCNT : Stop Count                                                      */
66443   SDIO_BLOCK_BLKCNT_1BLOCK             = 1,     /*!< 1BLOCK : 1 block                                                          */
66444   SDIO_BLOCK_BLKCNT_2BLOCKS            = 2,     /*!< 2BLOCKS : 2 blocks (and so on from 1-65535)                               */
66445   SDIO_BLOCK_BLKCNT_65535BLOCKS        = 65535, /*!< 65535BLOCKS : 65535 blocks                                                */
66446 } SDIO_BLOCK_BLKCNT_Enum;
66447 
66448 /* ===========================================  SDIO BLOCK HOSTSDMABUFSZ [12..14]  =========================================== */
66449 typedef enum {                                  /*!< SDIO_BLOCK_HOSTSDMABUFSZ                                                  */
66450   SDIO_BLOCK_HOSTSDMABUFSZ_4KB         = 0,     /*!< 4KB : 4KB(Detects A11 Carry out)                                          */
66451   SDIO_BLOCK_HOSTSDMABUFSZ_8KB         = 1,     /*!< 8KB : 8KB(Detects A12 Carry out)                                          */
66452   SDIO_BLOCK_HOSTSDMABUFSZ_16KB        = 2,     /*!< 16KB : 16KB(Detects A13 Carry out)                                        */
66453   SDIO_BLOCK_HOSTSDMABUFSZ_32KB        = 3,     /*!< 32KB : 32KB(Detects A14 Carry out)                                        */
66454   SDIO_BLOCK_HOSTSDMABUFSZ_64KB        = 4,     /*!< 64KB : 64KB(Detects A15 Carry out)                                        */
66455   SDIO_BLOCK_HOSTSDMABUFSZ_128KB       = 5,     /*!< 128KB : 128KB(Detects A16 Carry out)                                      */
66456   SDIO_BLOCK_HOSTSDMABUFSZ_256KB       = 6,     /*!< 256KB : 256KB(Detects A17 Carry out)                                      */
66457   SDIO_BLOCK_HOSTSDMABUFSZ_512KB       = 7,     /*!< 512KB : 512KB(Detects A18 Carry out)                                      */
66458 } SDIO_BLOCK_HOSTSDMABUFSZ_Enum;
66459 
66460 /* =========================================  SDIO BLOCK TRANSFERBLOCKSIZE [0..11]  ========================================== */
66461 typedef enum {                                  /*!< SDIO_BLOCK_TRANSFERBLOCKSIZE                                              */
66462   SDIO_BLOCK_TRANSFERBLOCKSIZE_NODATAXFER = 0,  /*!< NODATAXFER : No Data Transfer                                             */
66463   SDIO_BLOCK_TRANSFERBLOCKSIZE_1BYTE   = 1,     /*!< 1BYTE : 1 Byte                                                            */
66464   SDIO_BLOCK_TRANSFERBLOCKSIZE_2BYTES  = 2,     /*!< 2BYTES : 2 Bytes                                                          */
66465   SDIO_BLOCK_TRANSFERBLOCKSIZE_3BYTES  = 3,     /*!< 3BYTES : 3 Bytes                                                          */
66466   SDIO_BLOCK_TRANSFERBLOCKSIZE_4BYTES  = 4,     /*!< 4BYTES : 4 Bytes (and so on from 1-2048)                                  */
66467   SDIO_BLOCK_TRANSFERBLOCKSIZE_511BYTES = 511,  /*!< 511BYTES : 511 Bytes                                                      */
66468   SDIO_BLOCK_TRANSFERBLOCKSIZE_512BYTES = 512,  /*!< 512BYTES : 512 Bytes                                                      */
66469   SDIO_BLOCK_TRANSFERBLOCKSIZE_2048BYTES = 2048,/*!< 2048BYTES : 2048 Bytes                                                    */
66470 } SDIO_BLOCK_TRANSFERBLOCKSIZE_Enum;
66471 
66472 /* =======================================================  ARGUMENT1  ======================================================= */
66473 /* =======================================================  TRANSFER  ======================================================== */
66474 /* ============================================  SDIO TRANSFER CMDTYPE [22..23]  ============================================= */
66475 typedef enum {                                  /*!< SDIO_TRANSFER_CMDTYPE                                                     */
66476   SDIO_TRANSFER_CMDTYPE_NORMAL         = 0,     /*!< NORMAL : Normal                                                           */
66477   SDIO_TRANSFER_CMDTYPE_SUSPEND        = 1,     /*!< SUSPEND : Suspend                                                         */
66478   SDIO_TRANSFER_CMDTYPE_RESUME         = 2,     /*!< RESUME : Resume                                                           */
66479   SDIO_TRANSFER_CMDTYPE_ABORT          = 3,     /*!< ABORT : Abort                                                             */
66480 } SDIO_TRANSFER_CMDTYPE_Enum;
66481 
66482 /* ==========================================  SDIO TRANSFER DATAPRSNTSEL [21..21]  ========================================== */
66483 typedef enum {                                  /*!< SDIO_TRANSFER_DATAPRSNTSEL                                                */
66484   SDIO_TRANSFER_DATAPRSNTSEL_NODATAPRESENT = 0, /*!< NODATAPRESENT : No Data Present                                           */
66485   SDIO_TRANSFER_DATAPRSNTSEL_DATAPRESENT = 1,   /*!< DATAPRESENT : Data Present                                                */
66486 } SDIO_TRANSFER_DATAPRSNTSEL_Enum;
66487 
66488 /* ==========================================  SDIO TRANSFER CMDIDXCHKEN [20..20]  =========================================== */
66489 typedef enum {                                  /*!< SDIO_TRANSFER_CMDIDXCHKEN                                                 */
66490   SDIO_TRANSFER_CMDIDXCHKEN_DISABLE    = 0,     /*!< DISABLE : Disable                                                         */
66491   SDIO_TRANSFER_CMDIDXCHKEN_ENABLE     = 1,     /*!< ENABLE : Enable                                                           */
66492 } SDIO_TRANSFER_CMDIDXCHKEN_Enum;
66493 
66494 /* ==========================================  SDIO TRANSFER CMDCRCCHKEN [19..19]  =========================================== */
66495 typedef enum {                                  /*!< SDIO_TRANSFER_CMDCRCCHKEN                                                 */
66496   SDIO_TRANSFER_CMDCRCCHKEN_DISABLE    = 0,     /*!< DISABLE : Disable                                                         */
66497   SDIO_TRANSFER_CMDCRCCHKEN_ENABLE     = 1,     /*!< ENABLE : Enable                                                           */
66498 } SDIO_TRANSFER_CMDCRCCHKEN_Enum;
66499 
66500 /* ==========================================  SDIO TRANSFER RESPTYPESEL [16..17]  =========================================== */
66501 typedef enum {                                  /*!< SDIO_TRANSFER_RESPTYPESEL                                                 */
66502   SDIO_TRANSFER_RESPTYPESEL_NORESPONSE = 0,     /*!< NORESPONSE : No Response                                                  */
66503   SDIO_TRANSFER_RESPTYPESEL_LEN136     = 1,     /*!< LEN136 : Response length 136                                              */
66504   SDIO_TRANSFER_RESPTYPESEL_LEN48      = 2,     /*!< LEN48 : Response length 48                                                */
66505   SDIO_TRANSFER_RESPTYPESEL_LEN48CHKBUSY = 3,   /*!< LEN48CHKBUSY : Response length 48 check Busy after response               */
66506 } SDIO_TRANSFER_RESPTYPESEL_Enum;
66507 
66508 /* ==============================================  SDIO TRANSFER BLKSEL [5..5]  ============================================== */
66509 typedef enum {                                  /*!< SDIO_TRANSFER_BLKSEL                                                      */
66510   SDIO_TRANSFER_BLKSEL_SINGLEBLOCK     = 0,     /*!< SINGLEBLOCK : Single Block                                                */
66511   SDIO_TRANSFER_BLKSEL_MULTIPLEBLOCK   = 1,     /*!< MULTIPLEBLOCK : Multiple Block                                            */
66512 } SDIO_TRANSFER_BLKSEL_Enum;
66513 
66514 /* ===========================================  SDIO TRANSFER DXFERDIRSEL [4..4]  ============================================ */
66515 typedef enum {                                  /*!< SDIO_TRANSFER_DXFERDIRSEL                                                 */
66516   SDIO_TRANSFER_DXFERDIRSEL_WRITE      = 0,     /*!< WRITE : Write (Host to Card)                                              */
66517   SDIO_TRANSFER_DXFERDIRSEL_READ       = 1,     /*!< READ : Read (Card to Host)                                                */
66518 } SDIO_TRANSFER_DXFERDIRSEL_Enum;
66519 
66520 /* ==============================================  SDIO TRANSFER ACMDEN [2..3]  ============================================== */
66521 typedef enum {                                  /*!< SDIO_TRANSFER_ACMDEN                                                      */
66522   SDIO_TRANSFER_ACMDEN_DISABLED        = 0,     /*!< DISABLED : Auto Command Disabled                                          */
66523   SDIO_TRANSFER_ACMDEN_CMD12ENABLE     = 1,     /*!< CMD12ENABLE : Auto CMD12 Enable                                           */
66524   SDIO_TRANSFER_ACMDEN_CMD23ENABLE     = 2,     /*!< CMD23ENABLE : Auto CMD23 Enable                                           */
66525 } SDIO_TRANSFER_ACMDEN_Enum;
66526 
66527 /* =============================================  SDIO TRANSFER BLKCNTEN [1..1]  ============================================= */
66528 typedef enum {                                  /*!< SDIO_TRANSFER_BLKCNTEN                                                    */
66529   SDIO_TRANSFER_BLKCNTEN_DISABLE       = 0,     /*!< DISABLE : Disable                                                         */
66530   SDIO_TRANSFER_BLKCNTEN_ENABLE        = 1,     /*!< ENABLE : Enable                                                           */
66531 } SDIO_TRANSFER_BLKCNTEN_Enum;
66532 
66533 /* ==============================================  SDIO TRANSFER DMAEN [0..0]  =============================================== */
66534 typedef enum {                                  /*!< SDIO_TRANSFER_DMAEN                                                       */
66535   SDIO_TRANSFER_DMAEN_DISABLE          = 0,     /*!< DISABLE : Disable                                                         */
66536   SDIO_TRANSFER_DMAEN_ENABLE           = 1,     /*!< ENABLE : Enable                                                           */
66537 } SDIO_TRANSFER_DMAEN_Enum;
66538 
66539 /* =======================================================  RESPONSE0  ======================================================= */
66540 /* =======================================================  RESPONSE1  ======================================================= */
66541 /* =======================================================  RESPONSE2  ======================================================= */
66542 /* =======================================================  RESPONSE3  ======================================================= */
66543 /* ========================================================  BUFFER  ========================================================= */
66544 /* ========================================================  PRESENT  ======================================================== */
66545 /* ============================================  SDIO PRESENT DAT74LINE [25..28]  ============================================ */
66546 typedef enum {                                  /*!< SDIO_PRESENT_DAT74LINE                                                    */
66547   SDIO_PRESENT_DAT74LINE_DAT7          = 8,     /*!< DAT7 : DAT[7]                                                             */
66548   SDIO_PRESENT_DAT74LINE_DAT6          = 4,     /*!< DAT6 : DAT[6]                                                             */
66549   SDIO_PRESENT_DAT74LINE_DAT5          = 2,     /*!< DAT5 : DAT[5]                                                             */
66550   SDIO_PRESENT_DAT74LINE_DAT4          = 1,     /*!< DAT4 : DAT[4]                                                             */
66551 } SDIO_PRESENT_DAT74LINE_Enum;
66552 
66553 /* ============================================  SDIO PRESENT DAT30LINE [20..23]  ============================================ */
66554 typedef enum {                                  /*!< SDIO_PRESENT_DAT30LINE                                                    */
66555   SDIO_PRESENT_DAT30LINE_DAT3          = 8,     /*!< DAT3 : DAT[3]                                                             */
66556   SDIO_PRESENT_DAT30LINE_DAT2          = 4,     /*!< DAT2 : DAT[2]                                                             */
66557   SDIO_PRESENT_DAT30LINE_DAT1          = 2,     /*!< DAT1 : DAT[1]                                                             */
66558   SDIO_PRESENT_DAT30LINE_DAT0          = 1,     /*!< DAT0 : DAT[0]                                                             */
66559 } SDIO_PRESENT_DAT30LINE_Enum;
66560 
66561 /* ============================================  SDIO PRESENT WRPROTSW [19..19]  ============================================= */
66562 typedef enum {                                  /*!< SDIO_PRESENT_WRPROTSW                                                     */
66563   SDIO_PRESENT_WRPROTSW_WRITEPROTECTED = 0,     /*!< WRITEPROTECTED : Write protected (SDWP# = 0)                              */
66564   SDIO_PRESENT_WRPROTSW_WRITEENABLED   = 1,     /*!< WRITEENABLED : Write enabled (SDWP# = 1)                                  */
66565 } SDIO_PRESENT_WRPROTSW_Enum;
66566 
66567 /* =============================================  SDIO PRESENT CARDDET [18..18]  ============================================= */
66568 typedef enum {                                  /*!< SDIO_PRESENT_CARDDET                                                      */
66569   SDIO_PRESENT_CARDDET_NOCARDPRESENT   = 0,     /*!< NOCARDPRESENT : No Card present (SDCD# = 1)                               */
66570   SDIO_PRESENT_CARDDET_CARDPRESENT     = 1,     /*!< CARDPRESENT : Card present (SDCD# = 0)                                    */
66571 } SDIO_PRESENT_CARDDET_Enum;
66572 
66573 /* ===========================================  SDIO PRESENT CARDSTABLE [17..17]  ============================================ */
66574 typedef enum {                                  /*!< SDIO_PRESENT_CARDSTABLE                                                   */
66575   SDIO_PRESENT_CARDSTABLE_RESET_DEBOUNCING_NOCARD = 0,/*!< RESET_DEBOUNCING_NOCARD : Reset or Debouncing or No Card            */
66576   SDIO_PRESENT_CARDSTABLE_CARDINSERTED = 1,     /*!< CARDINSERTED : Card Inserted                                              */
66577 } SDIO_PRESENT_CARDSTABLE_Enum;
66578 
66579 /* ==========================================  SDIO PRESENT CARDINSERTED [16..16]  =========================================== */
66580 typedef enum {                                  /*!< SDIO_PRESENT_CARDINSERTED                                                 */
66581   SDIO_PRESENT_CARDINSERTED_RESET_DEBOUNCING_NOCARD = 0,/*!< RESET_DEBOUNCING_NOCARD : Reset or Debouncing or No Card          */
66582   SDIO_PRESENT_CARDINSERTED_CARDINSERTED = 1,   /*!< CARDINSERTED : Card Inserted                                              */
66583 } SDIO_PRESENT_CARDINSERTED_Enum;
66584 
66585 /* =============================================  SDIO PRESENT BUFRDEN [11..11]  ============================================= */
66586 typedef enum {                                  /*!< SDIO_PRESENT_BUFRDEN                                                      */
66587   SDIO_PRESENT_BUFRDEN_DISABLE         = 0,     /*!< DISABLE : Read Disable                                                    */
66588   SDIO_PRESENT_BUFRDEN_ENABLE          = 1,     /*!< ENABLE : Read Enable.                                                     */
66589 } SDIO_PRESENT_BUFRDEN_Enum;
66590 
66591 /* =============================================  SDIO PRESENT BUFWREN [10..10]  ============================================= */
66592 typedef enum {                                  /*!< SDIO_PRESENT_BUFWREN                                                      */
66593   SDIO_PRESENT_BUFWREN_DISABLE         = 0,     /*!< DISABLE : Write Disable                                                   */
66594   SDIO_PRESENT_BUFWREN_ENABLE          = 1,     /*!< ENABLE : Write Enable.                                                    */
66595 } SDIO_PRESENT_BUFWREN_Enum;
66596 
66597 /* =============================================  SDIO PRESENT RDXFERACT [9..9]  ============================================= */
66598 typedef enum {                                  /*!< SDIO_PRESENT_RDXFERACT                                                    */
66599   SDIO_PRESENT_RDXFERACT_TRANSFERRING  = 1,     /*!< TRANSFERRING : Transferring data                                          */
66600   SDIO_PRESENT_RDXFERACT_NOVALIDATA    = 0,     /*!< NOVALIDATA : No valid data                                                */
66601 } SDIO_PRESENT_RDXFERACT_Enum;
66602 
66603 /* =============================================  SDIO PRESENT WRXFERACT [8..8]  ============================================= */
66604 typedef enum {                                  /*!< SDIO_PRESENT_WRXFERACT                                                    */
66605   SDIO_PRESENT_WRXFERACT_TRANSFERRING  = 1,     /*!< TRANSFERRING : transferring data                                          */
66606   SDIO_PRESENT_WRXFERACT_NOVALIDDATA   = 0,     /*!< NOVALIDDATA : No valid data                                               */
66607 } SDIO_PRESENT_WRXFERACT_Enum;
66608 
66609 /* ==========================================  SDIO PRESENT RETUNINGREQUEST [3..3]  ========================================== */
66610 typedef enum {                                  /*!< SDIO_PRESENT_RETUNINGREQUEST                                              */
66611   SDIO_PRESENT_RETUNINGREQUEST_RETUNENEEDED = 1,/*!< RETUNENEEDED : Sampling clock needs re-tuning                             */
66612   SDIO_PRESENT_RETUNINGREQUEST_WELLTUNED = 0,   /*!< WELLTUNED : Fixed or well tuned sampling clock                            */
66613 } SDIO_PRESENT_RETUNINGREQUEST_Enum;
66614 
66615 /* =============================================  SDIO PRESENT DLINEACT [2..2]  ============================================== */
66616 typedef enum {                                  /*!< SDIO_PRESENT_DLINEACT                                                     */
66617   SDIO_PRESENT_DLINEACT_ACTIVE         = 1,     /*!< ACTIVE : DAT line active                                                  */
66618   SDIO_PRESENT_DLINEACT_INACTIVE       = 0,     /*!< INACTIVE : DAT line inactive                                              */
66619 } SDIO_PRESENT_DLINEACT_Enum;
66620 
66621 /* =============================================  SDIO PRESENT CMDINHDAT [1..1]  ============================================= */
66622 typedef enum {                                  /*!< SDIO_PRESENT_CMDINHDAT                                                    */
66623   SDIO_PRESENT_CMDINHDAT_DONTISSUE     = 1,     /*!< DONTISSUE : cannot issue command which uses the DAT line                  */
66624   SDIO_PRESENT_CMDINHDAT_ISSUE         = 0,     /*!< ISSUE : Can issue command which uses the DAT line                         */
66625 } SDIO_PRESENT_CMDINHDAT_Enum;
66626 
66627 /* =============================================  SDIO PRESENT CMDINHCMD [0..0]  ============================================= */
66628 typedef enum {                                  /*!< SDIO_PRESENT_CMDINHCMD                                                    */
66629   SDIO_PRESENT_CMDINHCMD_DONTISSUE     = 1,     /*!< DONTISSUE : CMD line is in use                                            */
66630   SDIO_PRESENT_CMDINHCMD_ISSUE         = 0,     /*!< ISSUE : Indicates that the CMD line is not in use and the HC
66631                                                      can issue a SD command using the CMD line.                                */
66632 } SDIO_PRESENT_CMDINHCMD_Enum;
66633 
66634 /* =======================================================  HOSTCTRL1  ======================================================= */
66635 /* ========================================  SDIO HOSTCTRL1 WUENCARDREMOVL [26..26]  ========================================= */
66636 typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDREMOVL                                             */
66637   SDIO_HOSTCTRL1_WUENCARDREMOVL_ENABLE = 1,     /*!< ENABLE : Enable                                                           */
66638   SDIO_HOSTCTRL1_WUENCARDREMOVL_DISABLE = 0,    /*!< DISABLE : Disable                                                         */
66639 } SDIO_HOSTCTRL1_WUENCARDREMOVL_Enum;
66640 
66641 /* ========================================  SDIO HOSTCTRL1 WUENCARDINSERT [25..25]  ========================================= */
66642 typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDINSERT                                             */
66643   SDIO_HOSTCTRL1_WUENCARDINSERT_ENABLE = 1,     /*!< ENABLE : Enable                                                           */
66644   SDIO_HOSTCTRL1_WUENCARDINSERT_DISABLE = 0,    /*!< DISABLE : Disable                                                         */
66645 } SDIO_HOSTCTRL1_WUENCARDINSERT_Enum;
66646 
66647 /* ==========================================  SDIO HOSTCTRL1 WUENCARDINT [24..24]  ========================================== */
66648 typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDINT                                                */
66649   SDIO_HOSTCTRL1_WUENCARDINT_ENABLE    = 1,     /*!< ENABLE : Enable                                                           */
66650   SDIO_HOSTCTRL1_WUENCARDINT_DISABLE   = 0,     /*!< DISABLE : Disable                                                         */
66651 } SDIO_HOSTCTRL1_WUENCARDINT_Enum;
66652 
66653 /* ==========================================  SDIO HOSTCTRL1 BOOTACKCHK [23..23]  =========================================== */
66654 typedef enum {                                  /*!< SDIO_HOSTCTRL1_BOOTACKCHK                                                 */
66655   SDIO_HOSTCTRL1_BOOTACKCHK_WAIT       = 1,     /*!< WAIT : wait for boot ack from eMMC card                                   */
66656   SDIO_HOSTCTRL1_BOOTACKCHK_NOWAIT     = 0,     /*!< NOWAIT : Will not wait for boot ack from eMMC card                        */
66657 } SDIO_HOSTCTRL1_BOOTACKCHK_Enum;
66658 
66659 /* ===========================================  SDIO HOSTCTRL1 ALTBOOTEN [22..22]  =========================================== */
66660 typedef enum {                                  /*!< SDIO_HOSTCTRL1_ALTBOOTEN                                                  */
66661   SDIO_HOSTCTRL1_ALTBOOTEN_START       = 1,     /*!< START : To start alternate boot mode access                               */
66662   SDIO_HOSTCTRL1_ALTBOOTEN_STOP        = 0,     /*!< STOP : To stop alternate boot mode access                                 */
66663 } SDIO_HOSTCTRL1_ALTBOOTEN_Enum;
66664 
66665 /* ============================================  SDIO HOSTCTRL1 BOOTEN [21..21]  ============================================= */
66666 typedef enum {                                  /*!< SDIO_HOSTCTRL1_BOOTEN                                                     */
66667   SDIO_HOSTCTRL1_BOOTEN_START          = 1,     /*!< START : To start boot code access                                         */
66668   SDIO_HOSTCTRL1_BOOTEN_STOP           = 0,     /*!< STOP : To stop boot code access                                           */
66669 } SDIO_HOSTCTRL1_BOOTEN_Enum;
66670 
66671 /* ============================================  SDIO HOSTCTRL1 SPIMODE [20..20]  ============================================ */
66672 typedef enum {                                  /*!< SDIO_HOSTCTRL1_SPIMODE                                                    */
66673   SDIO_HOSTCTRL1_SPIMODE_SPI           = 1,     /*!< SPI : SPI mode                                                            */
66674   SDIO_HOSTCTRL1_SPIMODE_SD            = 0,     /*!< SD : SD mode                                                              */
66675 } SDIO_HOSTCTRL1_SPIMODE_Enum;
66676 
66677 /* =========================================  SDIO HOSTCTRL1 READWAITCTRL [18..18]  ========================================== */
66678 typedef enum {                                  /*!< SDIO_HOSTCTRL1_READWAITCTRL                                               */
66679   SDIO_HOSTCTRL1_READWAITCTRL_ENABLE   = 1,     /*!< ENABLE : Enable Read Wait Control                                         */
66680   SDIO_HOSTCTRL1_READWAITCTRL_DISABLE  = 0,     /*!< DISABLE : Disable Read Wait Control                                       */
66681 } SDIO_HOSTCTRL1_READWAITCTRL_Enum;
66682 
66683 /* ============================================  SDIO HOSTCTRL1 CONTREQ [17..17]  ============================================ */
66684 typedef enum {                                  /*!< SDIO_HOSTCTRL1_CONTREQ                                                    */
66685   SDIO_HOSTCTRL1_CONTREQ_RESTART       = 1,     /*!< RESTART : Restart                                                         */
66686   SDIO_HOSTCTRL1_CONTREQ_IGNORED       = 0,     /*!< IGNORED : Ignored                                                         */
66687 } SDIO_HOSTCTRL1_CONTREQ_Enum;
66688 
66689 /* =====================================  SDIO HOSTCTRL1 STOPATBLOCKGAPREQUEST [16..16]  ===================================== */
66690 typedef enum {                                  /*!< SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST                                      */
66691   SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_STOP = 1,/*!< STOP : Stop                                                               */
66692   SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_TRANSFER = 0,/*!< TRANSFER : Transfer                                                   */
66693 } SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Enum;
66694 
66695 /* ============================================  SDIO HOSTCTRL1 HWRESET [12..12]  ============================================ */
66696 typedef enum {                                  /*!< SDIO_HOSTCTRL1_HWRESET                                                    */
66697   SDIO_HOSTCTRL1_HWRESET_ASSERT        = 1,     /*!< ASSERT : Drives the hardware reset pin as ZERO (Active LOW to
66698                                                      eMMC card)                                                                */
66699   SDIO_HOSTCTRL1_HWRESET_DEASSERT      = 0,     /*!< DEASSERT : Deassert the hardware reset pin                                */
66700 } SDIO_HOSTCTRL1_HWRESET_Enum;
66701 
66702 /* ===========================================  SDIO HOSTCTRL1 VOLTSELECT [9..11]  =========================================== */
66703 typedef enum {                                  /*!< SDIO_HOSTCTRL1_VOLTSELECT                                                 */
66704   SDIO_HOSTCTRL1_VOLTSELECT_3_3V       = 7,     /*!< 3_3V : 3.3 V(Typ.)                                                        */
66705   SDIO_HOSTCTRL1_VOLTSELECT_3_0V       = 6,     /*!< 3_0V : 3.0 V(Typ.)                                                        */
66706   SDIO_HOSTCTRL1_VOLTSELECT_1_8V       = 5,     /*!< 1_8V : 1.8 V(Typ.)                                                        */
66707 } SDIO_HOSTCTRL1_VOLTSELECT_Enum;
66708 
66709 /* ===========================================  SDIO HOSTCTRL1 SDBUSPOWER [8..8]  ============================================ */
66710 typedef enum {                                  /*!< SDIO_HOSTCTRL1_SDBUSPOWER                                                 */
66711   SDIO_HOSTCTRL1_SDBUSPOWER_POWERON    = 1,     /*!< POWERON : Power on                                                        */
66712   SDIO_HOSTCTRL1_SDBUSPOWER_POWEROFF   = 0,     /*!< POWEROFF : Power off                                                      */
66713 } SDIO_HOSTCTRL1_SDBUSPOWER_Enum;
66714 
66715 /* =============================================  SDIO HOSTCTRL1 CARDSRC [7..7]  ============================================= */
66716 typedef enum {                                  /*!< SDIO_HOSTCTRL1_CARDSRC                                                    */
66717   SDIO_HOSTCTRL1_CARDSRC_TEST          = 1,     /*!< TEST : The card detect test level is selected                             */
66718   SDIO_HOSTCTRL1_CARDSRC_SDCD          = 0,     /*!< SDCD : SDCD is selected (for normal use)                                  */
66719 } SDIO_HOSTCTRL1_CARDSRC_Enum;
66720 
66721 /* ============================================  SDIO HOSTCTRL1 TESTLEVEL [6..6]  ============================================ */
66722 typedef enum {                                  /*!< SDIO_HOSTCTRL1_TESTLEVEL                                                  */
66723   SDIO_HOSTCTRL1_TESTLEVEL_CARDINSERTED = 1,    /*!< CARDINSERTED : Card Inserted                                              */
66724   SDIO_HOSTCTRL1_TESTLEVEL_NOCARD      = 0,     /*!< NOCARD : No Card                                                          */
66725 } SDIO_HOSTCTRL1_TESTLEVEL_Enum;
66726 
66727 /* ============================================  SDIO HOSTCTRL1 XFERWIDTH [5..5]  ============================================ */
66728 typedef enum {                                  /*!< SDIO_HOSTCTRL1_XFERWIDTH                                                  */
66729   SDIO_HOSTCTRL1_XFERWIDTH_8BIT        = 1,     /*!< 8BIT : 8-bit Bus Width                                                    */
66730   SDIO_HOSTCTRL1_XFERWIDTH_XFER        = 0,     /*!< XFER : Bus Width is selected by Data Transfer Width                       */
66731 } SDIO_HOSTCTRL1_XFERWIDTH_Enum;
66732 
66733 /* ============================================  SDIO HOSTCTRL1 DMASELECT [3..4]  ============================================ */
66734 typedef enum {                                  /*!< SDIO_HOSTCTRL1_DMASELECT                                                  */
66735   SDIO_HOSTCTRL1_DMASELECT_SDMA        = 0,     /*!< SDMA : SDMA is selected                                                   */
66736   SDIO_HOSTCTRL1_DMASELECT_ADMA132     = 1,     /*!< ADMA132 : 32-bit Address ADMA1 is selected                                */
66737   SDIO_HOSTCTRL1_DMASELECT_ADMA232     = 2,     /*!< ADMA232 : 32-bit Address ADMA2 is selected                                */
66738   SDIO_HOSTCTRL1_DMASELECT_ADMA264     = 3,     /*!< ADMA264 : 64-bit Address ADMA2 is selected                                */
66739 } SDIO_HOSTCTRL1_DMASELECT_Enum;
66740 
66741 /* ============================================  SDIO HOSTCTRL1 HISPEEDEN [2..2]  ============================================ */
66742 typedef enum {                                  /*!< SDIO_HOSTCTRL1_HISPEEDEN                                                  */
66743   SDIO_HOSTCTRL1_HISPEEDEN_HIGH        = 1,     /*!< HIGH : High Speed Mode                                                    */
66744   SDIO_HOSTCTRL1_HISPEEDEN_NORMAL      = 0,     /*!< NORMAL : Normal Speed Mode                                                */
66745 } SDIO_HOSTCTRL1_HISPEEDEN_Enum;
66746 
66747 /* ========================================  SDIO HOSTCTRL1 DATATRANSFERWIDTH [1..1]  ======================================== */
66748 typedef enum {                                  /*!< SDIO_HOSTCTRL1_DATATRANSFERWIDTH                                          */
66749   SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD4 = 1,     /*!< SD4 : 4 bit mode                                                          */
66750   SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD1 = 0,     /*!< SD1 : 1 bit mode                                                          */
66751 } SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Enum;
66752 
66753 /* ===========================================  SDIO HOSTCTRL1 LEDCONTROL [0..0]  ============================================ */
66754 typedef enum {                                  /*!< SDIO_HOSTCTRL1_LEDCONTROL                                                 */
66755   SDIO_HOSTCTRL1_LEDCONTROL_ON         = 1,     /*!< ON : LED on                                                               */
66756   SDIO_HOSTCTRL1_LEDCONTROL_OFF        = 0,     /*!< OFF : LED off                                                             */
66757 } SDIO_HOSTCTRL1_LEDCONTROL_Enum;
66758 
66759 /* =======================================================  CLOCKCTRL  ======================================================= */
66760 /* ===========================================  SDIO CLOCKCTRL SWRSTDAT [26..26]  ============================================ */
66761 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTDAT                                                   */
66762   SDIO_CLOCKCTRL_SWRSTDAT_RESET        = 1,     /*!< RESET : Reset                                                             */
66763   SDIO_CLOCKCTRL_SWRSTDAT_WORK         = 0,     /*!< WORK : Work                                                               */
66764 } SDIO_CLOCKCTRL_SWRSTDAT_Enum;
66765 
66766 /* ===========================================  SDIO CLOCKCTRL SWRSTCMD [25..25]  ============================================ */
66767 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTCMD                                                   */
66768   SDIO_CLOCKCTRL_SWRSTCMD_RESET        = 1,     /*!< RESET : Reset                                                             */
66769   SDIO_CLOCKCTRL_SWRSTCMD_WORK         = 0,     /*!< WORK : Work                                                               */
66770 } SDIO_CLOCKCTRL_SWRSTCMD_Enum;
66771 
66772 /* ===========================================  SDIO CLOCKCTRL SWRSTALL [24..24]  ============================================ */
66773 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTALL                                                   */
66774   SDIO_CLOCKCTRL_SWRSTALL_RESET        = 1,     /*!< RESET : Reset                                                             */
66775   SDIO_CLOCKCTRL_SWRSTALL_WORK         = 0,     /*!< WORK : Work                                                               */
66776 } SDIO_CLOCKCTRL_SWRSTALL_Enum;
66777 
66778 /* ==========================================  SDIO CLOCKCTRL TIMEOUTCNT [16..19]  =========================================== */
66779 typedef enum {                                  /*!< SDIO_CLOCKCTRL_TIMEOUTCNT                                                 */
66780   SDIO_CLOCKCTRL_TIMEOUTCNT_27         = 14,    /*!< 27 : TMCLK * 2^27                                                         */
66781   SDIO_CLOCKCTRL_TIMEOUTCNT_26         = 0,     /*!< 26 : TMCLK * 2^26                                                         */
66782 } SDIO_CLOCKCTRL_TIMEOUTCNT_Enum;
66783 
66784 /* ============================================  SDIO CLOCKCTRL FREQSEL [8..15]  ============================================= */
66785 typedef enum {                                  /*!< SDIO_CLOCKCTRL_FREQSEL                                                    */
66786   SDIO_CLOCKCTRL_FREQSEL_DIV256        = 128,   /*!< DIV256 : base clock divided by 256                                        */
66787   SDIO_CLOCKCTRL_FREQSEL_DIV128        = 64,    /*!< DIV128 : base clock divided by 128                                        */
66788   SDIO_CLOCKCTRL_FREQSEL_DIV64         = 32,    /*!< DIV64 : base clock divided by 64                                          */
66789   SDIO_CLOCKCTRL_FREQSEL_DIV32         = 16,    /*!< DIV32 : base clock divided by 32                                          */
66790   SDIO_CLOCKCTRL_FREQSEL_DIV16         = 8,     /*!< DIV16 : base clock divided by 16                                          */
66791   SDIO_CLOCKCTRL_FREQSEL_DIV8          = 4,     /*!< DIV8 : base clock divided by 8                                            */
66792   SDIO_CLOCKCTRL_FREQSEL_DIV4          = 2,     /*!< DIV4 : base clock divided by 4                                            */
66793   SDIO_CLOCKCTRL_FREQSEL_DIV2          = 1,     /*!< DIV2 : base clock divided by 2                                            */
66794   SDIO_CLOCKCTRL_FREQSEL_BASECLK       = 0,     /*!< BASECLK : Base clock (10MHz - 63MHz)                                      */
66795 } SDIO_CLOCKCTRL_FREQSEL_Enum;
66796 
66797 /* ============================================  SDIO CLOCKCTRL CLKGENSEL [5..5]  ============================================ */
66798 typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKGENSEL                                                  */
66799   SDIO_CLOCKCTRL_CLKGENSEL_PROGCLK     = 1,     /*!< PROGCLK : Programmable Clock Mode                                         */
66800   SDIO_CLOCKCTRL_CLKGENSEL_DIVCLK      = 0,     /*!< DIVCLK : Divided Clock Mode                                               */
66801 } SDIO_CLOCKCTRL_CLKGENSEL_Enum;
66802 
66803 /* =============================================  SDIO CLOCKCTRL SDCLKEN [2..2]  ============================================= */
66804 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SDCLKEN                                                    */
66805   SDIO_CLOCKCTRL_SDCLKEN_ENABLE        = 1,     /*!< ENABLE : Enable                                                           */
66806   SDIO_CLOCKCTRL_SDCLKEN_DISABLE       = 0,     /*!< DISABLE : Disable                                                         */
66807 } SDIO_CLOCKCTRL_SDCLKEN_Enum;
66808 
66809 /* ============================================  SDIO CLOCKCTRL CLKSTABLE [1..1]  ============================================ */
66810 typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKSTABLE                                                  */
66811   SDIO_CLOCKCTRL_CLKSTABLE_READY       = 1,     /*!< READY : Ready                                                             */
66812   SDIO_CLOCKCTRL_CLKSTABLE_NOTREADY    = 0,     /*!< NOTREADY : Not Ready                                                      */
66813 } SDIO_CLOCKCTRL_CLKSTABLE_Enum;
66814 
66815 /* ==============================================  SDIO CLOCKCTRL CLKEN [0..0]  ============================================== */
66816 typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKEN                                                      */
66817   SDIO_CLOCKCTRL_CLKEN_OSC             = 1,     /*!< OSC : Oscillate                                                           */
66818   SDIO_CLOCKCTRL_CLKEN_STOP            = 0,     /*!< STOP : Stop                                                               */
66819 } SDIO_CLOCKCTRL_CLKEN_Enum;
66820 
66821 /* ========================================================  INTSTAT  ======================================================== */
66822 /* ===========================================  SDIO INTSTAT VNDERRSTAT [29..31]  ============================================ */
66823 typedef enum {                                  /*!< SDIO_INTSTAT_VNDERRSTAT                                                   */
66824   SDIO_INTSTAT_VNDERRSTAT_READY        = 1,     /*!< READY : Ready                                                             */
66825   SDIO_INTSTAT_VNDERRSTAT_NOTREADY     = 0,     /*!< NOTREADY : Not Ready                                                      */
66826 } SDIO_INTSTAT_VNDERRSTAT_Enum;
66827 
66828 /* ===========================================  SDIO INTSTAT TGTRESPERR [28..28]  ============================================ */
66829 typedef enum {                                  /*!< SDIO_INTSTAT_TGTRESPERR                                                   */
66830   SDIO_INTSTAT_TGTRESPERR_NOERROR      = 0,     /*!< NOERROR : no error                                                        */
66831   SDIO_INTSTAT_TGTRESPERR_ERROR        = 1,     /*!< ERROR : error                                                             */
66832 } SDIO_INTSTAT_TGTRESPERR_Enum;
66833 
66834 /* ============================================  SDIO INTSTAT ADMAERROR [25..25]  ============================================ */
66835 typedef enum {                                  /*!< SDIO_INTSTAT_ADMAERROR                                                    */
66836   SDIO_INTSTAT_ADMAERROR_ERROR         = 1,     /*!< ERROR : Error                                                             */
66837   SDIO_INTSTAT_ADMAERROR_NOERROR       = 0,     /*!< NOERROR : No error                                                        */
66838 } SDIO_INTSTAT_ADMAERROR_Enum;
66839 
66840 /* ==========================================  SDIO INTSTAT AUTOCMDERROR [24..24]  =========================================== */
66841 typedef enum {                                  /*!< SDIO_INTSTAT_AUTOCMDERROR                                                 */
66842   SDIO_INTSTAT_AUTOCMDERROR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
66843   SDIO_INTSTAT_AUTOCMDERROR_ERROR      = 1,     /*!< ERROR : Error                                                             */
66844 } SDIO_INTSTAT_AUTOCMDERROR_Enum;
66845 
66846 /* ========================================  SDIO INTSTAT CURRENTLIMITERROR [23..23]  ======================================== */
66847 typedef enum {                                  /*!< SDIO_INTSTAT_CURRENTLIMITERROR                                            */
66848   SDIO_INTSTAT_CURRENTLIMITERROR_NOERROR = 0,   /*!< NOERROR : No Error                                                        */
66849   SDIO_INTSTAT_CURRENTLIMITERROR_ERROR = 1,     /*!< ERROR : Power Fail                                                        */
66850 } SDIO_INTSTAT_CURRENTLIMITERROR_Enum;
66851 
66852 /* =========================================  SDIO INTSTAT DATAENDBITERROR [22..22]  ========================================= */
66853 typedef enum {                                  /*!< SDIO_INTSTAT_DATAENDBITERROR                                              */
66854   SDIO_INTSTAT_DATAENDBITERROR_NOERROR = 0,     /*!< NOERROR : No Error                                                        */
66855   SDIO_INTSTAT_DATAENDBITERROR_ERROR   = 1,     /*!< ERROR : Error                                                             */
66856 } SDIO_INTSTAT_DATAENDBITERROR_Enum;
66857 
66858 /* ==========================================  SDIO INTSTAT DATACRCERROR [21..21]  =========================================== */
66859 typedef enum {                                  /*!< SDIO_INTSTAT_DATACRCERROR                                                 */
66860   SDIO_INTSTAT_DATACRCERROR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
66861   SDIO_INTSTAT_DATACRCERROR_ERROR      = 1,     /*!< ERROR : Error                                                             */
66862 } SDIO_INTSTAT_DATACRCERROR_Enum;
66863 
66864 /* ========================================  SDIO INTSTAT DATATIMEOUTERROR [20..20]  ========================================= */
66865 typedef enum {                                  /*!< SDIO_INTSTAT_DATATIMEOUTERROR                                             */
66866   SDIO_INTSTAT_DATATIMEOUTERROR_NOERROR = 0,    /*!< NOERROR : No Error                                                        */
66867   SDIO_INTSTAT_DATATIMEOUTERROR_ERROR  = 1,     /*!< ERROR : Timeout                                                           */
66868 } SDIO_INTSTAT_DATATIMEOUTERROR_Enum;
66869 
66870 /* ========================================  SDIO INTSTAT COMMANDINDEXERROR [19..19]  ======================================== */
66871 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDINDEXERROR                                            */
66872   SDIO_INTSTAT_COMMANDINDEXERROR_NOERROR = 0,   /*!< NOERROR : No Error                                                        */
66873   SDIO_INTSTAT_COMMANDINDEXERROR_ERROR = 1,     /*!< ERROR : Error                                                             */
66874 } SDIO_INTSTAT_COMMANDINDEXERROR_Enum;
66875 
66876 /* =======================================  SDIO INTSTAT COMMANDENDBITERROR [18..18]  ======================================== */
66877 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDENDBITERROR                                           */
66878   SDIO_INTSTAT_COMMANDENDBITERROR_NOERROR = 0,  /*!< NOERROR : No Error                                                        */
66879   SDIO_INTSTAT_COMMANDENDBITERROR_ERROR = 1,    /*!< ERROR : Timeout                                                           */
66880 } SDIO_INTSTAT_COMMANDENDBITERROR_Enum;
66881 
66882 /* =========================================  SDIO INTSTAT COMMANDCRCERROR [17..17]  ========================================= */
66883 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDCRCERROR                                              */
66884   SDIO_INTSTAT_COMMANDCRCERROR_NOERROR = 0,     /*!< NOERROR : No Error                                                        */
66885   SDIO_INTSTAT_COMMANDCRCERROR_ERROR   = 1,     /*!< ERROR : End Bit Error Generated                                           */
66886 } SDIO_INTSTAT_COMMANDCRCERROR_Enum;
66887 
66888 /* =======================================  SDIO INTSTAT COMMANDTIMEOUTERROR [16..16]  ======================================= */
66889 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDTIMEOUTERROR                                          */
66890   SDIO_INTSTAT_COMMANDTIMEOUTERROR_NOERROR = 0, /*!< NOERROR : No Error                                                        */
66891   SDIO_INTSTAT_COMMANDTIMEOUTERROR_ERROR = 1,   /*!< ERROR : CRC Error Generated                                               */
66892 } SDIO_INTSTAT_COMMANDTIMEOUTERROR_Enum;
66893 
66894 /* =========================================  SDIO INTSTAT ERRORINTERRUPT [15..15]  ========================================== */
66895 typedef enum {                                  /*!< SDIO_INTSTAT_ERRORINTERRUPT                                               */
66896   SDIO_INTSTAT_ERRORINTERRUPT_NOERROR  = 0,     /*!< NOERROR : No Error.                                                       */
66897   SDIO_INTSTAT_ERRORINTERRUPT_ERROR    = 1,     /*!< ERROR : Error.                                                            */
66898 } SDIO_INTSTAT_ERRORINTERRUPT_Enum;
66899 
66900 /* ==========================================  SDIO INTSTAT BOOTTERMINATE [14..14]  ========================================== */
66901 typedef enum {                                  /*!< SDIO_INTSTAT_BOOTTERMINATE                                                */
66902   SDIO_INTSTAT_BOOTTERMINATE_OK        = 0,     /*!< OK : Boot operation is not terminated.                                    */
66903   SDIO_INTSTAT_BOOTTERMINATE_BOOTTERM  = 1,     /*!< BOOTTERM : Boot operation is terminated                                   */
66904 } SDIO_INTSTAT_BOOTTERMINATE_Enum;
66905 
66906 /* ===========================================  SDIO INTSTAT BOOTACKRCV [13..13]  ============================================ */
66907 typedef enum {                                  /*!< SDIO_INTSTAT_BOOTACKRCV                                                   */
66908   SDIO_INTSTAT_BOOTACKRCV_NOACK        = 0,     /*!< NOACK : Boot ack is not received.                                         */
66909   SDIO_INTSTAT_BOOTACKRCV_ACK          = 1,     /*!< ACK : Boot ack is received.                                               */
66910 } SDIO_INTSTAT_BOOTACKRCV_Enum;
66911 
66912 /* ==========================================  SDIO INTSTAT RETUNINGEVENT [12..12]  ========================================== */
66913 typedef enum {                                  /*!< SDIO_INTSTAT_RETUNINGEVENT                                                */
66914   SDIO_INTSTAT_RETUNINGEVENT_RETUNE    = 1,     /*!< RETUNE : ReTuning should be performed                                     */
66915   SDIO_INTSTAT_RETUNINGEVENT_NORETUNE  = 0,     /*!< NORETUNE : ReTuning is not required                                       */
66916 } SDIO_INTSTAT_RETUNINGEVENT_Enum;
66917 
66918 /* ===========================================  SDIO INTSTAT CARDINTERRUPT [8..8]  =========================================== */
66919 typedef enum {                                  /*!< SDIO_INTSTAT_CARDINTERRUPT                                                */
66920   SDIO_INTSTAT_CARDINTERRUPT_NOINT     = 0,     /*!< NOINT : No Card Interrupt                                                 */
66921   SDIO_INTSTAT_CARDINTERRUPT_INT       = 1,     /*!< INT : Generate Card Interrupt                                             */
66922 } SDIO_INTSTAT_CARDINTERRUPT_Enum;
66923 
66924 /* ============================================  SDIO INTSTAT CARDREMOVAL [7..7]  ============================================ */
66925 typedef enum {                                  /*!< SDIO_INTSTAT_CARDREMOVAL                                                  */
66926   SDIO_INTSTAT_CARDREMOVAL_STABLE      = 0,     /*!< STABLE : Card State Stable or Debouncing                                  */
66927   SDIO_INTSTAT_CARDREMOVAL_REMOVED     = 1,     /*!< REMOVED : Card Removed                                                    */
66928 } SDIO_INTSTAT_CARDREMOVAL_Enum;
66929 
66930 /* ===========================================  SDIO INTSTAT CARDINSERTION [6..6]  =========================================== */
66931 typedef enum {                                  /*!< SDIO_INTSTAT_CARDINSERTION                                                */
66932   SDIO_INTSTAT_CARDINSERTION_STABLE    = 0,     /*!< STABLE : Card State Stable or Debouncing                                  */
66933   SDIO_INTSTAT_CARDINSERTION_INSERTED  = 1,     /*!< INSERTED : Card Inserted                                                  */
66934 } SDIO_INTSTAT_CARDINSERTION_Enum;
66935 
66936 /* ==========================================  SDIO INTSTAT BUFFERREADREADY [5..5]  ========================================== */
66937 typedef enum {                                  /*!< SDIO_INTSTAT_BUFFERREADREADY                                              */
66938   SDIO_INTSTAT_BUFFERREADREADY_NOREADY = 0,     /*!< NOREADY : Not Ready to read Buffer.                                       */
66939   SDIO_INTSTAT_BUFFERREADREADY_READY   = 1,     /*!< READY : Ready to read Buffer.                                             */
66940 } SDIO_INTSTAT_BUFFERREADREADY_Enum;
66941 
66942 /* =========================================  SDIO INTSTAT BUFFERWRITEREADY [4..4]  ========================================== */
66943 typedef enum {                                  /*!< SDIO_INTSTAT_BUFFERWRITEREADY                                             */
66944   SDIO_INTSTAT_BUFFERWRITEREADY_NOTREADY = 0,   /*!< NOTREADY : Not Ready to Write Buffer.                                     */
66945   SDIO_INTSTAT_BUFFERWRITEREADY_READY  = 1,     /*!< READY : Ready to Write Buffer.                                            */
66946 } SDIO_INTSTAT_BUFFERWRITEREADY_Enum;
66947 
66948 /* ===========================================  SDIO INTSTAT DMAINTERRUPT [3..3]  ============================================ */
66949 typedef enum {                                  /*!< SDIO_INTSTAT_DMAINTERRUPT                                                 */
66950   SDIO_INTSTAT_DMAINTERRUPT_NOINT      = 0,     /*!< NOINT : No DMA Interrupt                                                  */
66951   SDIO_INTSTAT_DMAINTERRUPT_INT        = 1,     /*!< INT : DMA Interrupt is Generated                                          */
66952 } SDIO_INTSTAT_DMAINTERRUPT_Enum;
66953 
66954 /* ===========================================  SDIO INTSTAT BLOCKGAPEVENT [2..2]  =========================================== */
66955 typedef enum {                                  /*!< SDIO_INTSTAT_BLOCKGAPEVENT                                                */
66956   SDIO_INTSTAT_BLOCKGAPEVENT_NOEVENT   = 0,     /*!< NOEVENT : No Block Gap Event                                              */
66957   SDIO_INTSTAT_BLOCKGAPEVENT_STOPPED   = 1,     /*!< STOPPED : Transaction stopped at Block Gap                                */
66958 } SDIO_INTSTAT_BLOCKGAPEVENT_Enum;
66959 
66960 /* =========================================  SDIO INTSTAT TRANSFERCOMPLETE [1..1]  ========================================== */
66961 typedef enum {                                  /*!< SDIO_INTSTAT_TRANSFERCOMPLETE                                             */
66962   SDIO_INTSTAT_TRANSFERCOMPLETE_NODATA = 0,     /*!< NODATA : No Data Transfer Complete                                        */
66963   SDIO_INTSTAT_TRANSFERCOMPLETE_COMPLETE = 1,   /*!< COMPLETE : Data Transfer Complete                                         */
66964 } SDIO_INTSTAT_TRANSFERCOMPLETE_Enum;
66965 
66966 /* ==========================================  SDIO INTSTAT COMMANDCOMPLETE [0..0]  ========================================== */
66967 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDCOMPLETE                                              */
66968   SDIO_INTSTAT_COMMANDCOMPLETE_NOCMP   = 0,     /*!< NOCMP : No Command Complete                                               */
66969   SDIO_INTSTAT_COMMANDCOMPLETE_CMDCMP  = 1,     /*!< CMDCMP : Command Complete                                                 */
66970 } SDIO_INTSTAT_COMMANDCOMPLETE_Enum;
66971 
66972 /* =======================================================  INTENABLE  ======================================================= */
66973 /* ========================================================  INTSIG  ========================================================= */
66974 /* ============================================  SDIO INTSIG TGTRESPEN [28..28]  ============================================= */
66975 typedef enum {                                  /*!< SDIO_INTSIG_TGTRESPEN                                                     */
66976   SDIO_INTSIG_TGTRESPEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
66977   SDIO_INTSIG_TGTRESPEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
66978 } SDIO_INTSIG_TGTRESPEN_Enum;
66979 
66980 /* ===========================================  SDIO INTSIG TUNINGERREN [26..26]  ============================================ */
66981 typedef enum {                                  /*!< SDIO_INTSIG_TUNINGERREN                                                   */
66982   SDIO_INTSIG_TUNINGERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
66983   SDIO_INTSIG_TUNINGERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
66984 } SDIO_INTSIG_TUNINGERREN_Enum;
66985 
66986 /* ============================================  SDIO INTSIG ADMAERREN [25..25]  ============================================= */
66987 typedef enum {                                  /*!< SDIO_INTSIG_ADMAERREN                                                     */
66988   SDIO_INTSIG_ADMAERREN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
66989   SDIO_INTSIG_ADMAERREN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
66990 } SDIO_INTSIG_ADMAERREN_Enum;
66991 
66992 /* ==========================================  SDIO INTSIG AUTOCMD12ERREN [24..24]  ========================================== */
66993 typedef enum {                                  /*!< SDIO_INTSIG_AUTOCMD12ERREN                                                */
66994   SDIO_INTSIG_AUTOCMD12ERREN_MASKED    = 0,     /*!< MASKED : Masked                                                           */
66995   SDIO_INTSIG_AUTOCMD12ERREN_ENABLED   = 1,     /*!< ENABLED : Enabled                                                         */
66996 } SDIO_INTSIG_AUTOCMD12ERREN_Enum;
66997 
66998 /* ===========================================  SDIO INTSIG CURRLMTERREN [23..23]  =========================================== */
66999 typedef enum {                                  /*!< SDIO_INTSIG_CURRLMTERREN                                                  */
67000   SDIO_INTSIG_CURRLMTERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
67001   SDIO_INTSIG_CURRLMTERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
67002 } SDIO_INTSIG_CURRLMTERREN_Enum;
67003 
67004 /* ===========================================  SDIO INTSIG DATAENDERREN [22..22]  =========================================== */
67005 typedef enum {                                  /*!< SDIO_INTSIG_DATAENDERREN                                                  */
67006   SDIO_INTSIG_DATAENDERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
67007   SDIO_INTSIG_DATAENDERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
67008 } SDIO_INTSIG_DATAENDERREN_Enum;
67009 
67010 /* ===========================================  SDIO INTSIG DATACRCERREN [21..21]  =========================================== */
67011 typedef enum {                                  /*!< SDIO_INTSIG_DATACRCERREN                                                  */
67012   SDIO_INTSIG_DATACRCERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
67013   SDIO_INTSIG_DATACRCERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
67014 } SDIO_INTSIG_DATACRCERREN_Enum;
67015 
67016 /* ==========================================  SDIO INTSIG DATATOERROREN [20..20]  =========================================== */
67017 typedef enum {                                  /*!< SDIO_INTSIG_DATATOERROREN                                                 */
67018   SDIO_INTSIG_DATATOERROREN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
67019   SDIO_INTSIG_DATATOERROREN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
67020 } SDIO_INTSIG_DATATOERROREN_Enum;
67021 
67022 /* ===========================================  SDIO INTSIG CMDIDXERREN [19..19]  ============================================ */
67023 typedef enum {                                  /*!< SDIO_INTSIG_CMDIDXERREN                                                   */
67024   SDIO_INTSIG_CMDIDXERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
67025   SDIO_INTSIG_CMDIDXERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
67026 } SDIO_INTSIG_CMDIDXERREN_Enum;
67027 
67028 /* ==========================================  SDIO INTSIG CMDENDBITERREN [18..18]  ========================================== */
67029 typedef enum {                                  /*!< SDIO_INTSIG_CMDENDBITERREN                                                */
67030   SDIO_INTSIG_CMDENDBITERREN_MASKED    = 0,     /*!< MASKED : Masked                                                           */
67031   SDIO_INTSIG_CMDENDBITERREN_ENABLED   = 1,     /*!< ENABLED : Enabled                                                         */
67032 } SDIO_INTSIG_CMDENDBITERREN_Enum;
67033 
67034 /* ===========================================  SDIO INTSIG CMDCRCERREN [17..17]  ============================================ */
67035 typedef enum {                                  /*!< SDIO_INTSIG_CMDCRCERREN                                                   */
67036   SDIO_INTSIG_CMDCRCERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
67037   SDIO_INTSIG_CMDCRCERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
67038 } SDIO_INTSIG_CMDCRCERREN_Enum;
67039 
67040 /* ============================================  SDIO INTSIG CMDTOERREN [16..16]  ============================================ */
67041 typedef enum {                                  /*!< SDIO_INTSIG_CMDTOERREN                                                    */
67042   SDIO_INTSIG_CMDTOERREN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
67043   SDIO_INTSIG_CMDTOERREN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
67044 } SDIO_INTSIG_CMDTOERREN_Enum;
67045 
67046 /* ==============================================  SDIO INTSIG FIXED0 [15..15]  ============================================== */
67047 typedef enum {                                  /*!< SDIO_INTSIG_FIXED0                                                        */
67048   SDIO_INTSIG_FIXED0_MASKED            = 0,     /*!< MASKED : Masked                                                           */
67049   SDIO_INTSIG_FIXED0_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
67050 } SDIO_INTSIG_FIXED0_Enum;
67051 
67052 /* =============================================  SDIO INTSIG BOOTTERM [14..14]  ============================================= */
67053 typedef enum {                                  /*!< SDIO_INTSIG_BOOTTERM                                                      */
67054   SDIO_INTSIG_BOOTTERM_MASKED          = 0,     /*!< MASKED : Masked                                                           */
67055   SDIO_INTSIG_BOOTTERM_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
67056 } SDIO_INTSIG_BOOTTERM_Enum;
67057 
67058 /* ============================================  SDIO INTSIG BOOTACKEN [13..13]  ============================================= */
67059 typedef enum {                                  /*!< SDIO_INTSIG_BOOTACKEN                                                     */
67060   SDIO_INTSIG_BOOTACKEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
67061   SDIO_INTSIG_BOOTACKEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
67062 } SDIO_INTSIG_BOOTACKEN_Enum;
67063 
67064 /* ==========================================  SDIO INTSIG RETUNEEVENTEN [12..12]  =========================================== */
67065 typedef enum {                                  /*!< SDIO_INTSIG_RETUNEEVENTEN                                                 */
67066   SDIO_INTSIG_RETUNEEVENTEN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
67067   SDIO_INTSIG_RETUNEEVENTEN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
67068 } SDIO_INTSIG_RETUNEEVENTEN_Enum;
67069 
67070 /* ==============================================  SDIO INTSIG INTCEN [11..11]  ============================================== */
67071 typedef enum {                                  /*!< SDIO_INTSIG_INTCEN                                                        */
67072   SDIO_INTSIG_INTCEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
67073   SDIO_INTSIG_INTCEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
67074 } SDIO_INTSIG_INTCEN_Enum;
67075 
67076 /* ==============================================  SDIO INTSIG INTBEN [10..10]  ============================================== */
67077 typedef enum {                                  /*!< SDIO_INTSIG_INTBEN                                                        */
67078   SDIO_INTSIG_INTBEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
67079   SDIO_INTSIG_INTBEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
67080 } SDIO_INTSIG_INTBEN_Enum;
67081 
67082 /* ===============================================  SDIO INTSIG INTAEN [9..9]  =============================================== */
67083 typedef enum {                                  /*!< SDIO_INTSIG_INTAEN                                                        */
67084   SDIO_INTSIG_INTAEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
67085   SDIO_INTSIG_INTAEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
67086 } SDIO_INTSIG_INTAEN_Enum;
67087 
67088 /* =============================================  SDIO INTSIG CARDINTEN [8..8]  ============================================== */
67089 typedef enum {                                  /*!< SDIO_INTSIG_CARDINTEN                                                     */
67090   SDIO_INTSIG_CARDINTEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
67091   SDIO_INTSIG_CARDINTEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
67092 } SDIO_INTSIG_CARDINTEN_Enum;
67093 
67094 /* ===========================================  SDIO INTSIG CARDREMOVALEN [7..7]  ============================================ */
67095 typedef enum {                                  /*!< SDIO_INTSIG_CARDREMOVALEN                                                 */
67096   SDIO_INTSIG_CARDREMOVALEN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
67097   SDIO_INTSIG_CARDREMOVALEN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
67098 } SDIO_INTSIG_CARDREMOVALEN_Enum;
67099 
67100 /* ============================================  SDIO INTSIG CARDINSERTEN [6..6]  ============================================ */
67101 typedef enum {                                  /*!< SDIO_INTSIG_CARDINSERTEN                                                  */
67102   SDIO_INTSIG_CARDINSERTEN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
67103   SDIO_INTSIG_CARDINSERTEN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
67104 } SDIO_INTSIG_CARDINSERTEN_Enum;
67105 
67106 /* =============================================  SDIO INTSIG BUFFERRDEN [5..5]  ============================================= */
67107 typedef enum {                                  /*!< SDIO_INTSIG_BUFFERRDEN                                                    */
67108   SDIO_INTSIG_BUFFERRDEN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
67109   SDIO_INTSIG_BUFFERRDEN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
67110 } SDIO_INTSIG_BUFFERRDEN_Enum;
67111 
67112 /* =============================================  SDIO INTSIG BUFFERWREN [4..4]  ============================================= */
67113 typedef enum {                                  /*!< SDIO_INTSIG_BUFFERWREN                                                    */
67114   SDIO_INTSIG_BUFFERWREN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
67115   SDIO_INTSIG_BUFFERWREN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
67116 } SDIO_INTSIG_BUFFERWREN_Enum;
67117 
67118 /* ==============================================  SDIO INTSIG DMAINTEN [3..3]  ============================================== */
67119 typedef enum {                                  /*!< SDIO_INTSIG_DMAINTEN                                                      */
67120   SDIO_INTSIG_DMAINTEN_MASKED          = 0,     /*!< MASKED : Masked                                                           */
67121   SDIO_INTSIG_DMAINTEN_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
67122 } SDIO_INTSIG_DMAINTEN_Enum;
67123 
67124 /* =============================================  SDIO INTSIG BLOCKGAPEN [2..2]  ============================================= */
67125 typedef enum {                                  /*!< SDIO_INTSIG_BLOCKGAPEN                                                    */
67126   SDIO_INTSIG_BLOCKGAPEN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
67127   SDIO_INTSIG_BLOCKGAPEN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
67128 } SDIO_INTSIG_BLOCKGAPEN_Enum;
67129 
67130 /* =============================================  SDIO INTSIG XFERCMPEN [1..1]  ============================================== */
67131 typedef enum {                                  /*!< SDIO_INTSIG_XFERCMPEN                                                     */
67132   SDIO_INTSIG_XFERCMPEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
67133   SDIO_INTSIG_XFERCMPEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
67134 } SDIO_INTSIG_XFERCMPEN_Enum;
67135 
67136 /* ==============================================  SDIO INTSIG CMDCMPEN [0..0]  ============================================== */
67137 typedef enum {                                  /*!< SDIO_INTSIG_CMDCMPEN                                                      */
67138   SDIO_INTSIG_CMDCMPEN_MASKED          = 0,     /*!< MASKED : Masked                                                           */
67139   SDIO_INTSIG_CMDCMPEN_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
67140 } SDIO_INTSIG_CMDCMPEN_Enum;
67141 
67142 /* =========================================================  AUTO  ========================================================== */
67143 /* ==============================================  SDIO AUTO PRESETEN [31..31]  ============================================== */
67144 typedef enum {                                  /*!< SDIO_AUTO_PRESETEN                                                        */
67145   SDIO_AUTO_PRESETEN_AUTOEN            = 1,     /*!< AUTOEN : Automatic Selection by Preset Value are Enabled                  */
67146   SDIO_AUTO_PRESETEN_HOSTCTRL          = 0,     /*!< HOSTCTRL : SDCLK and Driver Strength are controlled by Host
67147                                                      Driver                                                                    */
67148 } SDIO_AUTO_PRESETEN_Enum;
67149 
67150 /* =============================================  SDIO AUTO ASYNCINTEN [30..30]  ============================================= */
67151 typedef enum {                                  /*!< SDIO_AUTO_ASYNCINTEN                                                      */
67152   SDIO_AUTO_ASYNCINTEN_ENABLED         = 1,     /*!< ENABLED : Enabled,                                                        */
67153   SDIO_AUTO_ASYNCINTEN_DISABLED        = 0,     /*!< DISABLED : Disabled                                                       */
67154 } SDIO_AUTO_ASYNCINTEN_Enum;
67155 
67156 /* ============================================  SDIO AUTO SAMPLCLKSEL [23..23]  ============================================= */
67157 typedef enum {                                  /*!< SDIO_AUTO_SAMPLCLKSEL                                                     */
67158   SDIO_AUTO_SAMPLCLKSEL_TUNEDCLK       = 1,     /*!< TUNEDCLK : Tuned clock is used to sample data                             */
67159   SDIO_AUTO_SAMPLCLKSEL_FIXEDCLK       = 0,     /*!< FIXEDCLK : Fixed clock is used to sample data                             */
67160 } SDIO_AUTO_SAMPLCLKSEL_Enum;
67161 
67162 /* ============================================  SDIO AUTO STARTTUNING [22..22]  ============================================= */
67163 typedef enum {                                  /*!< SDIO_AUTO_STARTTUNING                                                     */
67164   SDIO_AUTO_STARTTUNING_TUNESTART      = 1,     /*!< TUNESTART : Execute Tuning,                                               */
67165   SDIO_AUTO_STARTTUNING_TUNECMP        = 0,     /*!< TUNECMP : Not Tuned or Tuning Completed                                   */
67166 } SDIO_AUTO_STARTTUNING_Enum;
67167 
67168 /* =============================================  SDIO AUTO DRVRSTRSEL [20..21]  ============================================= */
67169 typedef enum {                                  /*!< SDIO_AUTO_DRVRSTRSEL                                                      */
67170   SDIO_AUTO_DRVRSTRSEL_DRVRB           = 0,     /*!< DRVRB : Driver Type B is Selected (Default)                               */
67171   SDIO_AUTO_DRVRSTRSEL_DRVRA           = 1,     /*!< DRVRA : Driver Type A is Selected                                         */
67172   SDIO_AUTO_DRVRSTRSEL_DRVRC           = 2,     /*!< DRVRC : Driver Type C is Selected                                         */
67173   SDIO_AUTO_DRVRSTRSEL_DRVRD           = 3,     /*!< DRVRD : Driver Type D is Selected                                         */
67174 } SDIO_AUTO_DRVRSTRSEL_Enum;
67175 
67176 /* =============================================  SDIO AUTO SIGNALVOLT [19..19]  ============================================= */
67177 typedef enum {                                  /*!< SDIO_AUTO_SIGNALVOLT                                                      */
67178   SDIO_AUTO_SIGNALVOLT_1_8V            = 1,     /*!< 1_8V : 1.8V Signaling                                                     */
67179   SDIO_AUTO_SIGNALVOLT_3_3V            = 0,     /*!< 3_3V : 3.3V Signaling                                                     */
67180 } SDIO_AUTO_SIGNALVOLT_Enum;
67181 
67182 /* =============================================  SDIO AUTO UHSMODESEL [16..18]  ============================================= */
67183 typedef enum {                                  /*!< SDIO_AUTO_UHSMODESEL                                                      */
67184   SDIO_AUTO_UHSMODESEL_SDR12           = 0,     /*!< SDR12 : UHS-I mode SDR12                                                  */
67185   SDIO_AUTO_UHSMODESEL_SDR25           = 1,     /*!< SDR25 : UHS-I mode SDR25                                                  */
67186   SDIO_AUTO_UHSMODESEL_SDR50           = 2,     /*!< SDR50 : UHS-I mode SDR50                                                  */
67187   SDIO_AUTO_UHSMODESEL_SDR104          = 3,     /*!< SDR104 : UHS-I mode SDR104                                                */
67188   SDIO_AUTO_UHSMODESEL_DDR50           = 4,     /*!< DDR50 : UHS-I mode DDR50                                                  */
67189 } SDIO_AUTO_UHSMODESEL_Enum;
67190 
67191 /* ===========================================  SDIO AUTO NOTAUTOCMD12ERR [7..7]  ============================================ */
67192 typedef enum {                                  /*!< SDIO_AUTO_NOTAUTOCMD12ERR                                                 */
67193   SDIO_AUTO_NOTAUTOCMD12ERR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
67194   SDIO_AUTO_NOTAUTOCMD12ERR_ERROR      = 1,     /*!< ERROR : Not Issued                                                        */
67195 } SDIO_AUTO_NOTAUTOCMD12ERR_Enum;
67196 
67197 /* ==============================================  SDIO AUTO CMDIDXERR [4..4]  =============================================== */
67198 typedef enum {                                  /*!< SDIO_AUTO_CMDIDXERR                                                       */
67199   SDIO_AUTO_CMDIDXERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
67200   SDIO_AUTO_CMDIDXERR_ERROR            = 1,     /*!< ERROR : Error                                                             */
67201 } SDIO_AUTO_CMDIDXERR_Enum;
67202 
67203 /* ==============================================  SDIO AUTO CMDENDERR [3..3]  =============================================== */
67204 typedef enum {                                  /*!< SDIO_AUTO_CMDENDERR                                                       */
67205   SDIO_AUTO_CMDENDERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
67206   SDIO_AUTO_CMDENDERR_ERROR            = 1,     /*!< ERROR : End Bit Error Generated                                           */
67207 } SDIO_AUTO_CMDENDERR_Enum;
67208 
67209 /* ==============================================  SDIO AUTO CMDCRCERR [2..2]  =============================================== */
67210 typedef enum {                                  /*!< SDIO_AUTO_CMDCRCERR                                                       */
67211   SDIO_AUTO_CMDCRCERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
67212   SDIO_AUTO_CMDCRCERR_ERROR            = 1,     /*!< ERROR : CRC Error Generated                                               */
67213 } SDIO_AUTO_CMDCRCERR_Enum;
67214 
67215 /* ===============================================  SDIO AUTO CMDTOERR [1..1]  =============================================== */
67216 typedef enum {                                  /*!< SDIO_AUTO_CMDTOERR                                                        */
67217   SDIO_AUTO_CMDTOERR_NOERROR           = 0,     /*!< NOERROR : No Error                                                        */
67218   SDIO_AUTO_CMDTOERR_ERROR             = 1,     /*!< ERROR : Timeout                                                           */
67219 } SDIO_AUTO_CMDTOERR_Enum;
67220 
67221 /* =============================================  SDIO AUTO CMD12NOTEXEC [0..0]  ============================================= */
67222 typedef enum {                                  /*!< SDIO_AUTO_CMD12NOTEXEC                                                    */
67223   SDIO_AUTO_CMD12NOTEXEC_EXECUTED      = 0,     /*!< EXECUTED : Executed                                                       */
67224   SDIO_AUTO_CMD12NOTEXEC_NOTEXECUTED   = 1,     /*!< NOTEXECUTED : Not Executed                                                */
67225 } SDIO_AUTO_CMD12NOTEXEC_Enum;
67226 
67227 /* =====================================================  CAPABILITIES0  ===================================================== */
67228 /* =========================================  SDIO CAPABILITIES0 SLOTTYPE [30..31]  ========================================== */
67229 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SLOTTYPE                                               */
67230   SDIO_CAPABILITIES0_SLOTTYPE_REMOVABLE = 0,    /*!< REMOVABLE : Removable card slot                                           */
67231   SDIO_CAPABILITIES0_SLOTTYPE_EMBEDDED = 1,     /*!< EMBEDDED : Embedded Slot for One Device                                   */
67232   SDIO_CAPABILITIES0_SLOTTYPE_SHARED   = 2,     /*!< SHARED : Shared Bus Slot                                                  */
67233 } SDIO_CAPABILITIES0_SLOTTYPE_Enum;
67234 
67235 /* =========================================  SDIO CAPABILITIES0 ASYNCINT [29..29]  ========================================== */
67236 typedef enum {                                  /*!< SDIO_CAPABILITIES0_ASYNCINT                                               */
67237   SDIO_CAPABILITIES0_ASYNCINT_SUPPORTED = 1,    /*!< SUPPORTED : Asynchronous Interrupt Supported                              */
67238   SDIO_CAPABILITIES0_ASYNCINT_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Asynchronous Interrupt Not Supported                       */
67239 } SDIO_CAPABILITIES0_ASYNCINT_Enum;
67240 
67241 /* =========================================  SDIO CAPABILITIES0 SYSBUS64 [28..28]  ========================================== */
67242 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SYSBUS64                                               */
67243   SDIO_CAPABILITIES0_SYSBUS64_SUPPORTED = 1,    /*!< SUPPORTED : Supports 64 bit system address                                */
67244   SDIO_CAPABILITIES0_SYSBUS64_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Does not support 64 bit system address                     */
67245 } SDIO_CAPABILITIES0_SYSBUS64_Enum;
67246 
67247 /* ==========================================  SDIO CAPABILITIES0 VOLT18V [26..26]  ========================================== */
67248 typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT18V                                                */
67249   SDIO_CAPABILITIES0_VOLT18V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 1.8 V Not Supported                                        */
67250   SDIO_CAPABILITIES0_VOLT18V_SUPPORTED = 1,     /*!< SUPPORTED : 1.8 V Supported                                               */
67251 } SDIO_CAPABILITIES0_VOLT18V_Enum;
67252 
67253 /* ==========================================  SDIO CAPABILITIES0 VOLT30V [25..25]  ========================================== */
67254 typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT30V                                                */
67255   SDIO_CAPABILITIES0_VOLT30V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 3.0 V Not Supported                                        */
67256   SDIO_CAPABILITIES0_VOLT30V_SUPPORTED = 1,     /*!< SUPPORTED : 3.0 V Supported                                               */
67257 } SDIO_CAPABILITIES0_VOLT30V_Enum;
67258 
67259 /* ==========================================  SDIO CAPABILITIES0 VOLT33V [24..24]  ========================================== */
67260 typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT33V                                                */
67261   SDIO_CAPABILITIES0_VOLT33V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 3.3 V Not Supported                                        */
67262   SDIO_CAPABILITIES0_VOLT33V_SUPPORTED = 1,     /*!< SUPPORTED : 3.3 V Supported                                               */
67263 } SDIO_CAPABILITIES0_VOLT33V_Enum;
67264 
67265 /* ==========================================  SDIO CAPABILITIES0 SUSPRES [23..23]  ========================================== */
67266 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SUSPRES                                                */
67267   SDIO_CAPABILITIES0_SUSPRES_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Suspend / Resume Not Supported                             */
67268   SDIO_CAPABILITIES0_SUSPRES_SUPPORTED = 1,     /*!< SUPPORTED : Suspend / Resume Supported                                    */
67269 } SDIO_CAPABILITIES0_SUSPRES_Enum;
67270 
67271 /* ===========================================  SDIO CAPABILITIES0 SDMA [22..22]  ============================================ */
67272 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SDMA                                                   */
67273   SDIO_CAPABILITIES0_SDMA_NOTSUPPORTED = 0,     /*!< NOTSUPPORTED : SDMA Not Supported                                         */
67274   SDIO_CAPABILITIES0_SDMA_SUPPORTED    = 1,     /*!< SUPPORTED : SDMA Supported.                                               */
67275 } SDIO_CAPABILITIES0_SDMA_Enum;
67276 
67277 /* =========================================  SDIO CAPABILITIES0 HIGHSPEED [21..21]  ========================================= */
67278 typedef enum {                                  /*!< SDIO_CAPABILITIES0_HIGHSPEED                                              */
67279   SDIO_CAPABILITIES0_HIGHSPEED_NOTSUPPORTED = 0,/*!< NOTSUPPORTED : High Speed Not Supported                                   */
67280   SDIO_CAPABILITIES0_HIGHSPEED_SUPPORTED = 1,   /*!< SUPPORTED : High Speed Supported                                          */
67281 } SDIO_CAPABILITIES0_HIGHSPEED_Enum;
67282 
67283 /* ===========================================  SDIO CAPABILITIES0 ADMA2 [19..19]  =========================================== */
67284 typedef enum {                                  /*!< SDIO_CAPABILITIES0_ADMA2                                                  */
67285   SDIO_CAPABILITIES0_ADMA2_SUPPORTED   = 1,     /*!< SUPPORTED : ADMA2 support.                                                */
67286   SDIO_CAPABILITIES0_ADMA2_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : ADMA2 not support                                          */
67287 } SDIO_CAPABILITIES0_ADMA2_Enum;
67288 
67289 /* =========================================  SDIO CAPABILITIES0 EXTMEDIA [18..18]  ========================================== */
67290 typedef enum {                                  /*!< SDIO_CAPABILITIES0_EXTMEDIA                                               */
67291   SDIO_CAPABILITIES0_EXTMEDIA_SUPPORTED = 1,    /*!< SUPPORTED : Extended Media Bus Supported                                  */
67292   SDIO_CAPABILITIES0_EXTMEDIA_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Extended Media Bus not supported                           */
67293 } SDIO_CAPABILITIES0_EXTMEDIA_Enum;
67294 
67295 /* =========================================  SDIO CAPABILITIES0 MAXBLKLEN [16..17]  ========================================= */
67296 typedef enum {                                  /*!< SDIO_CAPABILITIES0_MAXBLKLEN                                              */
67297   SDIO_CAPABILITIES0_MAXBLKLEN_512     = 0,     /*!< 512 : 512 byte                                                            */
67298   SDIO_CAPABILITIES0_MAXBLKLEN_1024    = 1,     /*!< 1024 : 1024 byte                                                          */
67299   SDIO_CAPABILITIES0_MAXBLKLEN_2048    = 2,     /*!< 2048 : 2048 byte                                                          */
67300   SDIO_CAPABILITIES0_MAXBLKLEN_4096    = 3,     /*!< 4096 : 4096 byte                                                          */
67301 } SDIO_CAPABILITIES0_MAXBLKLEN_Enum;
67302 
67303 /* =========================================  SDIO CAPABILITIES0 SDCLKFREQ [8..15]  ========================================== */
67304 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SDCLKFREQ                                              */
67305   SDIO_CAPABILITIES0_SDCLKFREQ_255MHZ  = 255,   /*!< 255MHZ : 2) 8-bit base clock frequency supports frequencies
67306                                                      10MHz-255MHz.                                                             */
67307   SDIO_CAPABILITIES0_SDCLKFREQ_63MHZ   = 63,    /*!< 63MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
67308                                                      2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
67309   SDIO_CAPABILITIES0_SDCLKFREQ_2MHZ    = 2,     /*!< 2MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
67310                                                      2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
67311   SDIO_CAPABILITIES0_SDCLKFREQ_1MHZ    = 1,     /*!< 1MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
67312                                                      2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
67313   SDIO_CAPABILITIES0_SDCLKFREQ_OTHER   = 0,     /*!< OTHER : Get information via another method                                */
67314 } SDIO_CAPABILITIES0_SDCLKFREQ_Enum;
67315 
67316 /* ==========================================  SDIO CAPABILITIES0 TOCLKUNIT [7..7]  ========================================== */
67317 typedef enum {                                  /*!< SDIO_CAPABILITIES0_TOCLKUNIT                                              */
67318   SDIO_CAPABILITIES0_TOCLKUNIT_KHZ     = 0,     /*!< KHZ : Khz                                                                 */
67319   SDIO_CAPABILITIES0_TOCLKUNIT_MHZ     = 1,     /*!< MHZ : Mhz                                                                 */
67320 } SDIO_CAPABILITIES0_TOCLKUNIT_Enum;
67321 
67322 /* ==========================================  SDIO CAPABILITIES0 TOCLKFREQ [0..5]  ========================================== */
67323 typedef enum {                                  /*!< SDIO_CAPABILITIES0_TOCLKFREQ                                              */
67324   SDIO_CAPABILITIES0_TOCLKFREQ_1       = 1,     /*!< 1 : 1KHZ or 1MHZ                                                          */
67325   SDIO_CAPABILITIES0_TOCLKFREQ_2       = 2,     /*!< 2 : 2KHZ or 2MHZ                                                          */
67326   SDIO_CAPABILITIES0_TOCLKFREQ_63      = 63,    /*!< 63 : 63KHZ or 63MHZ                                                       */
67327   SDIO_CAPABILITIES0_TOCLKFREQ_OTHER   = 0,     /*!< OTHER : Get Information via another method.                               */
67328 } SDIO_CAPABILITIES0_TOCLKFREQ_Enum;
67329 
67330 /* =====================================================  CAPABILITIES1  ===================================================== */
67331 /* =======================================  SDIO CAPABILITIES1 SPIBLOCKMODE [25..25]  ======================================== */
67332 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SPIBLOCKMODE                                           */
67333   SDIO_CAPABILITIES1_SPIBLOCKMODE_NOTSUPPORTED = 0,/*!< NOTSUPPORTED : Not Supported                                           */
67334   SDIO_CAPABILITIES1_SPIBLOCKMODE_SUPPORTED = 1,/*!< SUPPORTED : Supported                                                     */
67335 } SDIO_CAPABILITIES1_SPIBLOCKMODE_Enum;
67336 
67337 /* ==========================================  SDIO CAPABILITIES1 SPIMODE [24..24]  ========================================== */
67338 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SPIMODE                                                */
67339   SDIO_CAPABILITIES1_SPIMODE_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Not Supported                                              */
67340   SDIO_CAPABILITIES1_SPIMODE_SUPPORTED = 1,     /*!< SUPPORTED : Supported                                                     */
67341 } SDIO_CAPABILITIES1_SPIMODE_Enum;
67342 
67343 /* ==========================================  SDIO CAPABILITIES1 CLKMULT [16..23]  ========================================== */
67344 typedef enum {                                  /*!< SDIO_CAPABILITIES1_CLKMULT                                                */
67345   SDIO_CAPABILITIES1_CLKMULT_MULTX256  = 255,   /*!< MULTX256 : Clock Multiplier M = 256                                       */
67346   SDIO_CAPABILITIES1_CLKMULT_MULTX3    = 2,     /*!< MULTX3 : Clock Multiplier M = 3                                           */
67347   SDIO_CAPABILITIES1_CLKMULT_MULTX2    = 1,     /*!< MULTX2 : Clock Multiplier M = 2                                           */
67348   SDIO_CAPABILITIES1_CLKMULT_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Clock Multiplier is Not Supported                          */
67349 } SDIO_CAPABILITIES1_CLKMULT_Enum;
67350 
67351 /* =======================================  SDIO CAPABILITIES1 RETUNINGMODES [14..15]  ======================================= */
67352 typedef enum {                                  /*!< SDIO_CAPABILITIES1_RETUNINGMODES                                          */
67353   SDIO_CAPABILITIES1_RETUNINGMODES_MODE1 = 0,   /*!< MODE1 : Mode1                                                             */
67354   SDIO_CAPABILITIES1_RETUNINGMODES_MODE2 = 1,   /*!< MODE2 : Mode2                                                             */
67355   SDIO_CAPABILITIES1_RETUNINGMODES_MODE3 = 2,   /*!< MODE3 : Mode3                                                             */
67356   SDIO_CAPABILITIES1_RETUNINGMODES_NOTSUPPORTED = 3,/*!< NOTSUPPORTED : Clock Multiplier is not supported.                     */
67357 } SDIO_CAPABILITIES1_RETUNINGMODES_Enum;
67358 
67359 /* ========================================  SDIO CAPABILITIES1 TUNINGSDR50 [13..13]  ======================================== */
67360 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TUNINGSDR50                                            */
67361   SDIO_CAPABILITIES1_TUNINGSDR50_TUNINGREQD = 1,/*!< TUNINGREQD : SDR50 requires tuning                                        */
67362   SDIO_CAPABILITIES1_TUNINGSDR50_NOTUNINGREQD = 0,/*!< NOTUNINGREQD : SDR50 does not require tuning                            */
67363 } SDIO_CAPABILITIES1_TUNINGSDR50_Enum;
67364 
67365 /* =======================================  SDIO CAPABILITIES1 RETUNINGTMRCNT [8..11]  ======================================= */
67366 typedef enum {                                  /*!< SDIO_CAPABILITIES1_RETUNINGTMRCNT                                         */
67367   SDIO_CAPABILITIES1_RETUNINGTMRCNT_OTHER = 0,  /*!< OTHER : 0h Get information via other source.                              */
67368   SDIO_CAPABILITIES1_RETUNINGTMRCNT_1SEC = 1,   /*!< 1SEC : 1 seconds                                                          */
67369   SDIO_CAPABILITIES1_RETUNINGTMRCNT_2SEC = 2,   /*!< 2SEC : 2 seconds                                                          */
67370   SDIO_CAPABILITIES1_RETUNINGTMRCNT_4SEC = 3,   /*!< 4SEC : 4 seconds                                                          */
67371   SDIO_CAPABILITIES1_RETUNINGTMRCNT_8S = 4,     /*!< 8S : 8 seconds                                                            */
67372   SDIO_CAPABILITIES1_RETUNINGTMRCNT_16S = 5,    /*!< 16S : 16 seconds                                                          */
67373   SDIO_CAPABILITIES1_RETUNINGTMRCNT_32S = 6,    /*!< 32S : 32 seconds                                                          */
67374   SDIO_CAPABILITIES1_RETUNINGTMRCNT_64S = 7,    /*!< 64S : 64 seconds                                                          */
67375   SDIO_CAPABILITIES1_RETUNINGTMRCNT_128S = 8,   /*!< 128S : 128 seconds                                                        */
67376   SDIO_CAPABILITIES1_RETUNINGTMRCNT_256S = 9,   /*!< 256S : 256 seconds                                                        */
67377   SDIO_CAPABILITIES1_RETUNINGTMRCNT_512S = 10,  /*!< 512S : 512 seconds                                                        */
67378   SDIO_CAPABILITIES1_RETUNINGTMRCNT_1024S = 11, /*!< 1024S : 1024 seconds                                                      */
67379 } SDIO_CAPABILITIES1_RETUNINGTMRCNT_Enum;
67380 
67381 /* ============================================  SDIO CAPABILITIES1 TYPED [6..6]  ============================================ */
67382 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPED                                                  */
67383   SDIO_CAPABILITIES1_TYPED_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type D is Supported                                    */
67384   SDIO_CAPABILITIES1_TYPED_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type D is Not Supported                             */
67385 } SDIO_CAPABILITIES1_TYPED_Enum;
67386 
67387 /* ============================================  SDIO CAPABILITIES1 TYPEC [5..5]  ============================================ */
67388 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPEC                                                  */
67389   SDIO_CAPABILITIES1_TYPEC_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type C is Supported                                    */
67390   SDIO_CAPABILITIES1_TYPEC_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type C is Not Supported                             */
67391 } SDIO_CAPABILITIES1_TYPEC_Enum;
67392 
67393 /* ============================================  SDIO CAPABILITIES1 TYPEA [4..4]  ============================================ */
67394 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPEA                                                  */
67395   SDIO_CAPABILITIES1_TYPEA_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type A is Supported                                    */
67396   SDIO_CAPABILITIES1_TYPEA_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type A is Not Supported                             */
67397 } SDIO_CAPABILITIES1_TYPEA_Enum;
67398 
67399 /* ============================================  SDIO CAPABILITIES1 DDR50 [2..2]  ============================================ */
67400 typedef enum {                                  /*!< SDIO_CAPABILITIES1_DDR50                                                  */
67401   SDIO_CAPABILITIES1_DDR50_SUPPORTED   = 1,     /*!< SUPPORTED : DDR50 is Supported                                            */
67402   SDIO_CAPABILITIES1_DDR50_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : DDR50 is Not Supported                                     */
67403 } SDIO_CAPABILITIES1_DDR50_Enum;
67404 
67405 /* ===========================================  SDIO CAPABILITIES1 SDR104 [1..1]  ============================================ */
67406 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SDR104                                                 */
67407   SDIO_CAPABILITIES1_SDR104_SUPPORTED  = 1,     /*!< SUPPORTED : SDR104 is Not Supported                                       */
67408   SDIO_CAPABILITIES1_SDR104_NOTSUPPORTED = 0,   /*!< NOTSUPPORTED : SDR104 is Not Supported                                    */
67409 } SDIO_CAPABILITIES1_SDR104_Enum;
67410 
67411 /* ============================================  SDIO CAPABILITIES1 SDR50 [0..0]  ============================================ */
67412 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SDR50                                                  */
67413   SDIO_CAPABILITIES1_SDR50_SUPPORTED   = 1,     /*!< SUPPORTED : SDR50 is Not Supported                                        */
67414   SDIO_CAPABILITIES1_SDR50_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : SDR50 is Not Supported                                     */
67415 } SDIO_CAPABILITIES1_SDR50_Enum;
67416 
67417 /* =======================================================  MAXIMUM0  ======================================================== */
67418 /* =======================================================  MAXIMUM1  ======================================================== */
67419 /* ===========================================  SDIO MAXIMUM1 MAXCURR18V [16..23]  =========================================== */
67420 typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR18V                                                  */
67421   SDIO_MAXIMUM1_MAXCURR18V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
67422   SDIO_MAXIMUM1_MAXCURR18V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
67423 } SDIO_MAXIMUM1_MAXCURR18V_Enum;
67424 
67425 /* ===========================================  SDIO MAXIMUM1 MAXCURR30V [8..15]  ============================================ */
67426 typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR30V                                                  */
67427   SDIO_MAXIMUM1_MAXCURR30V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
67428   SDIO_MAXIMUM1_MAXCURR30V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
67429 } SDIO_MAXIMUM1_MAXCURR30V_Enum;
67430 
67431 /* ============================================  SDIO MAXIMUM1 MAXCURR33V [0..7]  ============================================ */
67432 typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR33V                                                  */
67433   SDIO_MAXIMUM1_MAXCURR33V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
67434   SDIO_MAXIMUM1_MAXCURR33V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
67435 } SDIO_MAXIMUM1_MAXCURR33V_Enum;
67436 
67437 /* =========================================================  FORCE  ========================================================= */
67438 /* ===========================================  SDIO FORCE FORCEADMAERR [25..25]  ============================================ */
67439 typedef enum {                                  /*!< SDIO_FORCE_FORCEADMAERR                                                   */
67440   SDIO_FORCE_FORCEADMAERR_INT          = 1,     /*!< INT : Interrupt is generated                                              */
67441   SDIO_FORCE_FORCEADMAERR_NOINT        = 0,     /*!< NOINT : No interrupt                                                      */
67442 } SDIO_FORCE_FORCEADMAERR_Enum;
67443 
67444 /* ===========================================  SDIO FORCE FORCEACMDERR [24..24]  ============================================ */
67445 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDERR                                                   */
67446   SDIO_FORCE_FORCEACMDERR_INT          = 1,     /*!< INT : Interrupt is generated                                              */
67447   SDIO_FORCE_FORCEACMDERR_NOINT        = 0,     /*!< NOINT : No interrupt                                                      */
67448 } SDIO_FORCE_FORCEACMDERR_Enum;
67449 
67450 /* =========================================  SDIO FORCE FORCECURRLIMITERR [23..23]  ========================================= */
67451 typedef enum {                                  /*!< SDIO_FORCE_FORCECURRLIMITERR                                              */
67452   SDIO_FORCE_FORCECURRLIMITERR_INT     = 1,     /*!< INT : Interrupt is generated                                              */
67453   SDIO_FORCE_FORCECURRLIMITERR_NOINT   = 0,     /*!< NOINT : No interrupt                                                      */
67454 } SDIO_FORCE_FORCECURRLIMITERR_Enum;
67455 
67456 /* ==========================================  SDIO FORCE FORCEDATAENDERR [22..22]  ========================================== */
67457 typedef enum {                                  /*!< SDIO_FORCE_FORCEDATAENDERR                                                */
67458   SDIO_FORCE_FORCEDATAENDERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
67459   SDIO_FORCE_FORCEDATAENDERR_NOINT     = 0,     /*!< NOINT : No interrupt                                                      */
67460 } SDIO_FORCE_FORCEDATAENDERR_Enum;
67461 
67462 /* ==========================================  SDIO FORCE FORCEDATACRCERR [21..21]  ========================================== */
67463 typedef enum {                                  /*!< SDIO_FORCE_FORCEDATACRCERR                                                */
67464   SDIO_FORCE_FORCEDATACRCERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
67465   SDIO_FORCE_FORCEDATACRCERR_NOINT     = 0,     /*!< NOINT : No interrupt                                                      */
67466 } SDIO_FORCE_FORCEDATACRCERR_Enum;
67467 
67468 /* ==========================================  SDIO FORCE FORCEDATATOERR [20..20]  =========================================== */
67469 typedef enum {                                  /*!< SDIO_FORCE_FORCEDATATOERR                                                 */
67470   SDIO_FORCE_FORCEDATATOERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
67471   SDIO_FORCE_FORCEDATATOERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
67472 } SDIO_FORCE_FORCEDATATOERR_Enum;
67473 
67474 /* ==========================================  SDIO FORCE FORCECMDIDXERR [19..19]  =========================================== */
67475 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDIDXERR                                                 */
67476   SDIO_FORCE_FORCECMDIDXERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
67477   SDIO_FORCE_FORCECMDIDXERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
67478 } SDIO_FORCE_FORCECMDIDXERR_Enum;
67479 
67480 /* ==========================================  SDIO FORCE FORCECMDENDERR [18..18]  =========================================== */
67481 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDENDERR                                                 */
67482   SDIO_FORCE_FORCECMDENDERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
67483   SDIO_FORCE_FORCECMDENDERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
67484 } SDIO_FORCE_FORCECMDENDERR_Enum;
67485 
67486 /* ==========================================  SDIO FORCE FORCECMDCRCERR [17..17]  =========================================== */
67487 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDCRCERR                                                 */
67488   SDIO_FORCE_FORCECMDCRCERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
67489   SDIO_FORCE_FORCECMDCRCERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
67490 } SDIO_FORCE_FORCECMDCRCERR_Enum;
67491 
67492 /* ===========================================  SDIO FORCE FORCECMDTOERR [16..16]  =========================================== */
67493 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDTOERR                                                  */
67494   SDIO_FORCE_FORCECMDTOERR_INT         = 1,     /*!< INT : Interrupt is generated                                              */
67495   SDIO_FORCE_FORCECMDTOERR_NOINT       = 0,     /*!< NOINT : No interrupt                                                      */
67496 } SDIO_FORCE_FORCECMDTOERR_Enum;
67497 
67498 /* =========================================  SDIO FORCE FORCEACMDISSUEDERR [7..7]  ========================================== */
67499 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDISSUEDERR                                             */
67500   SDIO_FORCE_FORCEACMDISSUEDERR_INT    = 1,     /*!< INT : Interrupt is generated                                              */
67501   SDIO_FORCE_FORCEACMDISSUEDERR_NOINT  = 0,     /*!< NOINT : no interrupt                                                      */
67502 } SDIO_FORCE_FORCEACMDISSUEDERR_Enum;
67503 
67504 /* ===========================================  SDIO FORCE FORCEACMDIDXERR [4..4]  =========================================== */
67505 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDIDXERR                                                */
67506   SDIO_FORCE_FORCEACMDIDXERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
67507   SDIO_FORCE_FORCEACMDIDXERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
67508 } SDIO_FORCE_FORCEACMDIDXERR_Enum;
67509 
67510 /* ===========================================  SDIO FORCE FORCEACMDENDERR [3..3]  =========================================== */
67511 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDENDERR                                                */
67512   SDIO_FORCE_FORCEACMDENDERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
67513   SDIO_FORCE_FORCEACMDENDERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
67514 } SDIO_FORCE_FORCEACMDENDERR_Enum;
67515 
67516 /* ===========================================  SDIO FORCE FORCEACMDCRCERR [2..2]  =========================================== */
67517 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDCRCERR                                                */
67518   SDIO_FORCE_FORCEACMDCRCERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
67519   SDIO_FORCE_FORCEACMDCRCERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
67520 } SDIO_FORCE_FORCEACMDCRCERR_Enum;
67521 
67522 /* ===========================================  SDIO FORCE FORCEACMDTOERR [1..1]  ============================================ */
67523 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDTOERR                                                 */
67524   SDIO_FORCE_FORCEACMDTOERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
67525   SDIO_FORCE_FORCEACMDTOERR_NOINT      = 0,     /*!< NOINT : no interrupt                                                      */
67526 } SDIO_FORCE_FORCEACMDTOERR_Enum;
67527 
67528 /* ===========================================  SDIO FORCE FORCEACMD12NOT [0..0]  ============================================ */
67529 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMD12NOT                                                 */
67530   SDIO_FORCE_FORCEACMD12NOT_INT        = 1,     /*!< INT : Interrupt is generated                                              */
67531   SDIO_FORCE_FORCEACMD12NOT_NOINT      = 0,     /*!< NOINT : no interrupt                                                      */
67532 } SDIO_FORCE_FORCEACMD12NOT_Enum;
67533 
67534 /* =========================================================  ADMA  ========================================================== */
67535 /* ==========================================  SDIO ADMA ADMALENMISMATCHERR [2..2]  ========================================== */
67536 typedef enum {                                  /*!< SDIO_ADMA_ADMALENMISMATCHERR                                              */
67537   SDIO_ADMA_ADMALENMISMATCHERR_ERROR   = 1,     /*!< ERROR : Error                                                             */
67538   SDIO_ADMA_ADMALENMISMATCHERR_NOERROR = 0,     /*!< NOERROR : No error                                                        */
67539 } SDIO_ADMA_ADMALENMISMATCHERR_Enum;
67540 
67541 /* ============================================  SDIO ADMA ADMAERRORSTATE [0..1]  ============================================ */
67542 typedef enum {                                  /*!< SDIO_ADMA_ADMAERRORSTATE                                                  */
67543   SDIO_ADMA_ADMAERRORSTATE_STDMA       = 0,     /*!< STDMA : ST_STOP (Stop DMA) Points to next of the error descriptor         */
67544   SDIO_ADMA_ADMAERRORSTATE_FETCHDESC   = 1,     /*!< FETCHDESC : ST_FDS (Fetch Descriptor) Points to the error descriptor      */
67545   SDIO_ADMA_ADMAERRORSTATE_INVALID     = 2,     /*!< INVALID : Never set this state (Not used)                                 */
67546   SDIO_ADMA_ADMAERRORSTATE_XFERDATA    = 3,     /*!< XFERDATA : ST_TFR (Transfer Data) Points to the next of the
67547                                                      error descriptor                                                          */
67548 } SDIO_ADMA_ADMAERRORSTATE_Enum;
67549 
67550 /* =======================================================  ADMALOWD  ======================================================== */
67551 /* =======================================================  ADMAHIWD  ======================================================== */
67552 /* ========================================================  PRESET0  ======================================================== */
67553 /* =========================================  SDIO PRESET0 DEFSPDRVRSTRSEL [30..31]  ========================================= */
67554 typedef enum {                                  /*!< SDIO_PRESET0_DEFSPDRVRSTRSEL                                              */
67555   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67556   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67557   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67558   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67559 } SDIO_PRESET0_DEFSPDRVRSTRSEL_Enum;
67560 
67561 /* =========================================  SDIO PRESET0 DEFSPCLKGENSEL [26..26]  ========================================== */
67562 typedef enum {                                  /*!< SDIO_PRESET0_DEFSPCLKGENSEL                                               */
67563   SDIO_PRESET0_DEFSPCLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67564   SDIO_PRESET0_DEFSPCLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67565 } SDIO_PRESET0_DEFSPCLKGENSEL_Enum;
67566 
67567 /* =========================================  SDIO PRESET0 HISPDRVRSTRSEL [14..15]  ========================================== */
67568 typedef enum {                                  /*!< SDIO_PRESET0_HISPDRVRSTRSEL                                               */
67569   SDIO_PRESET0_HISPDRVRSTRSEL_TYPED    = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67570   SDIO_PRESET0_HISPDRVRSTRSEL_TYPEC    = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67571   SDIO_PRESET0_HISPDRVRSTRSEL_TYPEA    = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67572   SDIO_PRESET0_HISPDRVRSTRSEL_TYPEB    = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67573 } SDIO_PRESET0_HISPDRVRSTRSEL_Enum;
67574 
67575 /* ==========================================  SDIO PRESET0 HISPCLKGENSEL [10..10]  ========================================== */
67576 typedef enum {                                  /*!< SDIO_PRESET0_HISPCLKGENSEL                                                */
67577   SDIO_PRESET0_HISPCLKGENSEL_PROGCLK   = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67578   SDIO_PRESET0_HISPCLKGENSEL_HOSTCTLR  = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67579 } SDIO_PRESET0_HISPCLKGENSEL_Enum;
67580 
67581 /* ========================================================  PRESET1  ======================================================== */
67582 /* =========================================  SDIO PRESET1 SDR12DRVRSTRSEL [30..31]  ========================================= */
67583 typedef enum {                                  /*!< SDIO_PRESET1_SDR12DRVRSTRSEL                                              */
67584   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67585   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67586   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67587   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67588 } SDIO_PRESET1_SDR12DRVRSTRSEL_Enum;
67589 
67590 /* =========================================  SDIO PRESET1 SDR12CLKGENSEL [26..26]  ========================================== */
67591 typedef enum {                                  /*!< SDIO_PRESET1_SDR12CLKGENSEL                                               */
67592   SDIO_PRESET1_SDR12CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67593   SDIO_PRESET1_SDR12CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67594 } SDIO_PRESET1_SDR12CLKGENSEL_Enum;
67595 
67596 /* ==========================================  SDIO PRESET1 HSDRVRSTRSEL [14..15]  =========================================== */
67597 typedef enum {                                  /*!< SDIO_PRESET1_HSDRVRSTRSEL                                                 */
67598   SDIO_PRESET1_HSDRVRSTRSEL_TYPED      = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67599   SDIO_PRESET1_HSDRVRSTRSEL_TYPEC      = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67600   SDIO_PRESET1_HSDRVRSTRSEL_TYPEA      = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67601   SDIO_PRESET1_HSDRVRSTRSEL_TYPEB      = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67602 } SDIO_PRESET1_HSDRVRSTRSEL_Enum;
67603 
67604 /* ===========================================  SDIO PRESET1 HSCLKGENSEL [10..10]  =========================================== */
67605 typedef enum {                                  /*!< SDIO_PRESET1_HSCLKGENSEL                                                  */
67606   SDIO_PRESET1_HSCLKGENSEL_PROGCLK     = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67607   SDIO_PRESET1_HSCLKGENSEL_HOSTCTLR    = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67608 } SDIO_PRESET1_HSCLKGENSEL_Enum;
67609 
67610 /* ========================================================  PRESET2  ======================================================== */
67611 /* =========================================  SDIO PRESET2 SDR50DRVRSTRSEL [30..31]  ========================================= */
67612 typedef enum {                                  /*!< SDIO_PRESET2_SDR50DRVRSTRSEL                                              */
67613   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67614   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67615   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67616   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67617 } SDIO_PRESET2_SDR50DRVRSTRSEL_Enum;
67618 
67619 /* =========================================  SDIO PRESET2 SDR50CLKGENSEL [26..26]  ========================================== */
67620 typedef enum {                                  /*!< SDIO_PRESET2_SDR50CLKGENSEL                                               */
67621   SDIO_PRESET2_SDR50CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67622   SDIO_PRESET2_SDR50CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67623 } SDIO_PRESET2_SDR50CLKGENSEL_Enum;
67624 
67625 /* =========================================  SDIO PRESET2 SDR25DRVRSTRSEL [14..15]  ========================================= */
67626 typedef enum {                                  /*!< SDIO_PRESET2_SDR25DRVRSTRSEL                                              */
67627   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67628   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67629   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67630   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67631 } SDIO_PRESET2_SDR25DRVRSTRSEL_Enum;
67632 
67633 /* =========================================  SDIO PRESET2 SDR25CLKGENSEL [10..10]  ========================================== */
67634 typedef enum {                                  /*!< SDIO_PRESET2_SDR25CLKGENSEL                                               */
67635   SDIO_PRESET2_SDR25CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67636   SDIO_PRESET2_SDR25CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67637 } SDIO_PRESET2_SDR25CLKGENSEL_Enum;
67638 
67639 /* ========================================================  PRESET3  ======================================================== */
67640 /* =========================================  SDIO PRESET3 DDR50DRVRSTRSEL [30..31]  ========================================= */
67641 typedef enum {                                  /*!< SDIO_PRESET3_DDR50DRVRSTRSEL                                              */
67642   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67643   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67644   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67645   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67646 } SDIO_PRESET3_DDR50DRVRSTRSEL_Enum;
67647 
67648 /* =========================================  SDIO PRESET3 DDR50CLKGENSEL [26..26]  ========================================== */
67649 typedef enum {                                  /*!< SDIO_PRESET3_DDR50CLKGENSEL                                               */
67650   SDIO_PRESET3_DDR50CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67651   SDIO_PRESET3_DDR50CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67652 } SDIO_PRESET3_DDR50CLKGENSEL_Enum;
67653 
67654 /* ========================================  SDIO PRESET3 SDR104DRVRSTRSEL [14..15]  ========================================= */
67655 typedef enum {                                  /*!< SDIO_PRESET3_SDR104DRVRSTRSEL                                             */
67656   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPED  = 3,     /*!< TYPED : Driver Type D is Selected                                         */
67657   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEC  = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
67658   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEA  = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
67659   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEB  = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
67660 } SDIO_PRESET3_SDR104DRVRSTRSEL_Enum;
67661 
67662 /* =========================================  SDIO PRESET3 SDR104CLKGENSEL [10..10]  ========================================= */
67663 typedef enum {                                  /*!< SDIO_PRESET3_SDR104CLKGENSEL                                              */
67664   SDIO_PRESET3_SDR104CLKGENSEL_PROGCLK = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
67665   SDIO_PRESET3_SDR104CLKGENSEL_HOSTCTLR = 0,    /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
67666 } SDIO_PRESET3_SDR104CLKGENSEL_Enum;
67667 
67668 /* ======================================================  BOOTTOCTRL  ======================================================= */
67669 /* ========================================================  VENDOR  ========================================================= */
67670 /* ===============================================  SDIO VENDOR DLYDIS [1..1]  =============================================== */
67671 typedef enum {                                  /*!< SDIO_VENDOR_DLYDIS                                                        */
67672   SDIO_VENDOR_DLYDIS_DISABLE           = 1,     /*!< DISABLE : Disable the hardware delay for sampling of cmd_in
67673                                                      and data_in                                                               */
67674   SDIO_VENDOR_DLYDIS_ENABLE            = 0,     /*!< ENABLE : Enable the hardware delay for sampling of cmd_in and
67675                                                      data_in                                                                   */
67676 } SDIO_VENDOR_DLYDIS_Enum;
67677 
67678 /* ============================================  SDIO VENDOR GATESDCLKEN [0..0]  ============================================= */
67679 typedef enum {                                  /*!< SDIO_VENDOR_GATESDCLKEN                                                   */
67680   SDIO_VENDOR_GATESDCLKEN_GATE         = 1,     /*!< GATE : SD_CLK to card will be gated automatically when there
67681                                                      is no transfer.                                                           */
67682   SDIO_VENDOR_GATESDCLKEN_NOGATE       = 0,     /*!< NOGATE : SD_CLK to card will NOT be gated automatically when
67683                                                      there is no transfer.                                                     */
67684 } SDIO_VENDOR_GATESDCLKEN_Enum;
67685 
67686 /* =======================================================  SLOTSTAT  ======================================================== */
67687 
67688 
67689 /* =========================================================================================================================== */
67690 /* ================                                         SECURITY                                          ================ */
67691 /* =========================================================================================================================== */
67692 
67693 /* =========================================================  CTRL  ========================================================== */
67694 /* =============================================  SECURITY CTRL FUNCTION [4..7]  ============================================= */
67695 typedef enum {                                  /*!< SECURITY_CTRL_FUNCTION                                                    */
67696   SECURITY_CTRL_FUNCTION_CRC32         = 0,     /*!< CRC32 : Perform CRC32 operation                                           */
67697   SECURITY_CTRL_FUNCTION_RAND          = 1,     /*!< RAND : DMA pseudo-random number stream based on CRC value                 */
67698   SECURITY_CTRL_FUNCTION_GENADDR       = 2,     /*!< GENADDR : Generate DMA stream based on address                            */
67699 } SECURITY_CTRL_FUNCTION_Enum;
67700 
67701 /* ========================================================  SRCADDR  ======================================================== */
67702 /* ==========================================================  LEN  ========================================================== */
67703 /* ========================================================  RESULT  ========================================================= */
67704 /* =======================================================  LOCKCTRL  ======================================================== */
67705 /* ============================================  SECURITY LOCKCTRL SELECT [0..7]  ============================================ */
67706 typedef enum {                                  /*!< SECURITY_LOCKCTRL_SELECT                                                  */
67707   SECURITY_LOCKCTRL_SELECT_NONE        = 0,     /*!< NONE : Lock Control should be set to NONE when not in use.                */
67708 } SECURITY_LOCKCTRL_SELECT_Enum;
67709 
67710 /* =======================================================  LOCKSTAT  ======================================================== */
67711 /* ===========================================  SECURITY LOCKSTAT STATUS [0..31]  ============================================ */
67712 typedef enum {                                  /*!< SECURITY_LOCKSTAT_STATUS                                                  */
67713   SECURITY_LOCKSTAT_STATUS_NONE        = 0,     /*!< NONE : No resources are unlocked                                          */
67714 } SECURITY_LOCKSTAT_STATUS_Enum;
67715 
67716 /* =========================================================  KEY0  ========================================================== */
67717 /* =========================================================  KEY1  ========================================================== */
67718 /* =========================================================  KEY2  ========================================================== */
67719 /* =========================================================  KEY3  ========================================================== */
67720 
67721 
67722 /* =========================================================================================================================== */
67723 /* ================                                          STIMER                                           ================ */
67724 /* =========================================================================================================================== */
67725 
67726 /* =========================================================  STCFG  ========================================================= */
67727 /* =============================================  STIMER STCFG FREEZE [31..31]  ============================================== */
67728 typedef enum {                                  /*!< STIMER_STCFG_FREEZE                                                       */
67729   STIMER_STCFG_FREEZE_THAW             = 0,     /*!< THAW : Let the COUNTER register run on its input clock.                   */
67730   STIMER_STCFG_FREEZE_FREEZE           = 1,     /*!< FREEZE : Stop the COUNTER register for loading.                           */
67731 } STIMER_STCFG_FREEZE_Enum;
67732 
67733 /* ==============================================  STIMER STCFG CLEAR [30..30]  ============================================== */
67734 typedef enum {                                  /*!< STIMER_STCFG_CLEAR                                                        */
67735   STIMER_STCFG_CLEAR_RUN               = 0,     /*!< RUN : Let the COUNTER register run on its input clock.                    */
67736   STIMER_STCFG_CLEAR_CLEAR             = 1,     /*!< CLEAR : Stop the COUNTER register for loading.                            */
67737 } STIMER_STCFG_CLEAR_Enum;
67738 
67739 /* ===========================================  STIMER STCFG COMPAREHEN [15..15]  ============================================ */
67740 typedef enum {                                  /*!< STIMER_STCFG_COMPAREHEN                                                   */
67741   STIMER_STCFG_COMPAREHEN_DISABLE      = 0,     /*!< DISABLE : Compare H disabled.                                             */
67742   STIMER_STCFG_COMPAREHEN_ENABLE       = 1,     /*!< ENABLE : Compare H enabled.                                               */
67743 } STIMER_STCFG_COMPAREHEN_Enum;
67744 
67745 /* ===========================================  STIMER STCFG COMPAREGEN [14..14]  ============================================ */
67746 typedef enum {                                  /*!< STIMER_STCFG_COMPAREGEN                                                   */
67747   STIMER_STCFG_COMPAREGEN_DISABLE      = 0,     /*!< DISABLE : Compare G disabled.                                             */
67748   STIMER_STCFG_COMPAREGEN_ENABLE       = 1,     /*!< ENABLE : Compare G enabled.                                               */
67749 } STIMER_STCFG_COMPAREGEN_Enum;
67750 
67751 /* ===========================================  STIMER STCFG COMPAREFEN [13..13]  ============================================ */
67752 typedef enum {                                  /*!< STIMER_STCFG_COMPAREFEN                                                   */
67753   STIMER_STCFG_COMPAREFEN_DISABLE      = 0,     /*!< DISABLE : Compare F disabled.                                             */
67754   STIMER_STCFG_COMPAREFEN_ENABLE       = 1,     /*!< ENABLE : Compare F enabled.                                               */
67755 } STIMER_STCFG_COMPAREFEN_Enum;
67756 
67757 /* ===========================================  STIMER STCFG COMPAREEEN [12..12]  ============================================ */
67758 typedef enum {                                  /*!< STIMER_STCFG_COMPAREEEN                                                   */
67759   STIMER_STCFG_COMPAREEEN_DISABLE      = 0,     /*!< DISABLE : Compare E disabled.                                             */
67760   STIMER_STCFG_COMPAREEEN_ENABLE       = 1,     /*!< ENABLE : Compare E enabled.                                               */
67761 } STIMER_STCFG_COMPAREEEN_Enum;
67762 
67763 /* ===========================================  STIMER STCFG COMPAREDEN [11..11]  ============================================ */
67764 typedef enum {                                  /*!< STIMER_STCFG_COMPAREDEN                                                   */
67765   STIMER_STCFG_COMPAREDEN_DISABLE      = 0,     /*!< DISABLE : Compare D disabled.                                             */
67766   STIMER_STCFG_COMPAREDEN_ENABLE       = 1,     /*!< ENABLE : Compare D enabled.                                               */
67767 } STIMER_STCFG_COMPAREDEN_Enum;
67768 
67769 /* ===========================================  STIMER STCFG COMPARECEN [10..10]  ============================================ */
67770 typedef enum {                                  /*!< STIMER_STCFG_COMPARECEN                                                   */
67771   STIMER_STCFG_COMPARECEN_DISABLE      = 0,     /*!< DISABLE : Compare C disabled.                                             */
67772   STIMER_STCFG_COMPARECEN_ENABLE       = 1,     /*!< ENABLE : Compare C enabled.                                               */
67773 } STIMER_STCFG_COMPARECEN_Enum;
67774 
67775 /* ============================================  STIMER STCFG COMPAREBEN [9..9]  ============================================= */
67776 typedef enum {                                  /*!< STIMER_STCFG_COMPAREBEN                                                   */
67777   STIMER_STCFG_COMPAREBEN_DISABLE      = 0,     /*!< DISABLE : Compare B disabled.                                             */
67778   STIMER_STCFG_COMPAREBEN_ENABLE       = 1,     /*!< ENABLE : Compare B enabled.                                               */
67779 } STIMER_STCFG_COMPAREBEN_Enum;
67780 
67781 /* ============================================  STIMER STCFG COMPAREAEN [8..8]  ============================================= */
67782 typedef enum {                                  /*!< STIMER_STCFG_COMPAREAEN                                                   */
67783   STIMER_STCFG_COMPAREAEN_DISABLE      = 0,     /*!< DISABLE : Compare A disabled.                                             */
67784   STIMER_STCFG_COMPAREAEN_ENABLE       = 1,     /*!< ENABLE : Compare A enabled.                                               */
67785 } STIMER_STCFG_COMPAREAEN_Enum;
67786 
67787 /* ==============================================  STIMER STCFG CLKSEL [0..3]  =============================================== */
67788 typedef enum {                                  /*!< STIMER_STCFG_CLKSEL                                                       */
67789   STIMER_STCFG_CLKSEL_NOCLK            = 0,     /*!< NOCLK : No clock enabled.                                                 */
67790   STIMER_STCFG_CLKSEL_HFRC_6MHZ        = 1,     /*!< HFRC_6MHZ : 6MHz from the HFRC clock divider.                             */
67791   STIMER_STCFG_CLKSEL_HFRC_375KHZ      = 2,     /*!< HFRC_375KHZ : 375KHz from the HFRC clock divider.                         */
67792   STIMER_STCFG_CLKSEL_XTAL_32KHZ       = 3,     /*!< XTAL_32KHZ : 32768Hz from the crystal oscillator.                         */
67793   STIMER_STCFG_CLKSEL_XTAL_16KHZ       = 4,     /*!< XTAL_16KHZ : 16384Hz from the crystal oscillator.                         */
67794   STIMER_STCFG_CLKSEL_XTAL_1KHZ        = 5,     /*!< XTAL_1KHZ : 1024Hz from the crystal oscillator.                           */
67795   STIMER_STCFG_CLKSEL_LFRC_1KHZ        = 6,     /*!< LFRC_1KHZ : Approximately 1KHz from the LFRC oscillator (uncalibrated).   */
67796   STIMER_STCFG_CLKSEL_CTIMER0          = 7,     /*!< CTIMER0 : Use CTIMER 0 for the clock source (allows prescaling
67797                                                      from other system clocks).                                                */
67798   STIMER_STCFG_CLKSEL_CTIMER1          = 8,     /*!< CTIMER1 : Use CTIMER 1 for the clock source (allows prescaling
67799                                                      from other system clocks).                                                */
67800 } STIMER_STCFG_CLKSEL_Enum;
67801 
67802 /* =========================================================  STTMR  ========================================================= */
67803 /* =======================================================  SCAPCTRL0  ======================================================= */
67804 /* ===========================================  STIMER SCAPCTRL0 CAPTURE0 [9..9]  ============================================ */
67805 typedef enum {                                  /*!< STIMER_SCAPCTRL0_CAPTURE0                                                 */
67806   STIMER_SCAPCTRL0_CAPTURE0_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
67807   STIMER_SCAPCTRL0_CAPTURE0_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
67808 } STIMER_SCAPCTRL0_CAPTURE0_Enum;
67809 
67810 /* ============================================  STIMER SCAPCTRL0 STPOL0 [8..8]  ============================================= */
67811 typedef enum {                                  /*!< STIMER_SCAPCTRL0_STPOL0                                                   */
67812   STIMER_SCAPCTRL0_STPOL0_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
67813   STIMER_SCAPCTRL0_STPOL0_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
67814 } STIMER_SCAPCTRL0_STPOL0_Enum;
67815 
67816 /* =======================================================  SCAPCTRL1  ======================================================= */
67817 /* ===========================================  STIMER SCAPCTRL1 CAPTURE1 [9..9]  ============================================ */
67818 typedef enum {                                  /*!< STIMER_SCAPCTRL1_CAPTURE1                                                 */
67819   STIMER_SCAPCTRL1_CAPTURE1_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
67820   STIMER_SCAPCTRL1_CAPTURE1_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
67821 } STIMER_SCAPCTRL1_CAPTURE1_Enum;
67822 
67823 /* ============================================  STIMER SCAPCTRL1 STPOL1 [8..8]  ============================================= */
67824 typedef enum {                                  /*!< STIMER_SCAPCTRL1_STPOL1                                                   */
67825   STIMER_SCAPCTRL1_STPOL1_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
67826   STIMER_SCAPCTRL1_STPOL1_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
67827 } STIMER_SCAPCTRL1_STPOL1_Enum;
67828 
67829 /* =======================================================  SCAPCTRL2  ======================================================= */
67830 /* ===========================================  STIMER SCAPCTRL2 CAPTURE2 [9..9]  ============================================ */
67831 typedef enum {                                  /*!< STIMER_SCAPCTRL2_CAPTURE2                                                 */
67832   STIMER_SCAPCTRL2_CAPTURE2_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
67833   STIMER_SCAPCTRL2_CAPTURE2_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
67834 } STIMER_SCAPCTRL2_CAPTURE2_Enum;
67835 
67836 /* ============================================  STIMER SCAPCTRL2 STPOL2 [8..8]  ============================================= */
67837 typedef enum {                                  /*!< STIMER_SCAPCTRL2_STPOL2                                                   */
67838   STIMER_SCAPCTRL2_STPOL2_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
67839   STIMER_SCAPCTRL2_STPOL2_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
67840 } STIMER_SCAPCTRL2_STPOL2_Enum;
67841 
67842 /* =======================================================  SCAPCTRL3  ======================================================= */
67843 /* ===========================================  STIMER SCAPCTRL3 CAPTURE3 [9..9]  ============================================ */
67844 typedef enum {                                  /*!< STIMER_SCAPCTRL3_CAPTURE3                                                 */
67845   STIMER_SCAPCTRL3_CAPTURE3_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
67846   STIMER_SCAPCTRL3_CAPTURE3_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
67847 } STIMER_SCAPCTRL3_CAPTURE3_Enum;
67848 
67849 /* ============================================  STIMER SCAPCTRL3 STPOL3 [8..8]  ============================================= */
67850 typedef enum {                                  /*!< STIMER_SCAPCTRL3_STPOL3                                                   */
67851   STIMER_SCAPCTRL3_STPOL3_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
67852   STIMER_SCAPCTRL3_STPOL3_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
67853 } STIMER_SCAPCTRL3_STPOL3_Enum;
67854 
67855 /* ========================================================  SCMPR0  ========================================================= */
67856 /* ========================================================  SCMPR1  ========================================================= */
67857 /* ========================================================  SCMPR2  ========================================================= */
67858 /* ========================================================  SCMPR3  ========================================================= */
67859 /* ========================================================  SCMPR4  ========================================================= */
67860 /* ========================================================  SCMPR5  ========================================================= */
67861 /* ========================================================  SCMPR6  ========================================================= */
67862 /* ========================================================  SCMPR7  ========================================================= */
67863 /* ========================================================  SCAPT0  ========================================================= */
67864 /* ========================================================  SCAPT1  ========================================================= */
67865 /* ========================================================  SCAPT2  ========================================================= */
67866 /* ========================================================  SCAPT3  ========================================================= */
67867 /* =========================================================  SNVR0  ========================================================= */
67868 /* =========================================================  SNVR1  ========================================================= */
67869 /* =========================================================  SNVR2  ========================================================= */
67870 /* =======================================================  STMINTEN  ======================================================== */
67871 /* ===========================================  STIMER STMINTEN CAPTURED [12..12]  =========================================== */
67872 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTURED                                                  */
67873   STIMER_STMINTEN_CAPTURED_CAPD_INT    = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
67874 } STIMER_STMINTEN_CAPTURED_Enum;
67875 
67876 /* ===========================================  STIMER STMINTEN CAPTUREC [11..11]  =========================================== */
67877 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREC                                                  */
67878   STIMER_STMINTEN_CAPTUREC_CAPC_INT    = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
67879 } STIMER_STMINTEN_CAPTUREC_Enum;
67880 
67881 /* ===========================================  STIMER STMINTEN CAPTUREB [10..10]  =========================================== */
67882 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREB                                                  */
67883   STIMER_STMINTEN_CAPTUREB_CAPB_INT    = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
67884 } STIMER_STMINTEN_CAPTUREB_Enum;
67885 
67886 /* ============================================  STIMER STMINTEN CAPTUREA [9..9]  ============================================ */
67887 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREA                                                  */
67888   STIMER_STMINTEN_CAPTUREA_CAPA_INT    = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
67889 } STIMER_STMINTEN_CAPTUREA_Enum;
67890 
67891 /* ============================================  STIMER STMINTEN OVERFLOW [8..8]  ============================================ */
67892 typedef enum {                                  /*!< STIMER_STMINTEN_OVERFLOW                                                  */
67893   STIMER_STMINTEN_OVERFLOW_OFLOW_INT   = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
67894 } STIMER_STMINTEN_OVERFLOW_Enum;
67895 
67896 /* ============================================  STIMER STMINTEN COMPAREH [7..7]  ============================================ */
67897 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREH                                                  */
67898   STIMER_STMINTEN_COMPAREH_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67899 } STIMER_STMINTEN_COMPAREH_Enum;
67900 
67901 /* ============================================  STIMER STMINTEN COMPAREG [6..6]  ============================================ */
67902 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREG                                                  */
67903   STIMER_STMINTEN_COMPAREG_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67904 } STIMER_STMINTEN_COMPAREG_Enum;
67905 
67906 /* ============================================  STIMER STMINTEN COMPAREF [5..5]  ============================================ */
67907 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREF                                                  */
67908   STIMER_STMINTEN_COMPAREF_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67909 } STIMER_STMINTEN_COMPAREF_Enum;
67910 
67911 /* ============================================  STIMER STMINTEN COMPAREE [4..4]  ============================================ */
67912 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREE                                                  */
67913   STIMER_STMINTEN_COMPAREE_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67914 } STIMER_STMINTEN_COMPAREE_Enum;
67915 
67916 /* ============================================  STIMER STMINTEN COMPARED [3..3]  ============================================ */
67917 typedef enum {                                  /*!< STIMER_STMINTEN_COMPARED                                                  */
67918   STIMER_STMINTEN_COMPARED_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67919 } STIMER_STMINTEN_COMPARED_Enum;
67920 
67921 /* ============================================  STIMER STMINTEN COMPAREC [2..2]  ============================================ */
67922 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREC                                                  */
67923   STIMER_STMINTEN_COMPAREC_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67924 } STIMER_STMINTEN_COMPAREC_Enum;
67925 
67926 /* ============================================  STIMER STMINTEN COMPAREB [1..1]  ============================================ */
67927 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREB                                                  */
67928   STIMER_STMINTEN_COMPAREB_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67929 } STIMER_STMINTEN_COMPAREB_Enum;
67930 
67931 /* ============================================  STIMER STMINTEN COMPAREA [0..0]  ============================================ */
67932 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREA                                                  */
67933   STIMER_STMINTEN_COMPAREA_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67934 } STIMER_STMINTEN_COMPAREA_Enum;
67935 
67936 /* ======================================================  STMINTSTAT  ======================================================= */
67937 /* ==========================================  STIMER STMINTSTAT CAPTURED [12..12]  ========================================== */
67938 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTURED                                                */
67939   STIMER_STMINTSTAT_CAPTURED_CAPD_INT  = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
67940 } STIMER_STMINTSTAT_CAPTURED_Enum;
67941 
67942 /* ==========================================  STIMER STMINTSTAT CAPTUREC [11..11]  ========================================== */
67943 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREC                                                */
67944   STIMER_STMINTSTAT_CAPTUREC_CAPC_INT  = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
67945 } STIMER_STMINTSTAT_CAPTUREC_Enum;
67946 
67947 /* ==========================================  STIMER STMINTSTAT CAPTUREB [10..10]  ========================================== */
67948 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREB                                                */
67949   STIMER_STMINTSTAT_CAPTUREB_CAPB_INT  = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
67950 } STIMER_STMINTSTAT_CAPTUREB_Enum;
67951 
67952 /* ===========================================  STIMER STMINTSTAT CAPTUREA [9..9]  =========================================== */
67953 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREA                                                */
67954   STIMER_STMINTSTAT_CAPTUREA_CAPA_INT  = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
67955 } STIMER_STMINTSTAT_CAPTUREA_Enum;
67956 
67957 /* ===========================================  STIMER STMINTSTAT OVERFLOW [8..8]  =========================================== */
67958 typedef enum {                                  /*!< STIMER_STMINTSTAT_OVERFLOW                                                */
67959   STIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
67960 } STIMER_STMINTSTAT_OVERFLOW_Enum;
67961 
67962 /* ===========================================  STIMER STMINTSTAT COMPAREH [7..7]  =========================================== */
67963 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREH                                                */
67964   STIMER_STMINTSTAT_COMPAREH_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67965 } STIMER_STMINTSTAT_COMPAREH_Enum;
67966 
67967 /* ===========================================  STIMER STMINTSTAT COMPAREG [6..6]  =========================================== */
67968 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREG                                                */
67969   STIMER_STMINTSTAT_COMPAREG_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67970 } STIMER_STMINTSTAT_COMPAREG_Enum;
67971 
67972 /* ===========================================  STIMER STMINTSTAT COMPAREF [5..5]  =========================================== */
67973 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREF                                                */
67974   STIMER_STMINTSTAT_COMPAREF_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67975 } STIMER_STMINTSTAT_COMPAREF_Enum;
67976 
67977 /* ===========================================  STIMER STMINTSTAT COMPAREE [4..4]  =========================================== */
67978 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREE                                                */
67979   STIMER_STMINTSTAT_COMPAREE_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67980 } STIMER_STMINTSTAT_COMPAREE_Enum;
67981 
67982 /* ===========================================  STIMER STMINTSTAT COMPARED [3..3]  =========================================== */
67983 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPARED                                                */
67984   STIMER_STMINTSTAT_COMPARED_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67985 } STIMER_STMINTSTAT_COMPARED_Enum;
67986 
67987 /* ===========================================  STIMER STMINTSTAT COMPAREC [2..2]  =========================================== */
67988 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREC                                                */
67989   STIMER_STMINTSTAT_COMPAREC_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67990 } STIMER_STMINTSTAT_COMPAREC_Enum;
67991 
67992 /* ===========================================  STIMER STMINTSTAT COMPAREB [1..1]  =========================================== */
67993 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREB                                                */
67994   STIMER_STMINTSTAT_COMPAREB_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
67995 } STIMER_STMINTSTAT_COMPAREB_Enum;
67996 
67997 /* ===========================================  STIMER STMINTSTAT COMPAREA [0..0]  =========================================== */
67998 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREA                                                */
67999   STIMER_STMINTSTAT_COMPAREA_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68000 } STIMER_STMINTSTAT_COMPAREA_Enum;
68001 
68002 /* =======================================================  STMINTCLR  ======================================================= */
68003 /* ==========================================  STIMER STMINTCLR CAPTURED [12..12]  =========================================== */
68004 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTURED                                                 */
68005   STIMER_STMINTCLR_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
68006 } STIMER_STMINTCLR_CAPTURED_Enum;
68007 
68008 /* ==========================================  STIMER STMINTCLR CAPTUREC [11..11]  =========================================== */
68009 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREC                                                 */
68010   STIMER_STMINTCLR_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
68011 } STIMER_STMINTCLR_CAPTUREC_Enum;
68012 
68013 /* ==========================================  STIMER STMINTCLR CAPTUREB [10..10]  =========================================== */
68014 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREB                                                 */
68015   STIMER_STMINTCLR_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
68016 } STIMER_STMINTCLR_CAPTUREB_Enum;
68017 
68018 /* ===========================================  STIMER STMINTCLR CAPTUREA [9..9]  ============================================ */
68019 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREA                                                 */
68020   STIMER_STMINTCLR_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
68021 } STIMER_STMINTCLR_CAPTUREA_Enum;
68022 
68023 /* ===========================================  STIMER STMINTCLR OVERFLOW [8..8]  ============================================ */
68024 typedef enum {                                  /*!< STIMER_STMINTCLR_OVERFLOW                                                 */
68025   STIMER_STMINTCLR_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
68026 } STIMER_STMINTCLR_OVERFLOW_Enum;
68027 
68028 /* ===========================================  STIMER STMINTCLR COMPAREH [7..7]  ============================================ */
68029 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREH                                                 */
68030   STIMER_STMINTCLR_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68031 } STIMER_STMINTCLR_COMPAREH_Enum;
68032 
68033 /* ===========================================  STIMER STMINTCLR COMPAREG [6..6]  ============================================ */
68034 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREG                                                 */
68035   STIMER_STMINTCLR_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68036 } STIMER_STMINTCLR_COMPAREG_Enum;
68037 
68038 /* ===========================================  STIMER STMINTCLR COMPAREF [5..5]  ============================================ */
68039 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREF                                                 */
68040   STIMER_STMINTCLR_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68041 } STIMER_STMINTCLR_COMPAREF_Enum;
68042 
68043 /* ===========================================  STIMER STMINTCLR COMPAREE [4..4]  ============================================ */
68044 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREE                                                 */
68045   STIMER_STMINTCLR_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68046 } STIMER_STMINTCLR_COMPAREE_Enum;
68047 
68048 /* ===========================================  STIMER STMINTCLR COMPARED [3..3]  ============================================ */
68049 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPARED                                                 */
68050   STIMER_STMINTCLR_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68051 } STIMER_STMINTCLR_COMPARED_Enum;
68052 
68053 /* ===========================================  STIMER STMINTCLR COMPAREC [2..2]  ============================================ */
68054 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREC                                                 */
68055   STIMER_STMINTCLR_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68056 } STIMER_STMINTCLR_COMPAREC_Enum;
68057 
68058 /* ===========================================  STIMER STMINTCLR COMPAREB [1..1]  ============================================ */
68059 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREB                                                 */
68060   STIMER_STMINTCLR_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68061 } STIMER_STMINTCLR_COMPAREB_Enum;
68062 
68063 /* ===========================================  STIMER STMINTCLR COMPAREA [0..0]  ============================================ */
68064 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREA                                                 */
68065   STIMER_STMINTCLR_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68066 } STIMER_STMINTCLR_COMPAREA_Enum;
68067 
68068 /* =======================================================  STMINTSET  ======================================================= */
68069 /* ==========================================  STIMER STMINTSET CAPTURED [12..12]  =========================================== */
68070 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTURED                                                 */
68071   STIMER_STMINTSET_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
68072 } STIMER_STMINTSET_CAPTURED_Enum;
68073 
68074 /* ==========================================  STIMER STMINTSET CAPTUREC [11..11]  =========================================== */
68075 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREC                                                 */
68076   STIMER_STMINTSET_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
68077 } STIMER_STMINTSET_CAPTUREC_Enum;
68078 
68079 /* ==========================================  STIMER STMINTSET CAPTUREB [10..10]  =========================================== */
68080 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREB                                                 */
68081   STIMER_STMINTSET_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
68082 } STIMER_STMINTSET_CAPTUREB_Enum;
68083 
68084 /* ===========================================  STIMER STMINTSET CAPTUREA [9..9]  ============================================ */
68085 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREA                                                 */
68086   STIMER_STMINTSET_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
68087 } STIMER_STMINTSET_CAPTUREA_Enum;
68088 
68089 /* ===========================================  STIMER STMINTSET OVERFLOW [8..8]  ============================================ */
68090 typedef enum {                                  /*!< STIMER_STMINTSET_OVERFLOW                                                 */
68091   STIMER_STMINTSET_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
68092 } STIMER_STMINTSET_OVERFLOW_Enum;
68093 
68094 /* ===========================================  STIMER STMINTSET COMPAREH [7..7]  ============================================ */
68095 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREH                                                 */
68096   STIMER_STMINTSET_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68097 } STIMER_STMINTSET_COMPAREH_Enum;
68098 
68099 /* ===========================================  STIMER STMINTSET COMPAREG [6..6]  ============================================ */
68100 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREG                                                 */
68101   STIMER_STMINTSET_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68102 } STIMER_STMINTSET_COMPAREG_Enum;
68103 
68104 /* ===========================================  STIMER STMINTSET COMPAREF [5..5]  ============================================ */
68105 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREF                                                 */
68106   STIMER_STMINTSET_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68107 } STIMER_STMINTSET_COMPAREF_Enum;
68108 
68109 /* ===========================================  STIMER STMINTSET COMPAREE [4..4]  ============================================ */
68110 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREE                                                 */
68111   STIMER_STMINTSET_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68112 } STIMER_STMINTSET_COMPAREE_Enum;
68113 
68114 /* ===========================================  STIMER STMINTSET COMPARED [3..3]  ============================================ */
68115 typedef enum {                                  /*!< STIMER_STMINTSET_COMPARED                                                 */
68116   STIMER_STMINTSET_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68117 } STIMER_STMINTSET_COMPARED_Enum;
68118 
68119 /* ===========================================  STIMER STMINTSET COMPAREC [2..2]  ============================================ */
68120 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREC                                                 */
68121   STIMER_STMINTSET_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68122 } STIMER_STMINTSET_COMPAREC_Enum;
68123 
68124 /* ===========================================  STIMER STMINTSET COMPAREB [1..1]  ============================================ */
68125 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREB                                                 */
68126   STIMER_STMINTSET_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68127 } STIMER_STMINTSET_COMPAREB_Enum;
68128 
68129 /* ===========================================  STIMER STMINTSET COMPAREA [0..0]  ============================================ */
68130 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREA                                                 */
68131   STIMER_STMINTSET_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
68132 } STIMER_STMINTSET_COMPAREA_Enum;
68133 
68134 
68135 
68136 /* =========================================================================================================================== */
68137 /* ================                                           TIMER                                           ================ */
68138 /* =========================================================================================================================== */
68139 
68140 /* =========================================================  CTRL  ========================================================== */
68141 /* ========================================================  STATUS  ========================================================= */
68142 /* ========================================================  GLOBEN  ========================================================= */
68143 /* ==============================================  TIMER GLOBEN ADCEN [31..31]  ============================================== */
68144 typedef enum {                                  /*!< TIMER_GLOBEN_ADCEN                                                        */
68145   TIMER_GLOBEN_ADCEN_EN                = 1,     /*!< EN : Timer Enabled. TMREN enable is used.                                 */
68146   TIMER_GLOBEN_ADCEN_DIS               = 0,     /*!< DIS : Disable TIMER .                                                     */
68147 } TIMER_GLOBEN_ADCEN_Enum;
68148 
68149 /* ============================================  TIMER GLOBEN AUDADCEN [30..30]  ============================================= */
68150 typedef enum {                                  /*!< TIMER_GLOBEN_AUDADCEN                                                     */
68151   TIMER_GLOBEN_AUDADCEN_EN             = 1,     /*!< EN : Timer Enabled. TMREN enable is used.                                 */
68152   TIMER_GLOBEN_AUDADCEN_DIS            = 0,     /*!< DIS : Disable TIMER .                                                     */
68153 } TIMER_GLOBEN_AUDADCEN_Enum;
68154 
68155 /* =========================================  TIMER GLOBEN ENABLEALLINPUTS [29..29]  ========================================= */
68156 typedef enum {                                  /*!< TIMER_GLOBEN_ENABLEALLINPUTS                                              */
68157   TIMER_GLOBEN_ENABLEALLINPUTS_EN      = 1,     /*!< EN : Override to enable all inputs from GPIO                              */
68158   TIMER_GLOBEN_ENABLEALLINPUTS_DIS     = 0,     /*!< DIS : Normal mode where inputs from GPIO are enabled based on
68159                                                      enabled clock and triggers.                                               */
68160 } TIMER_GLOBEN_ENABLEALLINPUTS_Enum;
68161 
68162 /* ==============================================  TIMER GLOBEN ENB15 [15..15]  ============================================== */
68163 typedef enum {                                  /*!< TIMER_GLOBEN_ENB15                                                        */
68164   TIMER_GLOBEN_ENB15_EN                = 1,     /*!< EN : Timer Enabled. TMR15EN enable is used.                               */
68165   TIMER_GLOBEN_ENB15_DIS               = 0,     /*!< DIS : Disable TIMER 15.                                                   */
68166 } TIMER_GLOBEN_ENB15_Enum;
68167 
68168 /* ==============================================  TIMER GLOBEN ENB14 [14..14]  ============================================== */
68169 typedef enum {                                  /*!< TIMER_GLOBEN_ENB14                                                        */
68170   TIMER_GLOBEN_ENB14_EN                = 1,     /*!< EN : Timer Enabled. TMR14EN enable is used.                               */
68171   TIMER_GLOBEN_ENB14_DIS               = 0,     /*!< DIS : Disable TIMER 14.                                                   */
68172 } TIMER_GLOBEN_ENB14_Enum;
68173 
68174 /* ==============================================  TIMER GLOBEN ENB13 [13..13]  ============================================== */
68175 typedef enum {                                  /*!< TIMER_GLOBEN_ENB13                                                        */
68176   TIMER_GLOBEN_ENB13_EN                = 1,     /*!< EN : Timer Enabled. TMR13EN enable is used.                               */
68177   TIMER_GLOBEN_ENB13_DIS               = 0,     /*!< DIS : Disable TIMER 13.                                                   */
68178 } TIMER_GLOBEN_ENB13_Enum;
68179 
68180 /* ==============================================  TIMER GLOBEN ENB12 [12..12]  ============================================== */
68181 typedef enum {                                  /*!< TIMER_GLOBEN_ENB12                                                        */
68182   TIMER_GLOBEN_ENB12_EN                = 1,     /*!< EN : Timer Enabled. TMR12EN enable is used.                               */
68183   TIMER_GLOBEN_ENB12_DIS               = 0,     /*!< DIS : Disable TIMER 12.                                                   */
68184 } TIMER_GLOBEN_ENB12_Enum;
68185 
68186 /* ==============================================  TIMER GLOBEN ENB11 [11..11]  ============================================== */
68187 typedef enum {                                  /*!< TIMER_GLOBEN_ENB11                                                        */
68188   TIMER_GLOBEN_ENB11_EN                = 1,     /*!< EN : Timer Enabled. TMR11EN enable is used.                               */
68189   TIMER_GLOBEN_ENB11_DIS               = 0,     /*!< DIS : Disable TIMER 11.                                                   */
68190 } TIMER_GLOBEN_ENB11_Enum;
68191 
68192 /* ==============================================  TIMER GLOBEN ENB10 [10..10]  ============================================== */
68193 typedef enum {                                  /*!< TIMER_GLOBEN_ENB10                                                        */
68194   TIMER_GLOBEN_ENB10_EN                = 1,     /*!< EN : Timer Enabled. TMR10EN enable is used.                               */
68195   TIMER_GLOBEN_ENB10_DIS               = 0,     /*!< DIS : Disable TIMER 10.                                                   */
68196 } TIMER_GLOBEN_ENB10_Enum;
68197 
68198 /* ===============================================  TIMER GLOBEN ENB9 [9..9]  ================================================ */
68199 typedef enum {                                  /*!< TIMER_GLOBEN_ENB9                                                         */
68200   TIMER_GLOBEN_ENB9_EN                 = 1,     /*!< EN : Timer Enabled. TMR9EN enable is used.                                */
68201   TIMER_GLOBEN_ENB9_DIS                = 0,     /*!< DIS : Disable TIMER 9.                                                    */
68202 } TIMER_GLOBEN_ENB9_Enum;
68203 
68204 /* ===============================================  TIMER GLOBEN ENB8 [8..8]  ================================================ */
68205 typedef enum {                                  /*!< TIMER_GLOBEN_ENB8                                                         */
68206   TIMER_GLOBEN_ENB8_EN                 = 1,     /*!< EN : Timer Enabled. TMR8EN enable is used.                                */
68207   TIMER_GLOBEN_ENB8_DIS                = 0,     /*!< DIS : Disable TIMER 8.                                                    */
68208 } TIMER_GLOBEN_ENB8_Enum;
68209 
68210 /* ===============================================  TIMER GLOBEN ENB7 [7..7]  ================================================ */
68211 typedef enum {                                  /*!< TIMER_GLOBEN_ENB7                                                         */
68212   TIMER_GLOBEN_ENB7_EN                 = 1,     /*!< EN : Timer Enabled. TMR7EN enable is used.                                */
68213   TIMER_GLOBEN_ENB7_DIS                = 0,     /*!< DIS : Disable TIMER 7.                                                    */
68214 } TIMER_GLOBEN_ENB7_Enum;
68215 
68216 /* ===============================================  TIMER GLOBEN ENB6 [6..6]  ================================================ */
68217 typedef enum {                                  /*!< TIMER_GLOBEN_ENB6                                                         */
68218   TIMER_GLOBEN_ENB6_EN                 = 1,     /*!< EN : Timer Enabled. TMR6EN enable is used.                                */
68219   TIMER_GLOBEN_ENB6_DIS                = 0,     /*!< DIS : Disable TIMER 6.                                                    */
68220 } TIMER_GLOBEN_ENB6_Enum;
68221 
68222 /* ===============================================  TIMER GLOBEN ENB5 [5..5]  ================================================ */
68223 typedef enum {                                  /*!< TIMER_GLOBEN_ENB5                                                         */
68224   TIMER_GLOBEN_ENB5_EN                 = 1,     /*!< EN : Timer Enabled. TMR5EN enable is used.                                */
68225   TIMER_GLOBEN_ENB5_DIS                = 0,     /*!< DIS : Disable TIMER 5.                                                    */
68226 } TIMER_GLOBEN_ENB5_Enum;
68227 
68228 /* ===============================================  TIMER GLOBEN ENB4 [4..4]  ================================================ */
68229 typedef enum {                                  /*!< TIMER_GLOBEN_ENB4                                                         */
68230   TIMER_GLOBEN_ENB4_EN                 = 1,     /*!< EN : Timer Enabled. TMR4EN enable is used.                                */
68231   TIMER_GLOBEN_ENB4_DIS                = 0,     /*!< DIS : Disable TIMER 4.                                                    */
68232 } TIMER_GLOBEN_ENB4_Enum;
68233 
68234 /* ===============================================  TIMER GLOBEN ENB3 [3..3]  ================================================ */
68235 typedef enum {                                  /*!< TIMER_GLOBEN_ENB3                                                         */
68236   TIMER_GLOBEN_ENB3_EN                 = 1,     /*!< EN : Timer Enabled. TMR3EN enable is used.                                */
68237   TIMER_GLOBEN_ENB3_DIS                = 0,     /*!< DIS : Disable TIMER 3.                                                    */
68238 } TIMER_GLOBEN_ENB3_Enum;
68239 
68240 /* ===============================================  TIMER GLOBEN ENB2 [2..2]  ================================================ */
68241 typedef enum {                                  /*!< TIMER_GLOBEN_ENB2                                                         */
68242   TIMER_GLOBEN_ENB2_EN                 = 1,     /*!< EN : Timer Enabled. TMR2EN enable is used.                                */
68243   TIMER_GLOBEN_ENB2_DIS                = 0,     /*!< DIS : Disable TIMER 2.                                                    */
68244 } TIMER_GLOBEN_ENB2_Enum;
68245 
68246 /* ===============================================  TIMER GLOBEN ENB1 [1..1]  ================================================ */
68247 typedef enum {                                  /*!< TIMER_GLOBEN_ENB1                                                         */
68248   TIMER_GLOBEN_ENB1_EN                 = 1,     /*!< EN : Timer Enabled. TMR1EN enable is used.                                */
68249   TIMER_GLOBEN_ENB1_DIS                = 0,     /*!< DIS : Disable TIMER 1.                                                    */
68250 } TIMER_GLOBEN_ENB1_Enum;
68251 
68252 /* ===============================================  TIMER GLOBEN ENB0 [0..0]  ================================================ */
68253 typedef enum {                                  /*!< TIMER_GLOBEN_ENB0                                                         */
68254   TIMER_GLOBEN_ENB0_EN                 = 1,     /*!< EN : Timer Enabled. TMR0EN enable is used.                                */
68255   TIMER_GLOBEN_ENB0_DIS                = 0,     /*!< DIS : Disable TIMER 0.                                                    */
68256 } TIMER_GLOBEN_ENB0_Enum;
68257 
68258 /* =========================================================  INTEN  ========================================================= */
68259 /* ========================================================  INTSTAT  ======================================================== */
68260 /* ========================================================  INTCLR  ========================================================= */
68261 /* ========================================================  INTSET  ========================================================= */
68262 /* ========================================================  OUTCFG0  ======================================================== */
68263 /* ============================================  TIMER OUTCFG0 OUTCFG3 [24..29]  ============================================= */
68264 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG3                                                     */
68265   TIMER_OUTCFG0_OUTCFG3_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68266   TIMER_OUTCFG0_OUTCFG3_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68267   TIMER_OUTCFG0_OUTCFG3_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68268   TIMER_OUTCFG0_OUTCFG3_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68269   TIMER_OUTCFG0_OUTCFG3_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68270   TIMER_OUTCFG0_OUTCFG3_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68271   TIMER_OUTCFG0_OUTCFG3_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68272   TIMER_OUTCFG0_OUTCFG3_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68273   TIMER_OUTCFG0_OUTCFG3_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68274   TIMER_OUTCFG0_OUTCFG3_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68275   TIMER_OUTCFG0_OUTCFG3_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68276   TIMER_OUTCFG0_OUTCFG3_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68277   TIMER_OUTCFG0_OUTCFG3_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68278   TIMER_OUTCFG0_OUTCFG3_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68279   TIMER_OUTCFG0_OUTCFG3_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68280   TIMER_OUTCFG0_OUTCFG3_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68281   TIMER_OUTCFG0_OUTCFG3_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68282   TIMER_OUTCFG0_OUTCFG3_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68283   TIMER_OUTCFG0_OUTCFG3_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68284   TIMER_OUTCFG0_OUTCFG3_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68285   TIMER_OUTCFG0_OUTCFG3_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68286   TIMER_OUTCFG0_OUTCFG3_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68287   TIMER_OUTCFG0_OUTCFG3_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68288   TIMER_OUTCFG0_OUTCFG3_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68289   TIMER_OUTCFG0_OUTCFG3_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68290   TIMER_OUTCFG0_OUTCFG3_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68291   TIMER_OUTCFG0_OUTCFG3_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68292   TIMER_OUTCFG0_OUTCFG3_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68293   TIMER_OUTCFG0_OUTCFG3_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68294   TIMER_OUTCFG0_OUTCFG3_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68295   TIMER_OUTCFG0_OUTCFG3_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68296   TIMER_OUTCFG0_OUTCFG3_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68297   TIMER_OUTCFG0_OUTCFG3_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68298   TIMER_OUTCFG0_OUTCFG3_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68299   TIMER_OUTCFG0_OUTCFG3_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68300   TIMER_OUTCFG0_OUTCFG3_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68301   TIMER_OUTCFG0_OUTCFG3_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68302   TIMER_OUTCFG0_OUTCFG3_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68303   TIMER_OUTCFG0_OUTCFG3_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68304   TIMER_OUTCFG0_OUTCFG3_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68305   TIMER_OUTCFG0_OUTCFG3_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68306 } TIMER_OUTCFG0_OUTCFG3_Enum;
68307 
68308 /* ============================================  TIMER OUTCFG0 OUTCFG2 [16..21]  ============================================= */
68309 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG2                                                     */
68310   TIMER_OUTCFG0_OUTCFG2_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68311   TIMER_OUTCFG0_OUTCFG2_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68312   TIMER_OUTCFG0_OUTCFG2_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68313   TIMER_OUTCFG0_OUTCFG2_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68314   TIMER_OUTCFG0_OUTCFG2_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68315   TIMER_OUTCFG0_OUTCFG2_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68316   TIMER_OUTCFG0_OUTCFG2_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68317   TIMER_OUTCFG0_OUTCFG2_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68318   TIMER_OUTCFG0_OUTCFG2_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68319   TIMER_OUTCFG0_OUTCFG2_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68320   TIMER_OUTCFG0_OUTCFG2_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68321   TIMER_OUTCFG0_OUTCFG2_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68322   TIMER_OUTCFG0_OUTCFG2_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68323   TIMER_OUTCFG0_OUTCFG2_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68324   TIMER_OUTCFG0_OUTCFG2_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68325   TIMER_OUTCFG0_OUTCFG2_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68326   TIMER_OUTCFG0_OUTCFG2_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68327   TIMER_OUTCFG0_OUTCFG2_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68328   TIMER_OUTCFG0_OUTCFG2_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68329   TIMER_OUTCFG0_OUTCFG2_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68330   TIMER_OUTCFG0_OUTCFG2_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68331   TIMER_OUTCFG0_OUTCFG2_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68332   TIMER_OUTCFG0_OUTCFG2_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68333   TIMER_OUTCFG0_OUTCFG2_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68334   TIMER_OUTCFG0_OUTCFG2_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68335   TIMER_OUTCFG0_OUTCFG2_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68336   TIMER_OUTCFG0_OUTCFG2_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68337   TIMER_OUTCFG0_OUTCFG2_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68338   TIMER_OUTCFG0_OUTCFG2_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68339   TIMER_OUTCFG0_OUTCFG2_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68340   TIMER_OUTCFG0_OUTCFG2_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68341   TIMER_OUTCFG0_OUTCFG2_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68342   TIMER_OUTCFG0_OUTCFG2_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68343   TIMER_OUTCFG0_OUTCFG2_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68344   TIMER_OUTCFG0_OUTCFG2_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68345   TIMER_OUTCFG0_OUTCFG2_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68346   TIMER_OUTCFG0_OUTCFG2_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68347   TIMER_OUTCFG0_OUTCFG2_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68348   TIMER_OUTCFG0_OUTCFG2_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68349   TIMER_OUTCFG0_OUTCFG2_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68350   TIMER_OUTCFG0_OUTCFG2_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68351 } TIMER_OUTCFG0_OUTCFG2_Enum;
68352 
68353 /* =============================================  TIMER OUTCFG0 OUTCFG1 [8..13]  ============================================= */
68354 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG1                                                     */
68355   TIMER_OUTCFG0_OUTCFG1_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68356   TIMER_OUTCFG0_OUTCFG1_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68357   TIMER_OUTCFG0_OUTCFG1_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68358   TIMER_OUTCFG0_OUTCFG1_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68359   TIMER_OUTCFG0_OUTCFG1_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68360   TIMER_OUTCFG0_OUTCFG1_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68361   TIMER_OUTCFG0_OUTCFG1_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68362   TIMER_OUTCFG0_OUTCFG1_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68363   TIMER_OUTCFG0_OUTCFG1_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68364   TIMER_OUTCFG0_OUTCFG1_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68365   TIMER_OUTCFG0_OUTCFG1_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68366   TIMER_OUTCFG0_OUTCFG1_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68367   TIMER_OUTCFG0_OUTCFG1_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68368   TIMER_OUTCFG0_OUTCFG1_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68369   TIMER_OUTCFG0_OUTCFG1_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68370   TIMER_OUTCFG0_OUTCFG1_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68371   TIMER_OUTCFG0_OUTCFG1_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68372   TIMER_OUTCFG0_OUTCFG1_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68373   TIMER_OUTCFG0_OUTCFG1_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68374   TIMER_OUTCFG0_OUTCFG1_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68375   TIMER_OUTCFG0_OUTCFG1_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68376   TIMER_OUTCFG0_OUTCFG1_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68377   TIMER_OUTCFG0_OUTCFG1_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68378   TIMER_OUTCFG0_OUTCFG1_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68379   TIMER_OUTCFG0_OUTCFG1_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68380   TIMER_OUTCFG0_OUTCFG1_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68381   TIMER_OUTCFG0_OUTCFG1_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68382   TIMER_OUTCFG0_OUTCFG1_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68383   TIMER_OUTCFG0_OUTCFG1_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68384   TIMER_OUTCFG0_OUTCFG1_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68385   TIMER_OUTCFG0_OUTCFG1_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68386   TIMER_OUTCFG0_OUTCFG1_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68387   TIMER_OUTCFG0_OUTCFG1_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68388   TIMER_OUTCFG0_OUTCFG1_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68389   TIMER_OUTCFG0_OUTCFG1_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68390   TIMER_OUTCFG0_OUTCFG1_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68391   TIMER_OUTCFG0_OUTCFG1_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68392   TIMER_OUTCFG0_OUTCFG1_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68393   TIMER_OUTCFG0_OUTCFG1_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68394   TIMER_OUTCFG0_OUTCFG1_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68395   TIMER_OUTCFG0_OUTCFG1_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68396 } TIMER_OUTCFG0_OUTCFG1_Enum;
68397 
68398 /* =============================================  TIMER OUTCFG0 OUTCFG0 [0..5]  ============================================== */
68399 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG0                                                     */
68400   TIMER_OUTCFG0_OUTCFG0_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68401   TIMER_OUTCFG0_OUTCFG0_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68402   TIMER_OUTCFG0_OUTCFG0_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68403   TIMER_OUTCFG0_OUTCFG0_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68404   TIMER_OUTCFG0_OUTCFG0_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68405   TIMER_OUTCFG0_OUTCFG0_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68406   TIMER_OUTCFG0_OUTCFG0_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68407   TIMER_OUTCFG0_OUTCFG0_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68408   TIMER_OUTCFG0_OUTCFG0_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68409   TIMER_OUTCFG0_OUTCFG0_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68410   TIMER_OUTCFG0_OUTCFG0_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68411   TIMER_OUTCFG0_OUTCFG0_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68412   TIMER_OUTCFG0_OUTCFG0_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68413   TIMER_OUTCFG0_OUTCFG0_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68414   TIMER_OUTCFG0_OUTCFG0_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68415   TIMER_OUTCFG0_OUTCFG0_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68416   TIMER_OUTCFG0_OUTCFG0_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68417   TIMER_OUTCFG0_OUTCFG0_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68418   TIMER_OUTCFG0_OUTCFG0_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68419   TIMER_OUTCFG0_OUTCFG0_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68420   TIMER_OUTCFG0_OUTCFG0_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68421   TIMER_OUTCFG0_OUTCFG0_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68422   TIMER_OUTCFG0_OUTCFG0_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68423   TIMER_OUTCFG0_OUTCFG0_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68424   TIMER_OUTCFG0_OUTCFG0_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68425   TIMER_OUTCFG0_OUTCFG0_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68426   TIMER_OUTCFG0_OUTCFG0_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68427   TIMER_OUTCFG0_OUTCFG0_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68428   TIMER_OUTCFG0_OUTCFG0_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68429   TIMER_OUTCFG0_OUTCFG0_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68430   TIMER_OUTCFG0_OUTCFG0_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68431   TIMER_OUTCFG0_OUTCFG0_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68432   TIMER_OUTCFG0_OUTCFG0_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68433   TIMER_OUTCFG0_OUTCFG0_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68434   TIMER_OUTCFG0_OUTCFG0_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68435   TIMER_OUTCFG0_OUTCFG0_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68436   TIMER_OUTCFG0_OUTCFG0_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68437   TIMER_OUTCFG0_OUTCFG0_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68438   TIMER_OUTCFG0_OUTCFG0_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68439   TIMER_OUTCFG0_OUTCFG0_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68440   TIMER_OUTCFG0_OUTCFG0_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68441 } TIMER_OUTCFG0_OUTCFG0_Enum;
68442 
68443 /* ========================================================  OUTCFG1  ======================================================== */
68444 /* ============================================  TIMER OUTCFG1 OUTCFG7 [24..29]  ============================================= */
68445 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG7                                                     */
68446   TIMER_OUTCFG1_OUTCFG7_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68447   TIMER_OUTCFG1_OUTCFG7_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68448   TIMER_OUTCFG1_OUTCFG7_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68449   TIMER_OUTCFG1_OUTCFG7_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68450   TIMER_OUTCFG1_OUTCFG7_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68451   TIMER_OUTCFG1_OUTCFG7_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68452   TIMER_OUTCFG1_OUTCFG7_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68453   TIMER_OUTCFG1_OUTCFG7_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68454   TIMER_OUTCFG1_OUTCFG7_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68455   TIMER_OUTCFG1_OUTCFG7_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68456   TIMER_OUTCFG1_OUTCFG7_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68457   TIMER_OUTCFG1_OUTCFG7_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68458   TIMER_OUTCFG1_OUTCFG7_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68459   TIMER_OUTCFG1_OUTCFG7_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68460   TIMER_OUTCFG1_OUTCFG7_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68461   TIMER_OUTCFG1_OUTCFG7_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68462   TIMER_OUTCFG1_OUTCFG7_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68463   TIMER_OUTCFG1_OUTCFG7_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68464   TIMER_OUTCFG1_OUTCFG7_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68465   TIMER_OUTCFG1_OUTCFG7_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68466   TIMER_OUTCFG1_OUTCFG7_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68467   TIMER_OUTCFG1_OUTCFG7_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68468   TIMER_OUTCFG1_OUTCFG7_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68469   TIMER_OUTCFG1_OUTCFG7_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68470   TIMER_OUTCFG1_OUTCFG7_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68471   TIMER_OUTCFG1_OUTCFG7_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68472   TIMER_OUTCFG1_OUTCFG7_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68473   TIMER_OUTCFG1_OUTCFG7_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68474   TIMER_OUTCFG1_OUTCFG7_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68475   TIMER_OUTCFG1_OUTCFG7_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68476   TIMER_OUTCFG1_OUTCFG7_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68477   TIMER_OUTCFG1_OUTCFG7_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68478   TIMER_OUTCFG1_OUTCFG7_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68479   TIMER_OUTCFG1_OUTCFG7_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68480   TIMER_OUTCFG1_OUTCFG7_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68481   TIMER_OUTCFG1_OUTCFG7_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68482   TIMER_OUTCFG1_OUTCFG7_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68483   TIMER_OUTCFG1_OUTCFG7_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68484   TIMER_OUTCFG1_OUTCFG7_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68485   TIMER_OUTCFG1_OUTCFG7_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68486   TIMER_OUTCFG1_OUTCFG7_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68487 } TIMER_OUTCFG1_OUTCFG7_Enum;
68488 
68489 /* ============================================  TIMER OUTCFG1 OUTCFG6 [16..21]  ============================================= */
68490 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG6                                                     */
68491   TIMER_OUTCFG1_OUTCFG6_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68492   TIMER_OUTCFG1_OUTCFG6_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68493   TIMER_OUTCFG1_OUTCFG6_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68494   TIMER_OUTCFG1_OUTCFG6_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68495   TIMER_OUTCFG1_OUTCFG6_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68496   TIMER_OUTCFG1_OUTCFG6_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68497   TIMER_OUTCFG1_OUTCFG6_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68498   TIMER_OUTCFG1_OUTCFG6_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68499   TIMER_OUTCFG1_OUTCFG6_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68500   TIMER_OUTCFG1_OUTCFG6_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68501   TIMER_OUTCFG1_OUTCFG6_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68502   TIMER_OUTCFG1_OUTCFG6_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68503   TIMER_OUTCFG1_OUTCFG6_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68504   TIMER_OUTCFG1_OUTCFG6_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68505   TIMER_OUTCFG1_OUTCFG6_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68506   TIMER_OUTCFG1_OUTCFG6_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68507   TIMER_OUTCFG1_OUTCFG6_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68508   TIMER_OUTCFG1_OUTCFG6_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68509   TIMER_OUTCFG1_OUTCFG6_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68510   TIMER_OUTCFG1_OUTCFG6_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68511   TIMER_OUTCFG1_OUTCFG6_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68512   TIMER_OUTCFG1_OUTCFG6_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68513   TIMER_OUTCFG1_OUTCFG6_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68514   TIMER_OUTCFG1_OUTCFG6_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68515   TIMER_OUTCFG1_OUTCFG6_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68516   TIMER_OUTCFG1_OUTCFG6_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68517   TIMER_OUTCFG1_OUTCFG6_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68518   TIMER_OUTCFG1_OUTCFG6_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68519   TIMER_OUTCFG1_OUTCFG6_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68520   TIMER_OUTCFG1_OUTCFG6_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68521   TIMER_OUTCFG1_OUTCFG6_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68522   TIMER_OUTCFG1_OUTCFG6_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68523   TIMER_OUTCFG1_OUTCFG6_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68524   TIMER_OUTCFG1_OUTCFG6_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68525   TIMER_OUTCFG1_OUTCFG6_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68526   TIMER_OUTCFG1_OUTCFG6_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68527   TIMER_OUTCFG1_OUTCFG6_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68528   TIMER_OUTCFG1_OUTCFG6_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68529   TIMER_OUTCFG1_OUTCFG6_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68530   TIMER_OUTCFG1_OUTCFG6_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68531   TIMER_OUTCFG1_OUTCFG6_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68532 } TIMER_OUTCFG1_OUTCFG6_Enum;
68533 
68534 /* =============================================  TIMER OUTCFG1 OUTCFG5 [8..13]  ============================================= */
68535 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG5                                                     */
68536   TIMER_OUTCFG1_OUTCFG5_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68537   TIMER_OUTCFG1_OUTCFG5_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68538   TIMER_OUTCFG1_OUTCFG5_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68539   TIMER_OUTCFG1_OUTCFG5_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68540   TIMER_OUTCFG1_OUTCFG5_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68541   TIMER_OUTCFG1_OUTCFG5_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68542   TIMER_OUTCFG1_OUTCFG5_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68543   TIMER_OUTCFG1_OUTCFG5_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68544   TIMER_OUTCFG1_OUTCFG5_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68545   TIMER_OUTCFG1_OUTCFG5_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68546   TIMER_OUTCFG1_OUTCFG5_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68547   TIMER_OUTCFG1_OUTCFG5_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68548   TIMER_OUTCFG1_OUTCFG5_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68549   TIMER_OUTCFG1_OUTCFG5_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68550   TIMER_OUTCFG1_OUTCFG5_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68551   TIMER_OUTCFG1_OUTCFG5_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68552   TIMER_OUTCFG1_OUTCFG5_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68553   TIMER_OUTCFG1_OUTCFG5_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68554   TIMER_OUTCFG1_OUTCFG5_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68555   TIMER_OUTCFG1_OUTCFG5_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68556   TIMER_OUTCFG1_OUTCFG5_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68557   TIMER_OUTCFG1_OUTCFG5_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68558   TIMER_OUTCFG1_OUTCFG5_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68559   TIMER_OUTCFG1_OUTCFG5_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68560   TIMER_OUTCFG1_OUTCFG5_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68561   TIMER_OUTCFG1_OUTCFG5_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68562   TIMER_OUTCFG1_OUTCFG5_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68563   TIMER_OUTCFG1_OUTCFG5_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68564   TIMER_OUTCFG1_OUTCFG5_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68565   TIMER_OUTCFG1_OUTCFG5_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68566   TIMER_OUTCFG1_OUTCFG5_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68567   TIMER_OUTCFG1_OUTCFG5_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68568   TIMER_OUTCFG1_OUTCFG5_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68569   TIMER_OUTCFG1_OUTCFG5_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68570   TIMER_OUTCFG1_OUTCFG5_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68571   TIMER_OUTCFG1_OUTCFG5_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68572   TIMER_OUTCFG1_OUTCFG5_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68573   TIMER_OUTCFG1_OUTCFG5_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68574   TIMER_OUTCFG1_OUTCFG5_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68575   TIMER_OUTCFG1_OUTCFG5_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68576   TIMER_OUTCFG1_OUTCFG5_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68577 } TIMER_OUTCFG1_OUTCFG5_Enum;
68578 
68579 /* =============================================  TIMER OUTCFG1 OUTCFG4 [0..5]  ============================================== */
68580 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG4                                                     */
68581   TIMER_OUTCFG1_OUTCFG4_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68582   TIMER_OUTCFG1_OUTCFG4_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68583   TIMER_OUTCFG1_OUTCFG4_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68584   TIMER_OUTCFG1_OUTCFG4_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68585   TIMER_OUTCFG1_OUTCFG4_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68586   TIMER_OUTCFG1_OUTCFG4_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68587   TIMER_OUTCFG1_OUTCFG4_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68588   TIMER_OUTCFG1_OUTCFG4_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68589   TIMER_OUTCFG1_OUTCFG4_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68590   TIMER_OUTCFG1_OUTCFG4_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68591   TIMER_OUTCFG1_OUTCFG4_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68592   TIMER_OUTCFG1_OUTCFG4_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68593   TIMER_OUTCFG1_OUTCFG4_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68594   TIMER_OUTCFG1_OUTCFG4_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68595   TIMER_OUTCFG1_OUTCFG4_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68596   TIMER_OUTCFG1_OUTCFG4_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68597   TIMER_OUTCFG1_OUTCFG4_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68598   TIMER_OUTCFG1_OUTCFG4_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68599   TIMER_OUTCFG1_OUTCFG4_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68600   TIMER_OUTCFG1_OUTCFG4_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68601   TIMER_OUTCFG1_OUTCFG4_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68602   TIMER_OUTCFG1_OUTCFG4_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68603   TIMER_OUTCFG1_OUTCFG4_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68604   TIMER_OUTCFG1_OUTCFG4_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68605   TIMER_OUTCFG1_OUTCFG4_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68606   TIMER_OUTCFG1_OUTCFG4_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68607   TIMER_OUTCFG1_OUTCFG4_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68608   TIMER_OUTCFG1_OUTCFG4_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68609   TIMER_OUTCFG1_OUTCFG4_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68610   TIMER_OUTCFG1_OUTCFG4_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68611   TIMER_OUTCFG1_OUTCFG4_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68612   TIMER_OUTCFG1_OUTCFG4_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68613   TIMER_OUTCFG1_OUTCFG4_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68614   TIMER_OUTCFG1_OUTCFG4_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68615   TIMER_OUTCFG1_OUTCFG4_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68616   TIMER_OUTCFG1_OUTCFG4_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68617   TIMER_OUTCFG1_OUTCFG4_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68618   TIMER_OUTCFG1_OUTCFG4_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68619   TIMER_OUTCFG1_OUTCFG4_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68620   TIMER_OUTCFG1_OUTCFG4_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68621   TIMER_OUTCFG1_OUTCFG4_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68622 } TIMER_OUTCFG1_OUTCFG4_Enum;
68623 
68624 /* ========================================================  OUTCFG2  ======================================================== */
68625 /* ============================================  TIMER OUTCFG2 OUTCFG11 [24..29]  ============================================ */
68626 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG11                                                    */
68627   TIMER_OUTCFG2_OUTCFG11_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68628   TIMER_OUTCFG2_OUTCFG11_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68629   TIMER_OUTCFG2_OUTCFG11_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68630   TIMER_OUTCFG2_OUTCFG11_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68631   TIMER_OUTCFG2_OUTCFG11_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68632   TIMER_OUTCFG2_OUTCFG11_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68633   TIMER_OUTCFG2_OUTCFG11_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68634   TIMER_OUTCFG2_OUTCFG11_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68635   TIMER_OUTCFG2_OUTCFG11_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68636   TIMER_OUTCFG2_OUTCFG11_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68637   TIMER_OUTCFG2_OUTCFG11_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68638   TIMER_OUTCFG2_OUTCFG11_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68639   TIMER_OUTCFG2_OUTCFG11_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68640   TIMER_OUTCFG2_OUTCFG11_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68641   TIMER_OUTCFG2_OUTCFG11_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68642   TIMER_OUTCFG2_OUTCFG11_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68643   TIMER_OUTCFG2_OUTCFG11_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68644   TIMER_OUTCFG2_OUTCFG11_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68645   TIMER_OUTCFG2_OUTCFG11_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68646   TIMER_OUTCFG2_OUTCFG11_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68647   TIMER_OUTCFG2_OUTCFG11_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68648   TIMER_OUTCFG2_OUTCFG11_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68649   TIMER_OUTCFG2_OUTCFG11_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68650   TIMER_OUTCFG2_OUTCFG11_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68651   TIMER_OUTCFG2_OUTCFG11_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68652   TIMER_OUTCFG2_OUTCFG11_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68653   TIMER_OUTCFG2_OUTCFG11_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68654   TIMER_OUTCFG2_OUTCFG11_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68655   TIMER_OUTCFG2_OUTCFG11_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68656   TIMER_OUTCFG2_OUTCFG11_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68657   TIMER_OUTCFG2_OUTCFG11_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68658   TIMER_OUTCFG2_OUTCFG11_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68659   TIMER_OUTCFG2_OUTCFG11_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68660   TIMER_OUTCFG2_OUTCFG11_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68661   TIMER_OUTCFG2_OUTCFG11_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68662   TIMER_OUTCFG2_OUTCFG11_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68663   TIMER_OUTCFG2_OUTCFG11_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68664   TIMER_OUTCFG2_OUTCFG11_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68665   TIMER_OUTCFG2_OUTCFG11_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68666   TIMER_OUTCFG2_OUTCFG11_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68667   TIMER_OUTCFG2_OUTCFG11_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
68668 } TIMER_OUTCFG2_OUTCFG11_Enum;
68669 
68670 /* ============================================  TIMER OUTCFG2 OUTCFG10 [16..21]  ============================================ */
68671 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG10                                                    */
68672   TIMER_OUTCFG2_OUTCFG10_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68673   TIMER_OUTCFG2_OUTCFG10_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68674   TIMER_OUTCFG2_OUTCFG10_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68675   TIMER_OUTCFG2_OUTCFG10_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68676   TIMER_OUTCFG2_OUTCFG10_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68677   TIMER_OUTCFG2_OUTCFG10_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68678   TIMER_OUTCFG2_OUTCFG10_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68679   TIMER_OUTCFG2_OUTCFG10_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68680   TIMER_OUTCFG2_OUTCFG10_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68681   TIMER_OUTCFG2_OUTCFG10_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68682   TIMER_OUTCFG2_OUTCFG10_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68683   TIMER_OUTCFG2_OUTCFG10_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68684   TIMER_OUTCFG2_OUTCFG10_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68685   TIMER_OUTCFG2_OUTCFG10_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68686   TIMER_OUTCFG2_OUTCFG10_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68687   TIMER_OUTCFG2_OUTCFG10_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68688   TIMER_OUTCFG2_OUTCFG10_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68689   TIMER_OUTCFG2_OUTCFG10_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68690   TIMER_OUTCFG2_OUTCFG10_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68691   TIMER_OUTCFG2_OUTCFG10_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68692   TIMER_OUTCFG2_OUTCFG10_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68693   TIMER_OUTCFG2_OUTCFG10_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68694   TIMER_OUTCFG2_OUTCFG10_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68695   TIMER_OUTCFG2_OUTCFG10_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68696   TIMER_OUTCFG2_OUTCFG10_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68697   TIMER_OUTCFG2_OUTCFG10_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68698   TIMER_OUTCFG2_OUTCFG10_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68699   TIMER_OUTCFG2_OUTCFG10_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68700   TIMER_OUTCFG2_OUTCFG10_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68701   TIMER_OUTCFG2_OUTCFG10_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68702   TIMER_OUTCFG2_OUTCFG10_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68703   TIMER_OUTCFG2_OUTCFG10_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68704   TIMER_OUTCFG2_OUTCFG10_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68705   TIMER_OUTCFG2_OUTCFG10_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68706   TIMER_OUTCFG2_OUTCFG10_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68707   TIMER_OUTCFG2_OUTCFG10_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68708   TIMER_OUTCFG2_OUTCFG10_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68709   TIMER_OUTCFG2_OUTCFG10_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68710   TIMER_OUTCFG2_OUTCFG10_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68711   TIMER_OUTCFG2_OUTCFG10_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68712   TIMER_OUTCFG2_OUTCFG10_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
68713 } TIMER_OUTCFG2_OUTCFG10_Enum;
68714 
68715 /* =============================================  TIMER OUTCFG2 OUTCFG9 [8..13]  ============================================= */
68716 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG9                                                     */
68717   TIMER_OUTCFG2_OUTCFG9_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68718   TIMER_OUTCFG2_OUTCFG9_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68719   TIMER_OUTCFG2_OUTCFG9_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68720   TIMER_OUTCFG2_OUTCFG9_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68721   TIMER_OUTCFG2_OUTCFG9_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68722   TIMER_OUTCFG2_OUTCFG9_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68723   TIMER_OUTCFG2_OUTCFG9_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68724   TIMER_OUTCFG2_OUTCFG9_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68725   TIMER_OUTCFG2_OUTCFG9_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68726   TIMER_OUTCFG2_OUTCFG9_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68727   TIMER_OUTCFG2_OUTCFG9_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68728   TIMER_OUTCFG2_OUTCFG9_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68729   TIMER_OUTCFG2_OUTCFG9_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68730   TIMER_OUTCFG2_OUTCFG9_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68731   TIMER_OUTCFG2_OUTCFG9_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68732   TIMER_OUTCFG2_OUTCFG9_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68733   TIMER_OUTCFG2_OUTCFG9_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68734   TIMER_OUTCFG2_OUTCFG9_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68735   TIMER_OUTCFG2_OUTCFG9_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68736   TIMER_OUTCFG2_OUTCFG9_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68737   TIMER_OUTCFG2_OUTCFG9_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68738   TIMER_OUTCFG2_OUTCFG9_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68739   TIMER_OUTCFG2_OUTCFG9_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68740   TIMER_OUTCFG2_OUTCFG9_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68741   TIMER_OUTCFG2_OUTCFG9_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68742   TIMER_OUTCFG2_OUTCFG9_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68743   TIMER_OUTCFG2_OUTCFG9_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68744   TIMER_OUTCFG2_OUTCFG9_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68745   TIMER_OUTCFG2_OUTCFG9_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68746   TIMER_OUTCFG2_OUTCFG9_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68747   TIMER_OUTCFG2_OUTCFG9_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68748   TIMER_OUTCFG2_OUTCFG9_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68749   TIMER_OUTCFG2_OUTCFG9_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68750   TIMER_OUTCFG2_OUTCFG9_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68751   TIMER_OUTCFG2_OUTCFG9_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68752   TIMER_OUTCFG2_OUTCFG9_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68753   TIMER_OUTCFG2_OUTCFG9_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68754   TIMER_OUTCFG2_OUTCFG9_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68755   TIMER_OUTCFG2_OUTCFG9_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68756   TIMER_OUTCFG2_OUTCFG9_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68757   TIMER_OUTCFG2_OUTCFG9_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68758 } TIMER_OUTCFG2_OUTCFG9_Enum;
68759 
68760 /* =============================================  TIMER OUTCFG2 OUTCFG8 [0..5]  ============================================== */
68761 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG8                                                     */
68762   TIMER_OUTCFG2_OUTCFG8_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68763   TIMER_OUTCFG2_OUTCFG8_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68764   TIMER_OUTCFG2_OUTCFG8_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68765   TIMER_OUTCFG2_OUTCFG8_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68766   TIMER_OUTCFG2_OUTCFG8_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68767   TIMER_OUTCFG2_OUTCFG8_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68768   TIMER_OUTCFG2_OUTCFG8_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68769   TIMER_OUTCFG2_OUTCFG8_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68770   TIMER_OUTCFG2_OUTCFG8_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68771   TIMER_OUTCFG2_OUTCFG8_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68772   TIMER_OUTCFG2_OUTCFG8_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68773   TIMER_OUTCFG2_OUTCFG8_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68774   TIMER_OUTCFG2_OUTCFG8_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68775   TIMER_OUTCFG2_OUTCFG8_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68776   TIMER_OUTCFG2_OUTCFG8_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68777   TIMER_OUTCFG2_OUTCFG8_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68778   TIMER_OUTCFG2_OUTCFG8_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68779   TIMER_OUTCFG2_OUTCFG8_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68780   TIMER_OUTCFG2_OUTCFG8_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68781   TIMER_OUTCFG2_OUTCFG8_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68782   TIMER_OUTCFG2_OUTCFG8_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68783   TIMER_OUTCFG2_OUTCFG8_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68784   TIMER_OUTCFG2_OUTCFG8_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68785   TIMER_OUTCFG2_OUTCFG8_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68786   TIMER_OUTCFG2_OUTCFG8_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68787   TIMER_OUTCFG2_OUTCFG8_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68788   TIMER_OUTCFG2_OUTCFG8_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68789   TIMER_OUTCFG2_OUTCFG8_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68790   TIMER_OUTCFG2_OUTCFG8_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68791   TIMER_OUTCFG2_OUTCFG8_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68792   TIMER_OUTCFG2_OUTCFG8_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68793   TIMER_OUTCFG2_OUTCFG8_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68794   TIMER_OUTCFG2_OUTCFG8_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68795   TIMER_OUTCFG2_OUTCFG8_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68796   TIMER_OUTCFG2_OUTCFG8_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68797   TIMER_OUTCFG2_OUTCFG8_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68798   TIMER_OUTCFG2_OUTCFG8_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68799   TIMER_OUTCFG2_OUTCFG8_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68800   TIMER_OUTCFG2_OUTCFG8_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68801   TIMER_OUTCFG2_OUTCFG8_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68802   TIMER_OUTCFG2_OUTCFG8_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
68803 } TIMER_OUTCFG2_OUTCFG8_Enum;
68804 
68805 /* ========================================================  OUTCFG3  ======================================================== */
68806 /* ============================================  TIMER OUTCFG3 OUTCFG15 [24..29]  ============================================ */
68807 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG15                                                    */
68808   TIMER_OUTCFG3_OUTCFG15_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68809   TIMER_OUTCFG3_OUTCFG15_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68810   TIMER_OUTCFG3_OUTCFG15_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68811   TIMER_OUTCFG3_OUTCFG15_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68812   TIMER_OUTCFG3_OUTCFG15_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68813   TIMER_OUTCFG3_OUTCFG15_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68814   TIMER_OUTCFG3_OUTCFG15_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68815   TIMER_OUTCFG3_OUTCFG15_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68816   TIMER_OUTCFG3_OUTCFG15_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68817   TIMER_OUTCFG3_OUTCFG15_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68818   TIMER_OUTCFG3_OUTCFG15_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68819   TIMER_OUTCFG3_OUTCFG15_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68820   TIMER_OUTCFG3_OUTCFG15_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68821   TIMER_OUTCFG3_OUTCFG15_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68822   TIMER_OUTCFG3_OUTCFG15_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68823   TIMER_OUTCFG3_OUTCFG15_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68824   TIMER_OUTCFG3_OUTCFG15_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68825   TIMER_OUTCFG3_OUTCFG15_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68826   TIMER_OUTCFG3_OUTCFG15_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68827   TIMER_OUTCFG3_OUTCFG15_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68828   TIMER_OUTCFG3_OUTCFG15_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68829   TIMER_OUTCFG3_OUTCFG15_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68830   TIMER_OUTCFG3_OUTCFG15_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68831   TIMER_OUTCFG3_OUTCFG15_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68832   TIMER_OUTCFG3_OUTCFG15_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68833   TIMER_OUTCFG3_OUTCFG15_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68834   TIMER_OUTCFG3_OUTCFG15_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68835   TIMER_OUTCFG3_OUTCFG15_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68836   TIMER_OUTCFG3_OUTCFG15_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68837   TIMER_OUTCFG3_OUTCFG15_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68838   TIMER_OUTCFG3_OUTCFG15_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68839   TIMER_OUTCFG3_OUTCFG15_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68840   TIMER_OUTCFG3_OUTCFG15_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68841   TIMER_OUTCFG3_OUTCFG15_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68842   TIMER_OUTCFG3_OUTCFG15_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68843   TIMER_OUTCFG3_OUTCFG15_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68844   TIMER_OUTCFG3_OUTCFG15_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68845   TIMER_OUTCFG3_OUTCFG15_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68846   TIMER_OUTCFG3_OUTCFG15_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68847   TIMER_OUTCFG3_OUTCFG15_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68848   TIMER_OUTCFG3_OUTCFG15_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
68849 } TIMER_OUTCFG3_OUTCFG15_Enum;
68850 
68851 /* ============================================  TIMER OUTCFG3 OUTCFG14 [16..21]  ============================================ */
68852 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG14                                                    */
68853   TIMER_OUTCFG3_OUTCFG14_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68854   TIMER_OUTCFG3_OUTCFG14_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68855   TIMER_OUTCFG3_OUTCFG14_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68856   TIMER_OUTCFG3_OUTCFG14_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68857   TIMER_OUTCFG3_OUTCFG14_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68858   TIMER_OUTCFG3_OUTCFG14_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68859   TIMER_OUTCFG3_OUTCFG14_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68860   TIMER_OUTCFG3_OUTCFG14_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68861   TIMER_OUTCFG3_OUTCFG14_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68862   TIMER_OUTCFG3_OUTCFG14_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68863   TIMER_OUTCFG3_OUTCFG14_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68864   TIMER_OUTCFG3_OUTCFG14_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68865   TIMER_OUTCFG3_OUTCFG14_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68866   TIMER_OUTCFG3_OUTCFG14_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68867   TIMER_OUTCFG3_OUTCFG14_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68868   TIMER_OUTCFG3_OUTCFG14_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68869   TIMER_OUTCFG3_OUTCFG14_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68870   TIMER_OUTCFG3_OUTCFG14_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68871   TIMER_OUTCFG3_OUTCFG14_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68872   TIMER_OUTCFG3_OUTCFG14_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68873   TIMER_OUTCFG3_OUTCFG14_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68874   TIMER_OUTCFG3_OUTCFG14_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68875   TIMER_OUTCFG3_OUTCFG14_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68876   TIMER_OUTCFG3_OUTCFG14_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68877   TIMER_OUTCFG3_OUTCFG14_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68878   TIMER_OUTCFG3_OUTCFG14_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68879   TIMER_OUTCFG3_OUTCFG14_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68880   TIMER_OUTCFG3_OUTCFG14_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68881   TIMER_OUTCFG3_OUTCFG14_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68882   TIMER_OUTCFG3_OUTCFG14_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68883   TIMER_OUTCFG3_OUTCFG14_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68884   TIMER_OUTCFG3_OUTCFG14_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68885   TIMER_OUTCFG3_OUTCFG14_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68886   TIMER_OUTCFG3_OUTCFG14_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68887   TIMER_OUTCFG3_OUTCFG14_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68888   TIMER_OUTCFG3_OUTCFG14_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68889   TIMER_OUTCFG3_OUTCFG14_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68890   TIMER_OUTCFG3_OUTCFG14_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68891   TIMER_OUTCFG3_OUTCFG14_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68892   TIMER_OUTCFG3_OUTCFG14_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68893   TIMER_OUTCFG3_OUTCFG14_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
68894 } TIMER_OUTCFG3_OUTCFG14_Enum;
68895 
68896 /* ============================================  TIMER OUTCFG3 OUTCFG13 [8..13]  ============================================= */
68897 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG13                                                    */
68898   TIMER_OUTCFG3_OUTCFG13_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68899   TIMER_OUTCFG3_OUTCFG13_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68900   TIMER_OUTCFG3_OUTCFG13_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68901   TIMER_OUTCFG3_OUTCFG13_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68902   TIMER_OUTCFG3_OUTCFG13_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68903   TIMER_OUTCFG3_OUTCFG13_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68904   TIMER_OUTCFG3_OUTCFG13_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68905   TIMER_OUTCFG3_OUTCFG13_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68906   TIMER_OUTCFG3_OUTCFG13_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68907   TIMER_OUTCFG3_OUTCFG13_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68908   TIMER_OUTCFG3_OUTCFG13_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68909   TIMER_OUTCFG3_OUTCFG13_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68910   TIMER_OUTCFG3_OUTCFG13_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68911   TIMER_OUTCFG3_OUTCFG13_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68912   TIMER_OUTCFG3_OUTCFG13_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68913   TIMER_OUTCFG3_OUTCFG13_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68914   TIMER_OUTCFG3_OUTCFG13_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68915   TIMER_OUTCFG3_OUTCFG13_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68916   TIMER_OUTCFG3_OUTCFG13_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68917   TIMER_OUTCFG3_OUTCFG13_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68918   TIMER_OUTCFG3_OUTCFG13_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68919   TIMER_OUTCFG3_OUTCFG13_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68920   TIMER_OUTCFG3_OUTCFG13_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68921   TIMER_OUTCFG3_OUTCFG13_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68922   TIMER_OUTCFG3_OUTCFG13_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68923   TIMER_OUTCFG3_OUTCFG13_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68924   TIMER_OUTCFG3_OUTCFG13_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68925   TIMER_OUTCFG3_OUTCFG13_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68926   TIMER_OUTCFG3_OUTCFG13_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68927   TIMER_OUTCFG3_OUTCFG13_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68928   TIMER_OUTCFG3_OUTCFG13_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68929   TIMER_OUTCFG3_OUTCFG13_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68930   TIMER_OUTCFG3_OUTCFG13_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68931   TIMER_OUTCFG3_OUTCFG13_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68932   TIMER_OUTCFG3_OUTCFG13_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68933   TIMER_OUTCFG3_OUTCFG13_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68934   TIMER_OUTCFG3_OUTCFG13_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68935   TIMER_OUTCFG3_OUTCFG13_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68936   TIMER_OUTCFG3_OUTCFG13_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68937   TIMER_OUTCFG3_OUTCFG13_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68938   TIMER_OUTCFG3_OUTCFG13_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
68939 } TIMER_OUTCFG3_OUTCFG13_Enum;
68940 
68941 /* =============================================  TIMER OUTCFG3 OUTCFG12 [0..5]  ============================================= */
68942 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG12                                                    */
68943   TIMER_OUTCFG3_OUTCFG12_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68944   TIMER_OUTCFG3_OUTCFG12_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68945   TIMER_OUTCFG3_OUTCFG12_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68946   TIMER_OUTCFG3_OUTCFG12_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68947   TIMER_OUTCFG3_OUTCFG12_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68948   TIMER_OUTCFG3_OUTCFG12_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68949   TIMER_OUTCFG3_OUTCFG12_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68950   TIMER_OUTCFG3_OUTCFG12_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68951   TIMER_OUTCFG3_OUTCFG12_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68952   TIMER_OUTCFG3_OUTCFG12_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68953   TIMER_OUTCFG3_OUTCFG12_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
68954   TIMER_OUTCFG3_OUTCFG12_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
68955   TIMER_OUTCFG3_OUTCFG12_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
68956   TIMER_OUTCFG3_OUTCFG12_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
68957   TIMER_OUTCFG3_OUTCFG12_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
68958   TIMER_OUTCFG3_OUTCFG12_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
68959   TIMER_OUTCFG3_OUTCFG12_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
68960   TIMER_OUTCFG3_OUTCFG12_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
68961   TIMER_OUTCFG3_OUTCFG12_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
68962   TIMER_OUTCFG3_OUTCFG12_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
68963   TIMER_OUTCFG3_OUTCFG12_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
68964   TIMER_OUTCFG3_OUTCFG12_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
68965   TIMER_OUTCFG3_OUTCFG12_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
68966   TIMER_OUTCFG3_OUTCFG12_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
68967   TIMER_OUTCFG3_OUTCFG12_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
68968   TIMER_OUTCFG3_OUTCFG12_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
68969   TIMER_OUTCFG3_OUTCFG12_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
68970   TIMER_OUTCFG3_OUTCFG12_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
68971   TIMER_OUTCFG3_OUTCFG12_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
68972   TIMER_OUTCFG3_OUTCFG12_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
68973   TIMER_OUTCFG3_OUTCFG12_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
68974   TIMER_OUTCFG3_OUTCFG12_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
68975   TIMER_OUTCFG3_OUTCFG12_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
68976   TIMER_OUTCFG3_OUTCFG12_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
68977   TIMER_OUTCFG3_OUTCFG12_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
68978   TIMER_OUTCFG3_OUTCFG12_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
68979   TIMER_OUTCFG3_OUTCFG12_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
68980   TIMER_OUTCFG3_OUTCFG12_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
68981   TIMER_OUTCFG3_OUTCFG12_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
68982   TIMER_OUTCFG3_OUTCFG12_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
68983   TIMER_OUTCFG3_OUTCFG12_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
68984 } TIMER_OUTCFG3_OUTCFG12_Enum;
68985 
68986 /* ========================================================  OUTCFG4  ======================================================== */
68987 /* ============================================  TIMER OUTCFG4 OUTCFG19 [24..29]  ============================================ */
68988 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG19                                                    */
68989   TIMER_OUTCFG4_OUTCFG19_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
68990   TIMER_OUTCFG4_OUTCFG19_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
68991   TIMER_OUTCFG4_OUTCFG19_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
68992   TIMER_OUTCFG4_OUTCFG19_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
68993   TIMER_OUTCFG4_OUTCFG19_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
68994   TIMER_OUTCFG4_OUTCFG19_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
68995   TIMER_OUTCFG4_OUTCFG19_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
68996   TIMER_OUTCFG4_OUTCFG19_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
68997   TIMER_OUTCFG4_OUTCFG19_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
68998   TIMER_OUTCFG4_OUTCFG19_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
68999   TIMER_OUTCFG4_OUTCFG19_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69000   TIMER_OUTCFG4_OUTCFG19_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69001   TIMER_OUTCFG4_OUTCFG19_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69002   TIMER_OUTCFG4_OUTCFG19_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69003   TIMER_OUTCFG4_OUTCFG19_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69004   TIMER_OUTCFG4_OUTCFG19_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69005   TIMER_OUTCFG4_OUTCFG19_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69006   TIMER_OUTCFG4_OUTCFG19_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69007   TIMER_OUTCFG4_OUTCFG19_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69008   TIMER_OUTCFG4_OUTCFG19_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69009   TIMER_OUTCFG4_OUTCFG19_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69010   TIMER_OUTCFG4_OUTCFG19_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69011   TIMER_OUTCFG4_OUTCFG19_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69012   TIMER_OUTCFG4_OUTCFG19_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69013   TIMER_OUTCFG4_OUTCFG19_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69014   TIMER_OUTCFG4_OUTCFG19_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69015   TIMER_OUTCFG4_OUTCFG19_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69016   TIMER_OUTCFG4_OUTCFG19_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69017   TIMER_OUTCFG4_OUTCFG19_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69018   TIMER_OUTCFG4_OUTCFG19_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69019   TIMER_OUTCFG4_OUTCFG19_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69020   TIMER_OUTCFG4_OUTCFG19_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69021   TIMER_OUTCFG4_OUTCFG19_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69022   TIMER_OUTCFG4_OUTCFG19_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69023   TIMER_OUTCFG4_OUTCFG19_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69024   TIMER_OUTCFG4_OUTCFG19_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69025   TIMER_OUTCFG4_OUTCFG19_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69026   TIMER_OUTCFG4_OUTCFG19_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69027   TIMER_OUTCFG4_OUTCFG19_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69028   TIMER_OUTCFG4_OUTCFG19_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69029   TIMER_OUTCFG4_OUTCFG19_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69030 } TIMER_OUTCFG4_OUTCFG19_Enum;
69031 
69032 /* ============================================  TIMER OUTCFG4 OUTCFG18 [16..21]  ============================================ */
69033 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG18                                                    */
69034   TIMER_OUTCFG4_OUTCFG18_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69035   TIMER_OUTCFG4_OUTCFG18_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69036   TIMER_OUTCFG4_OUTCFG18_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69037   TIMER_OUTCFG4_OUTCFG18_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69038   TIMER_OUTCFG4_OUTCFG18_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69039   TIMER_OUTCFG4_OUTCFG18_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69040   TIMER_OUTCFG4_OUTCFG18_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69041   TIMER_OUTCFG4_OUTCFG18_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69042   TIMER_OUTCFG4_OUTCFG18_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69043   TIMER_OUTCFG4_OUTCFG18_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69044   TIMER_OUTCFG4_OUTCFG18_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69045   TIMER_OUTCFG4_OUTCFG18_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69046   TIMER_OUTCFG4_OUTCFG18_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69047   TIMER_OUTCFG4_OUTCFG18_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69048   TIMER_OUTCFG4_OUTCFG18_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69049   TIMER_OUTCFG4_OUTCFG18_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69050   TIMER_OUTCFG4_OUTCFG18_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69051   TIMER_OUTCFG4_OUTCFG18_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69052   TIMER_OUTCFG4_OUTCFG18_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69053   TIMER_OUTCFG4_OUTCFG18_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69054   TIMER_OUTCFG4_OUTCFG18_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69055   TIMER_OUTCFG4_OUTCFG18_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69056   TIMER_OUTCFG4_OUTCFG18_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69057   TIMER_OUTCFG4_OUTCFG18_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69058   TIMER_OUTCFG4_OUTCFG18_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69059   TIMER_OUTCFG4_OUTCFG18_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69060   TIMER_OUTCFG4_OUTCFG18_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69061   TIMER_OUTCFG4_OUTCFG18_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69062   TIMER_OUTCFG4_OUTCFG18_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69063   TIMER_OUTCFG4_OUTCFG18_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69064   TIMER_OUTCFG4_OUTCFG18_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69065   TIMER_OUTCFG4_OUTCFG18_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69066   TIMER_OUTCFG4_OUTCFG18_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69067   TIMER_OUTCFG4_OUTCFG18_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69068   TIMER_OUTCFG4_OUTCFG18_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69069   TIMER_OUTCFG4_OUTCFG18_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69070   TIMER_OUTCFG4_OUTCFG18_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69071   TIMER_OUTCFG4_OUTCFG18_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69072   TIMER_OUTCFG4_OUTCFG18_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69073   TIMER_OUTCFG4_OUTCFG18_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69074   TIMER_OUTCFG4_OUTCFG18_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69075 } TIMER_OUTCFG4_OUTCFG18_Enum;
69076 
69077 /* ============================================  TIMER OUTCFG4 OUTCFG17 [8..13]  ============================================= */
69078 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG17                                                    */
69079   TIMER_OUTCFG4_OUTCFG17_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69080   TIMER_OUTCFG4_OUTCFG17_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69081   TIMER_OUTCFG4_OUTCFG17_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69082   TIMER_OUTCFG4_OUTCFG17_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69083   TIMER_OUTCFG4_OUTCFG17_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69084   TIMER_OUTCFG4_OUTCFG17_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69085   TIMER_OUTCFG4_OUTCFG17_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69086   TIMER_OUTCFG4_OUTCFG17_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69087   TIMER_OUTCFG4_OUTCFG17_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69088   TIMER_OUTCFG4_OUTCFG17_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69089   TIMER_OUTCFG4_OUTCFG17_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69090   TIMER_OUTCFG4_OUTCFG17_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69091   TIMER_OUTCFG4_OUTCFG17_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69092   TIMER_OUTCFG4_OUTCFG17_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69093   TIMER_OUTCFG4_OUTCFG17_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69094   TIMER_OUTCFG4_OUTCFG17_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69095   TIMER_OUTCFG4_OUTCFG17_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69096   TIMER_OUTCFG4_OUTCFG17_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69097   TIMER_OUTCFG4_OUTCFG17_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69098   TIMER_OUTCFG4_OUTCFG17_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69099   TIMER_OUTCFG4_OUTCFG17_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69100   TIMER_OUTCFG4_OUTCFG17_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69101   TIMER_OUTCFG4_OUTCFG17_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69102   TIMER_OUTCFG4_OUTCFG17_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69103   TIMER_OUTCFG4_OUTCFG17_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69104   TIMER_OUTCFG4_OUTCFG17_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69105   TIMER_OUTCFG4_OUTCFG17_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69106   TIMER_OUTCFG4_OUTCFG17_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69107   TIMER_OUTCFG4_OUTCFG17_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69108   TIMER_OUTCFG4_OUTCFG17_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69109   TIMER_OUTCFG4_OUTCFG17_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69110   TIMER_OUTCFG4_OUTCFG17_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69111   TIMER_OUTCFG4_OUTCFG17_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69112   TIMER_OUTCFG4_OUTCFG17_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69113   TIMER_OUTCFG4_OUTCFG17_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69114   TIMER_OUTCFG4_OUTCFG17_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69115   TIMER_OUTCFG4_OUTCFG17_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69116   TIMER_OUTCFG4_OUTCFG17_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69117   TIMER_OUTCFG4_OUTCFG17_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69118   TIMER_OUTCFG4_OUTCFG17_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69119   TIMER_OUTCFG4_OUTCFG17_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69120 } TIMER_OUTCFG4_OUTCFG17_Enum;
69121 
69122 /* =============================================  TIMER OUTCFG4 OUTCFG16 [0..5]  ============================================= */
69123 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG16                                                    */
69124   TIMER_OUTCFG4_OUTCFG16_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69125   TIMER_OUTCFG4_OUTCFG16_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69126   TIMER_OUTCFG4_OUTCFG16_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69127   TIMER_OUTCFG4_OUTCFG16_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69128   TIMER_OUTCFG4_OUTCFG16_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69129   TIMER_OUTCFG4_OUTCFG16_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69130   TIMER_OUTCFG4_OUTCFG16_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69131   TIMER_OUTCFG4_OUTCFG16_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69132   TIMER_OUTCFG4_OUTCFG16_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69133   TIMER_OUTCFG4_OUTCFG16_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69134   TIMER_OUTCFG4_OUTCFG16_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69135   TIMER_OUTCFG4_OUTCFG16_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69136   TIMER_OUTCFG4_OUTCFG16_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69137   TIMER_OUTCFG4_OUTCFG16_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69138   TIMER_OUTCFG4_OUTCFG16_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69139   TIMER_OUTCFG4_OUTCFG16_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69140   TIMER_OUTCFG4_OUTCFG16_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69141   TIMER_OUTCFG4_OUTCFG16_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69142   TIMER_OUTCFG4_OUTCFG16_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69143   TIMER_OUTCFG4_OUTCFG16_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69144   TIMER_OUTCFG4_OUTCFG16_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69145   TIMER_OUTCFG4_OUTCFG16_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69146   TIMER_OUTCFG4_OUTCFG16_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69147   TIMER_OUTCFG4_OUTCFG16_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69148   TIMER_OUTCFG4_OUTCFG16_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69149   TIMER_OUTCFG4_OUTCFG16_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69150   TIMER_OUTCFG4_OUTCFG16_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69151   TIMER_OUTCFG4_OUTCFG16_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69152   TIMER_OUTCFG4_OUTCFG16_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69153   TIMER_OUTCFG4_OUTCFG16_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69154   TIMER_OUTCFG4_OUTCFG16_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69155   TIMER_OUTCFG4_OUTCFG16_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69156   TIMER_OUTCFG4_OUTCFG16_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69157   TIMER_OUTCFG4_OUTCFG16_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69158   TIMER_OUTCFG4_OUTCFG16_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69159   TIMER_OUTCFG4_OUTCFG16_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69160   TIMER_OUTCFG4_OUTCFG16_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69161   TIMER_OUTCFG4_OUTCFG16_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69162   TIMER_OUTCFG4_OUTCFG16_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69163   TIMER_OUTCFG4_OUTCFG16_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69164   TIMER_OUTCFG4_OUTCFG16_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69165 } TIMER_OUTCFG4_OUTCFG16_Enum;
69166 
69167 /* ========================================================  OUTCFG5  ======================================================== */
69168 /* ============================================  TIMER OUTCFG5 OUTCFG23 [24..29]  ============================================ */
69169 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG23                                                    */
69170   TIMER_OUTCFG5_OUTCFG23_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69171   TIMER_OUTCFG5_OUTCFG23_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69172   TIMER_OUTCFG5_OUTCFG23_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69173   TIMER_OUTCFG5_OUTCFG23_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69174   TIMER_OUTCFG5_OUTCFG23_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69175   TIMER_OUTCFG5_OUTCFG23_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69176   TIMER_OUTCFG5_OUTCFG23_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69177   TIMER_OUTCFG5_OUTCFG23_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69178   TIMER_OUTCFG5_OUTCFG23_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69179   TIMER_OUTCFG5_OUTCFG23_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69180   TIMER_OUTCFG5_OUTCFG23_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69181   TIMER_OUTCFG5_OUTCFG23_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69182   TIMER_OUTCFG5_OUTCFG23_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69183   TIMER_OUTCFG5_OUTCFG23_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69184   TIMER_OUTCFG5_OUTCFG23_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69185   TIMER_OUTCFG5_OUTCFG23_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69186   TIMER_OUTCFG5_OUTCFG23_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69187   TIMER_OUTCFG5_OUTCFG23_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69188   TIMER_OUTCFG5_OUTCFG23_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69189   TIMER_OUTCFG5_OUTCFG23_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69190   TIMER_OUTCFG5_OUTCFG23_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69191   TIMER_OUTCFG5_OUTCFG23_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69192   TIMER_OUTCFG5_OUTCFG23_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69193   TIMER_OUTCFG5_OUTCFG23_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69194   TIMER_OUTCFG5_OUTCFG23_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69195   TIMER_OUTCFG5_OUTCFG23_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69196   TIMER_OUTCFG5_OUTCFG23_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69197   TIMER_OUTCFG5_OUTCFG23_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69198   TIMER_OUTCFG5_OUTCFG23_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69199   TIMER_OUTCFG5_OUTCFG23_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69200   TIMER_OUTCFG5_OUTCFG23_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69201   TIMER_OUTCFG5_OUTCFG23_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69202   TIMER_OUTCFG5_OUTCFG23_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69203   TIMER_OUTCFG5_OUTCFG23_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69204   TIMER_OUTCFG5_OUTCFG23_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69205   TIMER_OUTCFG5_OUTCFG23_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69206   TIMER_OUTCFG5_OUTCFG23_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69207   TIMER_OUTCFG5_OUTCFG23_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69208   TIMER_OUTCFG5_OUTCFG23_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69209   TIMER_OUTCFG5_OUTCFG23_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69210   TIMER_OUTCFG5_OUTCFG23_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69211 } TIMER_OUTCFG5_OUTCFG23_Enum;
69212 
69213 /* ============================================  TIMER OUTCFG5 OUTCFG22 [16..21]  ============================================ */
69214 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG22                                                    */
69215   TIMER_OUTCFG5_OUTCFG22_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69216   TIMER_OUTCFG5_OUTCFG22_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69217   TIMER_OUTCFG5_OUTCFG22_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69218   TIMER_OUTCFG5_OUTCFG22_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69219   TIMER_OUTCFG5_OUTCFG22_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69220   TIMER_OUTCFG5_OUTCFG22_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69221   TIMER_OUTCFG5_OUTCFG22_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69222   TIMER_OUTCFG5_OUTCFG22_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69223   TIMER_OUTCFG5_OUTCFG22_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69224   TIMER_OUTCFG5_OUTCFG22_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69225   TIMER_OUTCFG5_OUTCFG22_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69226   TIMER_OUTCFG5_OUTCFG22_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69227   TIMER_OUTCFG5_OUTCFG22_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69228   TIMER_OUTCFG5_OUTCFG22_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69229   TIMER_OUTCFG5_OUTCFG22_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69230   TIMER_OUTCFG5_OUTCFG22_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69231   TIMER_OUTCFG5_OUTCFG22_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69232   TIMER_OUTCFG5_OUTCFG22_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69233   TIMER_OUTCFG5_OUTCFG22_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69234   TIMER_OUTCFG5_OUTCFG22_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69235   TIMER_OUTCFG5_OUTCFG22_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69236   TIMER_OUTCFG5_OUTCFG22_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69237   TIMER_OUTCFG5_OUTCFG22_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69238   TIMER_OUTCFG5_OUTCFG22_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69239   TIMER_OUTCFG5_OUTCFG22_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69240   TIMER_OUTCFG5_OUTCFG22_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69241   TIMER_OUTCFG5_OUTCFG22_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69242   TIMER_OUTCFG5_OUTCFG22_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69243   TIMER_OUTCFG5_OUTCFG22_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69244   TIMER_OUTCFG5_OUTCFG22_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69245   TIMER_OUTCFG5_OUTCFG22_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69246   TIMER_OUTCFG5_OUTCFG22_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69247   TIMER_OUTCFG5_OUTCFG22_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69248   TIMER_OUTCFG5_OUTCFG22_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69249   TIMER_OUTCFG5_OUTCFG22_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69250   TIMER_OUTCFG5_OUTCFG22_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69251   TIMER_OUTCFG5_OUTCFG22_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69252   TIMER_OUTCFG5_OUTCFG22_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69253   TIMER_OUTCFG5_OUTCFG22_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69254   TIMER_OUTCFG5_OUTCFG22_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69255   TIMER_OUTCFG5_OUTCFG22_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69256 } TIMER_OUTCFG5_OUTCFG22_Enum;
69257 
69258 /* ============================================  TIMER OUTCFG5 OUTCFG21 [8..13]  ============================================= */
69259 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG21                                                    */
69260   TIMER_OUTCFG5_OUTCFG21_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69261   TIMER_OUTCFG5_OUTCFG21_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69262   TIMER_OUTCFG5_OUTCFG21_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69263   TIMER_OUTCFG5_OUTCFG21_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69264   TIMER_OUTCFG5_OUTCFG21_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69265   TIMER_OUTCFG5_OUTCFG21_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69266   TIMER_OUTCFG5_OUTCFG21_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69267   TIMER_OUTCFG5_OUTCFG21_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69268   TIMER_OUTCFG5_OUTCFG21_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69269   TIMER_OUTCFG5_OUTCFG21_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69270   TIMER_OUTCFG5_OUTCFG21_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69271   TIMER_OUTCFG5_OUTCFG21_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69272   TIMER_OUTCFG5_OUTCFG21_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69273   TIMER_OUTCFG5_OUTCFG21_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69274   TIMER_OUTCFG5_OUTCFG21_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69275   TIMER_OUTCFG5_OUTCFG21_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69276   TIMER_OUTCFG5_OUTCFG21_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69277   TIMER_OUTCFG5_OUTCFG21_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69278   TIMER_OUTCFG5_OUTCFG21_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69279   TIMER_OUTCFG5_OUTCFG21_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69280   TIMER_OUTCFG5_OUTCFG21_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69281   TIMER_OUTCFG5_OUTCFG21_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69282   TIMER_OUTCFG5_OUTCFG21_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69283   TIMER_OUTCFG5_OUTCFG21_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69284   TIMER_OUTCFG5_OUTCFG21_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69285   TIMER_OUTCFG5_OUTCFG21_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69286   TIMER_OUTCFG5_OUTCFG21_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69287   TIMER_OUTCFG5_OUTCFG21_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69288   TIMER_OUTCFG5_OUTCFG21_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69289   TIMER_OUTCFG5_OUTCFG21_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69290   TIMER_OUTCFG5_OUTCFG21_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69291   TIMER_OUTCFG5_OUTCFG21_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69292   TIMER_OUTCFG5_OUTCFG21_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69293   TIMER_OUTCFG5_OUTCFG21_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69294   TIMER_OUTCFG5_OUTCFG21_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69295   TIMER_OUTCFG5_OUTCFG21_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69296   TIMER_OUTCFG5_OUTCFG21_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69297   TIMER_OUTCFG5_OUTCFG21_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69298   TIMER_OUTCFG5_OUTCFG21_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69299   TIMER_OUTCFG5_OUTCFG21_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69300   TIMER_OUTCFG5_OUTCFG21_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69301 } TIMER_OUTCFG5_OUTCFG21_Enum;
69302 
69303 /* =============================================  TIMER OUTCFG5 OUTCFG20 [0..5]  ============================================= */
69304 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG20                                                    */
69305   TIMER_OUTCFG5_OUTCFG20_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69306   TIMER_OUTCFG5_OUTCFG20_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69307   TIMER_OUTCFG5_OUTCFG20_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69308   TIMER_OUTCFG5_OUTCFG20_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69309   TIMER_OUTCFG5_OUTCFG20_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69310   TIMER_OUTCFG5_OUTCFG20_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69311   TIMER_OUTCFG5_OUTCFG20_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69312   TIMER_OUTCFG5_OUTCFG20_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69313   TIMER_OUTCFG5_OUTCFG20_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69314   TIMER_OUTCFG5_OUTCFG20_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69315   TIMER_OUTCFG5_OUTCFG20_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69316   TIMER_OUTCFG5_OUTCFG20_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69317   TIMER_OUTCFG5_OUTCFG20_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69318   TIMER_OUTCFG5_OUTCFG20_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69319   TIMER_OUTCFG5_OUTCFG20_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69320   TIMER_OUTCFG5_OUTCFG20_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69321   TIMER_OUTCFG5_OUTCFG20_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69322   TIMER_OUTCFG5_OUTCFG20_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69323   TIMER_OUTCFG5_OUTCFG20_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69324   TIMER_OUTCFG5_OUTCFG20_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69325   TIMER_OUTCFG5_OUTCFG20_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69326   TIMER_OUTCFG5_OUTCFG20_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69327   TIMER_OUTCFG5_OUTCFG20_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69328   TIMER_OUTCFG5_OUTCFG20_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69329   TIMER_OUTCFG5_OUTCFG20_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69330   TIMER_OUTCFG5_OUTCFG20_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69331   TIMER_OUTCFG5_OUTCFG20_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69332   TIMER_OUTCFG5_OUTCFG20_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69333   TIMER_OUTCFG5_OUTCFG20_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69334   TIMER_OUTCFG5_OUTCFG20_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69335   TIMER_OUTCFG5_OUTCFG20_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69336   TIMER_OUTCFG5_OUTCFG20_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69337   TIMER_OUTCFG5_OUTCFG20_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69338   TIMER_OUTCFG5_OUTCFG20_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69339   TIMER_OUTCFG5_OUTCFG20_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69340   TIMER_OUTCFG5_OUTCFG20_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69341   TIMER_OUTCFG5_OUTCFG20_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69342   TIMER_OUTCFG5_OUTCFG20_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69343   TIMER_OUTCFG5_OUTCFG20_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69344   TIMER_OUTCFG5_OUTCFG20_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69345   TIMER_OUTCFG5_OUTCFG20_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69346 } TIMER_OUTCFG5_OUTCFG20_Enum;
69347 
69348 /* ========================================================  OUTCFG6  ======================================================== */
69349 /* ============================================  TIMER OUTCFG6 OUTCFG27 [24..29]  ============================================ */
69350 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG27                                                    */
69351   TIMER_OUTCFG6_OUTCFG27_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69352   TIMER_OUTCFG6_OUTCFG27_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69353   TIMER_OUTCFG6_OUTCFG27_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69354   TIMER_OUTCFG6_OUTCFG27_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69355   TIMER_OUTCFG6_OUTCFG27_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69356   TIMER_OUTCFG6_OUTCFG27_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69357   TIMER_OUTCFG6_OUTCFG27_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69358   TIMER_OUTCFG6_OUTCFG27_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69359   TIMER_OUTCFG6_OUTCFG27_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69360   TIMER_OUTCFG6_OUTCFG27_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69361   TIMER_OUTCFG6_OUTCFG27_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69362   TIMER_OUTCFG6_OUTCFG27_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69363   TIMER_OUTCFG6_OUTCFG27_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69364   TIMER_OUTCFG6_OUTCFG27_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69365   TIMER_OUTCFG6_OUTCFG27_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69366   TIMER_OUTCFG6_OUTCFG27_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69367   TIMER_OUTCFG6_OUTCFG27_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69368   TIMER_OUTCFG6_OUTCFG27_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69369   TIMER_OUTCFG6_OUTCFG27_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69370   TIMER_OUTCFG6_OUTCFG27_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69371   TIMER_OUTCFG6_OUTCFG27_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69372   TIMER_OUTCFG6_OUTCFG27_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69373   TIMER_OUTCFG6_OUTCFG27_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69374   TIMER_OUTCFG6_OUTCFG27_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69375   TIMER_OUTCFG6_OUTCFG27_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69376   TIMER_OUTCFG6_OUTCFG27_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69377   TIMER_OUTCFG6_OUTCFG27_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69378   TIMER_OUTCFG6_OUTCFG27_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69379   TIMER_OUTCFG6_OUTCFG27_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69380   TIMER_OUTCFG6_OUTCFG27_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69381   TIMER_OUTCFG6_OUTCFG27_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69382   TIMER_OUTCFG6_OUTCFG27_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69383   TIMER_OUTCFG6_OUTCFG27_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69384   TIMER_OUTCFG6_OUTCFG27_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69385   TIMER_OUTCFG6_OUTCFG27_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69386   TIMER_OUTCFG6_OUTCFG27_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69387   TIMER_OUTCFG6_OUTCFG27_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69388   TIMER_OUTCFG6_OUTCFG27_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69389   TIMER_OUTCFG6_OUTCFG27_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69390   TIMER_OUTCFG6_OUTCFG27_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69391   TIMER_OUTCFG6_OUTCFG27_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69392 } TIMER_OUTCFG6_OUTCFG27_Enum;
69393 
69394 /* ============================================  TIMER OUTCFG6 OUTCFG26 [16..21]  ============================================ */
69395 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG26                                                    */
69396   TIMER_OUTCFG6_OUTCFG26_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69397   TIMER_OUTCFG6_OUTCFG26_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69398   TIMER_OUTCFG6_OUTCFG26_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69399   TIMER_OUTCFG6_OUTCFG26_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69400   TIMER_OUTCFG6_OUTCFG26_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69401   TIMER_OUTCFG6_OUTCFG26_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69402   TIMER_OUTCFG6_OUTCFG26_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69403   TIMER_OUTCFG6_OUTCFG26_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69404   TIMER_OUTCFG6_OUTCFG26_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69405   TIMER_OUTCFG6_OUTCFG26_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69406   TIMER_OUTCFG6_OUTCFG26_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69407   TIMER_OUTCFG6_OUTCFG26_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69408   TIMER_OUTCFG6_OUTCFG26_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69409   TIMER_OUTCFG6_OUTCFG26_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69410   TIMER_OUTCFG6_OUTCFG26_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69411   TIMER_OUTCFG6_OUTCFG26_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69412   TIMER_OUTCFG6_OUTCFG26_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69413   TIMER_OUTCFG6_OUTCFG26_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69414   TIMER_OUTCFG6_OUTCFG26_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69415   TIMER_OUTCFG6_OUTCFG26_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69416   TIMER_OUTCFG6_OUTCFG26_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69417   TIMER_OUTCFG6_OUTCFG26_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69418   TIMER_OUTCFG6_OUTCFG26_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69419   TIMER_OUTCFG6_OUTCFG26_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69420   TIMER_OUTCFG6_OUTCFG26_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69421   TIMER_OUTCFG6_OUTCFG26_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69422   TIMER_OUTCFG6_OUTCFG26_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69423   TIMER_OUTCFG6_OUTCFG26_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69424   TIMER_OUTCFG6_OUTCFG26_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69425   TIMER_OUTCFG6_OUTCFG26_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69426   TIMER_OUTCFG6_OUTCFG26_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69427   TIMER_OUTCFG6_OUTCFG26_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69428   TIMER_OUTCFG6_OUTCFG26_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69429   TIMER_OUTCFG6_OUTCFG26_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69430   TIMER_OUTCFG6_OUTCFG26_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69431   TIMER_OUTCFG6_OUTCFG26_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69432   TIMER_OUTCFG6_OUTCFG26_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69433   TIMER_OUTCFG6_OUTCFG26_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69434   TIMER_OUTCFG6_OUTCFG26_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69435   TIMER_OUTCFG6_OUTCFG26_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69436   TIMER_OUTCFG6_OUTCFG26_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69437 } TIMER_OUTCFG6_OUTCFG26_Enum;
69438 
69439 /* ============================================  TIMER OUTCFG6 OUTCFG25 [8..13]  ============================================= */
69440 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG25                                                    */
69441   TIMER_OUTCFG6_OUTCFG25_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69442   TIMER_OUTCFG6_OUTCFG25_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69443   TIMER_OUTCFG6_OUTCFG25_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69444   TIMER_OUTCFG6_OUTCFG25_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69445   TIMER_OUTCFG6_OUTCFG25_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69446   TIMER_OUTCFG6_OUTCFG25_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69447   TIMER_OUTCFG6_OUTCFG25_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69448   TIMER_OUTCFG6_OUTCFG25_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69449   TIMER_OUTCFG6_OUTCFG25_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69450   TIMER_OUTCFG6_OUTCFG25_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69451   TIMER_OUTCFG6_OUTCFG25_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69452   TIMER_OUTCFG6_OUTCFG25_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69453   TIMER_OUTCFG6_OUTCFG25_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69454   TIMER_OUTCFG6_OUTCFG25_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69455   TIMER_OUTCFG6_OUTCFG25_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69456   TIMER_OUTCFG6_OUTCFG25_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69457   TIMER_OUTCFG6_OUTCFG25_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69458   TIMER_OUTCFG6_OUTCFG25_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69459   TIMER_OUTCFG6_OUTCFG25_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69460   TIMER_OUTCFG6_OUTCFG25_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69461   TIMER_OUTCFG6_OUTCFG25_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69462   TIMER_OUTCFG6_OUTCFG25_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69463   TIMER_OUTCFG6_OUTCFG25_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69464   TIMER_OUTCFG6_OUTCFG25_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69465   TIMER_OUTCFG6_OUTCFG25_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69466   TIMER_OUTCFG6_OUTCFG25_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69467   TIMER_OUTCFG6_OUTCFG25_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69468   TIMER_OUTCFG6_OUTCFG25_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69469   TIMER_OUTCFG6_OUTCFG25_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69470   TIMER_OUTCFG6_OUTCFG25_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69471   TIMER_OUTCFG6_OUTCFG25_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69472   TIMER_OUTCFG6_OUTCFG25_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69473   TIMER_OUTCFG6_OUTCFG25_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69474   TIMER_OUTCFG6_OUTCFG25_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69475   TIMER_OUTCFG6_OUTCFG25_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69476   TIMER_OUTCFG6_OUTCFG25_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69477   TIMER_OUTCFG6_OUTCFG25_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69478   TIMER_OUTCFG6_OUTCFG25_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69479   TIMER_OUTCFG6_OUTCFG25_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69480   TIMER_OUTCFG6_OUTCFG25_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69481   TIMER_OUTCFG6_OUTCFG25_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69482 } TIMER_OUTCFG6_OUTCFG25_Enum;
69483 
69484 /* =============================================  TIMER OUTCFG6 OUTCFG24 [0..5]  ============================================= */
69485 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG24                                                    */
69486   TIMER_OUTCFG6_OUTCFG24_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69487   TIMER_OUTCFG6_OUTCFG24_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69488   TIMER_OUTCFG6_OUTCFG24_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69489   TIMER_OUTCFG6_OUTCFG24_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69490   TIMER_OUTCFG6_OUTCFG24_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69491   TIMER_OUTCFG6_OUTCFG24_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69492   TIMER_OUTCFG6_OUTCFG24_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69493   TIMER_OUTCFG6_OUTCFG24_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69494   TIMER_OUTCFG6_OUTCFG24_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69495   TIMER_OUTCFG6_OUTCFG24_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69496   TIMER_OUTCFG6_OUTCFG24_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69497   TIMER_OUTCFG6_OUTCFG24_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69498   TIMER_OUTCFG6_OUTCFG24_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69499   TIMER_OUTCFG6_OUTCFG24_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69500   TIMER_OUTCFG6_OUTCFG24_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69501   TIMER_OUTCFG6_OUTCFG24_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69502   TIMER_OUTCFG6_OUTCFG24_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69503   TIMER_OUTCFG6_OUTCFG24_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69504   TIMER_OUTCFG6_OUTCFG24_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69505   TIMER_OUTCFG6_OUTCFG24_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69506   TIMER_OUTCFG6_OUTCFG24_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69507   TIMER_OUTCFG6_OUTCFG24_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69508   TIMER_OUTCFG6_OUTCFG24_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69509   TIMER_OUTCFG6_OUTCFG24_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69510   TIMER_OUTCFG6_OUTCFG24_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69511   TIMER_OUTCFG6_OUTCFG24_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69512   TIMER_OUTCFG6_OUTCFG24_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69513   TIMER_OUTCFG6_OUTCFG24_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69514   TIMER_OUTCFG6_OUTCFG24_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69515   TIMER_OUTCFG6_OUTCFG24_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69516   TIMER_OUTCFG6_OUTCFG24_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69517   TIMER_OUTCFG6_OUTCFG24_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69518   TIMER_OUTCFG6_OUTCFG24_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69519   TIMER_OUTCFG6_OUTCFG24_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69520   TIMER_OUTCFG6_OUTCFG24_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69521   TIMER_OUTCFG6_OUTCFG24_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69522   TIMER_OUTCFG6_OUTCFG24_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69523   TIMER_OUTCFG6_OUTCFG24_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69524   TIMER_OUTCFG6_OUTCFG24_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69525   TIMER_OUTCFG6_OUTCFG24_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69526   TIMER_OUTCFG6_OUTCFG24_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69527 } TIMER_OUTCFG6_OUTCFG24_Enum;
69528 
69529 /* ========================================================  OUTCFG7  ======================================================== */
69530 /* ============================================  TIMER OUTCFG7 OUTCFG31 [24..29]  ============================================ */
69531 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG31                                                    */
69532   TIMER_OUTCFG7_OUTCFG31_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69533   TIMER_OUTCFG7_OUTCFG31_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69534   TIMER_OUTCFG7_OUTCFG31_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69535   TIMER_OUTCFG7_OUTCFG31_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69536   TIMER_OUTCFG7_OUTCFG31_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69537   TIMER_OUTCFG7_OUTCFG31_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69538   TIMER_OUTCFG7_OUTCFG31_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69539   TIMER_OUTCFG7_OUTCFG31_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69540   TIMER_OUTCFG7_OUTCFG31_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69541   TIMER_OUTCFG7_OUTCFG31_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69542   TIMER_OUTCFG7_OUTCFG31_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69543   TIMER_OUTCFG7_OUTCFG31_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69544   TIMER_OUTCFG7_OUTCFG31_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69545   TIMER_OUTCFG7_OUTCFG31_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69546   TIMER_OUTCFG7_OUTCFG31_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69547   TIMER_OUTCFG7_OUTCFG31_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69548   TIMER_OUTCFG7_OUTCFG31_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69549   TIMER_OUTCFG7_OUTCFG31_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69550   TIMER_OUTCFG7_OUTCFG31_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69551   TIMER_OUTCFG7_OUTCFG31_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69552   TIMER_OUTCFG7_OUTCFG31_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69553   TIMER_OUTCFG7_OUTCFG31_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69554   TIMER_OUTCFG7_OUTCFG31_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69555   TIMER_OUTCFG7_OUTCFG31_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69556   TIMER_OUTCFG7_OUTCFG31_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69557   TIMER_OUTCFG7_OUTCFG31_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69558   TIMER_OUTCFG7_OUTCFG31_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69559   TIMER_OUTCFG7_OUTCFG31_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69560   TIMER_OUTCFG7_OUTCFG31_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69561   TIMER_OUTCFG7_OUTCFG31_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69562   TIMER_OUTCFG7_OUTCFG31_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69563   TIMER_OUTCFG7_OUTCFG31_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69564   TIMER_OUTCFG7_OUTCFG31_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69565   TIMER_OUTCFG7_OUTCFG31_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69566   TIMER_OUTCFG7_OUTCFG31_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69567   TIMER_OUTCFG7_OUTCFG31_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69568   TIMER_OUTCFG7_OUTCFG31_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69569   TIMER_OUTCFG7_OUTCFG31_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69570   TIMER_OUTCFG7_OUTCFG31_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69571   TIMER_OUTCFG7_OUTCFG31_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69572   TIMER_OUTCFG7_OUTCFG31_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69573 } TIMER_OUTCFG7_OUTCFG31_Enum;
69574 
69575 /* ============================================  TIMER OUTCFG7 OUTCFG30 [16..21]  ============================================ */
69576 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG30                                                    */
69577   TIMER_OUTCFG7_OUTCFG30_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69578   TIMER_OUTCFG7_OUTCFG30_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69579   TIMER_OUTCFG7_OUTCFG30_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69580   TIMER_OUTCFG7_OUTCFG30_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69581   TIMER_OUTCFG7_OUTCFG30_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69582   TIMER_OUTCFG7_OUTCFG30_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69583   TIMER_OUTCFG7_OUTCFG30_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69584   TIMER_OUTCFG7_OUTCFG30_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69585   TIMER_OUTCFG7_OUTCFG30_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69586   TIMER_OUTCFG7_OUTCFG30_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69587   TIMER_OUTCFG7_OUTCFG30_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69588   TIMER_OUTCFG7_OUTCFG30_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69589   TIMER_OUTCFG7_OUTCFG30_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69590   TIMER_OUTCFG7_OUTCFG30_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69591   TIMER_OUTCFG7_OUTCFG30_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69592   TIMER_OUTCFG7_OUTCFG30_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69593   TIMER_OUTCFG7_OUTCFG30_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69594   TIMER_OUTCFG7_OUTCFG30_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69595   TIMER_OUTCFG7_OUTCFG30_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69596   TIMER_OUTCFG7_OUTCFG30_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69597   TIMER_OUTCFG7_OUTCFG30_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69598   TIMER_OUTCFG7_OUTCFG30_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69599   TIMER_OUTCFG7_OUTCFG30_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69600   TIMER_OUTCFG7_OUTCFG30_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69601   TIMER_OUTCFG7_OUTCFG30_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69602   TIMER_OUTCFG7_OUTCFG30_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69603   TIMER_OUTCFG7_OUTCFG30_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69604   TIMER_OUTCFG7_OUTCFG30_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69605   TIMER_OUTCFG7_OUTCFG30_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69606   TIMER_OUTCFG7_OUTCFG30_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69607   TIMER_OUTCFG7_OUTCFG30_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69608   TIMER_OUTCFG7_OUTCFG30_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69609   TIMER_OUTCFG7_OUTCFG30_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69610   TIMER_OUTCFG7_OUTCFG30_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69611   TIMER_OUTCFG7_OUTCFG30_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69612   TIMER_OUTCFG7_OUTCFG30_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69613   TIMER_OUTCFG7_OUTCFG30_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69614   TIMER_OUTCFG7_OUTCFG30_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69615   TIMER_OUTCFG7_OUTCFG30_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69616   TIMER_OUTCFG7_OUTCFG30_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69617   TIMER_OUTCFG7_OUTCFG30_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69618 } TIMER_OUTCFG7_OUTCFG30_Enum;
69619 
69620 /* ============================================  TIMER OUTCFG7 OUTCFG29 [8..13]  ============================================= */
69621 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG29                                                    */
69622   TIMER_OUTCFG7_OUTCFG29_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69623   TIMER_OUTCFG7_OUTCFG29_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69624   TIMER_OUTCFG7_OUTCFG29_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69625   TIMER_OUTCFG7_OUTCFG29_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69626   TIMER_OUTCFG7_OUTCFG29_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69627   TIMER_OUTCFG7_OUTCFG29_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69628   TIMER_OUTCFG7_OUTCFG29_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69629   TIMER_OUTCFG7_OUTCFG29_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69630   TIMER_OUTCFG7_OUTCFG29_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69631   TIMER_OUTCFG7_OUTCFG29_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69632   TIMER_OUTCFG7_OUTCFG29_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69633   TIMER_OUTCFG7_OUTCFG29_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69634   TIMER_OUTCFG7_OUTCFG29_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69635   TIMER_OUTCFG7_OUTCFG29_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69636   TIMER_OUTCFG7_OUTCFG29_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69637   TIMER_OUTCFG7_OUTCFG29_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69638   TIMER_OUTCFG7_OUTCFG29_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69639   TIMER_OUTCFG7_OUTCFG29_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69640   TIMER_OUTCFG7_OUTCFG29_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69641   TIMER_OUTCFG7_OUTCFG29_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69642   TIMER_OUTCFG7_OUTCFG29_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69643   TIMER_OUTCFG7_OUTCFG29_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69644   TIMER_OUTCFG7_OUTCFG29_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69645   TIMER_OUTCFG7_OUTCFG29_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69646   TIMER_OUTCFG7_OUTCFG29_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69647   TIMER_OUTCFG7_OUTCFG29_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69648   TIMER_OUTCFG7_OUTCFG29_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69649   TIMER_OUTCFG7_OUTCFG29_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69650   TIMER_OUTCFG7_OUTCFG29_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69651   TIMER_OUTCFG7_OUTCFG29_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69652   TIMER_OUTCFG7_OUTCFG29_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69653   TIMER_OUTCFG7_OUTCFG29_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69654   TIMER_OUTCFG7_OUTCFG29_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69655   TIMER_OUTCFG7_OUTCFG29_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69656   TIMER_OUTCFG7_OUTCFG29_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69657   TIMER_OUTCFG7_OUTCFG29_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69658   TIMER_OUTCFG7_OUTCFG29_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69659   TIMER_OUTCFG7_OUTCFG29_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69660   TIMER_OUTCFG7_OUTCFG29_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69661   TIMER_OUTCFG7_OUTCFG29_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69662   TIMER_OUTCFG7_OUTCFG29_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69663 } TIMER_OUTCFG7_OUTCFG29_Enum;
69664 
69665 /* =============================================  TIMER OUTCFG7 OUTCFG28 [0..5]  ============================================= */
69666 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG28                                                    */
69667   TIMER_OUTCFG7_OUTCFG28_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69668   TIMER_OUTCFG7_OUTCFG28_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69669   TIMER_OUTCFG7_OUTCFG28_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69670   TIMER_OUTCFG7_OUTCFG28_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69671   TIMER_OUTCFG7_OUTCFG28_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69672   TIMER_OUTCFG7_OUTCFG28_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69673   TIMER_OUTCFG7_OUTCFG28_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69674   TIMER_OUTCFG7_OUTCFG28_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69675   TIMER_OUTCFG7_OUTCFG28_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69676   TIMER_OUTCFG7_OUTCFG28_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69677   TIMER_OUTCFG7_OUTCFG28_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69678   TIMER_OUTCFG7_OUTCFG28_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69679   TIMER_OUTCFG7_OUTCFG28_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69680   TIMER_OUTCFG7_OUTCFG28_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69681   TIMER_OUTCFG7_OUTCFG28_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69682   TIMER_OUTCFG7_OUTCFG28_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69683   TIMER_OUTCFG7_OUTCFG28_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69684   TIMER_OUTCFG7_OUTCFG28_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69685   TIMER_OUTCFG7_OUTCFG28_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69686   TIMER_OUTCFG7_OUTCFG28_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69687   TIMER_OUTCFG7_OUTCFG28_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69688   TIMER_OUTCFG7_OUTCFG28_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69689   TIMER_OUTCFG7_OUTCFG28_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69690   TIMER_OUTCFG7_OUTCFG28_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69691   TIMER_OUTCFG7_OUTCFG28_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69692   TIMER_OUTCFG7_OUTCFG28_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69693   TIMER_OUTCFG7_OUTCFG28_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69694   TIMER_OUTCFG7_OUTCFG28_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69695   TIMER_OUTCFG7_OUTCFG28_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69696   TIMER_OUTCFG7_OUTCFG28_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69697   TIMER_OUTCFG7_OUTCFG28_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69698   TIMER_OUTCFG7_OUTCFG28_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69699   TIMER_OUTCFG7_OUTCFG28_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69700   TIMER_OUTCFG7_OUTCFG28_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69701   TIMER_OUTCFG7_OUTCFG28_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69702   TIMER_OUTCFG7_OUTCFG28_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69703   TIMER_OUTCFG7_OUTCFG28_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69704   TIMER_OUTCFG7_OUTCFG28_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69705   TIMER_OUTCFG7_OUTCFG28_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69706   TIMER_OUTCFG7_OUTCFG28_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69707   TIMER_OUTCFG7_OUTCFG28_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69708 } TIMER_OUTCFG7_OUTCFG28_Enum;
69709 
69710 /* ========================================================  OUTCFG8  ======================================================== */
69711 /* ============================================  TIMER OUTCFG8 OUTCFG35 [24..29]  ============================================ */
69712 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG35                                                    */
69713   TIMER_OUTCFG8_OUTCFG35_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69714   TIMER_OUTCFG8_OUTCFG35_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69715   TIMER_OUTCFG8_OUTCFG35_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69716   TIMER_OUTCFG8_OUTCFG35_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69717   TIMER_OUTCFG8_OUTCFG35_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69718   TIMER_OUTCFG8_OUTCFG35_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69719   TIMER_OUTCFG8_OUTCFG35_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69720   TIMER_OUTCFG8_OUTCFG35_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69721   TIMER_OUTCFG8_OUTCFG35_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69722   TIMER_OUTCFG8_OUTCFG35_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69723   TIMER_OUTCFG8_OUTCFG35_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69724   TIMER_OUTCFG8_OUTCFG35_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69725   TIMER_OUTCFG8_OUTCFG35_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69726   TIMER_OUTCFG8_OUTCFG35_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69727   TIMER_OUTCFG8_OUTCFG35_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69728   TIMER_OUTCFG8_OUTCFG35_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69729   TIMER_OUTCFG8_OUTCFG35_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69730   TIMER_OUTCFG8_OUTCFG35_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69731   TIMER_OUTCFG8_OUTCFG35_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69732   TIMER_OUTCFG8_OUTCFG35_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69733   TIMER_OUTCFG8_OUTCFG35_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69734   TIMER_OUTCFG8_OUTCFG35_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69735   TIMER_OUTCFG8_OUTCFG35_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69736   TIMER_OUTCFG8_OUTCFG35_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69737   TIMER_OUTCFG8_OUTCFG35_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69738   TIMER_OUTCFG8_OUTCFG35_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69739   TIMER_OUTCFG8_OUTCFG35_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69740   TIMER_OUTCFG8_OUTCFG35_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69741   TIMER_OUTCFG8_OUTCFG35_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69742   TIMER_OUTCFG8_OUTCFG35_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69743   TIMER_OUTCFG8_OUTCFG35_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69744   TIMER_OUTCFG8_OUTCFG35_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69745   TIMER_OUTCFG8_OUTCFG35_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69746   TIMER_OUTCFG8_OUTCFG35_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69747   TIMER_OUTCFG8_OUTCFG35_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69748   TIMER_OUTCFG8_OUTCFG35_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69749   TIMER_OUTCFG8_OUTCFG35_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69750   TIMER_OUTCFG8_OUTCFG35_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69751   TIMER_OUTCFG8_OUTCFG35_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69752   TIMER_OUTCFG8_OUTCFG35_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69753   TIMER_OUTCFG8_OUTCFG35_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69754 } TIMER_OUTCFG8_OUTCFG35_Enum;
69755 
69756 /* ============================================  TIMER OUTCFG8 OUTCFG34 [16..21]  ============================================ */
69757 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG34                                                    */
69758   TIMER_OUTCFG8_OUTCFG34_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69759   TIMER_OUTCFG8_OUTCFG34_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69760   TIMER_OUTCFG8_OUTCFG34_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69761   TIMER_OUTCFG8_OUTCFG34_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69762   TIMER_OUTCFG8_OUTCFG34_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69763   TIMER_OUTCFG8_OUTCFG34_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69764   TIMER_OUTCFG8_OUTCFG34_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69765   TIMER_OUTCFG8_OUTCFG34_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69766   TIMER_OUTCFG8_OUTCFG34_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69767   TIMER_OUTCFG8_OUTCFG34_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69768   TIMER_OUTCFG8_OUTCFG34_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69769   TIMER_OUTCFG8_OUTCFG34_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69770   TIMER_OUTCFG8_OUTCFG34_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69771   TIMER_OUTCFG8_OUTCFG34_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69772   TIMER_OUTCFG8_OUTCFG34_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69773   TIMER_OUTCFG8_OUTCFG34_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69774   TIMER_OUTCFG8_OUTCFG34_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69775   TIMER_OUTCFG8_OUTCFG34_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69776   TIMER_OUTCFG8_OUTCFG34_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69777   TIMER_OUTCFG8_OUTCFG34_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69778   TIMER_OUTCFG8_OUTCFG34_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69779   TIMER_OUTCFG8_OUTCFG34_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69780   TIMER_OUTCFG8_OUTCFG34_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69781   TIMER_OUTCFG8_OUTCFG34_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69782   TIMER_OUTCFG8_OUTCFG34_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69783   TIMER_OUTCFG8_OUTCFG34_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69784   TIMER_OUTCFG8_OUTCFG34_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69785   TIMER_OUTCFG8_OUTCFG34_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69786   TIMER_OUTCFG8_OUTCFG34_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69787   TIMER_OUTCFG8_OUTCFG34_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69788   TIMER_OUTCFG8_OUTCFG34_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69789   TIMER_OUTCFG8_OUTCFG34_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69790   TIMER_OUTCFG8_OUTCFG34_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69791   TIMER_OUTCFG8_OUTCFG34_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69792   TIMER_OUTCFG8_OUTCFG34_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69793   TIMER_OUTCFG8_OUTCFG34_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69794   TIMER_OUTCFG8_OUTCFG34_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69795   TIMER_OUTCFG8_OUTCFG34_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69796   TIMER_OUTCFG8_OUTCFG34_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69797   TIMER_OUTCFG8_OUTCFG34_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69798   TIMER_OUTCFG8_OUTCFG34_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69799 } TIMER_OUTCFG8_OUTCFG34_Enum;
69800 
69801 /* ============================================  TIMER OUTCFG8 OUTCFG33 [8..13]  ============================================= */
69802 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG33                                                    */
69803   TIMER_OUTCFG8_OUTCFG33_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69804   TIMER_OUTCFG8_OUTCFG33_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69805   TIMER_OUTCFG8_OUTCFG33_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69806   TIMER_OUTCFG8_OUTCFG33_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69807   TIMER_OUTCFG8_OUTCFG33_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69808   TIMER_OUTCFG8_OUTCFG33_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69809   TIMER_OUTCFG8_OUTCFG33_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69810   TIMER_OUTCFG8_OUTCFG33_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69811   TIMER_OUTCFG8_OUTCFG33_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69812   TIMER_OUTCFG8_OUTCFG33_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69813   TIMER_OUTCFG8_OUTCFG33_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69814   TIMER_OUTCFG8_OUTCFG33_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69815   TIMER_OUTCFG8_OUTCFG33_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69816   TIMER_OUTCFG8_OUTCFG33_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69817   TIMER_OUTCFG8_OUTCFG33_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69818   TIMER_OUTCFG8_OUTCFG33_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69819   TIMER_OUTCFG8_OUTCFG33_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69820   TIMER_OUTCFG8_OUTCFG33_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69821   TIMER_OUTCFG8_OUTCFG33_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69822   TIMER_OUTCFG8_OUTCFG33_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69823   TIMER_OUTCFG8_OUTCFG33_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69824   TIMER_OUTCFG8_OUTCFG33_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69825   TIMER_OUTCFG8_OUTCFG33_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69826   TIMER_OUTCFG8_OUTCFG33_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69827   TIMER_OUTCFG8_OUTCFG33_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69828   TIMER_OUTCFG8_OUTCFG33_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69829   TIMER_OUTCFG8_OUTCFG33_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69830   TIMER_OUTCFG8_OUTCFG33_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69831   TIMER_OUTCFG8_OUTCFG33_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69832   TIMER_OUTCFG8_OUTCFG33_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69833   TIMER_OUTCFG8_OUTCFG33_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69834   TIMER_OUTCFG8_OUTCFG33_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69835   TIMER_OUTCFG8_OUTCFG33_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69836   TIMER_OUTCFG8_OUTCFG33_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69837   TIMER_OUTCFG8_OUTCFG33_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69838   TIMER_OUTCFG8_OUTCFG33_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69839   TIMER_OUTCFG8_OUTCFG33_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69840   TIMER_OUTCFG8_OUTCFG33_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69841   TIMER_OUTCFG8_OUTCFG33_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69842   TIMER_OUTCFG8_OUTCFG33_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69843   TIMER_OUTCFG8_OUTCFG33_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69844 } TIMER_OUTCFG8_OUTCFG33_Enum;
69845 
69846 /* =============================================  TIMER OUTCFG8 OUTCFG32 [0..5]  ============================================= */
69847 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG32                                                    */
69848   TIMER_OUTCFG8_OUTCFG32_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69849   TIMER_OUTCFG8_OUTCFG32_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69850   TIMER_OUTCFG8_OUTCFG32_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69851   TIMER_OUTCFG8_OUTCFG32_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69852   TIMER_OUTCFG8_OUTCFG32_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69853   TIMER_OUTCFG8_OUTCFG32_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69854   TIMER_OUTCFG8_OUTCFG32_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69855   TIMER_OUTCFG8_OUTCFG32_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69856   TIMER_OUTCFG8_OUTCFG32_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69857   TIMER_OUTCFG8_OUTCFG32_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69858   TIMER_OUTCFG8_OUTCFG32_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69859   TIMER_OUTCFG8_OUTCFG32_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69860   TIMER_OUTCFG8_OUTCFG32_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69861   TIMER_OUTCFG8_OUTCFG32_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69862   TIMER_OUTCFG8_OUTCFG32_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69863   TIMER_OUTCFG8_OUTCFG32_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69864   TIMER_OUTCFG8_OUTCFG32_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69865   TIMER_OUTCFG8_OUTCFG32_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69866   TIMER_OUTCFG8_OUTCFG32_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69867   TIMER_OUTCFG8_OUTCFG32_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69868   TIMER_OUTCFG8_OUTCFG32_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69869   TIMER_OUTCFG8_OUTCFG32_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69870   TIMER_OUTCFG8_OUTCFG32_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69871   TIMER_OUTCFG8_OUTCFG32_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69872   TIMER_OUTCFG8_OUTCFG32_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69873   TIMER_OUTCFG8_OUTCFG32_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69874   TIMER_OUTCFG8_OUTCFG32_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69875   TIMER_OUTCFG8_OUTCFG32_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69876   TIMER_OUTCFG8_OUTCFG32_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69877   TIMER_OUTCFG8_OUTCFG32_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69878   TIMER_OUTCFG8_OUTCFG32_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69879   TIMER_OUTCFG8_OUTCFG32_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69880   TIMER_OUTCFG8_OUTCFG32_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69881   TIMER_OUTCFG8_OUTCFG32_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69882   TIMER_OUTCFG8_OUTCFG32_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69883   TIMER_OUTCFG8_OUTCFG32_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69884   TIMER_OUTCFG8_OUTCFG32_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69885   TIMER_OUTCFG8_OUTCFG32_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69886   TIMER_OUTCFG8_OUTCFG32_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69887   TIMER_OUTCFG8_OUTCFG32_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69888   TIMER_OUTCFG8_OUTCFG32_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69889 } TIMER_OUTCFG8_OUTCFG32_Enum;
69890 
69891 /* ========================================================  OUTCFG9  ======================================================== */
69892 /* ============================================  TIMER OUTCFG9 OUTCFG39 [24..29]  ============================================ */
69893 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG39                                                    */
69894   TIMER_OUTCFG9_OUTCFG39_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69895   TIMER_OUTCFG9_OUTCFG39_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69896   TIMER_OUTCFG9_OUTCFG39_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69897   TIMER_OUTCFG9_OUTCFG39_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69898   TIMER_OUTCFG9_OUTCFG39_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69899   TIMER_OUTCFG9_OUTCFG39_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69900   TIMER_OUTCFG9_OUTCFG39_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69901   TIMER_OUTCFG9_OUTCFG39_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69902   TIMER_OUTCFG9_OUTCFG39_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69903   TIMER_OUTCFG9_OUTCFG39_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69904   TIMER_OUTCFG9_OUTCFG39_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69905   TIMER_OUTCFG9_OUTCFG39_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69906   TIMER_OUTCFG9_OUTCFG39_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69907   TIMER_OUTCFG9_OUTCFG39_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69908   TIMER_OUTCFG9_OUTCFG39_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69909   TIMER_OUTCFG9_OUTCFG39_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69910   TIMER_OUTCFG9_OUTCFG39_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69911   TIMER_OUTCFG9_OUTCFG39_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69912   TIMER_OUTCFG9_OUTCFG39_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69913   TIMER_OUTCFG9_OUTCFG39_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69914   TIMER_OUTCFG9_OUTCFG39_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69915   TIMER_OUTCFG9_OUTCFG39_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69916   TIMER_OUTCFG9_OUTCFG39_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69917   TIMER_OUTCFG9_OUTCFG39_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69918   TIMER_OUTCFG9_OUTCFG39_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69919   TIMER_OUTCFG9_OUTCFG39_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69920   TIMER_OUTCFG9_OUTCFG39_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69921   TIMER_OUTCFG9_OUTCFG39_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69922   TIMER_OUTCFG9_OUTCFG39_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69923   TIMER_OUTCFG9_OUTCFG39_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69924   TIMER_OUTCFG9_OUTCFG39_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69925   TIMER_OUTCFG9_OUTCFG39_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69926   TIMER_OUTCFG9_OUTCFG39_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69927   TIMER_OUTCFG9_OUTCFG39_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69928   TIMER_OUTCFG9_OUTCFG39_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69929   TIMER_OUTCFG9_OUTCFG39_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69930   TIMER_OUTCFG9_OUTCFG39_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69931   TIMER_OUTCFG9_OUTCFG39_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69932   TIMER_OUTCFG9_OUTCFG39_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69933   TIMER_OUTCFG9_OUTCFG39_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69934   TIMER_OUTCFG9_OUTCFG39_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69935 } TIMER_OUTCFG9_OUTCFG39_Enum;
69936 
69937 /* ============================================  TIMER OUTCFG9 OUTCFG38 [16..21]  ============================================ */
69938 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG38                                                    */
69939   TIMER_OUTCFG9_OUTCFG38_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69940   TIMER_OUTCFG9_OUTCFG38_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69941   TIMER_OUTCFG9_OUTCFG38_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69942   TIMER_OUTCFG9_OUTCFG38_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69943   TIMER_OUTCFG9_OUTCFG38_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69944   TIMER_OUTCFG9_OUTCFG38_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69945   TIMER_OUTCFG9_OUTCFG38_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69946   TIMER_OUTCFG9_OUTCFG38_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69947   TIMER_OUTCFG9_OUTCFG38_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69948   TIMER_OUTCFG9_OUTCFG38_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69949   TIMER_OUTCFG9_OUTCFG38_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69950   TIMER_OUTCFG9_OUTCFG38_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69951   TIMER_OUTCFG9_OUTCFG38_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69952   TIMER_OUTCFG9_OUTCFG38_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69953   TIMER_OUTCFG9_OUTCFG38_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69954   TIMER_OUTCFG9_OUTCFG38_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69955   TIMER_OUTCFG9_OUTCFG38_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69956   TIMER_OUTCFG9_OUTCFG38_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69957   TIMER_OUTCFG9_OUTCFG38_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69958   TIMER_OUTCFG9_OUTCFG38_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69959   TIMER_OUTCFG9_OUTCFG38_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69960   TIMER_OUTCFG9_OUTCFG38_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69961   TIMER_OUTCFG9_OUTCFG38_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69962   TIMER_OUTCFG9_OUTCFG38_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69963   TIMER_OUTCFG9_OUTCFG38_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69964   TIMER_OUTCFG9_OUTCFG38_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69965   TIMER_OUTCFG9_OUTCFG38_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69966   TIMER_OUTCFG9_OUTCFG38_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69967   TIMER_OUTCFG9_OUTCFG38_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69968   TIMER_OUTCFG9_OUTCFG38_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69969   TIMER_OUTCFG9_OUTCFG38_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69970   TIMER_OUTCFG9_OUTCFG38_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69971   TIMER_OUTCFG9_OUTCFG38_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69972   TIMER_OUTCFG9_OUTCFG38_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69973   TIMER_OUTCFG9_OUTCFG38_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69974   TIMER_OUTCFG9_OUTCFG38_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69975   TIMER_OUTCFG9_OUTCFG38_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69976   TIMER_OUTCFG9_OUTCFG38_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69977   TIMER_OUTCFG9_OUTCFG38_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69978   TIMER_OUTCFG9_OUTCFG38_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69979   TIMER_OUTCFG9_OUTCFG38_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
69980 } TIMER_OUTCFG9_OUTCFG38_Enum;
69981 
69982 /* ============================================  TIMER OUTCFG9 OUTCFG37 [8..13]  ============================================= */
69983 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG37                                                    */
69984   TIMER_OUTCFG9_OUTCFG37_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69985   TIMER_OUTCFG9_OUTCFG37_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69986   TIMER_OUTCFG9_OUTCFG37_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69987   TIMER_OUTCFG9_OUTCFG37_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69988   TIMER_OUTCFG9_OUTCFG37_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69989   TIMER_OUTCFG9_OUTCFG37_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69990   TIMER_OUTCFG9_OUTCFG37_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69991   TIMER_OUTCFG9_OUTCFG37_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69992   TIMER_OUTCFG9_OUTCFG37_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69993   TIMER_OUTCFG9_OUTCFG37_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69994   TIMER_OUTCFG9_OUTCFG37_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69995   TIMER_OUTCFG9_OUTCFG37_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69996   TIMER_OUTCFG9_OUTCFG37_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69997   TIMER_OUTCFG9_OUTCFG37_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69998   TIMER_OUTCFG9_OUTCFG37_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69999   TIMER_OUTCFG9_OUTCFG37_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70000   TIMER_OUTCFG9_OUTCFG37_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70001   TIMER_OUTCFG9_OUTCFG37_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70002   TIMER_OUTCFG9_OUTCFG37_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70003   TIMER_OUTCFG9_OUTCFG37_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70004   TIMER_OUTCFG9_OUTCFG37_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70005   TIMER_OUTCFG9_OUTCFG37_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70006   TIMER_OUTCFG9_OUTCFG37_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70007   TIMER_OUTCFG9_OUTCFG37_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70008   TIMER_OUTCFG9_OUTCFG37_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70009   TIMER_OUTCFG9_OUTCFG37_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70010   TIMER_OUTCFG9_OUTCFG37_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70011   TIMER_OUTCFG9_OUTCFG37_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70012   TIMER_OUTCFG9_OUTCFG37_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70013   TIMER_OUTCFG9_OUTCFG37_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70014   TIMER_OUTCFG9_OUTCFG37_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70015   TIMER_OUTCFG9_OUTCFG37_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70016   TIMER_OUTCFG9_OUTCFG37_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70017   TIMER_OUTCFG9_OUTCFG37_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70018   TIMER_OUTCFG9_OUTCFG37_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70019   TIMER_OUTCFG9_OUTCFG37_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70020   TIMER_OUTCFG9_OUTCFG37_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70021   TIMER_OUTCFG9_OUTCFG37_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70022   TIMER_OUTCFG9_OUTCFG37_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70023   TIMER_OUTCFG9_OUTCFG37_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70024   TIMER_OUTCFG9_OUTCFG37_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70025 } TIMER_OUTCFG9_OUTCFG37_Enum;
70026 
70027 /* =============================================  TIMER OUTCFG9 OUTCFG36 [0..5]  ============================================= */
70028 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG36                                                    */
70029   TIMER_OUTCFG9_OUTCFG36_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70030   TIMER_OUTCFG9_OUTCFG36_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70031   TIMER_OUTCFG9_OUTCFG36_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70032   TIMER_OUTCFG9_OUTCFG36_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70033   TIMER_OUTCFG9_OUTCFG36_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70034   TIMER_OUTCFG9_OUTCFG36_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70035   TIMER_OUTCFG9_OUTCFG36_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70036   TIMER_OUTCFG9_OUTCFG36_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70037   TIMER_OUTCFG9_OUTCFG36_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70038   TIMER_OUTCFG9_OUTCFG36_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70039   TIMER_OUTCFG9_OUTCFG36_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70040   TIMER_OUTCFG9_OUTCFG36_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70041   TIMER_OUTCFG9_OUTCFG36_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70042   TIMER_OUTCFG9_OUTCFG36_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70043   TIMER_OUTCFG9_OUTCFG36_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70044   TIMER_OUTCFG9_OUTCFG36_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70045   TIMER_OUTCFG9_OUTCFG36_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70046   TIMER_OUTCFG9_OUTCFG36_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70047   TIMER_OUTCFG9_OUTCFG36_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70048   TIMER_OUTCFG9_OUTCFG36_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70049   TIMER_OUTCFG9_OUTCFG36_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70050   TIMER_OUTCFG9_OUTCFG36_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70051   TIMER_OUTCFG9_OUTCFG36_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70052   TIMER_OUTCFG9_OUTCFG36_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70053   TIMER_OUTCFG9_OUTCFG36_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70054   TIMER_OUTCFG9_OUTCFG36_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70055   TIMER_OUTCFG9_OUTCFG36_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70056   TIMER_OUTCFG9_OUTCFG36_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70057   TIMER_OUTCFG9_OUTCFG36_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70058   TIMER_OUTCFG9_OUTCFG36_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70059   TIMER_OUTCFG9_OUTCFG36_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70060   TIMER_OUTCFG9_OUTCFG36_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70061   TIMER_OUTCFG9_OUTCFG36_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70062   TIMER_OUTCFG9_OUTCFG36_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70063   TIMER_OUTCFG9_OUTCFG36_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70064   TIMER_OUTCFG9_OUTCFG36_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70065   TIMER_OUTCFG9_OUTCFG36_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70066   TIMER_OUTCFG9_OUTCFG36_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70067   TIMER_OUTCFG9_OUTCFG36_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70068   TIMER_OUTCFG9_OUTCFG36_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70069   TIMER_OUTCFG9_OUTCFG36_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70070 } TIMER_OUTCFG9_OUTCFG36_Enum;
70071 
70072 /* =======================================================  OUTCFG10  ======================================================== */
70073 /* ===========================================  TIMER OUTCFG10 OUTCFG43 [24..29]  ============================================ */
70074 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG43                                                   */
70075   TIMER_OUTCFG10_OUTCFG43_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70076   TIMER_OUTCFG10_OUTCFG43_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70077   TIMER_OUTCFG10_OUTCFG43_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70078   TIMER_OUTCFG10_OUTCFG43_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70079   TIMER_OUTCFG10_OUTCFG43_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70080   TIMER_OUTCFG10_OUTCFG43_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70081   TIMER_OUTCFG10_OUTCFG43_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70082   TIMER_OUTCFG10_OUTCFG43_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70083   TIMER_OUTCFG10_OUTCFG43_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70084   TIMER_OUTCFG10_OUTCFG43_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70085   TIMER_OUTCFG10_OUTCFG43_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70086   TIMER_OUTCFG10_OUTCFG43_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70087   TIMER_OUTCFG10_OUTCFG43_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70088   TIMER_OUTCFG10_OUTCFG43_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70089   TIMER_OUTCFG10_OUTCFG43_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70090   TIMER_OUTCFG10_OUTCFG43_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70091   TIMER_OUTCFG10_OUTCFG43_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70092   TIMER_OUTCFG10_OUTCFG43_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70093   TIMER_OUTCFG10_OUTCFG43_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70094   TIMER_OUTCFG10_OUTCFG43_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70095   TIMER_OUTCFG10_OUTCFG43_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70096   TIMER_OUTCFG10_OUTCFG43_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70097   TIMER_OUTCFG10_OUTCFG43_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70098   TIMER_OUTCFG10_OUTCFG43_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70099   TIMER_OUTCFG10_OUTCFG43_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70100   TIMER_OUTCFG10_OUTCFG43_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70101   TIMER_OUTCFG10_OUTCFG43_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70102   TIMER_OUTCFG10_OUTCFG43_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70103   TIMER_OUTCFG10_OUTCFG43_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70104   TIMER_OUTCFG10_OUTCFG43_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70105   TIMER_OUTCFG10_OUTCFG43_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70106   TIMER_OUTCFG10_OUTCFG43_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70107   TIMER_OUTCFG10_OUTCFG43_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70108   TIMER_OUTCFG10_OUTCFG43_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70109   TIMER_OUTCFG10_OUTCFG43_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70110   TIMER_OUTCFG10_OUTCFG43_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70111   TIMER_OUTCFG10_OUTCFG43_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70112   TIMER_OUTCFG10_OUTCFG43_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70113   TIMER_OUTCFG10_OUTCFG43_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70114   TIMER_OUTCFG10_OUTCFG43_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70115   TIMER_OUTCFG10_OUTCFG43_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70116 } TIMER_OUTCFG10_OUTCFG43_Enum;
70117 
70118 /* ===========================================  TIMER OUTCFG10 OUTCFG42 [16..21]  ============================================ */
70119 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG42                                                   */
70120   TIMER_OUTCFG10_OUTCFG42_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70121   TIMER_OUTCFG10_OUTCFG42_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70122   TIMER_OUTCFG10_OUTCFG42_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70123   TIMER_OUTCFG10_OUTCFG42_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70124   TIMER_OUTCFG10_OUTCFG42_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70125   TIMER_OUTCFG10_OUTCFG42_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70126   TIMER_OUTCFG10_OUTCFG42_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70127   TIMER_OUTCFG10_OUTCFG42_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70128   TIMER_OUTCFG10_OUTCFG42_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70129   TIMER_OUTCFG10_OUTCFG42_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70130   TIMER_OUTCFG10_OUTCFG42_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70131   TIMER_OUTCFG10_OUTCFG42_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70132   TIMER_OUTCFG10_OUTCFG42_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70133   TIMER_OUTCFG10_OUTCFG42_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70134   TIMER_OUTCFG10_OUTCFG42_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70135   TIMER_OUTCFG10_OUTCFG42_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70136   TIMER_OUTCFG10_OUTCFG42_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70137   TIMER_OUTCFG10_OUTCFG42_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70138   TIMER_OUTCFG10_OUTCFG42_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70139   TIMER_OUTCFG10_OUTCFG42_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70140   TIMER_OUTCFG10_OUTCFG42_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70141   TIMER_OUTCFG10_OUTCFG42_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70142   TIMER_OUTCFG10_OUTCFG42_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70143   TIMER_OUTCFG10_OUTCFG42_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70144   TIMER_OUTCFG10_OUTCFG42_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70145   TIMER_OUTCFG10_OUTCFG42_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70146   TIMER_OUTCFG10_OUTCFG42_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70147   TIMER_OUTCFG10_OUTCFG42_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70148   TIMER_OUTCFG10_OUTCFG42_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70149   TIMER_OUTCFG10_OUTCFG42_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70150   TIMER_OUTCFG10_OUTCFG42_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70151   TIMER_OUTCFG10_OUTCFG42_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70152   TIMER_OUTCFG10_OUTCFG42_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70153   TIMER_OUTCFG10_OUTCFG42_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70154   TIMER_OUTCFG10_OUTCFG42_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70155   TIMER_OUTCFG10_OUTCFG42_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70156   TIMER_OUTCFG10_OUTCFG42_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70157   TIMER_OUTCFG10_OUTCFG42_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70158   TIMER_OUTCFG10_OUTCFG42_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70159   TIMER_OUTCFG10_OUTCFG42_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70160   TIMER_OUTCFG10_OUTCFG42_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70161 } TIMER_OUTCFG10_OUTCFG42_Enum;
70162 
70163 /* ============================================  TIMER OUTCFG10 OUTCFG41 [8..13]  ============================================ */
70164 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG41                                                   */
70165   TIMER_OUTCFG10_OUTCFG41_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70166   TIMER_OUTCFG10_OUTCFG41_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70167   TIMER_OUTCFG10_OUTCFG41_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70168   TIMER_OUTCFG10_OUTCFG41_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70169   TIMER_OUTCFG10_OUTCFG41_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70170   TIMER_OUTCFG10_OUTCFG41_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70171   TIMER_OUTCFG10_OUTCFG41_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70172   TIMER_OUTCFG10_OUTCFG41_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70173   TIMER_OUTCFG10_OUTCFG41_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70174   TIMER_OUTCFG10_OUTCFG41_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70175   TIMER_OUTCFG10_OUTCFG41_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70176   TIMER_OUTCFG10_OUTCFG41_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70177   TIMER_OUTCFG10_OUTCFG41_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70178   TIMER_OUTCFG10_OUTCFG41_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70179   TIMER_OUTCFG10_OUTCFG41_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70180   TIMER_OUTCFG10_OUTCFG41_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70181   TIMER_OUTCFG10_OUTCFG41_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70182   TIMER_OUTCFG10_OUTCFG41_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70183   TIMER_OUTCFG10_OUTCFG41_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70184   TIMER_OUTCFG10_OUTCFG41_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70185   TIMER_OUTCFG10_OUTCFG41_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70186   TIMER_OUTCFG10_OUTCFG41_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70187   TIMER_OUTCFG10_OUTCFG41_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70188   TIMER_OUTCFG10_OUTCFG41_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70189   TIMER_OUTCFG10_OUTCFG41_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70190   TIMER_OUTCFG10_OUTCFG41_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70191   TIMER_OUTCFG10_OUTCFG41_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70192   TIMER_OUTCFG10_OUTCFG41_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70193   TIMER_OUTCFG10_OUTCFG41_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70194   TIMER_OUTCFG10_OUTCFG41_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70195   TIMER_OUTCFG10_OUTCFG41_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70196   TIMER_OUTCFG10_OUTCFG41_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70197   TIMER_OUTCFG10_OUTCFG41_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70198   TIMER_OUTCFG10_OUTCFG41_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70199   TIMER_OUTCFG10_OUTCFG41_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70200   TIMER_OUTCFG10_OUTCFG41_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70201   TIMER_OUTCFG10_OUTCFG41_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70202   TIMER_OUTCFG10_OUTCFG41_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70203   TIMER_OUTCFG10_OUTCFG41_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70204   TIMER_OUTCFG10_OUTCFG41_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70205   TIMER_OUTCFG10_OUTCFG41_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70206 } TIMER_OUTCFG10_OUTCFG41_Enum;
70207 
70208 /* ============================================  TIMER OUTCFG10 OUTCFG40 [0..5]  ============================================= */
70209 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG40                                                   */
70210   TIMER_OUTCFG10_OUTCFG40_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70211   TIMER_OUTCFG10_OUTCFG40_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70212   TIMER_OUTCFG10_OUTCFG40_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70213   TIMER_OUTCFG10_OUTCFG40_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70214   TIMER_OUTCFG10_OUTCFG40_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70215   TIMER_OUTCFG10_OUTCFG40_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70216   TIMER_OUTCFG10_OUTCFG40_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70217   TIMER_OUTCFG10_OUTCFG40_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70218   TIMER_OUTCFG10_OUTCFG40_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70219   TIMER_OUTCFG10_OUTCFG40_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70220   TIMER_OUTCFG10_OUTCFG40_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70221   TIMER_OUTCFG10_OUTCFG40_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70222   TIMER_OUTCFG10_OUTCFG40_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70223   TIMER_OUTCFG10_OUTCFG40_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70224   TIMER_OUTCFG10_OUTCFG40_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70225   TIMER_OUTCFG10_OUTCFG40_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70226   TIMER_OUTCFG10_OUTCFG40_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70227   TIMER_OUTCFG10_OUTCFG40_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70228   TIMER_OUTCFG10_OUTCFG40_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70229   TIMER_OUTCFG10_OUTCFG40_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70230   TIMER_OUTCFG10_OUTCFG40_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70231   TIMER_OUTCFG10_OUTCFG40_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70232   TIMER_OUTCFG10_OUTCFG40_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70233   TIMER_OUTCFG10_OUTCFG40_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70234   TIMER_OUTCFG10_OUTCFG40_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70235   TIMER_OUTCFG10_OUTCFG40_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70236   TIMER_OUTCFG10_OUTCFG40_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70237   TIMER_OUTCFG10_OUTCFG40_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70238   TIMER_OUTCFG10_OUTCFG40_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70239   TIMER_OUTCFG10_OUTCFG40_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70240   TIMER_OUTCFG10_OUTCFG40_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70241   TIMER_OUTCFG10_OUTCFG40_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70242   TIMER_OUTCFG10_OUTCFG40_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70243   TIMER_OUTCFG10_OUTCFG40_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70244   TIMER_OUTCFG10_OUTCFG40_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70245   TIMER_OUTCFG10_OUTCFG40_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70246   TIMER_OUTCFG10_OUTCFG40_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70247   TIMER_OUTCFG10_OUTCFG40_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70248   TIMER_OUTCFG10_OUTCFG40_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70249   TIMER_OUTCFG10_OUTCFG40_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70250   TIMER_OUTCFG10_OUTCFG40_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70251 } TIMER_OUTCFG10_OUTCFG40_Enum;
70252 
70253 /* =======================================================  OUTCFG11  ======================================================== */
70254 /* ===========================================  TIMER OUTCFG11 OUTCFG47 [24..29]  ============================================ */
70255 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG47                                                   */
70256   TIMER_OUTCFG11_OUTCFG47_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70257   TIMER_OUTCFG11_OUTCFG47_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70258   TIMER_OUTCFG11_OUTCFG47_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70259   TIMER_OUTCFG11_OUTCFG47_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70260   TIMER_OUTCFG11_OUTCFG47_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70261   TIMER_OUTCFG11_OUTCFG47_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70262   TIMER_OUTCFG11_OUTCFG47_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70263   TIMER_OUTCFG11_OUTCFG47_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70264   TIMER_OUTCFG11_OUTCFG47_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70265   TIMER_OUTCFG11_OUTCFG47_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70266   TIMER_OUTCFG11_OUTCFG47_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70267   TIMER_OUTCFG11_OUTCFG47_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70268   TIMER_OUTCFG11_OUTCFG47_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70269   TIMER_OUTCFG11_OUTCFG47_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70270   TIMER_OUTCFG11_OUTCFG47_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70271   TIMER_OUTCFG11_OUTCFG47_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70272   TIMER_OUTCFG11_OUTCFG47_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70273   TIMER_OUTCFG11_OUTCFG47_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70274   TIMER_OUTCFG11_OUTCFG47_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70275   TIMER_OUTCFG11_OUTCFG47_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70276   TIMER_OUTCFG11_OUTCFG47_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70277   TIMER_OUTCFG11_OUTCFG47_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70278   TIMER_OUTCFG11_OUTCFG47_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70279   TIMER_OUTCFG11_OUTCFG47_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70280   TIMER_OUTCFG11_OUTCFG47_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70281   TIMER_OUTCFG11_OUTCFG47_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70282   TIMER_OUTCFG11_OUTCFG47_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70283   TIMER_OUTCFG11_OUTCFG47_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70284   TIMER_OUTCFG11_OUTCFG47_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70285   TIMER_OUTCFG11_OUTCFG47_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70286   TIMER_OUTCFG11_OUTCFG47_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70287   TIMER_OUTCFG11_OUTCFG47_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70288   TIMER_OUTCFG11_OUTCFG47_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70289   TIMER_OUTCFG11_OUTCFG47_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70290   TIMER_OUTCFG11_OUTCFG47_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70291   TIMER_OUTCFG11_OUTCFG47_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70292   TIMER_OUTCFG11_OUTCFG47_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70293   TIMER_OUTCFG11_OUTCFG47_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70294   TIMER_OUTCFG11_OUTCFG47_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70295   TIMER_OUTCFG11_OUTCFG47_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70296   TIMER_OUTCFG11_OUTCFG47_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70297 } TIMER_OUTCFG11_OUTCFG47_Enum;
70298 
70299 /* ===========================================  TIMER OUTCFG11 OUTCFG46 [16..21]  ============================================ */
70300 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG46                                                   */
70301   TIMER_OUTCFG11_OUTCFG46_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70302   TIMER_OUTCFG11_OUTCFG46_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70303   TIMER_OUTCFG11_OUTCFG46_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70304   TIMER_OUTCFG11_OUTCFG46_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70305   TIMER_OUTCFG11_OUTCFG46_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70306   TIMER_OUTCFG11_OUTCFG46_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70307   TIMER_OUTCFG11_OUTCFG46_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70308   TIMER_OUTCFG11_OUTCFG46_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70309   TIMER_OUTCFG11_OUTCFG46_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70310   TIMER_OUTCFG11_OUTCFG46_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70311   TIMER_OUTCFG11_OUTCFG46_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70312   TIMER_OUTCFG11_OUTCFG46_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70313   TIMER_OUTCFG11_OUTCFG46_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70314   TIMER_OUTCFG11_OUTCFG46_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70315   TIMER_OUTCFG11_OUTCFG46_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70316   TIMER_OUTCFG11_OUTCFG46_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70317   TIMER_OUTCFG11_OUTCFG46_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70318   TIMER_OUTCFG11_OUTCFG46_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70319   TIMER_OUTCFG11_OUTCFG46_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70320   TIMER_OUTCFG11_OUTCFG46_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70321   TIMER_OUTCFG11_OUTCFG46_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70322   TIMER_OUTCFG11_OUTCFG46_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70323   TIMER_OUTCFG11_OUTCFG46_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70324   TIMER_OUTCFG11_OUTCFG46_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70325   TIMER_OUTCFG11_OUTCFG46_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70326   TIMER_OUTCFG11_OUTCFG46_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70327   TIMER_OUTCFG11_OUTCFG46_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70328   TIMER_OUTCFG11_OUTCFG46_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70329   TIMER_OUTCFG11_OUTCFG46_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70330   TIMER_OUTCFG11_OUTCFG46_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70331   TIMER_OUTCFG11_OUTCFG46_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70332   TIMER_OUTCFG11_OUTCFG46_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70333   TIMER_OUTCFG11_OUTCFG46_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70334   TIMER_OUTCFG11_OUTCFG46_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70335   TIMER_OUTCFG11_OUTCFG46_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70336   TIMER_OUTCFG11_OUTCFG46_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70337   TIMER_OUTCFG11_OUTCFG46_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70338   TIMER_OUTCFG11_OUTCFG46_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70339   TIMER_OUTCFG11_OUTCFG46_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70340   TIMER_OUTCFG11_OUTCFG46_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70341   TIMER_OUTCFG11_OUTCFG46_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70342 } TIMER_OUTCFG11_OUTCFG46_Enum;
70343 
70344 /* ============================================  TIMER OUTCFG11 OUTCFG45 [8..13]  ============================================ */
70345 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG45                                                   */
70346   TIMER_OUTCFG11_OUTCFG45_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70347   TIMER_OUTCFG11_OUTCFG45_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70348   TIMER_OUTCFG11_OUTCFG45_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70349   TIMER_OUTCFG11_OUTCFG45_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70350   TIMER_OUTCFG11_OUTCFG45_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70351   TIMER_OUTCFG11_OUTCFG45_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70352   TIMER_OUTCFG11_OUTCFG45_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70353   TIMER_OUTCFG11_OUTCFG45_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70354   TIMER_OUTCFG11_OUTCFG45_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70355   TIMER_OUTCFG11_OUTCFG45_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70356   TIMER_OUTCFG11_OUTCFG45_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70357   TIMER_OUTCFG11_OUTCFG45_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70358   TIMER_OUTCFG11_OUTCFG45_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70359   TIMER_OUTCFG11_OUTCFG45_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70360   TIMER_OUTCFG11_OUTCFG45_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70361   TIMER_OUTCFG11_OUTCFG45_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70362   TIMER_OUTCFG11_OUTCFG45_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70363   TIMER_OUTCFG11_OUTCFG45_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70364   TIMER_OUTCFG11_OUTCFG45_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70365   TIMER_OUTCFG11_OUTCFG45_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70366   TIMER_OUTCFG11_OUTCFG45_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70367   TIMER_OUTCFG11_OUTCFG45_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70368   TIMER_OUTCFG11_OUTCFG45_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70369   TIMER_OUTCFG11_OUTCFG45_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70370   TIMER_OUTCFG11_OUTCFG45_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70371   TIMER_OUTCFG11_OUTCFG45_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70372   TIMER_OUTCFG11_OUTCFG45_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70373   TIMER_OUTCFG11_OUTCFG45_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70374   TIMER_OUTCFG11_OUTCFG45_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70375   TIMER_OUTCFG11_OUTCFG45_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70376   TIMER_OUTCFG11_OUTCFG45_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70377   TIMER_OUTCFG11_OUTCFG45_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70378   TIMER_OUTCFG11_OUTCFG45_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70379   TIMER_OUTCFG11_OUTCFG45_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70380   TIMER_OUTCFG11_OUTCFG45_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70381   TIMER_OUTCFG11_OUTCFG45_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70382   TIMER_OUTCFG11_OUTCFG45_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70383   TIMER_OUTCFG11_OUTCFG45_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70384   TIMER_OUTCFG11_OUTCFG45_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70385   TIMER_OUTCFG11_OUTCFG45_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70386   TIMER_OUTCFG11_OUTCFG45_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70387 } TIMER_OUTCFG11_OUTCFG45_Enum;
70388 
70389 /* ============================================  TIMER OUTCFG11 OUTCFG44 [0..5]  ============================================= */
70390 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG44                                                   */
70391   TIMER_OUTCFG11_OUTCFG44_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70392   TIMER_OUTCFG11_OUTCFG44_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70393   TIMER_OUTCFG11_OUTCFG44_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70394   TIMER_OUTCFG11_OUTCFG44_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70395   TIMER_OUTCFG11_OUTCFG44_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70396   TIMER_OUTCFG11_OUTCFG44_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70397   TIMER_OUTCFG11_OUTCFG44_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70398   TIMER_OUTCFG11_OUTCFG44_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70399   TIMER_OUTCFG11_OUTCFG44_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70400   TIMER_OUTCFG11_OUTCFG44_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70401   TIMER_OUTCFG11_OUTCFG44_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70402   TIMER_OUTCFG11_OUTCFG44_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70403   TIMER_OUTCFG11_OUTCFG44_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70404   TIMER_OUTCFG11_OUTCFG44_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70405   TIMER_OUTCFG11_OUTCFG44_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70406   TIMER_OUTCFG11_OUTCFG44_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70407   TIMER_OUTCFG11_OUTCFG44_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70408   TIMER_OUTCFG11_OUTCFG44_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70409   TIMER_OUTCFG11_OUTCFG44_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70410   TIMER_OUTCFG11_OUTCFG44_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70411   TIMER_OUTCFG11_OUTCFG44_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70412   TIMER_OUTCFG11_OUTCFG44_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70413   TIMER_OUTCFG11_OUTCFG44_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70414   TIMER_OUTCFG11_OUTCFG44_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70415   TIMER_OUTCFG11_OUTCFG44_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70416   TIMER_OUTCFG11_OUTCFG44_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70417   TIMER_OUTCFG11_OUTCFG44_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70418   TIMER_OUTCFG11_OUTCFG44_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70419   TIMER_OUTCFG11_OUTCFG44_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70420   TIMER_OUTCFG11_OUTCFG44_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70421   TIMER_OUTCFG11_OUTCFG44_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70422   TIMER_OUTCFG11_OUTCFG44_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70423   TIMER_OUTCFG11_OUTCFG44_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70424   TIMER_OUTCFG11_OUTCFG44_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70425   TIMER_OUTCFG11_OUTCFG44_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70426   TIMER_OUTCFG11_OUTCFG44_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70427   TIMER_OUTCFG11_OUTCFG44_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70428   TIMER_OUTCFG11_OUTCFG44_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70429   TIMER_OUTCFG11_OUTCFG44_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70430   TIMER_OUTCFG11_OUTCFG44_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70431   TIMER_OUTCFG11_OUTCFG44_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70432 } TIMER_OUTCFG11_OUTCFG44_Enum;
70433 
70434 /* =======================================================  OUTCFG12  ======================================================== */
70435 /* ===========================================  TIMER OUTCFG12 OUTCFG51 [24..29]  ============================================ */
70436 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG51                                                   */
70437   TIMER_OUTCFG12_OUTCFG51_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70438   TIMER_OUTCFG12_OUTCFG51_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70439   TIMER_OUTCFG12_OUTCFG51_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70440   TIMER_OUTCFG12_OUTCFG51_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70441   TIMER_OUTCFG12_OUTCFG51_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70442   TIMER_OUTCFG12_OUTCFG51_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70443   TIMER_OUTCFG12_OUTCFG51_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70444   TIMER_OUTCFG12_OUTCFG51_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70445   TIMER_OUTCFG12_OUTCFG51_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70446   TIMER_OUTCFG12_OUTCFG51_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70447   TIMER_OUTCFG12_OUTCFG51_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70448   TIMER_OUTCFG12_OUTCFG51_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70449   TIMER_OUTCFG12_OUTCFG51_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70450   TIMER_OUTCFG12_OUTCFG51_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70451   TIMER_OUTCFG12_OUTCFG51_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70452   TIMER_OUTCFG12_OUTCFG51_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70453   TIMER_OUTCFG12_OUTCFG51_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70454   TIMER_OUTCFG12_OUTCFG51_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70455   TIMER_OUTCFG12_OUTCFG51_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70456   TIMER_OUTCFG12_OUTCFG51_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70457   TIMER_OUTCFG12_OUTCFG51_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70458   TIMER_OUTCFG12_OUTCFG51_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70459   TIMER_OUTCFG12_OUTCFG51_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70460   TIMER_OUTCFG12_OUTCFG51_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70461   TIMER_OUTCFG12_OUTCFG51_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70462   TIMER_OUTCFG12_OUTCFG51_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70463   TIMER_OUTCFG12_OUTCFG51_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70464   TIMER_OUTCFG12_OUTCFG51_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70465   TIMER_OUTCFG12_OUTCFG51_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70466   TIMER_OUTCFG12_OUTCFG51_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70467   TIMER_OUTCFG12_OUTCFG51_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70468   TIMER_OUTCFG12_OUTCFG51_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70469   TIMER_OUTCFG12_OUTCFG51_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70470   TIMER_OUTCFG12_OUTCFG51_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70471   TIMER_OUTCFG12_OUTCFG51_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70472   TIMER_OUTCFG12_OUTCFG51_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70473   TIMER_OUTCFG12_OUTCFG51_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70474   TIMER_OUTCFG12_OUTCFG51_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70475   TIMER_OUTCFG12_OUTCFG51_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70476   TIMER_OUTCFG12_OUTCFG51_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70477   TIMER_OUTCFG12_OUTCFG51_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70478 } TIMER_OUTCFG12_OUTCFG51_Enum;
70479 
70480 /* ===========================================  TIMER OUTCFG12 OUTCFG50 [16..21]  ============================================ */
70481 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG50                                                   */
70482   TIMER_OUTCFG12_OUTCFG50_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70483   TIMER_OUTCFG12_OUTCFG50_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70484   TIMER_OUTCFG12_OUTCFG50_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70485   TIMER_OUTCFG12_OUTCFG50_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70486   TIMER_OUTCFG12_OUTCFG50_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70487   TIMER_OUTCFG12_OUTCFG50_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70488   TIMER_OUTCFG12_OUTCFG50_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70489   TIMER_OUTCFG12_OUTCFG50_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70490   TIMER_OUTCFG12_OUTCFG50_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70491   TIMER_OUTCFG12_OUTCFG50_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70492   TIMER_OUTCFG12_OUTCFG50_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70493   TIMER_OUTCFG12_OUTCFG50_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70494   TIMER_OUTCFG12_OUTCFG50_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70495   TIMER_OUTCFG12_OUTCFG50_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70496   TIMER_OUTCFG12_OUTCFG50_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70497   TIMER_OUTCFG12_OUTCFG50_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70498   TIMER_OUTCFG12_OUTCFG50_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70499   TIMER_OUTCFG12_OUTCFG50_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70500   TIMER_OUTCFG12_OUTCFG50_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70501   TIMER_OUTCFG12_OUTCFG50_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70502   TIMER_OUTCFG12_OUTCFG50_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70503   TIMER_OUTCFG12_OUTCFG50_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70504   TIMER_OUTCFG12_OUTCFG50_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70505   TIMER_OUTCFG12_OUTCFG50_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70506   TIMER_OUTCFG12_OUTCFG50_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70507   TIMER_OUTCFG12_OUTCFG50_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70508   TIMER_OUTCFG12_OUTCFG50_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70509   TIMER_OUTCFG12_OUTCFG50_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70510   TIMER_OUTCFG12_OUTCFG50_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70511   TIMER_OUTCFG12_OUTCFG50_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70512   TIMER_OUTCFG12_OUTCFG50_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70513   TIMER_OUTCFG12_OUTCFG50_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70514   TIMER_OUTCFG12_OUTCFG50_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70515   TIMER_OUTCFG12_OUTCFG50_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70516   TIMER_OUTCFG12_OUTCFG50_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70517   TIMER_OUTCFG12_OUTCFG50_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70518   TIMER_OUTCFG12_OUTCFG50_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70519   TIMER_OUTCFG12_OUTCFG50_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70520   TIMER_OUTCFG12_OUTCFG50_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70521   TIMER_OUTCFG12_OUTCFG50_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70522   TIMER_OUTCFG12_OUTCFG50_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70523 } TIMER_OUTCFG12_OUTCFG50_Enum;
70524 
70525 /* ============================================  TIMER OUTCFG12 OUTCFG49 [8..13]  ============================================ */
70526 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG49                                                   */
70527   TIMER_OUTCFG12_OUTCFG49_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70528   TIMER_OUTCFG12_OUTCFG49_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70529   TIMER_OUTCFG12_OUTCFG49_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70530   TIMER_OUTCFG12_OUTCFG49_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70531   TIMER_OUTCFG12_OUTCFG49_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70532   TIMER_OUTCFG12_OUTCFG49_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70533   TIMER_OUTCFG12_OUTCFG49_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70534   TIMER_OUTCFG12_OUTCFG49_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70535   TIMER_OUTCFG12_OUTCFG49_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70536   TIMER_OUTCFG12_OUTCFG49_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70537   TIMER_OUTCFG12_OUTCFG49_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70538   TIMER_OUTCFG12_OUTCFG49_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70539   TIMER_OUTCFG12_OUTCFG49_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70540   TIMER_OUTCFG12_OUTCFG49_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70541   TIMER_OUTCFG12_OUTCFG49_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70542   TIMER_OUTCFG12_OUTCFG49_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70543   TIMER_OUTCFG12_OUTCFG49_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70544   TIMER_OUTCFG12_OUTCFG49_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70545   TIMER_OUTCFG12_OUTCFG49_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70546   TIMER_OUTCFG12_OUTCFG49_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70547   TIMER_OUTCFG12_OUTCFG49_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70548   TIMER_OUTCFG12_OUTCFG49_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70549   TIMER_OUTCFG12_OUTCFG49_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70550   TIMER_OUTCFG12_OUTCFG49_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70551   TIMER_OUTCFG12_OUTCFG49_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70552   TIMER_OUTCFG12_OUTCFG49_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70553   TIMER_OUTCFG12_OUTCFG49_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70554   TIMER_OUTCFG12_OUTCFG49_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70555   TIMER_OUTCFG12_OUTCFG49_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70556   TIMER_OUTCFG12_OUTCFG49_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70557   TIMER_OUTCFG12_OUTCFG49_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70558   TIMER_OUTCFG12_OUTCFG49_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70559   TIMER_OUTCFG12_OUTCFG49_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70560   TIMER_OUTCFG12_OUTCFG49_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70561   TIMER_OUTCFG12_OUTCFG49_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70562   TIMER_OUTCFG12_OUTCFG49_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70563   TIMER_OUTCFG12_OUTCFG49_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70564   TIMER_OUTCFG12_OUTCFG49_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70565   TIMER_OUTCFG12_OUTCFG49_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70566   TIMER_OUTCFG12_OUTCFG49_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70567   TIMER_OUTCFG12_OUTCFG49_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70568 } TIMER_OUTCFG12_OUTCFG49_Enum;
70569 
70570 /* ============================================  TIMER OUTCFG12 OUTCFG48 [0..5]  ============================================= */
70571 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG48                                                   */
70572   TIMER_OUTCFG12_OUTCFG48_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70573   TIMER_OUTCFG12_OUTCFG48_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70574   TIMER_OUTCFG12_OUTCFG48_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70575   TIMER_OUTCFG12_OUTCFG48_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70576   TIMER_OUTCFG12_OUTCFG48_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70577   TIMER_OUTCFG12_OUTCFG48_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70578   TIMER_OUTCFG12_OUTCFG48_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70579   TIMER_OUTCFG12_OUTCFG48_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70580   TIMER_OUTCFG12_OUTCFG48_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70581   TIMER_OUTCFG12_OUTCFG48_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70582   TIMER_OUTCFG12_OUTCFG48_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70583   TIMER_OUTCFG12_OUTCFG48_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70584   TIMER_OUTCFG12_OUTCFG48_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70585   TIMER_OUTCFG12_OUTCFG48_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70586   TIMER_OUTCFG12_OUTCFG48_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70587   TIMER_OUTCFG12_OUTCFG48_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70588   TIMER_OUTCFG12_OUTCFG48_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70589   TIMER_OUTCFG12_OUTCFG48_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70590   TIMER_OUTCFG12_OUTCFG48_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70591   TIMER_OUTCFG12_OUTCFG48_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70592   TIMER_OUTCFG12_OUTCFG48_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70593   TIMER_OUTCFG12_OUTCFG48_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70594   TIMER_OUTCFG12_OUTCFG48_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70595   TIMER_OUTCFG12_OUTCFG48_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70596   TIMER_OUTCFG12_OUTCFG48_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70597   TIMER_OUTCFG12_OUTCFG48_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70598   TIMER_OUTCFG12_OUTCFG48_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70599   TIMER_OUTCFG12_OUTCFG48_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70600   TIMER_OUTCFG12_OUTCFG48_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70601   TIMER_OUTCFG12_OUTCFG48_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70602   TIMER_OUTCFG12_OUTCFG48_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70603   TIMER_OUTCFG12_OUTCFG48_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70604   TIMER_OUTCFG12_OUTCFG48_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70605   TIMER_OUTCFG12_OUTCFG48_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70606   TIMER_OUTCFG12_OUTCFG48_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70607   TIMER_OUTCFG12_OUTCFG48_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70608   TIMER_OUTCFG12_OUTCFG48_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70609   TIMER_OUTCFG12_OUTCFG48_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70610   TIMER_OUTCFG12_OUTCFG48_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70611   TIMER_OUTCFG12_OUTCFG48_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70612   TIMER_OUTCFG12_OUTCFG48_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70613 } TIMER_OUTCFG12_OUTCFG48_Enum;
70614 
70615 /* =======================================================  OUTCFG13  ======================================================== */
70616 /* ===========================================  TIMER OUTCFG13 OUTCFG55 [24..29]  ============================================ */
70617 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG55                                                   */
70618   TIMER_OUTCFG13_OUTCFG55_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70619   TIMER_OUTCFG13_OUTCFG55_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70620   TIMER_OUTCFG13_OUTCFG55_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70621   TIMER_OUTCFG13_OUTCFG55_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70622   TIMER_OUTCFG13_OUTCFG55_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70623   TIMER_OUTCFG13_OUTCFG55_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70624   TIMER_OUTCFG13_OUTCFG55_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70625   TIMER_OUTCFG13_OUTCFG55_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70626   TIMER_OUTCFG13_OUTCFG55_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70627   TIMER_OUTCFG13_OUTCFG55_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70628   TIMER_OUTCFG13_OUTCFG55_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70629   TIMER_OUTCFG13_OUTCFG55_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70630   TIMER_OUTCFG13_OUTCFG55_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70631   TIMER_OUTCFG13_OUTCFG55_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70632   TIMER_OUTCFG13_OUTCFG55_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70633   TIMER_OUTCFG13_OUTCFG55_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70634   TIMER_OUTCFG13_OUTCFG55_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70635   TIMER_OUTCFG13_OUTCFG55_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70636   TIMER_OUTCFG13_OUTCFG55_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70637   TIMER_OUTCFG13_OUTCFG55_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70638   TIMER_OUTCFG13_OUTCFG55_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70639   TIMER_OUTCFG13_OUTCFG55_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70640   TIMER_OUTCFG13_OUTCFG55_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70641   TIMER_OUTCFG13_OUTCFG55_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70642   TIMER_OUTCFG13_OUTCFG55_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70643   TIMER_OUTCFG13_OUTCFG55_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70644   TIMER_OUTCFG13_OUTCFG55_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70645   TIMER_OUTCFG13_OUTCFG55_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70646   TIMER_OUTCFG13_OUTCFG55_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70647   TIMER_OUTCFG13_OUTCFG55_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70648   TIMER_OUTCFG13_OUTCFG55_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70649   TIMER_OUTCFG13_OUTCFG55_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70650   TIMER_OUTCFG13_OUTCFG55_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70651   TIMER_OUTCFG13_OUTCFG55_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70652   TIMER_OUTCFG13_OUTCFG55_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70653   TIMER_OUTCFG13_OUTCFG55_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70654   TIMER_OUTCFG13_OUTCFG55_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70655   TIMER_OUTCFG13_OUTCFG55_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70656   TIMER_OUTCFG13_OUTCFG55_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70657   TIMER_OUTCFG13_OUTCFG55_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70658   TIMER_OUTCFG13_OUTCFG55_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70659 } TIMER_OUTCFG13_OUTCFG55_Enum;
70660 
70661 /* ===========================================  TIMER OUTCFG13 OUTCFG54 [16..21]  ============================================ */
70662 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG54                                                   */
70663   TIMER_OUTCFG13_OUTCFG54_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70664   TIMER_OUTCFG13_OUTCFG54_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70665   TIMER_OUTCFG13_OUTCFG54_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70666   TIMER_OUTCFG13_OUTCFG54_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70667   TIMER_OUTCFG13_OUTCFG54_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70668   TIMER_OUTCFG13_OUTCFG54_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70669   TIMER_OUTCFG13_OUTCFG54_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70670   TIMER_OUTCFG13_OUTCFG54_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70671   TIMER_OUTCFG13_OUTCFG54_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70672   TIMER_OUTCFG13_OUTCFG54_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70673   TIMER_OUTCFG13_OUTCFG54_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70674   TIMER_OUTCFG13_OUTCFG54_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70675   TIMER_OUTCFG13_OUTCFG54_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70676   TIMER_OUTCFG13_OUTCFG54_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70677   TIMER_OUTCFG13_OUTCFG54_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70678   TIMER_OUTCFG13_OUTCFG54_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70679   TIMER_OUTCFG13_OUTCFG54_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70680   TIMER_OUTCFG13_OUTCFG54_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70681   TIMER_OUTCFG13_OUTCFG54_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70682   TIMER_OUTCFG13_OUTCFG54_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70683   TIMER_OUTCFG13_OUTCFG54_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70684   TIMER_OUTCFG13_OUTCFG54_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70685   TIMER_OUTCFG13_OUTCFG54_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70686   TIMER_OUTCFG13_OUTCFG54_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70687   TIMER_OUTCFG13_OUTCFG54_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70688   TIMER_OUTCFG13_OUTCFG54_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70689   TIMER_OUTCFG13_OUTCFG54_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70690   TIMER_OUTCFG13_OUTCFG54_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70691   TIMER_OUTCFG13_OUTCFG54_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70692   TIMER_OUTCFG13_OUTCFG54_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70693   TIMER_OUTCFG13_OUTCFG54_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70694   TIMER_OUTCFG13_OUTCFG54_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70695   TIMER_OUTCFG13_OUTCFG54_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70696   TIMER_OUTCFG13_OUTCFG54_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70697   TIMER_OUTCFG13_OUTCFG54_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70698   TIMER_OUTCFG13_OUTCFG54_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70699   TIMER_OUTCFG13_OUTCFG54_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70700   TIMER_OUTCFG13_OUTCFG54_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70701   TIMER_OUTCFG13_OUTCFG54_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70702   TIMER_OUTCFG13_OUTCFG54_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70703   TIMER_OUTCFG13_OUTCFG54_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70704 } TIMER_OUTCFG13_OUTCFG54_Enum;
70705 
70706 /* ============================================  TIMER OUTCFG13 OUTCFG53 [8..13]  ============================================ */
70707 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG53                                                   */
70708   TIMER_OUTCFG13_OUTCFG53_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70709   TIMER_OUTCFG13_OUTCFG53_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70710   TIMER_OUTCFG13_OUTCFG53_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70711   TIMER_OUTCFG13_OUTCFG53_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70712   TIMER_OUTCFG13_OUTCFG53_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70713   TIMER_OUTCFG13_OUTCFG53_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70714   TIMER_OUTCFG13_OUTCFG53_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70715   TIMER_OUTCFG13_OUTCFG53_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70716   TIMER_OUTCFG13_OUTCFG53_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70717   TIMER_OUTCFG13_OUTCFG53_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70718   TIMER_OUTCFG13_OUTCFG53_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70719   TIMER_OUTCFG13_OUTCFG53_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70720   TIMER_OUTCFG13_OUTCFG53_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70721   TIMER_OUTCFG13_OUTCFG53_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70722   TIMER_OUTCFG13_OUTCFG53_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70723   TIMER_OUTCFG13_OUTCFG53_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70724   TIMER_OUTCFG13_OUTCFG53_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70725   TIMER_OUTCFG13_OUTCFG53_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70726   TIMER_OUTCFG13_OUTCFG53_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70727   TIMER_OUTCFG13_OUTCFG53_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70728   TIMER_OUTCFG13_OUTCFG53_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70729   TIMER_OUTCFG13_OUTCFG53_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70730   TIMER_OUTCFG13_OUTCFG53_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70731   TIMER_OUTCFG13_OUTCFG53_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70732   TIMER_OUTCFG13_OUTCFG53_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70733   TIMER_OUTCFG13_OUTCFG53_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70734   TIMER_OUTCFG13_OUTCFG53_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70735   TIMER_OUTCFG13_OUTCFG53_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70736   TIMER_OUTCFG13_OUTCFG53_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70737   TIMER_OUTCFG13_OUTCFG53_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70738   TIMER_OUTCFG13_OUTCFG53_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70739   TIMER_OUTCFG13_OUTCFG53_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70740   TIMER_OUTCFG13_OUTCFG53_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70741   TIMER_OUTCFG13_OUTCFG53_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70742   TIMER_OUTCFG13_OUTCFG53_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70743   TIMER_OUTCFG13_OUTCFG53_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70744   TIMER_OUTCFG13_OUTCFG53_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70745   TIMER_OUTCFG13_OUTCFG53_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70746   TIMER_OUTCFG13_OUTCFG53_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70747   TIMER_OUTCFG13_OUTCFG53_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70748   TIMER_OUTCFG13_OUTCFG53_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70749 } TIMER_OUTCFG13_OUTCFG53_Enum;
70750 
70751 /* ============================================  TIMER OUTCFG13 OUTCFG52 [0..5]  ============================================= */
70752 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG52                                                   */
70753   TIMER_OUTCFG13_OUTCFG52_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70754   TIMER_OUTCFG13_OUTCFG52_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70755   TIMER_OUTCFG13_OUTCFG52_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70756   TIMER_OUTCFG13_OUTCFG52_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70757   TIMER_OUTCFG13_OUTCFG52_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70758   TIMER_OUTCFG13_OUTCFG52_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70759   TIMER_OUTCFG13_OUTCFG52_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70760   TIMER_OUTCFG13_OUTCFG52_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70761   TIMER_OUTCFG13_OUTCFG52_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70762   TIMER_OUTCFG13_OUTCFG52_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70763   TIMER_OUTCFG13_OUTCFG52_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70764   TIMER_OUTCFG13_OUTCFG52_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70765   TIMER_OUTCFG13_OUTCFG52_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70766   TIMER_OUTCFG13_OUTCFG52_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70767   TIMER_OUTCFG13_OUTCFG52_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70768   TIMER_OUTCFG13_OUTCFG52_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70769   TIMER_OUTCFG13_OUTCFG52_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70770   TIMER_OUTCFG13_OUTCFG52_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70771   TIMER_OUTCFG13_OUTCFG52_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70772   TIMER_OUTCFG13_OUTCFG52_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70773   TIMER_OUTCFG13_OUTCFG52_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70774   TIMER_OUTCFG13_OUTCFG52_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70775   TIMER_OUTCFG13_OUTCFG52_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70776   TIMER_OUTCFG13_OUTCFG52_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70777   TIMER_OUTCFG13_OUTCFG52_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70778   TIMER_OUTCFG13_OUTCFG52_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70779   TIMER_OUTCFG13_OUTCFG52_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70780   TIMER_OUTCFG13_OUTCFG52_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70781   TIMER_OUTCFG13_OUTCFG52_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70782   TIMER_OUTCFG13_OUTCFG52_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70783   TIMER_OUTCFG13_OUTCFG52_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70784   TIMER_OUTCFG13_OUTCFG52_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70785   TIMER_OUTCFG13_OUTCFG52_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70786   TIMER_OUTCFG13_OUTCFG52_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70787   TIMER_OUTCFG13_OUTCFG52_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70788   TIMER_OUTCFG13_OUTCFG52_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70789   TIMER_OUTCFG13_OUTCFG52_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70790   TIMER_OUTCFG13_OUTCFG52_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70791   TIMER_OUTCFG13_OUTCFG52_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70792   TIMER_OUTCFG13_OUTCFG52_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70793   TIMER_OUTCFG13_OUTCFG52_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70794 } TIMER_OUTCFG13_OUTCFG52_Enum;
70795 
70796 /* =======================================================  OUTCFG14  ======================================================== */
70797 /* ===========================================  TIMER OUTCFG14 OUTCFG59 [24..29]  ============================================ */
70798 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG59                                                   */
70799   TIMER_OUTCFG14_OUTCFG59_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70800   TIMER_OUTCFG14_OUTCFG59_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70801   TIMER_OUTCFG14_OUTCFG59_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70802   TIMER_OUTCFG14_OUTCFG59_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70803   TIMER_OUTCFG14_OUTCFG59_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70804   TIMER_OUTCFG14_OUTCFG59_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70805   TIMER_OUTCFG14_OUTCFG59_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70806   TIMER_OUTCFG14_OUTCFG59_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70807   TIMER_OUTCFG14_OUTCFG59_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70808   TIMER_OUTCFG14_OUTCFG59_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70809   TIMER_OUTCFG14_OUTCFG59_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70810   TIMER_OUTCFG14_OUTCFG59_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70811   TIMER_OUTCFG14_OUTCFG59_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70812   TIMER_OUTCFG14_OUTCFG59_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70813   TIMER_OUTCFG14_OUTCFG59_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70814   TIMER_OUTCFG14_OUTCFG59_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70815   TIMER_OUTCFG14_OUTCFG59_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70816   TIMER_OUTCFG14_OUTCFG59_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70817   TIMER_OUTCFG14_OUTCFG59_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70818   TIMER_OUTCFG14_OUTCFG59_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70819   TIMER_OUTCFG14_OUTCFG59_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70820   TIMER_OUTCFG14_OUTCFG59_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70821   TIMER_OUTCFG14_OUTCFG59_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70822   TIMER_OUTCFG14_OUTCFG59_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70823   TIMER_OUTCFG14_OUTCFG59_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70824   TIMER_OUTCFG14_OUTCFG59_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70825   TIMER_OUTCFG14_OUTCFG59_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70826   TIMER_OUTCFG14_OUTCFG59_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70827   TIMER_OUTCFG14_OUTCFG59_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70828   TIMER_OUTCFG14_OUTCFG59_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70829   TIMER_OUTCFG14_OUTCFG59_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70830   TIMER_OUTCFG14_OUTCFG59_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70831   TIMER_OUTCFG14_OUTCFG59_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70832   TIMER_OUTCFG14_OUTCFG59_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70833   TIMER_OUTCFG14_OUTCFG59_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70834   TIMER_OUTCFG14_OUTCFG59_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70835   TIMER_OUTCFG14_OUTCFG59_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70836   TIMER_OUTCFG14_OUTCFG59_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70837   TIMER_OUTCFG14_OUTCFG59_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70838   TIMER_OUTCFG14_OUTCFG59_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70839   TIMER_OUTCFG14_OUTCFG59_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70840 } TIMER_OUTCFG14_OUTCFG59_Enum;
70841 
70842 /* ===========================================  TIMER OUTCFG14 OUTCFG58 [16..21]  ============================================ */
70843 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG58                                                   */
70844   TIMER_OUTCFG14_OUTCFG58_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70845   TIMER_OUTCFG14_OUTCFG58_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70846   TIMER_OUTCFG14_OUTCFG58_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70847   TIMER_OUTCFG14_OUTCFG58_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70848   TIMER_OUTCFG14_OUTCFG58_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70849   TIMER_OUTCFG14_OUTCFG58_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70850   TIMER_OUTCFG14_OUTCFG58_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70851   TIMER_OUTCFG14_OUTCFG58_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70852   TIMER_OUTCFG14_OUTCFG58_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70853   TIMER_OUTCFG14_OUTCFG58_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70854   TIMER_OUTCFG14_OUTCFG58_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70855   TIMER_OUTCFG14_OUTCFG58_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70856   TIMER_OUTCFG14_OUTCFG58_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70857   TIMER_OUTCFG14_OUTCFG58_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70858   TIMER_OUTCFG14_OUTCFG58_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70859   TIMER_OUTCFG14_OUTCFG58_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70860   TIMER_OUTCFG14_OUTCFG58_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70861   TIMER_OUTCFG14_OUTCFG58_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70862   TIMER_OUTCFG14_OUTCFG58_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70863   TIMER_OUTCFG14_OUTCFG58_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70864   TIMER_OUTCFG14_OUTCFG58_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70865   TIMER_OUTCFG14_OUTCFG58_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70866   TIMER_OUTCFG14_OUTCFG58_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70867   TIMER_OUTCFG14_OUTCFG58_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70868   TIMER_OUTCFG14_OUTCFG58_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70869   TIMER_OUTCFG14_OUTCFG58_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70870   TIMER_OUTCFG14_OUTCFG58_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70871   TIMER_OUTCFG14_OUTCFG58_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70872   TIMER_OUTCFG14_OUTCFG58_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70873   TIMER_OUTCFG14_OUTCFG58_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70874   TIMER_OUTCFG14_OUTCFG58_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70875   TIMER_OUTCFG14_OUTCFG58_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70876   TIMER_OUTCFG14_OUTCFG58_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70877   TIMER_OUTCFG14_OUTCFG58_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70878   TIMER_OUTCFG14_OUTCFG58_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70879   TIMER_OUTCFG14_OUTCFG58_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70880   TIMER_OUTCFG14_OUTCFG58_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70881   TIMER_OUTCFG14_OUTCFG58_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70882   TIMER_OUTCFG14_OUTCFG58_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70883   TIMER_OUTCFG14_OUTCFG58_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70884   TIMER_OUTCFG14_OUTCFG58_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70885 } TIMER_OUTCFG14_OUTCFG58_Enum;
70886 
70887 /* ============================================  TIMER OUTCFG14 OUTCFG57 [8..13]  ============================================ */
70888 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG57                                                   */
70889   TIMER_OUTCFG14_OUTCFG57_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70890   TIMER_OUTCFG14_OUTCFG57_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70891   TIMER_OUTCFG14_OUTCFG57_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70892   TIMER_OUTCFG14_OUTCFG57_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70893   TIMER_OUTCFG14_OUTCFG57_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70894   TIMER_OUTCFG14_OUTCFG57_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70895   TIMER_OUTCFG14_OUTCFG57_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70896   TIMER_OUTCFG14_OUTCFG57_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70897   TIMER_OUTCFG14_OUTCFG57_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70898   TIMER_OUTCFG14_OUTCFG57_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70899   TIMER_OUTCFG14_OUTCFG57_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70900   TIMER_OUTCFG14_OUTCFG57_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70901   TIMER_OUTCFG14_OUTCFG57_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70902   TIMER_OUTCFG14_OUTCFG57_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70903   TIMER_OUTCFG14_OUTCFG57_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70904   TIMER_OUTCFG14_OUTCFG57_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70905   TIMER_OUTCFG14_OUTCFG57_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70906   TIMER_OUTCFG14_OUTCFG57_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70907   TIMER_OUTCFG14_OUTCFG57_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70908   TIMER_OUTCFG14_OUTCFG57_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70909   TIMER_OUTCFG14_OUTCFG57_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70910   TIMER_OUTCFG14_OUTCFG57_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70911   TIMER_OUTCFG14_OUTCFG57_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70912   TIMER_OUTCFG14_OUTCFG57_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70913   TIMER_OUTCFG14_OUTCFG57_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70914   TIMER_OUTCFG14_OUTCFG57_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70915   TIMER_OUTCFG14_OUTCFG57_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70916   TIMER_OUTCFG14_OUTCFG57_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70917   TIMER_OUTCFG14_OUTCFG57_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70918   TIMER_OUTCFG14_OUTCFG57_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70919   TIMER_OUTCFG14_OUTCFG57_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70920   TIMER_OUTCFG14_OUTCFG57_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70921   TIMER_OUTCFG14_OUTCFG57_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70922   TIMER_OUTCFG14_OUTCFG57_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70923   TIMER_OUTCFG14_OUTCFG57_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70924   TIMER_OUTCFG14_OUTCFG57_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70925   TIMER_OUTCFG14_OUTCFG57_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70926   TIMER_OUTCFG14_OUTCFG57_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70927   TIMER_OUTCFG14_OUTCFG57_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70928   TIMER_OUTCFG14_OUTCFG57_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70929   TIMER_OUTCFG14_OUTCFG57_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70930 } TIMER_OUTCFG14_OUTCFG57_Enum;
70931 
70932 /* ============================================  TIMER OUTCFG14 OUTCFG56 [0..5]  ============================================= */
70933 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG56                                                   */
70934   TIMER_OUTCFG14_OUTCFG56_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70935   TIMER_OUTCFG14_OUTCFG56_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70936   TIMER_OUTCFG14_OUTCFG56_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70937   TIMER_OUTCFG14_OUTCFG56_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70938   TIMER_OUTCFG14_OUTCFG56_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70939   TIMER_OUTCFG14_OUTCFG56_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70940   TIMER_OUTCFG14_OUTCFG56_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70941   TIMER_OUTCFG14_OUTCFG56_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70942   TIMER_OUTCFG14_OUTCFG56_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70943   TIMER_OUTCFG14_OUTCFG56_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70944   TIMER_OUTCFG14_OUTCFG56_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70945   TIMER_OUTCFG14_OUTCFG56_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70946   TIMER_OUTCFG14_OUTCFG56_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70947   TIMER_OUTCFG14_OUTCFG56_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70948   TIMER_OUTCFG14_OUTCFG56_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70949   TIMER_OUTCFG14_OUTCFG56_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70950   TIMER_OUTCFG14_OUTCFG56_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70951   TIMER_OUTCFG14_OUTCFG56_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70952   TIMER_OUTCFG14_OUTCFG56_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70953   TIMER_OUTCFG14_OUTCFG56_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70954   TIMER_OUTCFG14_OUTCFG56_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70955   TIMER_OUTCFG14_OUTCFG56_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70956   TIMER_OUTCFG14_OUTCFG56_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70957   TIMER_OUTCFG14_OUTCFG56_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70958   TIMER_OUTCFG14_OUTCFG56_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70959   TIMER_OUTCFG14_OUTCFG56_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70960   TIMER_OUTCFG14_OUTCFG56_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70961   TIMER_OUTCFG14_OUTCFG56_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70962   TIMER_OUTCFG14_OUTCFG56_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70963   TIMER_OUTCFG14_OUTCFG56_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70964   TIMER_OUTCFG14_OUTCFG56_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70965   TIMER_OUTCFG14_OUTCFG56_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70966   TIMER_OUTCFG14_OUTCFG56_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70967   TIMER_OUTCFG14_OUTCFG56_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70968   TIMER_OUTCFG14_OUTCFG56_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70969   TIMER_OUTCFG14_OUTCFG56_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70970   TIMER_OUTCFG14_OUTCFG56_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70971   TIMER_OUTCFG14_OUTCFG56_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70972   TIMER_OUTCFG14_OUTCFG56_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70973   TIMER_OUTCFG14_OUTCFG56_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70974   TIMER_OUTCFG14_OUTCFG56_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
70975 } TIMER_OUTCFG14_OUTCFG56_Enum;
70976 
70977 /* =======================================================  OUTCFG15  ======================================================== */
70978 /* ===========================================  TIMER OUTCFG15 OUTCFG63 [24..29]  ============================================ */
70979 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG63                                                   */
70980   TIMER_OUTCFG15_OUTCFG63_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70981   TIMER_OUTCFG15_OUTCFG63_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70982   TIMER_OUTCFG15_OUTCFG63_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70983   TIMER_OUTCFG15_OUTCFG63_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70984   TIMER_OUTCFG15_OUTCFG63_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70985   TIMER_OUTCFG15_OUTCFG63_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70986   TIMER_OUTCFG15_OUTCFG63_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70987   TIMER_OUTCFG15_OUTCFG63_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70988   TIMER_OUTCFG15_OUTCFG63_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70989   TIMER_OUTCFG15_OUTCFG63_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70990   TIMER_OUTCFG15_OUTCFG63_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70991   TIMER_OUTCFG15_OUTCFG63_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70992   TIMER_OUTCFG15_OUTCFG63_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70993   TIMER_OUTCFG15_OUTCFG63_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70994   TIMER_OUTCFG15_OUTCFG63_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70995   TIMER_OUTCFG15_OUTCFG63_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70996   TIMER_OUTCFG15_OUTCFG63_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70997   TIMER_OUTCFG15_OUTCFG63_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70998   TIMER_OUTCFG15_OUTCFG63_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70999   TIMER_OUTCFG15_OUTCFG63_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71000   TIMER_OUTCFG15_OUTCFG63_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71001   TIMER_OUTCFG15_OUTCFG63_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71002   TIMER_OUTCFG15_OUTCFG63_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71003   TIMER_OUTCFG15_OUTCFG63_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71004   TIMER_OUTCFG15_OUTCFG63_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71005   TIMER_OUTCFG15_OUTCFG63_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71006   TIMER_OUTCFG15_OUTCFG63_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71007   TIMER_OUTCFG15_OUTCFG63_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71008   TIMER_OUTCFG15_OUTCFG63_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71009   TIMER_OUTCFG15_OUTCFG63_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71010   TIMER_OUTCFG15_OUTCFG63_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71011   TIMER_OUTCFG15_OUTCFG63_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71012   TIMER_OUTCFG15_OUTCFG63_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71013   TIMER_OUTCFG15_OUTCFG63_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71014   TIMER_OUTCFG15_OUTCFG63_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71015   TIMER_OUTCFG15_OUTCFG63_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71016   TIMER_OUTCFG15_OUTCFG63_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71017   TIMER_OUTCFG15_OUTCFG63_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71018   TIMER_OUTCFG15_OUTCFG63_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71019   TIMER_OUTCFG15_OUTCFG63_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71020   TIMER_OUTCFG15_OUTCFG63_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71021 } TIMER_OUTCFG15_OUTCFG63_Enum;
71022 
71023 /* ===========================================  TIMER OUTCFG15 OUTCFG62 [16..21]  ============================================ */
71024 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG62                                                   */
71025   TIMER_OUTCFG15_OUTCFG62_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71026   TIMER_OUTCFG15_OUTCFG62_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71027   TIMER_OUTCFG15_OUTCFG62_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71028   TIMER_OUTCFG15_OUTCFG62_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71029   TIMER_OUTCFG15_OUTCFG62_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71030   TIMER_OUTCFG15_OUTCFG62_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71031   TIMER_OUTCFG15_OUTCFG62_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71032   TIMER_OUTCFG15_OUTCFG62_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71033   TIMER_OUTCFG15_OUTCFG62_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71034   TIMER_OUTCFG15_OUTCFG62_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71035   TIMER_OUTCFG15_OUTCFG62_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71036   TIMER_OUTCFG15_OUTCFG62_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71037   TIMER_OUTCFG15_OUTCFG62_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71038   TIMER_OUTCFG15_OUTCFG62_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71039   TIMER_OUTCFG15_OUTCFG62_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71040   TIMER_OUTCFG15_OUTCFG62_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71041   TIMER_OUTCFG15_OUTCFG62_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71042   TIMER_OUTCFG15_OUTCFG62_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71043   TIMER_OUTCFG15_OUTCFG62_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71044   TIMER_OUTCFG15_OUTCFG62_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71045   TIMER_OUTCFG15_OUTCFG62_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71046   TIMER_OUTCFG15_OUTCFG62_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71047   TIMER_OUTCFG15_OUTCFG62_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71048   TIMER_OUTCFG15_OUTCFG62_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71049   TIMER_OUTCFG15_OUTCFG62_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71050   TIMER_OUTCFG15_OUTCFG62_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71051   TIMER_OUTCFG15_OUTCFG62_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71052   TIMER_OUTCFG15_OUTCFG62_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71053   TIMER_OUTCFG15_OUTCFG62_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71054   TIMER_OUTCFG15_OUTCFG62_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71055   TIMER_OUTCFG15_OUTCFG62_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71056   TIMER_OUTCFG15_OUTCFG62_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71057   TIMER_OUTCFG15_OUTCFG62_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71058   TIMER_OUTCFG15_OUTCFG62_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71059   TIMER_OUTCFG15_OUTCFG62_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71060   TIMER_OUTCFG15_OUTCFG62_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71061   TIMER_OUTCFG15_OUTCFG62_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71062   TIMER_OUTCFG15_OUTCFG62_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71063   TIMER_OUTCFG15_OUTCFG62_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71064   TIMER_OUTCFG15_OUTCFG62_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71065   TIMER_OUTCFG15_OUTCFG62_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71066 } TIMER_OUTCFG15_OUTCFG62_Enum;
71067 
71068 /* ============================================  TIMER OUTCFG15 OUTCFG61 [8..13]  ============================================ */
71069 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG61                                                   */
71070   TIMER_OUTCFG15_OUTCFG61_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71071   TIMER_OUTCFG15_OUTCFG61_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71072   TIMER_OUTCFG15_OUTCFG61_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71073   TIMER_OUTCFG15_OUTCFG61_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71074   TIMER_OUTCFG15_OUTCFG61_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71075   TIMER_OUTCFG15_OUTCFG61_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71076   TIMER_OUTCFG15_OUTCFG61_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71077   TIMER_OUTCFG15_OUTCFG61_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71078   TIMER_OUTCFG15_OUTCFG61_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71079   TIMER_OUTCFG15_OUTCFG61_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71080   TIMER_OUTCFG15_OUTCFG61_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71081   TIMER_OUTCFG15_OUTCFG61_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71082   TIMER_OUTCFG15_OUTCFG61_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71083   TIMER_OUTCFG15_OUTCFG61_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71084   TIMER_OUTCFG15_OUTCFG61_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71085   TIMER_OUTCFG15_OUTCFG61_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71086   TIMER_OUTCFG15_OUTCFG61_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71087   TIMER_OUTCFG15_OUTCFG61_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71088   TIMER_OUTCFG15_OUTCFG61_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71089   TIMER_OUTCFG15_OUTCFG61_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71090   TIMER_OUTCFG15_OUTCFG61_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71091   TIMER_OUTCFG15_OUTCFG61_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71092   TIMER_OUTCFG15_OUTCFG61_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71093   TIMER_OUTCFG15_OUTCFG61_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71094   TIMER_OUTCFG15_OUTCFG61_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71095   TIMER_OUTCFG15_OUTCFG61_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71096   TIMER_OUTCFG15_OUTCFG61_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71097   TIMER_OUTCFG15_OUTCFG61_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71098   TIMER_OUTCFG15_OUTCFG61_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71099   TIMER_OUTCFG15_OUTCFG61_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71100   TIMER_OUTCFG15_OUTCFG61_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71101   TIMER_OUTCFG15_OUTCFG61_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71102   TIMER_OUTCFG15_OUTCFG61_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71103   TIMER_OUTCFG15_OUTCFG61_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71104   TIMER_OUTCFG15_OUTCFG61_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71105   TIMER_OUTCFG15_OUTCFG61_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71106   TIMER_OUTCFG15_OUTCFG61_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71107   TIMER_OUTCFG15_OUTCFG61_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71108   TIMER_OUTCFG15_OUTCFG61_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71109   TIMER_OUTCFG15_OUTCFG61_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71110   TIMER_OUTCFG15_OUTCFG61_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71111 } TIMER_OUTCFG15_OUTCFG61_Enum;
71112 
71113 /* ============================================  TIMER OUTCFG15 OUTCFG60 [0..5]  ============================================= */
71114 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG60                                                   */
71115   TIMER_OUTCFG15_OUTCFG60_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71116   TIMER_OUTCFG15_OUTCFG60_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71117   TIMER_OUTCFG15_OUTCFG60_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71118   TIMER_OUTCFG15_OUTCFG60_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71119   TIMER_OUTCFG15_OUTCFG60_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71120   TIMER_OUTCFG15_OUTCFG60_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71121   TIMER_OUTCFG15_OUTCFG60_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71122   TIMER_OUTCFG15_OUTCFG60_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71123   TIMER_OUTCFG15_OUTCFG60_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71124   TIMER_OUTCFG15_OUTCFG60_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71125   TIMER_OUTCFG15_OUTCFG60_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71126   TIMER_OUTCFG15_OUTCFG60_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71127   TIMER_OUTCFG15_OUTCFG60_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71128   TIMER_OUTCFG15_OUTCFG60_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71129   TIMER_OUTCFG15_OUTCFG60_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71130   TIMER_OUTCFG15_OUTCFG60_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71131   TIMER_OUTCFG15_OUTCFG60_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71132   TIMER_OUTCFG15_OUTCFG60_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71133   TIMER_OUTCFG15_OUTCFG60_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71134   TIMER_OUTCFG15_OUTCFG60_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71135   TIMER_OUTCFG15_OUTCFG60_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71136   TIMER_OUTCFG15_OUTCFG60_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71137   TIMER_OUTCFG15_OUTCFG60_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71138   TIMER_OUTCFG15_OUTCFG60_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71139   TIMER_OUTCFG15_OUTCFG60_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71140   TIMER_OUTCFG15_OUTCFG60_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71141   TIMER_OUTCFG15_OUTCFG60_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71142   TIMER_OUTCFG15_OUTCFG60_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71143   TIMER_OUTCFG15_OUTCFG60_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71144   TIMER_OUTCFG15_OUTCFG60_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71145   TIMER_OUTCFG15_OUTCFG60_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71146   TIMER_OUTCFG15_OUTCFG60_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71147   TIMER_OUTCFG15_OUTCFG60_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71148   TIMER_OUTCFG15_OUTCFG60_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71149   TIMER_OUTCFG15_OUTCFG60_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71150   TIMER_OUTCFG15_OUTCFG60_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71151   TIMER_OUTCFG15_OUTCFG60_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71152   TIMER_OUTCFG15_OUTCFG60_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71153   TIMER_OUTCFG15_OUTCFG60_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71154   TIMER_OUTCFG15_OUTCFG60_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71155   TIMER_OUTCFG15_OUTCFG60_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71156 } TIMER_OUTCFG15_OUTCFG60_Enum;
71157 
71158 /* =======================================================  OUTCFG16  ======================================================== */
71159 /* ===========================================  TIMER OUTCFG16 OUTCFG67 [24..29]  ============================================ */
71160 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG67                                                   */
71161   TIMER_OUTCFG16_OUTCFG67_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71162   TIMER_OUTCFG16_OUTCFG67_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71163   TIMER_OUTCFG16_OUTCFG67_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71164   TIMER_OUTCFG16_OUTCFG67_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71165   TIMER_OUTCFG16_OUTCFG67_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71166   TIMER_OUTCFG16_OUTCFG67_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71167   TIMER_OUTCFG16_OUTCFG67_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71168   TIMER_OUTCFG16_OUTCFG67_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71169   TIMER_OUTCFG16_OUTCFG67_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71170   TIMER_OUTCFG16_OUTCFG67_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71171   TIMER_OUTCFG16_OUTCFG67_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71172   TIMER_OUTCFG16_OUTCFG67_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71173   TIMER_OUTCFG16_OUTCFG67_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71174   TIMER_OUTCFG16_OUTCFG67_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71175   TIMER_OUTCFG16_OUTCFG67_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71176   TIMER_OUTCFG16_OUTCFG67_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71177   TIMER_OUTCFG16_OUTCFG67_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71178   TIMER_OUTCFG16_OUTCFG67_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71179   TIMER_OUTCFG16_OUTCFG67_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71180   TIMER_OUTCFG16_OUTCFG67_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71181   TIMER_OUTCFG16_OUTCFG67_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71182   TIMER_OUTCFG16_OUTCFG67_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71183   TIMER_OUTCFG16_OUTCFG67_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71184   TIMER_OUTCFG16_OUTCFG67_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71185   TIMER_OUTCFG16_OUTCFG67_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71186   TIMER_OUTCFG16_OUTCFG67_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71187   TIMER_OUTCFG16_OUTCFG67_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71188   TIMER_OUTCFG16_OUTCFG67_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71189   TIMER_OUTCFG16_OUTCFG67_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71190   TIMER_OUTCFG16_OUTCFG67_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71191   TIMER_OUTCFG16_OUTCFG67_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71192   TIMER_OUTCFG16_OUTCFG67_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71193   TIMER_OUTCFG16_OUTCFG67_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71194   TIMER_OUTCFG16_OUTCFG67_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71195   TIMER_OUTCFG16_OUTCFG67_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71196   TIMER_OUTCFG16_OUTCFG67_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71197   TIMER_OUTCFG16_OUTCFG67_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71198   TIMER_OUTCFG16_OUTCFG67_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71199   TIMER_OUTCFG16_OUTCFG67_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71200   TIMER_OUTCFG16_OUTCFG67_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71201   TIMER_OUTCFG16_OUTCFG67_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71202 } TIMER_OUTCFG16_OUTCFG67_Enum;
71203 
71204 /* ===========================================  TIMER OUTCFG16 OUTCFG66 [16..21]  ============================================ */
71205 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG66                                                   */
71206   TIMER_OUTCFG16_OUTCFG66_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71207   TIMER_OUTCFG16_OUTCFG66_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71208   TIMER_OUTCFG16_OUTCFG66_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71209   TIMER_OUTCFG16_OUTCFG66_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71210   TIMER_OUTCFG16_OUTCFG66_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71211   TIMER_OUTCFG16_OUTCFG66_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71212   TIMER_OUTCFG16_OUTCFG66_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71213   TIMER_OUTCFG16_OUTCFG66_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71214   TIMER_OUTCFG16_OUTCFG66_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71215   TIMER_OUTCFG16_OUTCFG66_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71216   TIMER_OUTCFG16_OUTCFG66_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71217   TIMER_OUTCFG16_OUTCFG66_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71218   TIMER_OUTCFG16_OUTCFG66_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71219   TIMER_OUTCFG16_OUTCFG66_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71220   TIMER_OUTCFG16_OUTCFG66_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71221   TIMER_OUTCFG16_OUTCFG66_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71222   TIMER_OUTCFG16_OUTCFG66_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71223   TIMER_OUTCFG16_OUTCFG66_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71224   TIMER_OUTCFG16_OUTCFG66_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71225   TIMER_OUTCFG16_OUTCFG66_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71226   TIMER_OUTCFG16_OUTCFG66_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71227   TIMER_OUTCFG16_OUTCFG66_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71228   TIMER_OUTCFG16_OUTCFG66_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71229   TIMER_OUTCFG16_OUTCFG66_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71230   TIMER_OUTCFG16_OUTCFG66_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71231   TIMER_OUTCFG16_OUTCFG66_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71232   TIMER_OUTCFG16_OUTCFG66_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71233   TIMER_OUTCFG16_OUTCFG66_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71234   TIMER_OUTCFG16_OUTCFG66_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71235   TIMER_OUTCFG16_OUTCFG66_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71236   TIMER_OUTCFG16_OUTCFG66_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71237   TIMER_OUTCFG16_OUTCFG66_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71238   TIMER_OUTCFG16_OUTCFG66_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71239   TIMER_OUTCFG16_OUTCFG66_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71240   TIMER_OUTCFG16_OUTCFG66_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71241   TIMER_OUTCFG16_OUTCFG66_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71242   TIMER_OUTCFG16_OUTCFG66_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71243   TIMER_OUTCFG16_OUTCFG66_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71244   TIMER_OUTCFG16_OUTCFG66_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71245   TIMER_OUTCFG16_OUTCFG66_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71246   TIMER_OUTCFG16_OUTCFG66_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71247 } TIMER_OUTCFG16_OUTCFG66_Enum;
71248 
71249 /* ============================================  TIMER OUTCFG16 OUTCFG65 [8..13]  ============================================ */
71250 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG65                                                   */
71251   TIMER_OUTCFG16_OUTCFG65_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71252   TIMER_OUTCFG16_OUTCFG65_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71253   TIMER_OUTCFG16_OUTCFG65_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71254   TIMER_OUTCFG16_OUTCFG65_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71255   TIMER_OUTCFG16_OUTCFG65_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71256   TIMER_OUTCFG16_OUTCFG65_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71257   TIMER_OUTCFG16_OUTCFG65_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71258   TIMER_OUTCFG16_OUTCFG65_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71259   TIMER_OUTCFG16_OUTCFG65_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71260   TIMER_OUTCFG16_OUTCFG65_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71261   TIMER_OUTCFG16_OUTCFG65_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71262   TIMER_OUTCFG16_OUTCFG65_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71263   TIMER_OUTCFG16_OUTCFG65_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71264   TIMER_OUTCFG16_OUTCFG65_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71265   TIMER_OUTCFG16_OUTCFG65_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71266   TIMER_OUTCFG16_OUTCFG65_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71267   TIMER_OUTCFG16_OUTCFG65_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71268   TIMER_OUTCFG16_OUTCFG65_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71269   TIMER_OUTCFG16_OUTCFG65_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71270   TIMER_OUTCFG16_OUTCFG65_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71271   TIMER_OUTCFG16_OUTCFG65_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71272   TIMER_OUTCFG16_OUTCFG65_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71273   TIMER_OUTCFG16_OUTCFG65_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71274   TIMER_OUTCFG16_OUTCFG65_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71275   TIMER_OUTCFG16_OUTCFG65_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71276   TIMER_OUTCFG16_OUTCFG65_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71277   TIMER_OUTCFG16_OUTCFG65_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71278   TIMER_OUTCFG16_OUTCFG65_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71279   TIMER_OUTCFG16_OUTCFG65_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71280   TIMER_OUTCFG16_OUTCFG65_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71281   TIMER_OUTCFG16_OUTCFG65_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71282   TIMER_OUTCFG16_OUTCFG65_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71283   TIMER_OUTCFG16_OUTCFG65_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71284   TIMER_OUTCFG16_OUTCFG65_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71285   TIMER_OUTCFG16_OUTCFG65_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71286   TIMER_OUTCFG16_OUTCFG65_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71287   TIMER_OUTCFG16_OUTCFG65_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71288   TIMER_OUTCFG16_OUTCFG65_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71289   TIMER_OUTCFG16_OUTCFG65_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71290   TIMER_OUTCFG16_OUTCFG65_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71291   TIMER_OUTCFG16_OUTCFG65_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71292 } TIMER_OUTCFG16_OUTCFG65_Enum;
71293 
71294 /* ============================================  TIMER OUTCFG16 OUTCFG64 [0..5]  ============================================= */
71295 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG64                                                   */
71296   TIMER_OUTCFG16_OUTCFG64_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71297   TIMER_OUTCFG16_OUTCFG64_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71298   TIMER_OUTCFG16_OUTCFG64_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71299   TIMER_OUTCFG16_OUTCFG64_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71300   TIMER_OUTCFG16_OUTCFG64_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71301   TIMER_OUTCFG16_OUTCFG64_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71302   TIMER_OUTCFG16_OUTCFG64_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71303   TIMER_OUTCFG16_OUTCFG64_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71304   TIMER_OUTCFG16_OUTCFG64_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71305   TIMER_OUTCFG16_OUTCFG64_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71306   TIMER_OUTCFG16_OUTCFG64_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71307   TIMER_OUTCFG16_OUTCFG64_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71308   TIMER_OUTCFG16_OUTCFG64_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71309   TIMER_OUTCFG16_OUTCFG64_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71310   TIMER_OUTCFG16_OUTCFG64_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71311   TIMER_OUTCFG16_OUTCFG64_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71312   TIMER_OUTCFG16_OUTCFG64_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71313   TIMER_OUTCFG16_OUTCFG64_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71314   TIMER_OUTCFG16_OUTCFG64_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71315   TIMER_OUTCFG16_OUTCFG64_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71316   TIMER_OUTCFG16_OUTCFG64_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71317   TIMER_OUTCFG16_OUTCFG64_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71318   TIMER_OUTCFG16_OUTCFG64_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71319   TIMER_OUTCFG16_OUTCFG64_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71320   TIMER_OUTCFG16_OUTCFG64_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71321   TIMER_OUTCFG16_OUTCFG64_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71322   TIMER_OUTCFG16_OUTCFG64_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71323   TIMER_OUTCFG16_OUTCFG64_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71324   TIMER_OUTCFG16_OUTCFG64_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71325   TIMER_OUTCFG16_OUTCFG64_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71326   TIMER_OUTCFG16_OUTCFG64_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71327   TIMER_OUTCFG16_OUTCFG64_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71328   TIMER_OUTCFG16_OUTCFG64_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71329   TIMER_OUTCFG16_OUTCFG64_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71330   TIMER_OUTCFG16_OUTCFG64_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71331   TIMER_OUTCFG16_OUTCFG64_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71332   TIMER_OUTCFG16_OUTCFG64_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71333   TIMER_OUTCFG16_OUTCFG64_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71334   TIMER_OUTCFG16_OUTCFG64_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71335   TIMER_OUTCFG16_OUTCFG64_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71336   TIMER_OUTCFG16_OUTCFG64_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71337 } TIMER_OUTCFG16_OUTCFG64_Enum;
71338 
71339 /* =======================================================  OUTCFG17  ======================================================== */
71340 /* ===========================================  TIMER OUTCFG17 OUTCFG71 [24..29]  ============================================ */
71341 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG71                                                   */
71342   TIMER_OUTCFG17_OUTCFG71_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71343   TIMER_OUTCFG17_OUTCFG71_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71344   TIMER_OUTCFG17_OUTCFG71_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71345   TIMER_OUTCFG17_OUTCFG71_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71346   TIMER_OUTCFG17_OUTCFG71_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71347   TIMER_OUTCFG17_OUTCFG71_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71348   TIMER_OUTCFG17_OUTCFG71_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71349   TIMER_OUTCFG17_OUTCFG71_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71350   TIMER_OUTCFG17_OUTCFG71_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71351   TIMER_OUTCFG17_OUTCFG71_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71352   TIMER_OUTCFG17_OUTCFG71_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71353   TIMER_OUTCFG17_OUTCFG71_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71354   TIMER_OUTCFG17_OUTCFG71_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71355   TIMER_OUTCFG17_OUTCFG71_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71356   TIMER_OUTCFG17_OUTCFG71_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71357   TIMER_OUTCFG17_OUTCFG71_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71358   TIMER_OUTCFG17_OUTCFG71_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71359   TIMER_OUTCFG17_OUTCFG71_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71360   TIMER_OUTCFG17_OUTCFG71_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71361   TIMER_OUTCFG17_OUTCFG71_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71362   TIMER_OUTCFG17_OUTCFG71_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71363   TIMER_OUTCFG17_OUTCFG71_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71364   TIMER_OUTCFG17_OUTCFG71_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71365   TIMER_OUTCFG17_OUTCFG71_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71366   TIMER_OUTCFG17_OUTCFG71_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71367   TIMER_OUTCFG17_OUTCFG71_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71368   TIMER_OUTCFG17_OUTCFG71_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71369   TIMER_OUTCFG17_OUTCFG71_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71370   TIMER_OUTCFG17_OUTCFG71_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71371   TIMER_OUTCFG17_OUTCFG71_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71372   TIMER_OUTCFG17_OUTCFG71_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71373   TIMER_OUTCFG17_OUTCFG71_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71374   TIMER_OUTCFG17_OUTCFG71_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71375   TIMER_OUTCFG17_OUTCFG71_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71376   TIMER_OUTCFG17_OUTCFG71_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71377   TIMER_OUTCFG17_OUTCFG71_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71378   TIMER_OUTCFG17_OUTCFG71_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71379   TIMER_OUTCFG17_OUTCFG71_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71380   TIMER_OUTCFG17_OUTCFG71_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71381   TIMER_OUTCFG17_OUTCFG71_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71382   TIMER_OUTCFG17_OUTCFG71_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71383 } TIMER_OUTCFG17_OUTCFG71_Enum;
71384 
71385 /* ===========================================  TIMER OUTCFG17 OUTCFG70 [16..21]  ============================================ */
71386 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG70                                                   */
71387   TIMER_OUTCFG17_OUTCFG70_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71388   TIMER_OUTCFG17_OUTCFG70_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71389   TIMER_OUTCFG17_OUTCFG70_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71390   TIMER_OUTCFG17_OUTCFG70_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71391   TIMER_OUTCFG17_OUTCFG70_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71392   TIMER_OUTCFG17_OUTCFG70_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71393   TIMER_OUTCFG17_OUTCFG70_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71394   TIMER_OUTCFG17_OUTCFG70_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71395   TIMER_OUTCFG17_OUTCFG70_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71396   TIMER_OUTCFG17_OUTCFG70_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71397   TIMER_OUTCFG17_OUTCFG70_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71398   TIMER_OUTCFG17_OUTCFG70_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71399   TIMER_OUTCFG17_OUTCFG70_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71400   TIMER_OUTCFG17_OUTCFG70_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71401   TIMER_OUTCFG17_OUTCFG70_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71402   TIMER_OUTCFG17_OUTCFG70_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71403   TIMER_OUTCFG17_OUTCFG70_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71404   TIMER_OUTCFG17_OUTCFG70_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71405   TIMER_OUTCFG17_OUTCFG70_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71406   TIMER_OUTCFG17_OUTCFG70_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71407   TIMER_OUTCFG17_OUTCFG70_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71408   TIMER_OUTCFG17_OUTCFG70_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71409   TIMER_OUTCFG17_OUTCFG70_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71410   TIMER_OUTCFG17_OUTCFG70_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71411   TIMER_OUTCFG17_OUTCFG70_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71412   TIMER_OUTCFG17_OUTCFG70_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71413   TIMER_OUTCFG17_OUTCFG70_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71414   TIMER_OUTCFG17_OUTCFG70_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71415   TIMER_OUTCFG17_OUTCFG70_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71416   TIMER_OUTCFG17_OUTCFG70_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71417   TIMER_OUTCFG17_OUTCFG70_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71418   TIMER_OUTCFG17_OUTCFG70_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71419   TIMER_OUTCFG17_OUTCFG70_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71420   TIMER_OUTCFG17_OUTCFG70_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71421   TIMER_OUTCFG17_OUTCFG70_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71422   TIMER_OUTCFG17_OUTCFG70_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71423   TIMER_OUTCFG17_OUTCFG70_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71424   TIMER_OUTCFG17_OUTCFG70_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71425   TIMER_OUTCFG17_OUTCFG70_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71426   TIMER_OUTCFG17_OUTCFG70_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71427   TIMER_OUTCFG17_OUTCFG70_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71428 } TIMER_OUTCFG17_OUTCFG70_Enum;
71429 
71430 /* ============================================  TIMER OUTCFG17 OUTCFG69 [8..13]  ============================================ */
71431 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG69                                                   */
71432   TIMER_OUTCFG17_OUTCFG69_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71433   TIMER_OUTCFG17_OUTCFG69_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71434   TIMER_OUTCFG17_OUTCFG69_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71435   TIMER_OUTCFG17_OUTCFG69_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71436   TIMER_OUTCFG17_OUTCFG69_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71437   TIMER_OUTCFG17_OUTCFG69_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71438   TIMER_OUTCFG17_OUTCFG69_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71439   TIMER_OUTCFG17_OUTCFG69_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71440   TIMER_OUTCFG17_OUTCFG69_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71441   TIMER_OUTCFG17_OUTCFG69_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71442   TIMER_OUTCFG17_OUTCFG69_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71443   TIMER_OUTCFG17_OUTCFG69_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71444   TIMER_OUTCFG17_OUTCFG69_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71445   TIMER_OUTCFG17_OUTCFG69_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71446   TIMER_OUTCFG17_OUTCFG69_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71447   TIMER_OUTCFG17_OUTCFG69_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71448   TIMER_OUTCFG17_OUTCFG69_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71449   TIMER_OUTCFG17_OUTCFG69_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71450   TIMER_OUTCFG17_OUTCFG69_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71451   TIMER_OUTCFG17_OUTCFG69_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71452   TIMER_OUTCFG17_OUTCFG69_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71453   TIMER_OUTCFG17_OUTCFG69_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71454   TIMER_OUTCFG17_OUTCFG69_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71455   TIMER_OUTCFG17_OUTCFG69_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71456   TIMER_OUTCFG17_OUTCFG69_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71457   TIMER_OUTCFG17_OUTCFG69_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71458   TIMER_OUTCFG17_OUTCFG69_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71459   TIMER_OUTCFG17_OUTCFG69_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71460   TIMER_OUTCFG17_OUTCFG69_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71461   TIMER_OUTCFG17_OUTCFG69_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71462   TIMER_OUTCFG17_OUTCFG69_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71463   TIMER_OUTCFG17_OUTCFG69_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71464   TIMER_OUTCFG17_OUTCFG69_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71465   TIMER_OUTCFG17_OUTCFG69_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71466   TIMER_OUTCFG17_OUTCFG69_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71467   TIMER_OUTCFG17_OUTCFG69_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71468   TIMER_OUTCFG17_OUTCFG69_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71469   TIMER_OUTCFG17_OUTCFG69_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71470   TIMER_OUTCFG17_OUTCFG69_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71471   TIMER_OUTCFG17_OUTCFG69_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71472   TIMER_OUTCFG17_OUTCFG69_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71473 } TIMER_OUTCFG17_OUTCFG69_Enum;
71474 
71475 /* ============================================  TIMER OUTCFG17 OUTCFG68 [0..5]  ============================================= */
71476 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG68                                                   */
71477   TIMER_OUTCFG17_OUTCFG68_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71478   TIMER_OUTCFG17_OUTCFG68_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71479   TIMER_OUTCFG17_OUTCFG68_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71480   TIMER_OUTCFG17_OUTCFG68_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71481   TIMER_OUTCFG17_OUTCFG68_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71482   TIMER_OUTCFG17_OUTCFG68_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71483   TIMER_OUTCFG17_OUTCFG68_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71484   TIMER_OUTCFG17_OUTCFG68_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71485   TIMER_OUTCFG17_OUTCFG68_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71486   TIMER_OUTCFG17_OUTCFG68_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71487   TIMER_OUTCFG17_OUTCFG68_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71488   TIMER_OUTCFG17_OUTCFG68_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71489   TIMER_OUTCFG17_OUTCFG68_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71490   TIMER_OUTCFG17_OUTCFG68_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71491   TIMER_OUTCFG17_OUTCFG68_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71492   TIMER_OUTCFG17_OUTCFG68_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71493   TIMER_OUTCFG17_OUTCFG68_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71494   TIMER_OUTCFG17_OUTCFG68_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71495   TIMER_OUTCFG17_OUTCFG68_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71496   TIMER_OUTCFG17_OUTCFG68_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71497   TIMER_OUTCFG17_OUTCFG68_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71498   TIMER_OUTCFG17_OUTCFG68_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71499   TIMER_OUTCFG17_OUTCFG68_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71500   TIMER_OUTCFG17_OUTCFG68_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71501   TIMER_OUTCFG17_OUTCFG68_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71502   TIMER_OUTCFG17_OUTCFG68_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71503   TIMER_OUTCFG17_OUTCFG68_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71504   TIMER_OUTCFG17_OUTCFG68_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71505   TIMER_OUTCFG17_OUTCFG68_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71506   TIMER_OUTCFG17_OUTCFG68_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71507   TIMER_OUTCFG17_OUTCFG68_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71508   TIMER_OUTCFG17_OUTCFG68_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71509   TIMER_OUTCFG17_OUTCFG68_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71510   TIMER_OUTCFG17_OUTCFG68_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71511   TIMER_OUTCFG17_OUTCFG68_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71512   TIMER_OUTCFG17_OUTCFG68_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71513   TIMER_OUTCFG17_OUTCFG68_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71514   TIMER_OUTCFG17_OUTCFG68_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71515   TIMER_OUTCFG17_OUTCFG68_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71516   TIMER_OUTCFG17_OUTCFG68_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71517   TIMER_OUTCFG17_OUTCFG68_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71518 } TIMER_OUTCFG17_OUTCFG68_Enum;
71519 
71520 /* =======================================================  OUTCFG18  ======================================================== */
71521 /* ===========================================  TIMER OUTCFG18 OUTCFG75 [24..29]  ============================================ */
71522 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG75                                                   */
71523   TIMER_OUTCFG18_OUTCFG75_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71524   TIMER_OUTCFG18_OUTCFG75_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71525   TIMER_OUTCFG18_OUTCFG75_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71526   TIMER_OUTCFG18_OUTCFG75_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71527   TIMER_OUTCFG18_OUTCFG75_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71528   TIMER_OUTCFG18_OUTCFG75_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71529   TIMER_OUTCFG18_OUTCFG75_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71530   TIMER_OUTCFG18_OUTCFG75_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71531   TIMER_OUTCFG18_OUTCFG75_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71532   TIMER_OUTCFG18_OUTCFG75_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71533   TIMER_OUTCFG18_OUTCFG75_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71534   TIMER_OUTCFG18_OUTCFG75_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71535   TIMER_OUTCFG18_OUTCFG75_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71536   TIMER_OUTCFG18_OUTCFG75_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71537   TIMER_OUTCFG18_OUTCFG75_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71538   TIMER_OUTCFG18_OUTCFG75_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71539   TIMER_OUTCFG18_OUTCFG75_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71540   TIMER_OUTCFG18_OUTCFG75_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71541   TIMER_OUTCFG18_OUTCFG75_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71542   TIMER_OUTCFG18_OUTCFG75_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71543   TIMER_OUTCFG18_OUTCFG75_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71544   TIMER_OUTCFG18_OUTCFG75_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71545   TIMER_OUTCFG18_OUTCFG75_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71546   TIMER_OUTCFG18_OUTCFG75_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71547   TIMER_OUTCFG18_OUTCFG75_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71548   TIMER_OUTCFG18_OUTCFG75_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71549   TIMER_OUTCFG18_OUTCFG75_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71550   TIMER_OUTCFG18_OUTCFG75_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71551   TIMER_OUTCFG18_OUTCFG75_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71552   TIMER_OUTCFG18_OUTCFG75_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71553   TIMER_OUTCFG18_OUTCFG75_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71554   TIMER_OUTCFG18_OUTCFG75_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71555   TIMER_OUTCFG18_OUTCFG75_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71556   TIMER_OUTCFG18_OUTCFG75_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71557   TIMER_OUTCFG18_OUTCFG75_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71558   TIMER_OUTCFG18_OUTCFG75_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71559   TIMER_OUTCFG18_OUTCFG75_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71560   TIMER_OUTCFG18_OUTCFG75_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71561   TIMER_OUTCFG18_OUTCFG75_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71562   TIMER_OUTCFG18_OUTCFG75_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71563   TIMER_OUTCFG18_OUTCFG75_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71564 } TIMER_OUTCFG18_OUTCFG75_Enum;
71565 
71566 /* ===========================================  TIMER OUTCFG18 OUTCFG74 [16..21]  ============================================ */
71567 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG74                                                   */
71568   TIMER_OUTCFG18_OUTCFG74_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71569   TIMER_OUTCFG18_OUTCFG74_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71570   TIMER_OUTCFG18_OUTCFG74_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71571   TIMER_OUTCFG18_OUTCFG74_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71572   TIMER_OUTCFG18_OUTCFG74_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71573   TIMER_OUTCFG18_OUTCFG74_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71574   TIMER_OUTCFG18_OUTCFG74_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71575   TIMER_OUTCFG18_OUTCFG74_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71576   TIMER_OUTCFG18_OUTCFG74_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71577   TIMER_OUTCFG18_OUTCFG74_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71578   TIMER_OUTCFG18_OUTCFG74_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71579   TIMER_OUTCFG18_OUTCFG74_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71580   TIMER_OUTCFG18_OUTCFG74_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71581   TIMER_OUTCFG18_OUTCFG74_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71582   TIMER_OUTCFG18_OUTCFG74_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71583   TIMER_OUTCFG18_OUTCFG74_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71584   TIMER_OUTCFG18_OUTCFG74_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71585   TIMER_OUTCFG18_OUTCFG74_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71586   TIMER_OUTCFG18_OUTCFG74_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71587   TIMER_OUTCFG18_OUTCFG74_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71588   TIMER_OUTCFG18_OUTCFG74_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71589   TIMER_OUTCFG18_OUTCFG74_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71590   TIMER_OUTCFG18_OUTCFG74_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71591   TIMER_OUTCFG18_OUTCFG74_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71592   TIMER_OUTCFG18_OUTCFG74_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71593   TIMER_OUTCFG18_OUTCFG74_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71594   TIMER_OUTCFG18_OUTCFG74_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71595   TIMER_OUTCFG18_OUTCFG74_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71596   TIMER_OUTCFG18_OUTCFG74_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71597   TIMER_OUTCFG18_OUTCFG74_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71598   TIMER_OUTCFG18_OUTCFG74_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71599   TIMER_OUTCFG18_OUTCFG74_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71600   TIMER_OUTCFG18_OUTCFG74_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71601   TIMER_OUTCFG18_OUTCFG74_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71602   TIMER_OUTCFG18_OUTCFG74_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71603   TIMER_OUTCFG18_OUTCFG74_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71604   TIMER_OUTCFG18_OUTCFG74_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71605   TIMER_OUTCFG18_OUTCFG74_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71606   TIMER_OUTCFG18_OUTCFG74_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71607   TIMER_OUTCFG18_OUTCFG74_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71608   TIMER_OUTCFG18_OUTCFG74_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71609 } TIMER_OUTCFG18_OUTCFG74_Enum;
71610 
71611 /* ============================================  TIMER OUTCFG18 OUTCFG73 [8..13]  ============================================ */
71612 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG73                                                   */
71613   TIMER_OUTCFG18_OUTCFG73_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71614   TIMER_OUTCFG18_OUTCFG73_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71615   TIMER_OUTCFG18_OUTCFG73_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71616   TIMER_OUTCFG18_OUTCFG73_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71617   TIMER_OUTCFG18_OUTCFG73_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71618   TIMER_OUTCFG18_OUTCFG73_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71619   TIMER_OUTCFG18_OUTCFG73_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71620   TIMER_OUTCFG18_OUTCFG73_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71621   TIMER_OUTCFG18_OUTCFG73_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71622   TIMER_OUTCFG18_OUTCFG73_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71623   TIMER_OUTCFG18_OUTCFG73_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71624   TIMER_OUTCFG18_OUTCFG73_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71625   TIMER_OUTCFG18_OUTCFG73_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71626   TIMER_OUTCFG18_OUTCFG73_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71627   TIMER_OUTCFG18_OUTCFG73_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71628   TIMER_OUTCFG18_OUTCFG73_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71629   TIMER_OUTCFG18_OUTCFG73_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71630   TIMER_OUTCFG18_OUTCFG73_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71631   TIMER_OUTCFG18_OUTCFG73_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71632   TIMER_OUTCFG18_OUTCFG73_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71633   TIMER_OUTCFG18_OUTCFG73_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71634   TIMER_OUTCFG18_OUTCFG73_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71635   TIMER_OUTCFG18_OUTCFG73_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71636   TIMER_OUTCFG18_OUTCFG73_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71637   TIMER_OUTCFG18_OUTCFG73_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71638   TIMER_OUTCFG18_OUTCFG73_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71639   TIMER_OUTCFG18_OUTCFG73_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71640   TIMER_OUTCFG18_OUTCFG73_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71641   TIMER_OUTCFG18_OUTCFG73_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71642   TIMER_OUTCFG18_OUTCFG73_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71643   TIMER_OUTCFG18_OUTCFG73_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71644   TIMER_OUTCFG18_OUTCFG73_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71645   TIMER_OUTCFG18_OUTCFG73_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71646   TIMER_OUTCFG18_OUTCFG73_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71647   TIMER_OUTCFG18_OUTCFG73_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71648   TIMER_OUTCFG18_OUTCFG73_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71649   TIMER_OUTCFG18_OUTCFG73_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71650   TIMER_OUTCFG18_OUTCFG73_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71651   TIMER_OUTCFG18_OUTCFG73_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71652   TIMER_OUTCFG18_OUTCFG73_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71653   TIMER_OUTCFG18_OUTCFG73_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71654 } TIMER_OUTCFG18_OUTCFG73_Enum;
71655 
71656 /* ============================================  TIMER OUTCFG18 OUTCFG72 [0..5]  ============================================= */
71657 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG72                                                   */
71658   TIMER_OUTCFG18_OUTCFG72_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71659   TIMER_OUTCFG18_OUTCFG72_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71660   TIMER_OUTCFG18_OUTCFG72_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71661   TIMER_OUTCFG18_OUTCFG72_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71662   TIMER_OUTCFG18_OUTCFG72_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71663   TIMER_OUTCFG18_OUTCFG72_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71664   TIMER_OUTCFG18_OUTCFG72_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71665   TIMER_OUTCFG18_OUTCFG72_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71666   TIMER_OUTCFG18_OUTCFG72_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71667   TIMER_OUTCFG18_OUTCFG72_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71668   TIMER_OUTCFG18_OUTCFG72_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71669   TIMER_OUTCFG18_OUTCFG72_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71670   TIMER_OUTCFG18_OUTCFG72_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71671   TIMER_OUTCFG18_OUTCFG72_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71672   TIMER_OUTCFG18_OUTCFG72_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71673   TIMER_OUTCFG18_OUTCFG72_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71674   TIMER_OUTCFG18_OUTCFG72_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71675   TIMER_OUTCFG18_OUTCFG72_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71676   TIMER_OUTCFG18_OUTCFG72_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71677   TIMER_OUTCFG18_OUTCFG72_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71678   TIMER_OUTCFG18_OUTCFG72_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71679   TIMER_OUTCFG18_OUTCFG72_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71680   TIMER_OUTCFG18_OUTCFG72_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71681   TIMER_OUTCFG18_OUTCFG72_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71682   TIMER_OUTCFG18_OUTCFG72_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71683   TIMER_OUTCFG18_OUTCFG72_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71684   TIMER_OUTCFG18_OUTCFG72_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71685   TIMER_OUTCFG18_OUTCFG72_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71686   TIMER_OUTCFG18_OUTCFG72_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71687   TIMER_OUTCFG18_OUTCFG72_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71688   TIMER_OUTCFG18_OUTCFG72_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71689   TIMER_OUTCFG18_OUTCFG72_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71690   TIMER_OUTCFG18_OUTCFG72_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71691   TIMER_OUTCFG18_OUTCFG72_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71692   TIMER_OUTCFG18_OUTCFG72_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71693   TIMER_OUTCFG18_OUTCFG72_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71694   TIMER_OUTCFG18_OUTCFG72_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71695   TIMER_OUTCFG18_OUTCFG72_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71696   TIMER_OUTCFG18_OUTCFG72_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71697   TIMER_OUTCFG18_OUTCFG72_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71698   TIMER_OUTCFG18_OUTCFG72_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71699 } TIMER_OUTCFG18_OUTCFG72_Enum;
71700 
71701 /* =======================================================  OUTCFG19  ======================================================== */
71702 /* ===========================================  TIMER OUTCFG19 OUTCFG79 [24..29]  ============================================ */
71703 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG79                                                   */
71704   TIMER_OUTCFG19_OUTCFG79_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71705   TIMER_OUTCFG19_OUTCFG79_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71706   TIMER_OUTCFG19_OUTCFG79_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71707   TIMER_OUTCFG19_OUTCFG79_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71708   TIMER_OUTCFG19_OUTCFG79_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71709   TIMER_OUTCFG19_OUTCFG79_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71710   TIMER_OUTCFG19_OUTCFG79_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71711   TIMER_OUTCFG19_OUTCFG79_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71712   TIMER_OUTCFG19_OUTCFG79_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71713   TIMER_OUTCFG19_OUTCFG79_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71714   TIMER_OUTCFG19_OUTCFG79_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71715   TIMER_OUTCFG19_OUTCFG79_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71716   TIMER_OUTCFG19_OUTCFG79_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71717   TIMER_OUTCFG19_OUTCFG79_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71718   TIMER_OUTCFG19_OUTCFG79_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71719   TIMER_OUTCFG19_OUTCFG79_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71720   TIMER_OUTCFG19_OUTCFG79_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71721   TIMER_OUTCFG19_OUTCFG79_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71722   TIMER_OUTCFG19_OUTCFG79_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71723   TIMER_OUTCFG19_OUTCFG79_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71724   TIMER_OUTCFG19_OUTCFG79_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71725   TIMER_OUTCFG19_OUTCFG79_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71726   TIMER_OUTCFG19_OUTCFG79_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71727   TIMER_OUTCFG19_OUTCFG79_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71728   TIMER_OUTCFG19_OUTCFG79_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71729   TIMER_OUTCFG19_OUTCFG79_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71730   TIMER_OUTCFG19_OUTCFG79_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71731   TIMER_OUTCFG19_OUTCFG79_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71732   TIMER_OUTCFG19_OUTCFG79_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71733   TIMER_OUTCFG19_OUTCFG79_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71734   TIMER_OUTCFG19_OUTCFG79_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71735   TIMER_OUTCFG19_OUTCFG79_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71736   TIMER_OUTCFG19_OUTCFG79_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71737   TIMER_OUTCFG19_OUTCFG79_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71738   TIMER_OUTCFG19_OUTCFG79_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71739   TIMER_OUTCFG19_OUTCFG79_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71740   TIMER_OUTCFG19_OUTCFG79_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71741   TIMER_OUTCFG19_OUTCFG79_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71742   TIMER_OUTCFG19_OUTCFG79_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71743   TIMER_OUTCFG19_OUTCFG79_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71744   TIMER_OUTCFG19_OUTCFG79_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71745 } TIMER_OUTCFG19_OUTCFG79_Enum;
71746 
71747 /* ===========================================  TIMER OUTCFG19 OUTCFG78 [16..21]  ============================================ */
71748 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG78                                                   */
71749   TIMER_OUTCFG19_OUTCFG78_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71750   TIMER_OUTCFG19_OUTCFG78_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71751   TIMER_OUTCFG19_OUTCFG78_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71752   TIMER_OUTCFG19_OUTCFG78_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71753   TIMER_OUTCFG19_OUTCFG78_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71754   TIMER_OUTCFG19_OUTCFG78_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71755   TIMER_OUTCFG19_OUTCFG78_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71756   TIMER_OUTCFG19_OUTCFG78_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71757   TIMER_OUTCFG19_OUTCFG78_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71758   TIMER_OUTCFG19_OUTCFG78_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71759   TIMER_OUTCFG19_OUTCFG78_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71760   TIMER_OUTCFG19_OUTCFG78_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71761   TIMER_OUTCFG19_OUTCFG78_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71762   TIMER_OUTCFG19_OUTCFG78_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71763   TIMER_OUTCFG19_OUTCFG78_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71764   TIMER_OUTCFG19_OUTCFG78_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71765   TIMER_OUTCFG19_OUTCFG78_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71766   TIMER_OUTCFG19_OUTCFG78_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71767   TIMER_OUTCFG19_OUTCFG78_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71768   TIMER_OUTCFG19_OUTCFG78_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71769   TIMER_OUTCFG19_OUTCFG78_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71770   TIMER_OUTCFG19_OUTCFG78_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71771   TIMER_OUTCFG19_OUTCFG78_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71772   TIMER_OUTCFG19_OUTCFG78_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71773   TIMER_OUTCFG19_OUTCFG78_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71774   TIMER_OUTCFG19_OUTCFG78_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71775   TIMER_OUTCFG19_OUTCFG78_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71776   TIMER_OUTCFG19_OUTCFG78_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71777   TIMER_OUTCFG19_OUTCFG78_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71778   TIMER_OUTCFG19_OUTCFG78_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71779   TIMER_OUTCFG19_OUTCFG78_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71780   TIMER_OUTCFG19_OUTCFG78_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71781   TIMER_OUTCFG19_OUTCFG78_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71782   TIMER_OUTCFG19_OUTCFG78_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71783   TIMER_OUTCFG19_OUTCFG78_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71784   TIMER_OUTCFG19_OUTCFG78_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71785   TIMER_OUTCFG19_OUTCFG78_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71786   TIMER_OUTCFG19_OUTCFG78_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71787   TIMER_OUTCFG19_OUTCFG78_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71788   TIMER_OUTCFG19_OUTCFG78_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71789   TIMER_OUTCFG19_OUTCFG78_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71790 } TIMER_OUTCFG19_OUTCFG78_Enum;
71791 
71792 /* ============================================  TIMER OUTCFG19 OUTCFG77 [8..13]  ============================================ */
71793 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG77                                                   */
71794   TIMER_OUTCFG19_OUTCFG77_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71795   TIMER_OUTCFG19_OUTCFG77_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71796   TIMER_OUTCFG19_OUTCFG77_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71797   TIMER_OUTCFG19_OUTCFG77_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71798   TIMER_OUTCFG19_OUTCFG77_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71799   TIMER_OUTCFG19_OUTCFG77_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71800   TIMER_OUTCFG19_OUTCFG77_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71801   TIMER_OUTCFG19_OUTCFG77_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71802   TIMER_OUTCFG19_OUTCFG77_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71803   TIMER_OUTCFG19_OUTCFG77_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71804   TIMER_OUTCFG19_OUTCFG77_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71805   TIMER_OUTCFG19_OUTCFG77_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71806   TIMER_OUTCFG19_OUTCFG77_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71807   TIMER_OUTCFG19_OUTCFG77_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71808   TIMER_OUTCFG19_OUTCFG77_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71809   TIMER_OUTCFG19_OUTCFG77_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71810   TIMER_OUTCFG19_OUTCFG77_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71811   TIMER_OUTCFG19_OUTCFG77_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71812   TIMER_OUTCFG19_OUTCFG77_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71813   TIMER_OUTCFG19_OUTCFG77_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71814   TIMER_OUTCFG19_OUTCFG77_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71815   TIMER_OUTCFG19_OUTCFG77_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71816   TIMER_OUTCFG19_OUTCFG77_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71817   TIMER_OUTCFG19_OUTCFG77_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71818   TIMER_OUTCFG19_OUTCFG77_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71819   TIMER_OUTCFG19_OUTCFG77_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71820   TIMER_OUTCFG19_OUTCFG77_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71821   TIMER_OUTCFG19_OUTCFG77_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71822   TIMER_OUTCFG19_OUTCFG77_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71823   TIMER_OUTCFG19_OUTCFG77_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71824   TIMER_OUTCFG19_OUTCFG77_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71825   TIMER_OUTCFG19_OUTCFG77_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71826   TIMER_OUTCFG19_OUTCFG77_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71827   TIMER_OUTCFG19_OUTCFG77_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71828   TIMER_OUTCFG19_OUTCFG77_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71829   TIMER_OUTCFG19_OUTCFG77_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71830   TIMER_OUTCFG19_OUTCFG77_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71831   TIMER_OUTCFG19_OUTCFG77_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71832   TIMER_OUTCFG19_OUTCFG77_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71833   TIMER_OUTCFG19_OUTCFG77_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71834   TIMER_OUTCFG19_OUTCFG77_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71835 } TIMER_OUTCFG19_OUTCFG77_Enum;
71836 
71837 /* ============================================  TIMER OUTCFG19 OUTCFG76 [0..5]  ============================================= */
71838 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG76                                                   */
71839   TIMER_OUTCFG19_OUTCFG76_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71840   TIMER_OUTCFG19_OUTCFG76_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71841   TIMER_OUTCFG19_OUTCFG76_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71842   TIMER_OUTCFG19_OUTCFG76_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71843   TIMER_OUTCFG19_OUTCFG76_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71844   TIMER_OUTCFG19_OUTCFG76_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71845   TIMER_OUTCFG19_OUTCFG76_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71846   TIMER_OUTCFG19_OUTCFG76_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71847   TIMER_OUTCFG19_OUTCFG76_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71848   TIMER_OUTCFG19_OUTCFG76_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71849   TIMER_OUTCFG19_OUTCFG76_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71850   TIMER_OUTCFG19_OUTCFG76_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71851   TIMER_OUTCFG19_OUTCFG76_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71852   TIMER_OUTCFG19_OUTCFG76_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71853   TIMER_OUTCFG19_OUTCFG76_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71854   TIMER_OUTCFG19_OUTCFG76_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71855   TIMER_OUTCFG19_OUTCFG76_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71856   TIMER_OUTCFG19_OUTCFG76_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71857   TIMER_OUTCFG19_OUTCFG76_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71858   TIMER_OUTCFG19_OUTCFG76_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71859   TIMER_OUTCFG19_OUTCFG76_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71860   TIMER_OUTCFG19_OUTCFG76_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71861   TIMER_OUTCFG19_OUTCFG76_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71862   TIMER_OUTCFG19_OUTCFG76_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71863   TIMER_OUTCFG19_OUTCFG76_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71864   TIMER_OUTCFG19_OUTCFG76_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71865   TIMER_OUTCFG19_OUTCFG76_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71866   TIMER_OUTCFG19_OUTCFG76_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71867   TIMER_OUTCFG19_OUTCFG76_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71868   TIMER_OUTCFG19_OUTCFG76_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71869   TIMER_OUTCFG19_OUTCFG76_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71870   TIMER_OUTCFG19_OUTCFG76_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71871   TIMER_OUTCFG19_OUTCFG76_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71872   TIMER_OUTCFG19_OUTCFG76_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71873   TIMER_OUTCFG19_OUTCFG76_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71874   TIMER_OUTCFG19_OUTCFG76_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71875   TIMER_OUTCFG19_OUTCFG76_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71876   TIMER_OUTCFG19_OUTCFG76_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71877   TIMER_OUTCFG19_OUTCFG76_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71878   TIMER_OUTCFG19_OUTCFG76_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71879   TIMER_OUTCFG19_OUTCFG76_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71880 } TIMER_OUTCFG19_OUTCFG76_Enum;
71881 
71882 /* =======================================================  OUTCFG20  ======================================================== */
71883 /* ===========================================  TIMER OUTCFG20 OUTCFG83 [24..29]  ============================================ */
71884 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG83                                                   */
71885   TIMER_OUTCFG20_OUTCFG83_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71886   TIMER_OUTCFG20_OUTCFG83_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71887   TIMER_OUTCFG20_OUTCFG83_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71888   TIMER_OUTCFG20_OUTCFG83_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71889   TIMER_OUTCFG20_OUTCFG83_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71890   TIMER_OUTCFG20_OUTCFG83_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71891   TIMER_OUTCFG20_OUTCFG83_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71892   TIMER_OUTCFG20_OUTCFG83_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71893   TIMER_OUTCFG20_OUTCFG83_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71894   TIMER_OUTCFG20_OUTCFG83_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71895   TIMER_OUTCFG20_OUTCFG83_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71896   TIMER_OUTCFG20_OUTCFG83_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71897   TIMER_OUTCFG20_OUTCFG83_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71898   TIMER_OUTCFG20_OUTCFG83_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71899   TIMER_OUTCFG20_OUTCFG83_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71900   TIMER_OUTCFG20_OUTCFG83_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71901   TIMER_OUTCFG20_OUTCFG83_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71902   TIMER_OUTCFG20_OUTCFG83_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71903   TIMER_OUTCFG20_OUTCFG83_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71904   TIMER_OUTCFG20_OUTCFG83_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71905   TIMER_OUTCFG20_OUTCFG83_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71906   TIMER_OUTCFG20_OUTCFG83_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71907   TIMER_OUTCFG20_OUTCFG83_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71908   TIMER_OUTCFG20_OUTCFG83_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71909   TIMER_OUTCFG20_OUTCFG83_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71910   TIMER_OUTCFG20_OUTCFG83_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71911   TIMER_OUTCFG20_OUTCFG83_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71912   TIMER_OUTCFG20_OUTCFG83_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71913   TIMER_OUTCFG20_OUTCFG83_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71914   TIMER_OUTCFG20_OUTCFG83_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71915   TIMER_OUTCFG20_OUTCFG83_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71916   TIMER_OUTCFG20_OUTCFG83_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71917   TIMER_OUTCFG20_OUTCFG83_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71918   TIMER_OUTCFG20_OUTCFG83_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71919   TIMER_OUTCFG20_OUTCFG83_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71920   TIMER_OUTCFG20_OUTCFG83_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71921   TIMER_OUTCFG20_OUTCFG83_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71922   TIMER_OUTCFG20_OUTCFG83_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71923   TIMER_OUTCFG20_OUTCFG83_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71924   TIMER_OUTCFG20_OUTCFG83_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71925   TIMER_OUTCFG20_OUTCFG83_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71926 } TIMER_OUTCFG20_OUTCFG83_Enum;
71927 
71928 /* ===========================================  TIMER OUTCFG20 OUTCFG82 [16..21]  ============================================ */
71929 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG82                                                   */
71930   TIMER_OUTCFG20_OUTCFG82_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71931   TIMER_OUTCFG20_OUTCFG82_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71932   TIMER_OUTCFG20_OUTCFG82_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71933   TIMER_OUTCFG20_OUTCFG82_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71934   TIMER_OUTCFG20_OUTCFG82_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71935   TIMER_OUTCFG20_OUTCFG82_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71936   TIMER_OUTCFG20_OUTCFG82_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71937   TIMER_OUTCFG20_OUTCFG82_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71938   TIMER_OUTCFG20_OUTCFG82_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71939   TIMER_OUTCFG20_OUTCFG82_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71940   TIMER_OUTCFG20_OUTCFG82_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71941   TIMER_OUTCFG20_OUTCFG82_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71942   TIMER_OUTCFG20_OUTCFG82_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71943   TIMER_OUTCFG20_OUTCFG82_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71944   TIMER_OUTCFG20_OUTCFG82_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71945   TIMER_OUTCFG20_OUTCFG82_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71946   TIMER_OUTCFG20_OUTCFG82_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71947   TIMER_OUTCFG20_OUTCFG82_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71948   TIMER_OUTCFG20_OUTCFG82_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71949   TIMER_OUTCFG20_OUTCFG82_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71950   TIMER_OUTCFG20_OUTCFG82_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71951   TIMER_OUTCFG20_OUTCFG82_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71952   TIMER_OUTCFG20_OUTCFG82_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71953   TIMER_OUTCFG20_OUTCFG82_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71954   TIMER_OUTCFG20_OUTCFG82_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71955   TIMER_OUTCFG20_OUTCFG82_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71956   TIMER_OUTCFG20_OUTCFG82_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71957   TIMER_OUTCFG20_OUTCFG82_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71958   TIMER_OUTCFG20_OUTCFG82_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71959   TIMER_OUTCFG20_OUTCFG82_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71960   TIMER_OUTCFG20_OUTCFG82_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71961   TIMER_OUTCFG20_OUTCFG82_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71962   TIMER_OUTCFG20_OUTCFG82_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71963   TIMER_OUTCFG20_OUTCFG82_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71964   TIMER_OUTCFG20_OUTCFG82_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71965   TIMER_OUTCFG20_OUTCFG82_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71966   TIMER_OUTCFG20_OUTCFG82_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71967   TIMER_OUTCFG20_OUTCFG82_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71968   TIMER_OUTCFG20_OUTCFG82_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71969   TIMER_OUTCFG20_OUTCFG82_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71970   TIMER_OUTCFG20_OUTCFG82_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71971 } TIMER_OUTCFG20_OUTCFG82_Enum;
71972 
71973 /* ============================================  TIMER OUTCFG20 OUTCFG81 [8..13]  ============================================ */
71974 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG81                                                   */
71975   TIMER_OUTCFG20_OUTCFG81_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71976   TIMER_OUTCFG20_OUTCFG81_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71977   TIMER_OUTCFG20_OUTCFG81_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71978   TIMER_OUTCFG20_OUTCFG81_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71979   TIMER_OUTCFG20_OUTCFG81_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71980   TIMER_OUTCFG20_OUTCFG81_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71981   TIMER_OUTCFG20_OUTCFG81_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71982   TIMER_OUTCFG20_OUTCFG81_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71983   TIMER_OUTCFG20_OUTCFG81_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71984   TIMER_OUTCFG20_OUTCFG81_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71985   TIMER_OUTCFG20_OUTCFG81_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71986   TIMER_OUTCFG20_OUTCFG81_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71987   TIMER_OUTCFG20_OUTCFG81_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71988   TIMER_OUTCFG20_OUTCFG81_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71989   TIMER_OUTCFG20_OUTCFG81_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71990   TIMER_OUTCFG20_OUTCFG81_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71991   TIMER_OUTCFG20_OUTCFG81_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71992   TIMER_OUTCFG20_OUTCFG81_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71993   TIMER_OUTCFG20_OUTCFG81_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71994   TIMER_OUTCFG20_OUTCFG81_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71995   TIMER_OUTCFG20_OUTCFG81_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71996   TIMER_OUTCFG20_OUTCFG81_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71997   TIMER_OUTCFG20_OUTCFG81_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71998   TIMER_OUTCFG20_OUTCFG81_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71999   TIMER_OUTCFG20_OUTCFG81_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72000   TIMER_OUTCFG20_OUTCFG81_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72001   TIMER_OUTCFG20_OUTCFG81_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72002   TIMER_OUTCFG20_OUTCFG81_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72003   TIMER_OUTCFG20_OUTCFG81_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72004   TIMER_OUTCFG20_OUTCFG81_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72005   TIMER_OUTCFG20_OUTCFG81_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72006   TIMER_OUTCFG20_OUTCFG81_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72007   TIMER_OUTCFG20_OUTCFG81_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72008   TIMER_OUTCFG20_OUTCFG81_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72009   TIMER_OUTCFG20_OUTCFG81_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72010   TIMER_OUTCFG20_OUTCFG81_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72011   TIMER_OUTCFG20_OUTCFG81_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72012   TIMER_OUTCFG20_OUTCFG81_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72013   TIMER_OUTCFG20_OUTCFG81_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72014   TIMER_OUTCFG20_OUTCFG81_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72015   TIMER_OUTCFG20_OUTCFG81_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72016 } TIMER_OUTCFG20_OUTCFG81_Enum;
72017 
72018 /* ============================================  TIMER OUTCFG20 OUTCFG80 [0..5]  ============================================= */
72019 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG80                                                   */
72020   TIMER_OUTCFG20_OUTCFG80_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72021   TIMER_OUTCFG20_OUTCFG80_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72022   TIMER_OUTCFG20_OUTCFG80_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72023   TIMER_OUTCFG20_OUTCFG80_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72024   TIMER_OUTCFG20_OUTCFG80_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72025   TIMER_OUTCFG20_OUTCFG80_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72026   TIMER_OUTCFG20_OUTCFG80_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72027   TIMER_OUTCFG20_OUTCFG80_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72028   TIMER_OUTCFG20_OUTCFG80_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72029   TIMER_OUTCFG20_OUTCFG80_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72030   TIMER_OUTCFG20_OUTCFG80_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72031   TIMER_OUTCFG20_OUTCFG80_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72032   TIMER_OUTCFG20_OUTCFG80_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72033   TIMER_OUTCFG20_OUTCFG80_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72034   TIMER_OUTCFG20_OUTCFG80_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72035   TIMER_OUTCFG20_OUTCFG80_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72036   TIMER_OUTCFG20_OUTCFG80_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72037   TIMER_OUTCFG20_OUTCFG80_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72038   TIMER_OUTCFG20_OUTCFG80_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72039   TIMER_OUTCFG20_OUTCFG80_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72040   TIMER_OUTCFG20_OUTCFG80_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72041   TIMER_OUTCFG20_OUTCFG80_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72042   TIMER_OUTCFG20_OUTCFG80_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72043   TIMER_OUTCFG20_OUTCFG80_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72044   TIMER_OUTCFG20_OUTCFG80_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72045   TIMER_OUTCFG20_OUTCFG80_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72046   TIMER_OUTCFG20_OUTCFG80_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72047   TIMER_OUTCFG20_OUTCFG80_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72048   TIMER_OUTCFG20_OUTCFG80_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72049   TIMER_OUTCFG20_OUTCFG80_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72050   TIMER_OUTCFG20_OUTCFG80_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72051   TIMER_OUTCFG20_OUTCFG80_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72052   TIMER_OUTCFG20_OUTCFG80_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72053   TIMER_OUTCFG20_OUTCFG80_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72054   TIMER_OUTCFG20_OUTCFG80_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72055   TIMER_OUTCFG20_OUTCFG80_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72056   TIMER_OUTCFG20_OUTCFG80_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72057   TIMER_OUTCFG20_OUTCFG80_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72058   TIMER_OUTCFG20_OUTCFG80_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72059   TIMER_OUTCFG20_OUTCFG80_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72060   TIMER_OUTCFG20_OUTCFG80_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72061 } TIMER_OUTCFG20_OUTCFG80_Enum;
72062 
72063 /* =======================================================  OUTCFG21  ======================================================== */
72064 /* ===========================================  TIMER OUTCFG21 OUTCFG87 [24..29]  ============================================ */
72065 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG87                                                   */
72066   TIMER_OUTCFG21_OUTCFG87_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72067   TIMER_OUTCFG21_OUTCFG87_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72068   TIMER_OUTCFG21_OUTCFG87_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72069   TIMER_OUTCFG21_OUTCFG87_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72070   TIMER_OUTCFG21_OUTCFG87_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72071   TIMER_OUTCFG21_OUTCFG87_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72072   TIMER_OUTCFG21_OUTCFG87_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72073   TIMER_OUTCFG21_OUTCFG87_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72074   TIMER_OUTCFG21_OUTCFG87_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72075   TIMER_OUTCFG21_OUTCFG87_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72076   TIMER_OUTCFG21_OUTCFG87_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72077   TIMER_OUTCFG21_OUTCFG87_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72078   TIMER_OUTCFG21_OUTCFG87_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72079   TIMER_OUTCFG21_OUTCFG87_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72080   TIMER_OUTCFG21_OUTCFG87_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72081   TIMER_OUTCFG21_OUTCFG87_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72082   TIMER_OUTCFG21_OUTCFG87_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72083   TIMER_OUTCFG21_OUTCFG87_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72084   TIMER_OUTCFG21_OUTCFG87_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72085   TIMER_OUTCFG21_OUTCFG87_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72086   TIMER_OUTCFG21_OUTCFG87_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72087   TIMER_OUTCFG21_OUTCFG87_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72088   TIMER_OUTCFG21_OUTCFG87_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72089   TIMER_OUTCFG21_OUTCFG87_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72090   TIMER_OUTCFG21_OUTCFG87_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72091   TIMER_OUTCFG21_OUTCFG87_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72092   TIMER_OUTCFG21_OUTCFG87_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72093   TIMER_OUTCFG21_OUTCFG87_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72094   TIMER_OUTCFG21_OUTCFG87_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72095   TIMER_OUTCFG21_OUTCFG87_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72096   TIMER_OUTCFG21_OUTCFG87_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72097   TIMER_OUTCFG21_OUTCFG87_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72098   TIMER_OUTCFG21_OUTCFG87_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72099   TIMER_OUTCFG21_OUTCFG87_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72100   TIMER_OUTCFG21_OUTCFG87_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72101   TIMER_OUTCFG21_OUTCFG87_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72102   TIMER_OUTCFG21_OUTCFG87_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72103   TIMER_OUTCFG21_OUTCFG87_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72104   TIMER_OUTCFG21_OUTCFG87_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72105   TIMER_OUTCFG21_OUTCFG87_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72106   TIMER_OUTCFG21_OUTCFG87_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72107 } TIMER_OUTCFG21_OUTCFG87_Enum;
72108 
72109 /* ===========================================  TIMER OUTCFG21 OUTCFG86 [16..21]  ============================================ */
72110 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG86                                                   */
72111   TIMER_OUTCFG21_OUTCFG86_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72112   TIMER_OUTCFG21_OUTCFG86_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72113   TIMER_OUTCFG21_OUTCFG86_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72114   TIMER_OUTCFG21_OUTCFG86_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72115   TIMER_OUTCFG21_OUTCFG86_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72116   TIMER_OUTCFG21_OUTCFG86_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72117   TIMER_OUTCFG21_OUTCFG86_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72118   TIMER_OUTCFG21_OUTCFG86_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72119   TIMER_OUTCFG21_OUTCFG86_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72120   TIMER_OUTCFG21_OUTCFG86_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72121   TIMER_OUTCFG21_OUTCFG86_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72122   TIMER_OUTCFG21_OUTCFG86_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72123   TIMER_OUTCFG21_OUTCFG86_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72124   TIMER_OUTCFG21_OUTCFG86_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72125   TIMER_OUTCFG21_OUTCFG86_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72126   TIMER_OUTCFG21_OUTCFG86_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72127   TIMER_OUTCFG21_OUTCFG86_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72128   TIMER_OUTCFG21_OUTCFG86_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72129   TIMER_OUTCFG21_OUTCFG86_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72130   TIMER_OUTCFG21_OUTCFG86_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72131   TIMER_OUTCFG21_OUTCFG86_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72132   TIMER_OUTCFG21_OUTCFG86_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72133   TIMER_OUTCFG21_OUTCFG86_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72134   TIMER_OUTCFG21_OUTCFG86_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72135   TIMER_OUTCFG21_OUTCFG86_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72136   TIMER_OUTCFG21_OUTCFG86_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72137   TIMER_OUTCFG21_OUTCFG86_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72138   TIMER_OUTCFG21_OUTCFG86_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72139   TIMER_OUTCFG21_OUTCFG86_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72140   TIMER_OUTCFG21_OUTCFG86_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72141   TIMER_OUTCFG21_OUTCFG86_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72142   TIMER_OUTCFG21_OUTCFG86_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72143   TIMER_OUTCFG21_OUTCFG86_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72144   TIMER_OUTCFG21_OUTCFG86_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72145   TIMER_OUTCFG21_OUTCFG86_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72146   TIMER_OUTCFG21_OUTCFG86_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72147   TIMER_OUTCFG21_OUTCFG86_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72148   TIMER_OUTCFG21_OUTCFG86_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72149   TIMER_OUTCFG21_OUTCFG86_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72150   TIMER_OUTCFG21_OUTCFG86_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72151   TIMER_OUTCFG21_OUTCFG86_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72152 } TIMER_OUTCFG21_OUTCFG86_Enum;
72153 
72154 /* ============================================  TIMER OUTCFG21 OUTCFG85 [8..13]  ============================================ */
72155 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG85                                                   */
72156   TIMER_OUTCFG21_OUTCFG85_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72157   TIMER_OUTCFG21_OUTCFG85_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72158   TIMER_OUTCFG21_OUTCFG85_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72159   TIMER_OUTCFG21_OUTCFG85_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72160   TIMER_OUTCFG21_OUTCFG85_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72161   TIMER_OUTCFG21_OUTCFG85_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72162   TIMER_OUTCFG21_OUTCFG85_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72163   TIMER_OUTCFG21_OUTCFG85_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72164   TIMER_OUTCFG21_OUTCFG85_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72165   TIMER_OUTCFG21_OUTCFG85_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72166   TIMER_OUTCFG21_OUTCFG85_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72167   TIMER_OUTCFG21_OUTCFG85_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72168   TIMER_OUTCFG21_OUTCFG85_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72169   TIMER_OUTCFG21_OUTCFG85_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72170   TIMER_OUTCFG21_OUTCFG85_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72171   TIMER_OUTCFG21_OUTCFG85_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72172   TIMER_OUTCFG21_OUTCFG85_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72173   TIMER_OUTCFG21_OUTCFG85_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72174   TIMER_OUTCFG21_OUTCFG85_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72175   TIMER_OUTCFG21_OUTCFG85_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72176   TIMER_OUTCFG21_OUTCFG85_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72177   TIMER_OUTCFG21_OUTCFG85_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72178   TIMER_OUTCFG21_OUTCFG85_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72179   TIMER_OUTCFG21_OUTCFG85_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72180   TIMER_OUTCFG21_OUTCFG85_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72181   TIMER_OUTCFG21_OUTCFG85_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72182   TIMER_OUTCFG21_OUTCFG85_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72183   TIMER_OUTCFG21_OUTCFG85_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72184   TIMER_OUTCFG21_OUTCFG85_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72185   TIMER_OUTCFG21_OUTCFG85_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72186   TIMER_OUTCFG21_OUTCFG85_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72187   TIMER_OUTCFG21_OUTCFG85_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72188   TIMER_OUTCFG21_OUTCFG85_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72189   TIMER_OUTCFG21_OUTCFG85_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72190   TIMER_OUTCFG21_OUTCFG85_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72191   TIMER_OUTCFG21_OUTCFG85_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72192   TIMER_OUTCFG21_OUTCFG85_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72193   TIMER_OUTCFG21_OUTCFG85_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72194   TIMER_OUTCFG21_OUTCFG85_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72195   TIMER_OUTCFG21_OUTCFG85_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72196   TIMER_OUTCFG21_OUTCFG85_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72197 } TIMER_OUTCFG21_OUTCFG85_Enum;
72198 
72199 /* ============================================  TIMER OUTCFG21 OUTCFG84 [0..5]  ============================================= */
72200 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG84                                                   */
72201   TIMER_OUTCFG21_OUTCFG84_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72202   TIMER_OUTCFG21_OUTCFG84_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72203   TIMER_OUTCFG21_OUTCFG84_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72204   TIMER_OUTCFG21_OUTCFG84_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72205   TIMER_OUTCFG21_OUTCFG84_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72206   TIMER_OUTCFG21_OUTCFG84_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72207   TIMER_OUTCFG21_OUTCFG84_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72208   TIMER_OUTCFG21_OUTCFG84_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72209   TIMER_OUTCFG21_OUTCFG84_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72210   TIMER_OUTCFG21_OUTCFG84_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72211   TIMER_OUTCFG21_OUTCFG84_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72212   TIMER_OUTCFG21_OUTCFG84_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72213   TIMER_OUTCFG21_OUTCFG84_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72214   TIMER_OUTCFG21_OUTCFG84_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72215   TIMER_OUTCFG21_OUTCFG84_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72216   TIMER_OUTCFG21_OUTCFG84_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72217   TIMER_OUTCFG21_OUTCFG84_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72218   TIMER_OUTCFG21_OUTCFG84_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72219   TIMER_OUTCFG21_OUTCFG84_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72220   TIMER_OUTCFG21_OUTCFG84_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72221   TIMER_OUTCFG21_OUTCFG84_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72222   TIMER_OUTCFG21_OUTCFG84_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72223   TIMER_OUTCFG21_OUTCFG84_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72224   TIMER_OUTCFG21_OUTCFG84_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72225   TIMER_OUTCFG21_OUTCFG84_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72226   TIMER_OUTCFG21_OUTCFG84_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72227   TIMER_OUTCFG21_OUTCFG84_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72228   TIMER_OUTCFG21_OUTCFG84_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72229   TIMER_OUTCFG21_OUTCFG84_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72230   TIMER_OUTCFG21_OUTCFG84_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72231   TIMER_OUTCFG21_OUTCFG84_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72232   TIMER_OUTCFG21_OUTCFG84_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72233   TIMER_OUTCFG21_OUTCFG84_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72234   TIMER_OUTCFG21_OUTCFG84_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72235   TIMER_OUTCFG21_OUTCFG84_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72236   TIMER_OUTCFG21_OUTCFG84_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72237   TIMER_OUTCFG21_OUTCFG84_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72238   TIMER_OUTCFG21_OUTCFG84_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72239   TIMER_OUTCFG21_OUTCFG84_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72240   TIMER_OUTCFG21_OUTCFG84_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72241   TIMER_OUTCFG21_OUTCFG84_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72242 } TIMER_OUTCFG21_OUTCFG84_Enum;
72243 
72244 /* =======================================================  OUTCFG22  ======================================================== */
72245 /* ===========================================  TIMER OUTCFG22 OUTCFG91 [24..29]  ============================================ */
72246 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG91                                                   */
72247   TIMER_OUTCFG22_OUTCFG91_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72248   TIMER_OUTCFG22_OUTCFG91_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72249   TIMER_OUTCFG22_OUTCFG91_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72250   TIMER_OUTCFG22_OUTCFG91_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72251   TIMER_OUTCFG22_OUTCFG91_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72252   TIMER_OUTCFG22_OUTCFG91_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72253   TIMER_OUTCFG22_OUTCFG91_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72254   TIMER_OUTCFG22_OUTCFG91_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72255   TIMER_OUTCFG22_OUTCFG91_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72256   TIMER_OUTCFG22_OUTCFG91_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72257   TIMER_OUTCFG22_OUTCFG91_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72258   TIMER_OUTCFG22_OUTCFG91_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72259   TIMER_OUTCFG22_OUTCFG91_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72260   TIMER_OUTCFG22_OUTCFG91_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72261   TIMER_OUTCFG22_OUTCFG91_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72262   TIMER_OUTCFG22_OUTCFG91_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72263   TIMER_OUTCFG22_OUTCFG91_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72264   TIMER_OUTCFG22_OUTCFG91_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72265   TIMER_OUTCFG22_OUTCFG91_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72266   TIMER_OUTCFG22_OUTCFG91_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72267   TIMER_OUTCFG22_OUTCFG91_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72268   TIMER_OUTCFG22_OUTCFG91_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72269   TIMER_OUTCFG22_OUTCFG91_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72270   TIMER_OUTCFG22_OUTCFG91_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72271   TIMER_OUTCFG22_OUTCFG91_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72272   TIMER_OUTCFG22_OUTCFG91_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72273   TIMER_OUTCFG22_OUTCFG91_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72274   TIMER_OUTCFG22_OUTCFG91_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72275   TIMER_OUTCFG22_OUTCFG91_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72276   TIMER_OUTCFG22_OUTCFG91_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72277   TIMER_OUTCFG22_OUTCFG91_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72278   TIMER_OUTCFG22_OUTCFG91_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72279   TIMER_OUTCFG22_OUTCFG91_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72280   TIMER_OUTCFG22_OUTCFG91_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72281   TIMER_OUTCFG22_OUTCFG91_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72282   TIMER_OUTCFG22_OUTCFG91_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72283   TIMER_OUTCFG22_OUTCFG91_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72284   TIMER_OUTCFG22_OUTCFG91_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72285   TIMER_OUTCFG22_OUTCFG91_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72286   TIMER_OUTCFG22_OUTCFG91_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72287   TIMER_OUTCFG22_OUTCFG91_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72288 } TIMER_OUTCFG22_OUTCFG91_Enum;
72289 
72290 /* ===========================================  TIMER OUTCFG22 OUTCFG90 [16..21]  ============================================ */
72291 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG90                                                   */
72292   TIMER_OUTCFG22_OUTCFG90_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72293   TIMER_OUTCFG22_OUTCFG90_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72294   TIMER_OUTCFG22_OUTCFG90_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72295   TIMER_OUTCFG22_OUTCFG90_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72296   TIMER_OUTCFG22_OUTCFG90_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72297   TIMER_OUTCFG22_OUTCFG90_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72298   TIMER_OUTCFG22_OUTCFG90_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72299   TIMER_OUTCFG22_OUTCFG90_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72300   TIMER_OUTCFG22_OUTCFG90_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72301   TIMER_OUTCFG22_OUTCFG90_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72302   TIMER_OUTCFG22_OUTCFG90_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72303   TIMER_OUTCFG22_OUTCFG90_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72304   TIMER_OUTCFG22_OUTCFG90_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72305   TIMER_OUTCFG22_OUTCFG90_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72306   TIMER_OUTCFG22_OUTCFG90_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72307   TIMER_OUTCFG22_OUTCFG90_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72308   TIMER_OUTCFG22_OUTCFG90_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72309   TIMER_OUTCFG22_OUTCFG90_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72310   TIMER_OUTCFG22_OUTCFG90_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72311   TIMER_OUTCFG22_OUTCFG90_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72312   TIMER_OUTCFG22_OUTCFG90_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72313   TIMER_OUTCFG22_OUTCFG90_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72314   TIMER_OUTCFG22_OUTCFG90_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72315   TIMER_OUTCFG22_OUTCFG90_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72316   TIMER_OUTCFG22_OUTCFG90_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72317   TIMER_OUTCFG22_OUTCFG90_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72318   TIMER_OUTCFG22_OUTCFG90_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72319   TIMER_OUTCFG22_OUTCFG90_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72320   TIMER_OUTCFG22_OUTCFG90_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72321   TIMER_OUTCFG22_OUTCFG90_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72322   TIMER_OUTCFG22_OUTCFG90_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72323   TIMER_OUTCFG22_OUTCFG90_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72324   TIMER_OUTCFG22_OUTCFG90_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72325   TIMER_OUTCFG22_OUTCFG90_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72326   TIMER_OUTCFG22_OUTCFG90_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72327   TIMER_OUTCFG22_OUTCFG90_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72328   TIMER_OUTCFG22_OUTCFG90_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72329   TIMER_OUTCFG22_OUTCFG90_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72330   TIMER_OUTCFG22_OUTCFG90_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72331   TIMER_OUTCFG22_OUTCFG90_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72332   TIMER_OUTCFG22_OUTCFG90_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72333 } TIMER_OUTCFG22_OUTCFG90_Enum;
72334 
72335 /* ============================================  TIMER OUTCFG22 OUTCFG89 [8..13]  ============================================ */
72336 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG89                                                   */
72337   TIMER_OUTCFG22_OUTCFG89_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72338   TIMER_OUTCFG22_OUTCFG89_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72339   TIMER_OUTCFG22_OUTCFG89_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72340   TIMER_OUTCFG22_OUTCFG89_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72341   TIMER_OUTCFG22_OUTCFG89_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72342   TIMER_OUTCFG22_OUTCFG89_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72343   TIMER_OUTCFG22_OUTCFG89_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72344   TIMER_OUTCFG22_OUTCFG89_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72345   TIMER_OUTCFG22_OUTCFG89_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72346   TIMER_OUTCFG22_OUTCFG89_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72347   TIMER_OUTCFG22_OUTCFG89_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72348   TIMER_OUTCFG22_OUTCFG89_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72349   TIMER_OUTCFG22_OUTCFG89_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72350   TIMER_OUTCFG22_OUTCFG89_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72351   TIMER_OUTCFG22_OUTCFG89_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72352   TIMER_OUTCFG22_OUTCFG89_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72353   TIMER_OUTCFG22_OUTCFG89_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72354   TIMER_OUTCFG22_OUTCFG89_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72355   TIMER_OUTCFG22_OUTCFG89_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72356   TIMER_OUTCFG22_OUTCFG89_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72357   TIMER_OUTCFG22_OUTCFG89_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72358   TIMER_OUTCFG22_OUTCFG89_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72359   TIMER_OUTCFG22_OUTCFG89_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72360   TIMER_OUTCFG22_OUTCFG89_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72361   TIMER_OUTCFG22_OUTCFG89_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72362   TIMER_OUTCFG22_OUTCFG89_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72363   TIMER_OUTCFG22_OUTCFG89_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72364   TIMER_OUTCFG22_OUTCFG89_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72365   TIMER_OUTCFG22_OUTCFG89_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72366   TIMER_OUTCFG22_OUTCFG89_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72367   TIMER_OUTCFG22_OUTCFG89_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72368   TIMER_OUTCFG22_OUTCFG89_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72369   TIMER_OUTCFG22_OUTCFG89_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72370   TIMER_OUTCFG22_OUTCFG89_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72371   TIMER_OUTCFG22_OUTCFG89_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72372   TIMER_OUTCFG22_OUTCFG89_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72373   TIMER_OUTCFG22_OUTCFG89_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72374   TIMER_OUTCFG22_OUTCFG89_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72375   TIMER_OUTCFG22_OUTCFG89_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72376   TIMER_OUTCFG22_OUTCFG89_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72377   TIMER_OUTCFG22_OUTCFG89_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72378 } TIMER_OUTCFG22_OUTCFG89_Enum;
72379 
72380 /* ============================================  TIMER OUTCFG22 OUTCFG88 [0..5]  ============================================= */
72381 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG88                                                   */
72382   TIMER_OUTCFG22_OUTCFG88_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72383   TIMER_OUTCFG22_OUTCFG88_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72384   TIMER_OUTCFG22_OUTCFG88_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72385   TIMER_OUTCFG22_OUTCFG88_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72386   TIMER_OUTCFG22_OUTCFG88_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72387   TIMER_OUTCFG22_OUTCFG88_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72388   TIMER_OUTCFG22_OUTCFG88_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72389   TIMER_OUTCFG22_OUTCFG88_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72390   TIMER_OUTCFG22_OUTCFG88_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72391   TIMER_OUTCFG22_OUTCFG88_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72392   TIMER_OUTCFG22_OUTCFG88_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72393   TIMER_OUTCFG22_OUTCFG88_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72394   TIMER_OUTCFG22_OUTCFG88_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72395   TIMER_OUTCFG22_OUTCFG88_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72396   TIMER_OUTCFG22_OUTCFG88_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72397   TIMER_OUTCFG22_OUTCFG88_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72398   TIMER_OUTCFG22_OUTCFG88_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72399   TIMER_OUTCFG22_OUTCFG88_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72400   TIMER_OUTCFG22_OUTCFG88_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72401   TIMER_OUTCFG22_OUTCFG88_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72402   TIMER_OUTCFG22_OUTCFG88_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72403   TIMER_OUTCFG22_OUTCFG88_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72404   TIMER_OUTCFG22_OUTCFG88_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72405   TIMER_OUTCFG22_OUTCFG88_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72406   TIMER_OUTCFG22_OUTCFG88_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72407   TIMER_OUTCFG22_OUTCFG88_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72408   TIMER_OUTCFG22_OUTCFG88_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72409   TIMER_OUTCFG22_OUTCFG88_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72410   TIMER_OUTCFG22_OUTCFG88_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72411   TIMER_OUTCFG22_OUTCFG88_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72412   TIMER_OUTCFG22_OUTCFG88_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72413   TIMER_OUTCFG22_OUTCFG88_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72414   TIMER_OUTCFG22_OUTCFG88_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72415   TIMER_OUTCFG22_OUTCFG88_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72416   TIMER_OUTCFG22_OUTCFG88_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72417   TIMER_OUTCFG22_OUTCFG88_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72418   TIMER_OUTCFG22_OUTCFG88_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72419   TIMER_OUTCFG22_OUTCFG88_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72420   TIMER_OUTCFG22_OUTCFG88_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72421   TIMER_OUTCFG22_OUTCFG88_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72422   TIMER_OUTCFG22_OUTCFG88_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72423 } TIMER_OUTCFG22_OUTCFG88_Enum;
72424 
72425 /* =======================================================  OUTCFG23  ======================================================== */
72426 /* ===========================================  TIMER OUTCFG23 OUTCFG95 [24..29]  ============================================ */
72427 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG95                                                   */
72428   TIMER_OUTCFG23_OUTCFG95_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72429   TIMER_OUTCFG23_OUTCFG95_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72430   TIMER_OUTCFG23_OUTCFG95_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72431   TIMER_OUTCFG23_OUTCFG95_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72432   TIMER_OUTCFG23_OUTCFG95_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72433   TIMER_OUTCFG23_OUTCFG95_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72434   TIMER_OUTCFG23_OUTCFG95_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72435   TIMER_OUTCFG23_OUTCFG95_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72436   TIMER_OUTCFG23_OUTCFG95_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72437   TIMER_OUTCFG23_OUTCFG95_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72438   TIMER_OUTCFG23_OUTCFG95_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72439   TIMER_OUTCFG23_OUTCFG95_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72440   TIMER_OUTCFG23_OUTCFG95_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72441   TIMER_OUTCFG23_OUTCFG95_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72442   TIMER_OUTCFG23_OUTCFG95_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72443   TIMER_OUTCFG23_OUTCFG95_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72444   TIMER_OUTCFG23_OUTCFG95_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72445   TIMER_OUTCFG23_OUTCFG95_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72446   TIMER_OUTCFG23_OUTCFG95_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72447   TIMER_OUTCFG23_OUTCFG95_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72448   TIMER_OUTCFG23_OUTCFG95_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72449   TIMER_OUTCFG23_OUTCFG95_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72450   TIMER_OUTCFG23_OUTCFG95_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72451   TIMER_OUTCFG23_OUTCFG95_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72452   TIMER_OUTCFG23_OUTCFG95_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72453   TIMER_OUTCFG23_OUTCFG95_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72454   TIMER_OUTCFG23_OUTCFG95_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72455   TIMER_OUTCFG23_OUTCFG95_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72456   TIMER_OUTCFG23_OUTCFG95_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72457   TIMER_OUTCFG23_OUTCFG95_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72458   TIMER_OUTCFG23_OUTCFG95_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72459   TIMER_OUTCFG23_OUTCFG95_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72460   TIMER_OUTCFG23_OUTCFG95_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72461   TIMER_OUTCFG23_OUTCFG95_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72462   TIMER_OUTCFG23_OUTCFG95_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72463   TIMER_OUTCFG23_OUTCFG95_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72464   TIMER_OUTCFG23_OUTCFG95_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72465   TIMER_OUTCFG23_OUTCFG95_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72466   TIMER_OUTCFG23_OUTCFG95_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72467   TIMER_OUTCFG23_OUTCFG95_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72468   TIMER_OUTCFG23_OUTCFG95_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72469 } TIMER_OUTCFG23_OUTCFG95_Enum;
72470 
72471 /* ===========================================  TIMER OUTCFG23 OUTCFG94 [16..21]  ============================================ */
72472 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG94                                                   */
72473   TIMER_OUTCFG23_OUTCFG94_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72474   TIMER_OUTCFG23_OUTCFG94_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72475   TIMER_OUTCFG23_OUTCFG94_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72476   TIMER_OUTCFG23_OUTCFG94_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72477   TIMER_OUTCFG23_OUTCFG94_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72478   TIMER_OUTCFG23_OUTCFG94_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72479   TIMER_OUTCFG23_OUTCFG94_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72480   TIMER_OUTCFG23_OUTCFG94_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72481   TIMER_OUTCFG23_OUTCFG94_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72482   TIMER_OUTCFG23_OUTCFG94_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72483   TIMER_OUTCFG23_OUTCFG94_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72484   TIMER_OUTCFG23_OUTCFG94_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72485   TIMER_OUTCFG23_OUTCFG94_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72486   TIMER_OUTCFG23_OUTCFG94_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72487   TIMER_OUTCFG23_OUTCFG94_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72488   TIMER_OUTCFG23_OUTCFG94_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72489   TIMER_OUTCFG23_OUTCFG94_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72490   TIMER_OUTCFG23_OUTCFG94_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72491   TIMER_OUTCFG23_OUTCFG94_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72492   TIMER_OUTCFG23_OUTCFG94_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72493   TIMER_OUTCFG23_OUTCFG94_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72494   TIMER_OUTCFG23_OUTCFG94_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72495   TIMER_OUTCFG23_OUTCFG94_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72496   TIMER_OUTCFG23_OUTCFG94_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72497   TIMER_OUTCFG23_OUTCFG94_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72498   TIMER_OUTCFG23_OUTCFG94_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72499   TIMER_OUTCFG23_OUTCFG94_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72500   TIMER_OUTCFG23_OUTCFG94_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72501   TIMER_OUTCFG23_OUTCFG94_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72502   TIMER_OUTCFG23_OUTCFG94_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72503   TIMER_OUTCFG23_OUTCFG94_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72504   TIMER_OUTCFG23_OUTCFG94_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72505   TIMER_OUTCFG23_OUTCFG94_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72506   TIMER_OUTCFG23_OUTCFG94_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72507   TIMER_OUTCFG23_OUTCFG94_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72508   TIMER_OUTCFG23_OUTCFG94_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72509   TIMER_OUTCFG23_OUTCFG94_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72510   TIMER_OUTCFG23_OUTCFG94_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72511   TIMER_OUTCFG23_OUTCFG94_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72512   TIMER_OUTCFG23_OUTCFG94_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72513   TIMER_OUTCFG23_OUTCFG94_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72514 } TIMER_OUTCFG23_OUTCFG94_Enum;
72515 
72516 /* ============================================  TIMER OUTCFG23 OUTCFG93 [8..13]  ============================================ */
72517 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG93                                                   */
72518   TIMER_OUTCFG23_OUTCFG93_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72519   TIMER_OUTCFG23_OUTCFG93_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72520   TIMER_OUTCFG23_OUTCFG93_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72521   TIMER_OUTCFG23_OUTCFG93_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72522   TIMER_OUTCFG23_OUTCFG93_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72523   TIMER_OUTCFG23_OUTCFG93_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72524   TIMER_OUTCFG23_OUTCFG93_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72525   TIMER_OUTCFG23_OUTCFG93_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72526   TIMER_OUTCFG23_OUTCFG93_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72527   TIMER_OUTCFG23_OUTCFG93_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72528   TIMER_OUTCFG23_OUTCFG93_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72529   TIMER_OUTCFG23_OUTCFG93_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72530   TIMER_OUTCFG23_OUTCFG93_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72531   TIMER_OUTCFG23_OUTCFG93_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72532   TIMER_OUTCFG23_OUTCFG93_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72533   TIMER_OUTCFG23_OUTCFG93_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72534   TIMER_OUTCFG23_OUTCFG93_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72535   TIMER_OUTCFG23_OUTCFG93_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72536   TIMER_OUTCFG23_OUTCFG93_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72537   TIMER_OUTCFG23_OUTCFG93_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72538   TIMER_OUTCFG23_OUTCFG93_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72539   TIMER_OUTCFG23_OUTCFG93_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72540   TIMER_OUTCFG23_OUTCFG93_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72541   TIMER_OUTCFG23_OUTCFG93_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72542   TIMER_OUTCFG23_OUTCFG93_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72543   TIMER_OUTCFG23_OUTCFG93_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72544   TIMER_OUTCFG23_OUTCFG93_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72545   TIMER_OUTCFG23_OUTCFG93_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72546   TIMER_OUTCFG23_OUTCFG93_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72547   TIMER_OUTCFG23_OUTCFG93_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72548   TIMER_OUTCFG23_OUTCFG93_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72549   TIMER_OUTCFG23_OUTCFG93_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72550   TIMER_OUTCFG23_OUTCFG93_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72551   TIMER_OUTCFG23_OUTCFG93_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72552   TIMER_OUTCFG23_OUTCFG93_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72553   TIMER_OUTCFG23_OUTCFG93_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72554   TIMER_OUTCFG23_OUTCFG93_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72555   TIMER_OUTCFG23_OUTCFG93_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72556   TIMER_OUTCFG23_OUTCFG93_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72557   TIMER_OUTCFG23_OUTCFG93_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72558   TIMER_OUTCFG23_OUTCFG93_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72559 } TIMER_OUTCFG23_OUTCFG93_Enum;
72560 
72561 /* ============================================  TIMER OUTCFG23 OUTCFG92 [0..5]  ============================================= */
72562 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG92                                                   */
72563   TIMER_OUTCFG23_OUTCFG92_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72564   TIMER_OUTCFG23_OUTCFG92_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72565   TIMER_OUTCFG23_OUTCFG92_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72566   TIMER_OUTCFG23_OUTCFG92_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72567   TIMER_OUTCFG23_OUTCFG92_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72568   TIMER_OUTCFG23_OUTCFG92_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72569   TIMER_OUTCFG23_OUTCFG92_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72570   TIMER_OUTCFG23_OUTCFG92_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72571   TIMER_OUTCFG23_OUTCFG92_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72572   TIMER_OUTCFG23_OUTCFG92_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72573   TIMER_OUTCFG23_OUTCFG92_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72574   TIMER_OUTCFG23_OUTCFG92_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72575   TIMER_OUTCFG23_OUTCFG92_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72576   TIMER_OUTCFG23_OUTCFG92_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72577   TIMER_OUTCFG23_OUTCFG92_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72578   TIMER_OUTCFG23_OUTCFG92_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72579   TIMER_OUTCFG23_OUTCFG92_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72580   TIMER_OUTCFG23_OUTCFG92_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72581   TIMER_OUTCFG23_OUTCFG92_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72582   TIMER_OUTCFG23_OUTCFG92_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72583   TIMER_OUTCFG23_OUTCFG92_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72584   TIMER_OUTCFG23_OUTCFG92_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72585   TIMER_OUTCFG23_OUTCFG92_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72586   TIMER_OUTCFG23_OUTCFG92_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72587   TIMER_OUTCFG23_OUTCFG92_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72588   TIMER_OUTCFG23_OUTCFG92_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72589   TIMER_OUTCFG23_OUTCFG92_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72590   TIMER_OUTCFG23_OUTCFG92_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72591   TIMER_OUTCFG23_OUTCFG92_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72592   TIMER_OUTCFG23_OUTCFG92_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72593   TIMER_OUTCFG23_OUTCFG92_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72594   TIMER_OUTCFG23_OUTCFG92_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72595   TIMER_OUTCFG23_OUTCFG92_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72596   TIMER_OUTCFG23_OUTCFG92_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72597   TIMER_OUTCFG23_OUTCFG92_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72598   TIMER_OUTCFG23_OUTCFG92_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72599   TIMER_OUTCFG23_OUTCFG92_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72600   TIMER_OUTCFG23_OUTCFG92_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72601   TIMER_OUTCFG23_OUTCFG92_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72602   TIMER_OUTCFG23_OUTCFG92_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72603   TIMER_OUTCFG23_OUTCFG92_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72604 } TIMER_OUTCFG23_OUTCFG92_Enum;
72605 
72606 /* =======================================================  OUTCFG24  ======================================================== */
72607 /* ===========================================  TIMER OUTCFG24 OUTCFG99 [24..29]  ============================================ */
72608 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG99                                                   */
72609   TIMER_OUTCFG24_OUTCFG99_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72610   TIMER_OUTCFG24_OUTCFG99_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72611   TIMER_OUTCFG24_OUTCFG99_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72612   TIMER_OUTCFG24_OUTCFG99_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72613   TIMER_OUTCFG24_OUTCFG99_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72614   TIMER_OUTCFG24_OUTCFG99_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72615   TIMER_OUTCFG24_OUTCFG99_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72616   TIMER_OUTCFG24_OUTCFG99_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72617   TIMER_OUTCFG24_OUTCFG99_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72618   TIMER_OUTCFG24_OUTCFG99_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72619   TIMER_OUTCFG24_OUTCFG99_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72620   TIMER_OUTCFG24_OUTCFG99_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72621   TIMER_OUTCFG24_OUTCFG99_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72622   TIMER_OUTCFG24_OUTCFG99_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72623   TIMER_OUTCFG24_OUTCFG99_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72624   TIMER_OUTCFG24_OUTCFG99_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72625   TIMER_OUTCFG24_OUTCFG99_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72626   TIMER_OUTCFG24_OUTCFG99_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72627   TIMER_OUTCFG24_OUTCFG99_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72628   TIMER_OUTCFG24_OUTCFG99_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72629   TIMER_OUTCFG24_OUTCFG99_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72630   TIMER_OUTCFG24_OUTCFG99_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72631   TIMER_OUTCFG24_OUTCFG99_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72632   TIMER_OUTCFG24_OUTCFG99_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72633   TIMER_OUTCFG24_OUTCFG99_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72634   TIMER_OUTCFG24_OUTCFG99_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72635   TIMER_OUTCFG24_OUTCFG99_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72636   TIMER_OUTCFG24_OUTCFG99_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72637   TIMER_OUTCFG24_OUTCFG99_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72638   TIMER_OUTCFG24_OUTCFG99_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72639   TIMER_OUTCFG24_OUTCFG99_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72640   TIMER_OUTCFG24_OUTCFG99_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72641   TIMER_OUTCFG24_OUTCFG99_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72642   TIMER_OUTCFG24_OUTCFG99_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72643   TIMER_OUTCFG24_OUTCFG99_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72644   TIMER_OUTCFG24_OUTCFG99_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72645   TIMER_OUTCFG24_OUTCFG99_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72646   TIMER_OUTCFG24_OUTCFG99_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72647   TIMER_OUTCFG24_OUTCFG99_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72648   TIMER_OUTCFG24_OUTCFG99_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72649   TIMER_OUTCFG24_OUTCFG99_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72650 } TIMER_OUTCFG24_OUTCFG99_Enum;
72651 
72652 /* ===========================================  TIMER OUTCFG24 OUTCFG98 [16..21]  ============================================ */
72653 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG98                                                   */
72654   TIMER_OUTCFG24_OUTCFG98_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72655   TIMER_OUTCFG24_OUTCFG98_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72656   TIMER_OUTCFG24_OUTCFG98_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72657   TIMER_OUTCFG24_OUTCFG98_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72658   TIMER_OUTCFG24_OUTCFG98_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72659   TIMER_OUTCFG24_OUTCFG98_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72660   TIMER_OUTCFG24_OUTCFG98_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72661   TIMER_OUTCFG24_OUTCFG98_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72662   TIMER_OUTCFG24_OUTCFG98_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72663   TIMER_OUTCFG24_OUTCFG98_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72664   TIMER_OUTCFG24_OUTCFG98_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72665   TIMER_OUTCFG24_OUTCFG98_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72666   TIMER_OUTCFG24_OUTCFG98_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72667   TIMER_OUTCFG24_OUTCFG98_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72668   TIMER_OUTCFG24_OUTCFG98_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72669   TIMER_OUTCFG24_OUTCFG98_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72670   TIMER_OUTCFG24_OUTCFG98_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72671   TIMER_OUTCFG24_OUTCFG98_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72672   TIMER_OUTCFG24_OUTCFG98_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72673   TIMER_OUTCFG24_OUTCFG98_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72674   TIMER_OUTCFG24_OUTCFG98_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72675   TIMER_OUTCFG24_OUTCFG98_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72676   TIMER_OUTCFG24_OUTCFG98_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72677   TIMER_OUTCFG24_OUTCFG98_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72678   TIMER_OUTCFG24_OUTCFG98_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72679   TIMER_OUTCFG24_OUTCFG98_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72680   TIMER_OUTCFG24_OUTCFG98_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72681   TIMER_OUTCFG24_OUTCFG98_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72682   TIMER_OUTCFG24_OUTCFG98_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72683   TIMER_OUTCFG24_OUTCFG98_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72684   TIMER_OUTCFG24_OUTCFG98_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72685   TIMER_OUTCFG24_OUTCFG98_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72686   TIMER_OUTCFG24_OUTCFG98_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72687   TIMER_OUTCFG24_OUTCFG98_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72688   TIMER_OUTCFG24_OUTCFG98_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72689   TIMER_OUTCFG24_OUTCFG98_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72690   TIMER_OUTCFG24_OUTCFG98_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72691   TIMER_OUTCFG24_OUTCFG98_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72692   TIMER_OUTCFG24_OUTCFG98_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72693   TIMER_OUTCFG24_OUTCFG98_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72694   TIMER_OUTCFG24_OUTCFG98_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72695 } TIMER_OUTCFG24_OUTCFG98_Enum;
72696 
72697 /* ============================================  TIMER OUTCFG24 OUTCFG97 [8..13]  ============================================ */
72698 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG97                                                   */
72699   TIMER_OUTCFG24_OUTCFG97_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72700   TIMER_OUTCFG24_OUTCFG97_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72701   TIMER_OUTCFG24_OUTCFG97_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72702   TIMER_OUTCFG24_OUTCFG97_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72703   TIMER_OUTCFG24_OUTCFG97_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72704   TIMER_OUTCFG24_OUTCFG97_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72705   TIMER_OUTCFG24_OUTCFG97_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72706   TIMER_OUTCFG24_OUTCFG97_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72707   TIMER_OUTCFG24_OUTCFG97_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72708   TIMER_OUTCFG24_OUTCFG97_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72709   TIMER_OUTCFG24_OUTCFG97_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72710   TIMER_OUTCFG24_OUTCFG97_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72711   TIMER_OUTCFG24_OUTCFG97_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72712   TIMER_OUTCFG24_OUTCFG97_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72713   TIMER_OUTCFG24_OUTCFG97_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72714   TIMER_OUTCFG24_OUTCFG97_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72715   TIMER_OUTCFG24_OUTCFG97_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72716   TIMER_OUTCFG24_OUTCFG97_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72717   TIMER_OUTCFG24_OUTCFG97_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72718   TIMER_OUTCFG24_OUTCFG97_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72719   TIMER_OUTCFG24_OUTCFG97_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72720   TIMER_OUTCFG24_OUTCFG97_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72721   TIMER_OUTCFG24_OUTCFG97_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72722   TIMER_OUTCFG24_OUTCFG97_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72723   TIMER_OUTCFG24_OUTCFG97_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72724   TIMER_OUTCFG24_OUTCFG97_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72725   TIMER_OUTCFG24_OUTCFG97_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72726   TIMER_OUTCFG24_OUTCFG97_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72727   TIMER_OUTCFG24_OUTCFG97_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72728   TIMER_OUTCFG24_OUTCFG97_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72729   TIMER_OUTCFG24_OUTCFG97_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72730   TIMER_OUTCFG24_OUTCFG97_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72731   TIMER_OUTCFG24_OUTCFG97_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72732   TIMER_OUTCFG24_OUTCFG97_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72733   TIMER_OUTCFG24_OUTCFG97_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72734   TIMER_OUTCFG24_OUTCFG97_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72735   TIMER_OUTCFG24_OUTCFG97_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72736   TIMER_OUTCFG24_OUTCFG97_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72737   TIMER_OUTCFG24_OUTCFG97_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72738   TIMER_OUTCFG24_OUTCFG97_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72739   TIMER_OUTCFG24_OUTCFG97_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72740 } TIMER_OUTCFG24_OUTCFG97_Enum;
72741 
72742 /* ============================================  TIMER OUTCFG24 OUTCFG96 [0..5]  ============================================= */
72743 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG96                                                   */
72744   TIMER_OUTCFG24_OUTCFG96_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72745   TIMER_OUTCFG24_OUTCFG96_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72746   TIMER_OUTCFG24_OUTCFG96_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72747   TIMER_OUTCFG24_OUTCFG96_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72748   TIMER_OUTCFG24_OUTCFG96_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72749   TIMER_OUTCFG24_OUTCFG96_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72750   TIMER_OUTCFG24_OUTCFG96_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72751   TIMER_OUTCFG24_OUTCFG96_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72752   TIMER_OUTCFG24_OUTCFG96_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72753   TIMER_OUTCFG24_OUTCFG96_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72754   TIMER_OUTCFG24_OUTCFG96_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72755   TIMER_OUTCFG24_OUTCFG96_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72756   TIMER_OUTCFG24_OUTCFG96_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72757   TIMER_OUTCFG24_OUTCFG96_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72758   TIMER_OUTCFG24_OUTCFG96_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72759   TIMER_OUTCFG24_OUTCFG96_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72760   TIMER_OUTCFG24_OUTCFG96_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72761   TIMER_OUTCFG24_OUTCFG96_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72762   TIMER_OUTCFG24_OUTCFG96_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72763   TIMER_OUTCFG24_OUTCFG96_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72764   TIMER_OUTCFG24_OUTCFG96_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72765   TIMER_OUTCFG24_OUTCFG96_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72766   TIMER_OUTCFG24_OUTCFG96_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72767   TIMER_OUTCFG24_OUTCFG96_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72768   TIMER_OUTCFG24_OUTCFG96_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72769   TIMER_OUTCFG24_OUTCFG96_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72770   TIMER_OUTCFG24_OUTCFG96_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72771   TIMER_OUTCFG24_OUTCFG96_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72772   TIMER_OUTCFG24_OUTCFG96_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72773   TIMER_OUTCFG24_OUTCFG96_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72774   TIMER_OUTCFG24_OUTCFG96_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72775   TIMER_OUTCFG24_OUTCFG96_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72776   TIMER_OUTCFG24_OUTCFG96_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72777   TIMER_OUTCFG24_OUTCFG96_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72778   TIMER_OUTCFG24_OUTCFG96_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72779   TIMER_OUTCFG24_OUTCFG96_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72780   TIMER_OUTCFG24_OUTCFG96_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72781   TIMER_OUTCFG24_OUTCFG96_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72782   TIMER_OUTCFG24_OUTCFG96_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72783   TIMER_OUTCFG24_OUTCFG96_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72784   TIMER_OUTCFG24_OUTCFG96_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72785 } TIMER_OUTCFG24_OUTCFG96_Enum;
72786 
72787 /* =======================================================  OUTCFG25  ======================================================== */
72788 /* ===========================================  TIMER OUTCFG25 OUTCFG103 [24..29]  =========================================== */
72789 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG103                                                  */
72790   TIMER_OUTCFG25_OUTCFG103_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72791   TIMER_OUTCFG25_OUTCFG103_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72792   TIMER_OUTCFG25_OUTCFG103_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72793   TIMER_OUTCFG25_OUTCFG103_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72794   TIMER_OUTCFG25_OUTCFG103_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72795   TIMER_OUTCFG25_OUTCFG103_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72796   TIMER_OUTCFG25_OUTCFG103_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72797   TIMER_OUTCFG25_OUTCFG103_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72798   TIMER_OUTCFG25_OUTCFG103_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72799   TIMER_OUTCFG25_OUTCFG103_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72800   TIMER_OUTCFG25_OUTCFG103_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72801   TIMER_OUTCFG25_OUTCFG103_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72802   TIMER_OUTCFG25_OUTCFG103_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72803   TIMER_OUTCFG25_OUTCFG103_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72804   TIMER_OUTCFG25_OUTCFG103_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72805   TIMER_OUTCFG25_OUTCFG103_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72806   TIMER_OUTCFG25_OUTCFG103_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72807   TIMER_OUTCFG25_OUTCFG103_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72808   TIMER_OUTCFG25_OUTCFG103_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72809   TIMER_OUTCFG25_OUTCFG103_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72810   TIMER_OUTCFG25_OUTCFG103_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72811   TIMER_OUTCFG25_OUTCFG103_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72812   TIMER_OUTCFG25_OUTCFG103_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72813   TIMER_OUTCFG25_OUTCFG103_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72814   TIMER_OUTCFG25_OUTCFG103_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72815   TIMER_OUTCFG25_OUTCFG103_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72816   TIMER_OUTCFG25_OUTCFG103_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72817   TIMER_OUTCFG25_OUTCFG103_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72818   TIMER_OUTCFG25_OUTCFG103_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72819   TIMER_OUTCFG25_OUTCFG103_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72820   TIMER_OUTCFG25_OUTCFG103_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72821   TIMER_OUTCFG25_OUTCFG103_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72822   TIMER_OUTCFG25_OUTCFG103_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72823   TIMER_OUTCFG25_OUTCFG103_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72824   TIMER_OUTCFG25_OUTCFG103_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72825   TIMER_OUTCFG25_OUTCFG103_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72826   TIMER_OUTCFG25_OUTCFG103_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72827   TIMER_OUTCFG25_OUTCFG103_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72828   TIMER_OUTCFG25_OUTCFG103_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72829   TIMER_OUTCFG25_OUTCFG103_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72830   TIMER_OUTCFG25_OUTCFG103_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
72831 } TIMER_OUTCFG25_OUTCFG103_Enum;
72832 
72833 /* ===========================================  TIMER OUTCFG25 OUTCFG102 [16..21]  =========================================== */
72834 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG102                                                  */
72835   TIMER_OUTCFG25_OUTCFG102_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72836   TIMER_OUTCFG25_OUTCFG102_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72837   TIMER_OUTCFG25_OUTCFG102_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72838   TIMER_OUTCFG25_OUTCFG102_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72839   TIMER_OUTCFG25_OUTCFG102_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72840   TIMER_OUTCFG25_OUTCFG102_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72841   TIMER_OUTCFG25_OUTCFG102_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72842   TIMER_OUTCFG25_OUTCFG102_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72843   TIMER_OUTCFG25_OUTCFG102_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72844   TIMER_OUTCFG25_OUTCFG102_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72845   TIMER_OUTCFG25_OUTCFG102_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72846   TIMER_OUTCFG25_OUTCFG102_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72847   TIMER_OUTCFG25_OUTCFG102_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72848   TIMER_OUTCFG25_OUTCFG102_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72849   TIMER_OUTCFG25_OUTCFG102_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72850   TIMER_OUTCFG25_OUTCFG102_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72851   TIMER_OUTCFG25_OUTCFG102_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72852   TIMER_OUTCFG25_OUTCFG102_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72853   TIMER_OUTCFG25_OUTCFG102_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72854   TIMER_OUTCFG25_OUTCFG102_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72855   TIMER_OUTCFG25_OUTCFG102_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72856   TIMER_OUTCFG25_OUTCFG102_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72857   TIMER_OUTCFG25_OUTCFG102_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72858   TIMER_OUTCFG25_OUTCFG102_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72859   TIMER_OUTCFG25_OUTCFG102_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72860   TIMER_OUTCFG25_OUTCFG102_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72861   TIMER_OUTCFG25_OUTCFG102_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72862   TIMER_OUTCFG25_OUTCFG102_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72863   TIMER_OUTCFG25_OUTCFG102_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72864   TIMER_OUTCFG25_OUTCFG102_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72865   TIMER_OUTCFG25_OUTCFG102_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72866   TIMER_OUTCFG25_OUTCFG102_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72867   TIMER_OUTCFG25_OUTCFG102_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72868   TIMER_OUTCFG25_OUTCFG102_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72869   TIMER_OUTCFG25_OUTCFG102_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72870   TIMER_OUTCFG25_OUTCFG102_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72871   TIMER_OUTCFG25_OUTCFG102_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72872   TIMER_OUTCFG25_OUTCFG102_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72873   TIMER_OUTCFG25_OUTCFG102_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72874   TIMER_OUTCFG25_OUTCFG102_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72875   TIMER_OUTCFG25_OUTCFG102_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
72876 } TIMER_OUTCFG25_OUTCFG102_Enum;
72877 
72878 /* ===========================================  TIMER OUTCFG25 OUTCFG101 [8..13]  ============================================ */
72879 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG101                                                  */
72880   TIMER_OUTCFG25_OUTCFG101_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72881   TIMER_OUTCFG25_OUTCFG101_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72882   TIMER_OUTCFG25_OUTCFG101_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72883   TIMER_OUTCFG25_OUTCFG101_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72884   TIMER_OUTCFG25_OUTCFG101_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72885   TIMER_OUTCFG25_OUTCFG101_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72886   TIMER_OUTCFG25_OUTCFG101_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72887   TIMER_OUTCFG25_OUTCFG101_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72888   TIMER_OUTCFG25_OUTCFG101_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72889   TIMER_OUTCFG25_OUTCFG101_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72890   TIMER_OUTCFG25_OUTCFG101_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72891   TIMER_OUTCFG25_OUTCFG101_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72892   TIMER_OUTCFG25_OUTCFG101_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72893   TIMER_OUTCFG25_OUTCFG101_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72894   TIMER_OUTCFG25_OUTCFG101_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72895   TIMER_OUTCFG25_OUTCFG101_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72896   TIMER_OUTCFG25_OUTCFG101_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72897   TIMER_OUTCFG25_OUTCFG101_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72898   TIMER_OUTCFG25_OUTCFG101_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72899   TIMER_OUTCFG25_OUTCFG101_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72900   TIMER_OUTCFG25_OUTCFG101_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72901   TIMER_OUTCFG25_OUTCFG101_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72902   TIMER_OUTCFG25_OUTCFG101_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72903   TIMER_OUTCFG25_OUTCFG101_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72904   TIMER_OUTCFG25_OUTCFG101_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72905   TIMER_OUTCFG25_OUTCFG101_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72906   TIMER_OUTCFG25_OUTCFG101_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72907   TIMER_OUTCFG25_OUTCFG101_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72908   TIMER_OUTCFG25_OUTCFG101_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72909   TIMER_OUTCFG25_OUTCFG101_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72910   TIMER_OUTCFG25_OUTCFG101_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72911   TIMER_OUTCFG25_OUTCFG101_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72912   TIMER_OUTCFG25_OUTCFG101_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72913   TIMER_OUTCFG25_OUTCFG101_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72914   TIMER_OUTCFG25_OUTCFG101_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72915   TIMER_OUTCFG25_OUTCFG101_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72916   TIMER_OUTCFG25_OUTCFG101_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72917   TIMER_OUTCFG25_OUTCFG101_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72918   TIMER_OUTCFG25_OUTCFG101_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72919   TIMER_OUTCFG25_OUTCFG101_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72920   TIMER_OUTCFG25_OUTCFG101_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
72921 } TIMER_OUTCFG25_OUTCFG101_Enum;
72922 
72923 /* ============================================  TIMER OUTCFG25 OUTCFG100 [0..5]  ============================================ */
72924 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG100                                                  */
72925   TIMER_OUTCFG25_OUTCFG100_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72926   TIMER_OUTCFG25_OUTCFG100_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72927   TIMER_OUTCFG25_OUTCFG100_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72928   TIMER_OUTCFG25_OUTCFG100_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72929   TIMER_OUTCFG25_OUTCFG100_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72930   TIMER_OUTCFG25_OUTCFG100_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72931   TIMER_OUTCFG25_OUTCFG100_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72932   TIMER_OUTCFG25_OUTCFG100_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72933   TIMER_OUTCFG25_OUTCFG100_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72934   TIMER_OUTCFG25_OUTCFG100_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72935   TIMER_OUTCFG25_OUTCFG100_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72936   TIMER_OUTCFG25_OUTCFG100_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72937   TIMER_OUTCFG25_OUTCFG100_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72938   TIMER_OUTCFG25_OUTCFG100_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72939   TIMER_OUTCFG25_OUTCFG100_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72940   TIMER_OUTCFG25_OUTCFG100_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72941   TIMER_OUTCFG25_OUTCFG100_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72942   TIMER_OUTCFG25_OUTCFG100_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72943   TIMER_OUTCFG25_OUTCFG100_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72944   TIMER_OUTCFG25_OUTCFG100_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72945   TIMER_OUTCFG25_OUTCFG100_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72946   TIMER_OUTCFG25_OUTCFG100_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72947   TIMER_OUTCFG25_OUTCFG100_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72948   TIMER_OUTCFG25_OUTCFG100_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72949   TIMER_OUTCFG25_OUTCFG100_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72950   TIMER_OUTCFG25_OUTCFG100_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72951   TIMER_OUTCFG25_OUTCFG100_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72952   TIMER_OUTCFG25_OUTCFG100_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72953   TIMER_OUTCFG25_OUTCFG100_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72954   TIMER_OUTCFG25_OUTCFG100_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72955   TIMER_OUTCFG25_OUTCFG100_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72956   TIMER_OUTCFG25_OUTCFG100_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72957   TIMER_OUTCFG25_OUTCFG100_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72958   TIMER_OUTCFG25_OUTCFG100_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72959   TIMER_OUTCFG25_OUTCFG100_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72960   TIMER_OUTCFG25_OUTCFG100_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72961   TIMER_OUTCFG25_OUTCFG100_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72962   TIMER_OUTCFG25_OUTCFG100_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72963   TIMER_OUTCFG25_OUTCFG100_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72964   TIMER_OUTCFG25_OUTCFG100_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72965   TIMER_OUTCFG25_OUTCFG100_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
72966 } TIMER_OUTCFG25_OUTCFG100_Enum;
72967 
72968 /* =======================================================  OUTCFG26  ======================================================== */
72969 /* ===========================================  TIMER OUTCFG26 OUTCFG107 [24..29]  =========================================== */
72970 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG107                                                  */
72971   TIMER_OUTCFG26_OUTCFG107_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72972   TIMER_OUTCFG26_OUTCFG107_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72973   TIMER_OUTCFG26_OUTCFG107_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72974   TIMER_OUTCFG26_OUTCFG107_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72975   TIMER_OUTCFG26_OUTCFG107_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72976   TIMER_OUTCFG26_OUTCFG107_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72977   TIMER_OUTCFG26_OUTCFG107_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72978   TIMER_OUTCFG26_OUTCFG107_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72979   TIMER_OUTCFG26_OUTCFG107_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72980   TIMER_OUTCFG26_OUTCFG107_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72981   TIMER_OUTCFG26_OUTCFG107_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72982   TIMER_OUTCFG26_OUTCFG107_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72983   TIMER_OUTCFG26_OUTCFG107_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72984   TIMER_OUTCFG26_OUTCFG107_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72985   TIMER_OUTCFG26_OUTCFG107_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72986   TIMER_OUTCFG26_OUTCFG107_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72987   TIMER_OUTCFG26_OUTCFG107_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72988   TIMER_OUTCFG26_OUTCFG107_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72989   TIMER_OUTCFG26_OUTCFG107_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72990   TIMER_OUTCFG26_OUTCFG107_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72991   TIMER_OUTCFG26_OUTCFG107_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72992   TIMER_OUTCFG26_OUTCFG107_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72993   TIMER_OUTCFG26_OUTCFG107_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72994   TIMER_OUTCFG26_OUTCFG107_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72995   TIMER_OUTCFG26_OUTCFG107_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72996   TIMER_OUTCFG26_OUTCFG107_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72997   TIMER_OUTCFG26_OUTCFG107_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72998   TIMER_OUTCFG26_OUTCFG107_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72999   TIMER_OUTCFG26_OUTCFG107_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73000   TIMER_OUTCFG26_OUTCFG107_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73001   TIMER_OUTCFG26_OUTCFG107_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73002   TIMER_OUTCFG26_OUTCFG107_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73003   TIMER_OUTCFG26_OUTCFG107_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73004   TIMER_OUTCFG26_OUTCFG107_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73005   TIMER_OUTCFG26_OUTCFG107_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73006   TIMER_OUTCFG26_OUTCFG107_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73007   TIMER_OUTCFG26_OUTCFG107_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73008   TIMER_OUTCFG26_OUTCFG107_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73009   TIMER_OUTCFG26_OUTCFG107_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73010   TIMER_OUTCFG26_OUTCFG107_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73011   TIMER_OUTCFG26_OUTCFG107_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73012 } TIMER_OUTCFG26_OUTCFG107_Enum;
73013 
73014 /* ===========================================  TIMER OUTCFG26 OUTCFG106 [16..21]  =========================================== */
73015 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG106                                                  */
73016   TIMER_OUTCFG26_OUTCFG106_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73017   TIMER_OUTCFG26_OUTCFG106_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73018   TIMER_OUTCFG26_OUTCFG106_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73019   TIMER_OUTCFG26_OUTCFG106_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73020   TIMER_OUTCFG26_OUTCFG106_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73021   TIMER_OUTCFG26_OUTCFG106_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73022   TIMER_OUTCFG26_OUTCFG106_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73023   TIMER_OUTCFG26_OUTCFG106_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73024   TIMER_OUTCFG26_OUTCFG106_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73025   TIMER_OUTCFG26_OUTCFG106_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73026   TIMER_OUTCFG26_OUTCFG106_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73027   TIMER_OUTCFG26_OUTCFG106_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73028   TIMER_OUTCFG26_OUTCFG106_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73029   TIMER_OUTCFG26_OUTCFG106_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73030   TIMER_OUTCFG26_OUTCFG106_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73031   TIMER_OUTCFG26_OUTCFG106_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73032   TIMER_OUTCFG26_OUTCFG106_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73033   TIMER_OUTCFG26_OUTCFG106_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73034   TIMER_OUTCFG26_OUTCFG106_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73035   TIMER_OUTCFG26_OUTCFG106_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73036   TIMER_OUTCFG26_OUTCFG106_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73037   TIMER_OUTCFG26_OUTCFG106_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73038   TIMER_OUTCFG26_OUTCFG106_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73039   TIMER_OUTCFG26_OUTCFG106_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73040   TIMER_OUTCFG26_OUTCFG106_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73041   TIMER_OUTCFG26_OUTCFG106_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73042   TIMER_OUTCFG26_OUTCFG106_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73043   TIMER_OUTCFG26_OUTCFG106_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73044   TIMER_OUTCFG26_OUTCFG106_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73045   TIMER_OUTCFG26_OUTCFG106_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73046   TIMER_OUTCFG26_OUTCFG106_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73047   TIMER_OUTCFG26_OUTCFG106_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73048   TIMER_OUTCFG26_OUTCFG106_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73049   TIMER_OUTCFG26_OUTCFG106_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73050   TIMER_OUTCFG26_OUTCFG106_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73051   TIMER_OUTCFG26_OUTCFG106_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73052   TIMER_OUTCFG26_OUTCFG106_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73053   TIMER_OUTCFG26_OUTCFG106_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73054   TIMER_OUTCFG26_OUTCFG106_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73055   TIMER_OUTCFG26_OUTCFG106_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73056   TIMER_OUTCFG26_OUTCFG106_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73057 } TIMER_OUTCFG26_OUTCFG106_Enum;
73058 
73059 /* ===========================================  TIMER OUTCFG26 OUTCFG105 [8..13]  ============================================ */
73060 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG105                                                  */
73061   TIMER_OUTCFG26_OUTCFG105_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73062   TIMER_OUTCFG26_OUTCFG105_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73063   TIMER_OUTCFG26_OUTCFG105_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73064   TIMER_OUTCFG26_OUTCFG105_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73065   TIMER_OUTCFG26_OUTCFG105_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73066   TIMER_OUTCFG26_OUTCFG105_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73067   TIMER_OUTCFG26_OUTCFG105_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73068   TIMER_OUTCFG26_OUTCFG105_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73069   TIMER_OUTCFG26_OUTCFG105_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73070   TIMER_OUTCFG26_OUTCFG105_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73071   TIMER_OUTCFG26_OUTCFG105_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73072   TIMER_OUTCFG26_OUTCFG105_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73073   TIMER_OUTCFG26_OUTCFG105_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73074   TIMER_OUTCFG26_OUTCFG105_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73075   TIMER_OUTCFG26_OUTCFG105_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73076   TIMER_OUTCFG26_OUTCFG105_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73077   TIMER_OUTCFG26_OUTCFG105_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73078   TIMER_OUTCFG26_OUTCFG105_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73079   TIMER_OUTCFG26_OUTCFG105_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73080   TIMER_OUTCFG26_OUTCFG105_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73081   TIMER_OUTCFG26_OUTCFG105_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73082   TIMER_OUTCFG26_OUTCFG105_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73083   TIMER_OUTCFG26_OUTCFG105_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73084   TIMER_OUTCFG26_OUTCFG105_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73085   TIMER_OUTCFG26_OUTCFG105_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73086   TIMER_OUTCFG26_OUTCFG105_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73087   TIMER_OUTCFG26_OUTCFG105_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73088   TIMER_OUTCFG26_OUTCFG105_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73089   TIMER_OUTCFG26_OUTCFG105_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73090   TIMER_OUTCFG26_OUTCFG105_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73091   TIMER_OUTCFG26_OUTCFG105_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73092   TIMER_OUTCFG26_OUTCFG105_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73093   TIMER_OUTCFG26_OUTCFG105_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73094   TIMER_OUTCFG26_OUTCFG105_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73095   TIMER_OUTCFG26_OUTCFG105_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73096   TIMER_OUTCFG26_OUTCFG105_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73097   TIMER_OUTCFG26_OUTCFG105_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73098   TIMER_OUTCFG26_OUTCFG105_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73099   TIMER_OUTCFG26_OUTCFG105_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73100   TIMER_OUTCFG26_OUTCFG105_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73101   TIMER_OUTCFG26_OUTCFG105_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73102 } TIMER_OUTCFG26_OUTCFG105_Enum;
73103 
73104 /* ============================================  TIMER OUTCFG26 OUTCFG104 [0..5]  ============================================ */
73105 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG104                                                  */
73106   TIMER_OUTCFG26_OUTCFG104_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73107   TIMER_OUTCFG26_OUTCFG104_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73108   TIMER_OUTCFG26_OUTCFG104_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73109   TIMER_OUTCFG26_OUTCFG104_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73110   TIMER_OUTCFG26_OUTCFG104_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73111   TIMER_OUTCFG26_OUTCFG104_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73112   TIMER_OUTCFG26_OUTCFG104_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73113   TIMER_OUTCFG26_OUTCFG104_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73114   TIMER_OUTCFG26_OUTCFG104_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73115   TIMER_OUTCFG26_OUTCFG104_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73116   TIMER_OUTCFG26_OUTCFG104_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73117   TIMER_OUTCFG26_OUTCFG104_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73118   TIMER_OUTCFG26_OUTCFG104_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73119   TIMER_OUTCFG26_OUTCFG104_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73120   TIMER_OUTCFG26_OUTCFG104_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73121   TIMER_OUTCFG26_OUTCFG104_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73122   TIMER_OUTCFG26_OUTCFG104_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73123   TIMER_OUTCFG26_OUTCFG104_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73124   TIMER_OUTCFG26_OUTCFG104_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73125   TIMER_OUTCFG26_OUTCFG104_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73126   TIMER_OUTCFG26_OUTCFG104_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73127   TIMER_OUTCFG26_OUTCFG104_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73128   TIMER_OUTCFG26_OUTCFG104_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73129   TIMER_OUTCFG26_OUTCFG104_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73130   TIMER_OUTCFG26_OUTCFG104_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73131   TIMER_OUTCFG26_OUTCFG104_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73132   TIMER_OUTCFG26_OUTCFG104_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73133   TIMER_OUTCFG26_OUTCFG104_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73134   TIMER_OUTCFG26_OUTCFG104_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73135   TIMER_OUTCFG26_OUTCFG104_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73136   TIMER_OUTCFG26_OUTCFG104_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73137   TIMER_OUTCFG26_OUTCFG104_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73138   TIMER_OUTCFG26_OUTCFG104_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73139   TIMER_OUTCFG26_OUTCFG104_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73140   TIMER_OUTCFG26_OUTCFG104_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73141   TIMER_OUTCFG26_OUTCFG104_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73142   TIMER_OUTCFG26_OUTCFG104_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73143   TIMER_OUTCFG26_OUTCFG104_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73144   TIMER_OUTCFG26_OUTCFG104_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73145   TIMER_OUTCFG26_OUTCFG104_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73146   TIMER_OUTCFG26_OUTCFG104_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73147 } TIMER_OUTCFG26_OUTCFG104_Enum;
73148 
73149 /* =======================================================  OUTCFG27  ======================================================== */
73150 /* ===========================================  TIMER OUTCFG27 OUTCFG111 [24..29]  =========================================== */
73151 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG111                                                  */
73152   TIMER_OUTCFG27_OUTCFG111_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73153   TIMER_OUTCFG27_OUTCFG111_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73154   TIMER_OUTCFG27_OUTCFG111_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73155   TIMER_OUTCFG27_OUTCFG111_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73156   TIMER_OUTCFG27_OUTCFG111_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73157   TIMER_OUTCFG27_OUTCFG111_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73158   TIMER_OUTCFG27_OUTCFG111_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73159   TIMER_OUTCFG27_OUTCFG111_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73160   TIMER_OUTCFG27_OUTCFG111_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73161   TIMER_OUTCFG27_OUTCFG111_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73162   TIMER_OUTCFG27_OUTCFG111_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73163   TIMER_OUTCFG27_OUTCFG111_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73164   TIMER_OUTCFG27_OUTCFG111_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73165   TIMER_OUTCFG27_OUTCFG111_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73166   TIMER_OUTCFG27_OUTCFG111_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73167   TIMER_OUTCFG27_OUTCFG111_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73168   TIMER_OUTCFG27_OUTCFG111_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73169   TIMER_OUTCFG27_OUTCFG111_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73170   TIMER_OUTCFG27_OUTCFG111_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73171   TIMER_OUTCFG27_OUTCFG111_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73172   TIMER_OUTCFG27_OUTCFG111_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73173   TIMER_OUTCFG27_OUTCFG111_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73174   TIMER_OUTCFG27_OUTCFG111_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73175   TIMER_OUTCFG27_OUTCFG111_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73176   TIMER_OUTCFG27_OUTCFG111_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73177   TIMER_OUTCFG27_OUTCFG111_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73178   TIMER_OUTCFG27_OUTCFG111_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73179   TIMER_OUTCFG27_OUTCFG111_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73180   TIMER_OUTCFG27_OUTCFG111_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73181   TIMER_OUTCFG27_OUTCFG111_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73182   TIMER_OUTCFG27_OUTCFG111_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73183   TIMER_OUTCFG27_OUTCFG111_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73184   TIMER_OUTCFG27_OUTCFG111_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73185   TIMER_OUTCFG27_OUTCFG111_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73186   TIMER_OUTCFG27_OUTCFG111_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73187   TIMER_OUTCFG27_OUTCFG111_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73188   TIMER_OUTCFG27_OUTCFG111_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73189   TIMER_OUTCFG27_OUTCFG111_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73190   TIMER_OUTCFG27_OUTCFG111_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73191   TIMER_OUTCFG27_OUTCFG111_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73192   TIMER_OUTCFG27_OUTCFG111_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73193 } TIMER_OUTCFG27_OUTCFG111_Enum;
73194 
73195 /* ===========================================  TIMER OUTCFG27 OUTCFG110 [16..21]  =========================================== */
73196 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG110                                                  */
73197   TIMER_OUTCFG27_OUTCFG110_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73198   TIMER_OUTCFG27_OUTCFG110_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73199   TIMER_OUTCFG27_OUTCFG110_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73200   TIMER_OUTCFG27_OUTCFG110_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73201   TIMER_OUTCFG27_OUTCFG110_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73202   TIMER_OUTCFG27_OUTCFG110_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73203   TIMER_OUTCFG27_OUTCFG110_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73204   TIMER_OUTCFG27_OUTCFG110_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73205   TIMER_OUTCFG27_OUTCFG110_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73206   TIMER_OUTCFG27_OUTCFG110_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73207   TIMER_OUTCFG27_OUTCFG110_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73208   TIMER_OUTCFG27_OUTCFG110_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73209   TIMER_OUTCFG27_OUTCFG110_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73210   TIMER_OUTCFG27_OUTCFG110_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73211   TIMER_OUTCFG27_OUTCFG110_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73212   TIMER_OUTCFG27_OUTCFG110_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73213   TIMER_OUTCFG27_OUTCFG110_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73214   TIMER_OUTCFG27_OUTCFG110_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73215   TIMER_OUTCFG27_OUTCFG110_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73216   TIMER_OUTCFG27_OUTCFG110_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73217   TIMER_OUTCFG27_OUTCFG110_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73218   TIMER_OUTCFG27_OUTCFG110_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73219   TIMER_OUTCFG27_OUTCFG110_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73220   TIMER_OUTCFG27_OUTCFG110_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73221   TIMER_OUTCFG27_OUTCFG110_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73222   TIMER_OUTCFG27_OUTCFG110_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73223   TIMER_OUTCFG27_OUTCFG110_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73224   TIMER_OUTCFG27_OUTCFG110_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73225   TIMER_OUTCFG27_OUTCFG110_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73226   TIMER_OUTCFG27_OUTCFG110_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73227   TIMER_OUTCFG27_OUTCFG110_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73228   TIMER_OUTCFG27_OUTCFG110_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73229   TIMER_OUTCFG27_OUTCFG110_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73230   TIMER_OUTCFG27_OUTCFG110_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73231   TIMER_OUTCFG27_OUTCFG110_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73232   TIMER_OUTCFG27_OUTCFG110_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73233   TIMER_OUTCFG27_OUTCFG110_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73234   TIMER_OUTCFG27_OUTCFG110_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73235   TIMER_OUTCFG27_OUTCFG110_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73236   TIMER_OUTCFG27_OUTCFG110_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73237   TIMER_OUTCFG27_OUTCFG110_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73238 } TIMER_OUTCFG27_OUTCFG110_Enum;
73239 
73240 /* ===========================================  TIMER OUTCFG27 OUTCFG109 [8..13]  ============================================ */
73241 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG109                                                  */
73242   TIMER_OUTCFG27_OUTCFG109_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73243   TIMER_OUTCFG27_OUTCFG109_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73244   TIMER_OUTCFG27_OUTCFG109_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73245   TIMER_OUTCFG27_OUTCFG109_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73246   TIMER_OUTCFG27_OUTCFG109_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73247   TIMER_OUTCFG27_OUTCFG109_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73248   TIMER_OUTCFG27_OUTCFG109_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73249   TIMER_OUTCFG27_OUTCFG109_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73250   TIMER_OUTCFG27_OUTCFG109_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73251   TIMER_OUTCFG27_OUTCFG109_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73252   TIMER_OUTCFG27_OUTCFG109_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73253   TIMER_OUTCFG27_OUTCFG109_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73254   TIMER_OUTCFG27_OUTCFG109_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73255   TIMER_OUTCFG27_OUTCFG109_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73256   TIMER_OUTCFG27_OUTCFG109_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73257   TIMER_OUTCFG27_OUTCFG109_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73258   TIMER_OUTCFG27_OUTCFG109_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73259   TIMER_OUTCFG27_OUTCFG109_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73260   TIMER_OUTCFG27_OUTCFG109_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73261   TIMER_OUTCFG27_OUTCFG109_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73262   TIMER_OUTCFG27_OUTCFG109_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73263   TIMER_OUTCFG27_OUTCFG109_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73264   TIMER_OUTCFG27_OUTCFG109_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73265   TIMER_OUTCFG27_OUTCFG109_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73266   TIMER_OUTCFG27_OUTCFG109_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73267   TIMER_OUTCFG27_OUTCFG109_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73268   TIMER_OUTCFG27_OUTCFG109_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73269   TIMER_OUTCFG27_OUTCFG109_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73270   TIMER_OUTCFG27_OUTCFG109_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73271   TIMER_OUTCFG27_OUTCFG109_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73272   TIMER_OUTCFG27_OUTCFG109_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73273   TIMER_OUTCFG27_OUTCFG109_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73274   TIMER_OUTCFG27_OUTCFG109_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73275   TIMER_OUTCFG27_OUTCFG109_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73276   TIMER_OUTCFG27_OUTCFG109_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73277   TIMER_OUTCFG27_OUTCFG109_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73278   TIMER_OUTCFG27_OUTCFG109_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73279   TIMER_OUTCFG27_OUTCFG109_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73280   TIMER_OUTCFG27_OUTCFG109_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73281   TIMER_OUTCFG27_OUTCFG109_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73282   TIMER_OUTCFG27_OUTCFG109_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73283 } TIMER_OUTCFG27_OUTCFG109_Enum;
73284 
73285 /* ============================================  TIMER OUTCFG27 OUTCFG108 [0..5]  ============================================ */
73286 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG108                                                  */
73287   TIMER_OUTCFG27_OUTCFG108_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73288   TIMER_OUTCFG27_OUTCFG108_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73289   TIMER_OUTCFG27_OUTCFG108_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73290   TIMER_OUTCFG27_OUTCFG108_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73291   TIMER_OUTCFG27_OUTCFG108_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73292   TIMER_OUTCFG27_OUTCFG108_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73293   TIMER_OUTCFG27_OUTCFG108_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73294   TIMER_OUTCFG27_OUTCFG108_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73295   TIMER_OUTCFG27_OUTCFG108_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73296   TIMER_OUTCFG27_OUTCFG108_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73297   TIMER_OUTCFG27_OUTCFG108_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73298   TIMER_OUTCFG27_OUTCFG108_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73299   TIMER_OUTCFG27_OUTCFG108_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73300   TIMER_OUTCFG27_OUTCFG108_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73301   TIMER_OUTCFG27_OUTCFG108_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73302   TIMER_OUTCFG27_OUTCFG108_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73303   TIMER_OUTCFG27_OUTCFG108_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73304   TIMER_OUTCFG27_OUTCFG108_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73305   TIMER_OUTCFG27_OUTCFG108_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73306   TIMER_OUTCFG27_OUTCFG108_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73307   TIMER_OUTCFG27_OUTCFG108_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73308   TIMER_OUTCFG27_OUTCFG108_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73309   TIMER_OUTCFG27_OUTCFG108_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73310   TIMER_OUTCFG27_OUTCFG108_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73311   TIMER_OUTCFG27_OUTCFG108_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73312   TIMER_OUTCFG27_OUTCFG108_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73313   TIMER_OUTCFG27_OUTCFG108_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73314   TIMER_OUTCFG27_OUTCFG108_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73315   TIMER_OUTCFG27_OUTCFG108_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73316   TIMER_OUTCFG27_OUTCFG108_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73317   TIMER_OUTCFG27_OUTCFG108_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73318   TIMER_OUTCFG27_OUTCFG108_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73319   TIMER_OUTCFG27_OUTCFG108_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73320   TIMER_OUTCFG27_OUTCFG108_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73321   TIMER_OUTCFG27_OUTCFG108_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73322   TIMER_OUTCFG27_OUTCFG108_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73323   TIMER_OUTCFG27_OUTCFG108_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73324   TIMER_OUTCFG27_OUTCFG108_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73325   TIMER_OUTCFG27_OUTCFG108_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73326   TIMER_OUTCFG27_OUTCFG108_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73327   TIMER_OUTCFG27_OUTCFG108_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73328 } TIMER_OUTCFG27_OUTCFG108_Enum;
73329 
73330 /* =======================================================  OUTCFG28  ======================================================== */
73331 /* ===========================================  TIMER OUTCFG28 OUTCFG115 [24..29]  =========================================== */
73332 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG115                                                  */
73333   TIMER_OUTCFG28_OUTCFG115_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73334   TIMER_OUTCFG28_OUTCFG115_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73335   TIMER_OUTCFG28_OUTCFG115_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73336   TIMER_OUTCFG28_OUTCFG115_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73337   TIMER_OUTCFG28_OUTCFG115_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73338   TIMER_OUTCFG28_OUTCFG115_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73339   TIMER_OUTCFG28_OUTCFG115_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73340   TIMER_OUTCFG28_OUTCFG115_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73341   TIMER_OUTCFG28_OUTCFG115_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73342   TIMER_OUTCFG28_OUTCFG115_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73343   TIMER_OUTCFG28_OUTCFG115_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73344   TIMER_OUTCFG28_OUTCFG115_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73345   TIMER_OUTCFG28_OUTCFG115_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73346   TIMER_OUTCFG28_OUTCFG115_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73347   TIMER_OUTCFG28_OUTCFG115_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73348   TIMER_OUTCFG28_OUTCFG115_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73349   TIMER_OUTCFG28_OUTCFG115_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73350   TIMER_OUTCFG28_OUTCFG115_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73351   TIMER_OUTCFG28_OUTCFG115_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73352   TIMER_OUTCFG28_OUTCFG115_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73353   TIMER_OUTCFG28_OUTCFG115_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73354   TIMER_OUTCFG28_OUTCFG115_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73355   TIMER_OUTCFG28_OUTCFG115_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73356   TIMER_OUTCFG28_OUTCFG115_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73357   TIMER_OUTCFG28_OUTCFG115_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73358   TIMER_OUTCFG28_OUTCFG115_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73359   TIMER_OUTCFG28_OUTCFG115_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73360   TIMER_OUTCFG28_OUTCFG115_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73361   TIMER_OUTCFG28_OUTCFG115_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73362   TIMER_OUTCFG28_OUTCFG115_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73363   TIMER_OUTCFG28_OUTCFG115_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73364   TIMER_OUTCFG28_OUTCFG115_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73365   TIMER_OUTCFG28_OUTCFG115_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73366   TIMER_OUTCFG28_OUTCFG115_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73367   TIMER_OUTCFG28_OUTCFG115_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73368   TIMER_OUTCFG28_OUTCFG115_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73369   TIMER_OUTCFG28_OUTCFG115_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73370   TIMER_OUTCFG28_OUTCFG115_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73371   TIMER_OUTCFG28_OUTCFG115_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73372   TIMER_OUTCFG28_OUTCFG115_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73373   TIMER_OUTCFG28_OUTCFG115_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73374 } TIMER_OUTCFG28_OUTCFG115_Enum;
73375 
73376 /* ===========================================  TIMER OUTCFG28 OUTCFG114 [16..21]  =========================================== */
73377 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG114                                                  */
73378   TIMER_OUTCFG28_OUTCFG114_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73379   TIMER_OUTCFG28_OUTCFG114_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73380   TIMER_OUTCFG28_OUTCFG114_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73381   TIMER_OUTCFG28_OUTCFG114_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73382   TIMER_OUTCFG28_OUTCFG114_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73383   TIMER_OUTCFG28_OUTCFG114_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73384   TIMER_OUTCFG28_OUTCFG114_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73385   TIMER_OUTCFG28_OUTCFG114_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73386   TIMER_OUTCFG28_OUTCFG114_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73387   TIMER_OUTCFG28_OUTCFG114_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73388   TIMER_OUTCFG28_OUTCFG114_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73389   TIMER_OUTCFG28_OUTCFG114_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73390   TIMER_OUTCFG28_OUTCFG114_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73391   TIMER_OUTCFG28_OUTCFG114_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73392   TIMER_OUTCFG28_OUTCFG114_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73393   TIMER_OUTCFG28_OUTCFG114_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73394   TIMER_OUTCFG28_OUTCFG114_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73395   TIMER_OUTCFG28_OUTCFG114_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73396   TIMER_OUTCFG28_OUTCFG114_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73397   TIMER_OUTCFG28_OUTCFG114_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73398   TIMER_OUTCFG28_OUTCFG114_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73399   TIMER_OUTCFG28_OUTCFG114_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73400   TIMER_OUTCFG28_OUTCFG114_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73401   TIMER_OUTCFG28_OUTCFG114_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73402   TIMER_OUTCFG28_OUTCFG114_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73403   TIMER_OUTCFG28_OUTCFG114_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73404   TIMER_OUTCFG28_OUTCFG114_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73405   TIMER_OUTCFG28_OUTCFG114_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73406   TIMER_OUTCFG28_OUTCFG114_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73407   TIMER_OUTCFG28_OUTCFG114_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73408   TIMER_OUTCFG28_OUTCFG114_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73409   TIMER_OUTCFG28_OUTCFG114_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73410   TIMER_OUTCFG28_OUTCFG114_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73411   TIMER_OUTCFG28_OUTCFG114_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73412   TIMER_OUTCFG28_OUTCFG114_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73413   TIMER_OUTCFG28_OUTCFG114_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73414   TIMER_OUTCFG28_OUTCFG114_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73415   TIMER_OUTCFG28_OUTCFG114_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73416   TIMER_OUTCFG28_OUTCFG114_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73417   TIMER_OUTCFG28_OUTCFG114_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73418   TIMER_OUTCFG28_OUTCFG114_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73419 } TIMER_OUTCFG28_OUTCFG114_Enum;
73420 
73421 /* ===========================================  TIMER OUTCFG28 OUTCFG113 [8..13]  ============================================ */
73422 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG113                                                  */
73423   TIMER_OUTCFG28_OUTCFG113_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73424   TIMER_OUTCFG28_OUTCFG113_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73425   TIMER_OUTCFG28_OUTCFG113_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73426   TIMER_OUTCFG28_OUTCFG113_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73427   TIMER_OUTCFG28_OUTCFG113_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73428   TIMER_OUTCFG28_OUTCFG113_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73429   TIMER_OUTCFG28_OUTCFG113_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73430   TIMER_OUTCFG28_OUTCFG113_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73431   TIMER_OUTCFG28_OUTCFG113_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73432   TIMER_OUTCFG28_OUTCFG113_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73433   TIMER_OUTCFG28_OUTCFG113_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73434   TIMER_OUTCFG28_OUTCFG113_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73435   TIMER_OUTCFG28_OUTCFG113_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73436   TIMER_OUTCFG28_OUTCFG113_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73437   TIMER_OUTCFG28_OUTCFG113_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73438   TIMER_OUTCFG28_OUTCFG113_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73439   TIMER_OUTCFG28_OUTCFG113_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73440   TIMER_OUTCFG28_OUTCFG113_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73441   TIMER_OUTCFG28_OUTCFG113_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73442   TIMER_OUTCFG28_OUTCFG113_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73443   TIMER_OUTCFG28_OUTCFG113_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73444   TIMER_OUTCFG28_OUTCFG113_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73445   TIMER_OUTCFG28_OUTCFG113_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73446   TIMER_OUTCFG28_OUTCFG113_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73447   TIMER_OUTCFG28_OUTCFG113_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73448   TIMER_OUTCFG28_OUTCFG113_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73449   TIMER_OUTCFG28_OUTCFG113_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73450   TIMER_OUTCFG28_OUTCFG113_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73451   TIMER_OUTCFG28_OUTCFG113_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73452   TIMER_OUTCFG28_OUTCFG113_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73453   TIMER_OUTCFG28_OUTCFG113_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73454   TIMER_OUTCFG28_OUTCFG113_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73455   TIMER_OUTCFG28_OUTCFG113_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73456   TIMER_OUTCFG28_OUTCFG113_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73457   TIMER_OUTCFG28_OUTCFG113_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73458   TIMER_OUTCFG28_OUTCFG113_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73459   TIMER_OUTCFG28_OUTCFG113_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73460   TIMER_OUTCFG28_OUTCFG113_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73461   TIMER_OUTCFG28_OUTCFG113_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73462   TIMER_OUTCFG28_OUTCFG113_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73463   TIMER_OUTCFG28_OUTCFG113_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73464 } TIMER_OUTCFG28_OUTCFG113_Enum;
73465 
73466 /* ============================================  TIMER OUTCFG28 OUTCFG112 [0..5]  ============================================ */
73467 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG112                                                  */
73468   TIMER_OUTCFG28_OUTCFG112_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73469   TIMER_OUTCFG28_OUTCFG112_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73470   TIMER_OUTCFG28_OUTCFG112_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73471   TIMER_OUTCFG28_OUTCFG112_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73472   TIMER_OUTCFG28_OUTCFG112_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73473   TIMER_OUTCFG28_OUTCFG112_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73474   TIMER_OUTCFG28_OUTCFG112_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73475   TIMER_OUTCFG28_OUTCFG112_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73476   TIMER_OUTCFG28_OUTCFG112_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73477   TIMER_OUTCFG28_OUTCFG112_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73478   TIMER_OUTCFG28_OUTCFG112_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73479   TIMER_OUTCFG28_OUTCFG112_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73480   TIMER_OUTCFG28_OUTCFG112_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73481   TIMER_OUTCFG28_OUTCFG112_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73482   TIMER_OUTCFG28_OUTCFG112_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73483   TIMER_OUTCFG28_OUTCFG112_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73484   TIMER_OUTCFG28_OUTCFG112_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73485   TIMER_OUTCFG28_OUTCFG112_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73486   TIMER_OUTCFG28_OUTCFG112_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73487   TIMER_OUTCFG28_OUTCFG112_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73488   TIMER_OUTCFG28_OUTCFG112_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73489   TIMER_OUTCFG28_OUTCFG112_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73490   TIMER_OUTCFG28_OUTCFG112_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73491   TIMER_OUTCFG28_OUTCFG112_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73492   TIMER_OUTCFG28_OUTCFG112_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73493   TIMER_OUTCFG28_OUTCFG112_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73494   TIMER_OUTCFG28_OUTCFG112_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73495   TIMER_OUTCFG28_OUTCFG112_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73496   TIMER_OUTCFG28_OUTCFG112_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73497   TIMER_OUTCFG28_OUTCFG112_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73498   TIMER_OUTCFG28_OUTCFG112_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73499   TIMER_OUTCFG28_OUTCFG112_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73500   TIMER_OUTCFG28_OUTCFG112_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73501   TIMER_OUTCFG28_OUTCFG112_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73502   TIMER_OUTCFG28_OUTCFG112_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73503   TIMER_OUTCFG28_OUTCFG112_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73504   TIMER_OUTCFG28_OUTCFG112_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73505   TIMER_OUTCFG28_OUTCFG112_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73506   TIMER_OUTCFG28_OUTCFG112_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73507   TIMER_OUTCFG28_OUTCFG112_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73508   TIMER_OUTCFG28_OUTCFG112_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73509 } TIMER_OUTCFG28_OUTCFG112_Enum;
73510 
73511 /* =======================================================  OUTCFG29  ======================================================== */
73512 /* ===========================================  TIMER OUTCFG29 OUTCFG119 [24..29]  =========================================== */
73513 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG119                                                  */
73514   TIMER_OUTCFG29_OUTCFG119_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73515   TIMER_OUTCFG29_OUTCFG119_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73516   TIMER_OUTCFG29_OUTCFG119_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73517   TIMER_OUTCFG29_OUTCFG119_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73518   TIMER_OUTCFG29_OUTCFG119_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73519   TIMER_OUTCFG29_OUTCFG119_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73520   TIMER_OUTCFG29_OUTCFG119_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73521   TIMER_OUTCFG29_OUTCFG119_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73522   TIMER_OUTCFG29_OUTCFG119_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73523   TIMER_OUTCFG29_OUTCFG119_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73524   TIMER_OUTCFG29_OUTCFG119_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73525   TIMER_OUTCFG29_OUTCFG119_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73526   TIMER_OUTCFG29_OUTCFG119_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73527   TIMER_OUTCFG29_OUTCFG119_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73528   TIMER_OUTCFG29_OUTCFG119_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73529   TIMER_OUTCFG29_OUTCFG119_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73530   TIMER_OUTCFG29_OUTCFG119_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73531   TIMER_OUTCFG29_OUTCFG119_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73532   TIMER_OUTCFG29_OUTCFG119_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73533   TIMER_OUTCFG29_OUTCFG119_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73534   TIMER_OUTCFG29_OUTCFG119_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73535   TIMER_OUTCFG29_OUTCFG119_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73536   TIMER_OUTCFG29_OUTCFG119_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73537   TIMER_OUTCFG29_OUTCFG119_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73538   TIMER_OUTCFG29_OUTCFG119_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73539   TIMER_OUTCFG29_OUTCFG119_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73540   TIMER_OUTCFG29_OUTCFG119_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73541   TIMER_OUTCFG29_OUTCFG119_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73542   TIMER_OUTCFG29_OUTCFG119_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73543   TIMER_OUTCFG29_OUTCFG119_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73544   TIMER_OUTCFG29_OUTCFG119_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73545   TIMER_OUTCFG29_OUTCFG119_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73546   TIMER_OUTCFG29_OUTCFG119_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73547   TIMER_OUTCFG29_OUTCFG119_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73548   TIMER_OUTCFG29_OUTCFG119_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73549   TIMER_OUTCFG29_OUTCFG119_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73550   TIMER_OUTCFG29_OUTCFG119_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73551   TIMER_OUTCFG29_OUTCFG119_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73552   TIMER_OUTCFG29_OUTCFG119_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73553   TIMER_OUTCFG29_OUTCFG119_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73554   TIMER_OUTCFG29_OUTCFG119_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73555 } TIMER_OUTCFG29_OUTCFG119_Enum;
73556 
73557 /* ===========================================  TIMER OUTCFG29 OUTCFG118 [16..21]  =========================================== */
73558 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG118                                                  */
73559   TIMER_OUTCFG29_OUTCFG118_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73560   TIMER_OUTCFG29_OUTCFG118_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73561   TIMER_OUTCFG29_OUTCFG118_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73562   TIMER_OUTCFG29_OUTCFG118_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73563   TIMER_OUTCFG29_OUTCFG118_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73564   TIMER_OUTCFG29_OUTCFG118_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73565   TIMER_OUTCFG29_OUTCFG118_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73566   TIMER_OUTCFG29_OUTCFG118_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73567   TIMER_OUTCFG29_OUTCFG118_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73568   TIMER_OUTCFG29_OUTCFG118_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73569   TIMER_OUTCFG29_OUTCFG118_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73570   TIMER_OUTCFG29_OUTCFG118_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73571   TIMER_OUTCFG29_OUTCFG118_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73572   TIMER_OUTCFG29_OUTCFG118_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73573   TIMER_OUTCFG29_OUTCFG118_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73574   TIMER_OUTCFG29_OUTCFG118_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73575   TIMER_OUTCFG29_OUTCFG118_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73576   TIMER_OUTCFG29_OUTCFG118_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73577   TIMER_OUTCFG29_OUTCFG118_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73578   TIMER_OUTCFG29_OUTCFG118_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73579   TIMER_OUTCFG29_OUTCFG118_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73580   TIMER_OUTCFG29_OUTCFG118_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73581   TIMER_OUTCFG29_OUTCFG118_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73582   TIMER_OUTCFG29_OUTCFG118_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73583   TIMER_OUTCFG29_OUTCFG118_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73584   TIMER_OUTCFG29_OUTCFG118_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73585   TIMER_OUTCFG29_OUTCFG118_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73586   TIMER_OUTCFG29_OUTCFG118_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73587   TIMER_OUTCFG29_OUTCFG118_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73588   TIMER_OUTCFG29_OUTCFG118_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73589   TIMER_OUTCFG29_OUTCFG118_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73590   TIMER_OUTCFG29_OUTCFG118_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73591   TIMER_OUTCFG29_OUTCFG118_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73592   TIMER_OUTCFG29_OUTCFG118_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73593   TIMER_OUTCFG29_OUTCFG118_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73594   TIMER_OUTCFG29_OUTCFG118_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73595   TIMER_OUTCFG29_OUTCFG118_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73596   TIMER_OUTCFG29_OUTCFG118_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73597   TIMER_OUTCFG29_OUTCFG118_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73598   TIMER_OUTCFG29_OUTCFG118_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73599   TIMER_OUTCFG29_OUTCFG118_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73600 } TIMER_OUTCFG29_OUTCFG118_Enum;
73601 
73602 /* ===========================================  TIMER OUTCFG29 OUTCFG117 [8..13]  ============================================ */
73603 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG117                                                  */
73604   TIMER_OUTCFG29_OUTCFG117_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73605   TIMER_OUTCFG29_OUTCFG117_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73606   TIMER_OUTCFG29_OUTCFG117_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73607   TIMER_OUTCFG29_OUTCFG117_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73608   TIMER_OUTCFG29_OUTCFG117_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73609   TIMER_OUTCFG29_OUTCFG117_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73610   TIMER_OUTCFG29_OUTCFG117_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73611   TIMER_OUTCFG29_OUTCFG117_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73612   TIMER_OUTCFG29_OUTCFG117_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73613   TIMER_OUTCFG29_OUTCFG117_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73614   TIMER_OUTCFG29_OUTCFG117_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73615   TIMER_OUTCFG29_OUTCFG117_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73616   TIMER_OUTCFG29_OUTCFG117_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73617   TIMER_OUTCFG29_OUTCFG117_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73618   TIMER_OUTCFG29_OUTCFG117_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73619   TIMER_OUTCFG29_OUTCFG117_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73620   TIMER_OUTCFG29_OUTCFG117_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73621   TIMER_OUTCFG29_OUTCFG117_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73622   TIMER_OUTCFG29_OUTCFG117_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73623   TIMER_OUTCFG29_OUTCFG117_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73624   TIMER_OUTCFG29_OUTCFG117_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73625   TIMER_OUTCFG29_OUTCFG117_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73626   TIMER_OUTCFG29_OUTCFG117_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73627   TIMER_OUTCFG29_OUTCFG117_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73628   TIMER_OUTCFG29_OUTCFG117_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73629   TIMER_OUTCFG29_OUTCFG117_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73630   TIMER_OUTCFG29_OUTCFG117_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73631   TIMER_OUTCFG29_OUTCFG117_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73632   TIMER_OUTCFG29_OUTCFG117_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73633   TIMER_OUTCFG29_OUTCFG117_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73634   TIMER_OUTCFG29_OUTCFG117_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73635   TIMER_OUTCFG29_OUTCFG117_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73636   TIMER_OUTCFG29_OUTCFG117_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73637   TIMER_OUTCFG29_OUTCFG117_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73638   TIMER_OUTCFG29_OUTCFG117_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73639   TIMER_OUTCFG29_OUTCFG117_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73640   TIMER_OUTCFG29_OUTCFG117_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73641   TIMER_OUTCFG29_OUTCFG117_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73642   TIMER_OUTCFG29_OUTCFG117_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73643   TIMER_OUTCFG29_OUTCFG117_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73644   TIMER_OUTCFG29_OUTCFG117_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73645 } TIMER_OUTCFG29_OUTCFG117_Enum;
73646 
73647 /* ============================================  TIMER OUTCFG29 OUTCFG116 [0..5]  ============================================ */
73648 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG116                                                  */
73649   TIMER_OUTCFG29_OUTCFG116_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73650   TIMER_OUTCFG29_OUTCFG116_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73651   TIMER_OUTCFG29_OUTCFG116_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73652   TIMER_OUTCFG29_OUTCFG116_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73653   TIMER_OUTCFG29_OUTCFG116_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73654   TIMER_OUTCFG29_OUTCFG116_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73655   TIMER_OUTCFG29_OUTCFG116_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73656   TIMER_OUTCFG29_OUTCFG116_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73657   TIMER_OUTCFG29_OUTCFG116_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73658   TIMER_OUTCFG29_OUTCFG116_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73659   TIMER_OUTCFG29_OUTCFG116_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73660   TIMER_OUTCFG29_OUTCFG116_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73661   TIMER_OUTCFG29_OUTCFG116_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73662   TIMER_OUTCFG29_OUTCFG116_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73663   TIMER_OUTCFG29_OUTCFG116_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73664   TIMER_OUTCFG29_OUTCFG116_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73665   TIMER_OUTCFG29_OUTCFG116_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73666   TIMER_OUTCFG29_OUTCFG116_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73667   TIMER_OUTCFG29_OUTCFG116_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73668   TIMER_OUTCFG29_OUTCFG116_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73669   TIMER_OUTCFG29_OUTCFG116_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73670   TIMER_OUTCFG29_OUTCFG116_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73671   TIMER_OUTCFG29_OUTCFG116_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73672   TIMER_OUTCFG29_OUTCFG116_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73673   TIMER_OUTCFG29_OUTCFG116_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73674   TIMER_OUTCFG29_OUTCFG116_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73675   TIMER_OUTCFG29_OUTCFG116_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73676   TIMER_OUTCFG29_OUTCFG116_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73677   TIMER_OUTCFG29_OUTCFG116_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73678   TIMER_OUTCFG29_OUTCFG116_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73679   TIMER_OUTCFG29_OUTCFG116_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73680   TIMER_OUTCFG29_OUTCFG116_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73681   TIMER_OUTCFG29_OUTCFG116_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73682   TIMER_OUTCFG29_OUTCFG116_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73683   TIMER_OUTCFG29_OUTCFG116_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73684   TIMER_OUTCFG29_OUTCFG116_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73685   TIMER_OUTCFG29_OUTCFG116_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73686   TIMER_OUTCFG29_OUTCFG116_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73687   TIMER_OUTCFG29_OUTCFG116_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73688   TIMER_OUTCFG29_OUTCFG116_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73689   TIMER_OUTCFG29_OUTCFG116_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73690 } TIMER_OUTCFG29_OUTCFG116_Enum;
73691 
73692 /* =======================================================  OUTCFG30  ======================================================== */
73693 /* ===========================================  TIMER OUTCFG30 OUTCFG123 [24..29]  =========================================== */
73694 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG123                                                  */
73695   TIMER_OUTCFG30_OUTCFG123_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73696   TIMER_OUTCFG30_OUTCFG123_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73697   TIMER_OUTCFG30_OUTCFG123_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73698   TIMER_OUTCFG30_OUTCFG123_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73699   TIMER_OUTCFG30_OUTCFG123_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73700   TIMER_OUTCFG30_OUTCFG123_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73701   TIMER_OUTCFG30_OUTCFG123_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73702   TIMER_OUTCFG30_OUTCFG123_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73703   TIMER_OUTCFG30_OUTCFG123_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73704   TIMER_OUTCFG30_OUTCFG123_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73705   TIMER_OUTCFG30_OUTCFG123_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73706   TIMER_OUTCFG30_OUTCFG123_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73707   TIMER_OUTCFG30_OUTCFG123_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73708   TIMER_OUTCFG30_OUTCFG123_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73709   TIMER_OUTCFG30_OUTCFG123_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73710   TIMER_OUTCFG30_OUTCFG123_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73711   TIMER_OUTCFG30_OUTCFG123_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73712   TIMER_OUTCFG30_OUTCFG123_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73713   TIMER_OUTCFG30_OUTCFG123_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73714   TIMER_OUTCFG30_OUTCFG123_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73715   TIMER_OUTCFG30_OUTCFG123_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73716   TIMER_OUTCFG30_OUTCFG123_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73717   TIMER_OUTCFG30_OUTCFG123_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73718   TIMER_OUTCFG30_OUTCFG123_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73719   TIMER_OUTCFG30_OUTCFG123_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73720   TIMER_OUTCFG30_OUTCFG123_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73721   TIMER_OUTCFG30_OUTCFG123_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73722   TIMER_OUTCFG30_OUTCFG123_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73723   TIMER_OUTCFG30_OUTCFG123_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73724   TIMER_OUTCFG30_OUTCFG123_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73725   TIMER_OUTCFG30_OUTCFG123_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73726   TIMER_OUTCFG30_OUTCFG123_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73727   TIMER_OUTCFG30_OUTCFG123_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73728   TIMER_OUTCFG30_OUTCFG123_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73729   TIMER_OUTCFG30_OUTCFG123_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73730   TIMER_OUTCFG30_OUTCFG123_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73731   TIMER_OUTCFG30_OUTCFG123_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73732   TIMER_OUTCFG30_OUTCFG123_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73733   TIMER_OUTCFG30_OUTCFG123_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73734   TIMER_OUTCFG30_OUTCFG123_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73735   TIMER_OUTCFG30_OUTCFG123_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73736 } TIMER_OUTCFG30_OUTCFG123_Enum;
73737 
73738 /* ===========================================  TIMER OUTCFG30 OUTCFG122 [16..21]  =========================================== */
73739 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG122                                                  */
73740   TIMER_OUTCFG30_OUTCFG122_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73741   TIMER_OUTCFG30_OUTCFG122_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73742   TIMER_OUTCFG30_OUTCFG122_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73743   TIMER_OUTCFG30_OUTCFG122_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73744   TIMER_OUTCFG30_OUTCFG122_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73745   TIMER_OUTCFG30_OUTCFG122_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73746   TIMER_OUTCFG30_OUTCFG122_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73747   TIMER_OUTCFG30_OUTCFG122_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73748   TIMER_OUTCFG30_OUTCFG122_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73749   TIMER_OUTCFG30_OUTCFG122_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73750   TIMER_OUTCFG30_OUTCFG122_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73751   TIMER_OUTCFG30_OUTCFG122_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73752   TIMER_OUTCFG30_OUTCFG122_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73753   TIMER_OUTCFG30_OUTCFG122_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73754   TIMER_OUTCFG30_OUTCFG122_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73755   TIMER_OUTCFG30_OUTCFG122_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73756   TIMER_OUTCFG30_OUTCFG122_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73757   TIMER_OUTCFG30_OUTCFG122_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73758   TIMER_OUTCFG30_OUTCFG122_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73759   TIMER_OUTCFG30_OUTCFG122_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73760   TIMER_OUTCFG30_OUTCFG122_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73761   TIMER_OUTCFG30_OUTCFG122_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73762   TIMER_OUTCFG30_OUTCFG122_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73763   TIMER_OUTCFG30_OUTCFG122_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73764   TIMER_OUTCFG30_OUTCFG122_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73765   TIMER_OUTCFG30_OUTCFG122_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73766   TIMER_OUTCFG30_OUTCFG122_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73767   TIMER_OUTCFG30_OUTCFG122_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73768   TIMER_OUTCFG30_OUTCFG122_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73769   TIMER_OUTCFG30_OUTCFG122_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73770   TIMER_OUTCFG30_OUTCFG122_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73771   TIMER_OUTCFG30_OUTCFG122_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73772   TIMER_OUTCFG30_OUTCFG122_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73773   TIMER_OUTCFG30_OUTCFG122_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73774   TIMER_OUTCFG30_OUTCFG122_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73775   TIMER_OUTCFG30_OUTCFG122_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73776   TIMER_OUTCFG30_OUTCFG122_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73777   TIMER_OUTCFG30_OUTCFG122_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73778   TIMER_OUTCFG30_OUTCFG122_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73779   TIMER_OUTCFG30_OUTCFG122_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73780   TIMER_OUTCFG30_OUTCFG122_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73781 } TIMER_OUTCFG30_OUTCFG122_Enum;
73782 
73783 /* ===========================================  TIMER OUTCFG30 OUTCFG121 [8..13]  ============================================ */
73784 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG121                                                  */
73785   TIMER_OUTCFG30_OUTCFG121_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73786   TIMER_OUTCFG30_OUTCFG121_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73787   TIMER_OUTCFG30_OUTCFG121_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73788   TIMER_OUTCFG30_OUTCFG121_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73789   TIMER_OUTCFG30_OUTCFG121_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73790   TIMER_OUTCFG30_OUTCFG121_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73791   TIMER_OUTCFG30_OUTCFG121_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73792   TIMER_OUTCFG30_OUTCFG121_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73793   TIMER_OUTCFG30_OUTCFG121_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73794   TIMER_OUTCFG30_OUTCFG121_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73795   TIMER_OUTCFG30_OUTCFG121_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73796   TIMER_OUTCFG30_OUTCFG121_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73797   TIMER_OUTCFG30_OUTCFG121_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73798   TIMER_OUTCFG30_OUTCFG121_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73799   TIMER_OUTCFG30_OUTCFG121_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73800   TIMER_OUTCFG30_OUTCFG121_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73801   TIMER_OUTCFG30_OUTCFG121_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73802   TIMER_OUTCFG30_OUTCFG121_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73803   TIMER_OUTCFG30_OUTCFG121_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73804   TIMER_OUTCFG30_OUTCFG121_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73805   TIMER_OUTCFG30_OUTCFG121_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73806   TIMER_OUTCFG30_OUTCFG121_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73807   TIMER_OUTCFG30_OUTCFG121_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73808   TIMER_OUTCFG30_OUTCFG121_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73809   TIMER_OUTCFG30_OUTCFG121_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73810   TIMER_OUTCFG30_OUTCFG121_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73811   TIMER_OUTCFG30_OUTCFG121_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73812   TIMER_OUTCFG30_OUTCFG121_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73813   TIMER_OUTCFG30_OUTCFG121_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73814   TIMER_OUTCFG30_OUTCFG121_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73815   TIMER_OUTCFG30_OUTCFG121_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73816   TIMER_OUTCFG30_OUTCFG121_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73817   TIMER_OUTCFG30_OUTCFG121_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73818   TIMER_OUTCFG30_OUTCFG121_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73819   TIMER_OUTCFG30_OUTCFG121_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73820   TIMER_OUTCFG30_OUTCFG121_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73821   TIMER_OUTCFG30_OUTCFG121_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73822   TIMER_OUTCFG30_OUTCFG121_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73823   TIMER_OUTCFG30_OUTCFG121_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73824   TIMER_OUTCFG30_OUTCFG121_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73825   TIMER_OUTCFG30_OUTCFG121_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73826 } TIMER_OUTCFG30_OUTCFG121_Enum;
73827 
73828 /* ============================================  TIMER OUTCFG30 OUTCFG120 [0..5]  ============================================ */
73829 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG120                                                  */
73830   TIMER_OUTCFG30_OUTCFG120_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73831   TIMER_OUTCFG30_OUTCFG120_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73832   TIMER_OUTCFG30_OUTCFG120_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73833   TIMER_OUTCFG30_OUTCFG120_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73834   TIMER_OUTCFG30_OUTCFG120_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73835   TIMER_OUTCFG30_OUTCFG120_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73836   TIMER_OUTCFG30_OUTCFG120_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73837   TIMER_OUTCFG30_OUTCFG120_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73838   TIMER_OUTCFG30_OUTCFG120_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73839   TIMER_OUTCFG30_OUTCFG120_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73840   TIMER_OUTCFG30_OUTCFG120_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73841   TIMER_OUTCFG30_OUTCFG120_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73842   TIMER_OUTCFG30_OUTCFG120_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73843   TIMER_OUTCFG30_OUTCFG120_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73844   TIMER_OUTCFG30_OUTCFG120_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73845   TIMER_OUTCFG30_OUTCFG120_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73846   TIMER_OUTCFG30_OUTCFG120_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73847   TIMER_OUTCFG30_OUTCFG120_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73848   TIMER_OUTCFG30_OUTCFG120_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73849   TIMER_OUTCFG30_OUTCFG120_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73850   TIMER_OUTCFG30_OUTCFG120_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73851   TIMER_OUTCFG30_OUTCFG120_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73852   TIMER_OUTCFG30_OUTCFG120_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73853   TIMER_OUTCFG30_OUTCFG120_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73854   TIMER_OUTCFG30_OUTCFG120_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73855   TIMER_OUTCFG30_OUTCFG120_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73856   TIMER_OUTCFG30_OUTCFG120_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73857   TIMER_OUTCFG30_OUTCFG120_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73858   TIMER_OUTCFG30_OUTCFG120_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73859   TIMER_OUTCFG30_OUTCFG120_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73860   TIMER_OUTCFG30_OUTCFG120_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73861   TIMER_OUTCFG30_OUTCFG120_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73862   TIMER_OUTCFG30_OUTCFG120_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73863   TIMER_OUTCFG30_OUTCFG120_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73864   TIMER_OUTCFG30_OUTCFG120_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73865   TIMER_OUTCFG30_OUTCFG120_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73866   TIMER_OUTCFG30_OUTCFG120_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73867   TIMER_OUTCFG30_OUTCFG120_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73868   TIMER_OUTCFG30_OUTCFG120_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73869   TIMER_OUTCFG30_OUTCFG120_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73870   TIMER_OUTCFG30_OUTCFG120_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73871 } TIMER_OUTCFG30_OUTCFG120_Enum;
73872 
73873 /* =======================================================  OUTCFG31  ======================================================== */
73874 /* ===========================================  TIMER OUTCFG31 OUTCFG127 [24..29]  =========================================== */
73875 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG127                                                  */
73876   TIMER_OUTCFG31_OUTCFG127_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73877   TIMER_OUTCFG31_OUTCFG127_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73878   TIMER_OUTCFG31_OUTCFG127_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73879   TIMER_OUTCFG31_OUTCFG127_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73880   TIMER_OUTCFG31_OUTCFG127_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73881   TIMER_OUTCFG31_OUTCFG127_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73882   TIMER_OUTCFG31_OUTCFG127_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73883   TIMER_OUTCFG31_OUTCFG127_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73884   TIMER_OUTCFG31_OUTCFG127_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73885   TIMER_OUTCFG31_OUTCFG127_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73886   TIMER_OUTCFG31_OUTCFG127_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73887   TIMER_OUTCFG31_OUTCFG127_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73888   TIMER_OUTCFG31_OUTCFG127_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73889   TIMER_OUTCFG31_OUTCFG127_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73890   TIMER_OUTCFG31_OUTCFG127_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73891   TIMER_OUTCFG31_OUTCFG127_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73892   TIMER_OUTCFG31_OUTCFG127_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73893   TIMER_OUTCFG31_OUTCFG127_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73894   TIMER_OUTCFG31_OUTCFG127_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73895   TIMER_OUTCFG31_OUTCFG127_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73896   TIMER_OUTCFG31_OUTCFG127_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73897   TIMER_OUTCFG31_OUTCFG127_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73898   TIMER_OUTCFG31_OUTCFG127_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73899   TIMER_OUTCFG31_OUTCFG127_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73900   TIMER_OUTCFG31_OUTCFG127_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73901   TIMER_OUTCFG31_OUTCFG127_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73902   TIMER_OUTCFG31_OUTCFG127_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73903   TIMER_OUTCFG31_OUTCFG127_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73904   TIMER_OUTCFG31_OUTCFG127_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73905   TIMER_OUTCFG31_OUTCFG127_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73906   TIMER_OUTCFG31_OUTCFG127_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73907   TIMER_OUTCFG31_OUTCFG127_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73908   TIMER_OUTCFG31_OUTCFG127_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73909   TIMER_OUTCFG31_OUTCFG127_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73910   TIMER_OUTCFG31_OUTCFG127_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73911   TIMER_OUTCFG31_OUTCFG127_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73912   TIMER_OUTCFG31_OUTCFG127_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73913   TIMER_OUTCFG31_OUTCFG127_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73914   TIMER_OUTCFG31_OUTCFG127_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73915   TIMER_OUTCFG31_OUTCFG127_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73916   TIMER_OUTCFG31_OUTCFG127_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73917 } TIMER_OUTCFG31_OUTCFG127_Enum;
73918 
73919 /* ===========================================  TIMER OUTCFG31 OUTCFG126 [16..21]  =========================================== */
73920 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG126                                                  */
73921   TIMER_OUTCFG31_OUTCFG126_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73922   TIMER_OUTCFG31_OUTCFG126_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73923   TIMER_OUTCFG31_OUTCFG126_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73924   TIMER_OUTCFG31_OUTCFG126_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73925   TIMER_OUTCFG31_OUTCFG126_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73926   TIMER_OUTCFG31_OUTCFG126_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73927   TIMER_OUTCFG31_OUTCFG126_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73928   TIMER_OUTCFG31_OUTCFG126_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73929   TIMER_OUTCFG31_OUTCFG126_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73930   TIMER_OUTCFG31_OUTCFG126_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73931   TIMER_OUTCFG31_OUTCFG126_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73932   TIMER_OUTCFG31_OUTCFG126_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73933   TIMER_OUTCFG31_OUTCFG126_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73934   TIMER_OUTCFG31_OUTCFG126_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73935   TIMER_OUTCFG31_OUTCFG126_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73936   TIMER_OUTCFG31_OUTCFG126_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73937   TIMER_OUTCFG31_OUTCFG126_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73938   TIMER_OUTCFG31_OUTCFG126_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73939   TIMER_OUTCFG31_OUTCFG126_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73940   TIMER_OUTCFG31_OUTCFG126_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73941   TIMER_OUTCFG31_OUTCFG126_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73942   TIMER_OUTCFG31_OUTCFG126_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73943   TIMER_OUTCFG31_OUTCFG126_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73944   TIMER_OUTCFG31_OUTCFG126_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73945   TIMER_OUTCFG31_OUTCFG126_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73946   TIMER_OUTCFG31_OUTCFG126_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73947   TIMER_OUTCFG31_OUTCFG126_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73948   TIMER_OUTCFG31_OUTCFG126_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73949   TIMER_OUTCFG31_OUTCFG126_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73950   TIMER_OUTCFG31_OUTCFG126_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73951   TIMER_OUTCFG31_OUTCFG126_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73952   TIMER_OUTCFG31_OUTCFG126_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73953   TIMER_OUTCFG31_OUTCFG126_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73954   TIMER_OUTCFG31_OUTCFG126_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73955   TIMER_OUTCFG31_OUTCFG126_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73956   TIMER_OUTCFG31_OUTCFG126_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73957   TIMER_OUTCFG31_OUTCFG126_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73958   TIMER_OUTCFG31_OUTCFG126_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73959   TIMER_OUTCFG31_OUTCFG126_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73960   TIMER_OUTCFG31_OUTCFG126_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73961   TIMER_OUTCFG31_OUTCFG126_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
73962 } TIMER_OUTCFG31_OUTCFG126_Enum;
73963 
73964 /* ===========================================  TIMER OUTCFG31 OUTCFG125 [8..13]  ============================================ */
73965 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG125                                                  */
73966   TIMER_OUTCFG31_OUTCFG125_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73967   TIMER_OUTCFG31_OUTCFG125_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73968   TIMER_OUTCFG31_OUTCFG125_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73969   TIMER_OUTCFG31_OUTCFG125_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73970   TIMER_OUTCFG31_OUTCFG125_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73971   TIMER_OUTCFG31_OUTCFG125_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73972   TIMER_OUTCFG31_OUTCFG125_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73973   TIMER_OUTCFG31_OUTCFG125_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73974   TIMER_OUTCFG31_OUTCFG125_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73975   TIMER_OUTCFG31_OUTCFG125_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73976   TIMER_OUTCFG31_OUTCFG125_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73977   TIMER_OUTCFG31_OUTCFG125_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73978   TIMER_OUTCFG31_OUTCFG125_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73979   TIMER_OUTCFG31_OUTCFG125_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73980   TIMER_OUTCFG31_OUTCFG125_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73981   TIMER_OUTCFG31_OUTCFG125_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73982   TIMER_OUTCFG31_OUTCFG125_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73983   TIMER_OUTCFG31_OUTCFG125_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73984   TIMER_OUTCFG31_OUTCFG125_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73985   TIMER_OUTCFG31_OUTCFG125_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73986   TIMER_OUTCFG31_OUTCFG125_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73987   TIMER_OUTCFG31_OUTCFG125_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73988   TIMER_OUTCFG31_OUTCFG125_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73989   TIMER_OUTCFG31_OUTCFG125_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73990   TIMER_OUTCFG31_OUTCFG125_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73991   TIMER_OUTCFG31_OUTCFG125_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73992   TIMER_OUTCFG31_OUTCFG125_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73993   TIMER_OUTCFG31_OUTCFG125_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73994   TIMER_OUTCFG31_OUTCFG125_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73995   TIMER_OUTCFG31_OUTCFG125_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73996   TIMER_OUTCFG31_OUTCFG125_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73997   TIMER_OUTCFG31_OUTCFG125_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73998   TIMER_OUTCFG31_OUTCFG125_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73999   TIMER_OUTCFG31_OUTCFG125_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74000   TIMER_OUTCFG31_OUTCFG125_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74001   TIMER_OUTCFG31_OUTCFG125_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74002   TIMER_OUTCFG31_OUTCFG125_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74003   TIMER_OUTCFG31_OUTCFG125_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74004   TIMER_OUTCFG31_OUTCFG125_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74005   TIMER_OUTCFG31_OUTCFG125_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74006   TIMER_OUTCFG31_OUTCFG125_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74007 } TIMER_OUTCFG31_OUTCFG125_Enum;
74008 
74009 /* ============================================  TIMER OUTCFG31 OUTCFG124 [0..5]  ============================================ */
74010 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG124                                                  */
74011   TIMER_OUTCFG31_OUTCFG124_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74012   TIMER_OUTCFG31_OUTCFG124_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74013   TIMER_OUTCFG31_OUTCFG124_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74014   TIMER_OUTCFG31_OUTCFG124_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74015   TIMER_OUTCFG31_OUTCFG124_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74016   TIMER_OUTCFG31_OUTCFG124_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74017   TIMER_OUTCFG31_OUTCFG124_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74018   TIMER_OUTCFG31_OUTCFG124_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74019   TIMER_OUTCFG31_OUTCFG124_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74020   TIMER_OUTCFG31_OUTCFG124_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74021   TIMER_OUTCFG31_OUTCFG124_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74022   TIMER_OUTCFG31_OUTCFG124_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74023   TIMER_OUTCFG31_OUTCFG124_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74024   TIMER_OUTCFG31_OUTCFG124_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74025   TIMER_OUTCFG31_OUTCFG124_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74026   TIMER_OUTCFG31_OUTCFG124_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74027   TIMER_OUTCFG31_OUTCFG124_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74028   TIMER_OUTCFG31_OUTCFG124_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74029   TIMER_OUTCFG31_OUTCFG124_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74030   TIMER_OUTCFG31_OUTCFG124_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74031   TIMER_OUTCFG31_OUTCFG124_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74032   TIMER_OUTCFG31_OUTCFG124_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74033   TIMER_OUTCFG31_OUTCFG124_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74034   TIMER_OUTCFG31_OUTCFG124_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74035   TIMER_OUTCFG31_OUTCFG124_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74036   TIMER_OUTCFG31_OUTCFG124_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74037   TIMER_OUTCFG31_OUTCFG124_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74038   TIMER_OUTCFG31_OUTCFG124_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74039   TIMER_OUTCFG31_OUTCFG124_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74040   TIMER_OUTCFG31_OUTCFG124_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74041   TIMER_OUTCFG31_OUTCFG124_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74042   TIMER_OUTCFG31_OUTCFG124_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74043   TIMER_OUTCFG31_OUTCFG124_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74044   TIMER_OUTCFG31_OUTCFG124_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74045   TIMER_OUTCFG31_OUTCFG124_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74046   TIMER_OUTCFG31_OUTCFG124_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74047   TIMER_OUTCFG31_OUTCFG124_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74048   TIMER_OUTCFG31_OUTCFG124_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74049   TIMER_OUTCFG31_OUTCFG124_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74050   TIMER_OUTCFG31_OUTCFG124_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74051   TIMER_OUTCFG31_OUTCFG124_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74052 } TIMER_OUTCFG31_OUTCFG124_Enum;
74053 
74054 /* =========================================================  AUXEN  ========================================================= */
74055 /* ==============================================  TIMER AUXEN STMREN [16..16]  ============================================== */
74056 typedef enum {                                  /*!< TIMER_AUXEN_STMREN                                                        */
74057   TIMER_AUXEN_STMREN_DIS               = 0,     /*!< DIS : Disable STIMER.                                                     */
74058   TIMER_AUXEN_STMREN_EN                = 1,     /*!< EN : Enable STIMER.                                                       */
74059 } TIMER_AUXEN_STMREN_Enum;
74060 
74061 /* =============================================  TIMER AUXEN TMR15EN [15..15]  ============================================== */
74062 typedef enum {                                  /*!< TIMER_AUXEN_TMR15EN                                                       */
74063   TIMER_AUXEN_TMR15EN_DIS              = 0,     /*!< DIS : Disable TIMER15.                                                    */
74064   TIMER_AUXEN_TMR15EN_EN               = 1,     /*!< EN : Enable TIMER15.                                                      */
74065 } TIMER_AUXEN_TMR15EN_Enum;
74066 
74067 /* =============================================  TIMER AUXEN TMR14EN [14..14]  ============================================== */
74068 typedef enum {                                  /*!< TIMER_AUXEN_TMR14EN                                                       */
74069   TIMER_AUXEN_TMR14EN_DIS              = 0,     /*!< DIS : Disable TIMER14.                                                    */
74070   TIMER_AUXEN_TMR14EN_EN               = 1,     /*!< EN : Enable TIMER14.                                                      */
74071 } TIMER_AUXEN_TMR14EN_Enum;
74072 
74073 /* =============================================  TIMER AUXEN TMR13EN [13..13]  ============================================== */
74074 typedef enum {                                  /*!< TIMER_AUXEN_TMR13EN                                                       */
74075   TIMER_AUXEN_TMR13EN_DIS              = 0,     /*!< DIS : Disable TIMER13.                                                    */
74076   TIMER_AUXEN_TMR13EN_EN               = 1,     /*!< EN : Enable TIMER13.                                                      */
74077 } TIMER_AUXEN_TMR13EN_Enum;
74078 
74079 /* =============================================  TIMER AUXEN TMR12EN [12..12]  ============================================== */
74080 typedef enum {                                  /*!< TIMER_AUXEN_TMR12EN                                                       */
74081   TIMER_AUXEN_TMR12EN_DIS              = 0,     /*!< DIS : Disable TIMER12.                                                    */
74082   TIMER_AUXEN_TMR12EN_EN               = 1,     /*!< EN : Enable TIMER12.                                                      */
74083 } TIMER_AUXEN_TMR12EN_Enum;
74084 
74085 /* =============================================  TIMER AUXEN TMR11EN [11..11]  ============================================== */
74086 typedef enum {                                  /*!< TIMER_AUXEN_TMR11EN                                                       */
74087   TIMER_AUXEN_TMR11EN_DIS              = 0,     /*!< DIS : Disable TIMER11.                                                    */
74088   TIMER_AUXEN_TMR11EN_EN               = 1,     /*!< EN : Enable TIMER11.                                                      */
74089 } TIMER_AUXEN_TMR11EN_Enum;
74090 
74091 /* =============================================  TIMER AUXEN TMR10EN [10..10]  ============================================== */
74092 typedef enum {                                  /*!< TIMER_AUXEN_TMR10EN                                                       */
74093   TIMER_AUXEN_TMR10EN_DIS              = 0,     /*!< DIS : Disable TIMER10.                                                    */
74094   TIMER_AUXEN_TMR10EN_EN               = 1,     /*!< EN : Enable TIMER10.                                                      */
74095 } TIMER_AUXEN_TMR10EN_Enum;
74096 
74097 /* ==============================================  TIMER AUXEN TMR09EN [9..9]  =============================================== */
74098 typedef enum {                                  /*!< TIMER_AUXEN_TMR09EN                                                       */
74099   TIMER_AUXEN_TMR09EN_DIS              = 0,     /*!< DIS : Disable TIMER09.                                                    */
74100   TIMER_AUXEN_TMR09EN_EN               = 1,     /*!< EN : Enable TIMER09.                                                      */
74101 } TIMER_AUXEN_TMR09EN_Enum;
74102 
74103 /* ==============================================  TIMER AUXEN TMR08EN [8..8]  =============================================== */
74104 typedef enum {                                  /*!< TIMER_AUXEN_TMR08EN                                                       */
74105   TIMER_AUXEN_TMR08EN_DIS              = 0,     /*!< DIS : Disable TIMER08.                                                    */
74106   TIMER_AUXEN_TMR08EN_EN               = 1,     /*!< EN : Enable TIMER08.                                                      */
74107 } TIMER_AUXEN_TMR08EN_Enum;
74108 
74109 /* ==============================================  TIMER AUXEN TMR07EN [7..7]  =============================================== */
74110 typedef enum {                                  /*!< TIMER_AUXEN_TMR07EN                                                       */
74111   TIMER_AUXEN_TMR07EN_DIS              = 0,     /*!< DIS : Disable TIMER07.                                                    */
74112   TIMER_AUXEN_TMR07EN_EN               = 1,     /*!< EN : Enable TIMER07.                                                      */
74113 } TIMER_AUXEN_TMR07EN_Enum;
74114 
74115 /* ==============================================  TIMER AUXEN TMR06EN [6..6]  =============================================== */
74116 typedef enum {                                  /*!< TIMER_AUXEN_TMR06EN                                                       */
74117   TIMER_AUXEN_TMR06EN_DIS              = 0,     /*!< DIS : Disable TIMER06.                                                    */
74118   TIMER_AUXEN_TMR06EN_EN               = 1,     /*!< EN : Enable TIMER06.                                                      */
74119 } TIMER_AUXEN_TMR06EN_Enum;
74120 
74121 /* ==============================================  TIMER AUXEN TMR05EN [5..5]  =============================================== */
74122 typedef enum {                                  /*!< TIMER_AUXEN_TMR05EN                                                       */
74123   TIMER_AUXEN_TMR05EN_DIS              = 0,     /*!< DIS : Disable TIMER05.                                                    */
74124   TIMER_AUXEN_TMR05EN_EN               = 1,     /*!< EN : Enable TIMER05.                                                      */
74125 } TIMER_AUXEN_TMR05EN_Enum;
74126 
74127 /* ==============================================  TIMER AUXEN TMR04EN [4..4]  =============================================== */
74128 typedef enum {                                  /*!< TIMER_AUXEN_TMR04EN                                                       */
74129   TIMER_AUXEN_TMR04EN_DIS              = 0,     /*!< DIS : Disable TIMER04.                                                    */
74130   TIMER_AUXEN_TMR04EN_EN               = 1,     /*!< EN : Enable TIMER04.                                                      */
74131 } TIMER_AUXEN_TMR04EN_Enum;
74132 
74133 /* ==============================================  TIMER AUXEN TMR03EN [3..3]  =============================================== */
74134 typedef enum {                                  /*!< TIMER_AUXEN_TMR03EN                                                       */
74135   TIMER_AUXEN_TMR03EN_DIS              = 0,     /*!< DIS : Disable TIMER03.                                                    */
74136   TIMER_AUXEN_TMR03EN_EN               = 1,     /*!< EN : Enable TIMER03.                                                      */
74137 } TIMER_AUXEN_TMR03EN_Enum;
74138 
74139 /* ==============================================  TIMER AUXEN TMR02EN [2..2]  =============================================== */
74140 typedef enum {                                  /*!< TIMER_AUXEN_TMR02EN                                                       */
74141   TIMER_AUXEN_TMR02EN_DIS              = 0,     /*!< DIS : Disable TIMER02.                                                    */
74142   TIMER_AUXEN_TMR02EN_EN               = 1,     /*!< EN : Enable TIMER02.                                                      */
74143 } TIMER_AUXEN_TMR02EN_Enum;
74144 
74145 /* ==============================================  TIMER AUXEN TMR01EN [1..1]  =============================================== */
74146 typedef enum {                                  /*!< TIMER_AUXEN_TMR01EN                                                       */
74147   TIMER_AUXEN_TMR01EN_DIS              = 0,     /*!< DIS : Disable TIMER01.                                                    */
74148   TIMER_AUXEN_TMR01EN_EN               = 1,     /*!< EN : Enable TIMER01.                                                      */
74149 } TIMER_AUXEN_TMR01EN_Enum;
74150 
74151 /* ==============================================  TIMER AUXEN TMR00EN [0..0]  =============================================== */
74152 typedef enum {                                  /*!< TIMER_AUXEN_TMR00EN                                                       */
74153   TIMER_AUXEN_TMR00EN_DIS              = 0,     /*!< DIS : Disable TIMER00.                                                    */
74154   TIMER_AUXEN_TMR00EN_EN               = 1,     /*!< EN : Enable TIMER00.                                                      */
74155 } TIMER_AUXEN_TMR00EN_Enum;
74156 
74157 /* =========================================================  CTRL0  ========================================================= */
74158 /* ============================================  TIMER CTRL0 TMR0TMODE [16..17]  ============================================= */
74159 typedef enum {                                  /*!< TIMER_CTRL0_TMR0TMODE                                                     */
74160   TIMER_CTRL0_TMR0TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
74161   TIMER_CTRL0_TMR0TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
74162   TIMER_CTRL0_TMR0TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
74163   TIMER_CTRL0_TMR0TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
74164 } TIMER_CTRL0_TMR0TMODE_Enum;
74165 
74166 /* ==============================================  TIMER CTRL0 TMR0CLK [8..15]  ============================================== */
74167 typedef enum {                                  /*!< TIMER_CTRL0_TMR0CLK                                                       */
74168   TIMER_CTRL0_TMR0CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
74169   TIMER_CTRL0_TMR0CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
74170   TIMER_CTRL0_TMR0CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
74171   TIMER_CTRL0_TMR0CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
74172   TIMER_CTRL0_TMR0CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
74173   TIMER_CTRL0_TMR0CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
74174   TIMER_CTRL0_TMR0CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
74175   TIMER_CTRL0_TMR0CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
74176   TIMER_CTRL0_TMR0CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
74177   TIMER_CTRL0_TMR0CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
74178   TIMER_CTRL0_TMR0CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
74179   TIMER_CTRL0_TMR0CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
74180   TIMER_CTRL0_TMR0CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
74181   TIMER_CTRL0_TMR0CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
74182   TIMER_CTRL0_TMR0CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
74183   TIMER_CTRL0_TMR0CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
74184   TIMER_CTRL0_TMR0CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
74185   TIMER_CTRL0_TMR0CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
74186   TIMER_CTRL0_TMR0CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
74187   TIMER_CTRL0_TMR0CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
74188   TIMER_CTRL0_TMR0CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
74189   TIMER_CTRL0_TMR0CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
74190   TIMER_CTRL0_TMR0CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
74191   TIMER_CTRL0_TMR0CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
74192   TIMER_CTRL0_TMR0CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
74193   TIMER_CTRL0_TMR0CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
74194   TIMER_CTRL0_TMR0CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
74195   TIMER_CTRL0_TMR0CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
74196   TIMER_CTRL0_TMR0CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
74197   TIMER_CTRL0_TMR0CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
74198   TIMER_CTRL0_TMR0CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
74199   TIMER_CTRL0_TMR0CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
74200   TIMER_CTRL0_TMR0CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
74201   TIMER_CTRL0_TMR0CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
74202   TIMER_CTRL0_TMR0CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
74203   TIMER_CTRL0_TMR0CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
74204   TIMER_CTRL0_TMR0CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
74205   TIMER_CTRL0_TMR0CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
74206   TIMER_CTRL0_TMR0CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
74207   TIMER_CTRL0_TMR0CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
74208   TIMER_CTRL0_TMR0CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
74209   TIMER_CTRL0_TMR0CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
74210   TIMER_CTRL0_TMR0CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
74211   TIMER_CTRL0_TMR0CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
74212   TIMER_CTRL0_TMR0CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
74213   TIMER_CTRL0_TMR0CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
74214   TIMER_CTRL0_TMR0CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
74215   TIMER_CTRL0_TMR0CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
74216   TIMER_CTRL0_TMR0CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
74217   TIMER_CTRL0_TMR0CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
74218   TIMER_CTRL0_TMR0CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
74219   TIMER_CTRL0_TMR0CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
74220   TIMER_CTRL0_TMR0CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
74221   TIMER_CTRL0_TMR0CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
74222   TIMER_CTRL0_TMR0CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
74223   TIMER_CTRL0_TMR0CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
74224   TIMER_CTRL0_TMR0CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
74225 } TIMER_CTRL0_TMR0CLK_Enum;
74226 
74227 /* ===============================================  TIMER CTRL0 TMR0FN [4..7]  =============================================== */
74228 typedef enum {                                  /*!< TIMER_CTRL0_TMR0FN                                                        */
74229   TIMER_CTRL0_TMR0FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
74230                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
74231   TIMER_CTRL0_TMR0FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
74232                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
74233                                                      follows CMP1.                                                             */
74234   TIMER_CTRL0_TMR0FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
74235                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
74236                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
74237   TIMER_CTRL0_TMR0FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
74238                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
74239   TIMER_CTRL0_TMR0FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
74240                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
74241                                                      and OUT[1] formed by TIMER>=CMPn                                          */
74242   TIMER_CTRL0_TMR0FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
74243                                                      LMT field specifies length of pattern. When LMT>32 OUT0
74244                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
74245                                                      is CMP1,CMP1                                                              */
74246   TIMER_CTRL0_TMR0FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
74247                                                      pattern repeats after reaching LMT.                                       */
74248   TIMER_CTRL0_TMR0FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
74249                                                      trigger until next edge (rising or falling) of source clock
74250                                                      (used as a secondary event). This can be used to measure
74251                                                      time betwen GPIOs, etc.                                                   */
74252 } TIMER_CTRL0_TMR0FN_Enum;
74253 
74254 /* ==============================================  TIMER CTRL0 TMR0POL1 [3..3]  ============================================== */
74255 typedef enum {                                  /*!< TIMER_CTRL0_TMR0POL1                                                      */
74256   TIMER_CTRL0_TMR0POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR0OUT1 pin is the same as the
74257                                                      timer output.                                                             */
74258   TIMER_CTRL0_TMR0POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR0OUT1 pin is the inverse of
74259                                                      the timer output.                                                         */
74260 } TIMER_CTRL0_TMR0POL1_Enum;
74261 
74262 /* ==============================================  TIMER CTRL0 TMR0POL0 [2..2]  ============================================== */
74263 typedef enum {                                  /*!< TIMER_CTRL0_TMR0POL0                                                      */
74264   TIMER_CTRL0_TMR0POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR0OUT0 pin is the same as the
74265                                                      timer output.                                                             */
74266   TIMER_CTRL0_TMR0POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR0OUT0 pin is the inverse of
74267                                                      the timer output.                                                         */
74268 } TIMER_CTRL0_TMR0POL0_Enum;
74269 
74270 /* ==============================================  TIMER CTRL0 TMR0CLR [1..1]  =============================================== */
74271 typedef enum {                                  /*!< TIMER_CTRL0_TMR0CLR                                                       */
74272   TIMER_CTRL0_TMR0CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
74273                                                      cleared to its reset state (0 for count up counter, CMP0
74274                                                      for down counter)                                                         */
74275 } TIMER_CTRL0_TMR0CLR_Enum;
74276 
74277 /* ===============================================  TIMER CTRL0 TMR0EN [0..0]  =============================================== */
74278 typedef enum {                                  /*!< TIMER_CTRL0_TMR0EN                                                        */
74279   TIMER_CTRL0_TMR0EN_DIS               = 0,     /*!< DIS : Counter/Timer 0 Disable.                                            */
74280   TIMER_CTRL0_TMR0EN_EN                = 1,     /*!< EN : Counter/Timer 0 Enable.                                              */
74281 } TIMER_CTRL0_TMR0EN_Enum;
74282 
74283 /* ========================================================  TIMER0  ========================================================= */
74284 /* =======================================================  TMR0CMP0  ======================================================== */
74285 /* =======================================================  TMR0CMP1  ======================================================== */
74286 /* =========================================================  MODE0  ========================================================= */
74287 /* ============================================  TIMER MODE0 TMR0TRIGSEL [8..15]  ============================================ */
74288 typedef enum {                                  /*!< TIMER_MODE0_TMR0TRIGSEL                                                   */
74289   TIMER_MODE0_TMR0TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
74290   TIMER_MODE0_TMR0TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
74291   TIMER_MODE0_TMR0TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
74292   TIMER_MODE0_TMR0TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
74293   TIMER_MODE0_TMR0TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
74294   TIMER_MODE0_TMR0TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
74295   TIMER_MODE0_TMR0TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
74296   TIMER_MODE0_TMR0TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
74297   TIMER_MODE0_TMR0TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
74298   TIMER_MODE0_TMR0TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
74299   TIMER_MODE0_TMR0TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
74300   TIMER_MODE0_TMR0TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
74301   TIMER_MODE0_TMR0TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
74302   TIMER_MODE0_TMR0TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
74303   TIMER_MODE0_TMR0TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
74304   TIMER_MODE0_TMR0TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
74305   TIMER_MODE0_TMR0TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
74306   TIMER_MODE0_TMR0TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
74307   TIMER_MODE0_TMR0TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
74308   TIMER_MODE0_TMR0TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
74309   TIMER_MODE0_TMR0TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
74310   TIMER_MODE0_TMR0TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
74311   TIMER_MODE0_TMR0TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
74312   TIMER_MODE0_TMR0TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
74313   TIMER_MODE0_TMR0TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
74314   TIMER_MODE0_TMR0TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
74315   TIMER_MODE0_TMR0TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
74316   TIMER_MODE0_TMR0TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
74317   TIMER_MODE0_TMR0TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
74318   TIMER_MODE0_TMR0TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
74319   TIMER_MODE0_TMR0TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
74320   TIMER_MODE0_TMR0TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
74321   TIMER_MODE0_TMR0TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
74322   TIMER_MODE0_TMR0TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
74323   TIMER_MODE0_TMR0TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
74324   TIMER_MODE0_TMR0TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
74325   TIMER_MODE0_TMR0TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
74326   TIMER_MODE0_TMR0TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
74327   TIMER_MODE0_TMR0TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
74328   TIMER_MODE0_TMR0TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
74329   TIMER_MODE0_TMR0TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
74330   TIMER_MODE0_TMR0TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
74331   TIMER_MODE0_TMR0TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
74332   TIMER_MODE0_TMR0TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
74333   TIMER_MODE0_TMR0TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
74334   TIMER_MODE0_TMR0TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
74335   TIMER_MODE0_TMR0TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
74336   TIMER_MODE0_TMR0TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
74337   TIMER_MODE0_TMR0TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
74338   TIMER_MODE0_TMR0TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
74339 } TIMER_MODE0_TMR0TRIGSEL_Enum;
74340 
74341 /* =========================================================  CTRL1  ========================================================= */
74342 /* ============================================  TIMER CTRL1 TMR1TMODE [16..17]  ============================================= */
74343 typedef enum {                                  /*!< TIMER_CTRL1_TMR1TMODE                                                     */
74344   TIMER_CTRL1_TMR1TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
74345   TIMER_CTRL1_TMR1TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
74346   TIMER_CTRL1_TMR1TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
74347   TIMER_CTRL1_TMR1TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
74348 } TIMER_CTRL1_TMR1TMODE_Enum;
74349 
74350 /* ==============================================  TIMER CTRL1 TMR1CLK [8..15]  ============================================== */
74351 typedef enum {                                  /*!< TIMER_CTRL1_TMR1CLK                                                       */
74352   TIMER_CTRL1_TMR1CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
74353   TIMER_CTRL1_TMR1CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
74354   TIMER_CTRL1_TMR1CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
74355   TIMER_CTRL1_TMR1CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
74356   TIMER_CTRL1_TMR1CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
74357   TIMER_CTRL1_TMR1CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
74358   TIMER_CTRL1_TMR1CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
74359   TIMER_CTRL1_TMR1CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
74360   TIMER_CTRL1_TMR1CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
74361   TIMER_CTRL1_TMR1CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
74362   TIMER_CTRL1_TMR1CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
74363   TIMER_CTRL1_TMR1CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
74364   TIMER_CTRL1_TMR1CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
74365   TIMER_CTRL1_TMR1CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
74366   TIMER_CTRL1_TMR1CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
74367   TIMER_CTRL1_TMR1CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
74368   TIMER_CTRL1_TMR1CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
74369   TIMER_CTRL1_TMR1CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
74370   TIMER_CTRL1_TMR1CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
74371   TIMER_CTRL1_TMR1CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
74372   TIMER_CTRL1_TMR1CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
74373   TIMER_CTRL1_TMR1CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
74374   TIMER_CTRL1_TMR1CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
74375   TIMER_CTRL1_TMR1CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
74376   TIMER_CTRL1_TMR1CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
74377   TIMER_CTRL1_TMR1CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
74378   TIMER_CTRL1_TMR1CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
74379   TIMER_CTRL1_TMR1CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
74380   TIMER_CTRL1_TMR1CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
74381   TIMER_CTRL1_TMR1CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
74382   TIMER_CTRL1_TMR1CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
74383   TIMER_CTRL1_TMR1CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
74384   TIMER_CTRL1_TMR1CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
74385   TIMER_CTRL1_TMR1CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
74386   TIMER_CTRL1_TMR1CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
74387   TIMER_CTRL1_TMR1CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
74388   TIMER_CTRL1_TMR1CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
74389   TIMER_CTRL1_TMR1CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
74390   TIMER_CTRL1_TMR1CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
74391   TIMER_CTRL1_TMR1CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
74392   TIMER_CTRL1_TMR1CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
74393   TIMER_CTRL1_TMR1CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
74394   TIMER_CTRL1_TMR1CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
74395   TIMER_CTRL1_TMR1CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
74396   TIMER_CTRL1_TMR1CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
74397   TIMER_CTRL1_TMR1CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
74398   TIMER_CTRL1_TMR1CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
74399   TIMER_CTRL1_TMR1CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
74400   TIMER_CTRL1_TMR1CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
74401   TIMER_CTRL1_TMR1CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
74402   TIMER_CTRL1_TMR1CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
74403   TIMER_CTRL1_TMR1CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
74404   TIMER_CTRL1_TMR1CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
74405   TIMER_CTRL1_TMR1CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
74406   TIMER_CTRL1_TMR1CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
74407   TIMER_CTRL1_TMR1CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
74408   TIMER_CTRL1_TMR1CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
74409 } TIMER_CTRL1_TMR1CLK_Enum;
74410 
74411 /* ===============================================  TIMER CTRL1 TMR1FN [4..7]  =============================================== */
74412 typedef enum {                                  /*!< TIMER_CTRL1_TMR1FN                                                        */
74413   TIMER_CTRL1_TMR1FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
74414                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
74415   TIMER_CTRL1_TMR1FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
74416                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
74417                                                      follows CMP1.                                                             */
74418   TIMER_CTRL1_TMR1FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
74419                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
74420                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
74421   TIMER_CTRL1_TMR1FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
74422                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
74423   TIMER_CTRL1_TMR1FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
74424                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
74425                                                      and OUT[1] formed by TIMER>=CMPn                                          */
74426   TIMER_CTRL1_TMR1FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
74427                                                      LMT field specifies length of pattern. When LMT>32 OUT0
74428                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
74429                                                      is CMP1,CMP1                                                              */
74430   TIMER_CTRL1_TMR1FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
74431                                                      pattern repeats after reaching LMT.                                       */
74432   TIMER_CTRL1_TMR1FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
74433                                                      trigger until next edge (rising or falling) of source clock
74434                                                      (used as a secondary event). This can be used to measure
74435                                                      time betwen GPIOs, etc.                                                   */
74436 } TIMER_CTRL1_TMR1FN_Enum;
74437 
74438 /* ==============================================  TIMER CTRL1 TMR1POL1 [3..3]  ============================================== */
74439 typedef enum {                                  /*!< TIMER_CTRL1_TMR1POL1                                                      */
74440   TIMER_CTRL1_TMR1POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR1OUT1 pin is the same as the
74441                                                      timer output.                                                             */
74442   TIMER_CTRL1_TMR1POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR1OUT1 pin is the inverse of
74443                                                      the timer output.                                                         */
74444 } TIMER_CTRL1_TMR1POL1_Enum;
74445 
74446 /* ==============================================  TIMER CTRL1 TMR1POL0 [2..2]  ============================================== */
74447 typedef enum {                                  /*!< TIMER_CTRL1_TMR1POL0                                                      */
74448   TIMER_CTRL1_TMR1POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR1OUT0 pin is the same as the
74449                                                      timer output.                                                             */
74450   TIMER_CTRL1_TMR1POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR1OUT0 pin is the inverse of
74451                                                      the timer output.                                                         */
74452 } TIMER_CTRL1_TMR1POL0_Enum;
74453 
74454 /* ==============================================  TIMER CTRL1 TMR1CLR [1..1]  =============================================== */
74455 typedef enum {                                  /*!< TIMER_CTRL1_TMR1CLR                                                       */
74456   TIMER_CTRL1_TMR1CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
74457                                                      cleared to its reset state (0 for count up counter, CMP0
74458                                                      for down counter)                                                         */
74459 } TIMER_CTRL1_TMR1CLR_Enum;
74460 
74461 /* ===============================================  TIMER CTRL1 TMR1EN [0..0]  =============================================== */
74462 typedef enum {                                  /*!< TIMER_CTRL1_TMR1EN                                                        */
74463   TIMER_CTRL1_TMR1EN_DIS               = 0,     /*!< DIS : Counter/Timer 1 Disable.                                            */
74464   TIMER_CTRL1_TMR1EN_EN                = 1,     /*!< EN : Counter/Timer 1 Enable.                                              */
74465 } TIMER_CTRL1_TMR1EN_Enum;
74466 
74467 /* ========================================================  TIMER1  ========================================================= */
74468 /* =======================================================  TMR1CMP0  ======================================================== */
74469 /* =======================================================  TMR1CMP1  ======================================================== */
74470 /* =========================================================  MODE1  ========================================================= */
74471 /* ============================================  TIMER MODE1 TMR1TRIGSEL [8..15]  ============================================ */
74472 typedef enum {                                  /*!< TIMER_MODE1_TMR1TRIGSEL                                                   */
74473   TIMER_MODE1_TMR1TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
74474   TIMER_MODE1_TMR1TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
74475   TIMER_MODE1_TMR1TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
74476   TIMER_MODE1_TMR1TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
74477   TIMER_MODE1_TMR1TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
74478   TIMER_MODE1_TMR1TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
74479   TIMER_MODE1_TMR1TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
74480   TIMER_MODE1_TMR1TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
74481   TIMER_MODE1_TMR1TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
74482   TIMER_MODE1_TMR1TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
74483   TIMER_MODE1_TMR1TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
74484   TIMER_MODE1_TMR1TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
74485   TIMER_MODE1_TMR1TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
74486   TIMER_MODE1_TMR1TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
74487   TIMER_MODE1_TMR1TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
74488   TIMER_MODE1_TMR1TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
74489   TIMER_MODE1_TMR1TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
74490   TIMER_MODE1_TMR1TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
74491   TIMER_MODE1_TMR1TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
74492   TIMER_MODE1_TMR1TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
74493   TIMER_MODE1_TMR1TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
74494   TIMER_MODE1_TMR1TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
74495   TIMER_MODE1_TMR1TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
74496   TIMER_MODE1_TMR1TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
74497   TIMER_MODE1_TMR1TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
74498   TIMER_MODE1_TMR1TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
74499   TIMER_MODE1_TMR1TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
74500   TIMER_MODE1_TMR1TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
74501   TIMER_MODE1_TMR1TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
74502   TIMER_MODE1_TMR1TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
74503   TIMER_MODE1_TMR1TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
74504   TIMER_MODE1_TMR1TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
74505   TIMER_MODE1_TMR1TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
74506   TIMER_MODE1_TMR1TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
74507   TIMER_MODE1_TMR1TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
74508   TIMER_MODE1_TMR1TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
74509   TIMER_MODE1_TMR1TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
74510   TIMER_MODE1_TMR1TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
74511   TIMER_MODE1_TMR1TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
74512   TIMER_MODE1_TMR1TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
74513   TIMER_MODE1_TMR1TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
74514   TIMER_MODE1_TMR1TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
74515   TIMER_MODE1_TMR1TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
74516   TIMER_MODE1_TMR1TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
74517   TIMER_MODE1_TMR1TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
74518   TIMER_MODE1_TMR1TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
74519   TIMER_MODE1_TMR1TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
74520   TIMER_MODE1_TMR1TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
74521   TIMER_MODE1_TMR1TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
74522   TIMER_MODE1_TMR1TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
74523 } TIMER_MODE1_TMR1TRIGSEL_Enum;
74524 
74525 /* =========================================================  CTRL2  ========================================================= */
74526 /* ============================================  TIMER CTRL2 TMR2TMODE [16..17]  ============================================= */
74527 typedef enum {                                  /*!< TIMER_CTRL2_TMR2TMODE                                                     */
74528   TIMER_CTRL2_TMR2TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
74529   TIMER_CTRL2_TMR2TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
74530   TIMER_CTRL2_TMR2TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
74531   TIMER_CTRL2_TMR2TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
74532 } TIMER_CTRL2_TMR2TMODE_Enum;
74533 
74534 /* ==============================================  TIMER CTRL2 TMR2CLK [8..15]  ============================================== */
74535 typedef enum {                                  /*!< TIMER_CTRL2_TMR2CLK                                                       */
74536   TIMER_CTRL2_TMR2CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
74537   TIMER_CTRL2_TMR2CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
74538   TIMER_CTRL2_TMR2CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
74539   TIMER_CTRL2_TMR2CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
74540   TIMER_CTRL2_TMR2CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
74541   TIMER_CTRL2_TMR2CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
74542   TIMER_CTRL2_TMR2CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
74543   TIMER_CTRL2_TMR2CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
74544   TIMER_CTRL2_TMR2CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
74545   TIMER_CTRL2_TMR2CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
74546   TIMER_CTRL2_TMR2CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
74547   TIMER_CTRL2_TMR2CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
74548   TIMER_CTRL2_TMR2CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
74549   TIMER_CTRL2_TMR2CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
74550   TIMER_CTRL2_TMR2CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
74551   TIMER_CTRL2_TMR2CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
74552   TIMER_CTRL2_TMR2CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
74553   TIMER_CTRL2_TMR2CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
74554   TIMER_CTRL2_TMR2CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
74555   TIMER_CTRL2_TMR2CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
74556   TIMER_CTRL2_TMR2CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
74557   TIMER_CTRL2_TMR2CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
74558   TIMER_CTRL2_TMR2CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
74559   TIMER_CTRL2_TMR2CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
74560   TIMER_CTRL2_TMR2CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
74561   TIMER_CTRL2_TMR2CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
74562   TIMER_CTRL2_TMR2CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
74563   TIMER_CTRL2_TMR2CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
74564   TIMER_CTRL2_TMR2CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
74565   TIMER_CTRL2_TMR2CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
74566   TIMER_CTRL2_TMR2CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
74567   TIMER_CTRL2_TMR2CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
74568   TIMER_CTRL2_TMR2CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
74569   TIMER_CTRL2_TMR2CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
74570   TIMER_CTRL2_TMR2CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
74571   TIMER_CTRL2_TMR2CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
74572   TIMER_CTRL2_TMR2CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
74573   TIMER_CTRL2_TMR2CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
74574   TIMER_CTRL2_TMR2CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
74575   TIMER_CTRL2_TMR2CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
74576   TIMER_CTRL2_TMR2CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
74577   TIMER_CTRL2_TMR2CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
74578   TIMER_CTRL2_TMR2CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
74579   TIMER_CTRL2_TMR2CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
74580   TIMER_CTRL2_TMR2CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
74581   TIMER_CTRL2_TMR2CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
74582   TIMER_CTRL2_TMR2CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
74583   TIMER_CTRL2_TMR2CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
74584   TIMER_CTRL2_TMR2CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
74585   TIMER_CTRL2_TMR2CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
74586   TIMER_CTRL2_TMR2CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
74587   TIMER_CTRL2_TMR2CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
74588   TIMER_CTRL2_TMR2CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
74589   TIMER_CTRL2_TMR2CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
74590   TIMER_CTRL2_TMR2CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
74591   TIMER_CTRL2_TMR2CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
74592   TIMER_CTRL2_TMR2CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
74593 } TIMER_CTRL2_TMR2CLK_Enum;
74594 
74595 /* ===============================================  TIMER CTRL2 TMR2FN [4..7]  =============================================== */
74596 typedef enum {                                  /*!< TIMER_CTRL2_TMR2FN                                                        */
74597   TIMER_CTRL2_TMR2FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
74598                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
74599   TIMER_CTRL2_TMR2FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
74600                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
74601                                                      follows CMP1.                                                             */
74602   TIMER_CTRL2_TMR2FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
74603                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
74604                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
74605   TIMER_CTRL2_TMR2FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
74606                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
74607   TIMER_CTRL2_TMR2FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
74608                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
74609                                                      and OUT[1] formed by TIMER>=CMPn                                          */
74610   TIMER_CTRL2_TMR2FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
74611                                                      LMT field specifies length of pattern. When LMT>32 OUT0
74612                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
74613                                                      is CMP1,CMP1                                                              */
74614   TIMER_CTRL2_TMR2FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
74615                                                      pattern repeats after reaching LMT.                                       */
74616   TIMER_CTRL2_TMR2FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
74617                                                      trigger until next edge (rising or falling) of source clock
74618                                                      (used as a secondary event). This can be used to measure
74619                                                      time betwen GPIOs, etc.                                                   */
74620 } TIMER_CTRL2_TMR2FN_Enum;
74621 
74622 /* ==============================================  TIMER CTRL2 TMR2POL1 [3..3]  ============================================== */
74623 typedef enum {                                  /*!< TIMER_CTRL2_TMR2POL1                                                      */
74624   TIMER_CTRL2_TMR2POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR2OUT1 pin is the same as the
74625                                                      timer output.                                                             */
74626   TIMER_CTRL2_TMR2POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR2OUT1 pin is the inverse of
74627                                                      the timer output.                                                         */
74628 } TIMER_CTRL2_TMR2POL1_Enum;
74629 
74630 /* ==============================================  TIMER CTRL2 TMR2POL0 [2..2]  ============================================== */
74631 typedef enum {                                  /*!< TIMER_CTRL2_TMR2POL0                                                      */
74632   TIMER_CTRL2_TMR2POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR2OUT0 pin is the same as the
74633                                                      timer output.                                                             */
74634   TIMER_CTRL2_TMR2POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR2OUT0 pin is the inverse of
74635                                                      the timer output.                                                         */
74636 } TIMER_CTRL2_TMR2POL0_Enum;
74637 
74638 /* ==============================================  TIMER CTRL2 TMR2CLR [1..1]  =============================================== */
74639 typedef enum {                                  /*!< TIMER_CTRL2_TMR2CLR                                                       */
74640   TIMER_CTRL2_TMR2CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
74641                                                      cleared to its reset state (0 for count up counter, CMP0
74642                                                      for down counter)                                                         */
74643 } TIMER_CTRL2_TMR2CLR_Enum;
74644 
74645 /* ===============================================  TIMER CTRL2 TMR2EN [0..0]  =============================================== */
74646 typedef enum {                                  /*!< TIMER_CTRL2_TMR2EN                                                        */
74647   TIMER_CTRL2_TMR2EN_DIS               = 0,     /*!< DIS : Counter/Timer 2 Disable.                                            */
74648   TIMER_CTRL2_TMR2EN_EN                = 1,     /*!< EN : Counter/Timer 2 Enable.                                              */
74649 } TIMER_CTRL2_TMR2EN_Enum;
74650 
74651 /* ========================================================  TIMER2  ========================================================= */
74652 /* =======================================================  TMR2CMP0  ======================================================== */
74653 /* =======================================================  TMR2CMP1  ======================================================== */
74654 /* =========================================================  MODE2  ========================================================= */
74655 /* ============================================  TIMER MODE2 TMR2TRIGSEL [8..15]  ============================================ */
74656 typedef enum {                                  /*!< TIMER_MODE2_TMR2TRIGSEL                                                   */
74657   TIMER_MODE2_TMR2TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
74658   TIMER_MODE2_TMR2TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
74659   TIMER_MODE2_TMR2TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
74660   TIMER_MODE2_TMR2TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
74661   TIMER_MODE2_TMR2TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
74662   TIMER_MODE2_TMR2TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
74663   TIMER_MODE2_TMR2TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
74664   TIMER_MODE2_TMR2TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
74665   TIMER_MODE2_TMR2TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
74666   TIMER_MODE2_TMR2TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
74667   TIMER_MODE2_TMR2TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
74668   TIMER_MODE2_TMR2TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
74669   TIMER_MODE2_TMR2TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
74670   TIMER_MODE2_TMR2TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
74671   TIMER_MODE2_TMR2TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
74672   TIMER_MODE2_TMR2TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
74673   TIMER_MODE2_TMR2TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
74674   TIMER_MODE2_TMR2TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
74675   TIMER_MODE2_TMR2TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
74676   TIMER_MODE2_TMR2TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
74677   TIMER_MODE2_TMR2TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
74678   TIMER_MODE2_TMR2TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
74679   TIMER_MODE2_TMR2TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
74680   TIMER_MODE2_TMR2TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
74681   TIMER_MODE2_TMR2TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
74682   TIMER_MODE2_TMR2TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
74683   TIMER_MODE2_TMR2TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
74684   TIMER_MODE2_TMR2TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
74685   TIMER_MODE2_TMR2TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
74686   TIMER_MODE2_TMR2TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
74687   TIMER_MODE2_TMR2TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
74688   TIMER_MODE2_TMR2TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
74689   TIMER_MODE2_TMR2TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
74690   TIMER_MODE2_TMR2TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
74691   TIMER_MODE2_TMR2TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
74692   TIMER_MODE2_TMR2TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
74693   TIMER_MODE2_TMR2TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
74694   TIMER_MODE2_TMR2TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
74695   TIMER_MODE2_TMR2TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
74696   TIMER_MODE2_TMR2TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
74697   TIMER_MODE2_TMR2TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
74698   TIMER_MODE2_TMR2TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
74699   TIMER_MODE2_TMR2TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
74700   TIMER_MODE2_TMR2TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
74701   TIMER_MODE2_TMR2TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
74702   TIMER_MODE2_TMR2TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
74703   TIMER_MODE2_TMR2TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
74704   TIMER_MODE2_TMR2TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
74705   TIMER_MODE2_TMR2TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
74706   TIMER_MODE2_TMR2TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
74707 } TIMER_MODE2_TMR2TRIGSEL_Enum;
74708 
74709 /* =========================================================  CTRL3  ========================================================= */
74710 /* ============================================  TIMER CTRL3 TMR3TMODE [16..17]  ============================================= */
74711 typedef enum {                                  /*!< TIMER_CTRL3_TMR3TMODE                                                     */
74712   TIMER_CTRL3_TMR3TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
74713   TIMER_CTRL3_TMR3TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
74714   TIMER_CTRL3_TMR3TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
74715   TIMER_CTRL3_TMR3TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
74716 } TIMER_CTRL3_TMR3TMODE_Enum;
74717 
74718 /* ==============================================  TIMER CTRL3 TMR3CLK [8..15]  ============================================== */
74719 typedef enum {                                  /*!< TIMER_CTRL3_TMR3CLK                                                       */
74720   TIMER_CTRL3_TMR3CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
74721   TIMER_CTRL3_TMR3CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
74722   TIMER_CTRL3_TMR3CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
74723   TIMER_CTRL3_TMR3CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
74724   TIMER_CTRL3_TMR3CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
74725   TIMER_CTRL3_TMR3CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
74726   TIMER_CTRL3_TMR3CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
74727   TIMER_CTRL3_TMR3CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
74728   TIMER_CTRL3_TMR3CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
74729   TIMER_CTRL3_TMR3CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
74730   TIMER_CTRL3_TMR3CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
74731   TIMER_CTRL3_TMR3CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
74732   TIMER_CTRL3_TMR3CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
74733   TIMER_CTRL3_TMR3CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
74734   TIMER_CTRL3_TMR3CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
74735   TIMER_CTRL3_TMR3CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
74736   TIMER_CTRL3_TMR3CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
74737   TIMER_CTRL3_TMR3CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
74738   TIMER_CTRL3_TMR3CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
74739   TIMER_CTRL3_TMR3CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
74740   TIMER_CTRL3_TMR3CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
74741   TIMER_CTRL3_TMR3CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
74742   TIMER_CTRL3_TMR3CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
74743   TIMER_CTRL3_TMR3CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
74744   TIMER_CTRL3_TMR3CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
74745   TIMER_CTRL3_TMR3CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
74746   TIMER_CTRL3_TMR3CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
74747   TIMER_CTRL3_TMR3CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
74748   TIMER_CTRL3_TMR3CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
74749   TIMER_CTRL3_TMR3CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
74750   TIMER_CTRL3_TMR3CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
74751   TIMER_CTRL3_TMR3CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
74752   TIMER_CTRL3_TMR3CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
74753   TIMER_CTRL3_TMR3CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
74754   TIMER_CTRL3_TMR3CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
74755   TIMER_CTRL3_TMR3CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
74756   TIMER_CTRL3_TMR3CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
74757   TIMER_CTRL3_TMR3CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
74758   TIMER_CTRL3_TMR3CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
74759   TIMER_CTRL3_TMR3CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
74760   TIMER_CTRL3_TMR3CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
74761   TIMER_CTRL3_TMR3CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
74762   TIMER_CTRL3_TMR3CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
74763   TIMER_CTRL3_TMR3CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
74764   TIMER_CTRL3_TMR3CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
74765   TIMER_CTRL3_TMR3CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
74766   TIMER_CTRL3_TMR3CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
74767   TIMER_CTRL3_TMR3CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
74768   TIMER_CTRL3_TMR3CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
74769   TIMER_CTRL3_TMR3CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
74770   TIMER_CTRL3_TMR3CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
74771   TIMER_CTRL3_TMR3CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
74772   TIMER_CTRL3_TMR3CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
74773   TIMER_CTRL3_TMR3CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
74774   TIMER_CTRL3_TMR3CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
74775   TIMER_CTRL3_TMR3CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
74776   TIMER_CTRL3_TMR3CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
74777 } TIMER_CTRL3_TMR3CLK_Enum;
74778 
74779 /* ===============================================  TIMER CTRL3 TMR3FN [4..7]  =============================================== */
74780 typedef enum {                                  /*!< TIMER_CTRL3_TMR3FN                                                        */
74781   TIMER_CTRL3_TMR3FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
74782                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
74783   TIMER_CTRL3_TMR3FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
74784                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
74785                                                      follows CMP1.                                                             */
74786   TIMER_CTRL3_TMR3FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
74787                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
74788                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
74789   TIMER_CTRL3_TMR3FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
74790                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
74791   TIMER_CTRL3_TMR3FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
74792                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
74793                                                      and OUT[1] formed by TIMER>=CMPn                                          */
74794   TIMER_CTRL3_TMR3FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
74795                                                      LMT field specifies length of pattern. When LMT>32 OUT0
74796                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
74797                                                      is CMP1,CMP1                                                              */
74798   TIMER_CTRL3_TMR3FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
74799                                                      pattern repeats after reaching LMT.                                       */
74800   TIMER_CTRL3_TMR3FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
74801                                                      trigger until next edge (rising or falling) of source clock
74802                                                      (used as a secondary event). This can be used to measure
74803                                                      time betwen GPIOs, etc.                                                   */
74804 } TIMER_CTRL3_TMR3FN_Enum;
74805 
74806 /* ==============================================  TIMER CTRL3 TMR3POL1 [3..3]  ============================================== */
74807 typedef enum {                                  /*!< TIMER_CTRL3_TMR3POL1                                                      */
74808   TIMER_CTRL3_TMR3POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR3OUT1 pin is the same as the
74809                                                      timer output.                                                             */
74810   TIMER_CTRL3_TMR3POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR3OUT1 pin is the inverse of
74811                                                      the timer output.                                                         */
74812 } TIMER_CTRL3_TMR3POL1_Enum;
74813 
74814 /* ==============================================  TIMER CTRL3 TMR3POL0 [2..2]  ============================================== */
74815 typedef enum {                                  /*!< TIMER_CTRL3_TMR3POL0                                                      */
74816   TIMER_CTRL3_TMR3POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR3OUT0 pin is the same as the
74817                                                      timer output.                                                             */
74818   TIMER_CTRL3_TMR3POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR3OUT0 pin is the inverse of
74819                                                      the timer output.                                                         */
74820 } TIMER_CTRL3_TMR3POL0_Enum;
74821 
74822 /* ==============================================  TIMER CTRL3 TMR3CLR [1..1]  =============================================== */
74823 typedef enum {                                  /*!< TIMER_CTRL3_TMR3CLR                                                       */
74824   TIMER_CTRL3_TMR3CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
74825                                                      cleared to its reset state (0 for count up counter, CMP0
74826                                                      for down counter)                                                         */
74827 } TIMER_CTRL3_TMR3CLR_Enum;
74828 
74829 /* ===============================================  TIMER CTRL3 TMR3EN [0..0]  =============================================== */
74830 typedef enum {                                  /*!< TIMER_CTRL3_TMR3EN                                                        */
74831   TIMER_CTRL3_TMR3EN_DIS               = 0,     /*!< DIS : Counter/Timer 3 Disable.                                            */
74832   TIMER_CTRL3_TMR3EN_EN                = 1,     /*!< EN : Counter/Timer 3 Enable.                                              */
74833 } TIMER_CTRL3_TMR3EN_Enum;
74834 
74835 /* ========================================================  TIMER3  ========================================================= */
74836 /* =======================================================  TMR3CMP0  ======================================================== */
74837 /* =======================================================  TMR3CMP1  ======================================================== */
74838 /* =========================================================  MODE3  ========================================================= */
74839 /* ============================================  TIMER MODE3 TMR3TRIGSEL [8..15]  ============================================ */
74840 typedef enum {                                  /*!< TIMER_MODE3_TMR3TRIGSEL                                                   */
74841   TIMER_MODE3_TMR3TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
74842   TIMER_MODE3_TMR3TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
74843   TIMER_MODE3_TMR3TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
74844   TIMER_MODE3_TMR3TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
74845   TIMER_MODE3_TMR3TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
74846   TIMER_MODE3_TMR3TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
74847   TIMER_MODE3_TMR3TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
74848   TIMER_MODE3_TMR3TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
74849   TIMER_MODE3_TMR3TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
74850   TIMER_MODE3_TMR3TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
74851   TIMER_MODE3_TMR3TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
74852   TIMER_MODE3_TMR3TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
74853   TIMER_MODE3_TMR3TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
74854   TIMER_MODE3_TMR3TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
74855   TIMER_MODE3_TMR3TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
74856   TIMER_MODE3_TMR3TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
74857   TIMER_MODE3_TMR3TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
74858   TIMER_MODE3_TMR3TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
74859   TIMER_MODE3_TMR3TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
74860   TIMER_MODE3_TMR3TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
74861   TIMER_MODE3_TMR3TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
74862   TIMER_MODE3_TMR3TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
74863   TIMER_MODE3_TMR3TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
74864   TIMER_MODE3_TMR3TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
74865   TIMER_MODE3_TMR3TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
74866   TIMER_MODE3_TMR3TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
74867   TIMER_MODE3_TMR3TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
74868   TIMER_MODE3_TMR3TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
74869   TIMER_MODE3_TMR3TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
74870   TIMER_MODE3_TMR3TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
74871   TIMER_MODE3_TMR3TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
74872   TIMER_MODE3_TMR3TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
74873   TIMER_MODE3_TMR3TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
74874   TIMER_MODE3_TMR3TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
74875   TIMER_MODE3_TMR3TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
74876   TIMER_MODE3_TMR3TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
74877   TIMER_MODE3_TMR3TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
74878   TIMER_MODE3_TMR3TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
74879   TIMER_MODE3_TMR3TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
74880   TIMER_MODE3_TMR3TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
74881   TIMER_MODE3_TMR3TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
74882   TIMER_MODE3_TMR3TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
74883   TIMER_MODE3_TMR3TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
74884   TIMER_MODE3_TMR3TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
74885   TIMER_MODE3_TMR3TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
74886   TIMER_MODE3_TMR3TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
74887   TIMER_MODE3_TMR3TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
74888   TIMER_MODE3_TMR3TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
74889   TIMER_MODE3_TMR3TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
74890   TIMER_MODE3_TMR3TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
74891 } TIMER_MODE3_TMR3TRIGSEL_Enum;
74892 
74893 /* =========================================================  CTRL4  ========================================================= */
74894 /* ============================================  TIMER CTRL4 TMR4TMODE [16..17]  ============================================= */
74895 typedef enum {                                  /*!< TIMER_CTRL4_TMR4TMODE                                                     */
74896   TIMER_CTRL4_TMR4TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
74897   TIMER_CTRL4_TMR4TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
74898   TIMER_CTRL4_TMR4TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
74899   TIMER_CTRL4_TMR4TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
74900 } TIMER_CTRL4_TMR4TMODE_Enum;
74901 
74902 /* ==============================================  TIMER CTRL4 TMR4CLK [8..15]  ============================================== */
74903 typedef enum {                                  /*!< TIMER_CTRL4_TMR4CLK                                                       */
74904   TIMER_CTRL4_TMR4CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
74905   TIMER_CTRL4_TMR4CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
74906   TIMER_CTRL4_TMR4CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
74907   TIMER_CTRL4_TMR4CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
74908   TIMER_CTRL4_TMR4CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
74909   TIMER_CTRL4_TMR4CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
74910   TIMER_CTRL4_TMR4CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
74911   TIMER_CTRL4_TMR4CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
74912   TIMER_CTRL4_TMR4CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
74913   TIMER_CTRL4_TMR4CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
74914   TIMER_CTRL4_TMR4CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
74915   TIMER_CTRL4_TMR4CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
74916   TIMER_CTRL4_TMR4CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
74917   TIMER_CTRL4_TMR4CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
74918   TIMER_CTRL4_TMR4CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
74919   TIMER_CTRL4_TMR4CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
74920   TIMER_CTRL4_TMR4CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
74921   TIMER_CTRL4_TMR4CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
74922   TIMER_CTRL4_TMR4CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
74923   TIMER_CTRL4_TMR4CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
74924   TIMER_CTRL4_TMR4CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
74925   TIMER_CTRL4_TMR4CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
74926   TIMER_CTRL4_TMR4CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
74927   TIMER_CTRL4_TMR4CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
74928   TIMER_CTRL4_TMR4CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
74929   TIMER_CTRL4_TMR4CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
74930   TIMER_CTRL4_TMR4CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
74931   TIMER_CTRL4_TMR4CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
74932   TIMER_CTRL4_TMR4CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
74933   TIMER_CTRL4_TMR4CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
74934   TIMER_CTRL4_TMR4CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
74935   TIMER_CTRL4_TMR4CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
74936   TIMER_CTRL4_TMR4CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
74937   TIMER_CTRL4_TMR4CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
74938   TIMER_CTRL4_TMR4CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
74939   TIMER_CTRL4_TMR4CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
74940   TIMER_CTRL4_TMR4CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
74941   TIMER_CTRL4_TMR4CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
74942   TIMER_CTRL4_TMR4CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
74943   TIMER_CTRL4_TMR4CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
74944   TIMER_CTRL4_TMR4CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
74945   TIMER_CTRL4_TMR4CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
74946   TIMER_CTRL4_TMR4CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
74947   TIMER_CTRL4_TMR4CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
74948   TIMER_CTRL4_TMR4CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
74949   TIMER_CTRL4_TMR4CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
74950   TIMER_CTRL4_TMR4CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
74951   TIMER_CTRL4_TMR4CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
74952   TIMER_CTRL4_TMR4CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
74953   TIMER_CTRL4_TMR4CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
74954   TIMER_CTRL4_TMR4CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
74955   TIMER_CTRL4_TMR4CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
74956   TIMER_CTRL4_TMR4CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
74957   TIMER_CTRL4_TMR4CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
74958   TIMER_CTRL4_TMR4CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
74959   TIMER_CTRL4_TMR4CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
74960   TIMER_CTRL4_TMR4CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
74961 } TIMER_CTRL4_TMR4CLK_Enum;
74962 
74963 /* ===============================================  TIMER CTRL4 TMR4FN [4..7]  =============================================== */
74964 typedef enum {                                  /*!< TIMER_CTRL4_TMR4FN                                                        */
74965   TIMER_CTRL4_TMR4FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
74966                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
74967   TIMER_CTRL4_TMR4FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
74968                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
74969                                                      follows CMP1.                                                             */
74970   TIMER_CTRL4_TMR4FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
74971                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
74972                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
74973   TIMER_CTRL4_TMR4FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
74974                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
74975   TIMER_CTRL4_TMR4FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
74976                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
74977                                                      and OUT[1] formed by TIMER>=CMPn                                          */
74978   TIMER_CTRL4_TMR4FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
74979                                                      LMT field specifies length of pattern. When LMT>32 OUT0
74980                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
74981                                                      is CMP1,CMP1                                                              */
74982   TIMER_CTRL4_TMR4FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
74983                                                      pattern repeats after reaching LMT.                                       */
74984   TIMER_CTRL4_TMR4FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
74985                                                      trigger until next edge (rising or falling) of source clock
74986                                                      (used as a secondary event). This can be used to measure
74987                                                      time betwen GPIOs, etc.                                                   */
74988 } TIMER_CTRL4_TMR4FN_Enum;
74989 
74990 /* ==============================================  TIMER CTRL4 TMR4POL1 [3..3]  ============================================== */
74991 typedef enum {                                  /*!< TIMER_CTRL4_TMR4POL1                                                      */
74992   TIMER_CTRL4_TMR4POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR4OUT1 pin is the same as the
74993                                                      timer output.                                                             */
74994   TIMER_CTRL4_TMR4POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR4OUT1 pin is the inverse of
74995                                                      the timer output.                                                         */
74996 } TIMER_CTRL4_TMR4POL1_Enum;
74997 
74998 /* ==============================================  TIMER CTRL4 TMR4POL0 [2..2]  ============================================== */
74999 typedef enum {                                  /*!< TIMER_CTRL4_TMR4POL0                                                      */
75000   TIMER_CTRL4_TMR4POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR4OUT0 pin is the same as the
75001                                                      timer output.                                                             */
75002   TIMER_CTRL4_TMR4POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR4OUT0 pin is the inverse of
75003                                                      the timer output.                                                         */
75004 } TIMER_CTRL4_TMR4POL0_Enum;
75005 
75006 /* ==============================================  TIMER CTRL4 TMR4CLR [1..1]  =============================================== */
75007 typedef enum {                                  /*!< TIMER_CTRL4_TMR4CLR                                                       */
75008   TIMER_CTRL4_TMR4CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75009                                                      cleared to its reset state (0 for count up counter, CMP0
75010                                                      for down counter)                                                         */
75011 } TIMER_CTRL4_TMR4CLR_Enum;
75012 
75013 /* ===============================================  TIMER CTRL4 TMR4EN [0..0]  =============================================== */
75014 typedef enum {                                  /*!< TIMER_CTRL4_TMR4EN                                                        */
75015   TIMER_CTRL4_TMR4EN_DIS               = 0,     /*!< DIS : Counter/Timer 4 Disable.                                            */
75016   TIMER_CTRL4_TMR4EN_EN                = 1,     /*!< EN : Counter/Timer 4 Enable.                                              */
75017 } TIMER_CTRL4_TMR4EN_Enum;
75018 
75019 /* ========================================================  TIMER4  ========================================================= */
75020 /* =======================================================  TMR4CMP0  ======================================================== */
75021 /* =======================================================  TMR4CMP1  ======================================================== */
75022 /* =========================================================  MODE4  ========================================================= */
75023 /* ============================================  TIMER MODE4 TMR4TRIGSEL [8..15]  ============================================ */
75024 typedef enum {                                  /*!< TIMER_MODE4_TMR4TRIGSEL                                                   */
75025   TIMER_MODE4_TMR4TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75026   TIMER_MODE4_TMR4TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75027   TIMER_MODE4_TMR4TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75028   TIMER_MODE4_TMR4TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75029   TIMER_MODE4_TMR4TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75030   TIMER_MODE4_TMR4TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75031   TIMER_MODE4_TMR4TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75032   TIMER_MODE4_TMR4TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75033   TIMER_MODE4_TMR4TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75034   TIMER_MODE4_TMR4TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75035   TIMER_MODE4_TMR4TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75036   TIMER_MODE4_TMR4TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75037   TIMER_MODE4_TMR4TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75038   TIMER_MODE4_TMR4TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75039   TIMER_MODE4_TMR4TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75040   TIMER_MODE4_TMR4TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75041   TIMER_MODE4_TMR4TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75042   TIMER_MODE4_TMR4TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75043   TIMER_MODE4_TMR4TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75044   TIMER_MODE4_TMR4TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75045   TIMER_MODE4_TMR4TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75046   TIMER_MODE4_TMR4TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75047   TIMER_MODE4_TMR4TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75048   TIMER_MODE4_TMR4TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75049   TIMER_MODE4_TMR4TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75050   TIMER_MODE4_TMR4TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75051   TIMER_MODE4_TMR4TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75052   TIMER_MODE4_TMR4TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75053   TIMER_MODE4_TMR4TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75054   TIMER_MODE4_TMR4TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75055   TIMER_MODE4_TMR4TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75056   TIMER_MODE4_TMR4TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75057   TIMER_MODE4_TMR4TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
75058   TIMER_MODE4_TMR4TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
75059   TIMER_MODE4_TMR4TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
75060   TIMER_MODE4_TMR4TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
75061   TIMER_MODE4_TMR4TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
75062   TIMER_MODE4_TMR4TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
75063   TIMER_MODE4_TMR4TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
75064   TIMER_MODE4_TMR4TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
75065   TIMER_MODE4_TMR4TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
75066   TIMER_MODE4_TMR4TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
75067   TIMER_MODE4_TMR4TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
75068   TIMER_MODE4_TMR4TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
75069   TIMER_MODE4_TMR4TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
75070   TIMER_MODE4_TMR4TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
75071   TIMER_MODE4_TMR4TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
75072   TIMER_MODE4_TMR4TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
75073   TIMER_MODE4_TMR4TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75074   TIMER_MODE4_TMR4TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75075 } TIMER_MODE4_TMR4TRIGSEL_Enum;
75076 
75077 /* =========================================================  CTRL5  ========================================================= */
75078 /* ============================================  TIMER CTRL5 TMR5TMODE [16..17]  ============================================= */
75079 typedef enum {                                  /*!< TIMER_CTRL5_TMR5TMODE                                                     */
75080   TIMER_CTRL5_TMR5TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75081   TIMER_CTRL5_TMR5TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75082   TIMER_CTRL5_TMR5TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75083   TIMER_CTRL5_TMR5TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75084 } TIMER_CTRL5_TMR5TMODE_Enum;
75085 
75086 /* ==============================================  TIMER CTRL5 TMR5CLK [8..15]  ============================================== */
75087 typedef enum {                                  /*!< TIMER_CTRL5_TMR5CLK                                                       */
75088   TIMER_CTRL5_TMR5CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75089   TIMER_CTRL5_TMR5CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75090   TIMER_CTRL5_TMR5CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75091   TIMER_CTRL5_TMR5CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75092   TIMER_CTRL5_TMR5CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75093   TIMER_CTRL5_TMR5CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75094   TIMER_CTRL5_TMR5CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75095   TIMER_CTRL5_TMR5CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75096   TIMER_CTRL5_TMR5CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75097   TIMER_CTRL5_TMR5CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75098   TIMER_CTRL5_TMR5CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75099   TIMER_CTRL5_TMR5CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75100   TIMER_CTRL5_TMR5CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75101   TIMER_CTRL5_TMR5CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75102   TIMER_CTRL5_TMR5CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75103   TIMER_CTRL5_TMR5CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75104   TIMER_CTRL5_TMR5CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75105   TIMER_CTRL5_TMR5CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75106   TIMER_CTRL5_TMR5CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75107   TIMER_CTRL5_TMR5CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75108   TIMER_CTRL5_TMR5CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75109   TIMER_CTRL5_TMR5CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75110   TIMER_CTRL5_TMR5CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75111   TIMER_CTRL5_TMR5CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75112   TIMER_CTRL5_TMR5CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75113   TIMER_CTRL5_TMR5CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75114   TIMER_CTRL5_TMR5CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75115   TIMER_CTRL5_TMR5CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75116   TIMER_CTRL5_TMR5CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75117   TIMER_CTRL5_TMR5CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75118   TIMER_CTRL5_TMR5CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75119   TIMER_CTRL5_TMR5CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75120   TIMER_CTRL5_TMR5CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75121   TIMER_CTRL5_TMR5CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75122   TIMER_CTRL5_TMR5CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75123   TIMER_CTRL5_TMR5CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75124   TIMER_CTRL5_TMR5CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75125   TIMER_CTRL5_TMR5CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75126   TIMER_CTRL5_TMR5CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75127   TIMER_CTRL5_TMR5CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75128   TIMER_CTRL5_TMR5CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75129   TIMER_CTRL5_TMR5CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75130   TIMER_CTRL5_TMR5CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75131   TIMER_CTRL5_TMR5CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75132   TIMER_CTRL5_TMR5CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75133   TIMER_CTRL5_TMR5CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75134   TIMER_CTRL5_TMR5CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75135   TIMER_CTRL5_TMR5CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75136   TIMER_CTRL5_TMR5CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75137   TIMER_CTRL5_TMR5CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75138   TIMER_CTRL5_TMR5CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75139   TIMER_CTRL5_TMR5CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75140   TIMER_CTRL5_TMR5CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75141   TIMER_CTRL5_TMR5CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75142   TIMER_CTRL5_TMR5CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75143   TIMER_CTRL5_TMR5CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75144   TIMER_CTRL5_TMR5CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75145 } TIMER_CTRL5_TMR5CLK_Enum;
75146 
75147 /* ===============================================  TIMER CTRL5 TMR5FN [4..7]  =============================================== */
75148 typedef enum {                                  /*!< TIMER_CTRL5_TMR5FN                                                        */
75149   TIMER_CTRL5_TMR5FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
75150                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
75151   TIMER_CTRL5_TMR5FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
75152                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
75153                                                      follows CMP1.                                                             */
75154   TIMER_CTRL5_TMR5FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
75155                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
75156                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
75157   TIMER_CTRL5_TMR5FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
75158                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
75159   TIMER_CTRL5_TMR5FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
75160                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
75161                                                      and OUT[1] formed by TIMER>=CMPn                                          */
75162   TIMER_CTRL5_TMR5FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75163                                                      LMT field specifies length of pattern. When LMT>32 OUT0
75164                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
75165                                                      is CMP1,CMP1                                                              */
75166   TIMER_CTRL5_TMR5FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75167                                                      pattern repeats after reaching LMT.                                       */
75168   TIMER_CTRL5_TMR5FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
75169                                                      trigger until next edge (rising or falling) of source clock
75170                                                      (used as a secondary event). This can be used to measure
75171                                                      time betwen GPIOs, etc.                                                   */
75172 } TIMER_CTRL5_TMR5FN_Enum;
75173 
75174 /* ==============================================  TIMER CTRL5 TMR5POL1 [3..3]  ============================================== */
75175 typedef enum {                                  /*!< TIMER_CTRL5_TMR5POL1                                                      */
75176   TIMER_CTRL5_TMR5POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR5OUT1 pin is the same as the
75177                                                      timer output.                                                             */
75178   TIMER_CTRL5_TMR5POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR5OUT1 pin is the inverse of
75179                                                      the timer output.                                                         */
75180 } TIMER_CTRL5_TMR5POL1_Enum;
75181 
75182 /* ==============================================  TIMER CTRL5 TMR5POL0 [2..2]  ============================================== */
75183 typedef enum {                                  /*!< TIMER_CTRL5_TMR5POL0                                                      */
75184   TIMER_CTRL5_TMR5POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR5OUT0 pin is the same as the
75185                                                      timer output.                                                             */
75186   TIMER_CTRL5_TMR5POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR5OUT0 pin is the inverse of
75187                                                      the timer output.                                                         */
75188 } TIMER_CTRL5_TMR5POL0_Enum;
75189 
75190 /* ==============================================  TIMER CTRL5 TMR5CLR [1..1]  =============================================== */
75191 typedef enum {                                  /*!< TIMER_CTRL5_TMR5CLR                                                       */
75192   TIMER_CTRL5_TMR5CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75193                                                      cleared to its reset state (0 for count up counter, CMP0
75194                                                      for down counter)                                                         */
75195 } TIMER_CTRL5_TMR5CLR_Enum;
75196 
75197 /* ===============================================  TIMER CTRL5 TMR5EN [0..0]  =============================================== */
75198 typedef enum {                                  /*!< TIMER_CTRL5_TMR5EN                                                        */
75199   TIMER_CTRL5_TMR5EN_DIS               = 0,     /*!< DIS : Counter/Timer 5 Disable.                                            */
75200   TIMER_CTRL5_TMR5EN_EN                = 1,     /*!< EN : Counter/Timer 5 Enable.                                              */
75201 } TIMER_CTRL5_TMR5EN_Enum;
75202 
75203 /* ========================================================  TIMER5  ========================================================= */
75204 /* =======================================================  TMR5CMP0  ======================================================== */
75205 /* =======================================================  TMR5CMP1  ======================================================== */
75206 /* =========================================================  MODE5  ========================================================= */
75207 /* ============================================  TIMER MODE5 TMR5TRIGSEL [8..15]  ============================================ */
75208 typedef enum {                                  /*!< TIMER_MODE5_TMR5TRIGSEL                                                   */
75209   TIMER_MODE5_TMR5TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75210   TIMER_MODE5_TMR5TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75211   TIMER_MODE5_TMR5TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75212   TIMER_MODE5_TMR5TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75213   TIMER_MODE5_TMR5TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75214   TIMER_MODE5_TMR5TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75215   TIMER_MODE5_TMR5TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75216   TIMER_MODE5_TMR5TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75217   TIMER_MODE5_TMR5TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75218   TIMER_MODE5_TMR5TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75219   TIMER_MODE5_TMR5TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75220   TIMER_MODE5_TMR5TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75221   TIMER_MODE5_TMR5TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75222   TIMER_MODE5_TMR5TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75223   TIMER_MODE5_TMR5TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75224   TIMER_MODE5_TMR5TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75225   TIMER_MODE5_TMR5TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75226   TIMER_MODE5_TMR5TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75227   TIMER_MODE5_TMR5TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75228   TIMER_MODE5_TMR5TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75229   TIMER_MODE5_TMR5TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75230   TIMER_MODE5_TMR5TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75231   TIMER_MODE5_TMR5TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75232   TIMER_MODE5_TMR5TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75233   TIMER_MODE5_TMR5TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75234   TIMER_MODE5_TMR5TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75235   TIMER_MODE5_TMR5TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75236   TIMER_MODE5_TMR5TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75237   TIMER_MODE5_TMR5TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75238   TIMER_MODE5_TMR5TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75239   TIMER_MODE5_TMR5TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75240   TIMER_MODE5_TMR5TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75241   TIMER_MODE5_TMR5TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
75242   TIMER_MODE5_TMR5TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
75243   TIMER_MODE5_TMR5TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
75244   TIMER_MODE5_TMR5TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
75245   TIMER_MODE5_TMR5TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
75246   TIMER_MODE5_TMR5TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
75247   TIMER_MODE5_TMR5TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
75248   TIMER_MODE5_TMR5TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
75249   TIMER_MODE5_TMR5TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
75250   TIMER_MODE5_TMR5TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
75251   TIMER_MODE5_TMR5TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
75252   TIMER_MODE5_TMR5TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
75253   TIMER_MODE5_TMR5TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
75254   TIMER_MODE5_TMR5TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
75255   TIMER_MODE5_TMR5TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
75256   TIMER_MODE5_TMR5TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
75257   TIMER_MODE5_TMR5TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75258   TIMER_MODE5_TMR5TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75259 } TIMER_MODE5_TMR5TRIGSEL_Enum;
75260 
75261 /* =========================================================  CTRL6  ========================================================= */
75262 /* ============================================  TIMER CTRL6 TMR6TMODE [16..17]  ============================================= */
75263 typedef enum {                                  /*!< TIMER_CTRL6_TMR6TMODE                                                     */
75264   TIMER_CTRL6_TMR6TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75265   TIMER_CTRL6_TMR6TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75266   TIMER_CTRL6_TMR6TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75267   TIMER_CTRL6_TMR6TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75268 } TIMER_CTRL6_TMR6TMODE_Enum;
75269 
75270 /* ==============================================  TIMER CTRL6 TMR6CLK [8..15]  ============================================== */
75271 typedef enum {                                  /*!< TIMER_CTRL6_TMR6CLK                                                       */
75272   TIMER_CTRL6_TMR6CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75273   TIMER_CTRL6_TMR6CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75274   TIMER_CTRL6_TMR6CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75275   TIMER_CTRL6_TMR6CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75276   TIMER_CTRL6_TMR6CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75277   TIMER_CTRL6_TMR6CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75278   TIMER_CTRL6_TMR6CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75279   TIMER_CTRL6_TMR6CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75280   TIMER_CTRL6_TMR6CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75281   TIMER_CTRL6_TMR6CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75282   TIMER_CTRL6_TMR6CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75283   TIMER_CTRL6_TMR6CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75284   TIMER_CTRL6_TMR6CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75285   TIMER_CTRL6_TMR6CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75286   TIMER_CTRL6_TMR6CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75287   TIMER_CTRL6_TMR6CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75288   TIMER_CTRL6_TMR6CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75289   TIMER_CTRL6_TMR6CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75290   TIMER_CTRL6_TMR6CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75291   TIMER_CTRL6_TMR6CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75292   TIMER_CTRL6_TMR6CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75293   TIMER_CTRL6_TMR6CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75294   TIMER_CTRL6_TMR6CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75295   TIMER_CTRL6_TMR6CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75296   TIMER_CTRL6_TMR6CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75297   TIMER_CTRL6_TMR6CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75298   TIMER_CTRL6_TMR6CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75299   TIMER_CTRL6_TMR6CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75300   TIMER_CTRL6_TMR6CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75301   TIMER_CTRL6_TMR6CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75302   TIMER_CTRL6_TMR6CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75303   TIMER_CTRL6_TMR6CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75304   TIMER_CTRL6_TMR6CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75305   TIMER_CTRL6_TMR6CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75306   TIMER_CTRL6_TMR6CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75307   TIMER_CTRL6_TMR6CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75308   TIMER_CTRL6_TMR6CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75309   TIMER_CTRL6_TMR6CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75310   TIMER_CTRL6_TMR6CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75311   TIMER_CTRL6_TMR6CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75312   TIMER_CTRL6_TMR6CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75313   TIMER_CTRL6_TMR6CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75314   TIMER_CTRL6_TMR6CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75315   TIMER_CTRL6_TMR6CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75316   TIMER_CTRL6_TMR6CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75317   TIMER_CTRL6_TMR6CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75318   TIMER_CTRL6_TMR6CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75319   TIMER_CTRL6_TMR6CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75320   TIMER_CTRL6_TMR6CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75321   TIMER_CTRL6_TMR6CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75322   TIMER_CTRL6_TMR6CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75323   TIMER_CTRL6_TMR6CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75324   TIMER_CTRL6_TMR6CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75325   TIMER_CTRL6_TMR6CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75326   TIMER_CTRL6_TMR6CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75327   TIMER_CTRL6_TMR6CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75328   TIMER_CTRL6_TMR6CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75329 } TIMER_CTRL6_TMR6CLK_Enum;
75330 
75331 /* ===============================================  TIMER CTRL6 TMR6FN [4..7]  =============================================== */
75332 typedef enum {                                  /*!< TIMER_CTRL6_TMR6FN                                                        */
75333   TIMER_CTRL6_TMR6FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
75334                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
75335   TIMER_CTRL6_TMR6FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
75336                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
75337                                                      follows CMP1.                                                             */
75338   TIMER_CTRL6_TMR6FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
75339                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
75340                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
75341   TIMER_CTRL6_TMR6FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
75342                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
75343   TIMER_CTRL6_TMR6FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
75344                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
75345                                                      and OUT[1] formed by TIMER>=CMPn                                          */
75346   TIMER_CTRL6_TMR6FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75347                                                      LMT field specifies length of pattern. When LMT>32 OUT0
75348                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
75349                                                      is CMP1,CMP1                                                              */
75350   TIMER_CTRL6_TMR6FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75351                                                      pattern repeats after reaching LMT.                                       */
75352   TIMER_CTRL6_TMR6FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
75353                                                      trigger until next edge (rising or falling) of source clock
75354                                                      (used as a secondary event). This can be used to measure
75355                                                      time betwen GPIOs, etc.                                                   */
75356 } TIMER_CTRL6_TMR6FN_Enum;
75357 
75358 /* ==============================================  TIMER CTRL6 TMR6POL1 [3..3]  ============================================== */
75359 typedef enum {                                  /*!< TIMER_CTRL6_TMR6POL1                                                      */
75360   TIMER_CTRL6_TMR6POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR6OUT1 pin is the same as the
75361                                                      timer output.                                                             */
75362   TIMER_CTRL6_TMR6POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR6OUT1 pin is the inverse of
75363                                                      the timer output.                                                         */
75364 } TIMER_CTRL6_TMR6POL1_Enum;
75365 
75366 /* ==============================================  TIMER CTRL6 TMR6POL0 [2..2]  ============================================== */
75367 typedef enum {                                  /*!< TIMER_CTRL6_TMR6POL0                                                      */
75368   TIMER_CTRL6_TMR6POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR6OUT0 pin is the same as the
75369                                                      timer output.                                                             */
75370   TIMER_CTRL6_TMR6POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR6OUT0 pin is the inverse of
75371                                                      the timer output.                                                         */
75372 } TIMER_CTRL6_TMR6POL0_Enum;
75373 
75374 /* ==============================================  TIMER CTRL6 TMR6CLR [1..1]  =============================================== */
75375 typedef enum {                                  /*!< TIMER_CTRL6_TMR6CLR                                                       */
75376   TIMER_CTRL6_TMR6CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75377                                                      cleared to its reset state (0 for count up counter, CMP0
75378                                                      for down counter)                                                         */
75379 } TIMER_CTRL6_TMR6CLR_Enum;
75380 
75381 /* ===============================================  TIMER CTRL6 TMR6EN [0..0]  =============================================== */
75382 typedef enum {                                  /*!< TIMER_CTRL6_TMR6EN                                                        */
75383   TIMER_CTRL6_TMR6EN_DIS               = 0,     /*!< DIS : Counter/Timer 6 Disable.                                            */
75384   TIMER_CTRL6_TMR6EN_EN                = 1,     /*!< EN : Counter/Timer 6 Enable.                                              */
75385 } TIMER_CTRL6_TMR6EN_Enum;
75386 
75387 /* ========================================================  TIMER6  ========================================================= */
75388 /* =======================================================  TMR6CMP0  ======================================================== */
75389 /* =======================================================  TMR6CMP1  ======================================================== */
75390 /* =========================================================  MODE6  ========================================================= */
75391 /* ============================================  TIMER MODE6 TMR6TRIGSEL [8..15]  ============================================ */
75392 typedef enum {                                  /*!< TIMER_MODE6_TMR6TRIGSEL                                                   */
75393   TIMER_MODE6_TMR6TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75394   TIMER_MODE6_TMR6TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75395   TIMER_MODE6_TMR6TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75396   TIMER_MODE6_TMR6TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75397   TIMER_MODE6_TMR6TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75398   TIMER_MODE6_TMR6TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75399   TIMER_MODE6_TMR6TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75400   TIMER_MODE6_TMR6TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75401   TIMER_MODE6_TMR6TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75402   TIMER_MODE6_TMR6TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75403   TIMER_MODE6_TMR6TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75404   TIMER_MODE6_TMR6TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75405   TIMER_MODE6_TMR6TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75406   TIMER_MODE6_TMR6TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75407   TIMER_MODE6_TMR6TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75408   TIMER_MODE6_TMR6TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75409   TIMER_MODE6_TMR6TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75410   TIMER_MODE6_TMR6TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75411   TIMER_MODE6_TMR6TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75412   TIMER_MODE6_TMR6TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75413   TIMER_MODE6_TMR6TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75414   TIMER_MODE6_TMR6TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75415   TIMER_MODE6_TMR6TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75416   TIMER_MODE6_TMR6TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75417   TIMER_MODE6_TMR6TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75418   TIMER_MODE6_TMR6TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75419   TIMER_MODE6_TMR6TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75420   TIMER_MODE6_TMR6TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75421   TIMER_MODE6_TMR6TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75422   TIMER_MODE6_TMR6TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75423   TIMER_MODE6_TMR6TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75424   TIMER_MODE6_TMR6TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75425   TIMER_MODE6_TMR6TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
75426   TIMER_MODE6_TMR6TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
75427   TIMER_MODE6_TMR6TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
75428   TIMER_MODE6_TMR6TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
75429   TIMER_MODE6_TMR6TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
75430   TIMER_MODE6_TMR6TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
75431   TIMER_MODE6_TMR6TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
75432   TIMER_MODE6_TMR6TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
75433   TIMER_MODE6_TMR6TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
75434   TIMER_MODE6_TMR6TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
75435   TIMER_MODE6_TMR6TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
75436   TIMER_MODE6_TMR6TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
75437   TIMER_MODE6_TMR6TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
75438   TIMER_MODE6_TMR6TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
75439   TIMER_MODE6_TMR6TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
75440   TIMER_MODE6_TMR6TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
75441   TIMER_MODE6_TMR6TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75442   TIMER_MODE6_TMR6TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75443 } TIMER_MODE6_TMR6TRIGSEL_Enum;
75444 
75445 /* =========================================================  CTRL7  ========================================================= */
75446 /* ============================================  TIMER CTRL7 TMR7TMODE [16..17]  ============================================= */
75447 typedef enum {                                  /*!< TIMER_CTRL7_TMR7TMODE                                                     */
75448   TIMER_CTRL7_TMR7TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75449   TIMER_CTRL7_TMR7TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75450   TIMER_CTRL7_TMR7TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75451   TIMER_CTRL7_TMR7TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75452 } TIMER_CTRL7_TMR7TMODE_Enum;
75453 
75454 /* ==============================================  TIMER CTRL7 TMR7CLK [8..15]  ============================================== */
75455 typedef enum {                                  /*!< TIMER_CTRL7_TMR7CLK                                                       */
75456   TIMER_CTRL7_TMR7CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75457   TIMER_CTRL7_TMR7CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75458   TIMER_CTRL7_TMR7CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75459   TIMER_CTRL7_TMR7CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75460   TIMER_CTRL7_TMR7CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75461   TIMER_CTRL7_TMR7CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75462   TIMER_CTRL7_TMR7CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75463   TIMER_CTRL7_TMR7CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75464   TIMER_CTRL7_TMR7CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75465   TIMER_CTRL7_TMR7CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75466   TIMER_CTRL7_TMR7CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75467   TIMER_CTRL7_TMR7CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75468   TIMER_CTRL7_TMR7CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75469   TIMER_CTRL7_TMR7CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75470   TIMER_CTRL7_TMR7CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75471   TIMER_CTRL7_TMR7CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75472   TIMER_CTRL7_TMR7CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75473   TIMER_CTRL7_TMR7CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75474   TIMER_CTRL7_TMR7CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75475   TIMER_CTRL7_TMR7CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75476   TIMER_CTRL7_TMR7CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75477   TIMER_CTRL7_TMR7CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75478   TIMER_CTRL7_TMR7CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75479   TIMER_CTRL7_TMR7CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75480   TIMER_CTRL7_TMR7CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75481   TIMER_CTRL7_TMR7CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75482   TIMER_CTRL7_TMR7CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75483   TIMER_CTRL7_TMR7CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75484   TIMER_CTRL7_TMR7CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75485   TIMER_CTRL7_TMR7CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75486   TIMER_CTRL7_TMR7CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75487   TIMER_CTRL7_TMR7CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75488   TIMER_CTRL7_TMR7CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75489   TIMER_CTRL7_TMR7CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75490   TIMER_CTRL7_TMR7CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75491   TIMER_CTRL7_TMR7CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75492   TIMER_CTRL7_TMR7CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75493   TIMER_CTRL7_TMR7CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75494   TIMER_CTRL7_TMR7CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75495   TIMER_CTRL7_TMR7CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75496   TIMER_CTRL7_TMR7CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75497   TIMER_CTRL7_TMR7CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75498   TIMER_CTRL7_TMR7CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75499   TIMER_CTRL7_TMR7CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75500   TIMER_CTRL7_TMR7CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75501   TIMER_CTRL7_TMR7CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75502   TIMER_CTRL7_TMR7CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75503   TIMER_CTRL7_TMR7CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75504   TIMER_CTRL7_TMR7CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75505   TIMER_CTRL7_TMR7CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75506   TIMER_CTRL7_TMR7CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75507   TIMER_CTRL7_TMR7CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75508   TIMER_CTRL7_TMR7CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75509   TIMER_CTRL7_TMR7CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75510   TIMER_CTRL7_TMR7CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75511   TIMER_CTRL7_TMR7CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75512   TIMER_CTRL7_TMR7CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75513 } TIMER_CTRL7_TMR7CLK_Enum;
75514 
75515 /* ===============================================  TIMER CTRL7 TMR7FN [4..7]  =============================================== */
75516 typedef enum {                                  /*!< TIMER_CTRL7_TMR7FN                                                        */
75517   TIMER_CTRL7_TMR7FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
75518                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
75519   TIMER_CTRL7_TMR7FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
75520                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
75521                                                      follows CMP1.                                                             */
75522   TIMER_CTRL7_TMR7FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
75523                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
75524                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
75525   TIMER_CTRL7_TMR7FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
75526                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
75527   TIMER_CTRL7_TMR7FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
75528                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
75529                                                      and OUT[1] formed by TIMER>=CMPn                                          */
75530   TIMER_CTRL7_TMR7FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75531                                                      LMT field specifies length of pattern. When LMT>32 OUT0
75532                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
75533                                                      is CMP1,CMP1                                                              */
75534   TIMER_CTRL7_TMR7FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75535                                                      pattern repeats after reaching LMT.                                       */
75536   TIMER_CTRL7_TMR7FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
75537                                                      trigger until next edge (rising or falling) of source clock
75538                                                      (used as a secondary event). This can be used to measure
75539                                                      time betwen GPIOs, etc.                                                   */
75540 } TIMER_CTRL7_TMR7FN_Enum;
75541 
75542 /* ==============================================  TIMER CTRL7 TMR7POL1 [3..3]  ============================================== */
75543 typedef enum {                                  /*!< TIMER_CTRL7_TMR7POL1                                                      */
75544   TIMER_CTRL7_TMR7POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR7OUT1 pin is the same as the
75545                                                      timer output.                                                             */
75546   TIMER_CTRL7_TMR7POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR7OUT1 pin is the inverse of
75547                                                      the timer output.                                                         */
75548 } TIMER_CTRL7_TMR7POL1_Enum;
75549 
75550 /* ==============================================  TIMER CTRL7 TMR7POL0 [2..2]  ============================================== */
75551 typedef enum {                                  /*!< TIMER_CTRL7_TMR7POL0                                                      */
75552   TIMER_CTRL7_TMR7POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR7OUT0 pin is the same as the
75553                                                      timer output.                                                             */
75554   TIMER_CTRL7_TMR7POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR7OUT0 pin is the inverse of
75555                                                      the timer output.                                                         */
75556 } TIMER_CTRL7_TMR7POL0_Enum;
75557 
75558 /* ==============================================  TIMER CTRL7 TMR7CLR [1..1]  =============================================== */
75559 typedef enum {                                  /*!< TIMER_CTRL7_TMR7CLR                                                       */
75560   TIMER_CTRL7_TMR7CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75561                                                      cleared to its reset state (0 for count up counter, CMP0
75562                                                      for down counter)                                                         */
75563 } TIMER_CTRL7_TMR7CLR_Enum;
75564 
75565 /* ===============================================  TIMER CTRL7 TMR7EN [0..0]  =============================================== */
75566 typedef enum {                                  /*!< TIMER_CTRL7_TMR7EN                                                        */
75567   TIMER_CTRL7_TMR7EN_DIS               = 0,     /*!< DIS : Counter/Timer 7 Disable.                                            */
75568   TIMER_CTRL7_TMR7EN_EN                = 1,     /*!< EN : Counter/Timer 7 Enable.                                              */
75569 } TIMER_CTRL7_TMR7EN_Enum;
75570 
75571 /* ========================================================  TIMER7  ========================================================= */
75572 /* =======================================================  TMR7CMP0  ======================================================== */
75573 /* =======================================================  TMR7CMP1  ======================================================== */
75574 /* =========================================================  MODE7  ========================================================= */
75575 /* ============================================  TIMER MODE7 TMR7TRIGSEL [8..15]  ============================================ */
75576 typedef enum {                                  /*!< TIMER_MODE7_TMR7TRIGSEL                                                   */
75577   TIMER_MODE7_TMR7TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75578   TIMER_MODE7_TMR7TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75579   TIMER_MODE7_TMR7TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75580   TIMER_MODE7_TMR7TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75581   TIMER_MODE7_TMR7TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75582   TIMER_MODE7_TMR7TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75583   TIMER_MODE7_TMR7TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75584   TIMER_MODE7_TMR7TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75585   TIMER_MODE7_TMR7TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75586   TIMER_MODE7_TMR7TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75587   TIMER_MODE7_TMR7TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75588   TIMER_MODE7_TMR7TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75589   TIMER_MODE7_TMR7TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75590   TIMER_MODE7_TMR7TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75591   TIMER_MODE7_TMR7TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75592   TIMER_MODE7_TMR7TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75593   TIMER_MODE7_TMR7TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75594   TIMER_MODE7_TMR7TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75595   TIMER_MODE7_TMR7TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75596   TIMER_MODE7_TMR7TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75597   TIMER_MODE7_TMR7TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75598   TIMER_MODE7_TMR7TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75599   TIMER_MODE7_TMR7TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75600   TIMER_MODE7_TMR7TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75601   TIMER_MODE7_TMR7TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75602   TIMER_MODE7_TMR7TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75603   TIMER_MODE7_TMR7TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75604   TIMER_MODE7_TMR7TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75605   TIMER_MODE7_TMR7TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75606   TIMER_MODE7_TMR7TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75607   TIMER_MODE7_TMR7TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75608   TIMER_MODE7_TMR7TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75609   TIMER_MODE7_TMR7TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
75610   TIMER_MODE7_TMR7TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
75611   TIMER_MODE7_TMR7TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
75612   TIMER_MODE7_TMR7TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
75613   TIMER_MODE7_TMR7TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
75614   TIMER_MODE7_TMR7TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
75615   TIMER_MODE7_TMR7TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
75616   TIMER_MODE7_TMR7TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
75617   TIMER_MODE7_TMR7TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
75618   TIMER_MODE7_TMR7TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
75619   TIMER_MODE7_TMR7TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
75620   TIMER_MODE7_TMR7TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
75621   TIMER_MODE7_TMR7TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
75622   TIMER_MODE7_TMR7TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
75623   TIMER_MODE7_TMR7TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
75624   TIMER_MODE7_TMR7TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
75625   TIMER_MODE7_TMR7TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75626   TIMER_MODE7_TMR7TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75627 } TIMER_MODE7_TMR7TRIGSEL_Enum;
75628 
75629 /* =========================================================  CTRL8  ========================================================= */
75630 /* ============================================  TIMER CTRL8 TMR8TMODE [16..17]  ============================================= */
75631 typedef enum {                                  /*!< TIMER_CTRL8_TMR8TMODE                                                     */
75632   TIMER_CTRL8_TMR8TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75633   TIMER_CTRL8_TMR8TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75634   TIMER_CTRL8_TMR8TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75635   TIMER_CTRL8_TMR8TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75636 } TIMER_CTRL8_TMR8TMODE_Enum;
75637 
75638 /* ==============================================  TIMER CTRL8 TMR8CLK [8..15]  ============================================== */
75639 typedef enum {                                  /*!< TIMER_CTRL8_TMR8CLK                                                       */
75640   TIMER_CTRL8_TMR8CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75641   TIMER_CTRL8_TMR8CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75642   TIMER_CTRL8_TMR8CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75643   TIMER_CTRL8_TMR8CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75644   TIMER_CTRL8_TMR8CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75645   TIMER_CTRL8_TMR8CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75646   TIMER_CTRL8_TMR8CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75647   TIMER_CTRL8_TMR8CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75648   TIMER_CTRL8_TMR8CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75649   TIMER_CTRL8_TMR8CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75650   TIMER_CTRL8_TMR8CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75651   TIMER_CTRL8_TMR8CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75652   TIMER_CTRL8_TMR8CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75653   TIMER_CTRL8_TMR8CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75654   TIMER_CTRL8_TMR8CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75655   TIMER_CTRL8_TMR8CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75656   TIMER_CTRL8_TMR8CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75657   TIMER_CTRL8_TMR8CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75658   TIMER_CTRL8_TMR8CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75659   TIMER_CTRL8_TMR8CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75660   TIMER_CTRL8_TMR8CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75661   TIMER_CTRL8_TMR8CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75662   TIMER_CTRL8_TMR8CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75663   TIMER_CTRL8_TMR8CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75664   TIMER_CTRL8_TMR8CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75665   TIMER_CTRL8_TMR8CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75666   TIMER_CTRL8_TMR8CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75667   TIMER_CTRL8_TMR8CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75668   TIMER_CTRL8_TMR8CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75669   TIMER_CTRL8_TMR8CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75670   TIMER_CTRL8_TMR8CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75671   TIMER_CTRL8_TMR8CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75672   TIMER_CTRL8_TMR8CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75673   TIMER_CTRL8_TMR8CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75674   TIMER_CTRL8_TMR8CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75675   TIMER_CTRL8_TMR8CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75676   TIMER_CTRL8_TMR8CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75677   TIMER_CTRL8_TMR8CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75678   TIMER_CTRL8_TMR8CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75679   TIMER_CTRL8_TMR8CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75680   TIMER_CTRL8_TMR8CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75681   TIMER_CTRL8_TMR8CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75682   TIMER_CTRL8_TMR8CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75683   TIMER_CTRL8_TMR8CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75684   TIMER_CTRL8_TMR8CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75685   TIMER_CTRL8_TMR8CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75686   TIMER_CTRL8_TMR8CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75687   TIMER_CTRL8_TMR8CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75688   TIMER_CTRL8_TMR8CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75689   TIMER_CTRL8_TMR8CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75690   TIMER_CTRL8_TMR8CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75691   TIMER_CTRL8_TMR8CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75692   TIMER_CTRL8_TMR8CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75693   TIMER_CTRL8_TMR8CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75694   TIMER_CTRL8_TMR8CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75695   TIMER_CTRL8_TMR8CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75696   TIMER_CTRL8_TMR8CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75697 } TIMER_CTRL8_TMR8CLK_Enum;
75698 
75699 /* ===============================================  TIMER CTRL8 TMR8FN [4..7]  =============================================== */
75700 typedef enum {                                  /*!< TIMER_CTRL8_TMR8FN                                                        */
75701   TIMER_CTRL8_TMR8FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
75702                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
75703   TIMER_CTRL8_TMR8FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
75704                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
75705                                                      follows CMP1.                                                             */
75706   TIMER_CTRL8_TMR8FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
75707                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
75708                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
75709   TIMER_CTRL8_TMR8FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
75710                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
75711   TIMER_CTRL8_TMR8FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
75712                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
75713                                                      and OUT[1] formed by TIMER>=CMPn                                          */
75714   TIMER_CTRL8_TMR8FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75715                                                      LMT field specifies length of pattern. When LMT>32 OUT0
75716                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
75717                                                      is CMP1,CMP1                                                              */
75718   TIMER_CTRL8_TMR8FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75719                                                      pattern repeats after reaching LMT.                                       */
75720   TIMER_CTRL8_TMR8FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
75721                                                      trigger until next edge (rising or falling) of source clock
75722                                                      (used as a secondary event). This can be used to measure
75723                                                      time betwen GPIOs, etc.                                                   */
75724 } TIMER_CTRL8_TMR8FN_Enum;
75725 
75726 /* ==============================================  TIMER CTRL8 TMR8POL1 [3..3]  ============================================== */
75727 typedef enum {                                  /*!< TIMER_CTRL8_TMR8POL1                                                      */
75728   TIMER_CTRL8_TMR8POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR8OUT1 pin is the same as the
75729                                                      timer output.                                                             */
75730   TIMER_CTRL8_TMR8POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR8OUT1 pin is the inverse of
75731                                                      the timer output.                                                         */
75732 } TIMER_CTRL8_TMR8POL1_Enum;
75733 
75734 /* ==============================================  TIMER CTRL8 TMR8POL0 [2..2]  ============================================== */
75735 typedef enum {                                  /*!< TIMER_CTRL8_TMR8POL0                                                      */
75736   TIMER_CTRL8_TMR8POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR8OUT0 pin is the same as the
75737                                                      timer output.                                                             */
75738   TIMER_CTRL8_TMR8POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR8OUT0 pin is the inverse of
75739                                                      the timer output.                                                         */
75740 } TIMER_CTRL8_TMR8POL0_Enum;
75741 
75742 /* ==============================================  TIMER CTRL8 TMR8CLR [1..1]  =============================================== */
75743 typedef enum {                                  /*!< TIMER_CTRL8_TMR8CLR                                                       */
75744   TIMER_CTRL8_TMR8CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75745                                                      cleared to its reset state (0 for count up counter, CMP0
75746                                                      for down counter)                                                         */
75747 } TIMER_CTRL8_TMR8CLR_Enum;
75748 
75749 /* ===============================================  TIMER CTRL8 TMR8EN [0..0]  =============================================== */
75750 typedef enum {                                  /*!< TIMER_CTRL8_TMR8EN                                                        */
75751   TIMER_CTRL8_TMR8EN_DIS               = 0,     /*!< DIS : Counter/Timer 8 Disable.                                            */
75752   TIMER_CTRL8_TMR8EN_EN                = 1,     /*!< EN : Counter/Timer 8 Enable.                                              */
75753 } TIMER_CTRL8_TMR8EN_Enum;
75754 
75755 /* ========================================================  TIMER8  ========================================================= */
75756 /* =======================================================  TMR8CMP0  ======================================================== */
75757 /* =======================================================  TMR8CMP1  ======================================================== */
75758 /* =========================================================  MODE8  ========================================================= */
75759 /* ============================================  TIMER MODE8 TMR8TRIGSEL [8..15]  ============================================ */
75760 typedef enum {                                  /*!< TIMER_MODE8_TMR8TRIGSEL                                                   */
75761   TIMER_MODE8_TMR8TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75762   TIMER_MODE8_TMR8TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75763   TIMER_MODE8_TMR8TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75764   TIMER_MODE8_TMR8TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75765   TIMER_MODE8_TMR8TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75766   TIMER_MODE8_TMR8TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75767   TIMER_MODE8_TMR8TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75768   TIMER_MODE8_TMR8TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75769   TIMER_MODE8_TMR8TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75770   TIMER_MODE8_TMR8TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75771   TIMER_MODE8_TMR8TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75772   TIMER_MODE8_TMR8TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75773   TIMER_MODE8_TMR8TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75774   TIMER_MODE8_TMR8TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75775   TIMER_MODE8_TMR8TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75776   TIMER_MODE8_TMR8TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75777   TIMER_MODE8_TMR8TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75778   TIMER_MODE8_TMR8TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75779   TIMER_MODE8_TMR8TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75780   TIMER_MODE8_TMR8TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75781   TIMER_MODE8_TMR8TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75782   TIMER_MODE8_TMR8TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75783   TIMER_MODE8_TMR8TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75784   TIMER_MODE8_TMR8TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75785   TIMER_MODE8_TMR8TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75786   TIMER_MODE8_TMR8TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75787   TIMER_MODE8_TMR8TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75788   TIMER_MODE8_TMR8TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75789   TIMER_MODE8_TMR8TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75790   TIMER_MODE8_TMR8TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75791   TIMER_MODE8_TMR8TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75792   TIMER_MODE8_TMR8TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75793   TIMER_MODE8_TMR8TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
75794   TIMER_MODE8_TMR8TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
75795   TIMER_MODE8_TMR8TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
75796   TIMER_MODE8_TMR8TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
75797   TIMER_MODE8_TMR8TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
75798   TIMER_MODE8_TMR8TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
75799   TIMER_MODE8_TMR8TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
75800   TIMER_MODE8_TMR8TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
75801   TIMER_MODE8_TMR8TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
75802   TIMER_MODE8_TMR8TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
75803   TIMER_MODE8_TMR8TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
75804   TIMER_MODE8_TMR8TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
75805   TIMER_MODE8_TMR8TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
75806   TIMER_MODE8_TMR8TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
75807   TIMER_MODE8_TMR8TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
75808   TIMER_MODE8_TMR8TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
75809   TIMER_MODE8_TMR8TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75810   TIMER_MODE8_TMR8TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75811 } TIMER_MODE8_TMR8TRIGSEL_Enum;
75812 
75813 /* =========================================================  CTRL9  ========================================================= */
75814 /* ============================================  TIMER CTRL9 TMR9TMODE [16..17]  ============================================= */
75815 typedef enum {                                  /*!< TIMER_CTRL9_TMR9TMODE                                                     */
75816   TIMER_CTRL9_TMR9TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75817   TIMER_CTRL9_TMR9TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75818   TIMER_CTRL9_TMR9TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75819   TIMER_CTRL9_TMR9TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75820 } TIMER_CTRL9_TMR9TMODE_Enum;
75821 
75822 /* ==============================================  TIMER CTRL9 TMR9CLK [8..15]  ============================================== */
75823 typedef enum {                                  /*!< TIMER_CTRL9_TMR9CLK                                                       */
75824   TIMER_CTRL9_TMR9CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75825   TIMER_CTRL9_TMR9CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75826   TIMER_CTRL9_TMR9CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75827   TIMER_CTRL9_TMR9CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75828   TIMER_CTRL9_TMR9CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75829   TIMER_CTRL9_TMR9CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75830   TIMER_CTRL9_TMR9CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75831   TIMER_CTRL9_TMR9CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75832   TIMER_CTRL9_TMR9CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75833   TIMER_CTRL9_TMR9CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75834   TIMER_CTRL9_TMR9CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75835   TIMER_CTRL9_TMR9CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75836   TIMER_CTRL9_TMR9CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75837   TIMER_CTRL9_TMR9CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75838   TIMER_CTRL9_TMR9CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75839   TIMER_CTRL9_TMR9CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75840   TIMER_CTRL9_TMR9CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75841   TIMER_CTRL9_TMR9CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75842   TIMER_CTRL9_TMR9CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75843   TIMER_CTRL9_TMR9CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75844   TIMER_CTRL9_TMR9CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75845   TIMER_CTRL9_TMR9CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75846   TIMER_CTRL9_TMR9CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75847   TIMER_CTRL9_TMR9CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75848   TIMER_CTRL9_TMR9CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75849   TIMER_CTRL9_TMR9CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75850   TIMER_CTRL9_TMR9CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75851   TIMER_CTRL9_TMR9CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75852   TIMER_CTRL9_TMR9CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75853   TIMER_CTRL9_TMR9CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75854   TIMER_CTRL9_TMR9CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75855   TIMER_CTRL9_TMR9CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75856   TIMER_CTRL9_TMR9CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75857   TIMER_CTRL9_TMR9CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75858   TIMER_CTRL9_TMR9CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75859   TIMER_CTRL9_TMR9CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75860   TIMER_CTRL9_TMR9CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75861   TIMER_CTRL9_TMR9CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75862   TIMER_CTRL9_TMR9CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75863   TIMER_CTRL9_TMR9CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75864   TIMER_CTRL9_TMR9CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75865   TIMER_CTRL9_TMR9CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75866   TIMER_CTRL9_TMR9CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75867   TIMER_CTRL9_TMR9CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75868   TIMER_CTRL9_TMR9CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75869   TIMER_CTRL9_TMR9CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75870   TIMER_CTRL9_TMR9CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75871   TIMER_CTRL9_TMR9CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75872   TIMER_CTRL9_TMR9CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75873   TIMER_CTRL9_TMR9CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75874   TIMER_CTRL9_TMR9CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75875   TIMER_CTRL9_TMR9CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75876   TIMER_CTRL9_TMR9CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75877   TIMER_CTRL9_TMR9CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75878   TIMER_CTRL9_TMR9CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75879   TIMER_CTRL9_TMR9CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75880   TIMER_CTRL9_TMR9CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75881 } TIMER_CTRL9_TMR9CLK_Enum;
75882 
75883 /* ===============================================  TIMER CTRL9 TMR9FN [4..7]  =============================================== */
75884 typedef enum {                                  /*!< TIMER_CTRL9_TMR9FN                                                        */
75885   TIMER_CTRL9_TMR9FN_CONTINUOUS        = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
75886                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
75887   TIMER_CTRL9_TMR9FN_EDGE              = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
75888                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
75889                                                      follows CMP1.                                                             */
75890   TIMER_CTRL9_TMR9FN_UPCOUNT           = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
75891                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
75892                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
75893   TIMER_CTRL9_TMR9FN_PWM               = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
75894                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
75895   TIMER_CTRL9_TMR9FN_DOWNCOUNT         = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
75896                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
75897                                                      and OUT[1] formed by TIMER>=CMPn                                          */
75898   TIMER_CTRL9_TMR9FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75899                                                      LMT field specifies length of pattern. When LMT>32 OUT0
75900                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
75901                                                      is CMP1,CMP1                                                              */
75902   TIMER_CTRL9_TMR9FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75903                                                      pattern repeats after reaching LMT.                                       */
75904   TIMER_CTRL9_TMR9FN_EVENTTIMER        = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
75905                                                      trigger until next edge (rising or falling) of source clock
75906                                                      (used as a secondary event). This can be used to measure
75907                                                      time betwen GPIOs, etc.                                                   */
75908 } TIMER_CTRL9_TMR9FN_Enum;
75909 
75910 /* ==============================================  TIMER CTRL9 TMR9POL1 [3..3]  ============================================== */
75911 typedef enum {                                  /*!< TIMER_CTRL9_TMR9POL1                                                      */
75912   TIMER_CTRL9_TMR9POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR9OUT1 pin is the same as the
75913                                                      timer output.                                                             */
75914   TIMER_CTRL9_TMR9POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR9OUT1 pin is the inverse of
75915                                                      the timer output.                                                         */
75916 } TIMER_CTRL9_TMR9POL1_Enum;
75917 
75918 /* ==============================================  TIMER CTRL9 TMR9POL0 [2..2]  ============================================== */
75919 typedef enum {                                  /*!< TIMER_CTRL9_TMR9POL0                                                      */
75920   TIMER_CTRL9_TMR9POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR9OUT0 pin is the same as the
75921                                                      timer output.                                                             */
75922   TIMER_CTRL9_TMR9POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR9OUT0 pin is the inverse of
75923                                                      the timer output.                                                         */
75924 } TIMER_CTRL9_TMR9POL0_Enum;
75925 
75926 /* ==============================================  TIMER CTRL9 TMR9CLR [1..1]  =============================================== */
75927 typedef enum {                                  /*!< TIMER_CTRL9_TMR9CLR                                                       */
75928   TIMER_CTRL9_TMR9CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75929                                                      cleared to its reset state (0 for count up counter, CMP0
75930                                                      for down counter)                                                         */
75931 } TIMER_CTRL9_TMR9CLR_Enum;
75932 
75933 /* ===============================================  TIMER CTRL9 TMR9EN [0..0]  =============================================== */
75934 typedef enum {                                  /*!< TIMER_CTRL9_TMR9EN                                                        */
75935   TIMER_CTRL9_TMR9EN_DIS               = 0,     /*!< DIS : Counter/Timer 9 Disable.                                            */
75936   TIMER_CTRL9_TMR9EN_EN                = 1,     /*!< EN : Counter/Timer 9 Enable.                                              */
75937 } TIMER_CTRL9_TMR9EN_Enum;
75938 
75939 /* ========================================================  TIMER9  ========================================================= */
75940 /* =======================================================  TMR9CMP0  ======================================================== */
75941 /* =======================================================  TMR9CMP1  ======================================================== */
75942 /* =========================================================  MODE9  ========================================================= */
75943 /* ============================================  TIMER MODE9 TMR9TRIGSEL [8..15]  ============================================ */
75944 typedef enum {                                  /*!< TIMER_MODE9_TMR9TRIGSEL                                                   */
75945   TIMER_MODE9_TMR9TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75946   TIMER_MODE9_TMR9TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75947   TIMER_MODE9_TMR9TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75948   TIMER_MODE9_TMR9TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75949   TIMER_MODE9_TMR9TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75950   TIMER_MODE9_TMR9TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75951   TIMER_MODE9_TMR9TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75952   TIMER_MODE9_TMR9TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75953   TIMER_MODE9_TMR9TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75954   TIMER_MODE9_TMR9TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75955   TIMER_MODE9_TMR9TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75956   TIMER_MODE9_TMR9TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75957   TIMER_MODE9_TMR9TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75958   TIMER_MODE9_TMR9TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75959   TIMER_MODE9_TMR9TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75960   TIMER_MODE9_TMR9TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75961   TIMER_MODE9_TMR9TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75962   TIMER_MODE9_TMR9TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75963   TIMER_MODE9_TMR9TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75964   TIMER_MODE9_TMR9TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75965   TIMER_MODE9_TMR9TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75966   TIMER_MODE9_TMR9TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75967   TIMER_MODE9_TMR9TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75968   TIMER_MODE9_TMR9TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75969   TIMER_MODE9_TMR9TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75970   TIMER_MODE9_TMR9TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75971   TIMER_MODE9_TMR9TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75972   TIMER_MODE9_TMR9TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75973   TIMER_MODE9_TMR9TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75974   TIMER_MODE9_TMR9TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75975   TIMER_MODE9_TMR9TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75976   TIMER_MODE9_TMR9TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75977   TIMER_MODE9_TMR9TRIGSEL_STMRCMP00    = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
75978   TIMER_MODE9_TMR9TRIGSEL_STMRCMP10    = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
75979   TIMER_MODE9_TMR9TRIGSEL_STMRCMP20    = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
75980   TIMER_MODE9_TMR9TRIGSEL_STMRCMP30    = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
75981   TIMER_MODE9_TMR9TRIGSEL_STMRCMP40    = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
75982   TIMER_MODE9_TMR9TRIGSEL_STMRCMP50    = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
75983   TIMER_MODE9_TMR9TRIGSEL_STMRCMP60    = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
75984   TIMER_MODE9_TMR9TRIGSEL_STMRCMP70    = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
75985   TIMER_MODE9_TMR9TRIGSEL_STMRCAP00    = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
75986   TIMER_MODE9_TMR9TRIGSEL_STMRCAP10    = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
75987   TIMER_MODE9_TMR9TRIGSEL_STMRCAP20    = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
75988   TIMER_MODE9_TMR9TRIGSEL_STMRCAP30    = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
75989   TIMER_MODE9_TMR9TRIGSEL_STMRCAP40    = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
75990   TIMER_MODE9_TMR9TRIGSEL_STMRCAP50    = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
75991   TIMER_MODE9_TMR9TRIGSEL_STMRCAP60    = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
75992   TIMER_MODE9_TMR9TRIGSEL_STMRCAP70    = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
75993   TIMER_MODE9_TMR9TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75994   TIMER_MODE9_TMR9TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75995 } TIMER_MODE9_TMR9TRIGSEL_Enum;
75996 
75997 /* ========================================================  CTRL10  ========================================================= */
75998 /* ===========================================  TIMER CTRL10 TMR10TMODE [16..17]  ============================================ */
75999 typedef enum {                                  /*!< TIMER_CTRL10_TMR10TMODE                                                   */
76000   TIMER_CTRL10_TMR10TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
76001   TIMER_CTRL10_TMR10TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76002   TIMER_CTRL10_TMR10TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76003   TIMER_CTRL10_TMR10TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76004 } TIMER_CTRL10_TMR10TMODE_Enum;
76005 
76006 /* =============================================  TIMER CTRL10 TMR10CLK [8..15]  ============================================= */
76007 typedef enum {                                  /*!< TIMER_CTRL10_TMR10CLK                                                     */
76008   TIMER_CTRL10_TMR10CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76009   TIMER_CTRL10_TMR10CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76010   TIMER_CTRL10_TMR10CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76011   TIMER_CTRL10_TMR10CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76012   TIMER_CTRL10_TMR10CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76013   TIMER_CTRL10_TMR10CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
76014   TIMER_CTRL10_TMR10CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76015   TIMER_CTRL10_TMR10CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76016   TIMER_CTRL10_TMR10CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76017   TIMER_CTRL10_TMR10CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76018   TIMER_CTRL10_TMR10CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76019   TIMER_CTRL10_TMR10CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76020   TIMER_CTRL10_TMR10CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76021   TIMER_CTRL10_TMR10CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76022   TIMER_CTRL10_TMR10CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76023   TIMER_CTRL10_TMR10CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76024   TIMER_CTRL10_TMR10CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76025   TIMER_CTRL10_TMR10CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76026   TIMER_CTRL10_TMR10CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76027   TIMER_CTRL10_TMR10CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76028   TIMER_CTRL10_TMR10CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76029   TIMER_CTRL10_TMR10CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76030   TIMER_CTRL10_TMR10CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76031   TIMER_CTRL10_TMR10CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76032   TIMER_CTRL10_TMR10CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76033   TIMER_CTRL10_TMR10CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76034   TIMER_CTRL10_TMR10CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76035   TIMER_CTRL10_TMR10CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76036   TIMER_CTRL10_TMR10CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76037   TIMER_CTRL10_TMR10CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76038   TIMER_CTRL10_TMR10CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76039   TIMER_CTRL10_TMR10CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76040   TIMER_CTRL10_TMR10CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76041   TIMER_CTRL10_TMR10CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76042   TIMER_CTRL10_TMR10CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76043   TIMER_CTRL10_TMR10CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76044   TIMER_CTRL10_TMR10CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76045   TIMER_CTRL10_TMR10CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76046   TIMER_CTRL10_TMR10CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76047   TIMER_CTRL10_TMR10CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76048   TIMER_CTRL10_TMR10CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76049   TIMER_CTRL10_TMR10CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76050   TIMER_CTRL10_TMR10CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76051   TIMER_CTRL10_TMR10CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76052   TIMER_CTRL10_TMR10CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76053   TIMER_CTRL10_TMR10CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76054   TIMER_CTRL10_TMR10CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76055   TIMER_CTRL10_TMR10CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76056   TIMER_CTRL10_TMR10CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76057   TIMER_CTRL10_TMR10CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76058   TIMER_CTRL10_TMR10CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76059   TIMER_CTRL10_TMR10CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76060   TIMER_CTRL10_TMR10CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76061   TIMER_CTRL10_TMR10CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76062   TIMER_CTRL10_TMR10CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76063   TIMER_CTRL10_TMR10CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76064   TIMER_CTRL10_TMR10CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76065 } TIMER_CTRL10_TMR10CLK_Enum;
76066 
76067 /* ==============================================  TIMER CTRL10 TMR10FN [4..7]  ============================================== */
76068 typedef enum {                                  /*!< TIMER_CTRL10_TMR10FN                                                      */
76069   TIMER_CTRL10_TMR10FN_CONTINUOUS      = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
76070                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
76071   TIMER_CTRL10_TMR10FN_EDGE            = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
76072                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
76073                                                      follows CMP1.                                                             */
76074   TIMER_CTRL10_TMR10FN_UPCOUNT         = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
76075                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
76076                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
76077   TIMER_CTRL10_TMR10FN_PWM             = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
76078                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
76079   TIMER_CTRL10_TMR10FN_DOWNCOUNT       = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
76080                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
76081                                                      and OUT[1] formed by TIMER>=CMPn                                          */
76082   TIMER_CTRL10_TMR10FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76083                                                      LMT field specifies length of pattern. When LMT>32 OUT0
76084                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
76085                                                      is CMP1,CMP1                                                              */
76086   TIMER_CTRL10_TMR10FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76087                                                      pattern repeats after reaching LMT.                                       */
76088   TIMER_CTRL10_TMR10FN_EVENTTIMER      = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
76089                                                      trigger until next edge (rising or falling) of source clock
76090                                                      (used as a secondary event). This can be used to measure
76091                                                      time betwen GPIOs, etc.                                                   */
76092 } TIMER_CTRL10_TMR10FN_Enum;
76093 
76094 /* =============================================  TIMER CTRL10 TMR10POL1 [3..3]  ============================================= */
76095 typedef enum {                                  /*!< TIMER_CTRL10_TMR10POL1                                                    */
76096   TIMER_CTRL10_TMR10POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR10OUT1 pin is the same as the
76097                                                      timer output.                                                             */
76098   TIMER_CTRL10_TMR10POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR10OUT1 pin is the inverse
76099                                                      of the timer output.                                                      */
76100 } TIMER_CTRL10_TMR10POL1_Enum;
76101 
76102 /* =============================================  TIMER CTRL10 TMR10POL0 [2..2]  ============================================= */
76103 typedef enum {                                  /*!< TIMER_CTRL10_TMR10POL0                                                    */
76104   TIMER_CTRL10_TMR10POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR10OUT0 pin is the same as the
76105                                                      timer output.                                                             */
76106   TIMER_CTRL10_TMR10POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR10OUT0 pin is the inverse
76107                                                      of the timer output.                                                      */
76108 } TIMER_CTRL10_TMR10POL0_Enum;
76109 
76110 /* =============================================  TIMER CTRL10 TMR10CLR [1..1]  ============================================== */
76111 typedef enum {                                  /*!< TIMER_CTRL10_TMR10CLR                                                     */
76112   TIMER_CTRL10_TMR10CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76113                                                      cleared to its reset state (0 for count up counter, CMP0
76114                                                      for down counter)                                                         */
76115 } TIMER_CTRL10_TMR10CLR_Enum;
76116 
76117 /* ==============================================  TIMER CTRL10 TMR10EN [0..0]  ============================================== */
76118 typedef enum {                                  /*!< TIMER_CTRL10_TMR10EN                                                      */
76119   TIMER_CTRL10_TMR10EN_DIS             = 0,     /*!< DIS : Counter/Timer 10 Disable.                                           */
76120   TIMER_CTRL10_TMR10EN_EN              = 1,     /*!< EN : Counter/Timer 10 Enable.                                             */
76121 } TIMER_CTRL10_TMR10EN_Enum;
76122 
76123 /* ========================================================  TIMER10  ======================================================== */
76124 /* =======================================================  TMR10CMP0  ======================================================= */
76125 /* =======================================================  TMR10CMP1  ======================================================= */
76126 /* ========================================================  MODE10  ========================================================= */
76127 /* ===========================================  TIMER MODE10 TMR10TRIGSEL [8..15]  =========================================== */
76128 typedef enum {                                  /*!< TIMER_MODE10_TMR10TRIGSEL                                                 */
76129   TIMER_MODE10_TMR10TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76130   TIMER_MODE10_TMR10TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76131   TIMER_MODE10_TMR10TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76132   TIMER_MODE10_TMR10TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76133   TIMER_MODE10_TMR10TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76134   TIMER_MODE10_TMR10TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76135   TIMER_MODE10_TMR10TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76136   TIMER_MODE10_TMR10TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76137   TIMER_MODE10_TMR10TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76138   TIMER_MODE10_TMR10TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76139   TIMER_MODE10_TMR10TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76140   TIMER_MODE10_TMR10TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76141   TIMER_MODE10_TMR10TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76142   TIMER_MODE10_TMR10TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76143   TIMER_MODE10_TMR10TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76144   TIMER_MODE10_TMR10TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76145   TIMER_MODE10_TMR10TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76146   TIMER_MODE10_TMR10TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76147   TIMER_MODE10_TMR10TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76148   TIMER_MODE10_TMR10TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76149   TIMER_MODE10_TMR10TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76150   TIMER_MODE10_TMR10TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76151   TIMER_MODE10_TMR10TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76152   TIMER_MODE10_TMR10TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76153   TIMER_MODE10_TMR10TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76154   TIMER_MODE10_TMR10TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76155   TIMER_MODE10_TMR10TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76156   TIMER_MODE10_TMR10TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76157   TIMER_MODE10_TMR10TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76158   TIMER_MODE10_TMR10TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76159   TIMER_MODE10_TMR10TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76160   TIMER_MODE10_TMR10TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76161   TIMER_MODE10_TMR10TRIGSEL_STMRCMP00  = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
76162   TIMER_MODE10_TMR10TRIGSEL_STMRCMP10  = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
76163   TIMER_MODE10_TMR10TRIGSEL_STMRCMP20  = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
76164   TIMER_MODE10_TMR10TRIGSEL_STMRCMP30  = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
76165   TIMER_MODE10_TMR10TRIGSEL_STMRCMP40  = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
76166   TIMER_MODE10_TMR10TRIGSEL_STMRCMP50  = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
76167   TIMER_MODE10_TMR10TRIGSEL_STMRCMP60  = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
76168   TIMER_MODE10_TMR10TRIGSEL_STMRCMP70  = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
76169   TIMER_MODE10_TMR10TRIGSEL_STMRCAP00  = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
76170   TIMER_MODE10_TMR10TRIGSEL_STMRCAP10  = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
76171   TIMER_MODE10_TMR10TRIGSEL_STMRCAP20  = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
76172   TIMER_MODE10_TMR10TRIGSEL_STMRCAP30  = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
76173   TIMER_MODE10_TMR10TRIGSEL_STMRCAP40  = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
76174   TIMER_MODE10_TMR10TRIGSEL_STMRCAP50  = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
76175   TIMER_MODE10_TMR10TRIGSEL_STMRCAP60  = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
76176   TIMER_MODE10_TMR10TRIGSEL_STMRCAP70  = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
76177   TIMER_MODE10_TMR10TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76178   TIMER_MODE10_TMR10TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76179 } TIMER_MODE10_TMR10TRIGSEL_Enum;
76180 
76181 /* ========================================================  CTRL11  ========================================================= */
76182 /* ===========================================  TIMER CTRL11 TMR11TMODE [16..17]  ============================================ */
76183 typedef enum {                                  /*!< TIMER_CTRL11_TMR11TMODE                                                   */
76184   TIMER_CTRL11_TMR11TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
76185   TIMER_CTRL11_TMR11TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76186   TIMER_CTRL11_TMR11TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76187   TIMER_CTRL11_TMR11TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76188 } TIMER_CTRL11_TMR11TMODE_Enum;
76189 
76190 /* =============================================  TIMER CTRL11 TMR11CLK [8..15]  ============================================= */
76191 typedef enum {                                  /*!< TIMER_CTRL11_TMR11CLK                                                     */
76192   TIMER_CTRL11_TMR11CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76193   TIMER_CTRL11_TMR11CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76194   TIMER_CTRL11_TMR11CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76195   TIMER_CTRL11_TMR11CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76196   TIMER_CTRL11_TMR11CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76197   TIMER_CTRL11_TMR11CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
76198   TIMER_CTRL11_TMR11CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76199   TIMER_CTRL11_TMR11CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76200   TIMER_CTRL11_TMR11CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76201   TIMER_CTRL11_TMR11CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76202   TIMER_CTRL11_TMR11CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76203   TIMER_CTRL11_TMR11CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76204   TIMER_CTRL11_TMR11CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76205   TIMER_CTRL11_TMR11CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76206   TIMER_CTRL11_TMR11CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76207   TIMER_CTRL11_TMR11CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76208   TIMER_CTRL11_TMR11CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76209   TIMER_CTRL11_TMR11CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76210   TIMER_CTRL11_TMR11CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76211   TIMER_CTRL11_TMR11CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76212   TIMER_CTRL11_TMR11CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76213   TIMER_CTRL11_TMR11CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76214   TIMER_CTRL11_TMR11CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76215   TIMER_CTRL11_TMR11CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76216   TIMER_CTRL11_TMR11CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76217   TIMER_CTRL11_TMR11CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76218   TIMER_CTRL11_TMR11CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76219   TIMER_CTRL11_TMR11CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76220   TIMER_CTRL11_TMR11CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76221   TIMER_CTRL11_TMR11CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76222   TIMER_CTRL11_TMR11CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76223   TIMER_CTRL11_TMR11CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76224   TIMER_CTRL11_TMR11CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76225   TIMER_CTRL11_TMR11CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76226   TIMER_CTRL11_TMR11CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76227   TIMER_CTRL11_TMR11CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76228   TIMER_CTRL11_TMR11CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76229   TIMER_CTRL11_TMR11CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76230   TIMER_CTRL11_TMR11CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76231   TIMER_CTRL11_TMR11CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76232   TIMER_CTRL11_TMR11CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76233   TIMER_CTRL11_TMR11CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76234   TIMER_CTRL11_TMR11CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76235   TIMER_CTRL11_TMR11CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76236   TIMER_CTRL11_TMR11CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76237   TIMER_CTRL11_TMR11CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76238   TIMER_CTRL11_TMR11CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76239   TIMER_CTRL11_TMR11CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76240   TIMER_CTRL11_TMR11CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76241   TIMER_CTRL11_TMR11CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76242   TIMER_CTRL11_TMR11CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76243   TIMER_CTRL11_TMR11CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76244   TIMER_CTRL11_TMR11CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76245   TIMER_CTRL11_TMR11CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76246   TIMER_CTRL11_TMR11CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76247   TIMER_CTRL11_TMR11CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76248   TIMER_CTRL11_TMR11CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76249 } TIMER_CTRL11_TMR11CLK_Enum;
76250 
76251 /* ==============================================  TIMER CTRL11 TMR11FN [4..7]  ============================================== */
76252 typedef enum {                                  /*!< TIMER_CTRL11_TMR11FN                                                      */
76253   TIMER_CTRL11_TMR11FN_CONTINUOUS      = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
76254                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
76255   TIMER_CTRL11_TMR11FN_EDGE            = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
76256                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
76257                                                      follows CMP1.                                                             */
76258   TIMER_CTRL11_TMR11FN_UPCOUNT         = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
76259                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
76260                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
76261   TIMER_CTRL11_TMR11FN_PWM             = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
76262                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
76263   TIMER_CTRL11_TMR11FN_DOWNCOUNT       = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
76264                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
76265                                                      and OUT[1] formed by TIMER>=CMPn                                          */
76266   TIMER_CTRL11_TMR11FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76267                                                      LMT field specifies length of pattern. When LMT>32 OUT0
76268                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
76269                                                      is CMP1,CMP1                                                              */
76270   TIMER_CTRL11_TMR11FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76271                                                      pattern repeats after reaching LMT.                                       */
76272   TIMER_CTRL11_TMR11FN_EVENTTIMER      = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
76273                                                      trigger until next edge (rising or falling) of source clock
76274                                                      (used as a secondary event). This can be used to measure
76275                                                      time betwen GPIOs, etc.                                                   */
76276 } TIMER_CTRL11_TMR11FN_Enum;
76277 
76278 /* =============================================  TIMER CTRL11 TMR11POL1 [3..3]  ============================================= */
76279 typedef enum {                                  /*!< TIMER_CTRL11_TMR11POL1                                                    */
76280   TIMER_CTRL11_TMR11POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR11OUT1 pin is the same as the
76281                                                      timer output.                                                             */
76282   TIMER_CTRL11_TMR11POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR11OUT1 pin is the inverse
76283                                                      of the timer output.                                                      */
76284 } TIMER_CTRL11_TMR11POL1_Enum;
76285 
76286 /* =============================================  TIMER CTRL11 TMR11POL0 [2..2]  ============================================= */
76287 typedef enum {                                  /*!< TIMER_CTRL11_TMR11POL0                                                    */
76288   TIMER_CTRL11_TMR11POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR11OUT0 pin is the same as the
76289                                                      timer output.                                                             */
76290   TIMER_CTRL11_TMR11POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR11OUT0 pin is the inverse
76291                                                      of the timer output.                                                      */
76292 } TIMER_CTRL11_TMR11POL0_Enum;
76293 
76294 /* =============================================  TIMER CTRL11 TMR11CLR [1..1]  ============================================== */
76295 typedef enum {                                  /*!< TIMER_CTRL11_TMR11CLR                                                     */
76296   TIMER_CTRL11_TMR11CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76297                                                      cleared to its reset state (0 for count up counter, CMP0
76298                                                      for down counter)                                                         */
76299 } TIMER_CTRL11_TMR11CLR_Enum;
76300 
76301 /* ==============================================  TIMER CTRL11 TMR11EN [0..0]  ============================================== */
76302 typedef enum {                                  /*!< TIMER_CTRL11_TMR11EN                                                      */
76303   TIMER_CTRL11_TMR11EN_DIS             = 0,     /*!< DIS : Counter/Timer 11 Disable.                                           */
76304   TIMER_CTRL11_TMR11EN_EN              = 1,     /*!< EN : Counter/Timer 11 Enable.                                             */
76305 } TIMER_CTRL11_TMR11EN_Enum;
76306 
76307 /* ========================================================  TIMER11  ======================================================== */
76308 /* =======================================================  TMR11CMP0  ======================================================= */
76309 /* =======================================================  TMR11CMP1  ======================================================= */
76310 /* ========================================================  MODE11  ========================================================= */
76311 /* ===========================================  TIMER MODE11 TMR11TRIGSEL [8..15]  =========================================== */
76312 typedef enum {                                  /*!< TIMER_MODE11_TMR11TRIGSEL                                                 */
76313   TIMER_MODE11_TMR11TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76314   TIMER_MODE11_TMR11TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76315   TIMER_MODE11_TMR11TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76316   TIMER_MODE11_TMR11TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76317   TIMER_MODE11_TMR11TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76318   TIMER_MODE11_TMR11TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76319   TIMER_MODE11_TMR11TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76320   TIMER_MODE11_TMR11TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76321   TIMER_MODE11_TMR11TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76322   TIMER_MODE11_TMR11TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76323   TIMER_MODE11_TMR11TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76324   TIMER_MODE11_TMR11TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76325   TIMER_MODE11_TMR11TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76326   TIMER_MODE11_TMR11TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76327   TIMER_MODE11_TMR11TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76328   TIMER_MODE11_TMR11TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76329   TIMER_MODE11_TMR11TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76330   TIMER_MODE11_TMR11TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76331   TIMER_MODE11_TMR11TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76332   TIMER_MODE11_TMR11TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76333   TIMER_MODE11_TMR11TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76334   TIMER_MODE11_TMR11TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76335   TIMER_MODE11_TMR11TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76336   TIMER_MODE11_TMR11TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76337   TIMER_MODE11_TMR11TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76338   TIMER_MODE11_TMR11TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76339   TIMER_MODE11_TMR11TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76340   TIMER_MODE11_TMR11TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76341   TIMER_MODE11_TMR11TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76342   TIMER_MODE11_TMR11TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76343   TIMER_MODE11_TMR11TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76344   TIMER_MODE11_TMR11TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76345   TIMER_MODE11_TMR11TRIGSEL_STMRCMP00  = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
76346   TIMER_MODE11_TMR11TRIGSEL_STMRCMP10  = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
76347   TIMER_MODE11_TMR11TRIGSEL_STMRCMP20  = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
76348   TIMER_MODE11_TMR11TRIGSEL_STMRCMP30  = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
76349   TIMER_MODE11_TMR11TRIGSEL_STMRCMP40  = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
76350   TIMER_MODE11_TMR11TRIGSEL_STMRCMP50  = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
76351   TIMER_MODE11_TMR11TRIGSEL_STMRCMP60  = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
76352   TIMER_MODE11_TMR11TRIGSEL_STMRCMP70  = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
76353   TIMER_MODE11_TMR11TRIGSEL_STMRCAP00  = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
76354   TIMER_MODE11_TMR11TRIGSEL_STMRCAP10  = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
76355   TIMER_MODE11_TMR11TRIGSEL_STMRCAP20  = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
76356   TIMER_MODE11_TMR11TRIGSEL_STMRCAP30  = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
76357   TIMER_MODE11_TMR11TRIGSEL_STMRCAP40  = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
76358   TIMER_MODE11_TMR11TRIGSEL_STMRCAP50  = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
76359   TIMER_MODE11_TMR11TRIGSEL_STMRCAP60  = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
76360   TIMER_MODE11_TMR11TRIGSEL_STMRCAP70  = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
76361   TIMER_MODE11_TMR11TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76362   TIMER_MODE11_TMR11TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76363 } TIMER_MODE11_TMR11TRIGSEL_Enum;
76364 
76365 /* ========================================================  CTRL12  ========================================================= */
76366 /* ===========================================  TIMER CTRL12 TMR12TMODE [16..17]  ============================================ */
76367 typedef enum {                                  /*!< TIMER_CTRL12_TMR12TMODE                                                   */
76368   TIMER_CTRL12_TMR12TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
76369   TIMER_CTRL12_TMR12TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76370   TIMER_CTRL12_TMR12TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76371   TIMER_CTRL12_TMR12TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76372 } TIMER_CTRL12_TMR12TMODE_Enum;
76373 
76374 /* =============================================  TIMER CTRL12 TMR12CLK [8..15]  ============================================= */
76375 typedef enum {                                  /*!< TIMER_CTRL12_TMR12CLK                                                     */
76376   TIMER_CTRL12_TMR12CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76377   TIMER_CTRL12_TMR12CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76378   TIMER_CTRL12_TMR12CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76379   TIMER_CTRL12_TMR12CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76380   TIMER_CTRL12_TMR12CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76381   TIMER_CTRL12_TMR12CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
76382   TIMER_CTRL12_TMR12CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76383   TIMER_CTRL12_TMR12CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76384   TIMER_CTRL12_TMR12CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76385   TIMER_CTRL12_TMR12CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76386   TIMER_CTRL12_TMR12CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76387   TIMER_CTRL12_TMR12CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76388   TIMER_CTRL12_TMR12CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76389   TIMER_CTRL12_TMR12CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76390   TIMER_CTRL12_TMR12CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76391   TIMER_CTRL12_TMR12CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76392   TIMER_CTRL12_TMR12CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76393   TIMER_CTRL12_TMR12CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76394   TIMER_CTRL12_TMR12CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76395   TIMER_CTRL12_TMR12CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76396   TIMER_CTRL12_TMR12CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76397   TIMER_CTRL12_TMR12CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76398   TIMER_CTRL12_TMR12CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76399   TIMER_CTRL12_TMR12CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76400   TIMER_CTRL12_TMR12CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76401   TIMER_CTRL12_TMR12CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76402   TIMER_CTRL12_TMR12CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76403   TIMER_CTRL12_TMR12CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76404   TIMER_CTRL12_TMR12CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76405   TIMER_CTRL12_TMR12CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76406   TIMER_CTRL12_TMR12CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76407   TIMER_CTRL12_TMR12CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76408   TIMER_CTRL12_TMR12CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76409   TIMER_CTRL12_TMR12CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76410   TIMER_CTRL12_TMR12CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76411   TIMER_CTRL12_TMR12CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76412   TIMER_CTRL12_TMR12CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76413   TIMER_CTRL12_TMR12CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76414   TIMER_CTRL12_TMR12CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76415   TIMER_CTRL12_TMR12CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76416   TIMER_CTRL12_TMR12CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76417   TIMER_CTRL12_TMR12CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76418   TIMER_CTRL12_TMR12CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76419   TIMER_CTRL12_TMR12CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76420   TIMER_CTRL12_TMR12CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76421   TIMER_CTRL12_TMR12CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76422   TIMER_CTRL12_TMR12CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76423   TIMER_CTRL12_TMR12CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76424   TIMER_CTRL12_TMR12CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76425   TIMER_CTRL12_TMR12CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76426   TIMER_CTRL12_TMR12CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76427   TIMER_CTRL12_TMR12CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76428   TIMER_CTRL12_TMR12CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76429   TIMER_CTRL12_TMR12CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76430   TIMER_CTRL12_TMR12CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76431   TIMER_CTRL12_TMR12CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76432   TIMER_CTRL12_TMR12CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76433 } TIMER_CTRL12_TMR12CLK_Enum;
76434 
76435 /* ==============================================  TIMER CTRL12 TMR12FN [4..7]  ============================================== */
76436 typedef enum {                                  /*!< TIMER_CTRL12_TMR12FN                                                      */
76437   TIMER_CTRL12_TMR12FN_CONTINUOUS      = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
76438                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
76439   TIMER_CTRL12_TMR12FN_EDGE            = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
76440                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
76441                                                      follows CMP1.                                                             */
76442   TIMER_CTRL12_TMR12FN_UPCOUNT         = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
76443                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
76444                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
76445   TIMER_CTRL12_TMR12FN_PWM             = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
76446                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
76447   TIMER_CTRL12_TMR12FN_DOWNCOUNT       = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
76448                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
76449                                                      and OUT[1] formed by TIMER>=CMPn                                          */
76450   TIMER_CTRL12_TMR12FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76451                                                      LMT field specifies length of pattern. When LMT>32 OUT0
76452                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
76453                                                      is CMP1,CMP1                                                              */
76454   TIMER_CTRL12_TMR12FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76455                                                      pattern repeats after reaching LMT.                                       */
76456   TIMER_CTRL12_TMR12FN_EVENTTIMER      = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
76457                                                      trigger until next edge (rising or falling) of source clock
76458                                                      (used as a secondary event). This can be used to measure
76459                                                      time betwen GPIOs, etc.                                                   */
76460 } TIMER_CTRL12_TMR12FN_Enum;
76461 
76462 /* =============================================  TIMER CTRL12 TMR12POL1 [3..3]  ============================================= */
76463 typedef enum {                                  /*!< TIMER_CTRL12_TMR12POL1                                                    */
76464   TIMER_CTRL12_TMR12POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR12OUT1 pin is the same as the
76465                                                      timer output.                                                             */
76466   TIMER_CTRL12_TMR12POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR12OUT1 pin is the inverse
76467                                                      of the timer output.                                                      */
76468 } TIMER_CTRL12_TMR12POL1_Enum;
76469 
76470 /* =============================================  TIMER CTRL12 TMR12POL0 [2..2]  ============================================= */
76471 typedef enum {                                  /*!< TIMER_CTRL12_TMR12POL0                                                    */
76472   TIMER_CTRL12_TMR12POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR12OUT0 pin is the same as the
76473                                                      timer output.                                                             */
76474   TIMER_CTRL12_TMR12POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR12OUT0 pin is the inverse
76475                                                      of the timer output.                                                      */
76476 } TIMER_CTRL12_TMR12POL0_Enum;
76477 
76478 /* =============================================  TIMER CTRL12 TMR12CLR [1..1]  ============================================== */
76479 typedef enum {                                  /*!< TIMER_CTRL12_TMR12CLR                                                     */
76480   TIMER_CTRL12_TMR12CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76481                                                      cleared to its reset state (0 for count up counter, CMP0
76482                                                      for down counter)                                                         */
76483 } TIMER_CTRL12_TMR12CLR_Enum;
76484 
76485 /* ==============================================  TIMER CTRL12 TMR12EN [0..0]  ============================================== */
76486 typedef enum {                                  /*!< TIMER_CTRL12_TMR12EN                                                      */
76487   TIMER_CTRL12_TMR12EN_DIS             = 0,     /*!< DIS : Counter/Timer 12 Disable.                                           */
76488   TIMER_CTRL12_TMR12EN_EN              = 1,     /*!< EN : Counter/Timer 12 Enable.                                             */
76489 } TIMER_CTRL12_TMR12EN_Enum;
76490 
76491 /* ========================================================  TIMER12  ======================================================== */
76492 /* =======================================================  TMR12CMP0  ======================================================= */
76493 /* =======================================================  TMR12CMP1  ======================================================= */
76494 /* ========================================================  MODE12  ========================================================= */
76495 /* ===========================================  TIMER MODE12 TMR12TRIGSEL [8..15]  =========================================== */
76496 typedef enum {                                  /*!< TIMER_MODE12_TMR12TRIGSEL                                                 */
76497   TIMER_MODE12_TMR12TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76498   TIMER_MODE12_TMR12TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76499   TIMER_MODE12_TMR12TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76500   TIMER_MODE12_TMR12TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76501   TIMER_MODE12_TMR12TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76502   TIMER_MODE12_TMR12TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76503   TIMER_MODE12_TMR12TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76504   TIMER_MODE12_TMR12TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76505   TIMER_MODE12_TMR12TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76506   TIMER_MODE12_TMR12TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76507   TIMER_MODE12_TMR12TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76508   TIMER_MODE12_TMR12TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76509   TIMER_MODE12_TMR12TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76510   TIMER_MODE12_TMR12TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76511   TIMER_MODE12_TMR12TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76512   TIMER_MODE12_TMR12TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76513   TIMER_MODE12_TMR12TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76514   TIMER_MODE12_TMR12TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76515   TIMER_MODE12_TMR12TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76516   TIMER_MODE12_TMR12TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76517   TIMER_MODE12_TMR12TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76518   TIMER_MODE12_TMR12TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76519   TIMER_MODE12_TMR12TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76520   TIMER_MODE12_TMR12TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76521   TIMER_MODE12_TMR12TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76522   TIMER_MODE12_TMR12TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76523   TIMER_MODE12_TMR12TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76524   TIMER_MODE12_TMR12TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76525   TIMER_MODE12_TMR12TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76526   TIMER_MODE12_TMR12TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76527   TIMER_MODE12_TMR12TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76528   TIMER_MODE12_TMR12TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76529   TIMER_MODE12_TMR12TRIGSEL_STMRCMP00  = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
76530   TIMER_MODE12_TMR12TRIGSEL_STMRCMP10  = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
76531   TIMER_MODE12_TMR12TRIGSEL_STMRCMP20  = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
76532   TIMER_MODE12_TMR12TRIGSEL_STMRCMP30  = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
76533   TIMER_MODE12_TMR12TRIGSEL_STMRCMP40  = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
76534   TIMER_MODE12_TMR12TRIGSEL_STMRCMP50  = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
76535   TIMER_MODE12_TMR12TRIGSEL_STMRCMP60  = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
76536   TIMER_MODE12_TMR12TRIGSEL_STMRCMP70  = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
76537   TIMER_MODE12_TMR12TRIGSEL_STMRCAP00  = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
76538   TIMER_MODE12_TMR12TRIGSEL_STMRCAP10  = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
76539   TIMER_MODE12_TMR12TRIGSEL_STMRCAP20  = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
76540   TIMER_MODE12_TMR12TRIGSEL_STMRCAP30  = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
76541   TIMER_MODE12_TMR12TRIGSEL_STMRCAP40  = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
76542   TIMER_MODE12_TMR12TRIGSEL_STMRCAP50  = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
76543   TIMER_MODE12_TMR12TRIGSEL_STMRCAP60  = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
76544   TIMER_MODE12_TMR12TRIGSEL_STMRCAP70  = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
76545   TIMER_MODE12_TMR12TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76546   TIMER_MODE12_TMR12TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76547 } TIMER_MODE12_TMR12TRIGSEL_Enum;
76548 
76549 /* ========================================================  CTRL13  ========================================================= */
76550 /* ===========================================  TIMER CTRL13 TMR13TMODE [16..17]  ============================================ */
76551 typedef enum {                                  /*!< TIMER_CTRL13_TMR13TMODE                                                   */
76552   TIMER_CTRL13_TMR13TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
76553   TIMER_CTRL13_TMR13TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76554   TIMER_CTRL13_TMR13TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76555   TIMER_CTRL13_TMR13TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76556 } TIMER_CTRL13_TMR13TMODE_Enum;
76557 
76558 /* =============================================  TIMER CTRL13 TMR13CLK [8..15]  ============================================= */
76559 typedef enum {                                  /*!< TIMER_CTRL13_TMR13CLK                                                     */
76560   TIMER_CTRL13_TMR13CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76561   TIMER_CTRL13_TMR13CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76562   TIMER_CTRL13_TMR13CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76563   TIMER_CTRL13_TMR13CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76564   TIMER_CTRL13_TMR13CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76565   TIMER_CTRL13_TMR13CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
76566   TIMER_CTRL13_TMR13CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76567   TIMER_CTRL13_TMR13CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76568   TIMER_CTRL13_TMR13CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76569   TIMER_CTRL13_TMR13CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76570   TIMER_CTRL13_TMR13CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76571   TIMER_CTRL13_TMR13CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76572   TIMER_CTRL13_TMR13CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76573   TIMER_CTRL13_TMR13CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76574   TIMER_CTRL13_TMR13CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76575   TIMER_CTRL13_TMR13CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76576   TIMER_CTRL13_TMR13CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76577   TIMER_CTRL13_TMR13CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76578   TIMER_CTRL13_TMR13CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76579   TIMER_CTRL13_TMR13CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76580   TIMER_CTRL13_TMR13CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76581   TIMER_CTRL13_TMR13CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76582   TIMER_CTRL13_TMR13CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76583   TIMER_CTRL13_TMR13CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76584   TIMER_CTRL13_TMR13CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76585   TIMER_CTRL13_TMR13CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76586   TIMER_CTRL13_TMR13CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76587   TIMER_CTRL13_TMR13CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76588   TIMER_CTRL13_TMR13CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76589   TIMER_CTRL13_TMR13CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76590   TIMER_CTRL13_TMR13CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76591   TIMER_CTRL13_TMR13CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76592   TIMER_CTRL13_TMR13CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76593   TIMER_CTRL13_TMR13CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76594   TIMER_CTRL13_TMR13CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76595   TIMER_CTRL13_TMR13CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76596   TIMER_CTRL13_TMR13CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76597   TIMER_CTRL13_TMR13CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76598   TIMER_CTRL13_TMR13CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76599   TIMER_CTRL13_TMR13CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76600   TIMER_CTRL13_TMR13CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76601   TIMER_CTRL13_TMR13CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76602   TIMER_CTRL13_TMR13CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76603   TIMER_CTRL13_TMR13CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76604   TIMER_CTRL13_TMR13CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76605   TIMER_CTRL13_TMR13CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76606   TIMER_CTRL13_TMR13CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76607   TIMER_CTRL13_TMR13CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76608   TIMER_CTRL13_TMR13CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76609   TIMER_CTRL13_TMR13CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76610   TIMER_CTRL13_TMR13CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76611   TIMER_CTRL13_TMR13CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76612   TIMER_CTRL13_TMR13CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76613   TIMER_CTRL13_TMR13CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76614   TIMER_CTRL13_TMR13CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76615   TIMER_CTRL13_TMR13CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76616   TIMER_CTRL13_TMR13CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76617 } TIMER_CTRL13_TMR13CLK_Enum;
76618 
76619 /* ==============================================  TIMER CTRL13 TMR13FN [4..7]  ============================================== */
76620 typedef enum {                                  /*!< TIMER_CTRL13_TMR13FN                                                      */
76621   TIMER_CTRL13_TMR13FN_CONTINUOUS      = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
76622                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
76623   TIMER_CTRL13_TMR13FN_EDGE            = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
76624                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
76625                                                      follows CMP1.                                                             */
76626   TIMER_CTRL13_TMR13FN_UPCOUNT         = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
76627                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
76628                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
76629   TIMER_CTRL13_TMR13FN_PWM             = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
76630                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
76631   TIMER_CTRL13_TMR13FN_DOWNCOUNT       = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
76632                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
76633                                                      and OUT[1] formed by TIMER>=CMPn                                          */
76634   TIMER_CTRL13_TMR13FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76635                                                      LMT field specifies length of pattern. When LMT>32 OUT0
76636                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
76637                                                      is CMP1,CMP1                                                              */
76638   TIMER_CTRL13_TMR13FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76639                                                      pattern repeats after reaching LMT.                                       */
76640   TIMER_CTRL13_TMR13FN_EVENTTIMER      = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
76641                                                      trigger until next edge (rising or falling) of source clock
76642                                                      (used as a secondary event). This can be used to measure
76643                                                      time betwen GPIOs, etc.                                                   */
76644 } TIMER_CTRL13_TMR13FN_Enum;
76645 
76646 /* =============================================  TIMER CTRL13 TMR13POL1 [3..3]  ============================================= */
76647 typedef enum {                                  /*!< TIMER_CTRL13_TMR13POL1                                                    */
76648   TIMER_CTRL13_TMR13POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR13OUT1 pin is the same as the
76649                                                      timer output.                                                             */
76650   TIMER_CTRL13_TMR13POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR13OUT1 pin is the inverse
76651                                                      of the timer output.                                                      */
76652 } TIMER_CTRL13_TMR13POL1_Enum;
76653 
76654 /* =============================================  TIMER CTRL13 TMR13POL0 [2..2]  ============================================= */
76655 typedef enum {                                  /*!< TIMER_CTRL13_TMR13POL0                                                    */
76656   TIMER_CTRL13_TMR13POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR13OUT0 pin is the same as the
76657                                                      timer output.                                                             */
76658   TIMER_CTRL13_TMR13POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR13OUT0 pin is the inverse
76659                                                      of the timer output.                                                      */
76660 } TIMER_CTRL13_TMR13POL0_Enum;
76661 
76662 /* =============================================  TIMER CTRL13 TMR13CLR [1..1]  ============================================== */
76663 typedef enum {                                  /*!< TIMER_CTRL13_TMR13CLR                                                     */
76664   TIMER_CTRL13_TMR13CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76665                                                      cleared to its reset state (0 for count up counter, CMP0
76666                                                      for down counter)                                                         */
76667 } TIMER_CTRL13_TMR13CLR_Enum;
76668 
76669 /* ==============================================  TIMER CTRL13 TMR13EN [0..0]  ============================================== */
76670 typedef enum {                                  /*!< TIMER_CTRL13_TMR13EN                                                      */
76671   TIMER_CTRL13_TMR13EN_DIS             = 0,     /*!< DIS : Counter/Timer 13 Disable.                                           */
76672   TIMER_CTRL13_TMR13EN_EN              = 1,     /*!< EN : Counter/Timer 13 Enable.                                             */
76673 } TIMER_CTRL13_TMR13EN_Enum;
76674 
76675 /* ========================================================  TIMER13  ======================================================== */
76676 /* =======================================================  TMR13CMP0  ======================================================= */
76677 /* =======================================================  TMR13CMP1  ======================================================= */
76678 /* ========================================================  MODE13  ========================================================= */
76679 /* ===========================================  TIMER MODE13 TMR13TRIGSEL [8..15]  =========================================== */
76680 typedef enum {                                  /*!< TIMER_MODE13_TMR13TRIGSEL                                                 */
76681   TIMER_MODE13_TMR13TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76682   TIMER_MODE13_TMR13TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76683   TIMER_MODE13_TMR13TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76684   TIMER_MODE13_TMR13TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76685   TIMER_MODE13_TMR13TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76686   TIMER_MODE13_TMR13TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76687   TIMER_MODE13_TMR13TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76688   TIMER_MODE13_TMR13TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76689   TIMER_MODE13_TMR13TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76690   TIMER_MODE13_TMR13TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76691   TIMER_MODE13_TMR13TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76692   TIMER_MODE13_TMR13TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76693   TIMER_MODE13_TMR13TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76694   TIMER_MODE13_TMR13TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76695   TIMER_MODE13_TMR13TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76696   TIMER_MODE13_TMR13TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76697   TIMER_MODE13_TMR13TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76698   TIMER_MODE13_TMR13TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76699   TIMER_MODE13_TMR13TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76700   TIMER_MODE13_TMR13TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76701   TIMER_MODE13_TMR13TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76702   TIMER_MODE13_TMR13TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76703   TIMER_MODE13_TMR13TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76704   TIMER_MODE13_TMR13TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76705   TIMER_MODE13_TMR13TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76706   TIMER_MODE13_TMR13TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76707   TIMER_MODE13_TMR13TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76708   TIMER_MODE13_TMR13TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76709   TIMER_MODE13_TMR13TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76710   TIMER_MODE13_TMR13TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76711   TIMER_MODE13_TMR13TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76712   TIMER_MODE13_TMR13TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76713   TIMER_MODE13_TMR13TRIGSEL_STMRCMP00  = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
76714   TIMER_MODE13_TMR13TRIGSEL_STMRCMP10  = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
76715   TIMER_MODE13_TMR13TRIGSEL_STMRCMP20  = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
76716   TIMER_MODE13_TMR13TRIGSEL_STMRCMP30  = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
76717   TIMER_MODE13_TMR13TRIGSEL_STMRCMP40  = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
76718   TIMER_MODE13_TMR13TRIGSEL_STMRCMP50  = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
76719   TIMER_MODE13_TMR13TRIGSEL_STMRCMP60  = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
76720   TIMER_MODE13_TMR13TRIGSEL_STMRCMP70  = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
76721   TIMER_MODE13_TMR13TRIGSEL_STMRCAP00  = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
76722   TIMER_MODE13_TMR13TRIGSEL_STMRCAP10  = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
76723   TIMER_MODE13_TMR13TRIGSEL_STMRCAP20  = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
76724   TIMER_MODE13_TMR13TRIGSEL_STMRCAP30  = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
76725   TIMER_MODE13_TMR13TRIGSEL_STMRCAP40  = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
76726   TIMER_MODE13_TMR13TRIGSEL_STMRCAP50  = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
76727   TIMER_MODE13_TMR13TRIGSEL_STMRCAP60  = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
76728   TIMER_MODE13_TMR13TRIGSEL_STMRCAP70  = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
76729   TIMER_MODE13_TMR13TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76730   TIMER_MODE13_TMR13TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76731 } TIMER_MODE13_TMR13TRIGSEL_Enum;
76732 
76733 /* ========================================================  CTRL14  ========================================================= */
76734 /* ===========================================  TIMER CTRL14 TMR14TMODE [16..17]  ============================================ */
76735 typedef enum {                                  /*!< TIMER_CTRL14_TMR14TMODE                                                   */
76736   TIMER_CTRL14_TMR14TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
76737   TIMER_CTRL14_TMR14TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76738   TIMER_CTRL14_TMR14TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76739   TIMER_CTRL14_TMR14TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76740 } TIMER_CTRL14_TMR14TMODE_Enum;
76741 
76742 /* =============================================  TIMER CTRL14 TMR14CLK [8..15]  ============================================= */
76743 typedef enum {                                  /*!< TIMER_CTRL14_TMR14CLK                                                     */
76744   TIMER_CTRL14_TMR14CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76745   TIMER_CTRL14_TMR14CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76746   TIMER_CTRL14_TMR14CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76747   TIMER_CTRL14_TMR14CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76748   TIMER_CTRL14_TMR14CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76749   TIMER_CTRL14_TMR14CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
76750   TIMER_CTRL14_TMR14CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76751   TIMER_CTRL14_TMR14CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76752   TIMER_CTRL14_TMR14CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76753   TIMER_CTRL14_TMR14CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76754   TIMER_CTRL14_TMR14CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76755   TIMER_CTRL14_TMR14CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76756   TIMER_CTRL14_TMR14CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76757   TIMER_CTRL14_TMR14CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76758   TIMER_CTRL14_TMR14CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76759   TIMER_CTRL14_TMR14CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76760   TIMER_CTRL14_TMR14CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76761   TIMER_CTRL14_TMR14CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76762   TIMER_CTRL14_TMR14CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76763   TIMER_CTRL14_TMR14CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76764   TIMER_CTRL14_TMR14CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76765   TIMER_CTRL14_TMR14CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76766   TIMER_CTRL14_TMR14CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76767   TIMER_CTRL14_TMR14CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76768   TIMER_CTRL14_TMR14CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76769   TIMER_CTRL14_TMR14CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76770   TIMER_CTRL14_TMR14CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76771   TIMER_CTRL14_TMR14CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76772   TIMER_CTRL14_TMR14CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76773   TIMER_CTRL14_TMR14CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76774   TIMER_CTRL14_TMR14CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76775   TIMER_CTRL14_TMR14CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76776   TIMER_CTRL14_TMR14CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76777   TIMER_CTRL14_TMR14CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76778   TIMER_CTRL14_TMR14CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76779   TIMER_CTRL14_TMR14CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76780   TIMER_CTRL14_TMR14CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76781   TIMER_CTRL14_TMR14CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76782   TIMER_CTRL14_TMR14CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76783   TIMER_CTRL14_TMR14CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76784   TIMER_CTRL14_TMR14CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76785   TIMER_CTRL14_TMR14CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76786   TIMER_CTRL14_TMR14CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76787   TIMER_CTRL14_TMR14CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76788   TIMER_CTRL14_TMR14CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76789   TIMER_CTRL14_TMR14CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76790   TIMER_CTRL14_TMR14CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76791   TIMER_CTRL14_TMR14CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76792   TIMER_CTRL14_TMR14CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76793   TIMER_CTRL14_TMR14CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76794   TIMER_CTRL14_TMR14CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76795   TIMER_CTRL14_TMR14CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76796   TIMER_CTRL14_TMR14CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76797   TIMER_CTRL14_TMR14CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76798   TIMER_CTRL14_TMR14CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76799   TIMER_CTRL14_TMR14CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76800   TIMER_CTRL14_TMR14CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76801 } TIMER_CTRL14_TMR14CLK_Enum;
76802 
76803 /* ==============================================  TIMER CTRL14 TMR14FN [4..7]  ============================================== */
76804 typedef enum {                                  /*!< TIMER_CTRL14_TMR14FN                                                      */
76805   TIMER_CTRL14_TMR14FN_CONTINUOUS      = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
76806                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
76807   TIMER_CTRL14_TMR14FN_EDGE            = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
76808                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
76809                                                      follows CMP1.                                                             */
76810   TIMER_CTRL14_TMR14FN_UPCOUNT         = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
76811                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
76812                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
76813   TIMER_CTRL14_TMR14FN_PWM             = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
76814                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
76815   TIMER_CTRL14_TMR14FN_DOWNCOUNT       = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
76816                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
76817                                                      and OUT[1] formed by TIMER>=CMPn                                          */
76818   TIMER_CTRL14_TMR14FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76819                                                      LMT field specifies length of pattern. When LMT>32 OUT0
76820                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
76821                                                      is CMP1,CMP1                                                              */
76822   TIMER_CTRL14_TMR14FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76823                                                      pattern repeats after reaching LMT.                                       */
76824   TIMER_CTRL14_TMR14FN_EVENTTIMER      = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
76825                                                      trigger until next edge (rising or falling) of source clock
76826                                                      (used as a secondary event). This can be used to measure
76827                                                      time betwen GPIOs, etc.                                                   */
76828 } TIMER_CTRL14_TMR14FN_Enum;
76829 
76830 /* =============================================  TIMER CTRL14 TMR14POL1 [3..3]  ============================================= */
76831 typedef enum {                                  /*!< TIMER_CTRL14_TMR14POL1                                                    */
76832   TIMER_CTRL14_TMR14POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR14OUT1 pin is the same as the
76833                                                      timer output.                                                             */
76834   TIMER_CTRL14_TMR14POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR14OUT1 pin is the inverse
76835                                                      of the timer output.                                                      */
76836 } TIMER_CTRL14_TMR14POL1_Enum;
76837 
76838 /* =============================================  TIMER CTRL14 TMR14POL0 [2..2]  ============================================= */
76839 typedef enum {                                  /*!< TIMER_CTRL14_TMR14POL0                                                    */
76840   TIMER_CTRL14_TMR14POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR14OUT0 pin is the same as the
76841                                                      timer output.                                                             */
76842   TIMER_CTRL14_TMR14POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR14OUT0 pin is the inverse
76843                                                      of the timer output.                                                      */
76844 } TIMER_CTRL14_TMR14POL0_Enum;
76845 
76846 /* =============================================  TIMER CTRL14 TMR14CLR [1..1]  ============================================== */
76847 typedef enum {                                  /*!< TIMER_CTRL14_TMR14CLR                                                     */
76848   TIMER_CTRL14_TMR14CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76849                                                      cleared to its reset state (0 for count up counter, CMP0
76850                                                      for down counter)                                                         */
76851 } TIMER_CTRL14_TMR14CLR_Enum;
76852 
76853 /* ==============================================  TIMER CTRL14 TMR14EN [0..0]  ============================================== */
76854 typedef enum {                                  /*!< TIMER_CTRL14_TMR14EN                                                      */
76855   TIMER_CTRL14_TMR14EN_DIS             = 0,     /*!< DIS : Counter/Timer 14 Disable.                                           */
76856   TIMER_CTRL14_TMR14EN_EN              = 1,     /*!< EN : Counter/Timer 14 Enable.                                             */
76857 } TIMER_CTRL14_TMR14EN_Enum;
76858 
76859 /* ========================================================  TIMER14  ======================================================== */
76860 /* =======================================================  TMR14CMP0  ======================================================= */
76861 /* =======================================================  TMR14CMP1  ======================================================= */
76862 /* ========================================================  MODE14  ========================================================= */
76863 /* ===========================================  TIMER MODE14 TMR14TRIGSEL [8..15]  =========================================== */
76864 typedef enum {                                  /*!< TIMER_MODE14_TMR14TRIGSEL                                                 */
76865   TIMER_MODE14_TMR14TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76866   TIMER_MODE14_TMR14TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76867   TIMER_MODE14_TMR14TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76868   TIMER_MODE14_TMR14TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76869   TIMER_MODE14_TMR14TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76870   TIMER_MODE14_TMR14TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76871   TIMER_MODE14_TMR14TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76872   TIMER_MODE14_TMR14TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76873   TIMER_MODE14_TMR14TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76874   TIMER_MODE14_TMR14TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76875   TIMER_MODE14_TMR14TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76876   TIMER_MODE14_TMR14TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76877   TIMER_MODE14_TMR14TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76878   TIMER_MODE14_TMR14TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76879   TIMER_MODE14_TMR14TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76880   TIMER_MODE14_TMR14TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76881   TIMER_MODE14_TMR14TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76882   TIMER_MODE14_TMR14TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76883   TIMER_MODE14_TMR14TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76884   TIMER_MODE14_TMR14TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76885   TIMER_MODE14_TMR14TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76886   TIMER_MODE14_TMR14TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76887   TIMER_MODE14_TMR14TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76888   TIMER_MODE14_TMR14TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76889   TIMER_MODE14_TMR14TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76890   TIMER_MODE14_TMR14TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76891   TIMER_MODE14_TMR14TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76892   TIMER_MODE14_TMR14TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76893   TIMER_MODE14_TMR14TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76894   TIMER_MODE14_TMR14TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76895   TIMER_MODE14_TMR14TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76896   TIMER_MODE14_TMR14TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76897   TIMER_MODE14_TMR14TRIGSEL_STMRCMP00  = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
76898   TIMER_MODE14_TMR14TRIGSEL_STMRCMP10  = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
76899   TIMER_MODE14_TMR14TRIGSEL_STMRCMP20  = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
76900   TIMER_MODE14_TMR14TRIGSEL_STMRCMP30  = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
76901   TIMER_MODE14_TMR14TRIGSEL_STMRCMP40  = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
76902   TIMER_MODE14_TMR14TRIGSEL_STMRCMP50  = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
76903   TIMER_MODE14_TMR14TRIGSEL_STMRCMP60  = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
76904   TIMER_MODE14_TMR14TRIGSEL_STMRCMP70  = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
76905   TIMER_MODE14_TMR14TRIGSEL_STMRCAP00  = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
76906   TIMER_MODE14_TMR14TRIGSEL_STMRCAP10  = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
76907   TIMER_MODE14_TMR14TRIGSEL_STMRCAP20  = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
76908   TIMER_MODE14_TMR14TRIGSEL_STMRCAP30  = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
76909   TIMER_MODE14_TMR14TRIGSEL_STMRCAP40  = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
76910   TIMER_MODE14_TMR14TRIGSEL_STMRCAP50  = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
76911   TIMER_MODE14_TMR14TRIGSEL_STMRCAP60  = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
76912   TIMER_MODE14_TMR14TRIGSEL_STMRCAP70  = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
76913   TIMER_MODE14_TMR14TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76914   TIMER_MODE14_TMR14TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76915 } TIMER_MODE14_TMR14TRIGSEL_Enum;
76916 
76917 /* ========================================================  CTRL15  ========================================================= */
76918 /* ===========================================  TIMER CTRL15 TMR15TMODE [16..17]  ============================================ */
76919 typedef enum {                                  /*!< TIMER_CTRL15_TMR15TMODE                                                   */
76920   TIMER_CTRL15_TMR15TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
76921   TIMER_CTRL15_TMR15TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76922   TIMER_CTRL15_TMR15TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76923   TIMER_CTRL15_TMR15TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76924 } TIMER_CTRL15_TMR15TMODE_Enum;
76925 
76926 /* =============================================  TIMER CTRL15 TMR15CLK [8..15]  ============================================= */
76927 typedef enum {                                  /*!< TIMER_CTRL15_TMR15CLK                                                     */
76928   TIMER_CTRL15_TMR15CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76929   TIMER_CTRL15_TMR15CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76930   TIMER_CTRL15_TMR15CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76931   TIMER_CTRL15_TMR15CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76932   TIMER_CTRL15_TMR15CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76933   TIMER_CTRL15_TMR15CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
76934   TIMER_CTRL15_TMR15CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76935   TIMER_CTRL15_TMR15CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76936   TIMER_CTRL15_TMR15CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76937   TIMER_CTRL15_TMR15CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76938   TIMER_CTRL15_TMR15CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76939   TIMER_CTRL15_TMR15CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76940   TIMER_CTRL15_TMR15CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76941   TIMER_CTRL15_TMR15CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76942   TIMER_CTRL15_TMR15CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76943   TIMER_CTRL15_TMR15CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76944   TIMER_CTRL15_TMR15CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76945   TIMER_CTRL15_TMR15CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76946   TIMER_CTRL15_TMR15CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76947   TIMER_CTRL15_TMR15CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76948   TIMER_CTRL15_TMR15CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76949   TIMER_CTRL15_TMR15CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76950   TIMER_CTRL15_TMR15CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76951   TIMER_CTRL15_TMR15CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76952   TIMER_CTRL15_TMR15CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76953   TIMER_CTRL15_TMR15CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76954   TIMER_CTRL15_TMR15CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76955   TIMER_CTRL15_TMR15CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76956   TIMER_CTRL15_TMR15CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76957   TIMER_CTRL15_TMR15CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76958   TIMER_CTRL15_TMR15CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76959   TIMER_CTRL15_TMR15CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76960   TIMER_CTRL15_TMR15CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76961   TIMER_CTRL15_TMR15CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76962   TIMER_CTRL15_TMR15CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76963   TIMER_CTRL15_TMR15CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76964   TIMER_CTRL15_TMR15CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76965   TIMER_CTRL15_TMR15CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76966   TIMER_CTRL15_TMR15CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76967   TIMER_CTRL15_TMR15CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76968   TIMER_CTRL15_TMR15CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76969   TIMER_CTRL15_TMR15CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76970   TIMER_CTRL15_TMR15CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76971   TIMER_CTRL15_TMR15CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76972   TIMER_CTRL15_TMR15CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76973   TIMER_CTRL15_TMR15CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76974   TIMER_CTRL15_TMR15CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76975   TIMER_CTRL15_TMR15CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76976   TIMER_CTRL15_TMR15CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76977   TIMER_CTRL15_TMR15CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76978   TIMER_CTRL15_TMR15CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76979   TIMER_CTRL15_TMR15CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76980   TIMER_CTRL15_TMR15CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76981   TIMER_CTRL15_TMR15CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76982   TIMER_CTRL15_TMR15CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76983   TIMER_CTRL15_TMR15CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76984   TIMER_CTRL15_TMR15CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76985 } TIMER_CTRL15_TMR15CLK_Enum;
76986 
76987 /* ==============================================  TIMER CTRL15 TMR15FN [4..7]  ============================================== */
76988 typedef enum {                                  /*!< TIMER_CTRL15_TMR15FN                                                      */
76989   TIMER_CTRL15_TMR15FN_CONTINUOUS      = 0,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.
76990                                                      OUT[0]=(TIMER>CMP0), OUT[1]=(TIMER>CMP1)                                  */
76991   TIMER_CTRL15_TMR15FN_EDGE            = 1,     /*!< EDGE : Single run up counter generating an edge on CMP. OUT[0]=0,
76992                                                      counter increments to CMP0, OUT[0]=1, counter stops. OUT[1]
76993                                                      follows CMP1.                                                             */
76994   TIMER_CTRL15_TMR15FN_UPCOUNT         = 2,     /*!< UPCOUNT : Single run up counter generating a pulse on CMP. OUT[0]=0,
76995                                                      counter increments to CMP0, OUT[0]=1 (for one clock), timer
76996                                                      resets to 0, repeat. OUT[1]=1 for one cycle when CMP1 matches             */
76997   TIMER_CTRL15_TMR15FN_PWM             = 4,     /*!< PWM : PWM mode. OUT[0]=0, counter increments to CMP1, OUT[0]=1,
76998                                                      counter increments to CMP0, OUT[0]=0. Counter stops. OUT[1]=~OUT[0].      */
76999   TIMER_CTRL15_TMR15FN_DOWNCOUNT       = 6,     /*!< DOWNCOUNT : Counter starts at CMP0 and counts down to zero and
77000                                                      restarts. TMRLIMIT can create 1-255 repetitions. OUT[0]
77001                                                      and OUT[1] formed by TIMER>=CMPn                                          */
77002   TIMER_CTRL15_TMR15FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
77003                                                      LMT field specifies length of pattern. When LMT>32 OUT0
77004                                                      pattern is 64-bit pattern consisting of CMP1,CMP0 and OUT1
77005                                                      is CMP1,CMP1                                                              */
77006   TIMER_CTRL15_TMR15FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
77007                                                      pattern repeats after reaching LMT.                                       */
77008   TIMER_CTRL15_TMR15FN_EVENTTIMER      = 14,    /*!< EVENTTIMER : Timer uses bus clock to measure clock cycles from
77009                                                      trigger until next edge (rising or falling) of source clock
77010                                                      (used as a secondary event). This can be used to measure
77011                                                      time betwen GPIOs, etc.                                                   */
77012 } TIMER_CTRL15_TMR15FN_Enum;
77013 
77014 /* =============================================  TIMER CTRL15 TMR15POL1 [3..3]  ============================================= */
77015 typedef enum {                                  /*!< TIMER_CTRL15_TMR15POL1                                                    */
77016   TIMER_CTRL15_TMR15POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR15OUT1 pin is the same as the
77017                                                      timer output.                                                             */
77018   TIMER_CTRL15_TMR15POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR15OUT1 pin is the inverse
77019                                                      of the timer output.                                                      */
77020 } TIMER_CTRL15_TMR15POL1_Enum;
77021 
77022 /* =============================================  TIMER CTRL15 TMR15POL0 [2..2]  ============================================= */
77023 typedef enum {                                  /*!< TIMER_CTRL15_TMR15POL0                                                    */
77024   TIMER_CTRL15_TMR15POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR15OUT0 pin is the same as the
77025                                                      timer output.                                                             */
77026   TIMER_CTRL15_TMR15POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR15OUT0 pin is the inverse
77027                                                      of the timer output.                                                      */
77028 } TIMER_CTRL15_TMR15POL0_Enum;
77029 
77030 /* =============================================  TIMER CTRL15 TMR15CLR [1..1]  ============================================== */
77031 typedef enum {                                  /*!< TIMER_CTRL15_TMR15CLR                                                     */
77032   TIMER_CTRL15_TMR15CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
77033                                                      cleared to its reset state (0 for count up counter, CMP0
77034                                                      for down counter)                                                         */
77035 } TIMER_CTRL15_TMR15CLR_Enum;
77036 
77037 /* ==============================================  TIMER CTRL15 TMR15EN [0..0]  ============================================== */
77038 typedef enum {                                  /*!< TIMER_CTRL15_TMR15EN                                                      */
77039   TIMER_CTRL15_TMR15EN_DIS             = 0,     /*!< DIS : Counter/Timer 15 Disable.                                           */
77040   TIMER_CTRL15_TMR15EN_EN              = 1,     /*!< EN : Counter/Timer 15 Enable.                                             */
77041 } TIMER_CTRL15_TMR15EN_Enum;
77042 
77043 /* ========================================================  TIMER15  ======================================================== */
77044 /* =======================================================  TMR15CMP0  ======================================================= */
77045 /* =======================================================  TMR15CMP1  ======================================================= */
77046 /* ========================================================  MODE15  ========================================================= */
77047 /* ===========================================  TIMER MODE15 TMR15TRIGSEL [8..15]  =========================================== */
77048 typedef enum {                                  /*!< TIMER_MODE15_TMR15TRIGSEL                                                 */
77049   TIMER_MODE15_TMR15TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
77050   TIMER_MODE15_TMR15TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
77051   TIMER_MODE15_TMR15TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
77052   TIMER_MODE15_TMR15TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
77053   TIMER_MODE15_TMR15TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
77054   TIMER_MODE15_TMR15TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
77055   TIMER_MODE15_TMR15TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
77056   TIMER_MODE15_TMR15TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
77057   TIMER_MODE15_TMR15TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
77058   TIMER_MODE15_TMR15TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
77059   TIMER_MODE15_TMR15TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
77060   TIMER_MODE15_TMR15TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
77061   TIMER_MODE15_TMR15TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
77062   TIMER_MODE15_TMR15TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
77063   TIMER_MODE15_TMR15TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
77064   TIMER_MODE15_TMR15TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
77065   TIMER_MODE15_TMR15TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
77066   TIMER_MODE15_TMR15TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
77067   TIMER_MODE15_TMR15TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
77068   TIMER_MODE15_TMR15TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
77069   TIMER_MODE15_TMR15TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
77070   TIMER_MODE15_TMR15TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
77071   TIMER_MODE15_TMR15TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
77072   TIMER_MODE15_TMR15TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
77073   TIMER_MODE15_TMR15TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
77074   TIMER_MODE15_TMR15TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
77075   TIMER_MODE15_TMR15TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
77076   TIMER_MODE15_TMR15TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
77077   TIMER_MODE15_TMR15TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
77078   TIMER_MODE15_TMR15TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
77079   TIMER_MODE15_TMR15TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
77080   TIMER_MODE15_TMR15TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
77081   TIMER_MODE15_TMR15TRIGSEL_STMRCMP00  = 48,    /*!< STMRCMP00 : Trigger source is STIMER Compare 0                            */
77082   TIMER_MODE15_TMR15TRIGSEL_STMRCMP10  = 49,    /*!< STMRCMP10 : Trigger source is STIMER Compare 1                            */
77083   TIMER_MODE15_TMR15TRIGSEL_STMRCMP20  = 50,    /*!< STMRCMP20 : Trigger source is STIMER Compare 2                            */
77084   TIMER_MODE15_TMR15TRIGSEL_STMRCMP30  = 51,    /*!< STMRCMP30 : Trigger source is STIMER Compare 3                            */
77085   TIMER_MODE15_TMR15TRIGSEL_STMRCMP40  = 52,    /*!< STMRCMP40 : Trigger source is STIMER Compare 4                            */
77086   TIMER_MODE15_TMR15TRIGSEL_STMRCMP50  = 53,    /*!< STMRCMP50 : Trigger source is STIMER Compare 5                            */
77087   TIMER_MODE15_TMR15TRIGSEL_STMRCMP60  = 54,    /*!< STMRCMP60 : Trigger source is STIMER Compare 6                            */
77088   TIMER_MODE15_TMR15TRIGSEL_STMRCMP70  = 55,    /*!< STMRCMP70 : Trigger source is STIMER Compare 7                            */
77089   TIMER_MODE15_TMR15TRIGSEL_STMRCAP00  = 56,    /*!< STMRCAP00 : Trigger source is STIMER Capture 0                            */
77090   TIMER_MODE15_TMR15TRIGSEL_STMRCAP10  = 57,    /*!< STMRCAP10 : Trigger source is STIMER Capture 1                            */
77091   TIMER_MODE15_TMR15TRIGSEL_STMRCAP20  = 58,    /*!< STMRCAP20 : Trigger source is STIMER Capture 2                            */
77092   TIMER_MODE15_TMR15TRIGSEL_STMRCAP30  = 59,    /*!< STMRCAP30 : Trigger source is STIMER Capture 3                            */
77093   TIMER_MODE15_TMR15TRIGSEL_STMRCAP40  = 60,    /*!< STMRCAP40 : Trigger source is STIMER Capture 4                            */
77094   TIMER_MODE15_TMR15TRIGSEL_STMRCAP50  = 61,    /*!< STMRCAP50 : Trigger source is STIMER Capture 5                            */
77095   TIMER_MODE15_TMR15TRIGSEL_STMRCAP60  = 62,    /*!< STMRCAP60 : Trigger source is STIMER Capture 6                            */
77096   TIMER_MODE15_TMR15TRIGSEL_STMRCAP70  = 63,    /*!< STMRCAP70 : Trigger source is STIMER Capture 7                            */
77097   TIMER_MODE15_TMR15TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
77098   TIMER_MODE15_TMR15TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
77099 } TIMER_MODE15_TMR15TRIGSEL_Enum;
77100 
77101 
77102 
77103 /* =========================================================================================================================== */
77104 /* ================                                           UART0                                           ================ */
77105 /* =========================================================================================================================== */
77106 
77107 /* ==========================================================  DR  =========================================================== */
77108 /* ===============================================  UART0 DR OEDATA [11..11]  ================================================ */
77109 typedef enum {                                  /*!< UART0_DR_OEDATA                                                           */
77110   UART0_DR_OEDATA_NOERR                = 0,     /*!< NOERR : No error on UART OEDATA, overrun error indicator.                 */
77111   UART0_DR_OEDATA_ERR                  = 1,     /*!< ERR : Error on UART OEDATA, overrun error indicator.                      */
77112 } UART0_DR_OEDATA_Enum;
77113 
77114 /* ===============================================  UART0 DR BEDATA [10..10]  ================================================ */
77115 typedef enum {                                  /*!< UART0_DR_BEDATA                                                           */
77116   UART0_DR_BEDATA_NOERR                = 0,     /*!< NOERR : No error on UART BEDATA, break error indicator.                   */
77117   UART0_DR_BEDATA_ERR                  = 1,     /*!< ERR : Error on UART BEDATA, break error indicator.                        */
77118 } UART0_DR_BEDATA_Enum;
77119 
77120 /* ================================================  UART0 DR PEDATA [9..9]  ================================================= */
77121 typedef enum {                                  /*!< UART0_DR_PEDATA                                                           */
77122   UART0_DR_PEDATA_NOERR                = 0,     /*!< NOERR : No error on UART PEDATA, parity error indicator.                  */
77123   UART0_DR_PEDATA_ERR                  = 1,     /*!< ERR : Error on UART PEDATA, parity error indicator.                       */
77124 } UART0_DR_PEDATA_Enum;
77125 
77126 /* ================================================  UART0 DR FEDATA [8..8]  ================================================= */
77127 typedef enum {                                  /*!< UART0_DR_FEDATA                                                           */
77128   UART0_DR_FEDATA_NOERR                = 0,     /*!< NOERR : No error on UART FEDATA, framing error indicator.                 */
77129   UART0_DR_FEDATA_ERR                  = 1,     /*!< ERR : Error on UART FEDATA, framing error indicator.                      */
77130 } UART0_DR_FEDATA_Enum;
77131 
77132 /* ==========================================================  RSR  ========================================================== */
77133 /* ================================================  UART0 RSR OESTAT [3..3]  ================================================ */
77134 typedef enum {                                  /*!< UART0_RSR_OESTAT                                                          */
77135   UART0_RSR_OESTAT_NOERR               = 0,     /*!< NOERR : No error on UART OESTAT, overrun error indicator.                 */
77136   UART0_RSR_OESTAT_ERR                 = 1,     /*!< ERR : Error on UART OESTAT, overrun error indicator.                      */
77137 } UART0_RSR_OESTAT_Enum;
77138 
77139 /* ================================================  UART0 RSR BESTAT [2..2]  ================================================ */
77140 typedef enum {                                  /*!< UART0_RSR_BESTAT                                                          */
77141   UART0_RSR_BESTAT_NOERR               = 0,     /*!< NOERR : No error on UART BESTAT, break error indicator.                   */
77142   UART0_RSR_BESTAT_ERR                 = 1,     /*!< ERR : Error on UART BESTAT, break error indicator.                        */
77143 } UART0_RSR_BESTAT_Enum;
77144 
77145 /* ================================================  UART0 RSR PESTAT [1..1]  ================================================ */
77146 typedef enum {                                  /*!< UART0_RSR_PESTAT                                                          */
77147   UART0_RSR_PESTAT_NOERR               = 0,     /*!< NOERR : No error on UART PESTAT, parity error indicator.                  */
77148   UART0_RSR_PESTAT_ERR                 = 1,     /*!< ERR : Error on UART PESTAT, parity error indicator.                       */
77149 } UART0_RSR_PESTAT_Enum;
77150 
77151 /* ================================================  UART0 RSR FESTAT [0..0]  ================================================ */
77152 typedef enum {                                  /*!< UART0_RSR_FESTAT                                                          */
77153   UART0_RSR_FESTAT_NOERR               = 0,     /*!< NOERR : No error on UART FESTAT, framing error indicator.                 */
77154   UART0_RSR_FESTAT_ERR                 = 1,     /*!< ERR : Error on UART FESTAT, framing error indicator.                      */
77155 } UART0_RSR_FESTAT_Enum;
77156 
77157 /* ==========================================================  FR  =========================================================== */
77158 /* =================================================  UART0 FR TXFE [7..7]  ================================================== */
77159 typedef enum {                                  /*!< UART0_FR_TXFE                                                             */
77160   UART0_FR_TXFE_XMTFIFO_EMPTY          = 1,     /*!< XMTFIFO_EMPTY : Transmit fifo is empty.                                   */
77161 } UART0_FR_TXFE_Enum;
77162 
77163 /* =================================================  UART0 FR RXFF [6..6]  ================================================== */
77164 typedef enum {                                  /*!< UART0_FR_RXFF                                                             */
77165   UART0_FR_RXFF_RCVFIFO_FULL           = 1,     /*!< RCVFIFO_FULL : Receive fifo is full.                                      */
77166 } UART0_FR_RXFF_Enum;
77167 
77168 /* =================================================  UART0 FR TXFF [5..5]  ================================================== */
77169 typedef enum {                                  /*!< UART0_FR_TXFF                                                             */
77170   UART0_FR_TXFF_XMTFIFO_FULL           = 1,     /*!< XMTFIFO_FULL : Transmit fifo is full.                                     */
77171 } UART0_FR_TXFF_Enum;
77172 
77173 /* =================================================  UART0 FR RXFE [4..4]  ================================================== */
77174 typedef enum {                                  /*!< UART0_FR_RXFE                                                             */
77175   UART0_FR_RXFE_RCVFIFO_EMPTY          = 1,     /*!< RCVFIFO_EMPTY : Receive fifo is empty.                                    */
77176 } UART0_FR_RXFE_Enum;
77177 
77178 /* =================================================  UART0 FR BUSY [3..3]  ================================================== */
77179 typedef enum {                                  /*!< UART0_FR_BUSY                                                             */
77180   UART0_FR_BUSY_BUSY                   = 1,     /*!< BUSY : UART busy indicator.                                               */
77181 } UART0_FR_BUSY_Enum;
77182 
77183 /* ==================================================  UART0 FR DCD [2..2]  ================================================== */
77184 typedef enum {                                  /*!< UART0_FR_DCD                                                              */
77185   UART0_FR_DCD_DETECTED                = 1,     /*!< DETECTED : Data carrier detect detected.                                  */
77186 } UART0_FR_DCD_Enum;
77187 
77188 /* ==================================================  UART0 FR DSR [1..1]  ================================================== */
77189 typedef enum {                                  /*!< UART0_FR_DSR                                                              */
77190   UART0_FR_DSR_READY                   = 1,     /*!< READY : Data set ready.                                                   */
77191 } UART0_FR_DSR_Enum;
77192 
77193 /* ==================================================  UART0 FR CTS [0..0]  ================================================== */
77194 typedef enum {                                  /*!< UART0_FR_CTS                                                              */
77195   UART0_FR_CTS_CLEARTOSEND             = 1,     /*!< CLEARTOSEND : Clear to send is indicated.                                 */
77196 } UART0_FR_CTS_Enum;
77197 
77198 /* =========================================================  ILPR  ========================================================== */
77199 /* =========================================================  IBRD  ========================================================== */
77200 /* =========================================================  FBRD  ========================================================== */
77201 /* =========================================================  LCRH  ========================================================== */
77202 /* ==========================================================  CR  =========================================================== */
77203 /* ================================================  UART0 CR CLKSEL [4..6]  ================================================= */
77204 typedef enum {                                  /*!< UART0_CR_CLKSEL                                                           */
77205   UART0_CR_CLKSEL_NOCLK                = 0,     /*!< NOCLK : No UART clock. This is the low power default.                     */
77206   UART0_CR_CLKSEL_24MHZ                = 1,     /*!< 24MHZ : 24 MHz clock.                                                     */
77207   UART0_CR_CLKSEL_12MHZ                = 2,     /*!< 12MHZ : 12 MHz clock.                                                     */
77208   UART0_CR_CLKSEL_6MHZ                 = 3,     /*!< 6MHZ : 6 MHz clock.                                                       */
77209   UART0_CR_CLKSEL_3MHZ                 = 4,     /*!< 3MHZ : 3 MHz clock.                                                       */
77210   UART0_CR_CLKSEL_48MHZ                = 5,     /*!< 48MHZ : Reserved.                                                         */
77211 } UART0_CR_CLKSEL_Enum;
77212 
77213 /* =========================================================  IFLS  ========================================================== */
77214 /* ==========================================================  IER  ========================================================== */
77215 /* ==========================================================  IES  ========================================================== */
77216 /* ==========================================================  MIS  ========================================================== */
77217 /* ==========================================================  IEC  ========================================================== */
77218 
77219 
77220 /* =========================================================================================================================== */
77221 /* ================                                          USBPHY                                           ================ */
77222 /* =========================================================================================================================== */
77223 
77224 /* =========================================================  REG00  ========================================================= */
77225 /* =========================================================  REG04  ========================================================= */
77226 /* =========================================================  REG08  ========================================================= */
77227 /* =========================================================  REG0C  ========================================================= */
77228 /* =========================================================  REG10  ========================================================= */
77229 /* =========================================================  REG14  ========================================================= */
77230 /* =========================================================  REG18  ========================================================= */
77231 /* =========================================================  REG1C  ========================================================= */
77232 /* =========================================================  REG20  ========================================================= */
77233 /* =========================================================  REG24  ========================================================= */
77234 /* =========================================================  REG28  ========================================================= */
77235 /* =========================================================  REG2C  ========================================================= */
77236 /* =========================================================  REG30  ========================================================= */
77237 /* =========================================================  REG34  ========================================================= */
77238 /* =========================================================  REG38  ========================================================= */
77239 /* =========================================================  REG3C  ========================================================= */
77240 /* =========================================================  REG40  ========================================================= */
77241 /* =========================================================  REG44  ========================================================= */
77242 /* =========================================================  REG48  ========================================================= */
77243 /* =========================================================  REG4C  ========================================================= */
77244 /* =========================================================  REG50  ========================================================= */
77245 /* =========================================================  REG54  ========================================================= */
77246 /* =========================================================  REG58  ========================================================= */
77247 /* =========================================================  REG5C  ========================================================= */
77248 /* =========================================================  REG60  ========================================================= */
77249 /* =========================================================  REG64  ========================================================= */
77250 /* =========================================================  REG68  ========================================================= */
77251 /* =========================================================  REG6C  ========================================================= */
77252 /* =========================================================  REG70  ========================================================= */
77253 /* =========================================================  REG74  ========================================================= */
77254 /* =========================================================  REG78  ========================================================= */
77255 /* =========================================================  REG7C  ========================================================= */
77256 /* =========================================================  REG80  ========================================================= */
77257 /* =========================================================  REG84  ========================================================= */
77258 
77259 
77260 /* =========================================================================================================================== */
77261 /* ================                                            USB                                            ================ */
77262 /* =========================================================================================================================== */
77263 
77264 /* =========================================================  CFG0  ========================================================== */
77265 /* ============================================  USB CFG0 EP5InIntStat [21..21]  ============================================= */
77266 typedef enum {                                  /*!< USB_CFG0_EP5InIntStat                                                     */
77267   USB_CFG0_EP5InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77268   USB_CFG0_EP5InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
77269 } USB_CFG0_EP5InIntStat_Enum;
77270 
77271 /* ============================================  USB CFG0 EP4InIntStat [20..20]  ============================================= */
77272 typedef enum {                                  /*!< USB_CFG0_EP4InIntStat                                                     */
77273   USB_CFG0_EP4InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77274   USB_CFG0_EP4InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
77275 } USB_CFG0_EP4InIntStat_Enum;
77276 
77277 /* ============================================  USB CFG0 EP3InIntStat [19..19]  ============================================= */
77278 typedef enum {                                  /*!< USB_CFG0_EP3InIntStat                                                     */
77279   USB_CFG0_EP3InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77280   USB_CFG0_EP3InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
77281 } USB_CFG0_EP3InIntStat_Enum;
77282 
77283 /* ============================================  USB CFG0 EP2InIntStat [18..18]  ============================================= */
77284 typedef enum {                                  /*!< USB_CFG0_EP2InIntStat                                                     */
77285   USB_CFG0_EP2InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77286   USB_CFG0_EP2InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
77287 } USB_CFG0_EP2InIntStat_Enum;
77288 
77289 /* ============================================  USB CFG0 EP1InIntStat [17..17]  ============================================= */
77290 typedef enum {                                  /*!< USB_CFG0_EP1InIntStat                                                     */
77291   USB_CFG0_EP1InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77292   USB_CFG0_EP1InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
77293 } USB_CFG0_EP1InIntStat_Enum;
77294 
77295 /* ============================================  USB CFG0 EP0InIntStat [16..16]  ============================================= */
77296 typedef enum {                                  /*!< USB_CFG0_EP0InIntStat                                                     */
77297   USB_CFG0_EP0InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77298   USB_CFG0_EP0InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
77299 } USB_CFG0_EP0InIntStat_Enum;
77300 
77301 /* ==============================================  USB CFG0 ISOUpdate [15..15]  ============================================== */
77302 typedef enum {                                  /*!< USB_CFG0_ISOUpdate                                                        */
77303   USB_CFG0_ISOUpdate_DONT_WAIT         = 0,     /*!< DONT_WAIT : Clear for USB Controller not to wait for SOF token
77304                                                      before sending packet.                                                    */
77305   USB_CFG0_ISOUpdate_WAIT              = 1,     /*!< WAIT : Set to have USB Controller wait for SOF token before
77306                                                      sending packet.                                                           */
77307 } USB_CFG0_ISOUpdate_Enum;
77308 
77309 /* =============================================  USB CFG0 AMSPECIFIC [14..14]  ============================================== */
77310 typedef enum {                                  /*!< USB_CFG0_AMSPECIFIC                                                       */
77311   USB_CFG0_AMSPECIFIC_NOT_CONNECTED    = 0,     /*!< NOT_CONNECTED : Clear to disable/disconnect USB lines.                    */
77312   USB_CFG0_AMSPECIFIC_CONNECTED        = 1,     /*!< CONNECTED : Set to enable USB lines.                                      */
77313 } USB_CFG0_AMSPECIFIC_Enum;
77314 
77315 /* ===============================================  USB CFG0 HSEnab [13..13]  ================================================ */
77316 typedef enum {                                  /*!< USB_CFG0_HSEnab                                                           */
77317   USB_CFG0_HSEnab_DIS_HS               = 0,     /*!< DIS_HS : Clear to disable High-speed mode (Full-speed mode only).         */
77318   USB_CFG0_HSEnab_EN_HS                = 1,     /*!< EN_HS : Set to enable High-speed mode.                                    */
77319 } USB_CFG0_HSEnab_Enum;
77320 
77321 /* ===============================================  USB CFG0 HSMode [12..12]  ================================================ */
77322 typedef enum {                                  /*!< USB_CFG0_HSMode                                                           */
77323   USB_CFG0_HSMode_FS_MODE              = 0,     /*!< FS_MODE : Indicates USB Controller is in Full-speed mode only.            */
77324   USB_CFG0_HSMode_HS_MODE              = 1,     /*!< HS_MODE : Indicates USB Controller is in High-speed mode.                 */
77325 } USB_CFG0_HSMode_Enum;
77326 
77327 /* ================================================  USB CFG0 Reset [11..11]  ================================================ */
77328 typedef enum {                                  /*!< USB_CFG0_Reset                                                            */
77329   USB_CFG0_Reset_NEG_RESET_COMPLETE    = 0,     /*!< NEG_RESET_COMPLETE : Indicates that HS negotiation has completed
77330                                                      successfully, or 2.1 ms of reset signaling has elapsed.                   */
77331   USB_CFG0_Reset_RESETTING             = 1,     /*!< RESETTING : Indicates that Reset signaling is detected and remains
77332                                                      high until the bus reverts to an idle state.                              */
77333 } USB_CFG0_Reset_Enum;
77334 
77335 /* ===============================================  USB CFG0 Resume [10..10]  ================================================ */
77336 typedef enum {                                  /*!< USB_CFG0_Resume                                                           */
77337   USB_CFG0_Resume_END_RESUME           = 0,     /*!< END_RESUME : Cleared automatically 10-15 ms after being manually
77338                                                      set.                                                                      */
77339   USB_CFG0_Resume_RESUME               = 1,     /*!< RESUME : Set to force USB Controller to generate Resume signal
77340                                                      on the USB to cause remote wake-up from Suspend mode.                     */
77341 } USB_CFG0_Resume_Enum;
77342 
77343 /* ================================================  USB CFG0 Suspen [9..9]  ================================================= */
77344 typedef enum {                                  /*!< USB_CFG0_Suspen                                                           */
77345   USB_CFG0_Suspen_RESUMED              = 0,     /*!< RESUMED : Indicates that Suspend Mode exited.                             */
77346   USB_CFG0_Suspen_SUSPENDED            = 1,     /*!< SUSPENDED : Indicates that Suspend Mode entered.                          */
77347 } USB_CFG0_Suspen_Enum;
77348 
77349 /* =================================================  USB CFG0 Enabl [8..8]  ================================================= */
77350 typedef enum {                                  /*!< USB_CFG0_Enabl                                                            */
77351   USB_CFG0_Enabl_DISABLE_SUSPENDM      = 0,     /*!< DISABLE_SUSPENDM : Clear to disable SUSPENDM signal - UTM does
77352                                                      not go into its low-power mode.                                           */
77353   USB_CFG0_Enabl_ENABLE_SUSPENDM       = 1,     /*!< ENABLE_SUSPENDM : Set to enable the SUSPENDM signal to put the
77354                                                      UTM (and any other HW which uses the SUSPENDM signal) into
77355                                                      Suspend mode.                                                             */
77356 } USB_CFG0_Enabl_Enum;
77357 
77358 /* ================================================  USB CFG0 Update [7..7]  ================================================= */
77359 typedef enum {                                  /*!< USB_CFG0_Update                                                           */
77360   USB_CFG0_Update_NEW_ADDR_SET         = 0,     /*!< NEW_ADDR_SET : Indicates that the new address has taken effect.           */
77361   USB_CFG0_Update_NEW_ADDR_WRITTEN     = 1,     /*!< NEW_ADDR_WRITTEN : Indicates that a new function address has
77362                                                      been written to the FuncAddr field.                                       */
77363 } USB_CFG0_Update_Enum;
77364 
77365 /* =========================================================  CFG1  ========================================================== */
77366 /* =============================================  USB CFG1 EP5InIntEn [21..21]  ============================================== */
77367 typedef enum {                                  /*!< USB_CFG1_EP5InIntEn                                                       */
77368   USB_CFG1_EP5InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
77369   USB_CFG1_EP5InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
77370 } USB_CFG1_EP5InIntEn_Enum;
77371 
77372 /* =============================================  USB CFG1 EP4InIntEn [20..20]  ============================================== */
77373 typedef enum {                                  /*!< USB_CFG1_EP4InIntEn                                                       */
77374   USB_CFG1_EP4InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
77375   USB_CFG1_EP4InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
77376 } USB_CFG1_EP4InIntEn_Enum;
77377 
77378 /* =============================================  USB CFG1 EP3InIntEn [19..19]  ============================================== */
77379 typedef enum {                                  /*!< USB_CFG1_EP3InIntEn                                                       */
77380   USB_CFG1_EP3InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
77381   USB_CFG1_EP3InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
77382 } USB_CFG1_EP3InIntEn_Enum;
77383 
77384 /* =============================================  USB CFG1 EP2InIntEn [18..18]  ============================================== */
77385 typedef enum {                                  /*!< USB_CFG1_EP2InIntEn                                                       */
77386   USB_CFG1_EP2InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
77387   USB_CFG1_EP2InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
77388 } USB_CFG1_EP2InIntEn_Enum;
77389 
77390 /* =============================================  USB CFG1 EP1InIntEn [17..17]  ============================================== */
77391 typedef enum {                                  /*!< USB_CFG1_EP1InIntEn                                                       */
77392   USB_CFG1_EP1InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
77393   USB_CFG1_EP1InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
77394 } USB_CFG1_EP1InIntEn_Enum;
77395 
77396 /* =============================================  USB CFG1 EP0InIntEn [16..16]  ============================================== */
77397 typedef enum {                                  /*!< USB_CFG1_EP0InIntEn                                                       */
77398   USB_CFG1_EP0InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
77399   USB_CFG1_EP0InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
77400 } USB_CFG1_EP0InIntEn_Enum;
77401 
77402 /* =============================================  USB CFG1 EP5OutIntStat [5..5]  ============================================= */
77403 typedef enum {                                  /*!< USB_CFG1_EP5OutIntStat                                                    */
77404   USB_CFG1_EP5OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77405   USB_CFG1_EP5OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
77406 } USB_CFG1_EP5OutIntStat_Enum;
77407 
77408 /* =============================================  USB CFG1 EP4OutIntStat [4..4]  ============================================= */
77409 typedef enum {                                  /*!< USB_CFG1_EP4OutIntStat                                                    */
77410   USB_CFG1_EP4OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77411   USB_CFG1_EP4OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
77412 } USB_CFG1_EP4OutIntStat_Enum;
77413 
77414 /* =============================================  USB CFG1 EP3OutIntStat [3..3]  ============================================= */
77415 typedef enum {                                  /*!< USB_CFG1_EP3OutIntStat                                                    */
77416   USB_CFG1_EP3OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77417   USB_CFG1_EP3OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
77418 } USB_CFG1_EP3OutIntStat_Enum;
77419 
77420 /* =============================================  USB CFG1 EP2OutIntStat [2..2]  ============================================= */
77421 typedef enum {                                  /*!< USB_CFG1_EP2OutIntStat                                                    */
77422   USB_CFG1_EP2OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77423   USB_CFG1_EP2OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
77424 } USB_CFG1_EP2OutIntStat_Enum;
77425 
77426 /* =============================================  USB CFG1 EP1OutIntStat [1..1]  ============================================= */
77427 typedef enum {                                  /*!< USB_CFG1_EP1OutIntStat                                                    */
77428   USB_CFG1_EP1OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77429   USB_CFG1_EP1OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
77430 } USB_CFG1_EP1OutIntStat_Enum;
77431 
77432 /* =============================================  USB CFG1 EP0OutIntStat [0..0]  ============================================= */
77433 typedef enum {                                  /*!< USB_CFG1_EP0OutIntStat                                                    */
77434   USB_CFG1_EP0OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
77435   USB_CFG1_EP0OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
77436 } USB_CFG1_EP0OutIntStat_Enum;
77437 
77438 /* =========================================================  CFG2  ========================================================== */
77439 /* ================================================  USB CFG2 SOFE [27..27]  ================================================= */
77440 typedef enum {                                  /*!< USB_CFG2_SOFE                                                             */
77441   USB_CFG2_SOFE_DIS                    = 0,     /*!< DIS : SOF interrupt disable.                                              */
77442   USB_CFG2_SOFE_EN                     = 1,     /*!< EN : SOF interrupt enable.                                                */
77443 } USB_CFG2_SOFE_Enum;
77444 
77445 /* ===============================================  USB CFG2 ResetE [26..26]  ================================================ */
77446 typedef enum {                                  /*!< USB_CFG2_ResetE                                                           */
77447   USB_CFG2_ResetE_DIS                  = 0,     /*!< DIS : Reset detect interrupt disable.                                     */
77448   USB_CFG2_ResetE_EN                   = 1,     /*!< EN : Reset detect interrupt enable.                                       */
77449 } USB_CFG2_ResetE_Enum;
77450 
77451 /* ===============================================  USB CFG2 ResumeE [25..25]  =============================================== */
77452 typedef enum {                                  /*!< USB_CFG2_ResumeE                                                          */
77453   USB_CFG2_ResumeE_DIS                 = 0,     /*!< DIS : Resume interrupt disable.                                           */
77454   USB_CFG2_ResumeE_EN                  = 1,     /*!< EN : Resume interrupt enable.                                             */
77455 } USB_CFG2_ResumeE_Enum;
77456 
77457 /* ==============================================  USB CFG2 SuspendE [24..24]  =============================================== */
77458 typedef enum {                                  /*!< USB_CFG2_SuspendE                                                         */
77459   USB_CFG2_SuspendE_DIS                = 0,     /*!< DIS : Suspend interrupt disable.                                          */
77460   USB_CFG2_SuspendE_EN                 = 1,     /*!< EN : Suspend interrupt enable.                                            */
77461 } USB_CFG2_SuspendE_Enum;
77462 
77463 /* =================================================  USB CFG2 SOF [19..19]  ================================================= */
77464 typedef enum {                                  /*!< USB_CFG2_SOF                                                              */
77465   USB_CFG2_SOF_SOF_INACTIVE            = 0,     /*!< SOF_INACTIVE : SOF interrupt inactive.                                    */
77466   USB_CFG2_SOF_SOF_ACTIVE              = 1,     /*!< SOF_ACTIVE : SOF interrupt active.                                        */
77467 } USB_CFG2_SOF_Enum;
77468 
77469 /* ================================================  USB CFG2 Reset [18..18]  ================================================ */
77470 typedef enum {                                  /*!< USB_CFG2_Reset                                                            */
77471   USB_CFG2_Reset_RESET_INACTIVE        = 0,     /*!< RESET_INACTIVE : Reset Detect interrupt inactive.                         */
77472   USB_CFG2_Reset_RESET_ACTIVE          = 1,     /*!< RESET_ACTIVE : Reset Detect interrupt active.                             */
77473 } USB_CFG2_Reset_Enum;
77474 
77475 /* ===============================================  USB CFG2 Resume [17..17]  ================================================ */
77476 typedef enum {                                  /*!< USB_CFG2_Resume                                                           */
77477   USB_CFG2_Resume_RESUME_INACTIVE      = 0,     /*!< RESUME_INACTIVE : Resume interrupt inactive.                              */
77478   USB_CFG2_Resume_RESUME_ACTIVE        = 1,     /*!< RESUME_ACTIVE : Resume interrupt active.                                  */
77479 } USB_CFG2_Resume_Enum;
77480 
77481 /* ===============================================  USB CFG2 Suspend [16..16]  =============================================== */
77482 typedef enum {                                  /*!< USB_CFG2_Suspend                                                          */
77483   USB_CFG2_Suspend_SUSPEND_INACTIVE    = 0,     /*!< SUSPEND_INACTIVE : Suspend interrupt inactive.                            */
77484   USB_CFG2_Suspend_SUSPEND_ACTIVE      = 1,     /*!< SUSPEND_ACTIVE : Suspend interrupt active.                                */
77485 } USB_CFG2_Suspend_Enum;
77486 
77487 /* ==============================================  USB CFG2 EP5OutIntEn [5..5]  ============================================== */
77488 typedef enum {                                  /*!< USB_CFG2_EP5OutIntEn                                                      */
77489   USB_CFG2_EP5OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
77490   USB_CFG2_EP5OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
77491 } USB_CFG2_EP5OutIntEn_Enum;
77492 
77493 /* ==============================================  USB CFG2 EP4OutIntEn [4..4]  ============================================== */
77494 typedef enum {                                  /*!< USB_CFG2_EP4OutIntEn                                                      */
77495   USB_CFG2_EP4OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
77496   USB_CFG2_EP4OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
77497 } USB_CFG2_EP4OutIntEn_Enum;
77498 
77499 /* ==============================================  USB CFG2 EP3OutIntEn [3..3]  ============================================== */
77500 typedef enum {                                  /*!< USB_CFG2_EP3OutIntEn                                                      */
77501   USB_CFG2_EP3OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
77502   USB_CFG2_EP3OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
77503 } USB_CFG2_EP3OutIntEn_Enum;
77504 
77505 /* ==============================================  USB CFG2 EP2OutIntEn [2..2]  ============================================== */
77506 typedef enum {                                  /*!< USB_CFG2_EP2OutIntEn                                                      */
77507   USB_CFG2_EP2OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
77508   USB_CFG2_EP2OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
77509 } USB_CFG2_EP2OutIntEn_Enum;
77510 
77511 /* ==============================================  USB CFG2 EP1OutIntEn [1..1]  ============================================== */
77512 typedef enum {                                  /*!< USB_CFG2_EP1OutIntEn                                                      */
77513   USB_CFG2_EP1OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
77514   USB_CFG2_EP1OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
77515 } USB_CFG2_EP1OutIntEn_Enum;
77516 
77517 /* ==============================================  USB CFG2 EP0OutIntEn [0..0]  ============================================== */
77518 typedef enum {                                  /*!< USB_CFG2_EP0OutIntEn                                                      */
77519   USB_CFG2_EP0OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
77520   USB_CFG2_EP0OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
77521 } USB_CFG2_EP0OutIntEn_Enum;
77522 
77523 /* =========================================================  CFG3  ========================================================== */
77524 /* ===============================================  USB CFG3 ForceFS [29..29]  =============================================== */
77525 typedef enum {                                  /*!< USB_CFG3_ForceFS                                                          */
77526   USB_CFG3_ForceFS_FS_NOT_FORCED       = 0,     /*!< FS_NOT_FORCED : Do not force FS mode upon USB reset.                      */
77527   USB_CFG3_ForceFS_FS_FORCED           = 1,     /*!< FS_FORCED : Force FS mode upon USB reset.                                 */
77528 } USB_CFG3_ForceFS_Enum;
77529 
77530 /* ===============================================  USB CFG3 ForceHS [28..28]  =============================================== */
77531 typedef enum {                                  /*!< USB_CFG3_ForceHS                                                          */
77532   USB_CFG3_ForceHS_HS_NOT_FORCED       = 0,     /*!< HS_NOT_FORCED : Do not force HS mode upon USB reset.                      */
77533   USB_CFG3_ForceHS_HS_FORCED           = 1,     /*!< HS_FORCED : Force HS mode upon USB reset.                                 */
77534 } USB_CFG3_ForceHS_Enum;
77535 
77536 /* =============================================  USB CFG3 TestPacket [27..27]  ============================================== */
77537 typedef enum {                                  /*!< USB_CFG3_TestPacket                                                       */
77538   USB_CFG3_TestPacket_STOP_TPTM        = 0,     /*!< STOP_TPTM : Terminates Test Packet Test Mode.                             */
77539   USB_CFG3_TestPacket_START_TPTM       = 1,     /*!< START_TPTM : Initiates Test Packet Test Mode.                             */
77540 } USB_CFG3_TestPacket_Enum;
77541 
77542 /* ================================================  USB CFG3 TestK [26..26]  ================================================ */
77543 typedef enum {                                  /*!< USB_CFG3_TestK                                                            */
77544   USB_CFG3_TestK_STOP_TESTK            = 0,     /*!< STOP_TESTK : Terminates Test_K Test Mode.                                 */
77545   USB_CFG3_TestK_START_TESTK           = 1,     /*!< START_TESTK : Initiates Test_K Test Mode.                                 */
77546 } USB_CFG3_TestK_Enum;
77547 
77548 /* ================================================  USB CFG3 TestJ [25..25]  ================================================ */
77549 typedef enum {                                  /*!< USB_CFG3_TestJ                                                            */
77550   USB_CFG3_TestJ_STOP_TESTJ            = 0,     /*!< STOP_TESTJ : Terminates Test_J Test Mode.                                 */
77551   USB_CFG3_TestJ_START_TESTJ           = 1,     /*!< START_TESTJ : Initiates Test_J Test Mode.                                 */
77552 } USB_CFG3_TestJ_Enum;
77553 
77554 /* =============================================  USB CFG3 TestSE0NAK [24..24]  ============================================== */
77555 typedef enum {                                  /*!< USB_CFG3_TestSE0NAK                                                       */
77556   USB_CFG3_TestSE0NAK_STOP_TESTSE0NAK  = 0,     /*!< STOP_TESTSE0NAK : Terminates Test_SE0_NAK Test Mode.                      */
77557   USB_CFG3_TestSE0NAK_START_TESTSE0NAK = 1,     /*!< START_TESTSE0NAK : Initiates Test_SE0_NAK Test Mode.                      */
77558 } USB_CFG3_TestSE0NAK_Enum;
77559 
77560 /* ==============================================  USB CFG3 ENDPOINT [16..19]  =============================================== */
77561 typedef enum {                                  /*!< USB_CFG3_ENDPOINT                                                         */
77562   USB_CFG3_ENDPOINT_ENDPOINT0          = 0,     /*!< ENDPOINT0 : Endpoint 0 selected.                                          */
77563   USB_CFG3_ENDPOINT_ENDPOINT1          = 1,     /*!< ENDPOINT1 : Endpoint 1 selected.                                          */
77564   USB_CFG3_ENDPOINT_ENDPOINT2          = 2,     /*!< ENDPOINT2 : Endpoint 2 selected.                                          */
77565   USB_CFG3_ENDPOINT_ENDPOINT3          = 3,     /*!< ENDPOINT3 : Endpoint 3 selected.                                          */
77566   USB_CFG3_ENDPOINT_ENDPOINT4          = 4,     /*!< ENDPOINT4 : Endpoint 4 selected.                                          */
77567   USB_CFG3_ENDPOINT_ENDPOINT5          = 5,     /*!< ENDPOINT5 : Endpoint 5 selected.                                          */
77568 } USB_CFG3_ENDPOINT_Enum;
77569 
77570 /* =========================================================  IDX0  ========================================================== */
77571 /* ===============================================  USB IDX0 AutoSet [31..31]  =============================================== */
77572 typedef enum {                                  /*!< USB_IDX0_AutoSet                                                          */
77573   USB_IDX0_AutoSet_NO_AUTOSET          = 0,     /*!< NO_AUTOSET : InPktRdy field is not automatically set when MAXPAYLOAD
77574                                                      data size is loaded into the IN FIFO.                                     */
77575   USB_IDX0_AutoSet_AUTOSET             = 1,     /*!< AUTOSET : Applicable InPktRdy field is automatically set when
77576                                                      MAXPAYLOAD data size is loaded into the IN FIFO. If a packet
77577                                                      of less than the maximum packet size is loaded, InPktRdy
77578                                                      will have to be set manually. Note: Should not be set for
77579                                                      high-bandwidth Isochronous endpoints.                                     */
77580 } USB_IDX0_AutoSet_Enum;
77581 
77582 /* =================================================  USB IDX0 ISO [30..30]  ================================================= */
77583 typedef enum {                                  /*!< USB_IDX0_ISO                                                              */
77584   USB_IDX0_ISO_BULK_INT                = 0,     /*!< BULK_INT : Clear to enable the IN endpoint for Bulk/Interrupt
77585                                                      transfers.                                                                */
77586   USB_IDX0_ISO_ISO                     = 1,     /*!< ISO : Set to enable the IN endpoint for Isochronous transfers.            */
77587 } USB_IDX0_ISO_Enum;
77588 
77589 /* ================================================  USB IDX0 Mode [29..29]  ================================================= */
77590 typedef enum {                                  /*!< USB_IDX0_Mode                                                             */
77591   USB_IDX0_Mode_OUT                    = 0,     /*!< OUT : Clear to enable the OUT direction for endpoint.                     */
77592   USB_IDX0_Mode_IN                     = 1,     /*!< IN : Set to enable the IN direction for endpoint.                         */
77593 } USB_IDX0_Mode_Enum;
77594 
77595 /* =============================================  USB IDX0 FrcDataTog [27..27]  ============================================== */
77596 typedef enum {                                  /*!< USB_IDX0_FrcDataTog                                                       */
77597   USB_IDX0_FrcDataTog_NO_FORCE_TOGGLE  = 0,     /*!< NO_FORCE_TOGGLE : Keep cleared to not force data toggle.                  */
77598   USB_IDX0_FrcDataTog_FORCE_TOGGLE     = 1,     /*!< FORCE_TOGGLE : Set to force the endpoint's IN data toggle to
77599                                                      switch after each data packet is sent.                                    */
77600 } USB_IDX0_FrcDataTog_Enum;
77601 
77602 /* =============================================  USB IDX0 DPktBufDis [25..25]  ============================================== */
77603 typedef enum {                                  /*!< USB_IDX0_DPktBufDis                                                       */
77604   USB_IDX0_DPktBufDis_EN_DPB           = 0,     /*!< EN_DPB : Clear to allow Double Packet Buffering.                          */
77605   USB_IDX0_DPktBufDis_DIS_DPB          = 1,     /*!< DIS_DPB : Set to disable Double Packet Buffering regardless
77606                                                      of the End Point FIFO size and MAXPAYLOAD size relationship.              */
77607 } USB_IDX0_DPktBufDis_Enum;
77608 
77609 /* =======================================  USB IDX0 IncompTxServiceSetupEnd [23..23]  ======================================= */
77610 typedef enum {                                  /*!< USB_IDX0_IncompTxServiceSetupEnd                                          */
77611   USB_IDX0_IncompTxServiceSetupEnd_NO_PACKET_SPLIT = 0,/*!< NO_PACKET_SPLIT : Packet has NOT been split into multiple packets
77612                                                      for transmission.                                                         */
77613   USB_IDX0_IncompTxServiceSetupEnd_PACKET_SPLIT = 1,/*!< PACKET_SPLIT : A large packet has been split into 2 or 3 packets
77614                                                      for transmission but insufficient IN tokens have been received
77615                                                      to send all the parts.If CFG3_ENDPOINT = 0x0, this bit
77616                                                      serves as the ServiceSetupEnd field.                                      */
77617 } USB_IDX0_IncompTxServiceSetupEnd_Enum;
77618 
77619 /* =========================================================  IDX1  ========================================================== */
77620 /* ==============================================  USB IDX1 AutoClear [31..31]  ============================================== */
77621 typedef enum {                                  /*!< USB_IDX1_AutoClear                                                        */
77622   USB_IDX1_AutoClear_NO_AUTOCLR        = 0,     /*!< NO_AUTOCLR : OutPktRdy field will not be automatically cleared
77623                                                      when a packet of MAXPAYLOAD data size is unloaded from
77624                                                      the OUT FIFO.                                                             */
77625   USB_IDX1_AutoClear_AUTOCLR           = 1,     /*!< AUTOCLR : OutPktRdy field will be automatically cleared when
77626                                                      a packet of MAXPAYLOAD data size is unloaded from the OUT
77627                                                      FIFO. When packets of less than the maximum packet size
77628                                                      are unloaded, OutPktRdy must be cleared manually. Note:
77629                                                      Should not be set for high bandwidth Isochronous endpoints.               */
77630 } USB_IDX1_AutoClear_Enum;
77631 
77632 /* =================================================  USB IDX1 ISO [30..30]  ================================================= */
77633 typedef enum {                                  /*!< USB_IDX1_ISO                                                              */
77634   USB_IDX1_ISO_BULK_INT                = 0,     /*!< BULK_INT : Clear to enable the OUT endpoint for Bulk/Interrupt
77635                                                      transfers.                                                                */
77636   USB_IDX1_ISO_ISO                     = 1,     /*!< ISO : Set to enable the OUT endpoint for Isochronous transfers.           */
77637 } USB_IDX1_ISO_Enum;
77638 
77639 /* =============================================  USB IDX1 DPktBufDis [25..25]  ============================================== */
77640 typedef enum {                                  /*!< USB_IDX1_DPktBufDis                                                       */
77641   USB_IDX1_DPktBufDis_EN_DPB           = 0,     /*!< EN_DPB : Clear to allow Double Packet Buffering.                          */
77642   USB_IDX1_DPktBufDis_DIS_DPB          = 1,     /*!< DIS_DPB : Set to disable Double Packet Buffering regardless
77643                                                      of the End Point FIFO size and MAXPAYLOAD size relationship.              */
77644 } USB_IDX1_DPktBufDis_Enum;
77645 
77646 /* =========================================================  IDX2  ========================================================== */
77647 /* ========================================================  FIFOADD  ======================================================== */
77648 /* =========================================================  FIFO0  ========================================================= */
77649 /* =========================================================  FIFO1  ========================================================= */
77650 /* =========================================================  FIFO2  ========================================================= */
77651 /* =========================================================  FIFO3  ========================================================= */
77652 /* =========================================================  FIFO4  ========================================================= */
77653 /* =========================================================  FIFO5  ========================================================= */
77654 /* ========================================================  HWVERS  ========================================================= */
77655 /* =========================================================  INFO  ========================================================== */
77656 /* =======================================================  TIMEOUT1  ======================================================== */
77657 /* =======================================================  TIMEOUT2  ======================================================== */
77658 /* ========================================================  CLKCTRL  ======================================================== */
77659 /* ===========================================  USB CLKCTRL PHYREFCLKSEL [24..25]  =========================================== */
77660 typedef enum {                                  /*!< USB_CLKCTRL_PHYREFCLKSEL                                                  */
77661   USB_CLKCTRL_PHYREFCLKSEL_HFRC48      = 0,     /*!< HFRC48 : 48 MHz HFRC-based reference clock for Full-Speed Mode            */
77662   USB_CLKCTRL_PHYREFCLKSEL_HFRC248     = 1,     /*!< HFRC248 : 48 MHz HFRC2-based reference clock for High-Speed
77663                                                      Mode                                                                      */
77664   USB_CLKCTRL_PHYREFCLKSEL_HFRC24      = 2,     /*!< HFRC24 : 24 MHz HFRC-based reference clock for Full-Speed Mode            */
77665 } USB_CLKCTRL_PHYREFCLKSEL_Enum;
77666 
77667 /* =======================================================  SRAMCTRL  ======================================================== */
77668 /* ===============================================  USB SRAMCTRL RAWLM [7..8]  =============================================== */
77669 typedef enum {                                  /*!< USB_SRAMCTRL_RAWLM                                                        */
77670   USB_SRAMCTRL_RAWLM_INCDLY            = 3,     /*!< INCDLY : Increased margin adjustment, increased delay for enabling
77671                                                      write assist.                                                             */
77672   USB_SRAMCTRL_RAWLM_MBINCDLY          = 2,     /*!< MBINCDLY : Minimum boost level with increased delay for enabling
77673                                                      write assist.                                                             */
77674   USB_SRAMCTRL_RAWLM_IMNB              = 1,     /*!< IMNB : Increased margin adjustment with more negative boost.              */
77675   USB_SRAMCTRL_RAWLM_MMNB              = 0,     /*!< MMNB : Minimum margin adjustment with lowest negative boost
77676                                                      level.                                                                    */
77677 } USB_SRAMCTRL_RAWLM_Enum;
77678 
77679 /* ===================================================  UTMISTICKYSTATUS  ==================================================== */
77680 /* =======================================  USB UTMISTICKYSTATUS obsportstciky [0..1]  ======================================= */
77681 typedef enum {                                  /*!< USB_UTMISTICKYSTATUS_obsportstciky                                        */
77682   USB_UTMISTICKYSTATUS_obsportstciky_OBS3 = 3,  /*!< OBS3 : bit 1:HS BIST results, bit 0:FS BIST results                       */
77683   USB_UTMISTICKYSTATUS_obsportstciky_OBS2 = 2,  /*!< OBS2 : bit 1: ODT calibration state, bit 0: Current calibration
77684                                                      state                                                                     */
77685   USB_UTMISTICKYSTATUS_obsportstciky_OBS1 = 1,  /*!< OBS1 : bit 1: Rx squelch signal, bit 0: Rx datap                          */
77686   USB_UTMISTICKYSTATUS_obsportstciky_OBS0 = 0,  /*!< OBS0 : bit 1: PLL lock signal, bit 0: Host Disconnect                     */
77687 } USB_UTMISTICKYSTATUS_obsportstciky_Enum;
77688 
77689 /* ======================================================  OBSCLRSTAT  ======================================================= */
77690 /* =====================================================  DPDMPULLDOWN  ====================================================== */
77691 /* ======================================================  BCDETSTATUS  ====================================================== */
77692 /* ======================================================  BCDETCRTL1  ======================================================= */
77693 /* ===========================================  USB BCDETCRTL1 USBDCOMPREF [8..9]  =========================================== */
77694 typedef enum {                                  /*!< USB_BCDETCRTL1_USBDCOMPREF                                                */
77695   USB_BCDETCRTL1_USBDCOMPREF_1P25V     = 3,     /*!< 1P25V : 1.25V                                                             */
77696   USB_BCDETCRTL1_USBDCOMPREF_2P35      = 2,     /*!< 2P35 : 2.35V                                                              */
77697   USB_BCDETCRTL1_USBDCOMPREF_3P10V     = 1,     /*!< 3P10V : 3.10V                                                             */
77698   USB_BCDETCRTL1_USBDCOMPREF_1P65      = 0,     /*!< 1P65 : 1.65V (VCCIO/2)                                                    */
77699 } USB_BCDETCRTL1_USBDCOMPREF_Enum;
77700 
77701 /* ======================================================  BCDETCRTL2  ======================================================= */
77702 
77703 
77704 /* =========================================================================================================================== */
77705 /* ================                                           VCOMP                                           ================ */
77706 /* =========================================================================================================================== */
77707 
77708 /* ==========================================================  CFG  ========================================================== */
77709 /* ===============================================  VCOMP CFG LVLSEL [16..19]  =============================================== */
77710 typedef enum {                                  /*!< VCOMP_CFG_LVLSEL                                                          */
77711   VCOMP_CFG_LVLSEL_0P58V               = 0,     /*!< 0P58V : Set Reference input to 0.58 Volts.                                */
77712   VCOMP_CFG_LVLSEL_0P77V               = 1,     /*!< 0P77V : Set Reference input to 0.77 Volts.                                */
77713   VCOMP_CFG_LVLSEL_0P97V               = 2,     /*!< 0P97V : Set Reference input to 0.97 Volts.                                */
77714   VCOMP_CFG_LVLSEL_1P16V               = 3,     /*!< 1P16V : Set Reference input to 1.16 Volts.                                */
77715   VCOMP_CFG_LVLSEL_1P35V               = 4,     /*!< 1P35V : Set Reference input to 1.35 Volts.                                */
77716   VCOMP_CFG_LVLSEL_1P55V               = 5,     /*!< 1P55V : Set Reference input to 1.55 Volts.                                */
77717   VCOMP_CFG_LVLSEL_1P74V               = 6,     /*!< 1P74V : Set Reference input to 1.74 Volts.                                */
77718   VCOMP_CFG_LVLSEL_1P93V               = 7,     /*!< 1P93V : Set Reference input to 1.93 Volts.                                */
77719   VCOMP_CFG_LVLSEL_2P13V               = 8,     /*!< 2P13V : Set Reference input to 2.13 Volts.                                */
77720   VCOMP_CFG_LVLSEL_2P32V               = 9,     /*!< 2P32V : Set Reference input to 2.32 Volts.                                */
77721   VCOMP_CFG_LVLSEL_2P51V               = 10,    /*!< 2P51V : Set Reference input to 2.51 Volts.                                */
77722   VCOMP_CFG_LVLSEL_2P71V               = 11,    /*!< 2P71V : Set Reference input to 2.71 Volts.                                */
77723   VCOMP_CFG_LVLSEL_2P90V               = 12,    /*!< 2P90V : Set Reference input to 2.90 Volts.                                */
77724   VCOMP_CFG_LVLSEL_3P09V               = 13,    /*!< 3P09V : Set Reference input to 3.09 Volts.                                */
77725   VCOMP_CFG_LVLSEL_3P29V               = 14,    /*!< 3P29V : Set Reference input to 3.29 Volts.                                */
77726   VCOMP_CFG_LVLSEL_3P48V               = 15,    /*!< 3P48V : Set Reference input to 3.48 Volts.                                */
77727 } VCOMP_CFG_LVLSEL_Enum;
77728 
77729 /* =================================================  VCOMP CFG NSEL [8..9]  ================================================= */
77730 typedef enum {                                  /*!< VCOMP_CFG_NSEL                                                            */
77731   VCOMP_CFG_NSEL_VREFEXT1              = 0,     /*!< VREFEXT1 : Use external reference 1 for reference input.                  */
77732   VCOMP_CFG_NSEL_VREFEXT2              = 1,     /*!< VREFEXT2 : Use external reference 2 for reference input.                  */
77733   VCOMP_CFG_NSEL_VREFEXT3              = 2,     /*!< VREFEXT3 : Use external reference 3 for reference input.                  */
77734   VCOMP_CFG_NSEL_DAC                   = 3,     /*!< DAC : Use DAC output selected by LVLSEL for reference input.              */
77735 } VCOMP_CFG_NSEL_Enum;
77736 
77737 /* =================================================  VCOMP CFG PSEL [0..1]  ================================================= */
77738 typedef enum {                                  /*!< VCOMP_CFG_PSEL                                                            */
77739   VCOMP_CFG_PSEL_VDDADJ                = 0,     /*!< VDDADJ : Use VDDADJ for the positive input.                               */
77740   VCOMP_CFG_PSEL_VTEMP                 = 1,     /*!< VTEMP : Use the temperature sensor output for the positive input.
77741                                                      Note: If this channel is selected for PSEL, the bandap
77742                                                      circuit required for temperature comparisons will automatically
77743                                                      turn on. The bandgap circuit requires 11us to stabalize.                  */
77744   VCOMP_CFG_PSEL_VEXT1                 = 2,     /*!< VEXT1 : Use external voltage 0 for positive input.                        */
77745   VCOMP_CFG_PSEL_VEXT2                 = 3,     /*!< VEXT2 : Use external voltage 1 for positive input.                        */
77746 } VCOMP_CFG_PSEL_Enum;
77747 
77748 /* =========================================================  STAT  ========================================================== */
77749 /* ===============================================  VCOMP STAT PWDSTAT [1..1]  =============================================== */
77750 typedef enum {                                  /*!< VCOMP_STAT_PWDSTAT                                                        */
77751   VCOMP_STAT_PWDSTAT_POWERED_DOWN      = 1,     /*!< POWERED_DOWN : The voltage comparator is powered down.                    */
77752 } VCOMP_STAT_PWDSTAT_Enum;
77753 
77754 /* ===============================================  VCOMP STAT CMPOUT [0..0]  ================================================ */
77755 typedef enum {                                  /*!< VCOMP_STAT_CMPOUT                                                         */
77756   VCOMP_STAT_CMPOUT_VOUT_LOW           = 0,     /*!< VOUT_LOW : The negative input of the comparator is greater than
77757                                                      the positive input.                                                       */
77758   VCOMP_STAT_CMPOUT_VOUT_HIGH          = 1,     /*!< VOUT_HIGH : The positive input of the comparator is greater
77759                                                      than the negative input.                                                  */
77760 } VCOMP_STAT_CMPOUT_Enum;
77761 
77762 /* ========================================================  PWDKEY  ========================================================= */
77763 /* ==============================================  VCOMP PWDKEY PWDKEY [0..31]  ============================================== */
77764 typedef enum {                                  /*!< VCOMP_PWDKEY_PWDKEY                                                       */
77765   VCOMP_PWDKEY_PWDKEY_Key              = 55,    /*!< Key : Key value to unlock the register.                                   */
77766 } VCOMP_PWDKEY_PWDKEY_Enum;
77767 
77768 /* =========================================================  INTEN  ========================================================= */
77769 /* ========================================================  INTSTAT  ======================================================== */
77770 /* ========================================================  INTCLR  ========================================================= */
77771 /* ========================================================  INTSET  ========================================================= */
77772 
77773 
77774 /* =========================================================================================================================== */
77775 /* ================                                            WDT                                            ================ */
77776 /* =========================================================================================================================== */
77777 
77778 /* ==========================================================  CFG  ========================================================== */
77779 /* ================================================  WDT CFG CLKSEL [24..26]  ================================================ */
77780 typedef enum {                                  /*!< WDT_CFG_CLKSEL                                                            */
77781   WDT_CFG_CLKSEL_OFF                   = 0,     /*!< OFF : Low Power Mode. This setting disables the watch dog timer.          */
77782   WDT_CFG_CLKSEL_128HZ                 = 1,     /*!< 128HZ : 128 Hz LFRC clock.                                                */
77783   WDT_CFG_CLKSEL_16HZ                  = 2,     /*!< 16HZ : 16 Hz LFRC clock.                                                  */
77784   WDT_CFG_CLKSEL_1HZ                   = 3,     /*!< 1HZ : 1 Hz LFRC clock.                                                    */
77785   WDT_CFG_CLKSEL_1_16HZ                = 4,     /*!< 1_16HZ : 1/16th Hz LFRC clock.                                            */
77786 } WDT_CFG_CLKSEL_Enum;
77787 
77788 /* =========================================================  RSTRT  ========================================================= */
77789 /* ================================================  WDT RSTRT RSTRT [0..7]  ================================================= */
77790 typedef enum {                                  /*!< WDT_RSTRT_RSTRT                                                           */
77791   WDT_RSTRT_RSTRT_KEYVALUE             = 178,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
77792                                                      the WDT. This is a write only register.                                   */
77793 } WDT_RSTRT_RSTRT_Enum;
77794 
77795 /* =========================================================  LOCK  ========================================================== */
77796 /* =================================================  WDT LOCK LOCK [0..7]  ================================================== */
77797 typedef enum {                                  /*!< WDT_LOCK_LOCK                                                             */
77798   WDT_LOCK_LOCK_KEYVALUE               = 58,    /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
77799                                                      the WDT.                                                                  */
77800 } WDT_LOCK_LOCK_Enum;
77801 
77802 /* =========================================================  COUNT  ========================================================= */
77803 /* ========================================================  DSP0CFG  ======================================================== */
77804 /* =======================================================  DSP0RSTRT  ======================================================= */
77805 /* ============================================  WDT DSP0RSTRT DSP0RSTART [0..7]  ============================================ */
77806 typedef enum {                                  /*!< WDT_DSP0RSTRT_DSP0RSTART                                                  */
77807   WDT_DSP0RSTRT_DSP0RSTART_KEYVALUE    = 105,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
77808                                                      the WDT. This is a write only register.                                   */
77809 } WDT_DSP0RSTRT_DSP0RSTART_Enum;
77810 
77811 /* =======================================================  DSP0TLOCK  ======================================================= */
77812 /* =============================================  WDT DSP0TLOCK DSP0LOCK [0..7]  ============================================= */
77813 typedef enum {                                  /*!< WDT_DSP0TLOCK_DSP0LOCK                                                    */
77814   WDT_DSP0TLOCK_DSP0LOCK_KEYVALUE      = 167,   /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
77815                                                      the WDT.                                                                  */
77816 } WDT_DSP0TLOCK_DSP0LOCK_Enum;
77817 
77818 /* =======================================================  DSP0COUNT  ======================================================= */
77819 /* ========================================================  DSP1CFG  ======================================================== */
77820 /* =======================================================  DSP1RSTRT  ======================================================= */
77821 /* ============================================  WDT DSP1RSTRT DSP1RSTART [0..7]  ============================================ */
77822 typedef enum {                                  /*!< WDT_DSP1RSTRT_DSP1RSTART                                                  */
77823   WDT_DSP1RSTRT_DSP1RSTART_KEYVALUE    = 210,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
77824                                                      the WDT. This is a write only register.                                   */
77825 } WDT_DSP1RSTRT_DSP1RSTART_Enum;
77826 
77827 /* =======================================================  DSP1TLOCK  ======================================================= */
77828 /* =============================================  WDT DSP1TLOCK DSP1LOCK [0..7]  ============================================= */
77829 typedef enum {                                  /*!< WDT_DSP1TLOCK_DSP1LOCK                                                    */
77830   WDT_DSP1TLOCK_DSP1LOCK_KEYVALUE      = 78,    /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
77831                                                      the WDT.                                                                  */
77832 } WDT_DSP1TLOCK_DSP1LOCK_Enum;
77833 
77834 /* =======================================================  DSP1COUNT  ======================================================= */
77835 /* =======================================================  WDTIEREN  ======================================================== */
77836 /* ======================================================  WDTIERSTAT  ======================================================= */
77837 /* =======================================================  WDTIERCLR  ======================================================= */
77838 /* =======================================================  WDTIERSET  ======================================================= */
77839 /* =======================================================  DSP0IEREN  ======================================================= */
77840 /* ======================================================  DSP0IERSTAT  ====================================================== */
77841 /* ======================================================  DSP0IERCLR  ======================================================= */
77842 /* ======================================================  DSP0IERSET  ======================================================= */
77843 /* =======================================================  DSP1IEREN  ======================================================= */
77844 /* ======================================================  DSP1IERSTAT  ====================================================== */
77845 /* ======================================================  DSP1IERCLR  ======================================================= */
77846 /* ======================================================  DSP1IERSET  ======================================================= */
77847 
77848 /** @} */ /* End of group EnumValue_peripherals */
77849 
77850 
77851 #ifdef __cplusplus
77852 }
77853 #endif
77854 
77855 #endif /* APOLLO4B_H */
77856 
77857 
77858 /** @} */ /* End of group apollo4b */
77859 
77860 /** @} */ /* End of group Ambiq Micro */
77861