1 //***************************************************************************** 2 // 3 // am_mcu_apollo4p_info0.h 4 // 5 //***************************************************************************** 6 7 //***************************************************************************** 8 // 9 // Copyright (c) 2023, Ambiq Micro, Inc. 10 // All rights reserved. 11 // 12 // Redistribution and use in source and binary forms, with or without 13 // modification, are permitted provided that the following conditions are met: 14 // 15 // 1. Redistributions of source code must retain the above copyright notice, 16 // this list of conditions and the following disclaimer. 17 // 18 // 2. Redistributions in binary form must reproduce the above copyright 19 // notice, this list of conditions and the following disclaimer in the 20 // documentation and/or other materials provided with the distribution. 21 // 22 // 3. Neither the name of the copyright holder nor the names of its 23 // contributors may be used to endorse or promote products derived from this 24 // software without specific prior written permission. 25 // 26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 30 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 // POSSIBILITY OF SUCH DAMAGE. 37 // 38 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package. 39 // 40 //***************************************************************************** 41 42 #ifndef AM_REG_INFO0_H 43 #define AM_REG_INFO0_H 44 45 #define AM_REG_INFO0_BASEADDR 0x42000000 46 #define AM_REG_INFO0n(n) 0x42000000 47 48 #define AM_REG_INFO0_SIGNATURE0_O 0x00000000 49 #define AM_REG_INFO0_SIGNATURE0_ADDR 0x42000000 50 #define AM_REG_INFO0_SIGNATURE1_O 0x00000004 51 #define AM_REG_INFO0_SIGNATURE1_ADDR 0x42000004 52 #define AM_REG_INFO0_SIGNATURE2_O 0x00000008 53 #define AM_REG_INFO0_SIGNATURE2_ADDR 0x42000008 54 #define AM_REG_INFO0_SIGNATURE3_O 0x0000000c 55 #define AM_REG_INFO0_SIGNATURE3_ADDR 0x4200000c 56 #define AM_REG_INFO0_CUSTOMER_TRIM_O 0x00000014 57 #define AM_REG_INFO0_CUSTOMER_TRIM_ADDR 0x42000014 58 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_O 0x00000028 59 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_ADDR 0x42000028 60 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_O 0x0000002c 61 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_ADDR 0x4200002c 62 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG2_O 0x00000030 63 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG2_ADDR 0x42000030 64 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG3_O 0x00000034 65 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG3_ADDR 0x42000034 66 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG4_O 0x00000038 67 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG4_ADDR 0x42000038 68 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG5_O 0x0000003c 69 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG5_ADDR 0x4200003c 70 #define AM_REG_INFO0_SECURITY_VERSION_O 0x00000040 71 #define AM_REG_INFO0_SECURITY_VERSION_ADDR 0x42000040 72 #define AM_REG_INFO0_SECURITY_SRAM_RESV_O 0x00000044 73 #define AM_REG_INFO0_SECURITY_SRAM_RESV_ADDR 0x42000044 74 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_O 0x00000048 75 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_ADDR 0x42000048 76 #define AM_REG_INFO0_WIRED_TIMEOUT_O 0x00000054 77 #define AM_REG_INFO0_WIRED_TIMEOUT_ADDR 0x42000054 78 #define AM_REG_INFO0_SBR_SDCERT_ADDR_O 0x00000058 79 #define AM_REG_INFO0_SBR_SDCERT_ADDR_ADDR 0x42000058 80 #define AM_REG_INFO0_MAINPTR_O 0x00000060 81 #define AM_REG_INFO0_MAINPTR_ADDR 0x42000060 82 #define AM_REG_INFO0_CERTCHAINPTR_O 0x00000064 83 #define AM_REG_INFO0_CERTCHAINPTR_ADDR 0x42000064 84 85 // SIGNATURE0 - Word 0 (low word, bits 31:0) of the 128-bit INFO0 signature. 86 #define AM_REG_INFO0_SIGNATURE0_SIG0_S 0 87 #define AM_REG_INFO0_SIGNATURE0_SIG0_M 0xFFFFFFFF 88 #define AM_REG_INFO0_SIGNATURE0_SIG0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 89 #define AM_REG_INFO0_SIGNATURE0_SIG0_Pos 0 90 #define AM_REG_INFO0_SIGNATURE0_SIG0_Msk 0xFFFFFFFF 91 92 // SIGNATURE1 - Word 1 (bits 63:32) of the 128-bit INFO0 signature. 93 #define AM_REG_INFO0_SIGNATURE1_SIG1_S 0 94 #define AM_REG_INFO0_SIGNATURE1_SIG1_M 0xFFFFFFFF 95 #define AM_REG_INFO0_SIGNATURE1_SIG1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 96 #define AM_REG_INFO0_SIGNATURE1_SIG1_Pos 0 97 #define AM_REG_INFO0_SIGNATURE1_SIG1_Msk 0xFFFFFFFF 98 99 // SIGNATURE2 - Word 2 (bits 95:64) of the 128-bit INFO0 signature. 100 #define AM_REG_INFO0_SIGNATURE2_SIG2_S 0 101 #define AM_REG_INFO0_SIGNATURE2_SIG2_M 0xFFFFFFFF 102 #define AM_REG_INFO0_SIGNATURE2_SIG2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 103 #define AM_REG_INFO0_SIGNATURE2_SIG2_Pos 0 104 #define AM_REG_INFO0_SIGNATURE2_SIG2_Msk 0xFFFFFFFF 105 106 // SIGNATURE3 - Word 3 (high word, bits 127:96) of the 128-bit INFO0 signature. 107 #define AM_REG_INFO0_SIGNATURE3_SIG3_S 0 108 #define AM_REG_INFO0_SIGNATURE3_SIG3_M 0xFFFFFFFF 109 #define AM_REG_INFO0_SIGNATURE3_SIG3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 110 #define AM_REG_INFO0_SIGNATURE3_SIG3_Pos 0 111 #define AM_REG_INFO0_SIGNATURE3_SIG3_Msk 0xFFFFFFFF 112 113 // CUSTOMER_TRIM - Customer Programmable trim overrides. Bits in this register are loaded into hardware registers at reset. 114 #define AM_REG_INFO0_CUSTOMER_TRIM_ERR001_MUSTBE_0_S 0 115 #define AM_REG_INFO0_CUSTOMER_TRIM_ERR001_MUSTBE_0_M 0x00000001 116 #define AM_REG_INFO0_CUSTOMER_TRIM_ERR001_MUSTBE_0(n) (((uint32_t)(n) << 0) & 0x00000001) 117 #define AM_REG_INFO0_CUSTOMER_TRIM_ERR001_MUSTBE_0_Pos 0 118 #define AM_REG_INFO0_CUSTOMER_TRIM_ERR001_MUSTBE_0_Msk 0x00000001 119 120 // SECURITY_WIRED_IFC_CFG0 - This 32-bit word contains the interface configuration word0 for the UART wired update. This feature is not applicable to Apollo4 revA without pre-installed bootloader. 121 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_S 30 122 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_M 0xC0000000 123 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30(n) (((uint32_t)(n) << 30) & 0xC0000000) 124 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_Pos 30 125 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_Msk 0xC0000000 126 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_S 8 127 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_M 0x3FFFFF00 128 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE(n) (((uint32_t)(n) << 8) & 0x3FFFFF00) 129 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_Pos 8 130 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_Msk 0x3FFFFF00 131 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_S 6 132 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_M 0x000000C0 133 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN(n) (((uint32_t)(n) << 6) & 0x000000C0) 134 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_Pos 6 135 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_Msk 0x000000C0 136 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_S 5 137 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_M 0x00000020 138 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP(n) (((uint32_t)(n) << 5) & 0x00000020) 139 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_Pos 5 140 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_Msk 0x00000020 141 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_S 4 142 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_M 0x00000010 143 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN(n) (((uint32_t)(n) << 4) & 0x00000010) 144 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_Pos 4 145 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_Msk 0x00000010 146 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_S 3 147 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_M 0x00000008 148 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_PAR(n) (((uint32_t)(n) << 3) & 0x00000008) 149 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_Pos 3 150 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_Msk 0x00000008 151 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_S 2 152 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_M 0x00000004 153 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_CTS(n) (((uint32_t)(n) << 2) & 0x00000004) 154 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_Pos 2 155 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_Msk 0x00000004 156 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_S 1 157 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_M 0x00000002 158 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RTS(n) (((uint32_t)(n) << 1) & 0x00000002) 159 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_Pos 1 160 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_Msk 0x00000002 161 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_S 0 162 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_M 0x00000001 163 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0(n) (((uint32_t)(n) << 0) & 0x00000001) 164 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_Pos 0 165 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_Msk 0x00000001 166 167 // SECURITY_WIRED_IFC_CFG1 - This 32-bit word contains the interface configuration word1 for the UART wired update. This feature is not applicable to Apollo4 revA without pre-installed bootloader. 168 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_S 24 169 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_M 0xFF000000 170 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3(n) (((uint32_t)(n) << 24) & 0xFF000000) 171 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_Pos 24 172 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_Msk 0xFF000000 173 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_S 16 174 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_M 0x00FF0000 175 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 176 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_Pos 16 177 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_Msk 0x00FF0000 178 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_S 8 179 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_M 0x0000FF00 180 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 181 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_Pos 8 182 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_Msk 0x0000FF00 183 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_S 0 184 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_M 0x000000FF 185 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0(n) (((uint32_t)(n) << 0) & 0x000000FF) 186 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_Pos 0 187 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_Msk 0x000000FF 188 189 // SECURITY_WIRED_IFC_CFG2 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 0. This feature is not applicable to Apollo4 revA without pre-installed bootloader. 190 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_S 0 191 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_M 0xFFFFFFFF 192 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 193 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_Pos 0 194 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_Msk 0xFFFFFFFF 195 196 // SECURITY_WIRED_IFC_CFG3 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 1. This feature is not applicable to Apollo4 revA without pre-installed bootloader. 197 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_S 0 198 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_M 0xFFFFFFFF 199 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 200 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_Pos 0 201 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_Msk 0xFFFFFFFF 202 203 // SECURITY_WIRED_IFC_CFG4 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 2. This feature is not applicable to Apollo4 revA without pre-installed bootloader. 204 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_S 0 205 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_M 0xFFFFFFFF 206 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 207 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_Pos 0 208 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_Msk 0xFFFFFFFF 209 210 // SECURITY_WIRED_IFC_CFG5 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 3. This feature is not applicable to Apollo4 revA without pre-installed bootloader. 211 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_S 0 212 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_M 0xFFFFFFFF 213 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 214 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_Pos 0 215 #define AM_REG_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_Msk 0xFFFFFFFF 216 217 // SECURITY_VERSION - This 32-bit word contains the version ID used for revision control 218 #define AM_REG_INFO0_SECURITY_VERSION_VERSION_S 0 219 #define AM_REG_INFO0_SECURITY_VERSION_VERSION_M 0xFFFFFFFF 220 #define AM_REG_INFO0_SECURITY_VERSION_VERSION(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 221 #define AM_REG_INFO0_SECURITY_VERSION_VERSION_Pos 0 222 #define AM_REG_INFO0_SECURITY_VERSION_VERSION_Msk 0xFFFFFFFF 223 224 // SECURITY_SRAM_RESV - This 32-bit word indicates the amount of DTCM to keep reserved for application scratch space. This reserves the specified memory at the top end of DTCM memory address range. This memory is not disturbed by the Secure Boot Loader. This feature is not applicable to Apollo4 revA without pre-installed bootloader. 225 #define AM_REG_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_S 0 226 #define AM_REG_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_M 0x000FFFFF 227 #define AM_REG_INFO0_SECURITY_SRAM_RESV_SRAM_RESV(n) (((uint32_t)(n) << 0) & 0x000FFFFF) 228 #define AM_REG_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_Pos 0 229 #define AM_REG_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_Msk 0x000FFFFF 230 231 // SECURITY_RMAOVERRIDE - Enables Ambiq to have the ability to download Ambiq RMA. 232 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_S 3 233 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_M 0xFFFFFFF8 234 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO(n) (((uint32_t)(n) << 3) & 0xFFFFFFF8) 235 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_Pos 3 236 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_Msk 0xFFFFFFF8 237 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_S 0 238 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_M 0x00000007 239 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE(n) (((uint32_t)(n) << 0) & 0x00000007) 240 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_Pos 0 241 #define AM_REG_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_Msk 0x00000007 242 243 // WIRED_TIMEOUT - Holds the timeout value for wired transfers (in milliseconds). 244 #define AM_REG_INFO0_WIRED_TIMEOUT_TIMEOUT_S 0 245 #define AM_REG_INFO0_WIRED_TIMEOUT_TIMEOUT_M 0x0000FFFF 246 #define AM_REG_INFO0_WIRED_TIMEOUT_TIMEOUT(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 247 #define AM_REG_INFO0_WIRED_TIMEOUT_TIMEOUT_Pos 0 248 #define AM_REG_INFO0_WIRED_TIMEOUT_TIMEOUT_Msk 0x0000FFFF 249 250 // SBR_SDCERT_ADDR - Location where bootloader will find SD certificates. Customer configures this based on the memory layout. 251 #define AM_REG_INFO0_SBR_SDCERT_ADDR_ICV_S 0 252 #define AM_REG_INFO0_SBR_SDCERT_ADDR_ICV_M 0xFFFFFFFF 253 #define AM_REG_INFO0_SBR_SDCERT_ADDR_ICV(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 254 #define AM_REG_INFO0_SBR_SDCERT_ADDR_ICV_Pos 0 255 #define AM_REG_INFO0_SBR_SDCERT_ADDR_ICV_Msk 0xFFFFFFFF 256 257 // MAINPTR - Pointer to the main OEM image when Secure Boot is disabled. 258 #define AM_REG_INFO0_MAINPTR_ADDRESS_S 0 259 #define AM_REG_INFO0_MAINPTR_ADDRESS_M 0xFFFFFFFF 260 #define AM_REG_INFO0_MAINPTR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 261 #define AM_REG_INFO0_MAINPTR_ADDRESS_Pos 0 262 #define AM_REG_INFO0_MAINPTR_ADDRESS_Msk 0xFFFFFFFF 263 264 // CERTCHAINPTR - Pointer to OEM certificate chain when Secure Boot is enabled. 265 #define AM_REG_INFO0_CERTCHAINPTR_ADDRESS_S 0 266 #define AM_REG_INFO0_CERTCHAINPTR_ADDRESS_M 0xFFFFFFFF 267 #define AM_REG_INFO0_CERTCHAINPTR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 268 #define AM_REG_INFO0_CERTCHAINPTR_ADDRESS_Pos 0 269 #define AM_REG_INFO0_CERTCHAINPTR_ADDRESS_Msk 0xFFFFFFFF 270 271 #endif 272
