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28 
29 #ifndef __ALTERA_EPCQ_CONTROLLER_REGS_H__
30 #define __ALTERA_EPCQ_CONTROLLER_REGS_H__
31 
32 #include <io.h>
33 
34 /*
35  * EPCQ_RD_STATUS register offset
36  *
37  * The EPCQ_RD_STATUS register contains information from the read status
38  * register operation. A full description of the register can be found in the
39  * data sheet,
40  *
41  */
42 #define ALTERA_EPCQ_CONTROLLER_STATUS_REG                       (0x0)
43 
44 /*
45  * EPCQ_RD_STATUS register access macros
46  */
47 #define IOADDR_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
48     __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
49 
50 #define IORD_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
51     IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
52 
53 #define IOWR_ALTERA_EPCQ_CONTROLLER_STATUS(base, data) \
54     IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG, data)
55 
56 /*
57  * EPCQ_RD_STATUS register description macros
58  */
59 
60 /** Write in progress bit */
61 #define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_MASK                  (0x00000001)
62 #define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_AVAILABLE             (0x00000000)
63 #define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_BUSY                  (0x00000001)
64 /** When to time out a poll of the write in progress bit */
65 /* 0.7 sec time out */
66 #define ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE    		    700000
67 
68 /*
69  * EPCQ_RD_SID register offset
70  *
71  * The EPCQ_RD_SID register contains the information from the read silicon ID
72  * operation and can be used to determine what type of EPCS device we have.
73  * Only support in EPCS16 and EPCS64.
74  *
75  * This register is valid only if the device is an EPCS.
76  *
77  */
78 #define ALTERA_EPCQ_CONTROLLER_SID_REG                          (0x4)
79 
80 /*
81  * EPCQ_RD_SID register access macros
82  */
83 #define IOADDR_ALTERA_EPCQ_CONTROLLER_SID(base) \
84     __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
85 
86 #define IORD_ALTERA_EPCQ_CONTROLLER_SID(base) \
87     IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
88 
89 #define IOWR_ALTERA_EPCQ_CONTROLLER_SID(base, data) \
90     IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG, data)
91 
92 /*
93  * EPCQ_RD_SID register description macros
94  *
95  * Specific device values obtained from Table 14 of:
96  * "Serial Configuration (EPCS) Devices Datasheet"
97  */
98 #define ALTERA_EPCQ_CONTROLLER_SID_MASK                         (0x000000FF)
99 #define ALTERA_EPCQ_CONTROLLER_SID_EPCS16                       (0x00000014)
100 #define ALTERA_EPCQ_CONTROLLER_SID_EPCS64                       (0x00000016)
101 #define ALTERA_EPCQ_CONTROLLER_SID_EPCS128                      (0x00000018)
102 
103 /*
104  * EPCQ_RD_RDID register offset
105  *
106  * The EPCQ_RD_RDID register contains the information from the read memory
107  * capacity operation and can be used to determine what type of EPCQ device
108  * we have.
109  *
110  * This register is only valid if the device is an EPCQ.
111  *
112  */
113 #define ALTERA_EPCQ_CONTROLLER_RDID_REG                         (0x8)
114 
115 /*
116  * EPCQ_RD_RDID register access macros
117  */
118 #define IOADDR_ALTERA_EPCQ_CONTROLLER_RDID(base) \
119     __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
120 
121 #define IORD_ALTERA_EPCQ_CONTROLLER_RDID(base) \
122     IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
123 
124 #define IOWR_ALTERA_EPCQ_CONTROLLER_RDID(base, data) \
125     IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG, data)
126 
127 /*
128  * EPCQ_RD_RDID register description macros
129  *
130  * Specific device values obtained from Table 28 of:
131  *  "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
132  *  Devices Datasheet"
133  */
134 #define ALTERA_EPCQ_CONTROLLER_RDID_MASK                         (0x000000FF)
135 #define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ16                       (0x00000015)
136 #define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ32                       (0x00000016)
137 #define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ64                       (0x00000017)
138 #define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ128                      (0x00000018)
139 #define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ256                      (0x00000019)
140 #define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ512                      (0x00000020)
141 #define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ1024                     (0x00000021)
142 
143 /*
144  * EPCQ_MEM_OP register offset
145  *
146  * The EPCQ_MEM_OP register is used to do memory protect and erase operations
147  *
148  */
149 #define ALTERA_EPCQ_CONTROLLER_MEM_OP_REG                       (0xC)
150 
151 /*
152  * EPCQ_MEM_OP register access macros
153  */
154 #define IOADDR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
155     __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
156 
157 #define IORD_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
158     IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
159 
160 #define IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base, data) \
161     IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG, data)
162 
163 /*
164  * EPCQ_MEM_OP register description macros
165  */
166 #define ALTERA_EPCQ_CONTROLLER_MEM_OP_CMD_MASK                  (0x00000003)
167 #define ALTERA_EPCQ_CONTROLLER_MEM_OP_BULK_ERASE_CMD            (0x00000001)
168 #define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD          (0x00000002)
169 #define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD        (0x00000003)
170 
171 /** see datasheet for sector values */
172 #define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK         (0x00FFFF00)
173 
174 /*
175  * EPCQ_ISR register offset
176  *
177  * The EPCQ_ISR register is used to determine whether an invalid write or erase
178  * operation triggered an interrupt
179  *
180  */
181 #define ALTERA_EPCQ_CONTROLLER_ISR_REG                          (0x10)
182 
183 /*
184  * EPCQ_ISR register access macros
185  */
186 #define IOADDR_ALTERA_EPCQ_CONTROLLER_ISR(base) \
187     __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
188 
189 #define IORD_ALTERA_EPCQ_CONTROLLER_ISR(base) \
190     IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
191 
192 #define IOWR_ALTERA_EPCQ_CONTROLLER_ISR(base, data) \
193     IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG, data)
194 
195 /*
196  * EPCQ_ISR register description macros
197  */
198 #define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK           (0x00000001)
199 #define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE         (0x00000001)
200 
201 #define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK           (0x00000002)
202 #define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE         (0x00000002)
203 
204 
205 /*
206  * EPCQ_IMR register offset
207  *
208  * The EPCQ_IMR register is used to mask the invalid erase or the invalid write
209  * interrupts.
210  *
211  */
212 #define ALTERA_EPCQ_CONTROLLER_IMR_REG                          (0x14)
213 
214 /*
215  * EPCQ_IMR register access macros
216  */
217 #define IOADDR_ALTERA_EPCQ_CONTROLLER_IMR(base) \
218     __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
219 
220 #define IORD_ALTERA_EPCQ_CONTROLLER_IMR(base) \
221     IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
222 
223 #define IOWR_ALTERA_EPCQ_CONTROLLER_IMR(base, data) \
224     IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG, data)
225 
226 /*
227  * EPCQ_IMR register description macros
228  */
229 #define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_MASK           (0x00000001)
230 #define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED        (0x00000001)
231 
232 #define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_MASK           (0x00000002)
233 #define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED        (0x00000002)
234 
235 /*
236  * EPCQ_CHIP_SELECT register offset
237  *
238  * The EPCQ_CHIP_SELECT register is used to issue chip select
239  */
240 #define ALTERA_EPCQ_CHIP_SELECT_REG                          (0x18)
241 
242 /*
243  * EPCQ_CHIP_SELECT register access macros
244  */
245 #define IOADDR_ALTERA_EPCQ_CHIP_SELECT(base) \
246     __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CHIP_SELECT_REG)
247 
248 #define IOWR_ALTERA_EPCQ_CHIP_SELECT(base, data) \
249     IOWR_32DIRECT(base, ALTERA_EPCQ_CHIP_SELECT_REG, data)
250 
251 /*
252  * EPCQ_CHIP_SELECT register description macros
253  */
254 #define ALTERA_EPCQ_CHIP1_SELECT        (0x00000001)
255 #define ALTERA_EPCQ_CHIP2_SELECT        (0x00000002)
256 #define ALTERA_EPCQ_CHIP3_SELECT        (0x00000003)
257 
258 #endif /* __ALTERA_EPCQ_CONTROLLER_REGS_H__ */
259