1 /****************************************************************************** 2 * * 3 * License Agreement * 4 * * 5 * Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * 6 * All rights reserved. * 7 * * 8 * Permission is hereby granted, free of charge, to any person obtaining a * 9 * copy of this software and associated documentation files (the "Software"), * 10 * to deal in the Software without restriction, including without limitation * 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 12 * and/or sell copies of the Software, and to permit persons to whom the * 13 * Software is furnished to do so, subject to the following conditions: * 14 * * 15 * The above copyright notice and this permission notice shall be included in * 16 * all copies or substantial portions of the Software. * 17 * * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 24 * DEALINGS IN THE SOFTWARE. * 25 * * 26 ******************************************************************************/ 27 28 #ifndef ALT_MSGDMA_PREFETCHER_REGS_H_ 29 #define ALT_MSGDMA_PREFETCHER_REGS_H_ 30 31 #include "io.h" 32 33 /* 34 MSGDMA Prefetcher core is an additional micro core to existing MSGDMA core which 35 already consists of dispatcher, read master and write master micro core. Prefetcher 36 core provides functionality to fetch a series of descriptors from memory that 37 describes the required data transfers before pass them to dispatcher core for data 38 transfer execution. 39 */ 40 41 42 /* 43 * Component : MSGDMA PREFETCHER 44 * 45 */ 46 #define ALT_MSGDMA_PREFETCHER_CONTROL_OFST 0x00 47 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST 0x04 48 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST 0x08 49 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST 0x0C 50 #define ALT_MSGDMA_PREFETCHER_STATUS_OFST 0x10 51 52 /* 53 * New MSGDMA PREFETCHER Descriptor fields. These are not prefetcher registers 54 * they are in the prefetcher descriptor structs 55 */ 56 /* The mask used to set the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW value. */ 57 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK (1 << 30) 58 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW value. */ 59 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK 0xBFFFFFFF 60 /* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW field. */ 61 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_BIT_OFFSET 30 62 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN field value from a register. */ 63 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_GET(value) (((value) & 0x40000000) >> 30) 64 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value suitable for setting the register. */ 65 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET(value) (((value) << 30) & 0x40000000) 66 67 /* 68 * Register : control 69 * 70 * The control register has two defined bits. 71 * 72 * DESC_POLL_EN and RUN . 73 * 74 * Detailed description available in their individual bitfields 75 * 76 * Register Layout 77 * 78 * Bits | Access | Reset | Description 79 * :-------|:-------|:------|:------------ 80 * [0] | R/W | 0x0 | RUN 81 * [1] | R/W | 0x0 | DESC_POLL_EN 82 * [2] | R/W1S | 0x0 | RESET_PREFETCHER 83 * [3] | R/W | 0x0 | GLOBAL_INTR_EN_MASK 84 * [4] | R/W | 0x0 | PARK_MODE 85 * [31:5] | R | 0x0 | RESERVED 86 * 87 */ 88 89 /* bits making up the "control" register */ 90 91 /* the RUN bit field in the control register */ 92 /* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ 93 #define ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET_MASK 0x1 94 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ 95 #define ALT_MSGDMA_PREFETCHER_CTRL_RUN_CLR_MASK 0xFFFFFFFE 96 /* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ 97 #define ALT_MSGDMA_PREFETCHER_CTRL_RUN_BIT_OFFSET 0 98 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ 99 #define ALT_MSGDMA_PREFETCHER_CTRL_RUN_GET(value) (((value) & 0x00000001) >> 0) 100 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ 101 #define ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET(value) (((value) << 0) & 0x00000001) 102 103 /* the DESC_POLL_EN bit field in the control register */ 104 /* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value. */ 105 #define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_MASK 0x2 106 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value. */ 107 #define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_CLR_MASK 0xFFFFFFFD 108 /* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field. */ 109 #define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_BIT_OFFSET 1 110 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN field value from a register. */ 111 #define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_GET(value) (((value) & 0x00000002) >> 1) 112 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value suitable for setting the register. */ 113 #define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_SET(value) (((value) << 1) & 0x00000002) 114 115 /* the RESET_PREFETCHER bit field in the control register */ 116 /* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_RESET register field value. */ 117 #define ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK 0x4 118 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ 119 #define ALT_MSGDMA_PREFETCHER_CTRL_RESET_CLR_MASK 0xFFFFFFFB 120 /* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ 121 #define ALT_MSGDMA_PREFETCHER_CTRL_RESET_BIT_OFFSET 2 122 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ 123 #define ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(value) (((value) & 0x00000004) >> 2) 124 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ 125 #define ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET(value) (((value) << 2) & 0x00000004) 126 127 /* the GLOBAL_INTR_EN_MASK bit field in the control register */ 128 /* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_MASK register field value. */ 129 #define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK 0x8 130 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ 131 #define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK 0xFFFFFFF7 132 /* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ 133 #define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_BIT_OFFSET 3 134 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ 135 #define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_GET(value) (((value) & 0x00000008) >> 3) 136 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ 137 #define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET(value) (((value) << 3) & 0x00000008) 138 139 /* the PARK_MODE bit field in the control register */ 140 /* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE register field value. */ 141 #define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET_MASK 0x10 142 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ 143 #define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_CLR_MASK 0xFFFFFFEF 144 /* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */ 145 #define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_BIT_OFFSET 4 146 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ 147 #define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_GET(value) (((value) & 0x00000010) >> 4) 148 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ 149 #define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET(value) (((value) << 4) & 0x00000010) 150 151 /* 152 * Registers : Next Descriptor Pointer Low/High 153 * 154 * The register has no bit fields, the 64 bits represent an address. 155 * 156 * Register Layout 157 * 158 * Bits | Access | Reset | Description 159 * :-------|:-------|:------|:------------ 160 * [31:0] | R/W | 0x0 | NEXT_PTR_ADDR_LOW 161 * [63:32]| R/W | 0x0 | NEXT_PTR_ADDR_HIGH 162 * 163 */ 164 165 /* bits making up the "Next Descriptor Pointer " register */ 166 167 /* the NEXT_PTR_ADDR_LOW bit field in the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW register */ 168 /* The mask used to set the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_REG register field value. */ 169 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_SET_MASK 0xFFFFFFFF 170 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value. */ 171 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_CLR_MASK 0x0 172 /* The bit offset of the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field. */ 173 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_BIT_OFFSET 0 174 /* Extracts the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG field value from a register. */ 175 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_GET(value) (((value) & 0xFFFFFFFF) >> 0) 176 /* Produces a ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value suitable for setting the register. */ 177 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_SET(value) (((value) << 0) & 0xFFFFFFFF) 178 179 /* the NEXT_PTR_ADDR_HIGH bit field in the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH register */ 180 /* The mask used to set the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_REG register field value. */ 181 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_SET_MASK 0xFFFFFFFF 182 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value. */ 183 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_CLR_MASK 0x0 184 /* The bit offset of the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field. */ 185 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_BIT_OFFSET 0 186 /* Extracts the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG field value from a register. */ 187 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_GET(value) (((value) & 0xFFFFFFFF) >> 0) 188 /* Produces a ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value suitable for setting the register. */ 189 #define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_SET(value) (((value) << 0) & 0xFFFFFFFF) 190 191 192 /* 193 * Register : Descriptor Polling Frequency 194 * 195 * The Descriptor Polling Frequency register has one defined bit field. 196 * 197 * POLL_FREQ 198 * 199 * Detailed description available in their individual bitfields 200 * 201 * Register Layout 202 * 203 * Bits | Access | Reset | Description 204 * :--------|:-------|:------|:------------ 205 * [15:0] | R/W | 0x0 | POLL_FREQ 206 * [31:16] | R | 0x0 | RESERVED 207 * 208 */ 209 210 /* bits making up the "DESC_POLL_FREQ" register */ 211 212 /* the POLL_FREQ bit field in the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register */ 213 /* The mask used to set the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field value. */ 214 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_SET_MASK 0xFFFF 215 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */ 216 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_CLR_MASK 0xFFFF0000 217 /* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field. */ 218 #define ALT_MSGDMA_PREFETCHER_CTRL_RUN_BIT_OFFSET 0 219 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ 220 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_GET(value) (((value) & 0x0000FFFF) >> 0) 221 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ 222 #define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_SET(value) (((value) << 0) & 0x0000FFFF) 223 224 225 /* 226 * Register : Status 227 * 228 * The Status register has one defined bit field. 229 * 230 * IRQ 231 * 232 * Detailed description available in their individual bitfields 233 * 234 * Register Layout 235 * 236 * Bits | Access | Reset | Description 237 * :--------|:-------|:------|:------------ 238 * [0] | R/W1C | 0x0 | IRQ 239 * [31:1] | R | 0x0 | RESERVED 240 * 241 */ 242 243 /* bits making up the "STATUS" register */ 244 245 /* the IRQ bit field in the ALT_MSGDMA_PREFETCHER_STATUS register */ 246 /* The mask used to set the ALT_MSGDMA_PREFETCHER_STATUS_IRQ register field value. */ 247 #define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET_MASK 0x1 248 /* The mask used to clear the ALT_MSGDMA_PREFETCHER_STATUS_IRQ register field value. */ 249 #define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_CLR_MASK 0xFFFFFFFE 250 /* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field. */ 251 #define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_BIT_OFFSET 0 252 /* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */ 253 #define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_GET(value) (((value) & 0x00000001) >> 0) 254 /* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */ 255 #define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET(value) (((value) << 0) & 0x00000001) 256 257 258 259 /*****************************************************************/ 260 /*** READ/WRITE macros for the MSGDMA PREFETCHER registers ***/ 261 /*****************************************************************/ 262 /* ALT_MSGDMA_PREFETCHER_CONTROL_REG */ 263 #define IORD_ALT_MSGDMA_PREFETCHER_CONTROL(base) \ 264 IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_CONTROL_OFST) 265 #define IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(base, data) \ 266 IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_CONTROL_OFST, data) 267 /* ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_REG */ 268 #define IORD_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(base) \ 269 IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST) 270 #define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(base, data) \ 271 IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST, data) 272 /* ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_REG */ 273 #define IORD_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(base) \ 274 IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST) 275 #define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(base, data) \ 276 IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST, data) 277 /* ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ_REG */ 278 #define IORD_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(base) \ 279 IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST) 280 #define IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(base, data) \ 281 IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST, data) 282 /* ALT_MSGDMA_PREFETCHER_STATUS_REG */ 283 #define IORD_ALT_MSGDMA_PREFETCHER_STATUS(base) \ 284 IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_STATUS_OFST) 285 #define IOWR_ALT_MSGDMA_PREFETCHER_STATUS(base, data) \ 286 IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_STATUS_OFST, data) 287 288 #endif /*ALT_MSGDMA_PREFETCHER_REGS_H_*/ 289
