1 /****************************************************************************** 2 * * 3 * License Agreement * 4 * * 5 * Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * 6 * All rights reserved. * 7 * * 8 * Permission is hereby granted, free of charge, to any person obtaining a * 9 * copy of this software and associated documentation files (the "Software"), * 10 * to deal in the Software without restriction, including without limitation * 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 12 * and/or sell copies of the Software, and to permit persons to whom the * 13 * Software is furnished to do so, subject to the following conditions: * 14 * * 15 * The above copyright notice and this permission notice shall be included in * 16 * all copies or substantial portions of the Software. * 17 * * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 24 * DEALINGS IN THE SOFTWARE. * 25 * * 26 ******************************************************************************/ 27 28 #ifndef ALTERA_MSGDMA_DESCRIPTOR_REGS_H_ 29 #define ALTERA_MSGDMA_DESCRIPTOR_REGS_H_ 30 31 #include "io.h" 32 33 /* 34 Descriptor formats: 35 36 Standard Format: 37 38 Offset | 3 2 1 0 39 ------------------------------------------------------------------------------ 40 0x0 | Read Address[31..0] 41 0x4 | Write Address[31..0] 42 0x8 | Length[31..0] 43 0xC | Control[31..0] 44 45 Extended Format: 46 47 Offset| 3 2 1 0 48 ------------------------------------------------------------------------------ 49 0x0 | Read Address[31..0] 50 0x4 | Write Address[31..0] 51 0x8 | Length[31..0] 52 0xC |Write Burst Count[7..0] | Read Burst Count[7..0] | Sequence Number[15..0] 53 0x10 | Write Stride[15..0] | Read Stride[15..0] 54 0x14 | Read Address[63..32] 55 0x18 | Write Address[63..32] 56 0x1C | Control[31..0] 57 58 Note: The control register moves from offset 0xC to 0x1C depending on the 59 format used 60 61 */ 62 63 64 65 66 #define ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_REG 0x0 67 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_REG 0x4 68 #define ALTERA_MSGDMA_DESCRIPTOR_LENGTH_REG 0x8 69 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD_REG 0xC 70 #define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_REG 0xC 71 #define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_REG 0xE 72 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_REG 0xF 73 #define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_REG 0x10 74 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_REG 0x12 75 #define ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH_REG 0x14 76 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH_REG 0x18 77 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED_REG 0x1C 78 79 80 /* masks and offsets for the sequence number and programmable burst counts */ 81 #define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_MASK 0xFFFF 82 #define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_OFFSET 0 83 #define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_COUNT_MASK 0x00FF0000 84 #define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_COUNT_OFFSET 16 85 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_COUNT_MASK 0xFF000000 86 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_COUNT_OFFSET 24 87 88 89 /* masks and offsets for the read and write strides */ 90 #define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_MASK 0xFFFF 91 #define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_OFFSET 0 92 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_MASK 0xFFFF0000 93 #define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_OFFSET 16 94 95 96 /* masks and offsets for the bits in the descriptor control field */ 97 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSMIT_CHANNEL_MASK 0xFF 98 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSMIT_CHANNEL_OFFSET 0 99 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK (1 << 8) 100 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_OFFSET 8 101 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK (1 << 9) 102 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_OFFSET 9 103 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_READS_MASK (1 << 10) 104 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_READS_OFFSET 10 105 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_WRITES_MASK (1 << 11) 106 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_WRITES_OFFSET 11 107 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_MASK (1 << 12) 108 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_OFFSET 12 109 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK (1 << 14) 110 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_OFFSET 14 111 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_TERMINATION_IRQ_MASK (1 << 15) 112 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_TERMINATION_IRQ_OFFSET 15 113 /* the read master will use this as the transmit error, the dispatcher will use 114 this to generate an interrupt if any of the error bits are asserted by the 115 write master */ 116 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_MASK (0xFF << 16) 117 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_OFFSET 16 118 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK (1 << 24) 119 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_OFFSET 24 120 /* at a minimum you always have to write '1' to this bit as it commits the 121 descriptor to the dispatcher */ 122 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK (1 << 31) 123 #define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_OFFSET 31 124 125 /* Each register is byte lane accessible so the some of the values that are 126 * less than 32 bits wide are written to according to the field width. 127 */ 128 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(base, data) \ 129 IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_REG, data) 130 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(base, data) \ 131 IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_REG, data) 132 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(base, data) \ 133 IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_LENGTH_REG, data) 134 /* this pushes the descriptor into the read/write FIFOs when standard descriptors 135 are used */ 136 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(base, data) \ 137 IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD_REG, data) 138 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER(base, data) \ 139 IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_REG, data) 140 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST(base, data) \ 141 IOWR_8DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_REG, data) 142 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST(base, data) \ 143 IOWR_8DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_REG, data) 144 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE(base, data) \ 145 IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_REG, data) 146 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE(base, data) \ 147 IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_REG, data) 148 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(base, data) \ 149 IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH_REG, data) 150 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH(base, data) \ 151 IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH_REG, data) 152 /* this pushes the descriptor into the read/write FIFOs when the extended 153 descriptors are used */ 154 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED(base, data) \ 155 IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED_REG, data) 156 157 158 159 #endif /*ALTERA_MSGDMA_ALTERA_MSGDMA_DESCRIPTOR_REGS_H_*/ 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