1 /****************************************************************************** 2 * * 3 * License Agreement * 4 * * 5 * Copyright (c) 2014 Altera Corporation, San Jose, California, USA. * 6 * All rights reserved. * 7 * * 8 * Permission is hereby granted, free of charge, to any person obtaining a * 9 * copy of this software and associated documentation files (the "Software"), * 10 * to deal in the Software without restriction, including without limitation * 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 12 * and/or sell copies of the Software, and to permit persons to whom the * 13 * Software is furnished to do so, subject to the following conditions: * 14 * * 15 * The above copyright notice and this permission notice shall be included in * 16 * all copies or substantial portions of the Software. * 17 * * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 24 * DEALINGS IN THE SOFTWARE. * 25 * * 26 ******************************************************************************/ 27 28 #ifndef ALTERA_MSGDMA_CSR_REGS_H_ 29 #define ALTERA_MSGDMA_CSR_REGS_H_ 30 31 #include "io.h" 32 /* 33 Enhanced features off: 34 35 Bytes Access Type Description 36 ----- ----------- ----------- 37 0-3 R/Clr Status(1) 38 4-7 R/W Control(2) 39 8-12 R Descriptor Fill Level(write fill level[15:0], read 40 fill level[15:0]) 41 13-15 R Response Fill Level[15:0] 42 16-31 N/A <Reserved> 43 44 45 Enhanced features on: 46 47 Bytes Access Type Description 48 ----- ----------- ----------- 49 0-3 R/Clr Status(1) 50 4-7 R/W Control(2) 51 8-12 R Descriptor Fill Level (write fill level[15:0], read 52 fill level[15:0]) 53 13-15 R Response Fill Level[15:0] 54 16-20 R Sequence Number (write sequence number[15:0], read 55 sequence number[15:0]) 56 21-31 N/A <Reserved> 57 58 (1) Writing a '1' to the interrupt bit of the status register clears the 59 interrupt bit (when applicable), all other bits are unaffected by writes. 60 (2) Writing to the software reset bit will clear the entire register 61 (as well as all the registers for the entire msgdma). 62 63 Status Register: 64 65 Bits Description 66 ---- ----------- 67 0 Busy 68 1 Descriptor Buffer Empty 69 2 Descriptor Buffer Full 70 3 Response Buffer Empty 71 4 Response Buffer Full 72 5 Stop State 73 6 Reset State 74 7 Stopped on Error 75 8 Stopped on Early Termination 76 9 IRQ 77 10-31 <Reserved> 78 79 Control Register: 80 81 Bits Description 82 ---- ----------- 83 0 Stop (will also be set if a stop on error/early termination 84 condition occurs) 85 1 Software Reset 86 2 Stop on Error 87 3 Stop on Early Termination 88 4 Global Interrupt Enable Mask 89 5 Stop dispatcher (stops the dispatcher from issuing more read/write 90 commands) 91 6-31 <Reserved> 92 */ 93 94 95 96 #define ALTERA_MSGDMA_CSR_STATUS_REG 0x0 97 #define ALTERA_MSGDMA_CSR_CONTROL_REG 0x4 98 #define ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG 0x8 99 #define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG 0xC 100 /* this register only exists when the enhanced features are enabled */ 101 #define ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG 0x10 102 103 104 /* masks for the status register bits */ 105 #define ALTERA_MSGDMA_CSR_BUSY_MASK 1 106 #define ALTERA_MSGDMA_CSR_BUSY_OFFSET 0 107 #define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_MASK (1 << 1) 108 #define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_OFFSET 1 109 #define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK (1 << 2) 110 #define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_OFFSET 2 111 #define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_MASK (1 << 3) 112 #define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_OFFSET 3 113 #define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_MASK (1 << 4) 114 #define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_OFFSET 4 115 #define ALTERA_MSGDMA_CSR_STOP_STATE_MASK (1 << 5) 116 #define ALTERA_MSGDMA_CSR_STOP_STATE_OFFSET 5 117 #define ALTERA_MSGDMA_CSR_RESET_STATE_MASK (1 << 6) 118 #define ALTERA_MSGDMA_CSR_RESET_STATE_OFFSET 6 119 #define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK (1 << 7) 120 #define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_OFFSET 7 121 #define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK (1 << 8) 122 #define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_OFFSET 8 123 #define ALTERA_MSGDMA_CSR_IRQ_SET_MASK (1 << 9) 124 #define ALTERA_MSGDMA_CSR_IRQ_SET_OFFSET 9 125 126 /* masks for the control register bits */ 127 #define ALTERA_MSGDMA_CSR_STOP_MASK 1 128 #define ALTERA_MSGDMA_CSR_STOP_OFFSET 0 129 #define ALTERA_MSGDMA_CSR_RESET_MASK (1 << 1) 130 #define ALTERA_MSGDMA_CSR_RESET_OFFSET 1 131 #define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK (1 << 2) 132 #define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_OFFSET 2 133 #define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_MASK (1 << 3) 134 #define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_OFFSET 3 135 #define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK (1 << 4) 136 #define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_OFFSET 4 137 #define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK (1 << 5) 138 #define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_OFFSET 5 139 140 /* masks for the FIFO fill levels and sequence number */ 141 #define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK 0xFFFF 142 #define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET 0 143 #define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK 0xFFFF0000 144 #define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET 16 145 #define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_MASK 0xFFFF 146 #define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_OFFSET 0 147 #define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_MASK 0xFFFF 148 #define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_OFFSET 0 149 #define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_MASK 0xFFFF0000 150 #define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_OFFSET 16 151 152 153 /* read/write macros for each 32 bit register of the CSR port */ 154 #define IOWR_ALTERA_MSGDMA_CSR_STATUS(base, data) \ 155 IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG, data) 156 #define IOWR_ALTERA_MSGDMA_CSR_CONTROL(base, data) \ 157 IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG, data) 158 #define IORD_ALTERA_MSGDMA_CSR_STATUS(base) \ 159 IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG) 160 #define IORD_ALTERA_MSGDMA_CSR_CONTROL(base) \ 161 IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG) 162 #define IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(base) \ 163 IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG) 164 #define IORD_ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL(base) \ 165 IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG) 166 #define IORD_ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER(base) \ 167 IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG) 168 169 170 171 #endif /*ALTERA_MSGDMA_ALTERA_MSGDMA_CSR_REGS_H_*/ 172
