1 /******************************************************************************
2 *                                                                             *
3 * License Agreement                                                           *
4 *                                                                             *
5 * Copyright (c) 2016 Altera Corporation, San Jose, California, USA.           *
6 * All rights reserved.                                                        *
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8 * Permission is hereby granted, free of charge, to any person obtaining a     *
9 * copy of this software and associated documentation files (the "Software"),  *
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12 * and/or sell copies of the Software, and to permit persons to whom the       *
13 * Software is furnished to do so, subject to the following conditions:        *
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24 * DEALINGS IN THE SOFTWARE.                                                   *
25 *                                                                             *
26 *                                                                             *
27 ******************************************************************************/
28 
29 #ifndef __ALT_AVALON_I2C_REGS_H__
30 #define __ALT_AVALON_I2C_REGS_H__
31 
32 #include <io.h>
33 
34 #define IORMW(base, reg, data, mask)                           IOWR(base,reg,(IORD(base,reg) & (~mask)) | (data & mask))
35 
36 #define ALT_AVALON_I2C_TFR_CMD_REG                          0
37 #define IOADDR_ALT_AVALON_I2C_TFR_CMD(base)                 __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_TFR_CMD_REG)
38 #define IORD_ALT_AVALON_I2C_TFR_CMD(base)                   IORD(base, ALT_AVALON_I2C_TFR_CMD_REG)
39 #define IOWR_ALT_AVALON_I2C_TFR_CMD(base, data)             IOWR(base, ALT_AVALON_I2C_TFR_CMD_REG, data)
40 #define ALT_AVALON_I2C_TFR_CMD_STA_OFST                     (9)
41 #define ALT_AVALON_I2C_TFR_CMD_STA_MSK                      (1 << ALT_AVALON_I2C_TFR_CMD_STA_OFST)
42 #define ALT_AVALON_I2C_TFR_CMD_STO_OFST                     (8)
43 #define ALT_AVALON_I2C_TFR_CMD_STO_MSK                      (1 << ALT_AVALON_I2C_TFR_CMD_STO_OFST)
44 #define ALT_AVALON_I2C_TFR_CMD_AD_OFST                      (1)
45 #define ALT_AVALON_I2C_TFR_CMD_AD_MSK                       (0x7f << ALT_AVALON_I2C_TFR_CMD_AD_OFST)
46 #define ALT_AVALON_I2C_TFR_CMD_RW_D_OFST                    (0)
47 #define ALT_AVALON_I2C_TFR_CMD_RW_D_MSK                     (1 << ALT_AVALON_I2C_TFR_CMD_RW_D_OFST)
48 #define ALT_AVALON_I2C_TFR_CMD_ALL_BITS_MSK                 (0x3ff)
49 
50 #define ALT_AVALON_I2C_RX_DATA_REG                          1
51 #define IOADDR_ALT_AVALON_I2C_RX_DATA(base)                 __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_RX_DATA_REG)
52 #define IORD_ALT_AVALON_I2C_RX_DATA(base)                   IORD(base, ALT_AVALON_I2C_RX_DATA_REG)
53 #define IOWR_ALT_AVALON_I2C_RX_DATA(base, data)             IOWR(base, ALT_AVALON_I2C_RX_DATA_REG, data)
54 #define ALT_AVALON_I2C_RX_DATA_RXDATA_OFST                  (0)
55 #define ALT_AVALON_I2C_RX_DATA_RXDATA_MSK                   (0xff << ALT_AVALON_I2C_RX_DATA_RXDATA_OFST)
56 
57 #define ALT_AVALON_I2C_CTRL_REG                             2
58 #define IOADDR_ALT_AVALON_I2C_CTRL(base)                    __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_CTRL_REG)
59 #define IORD_ALT_AVALON_I2C_CTRL(base)                      IORD(base, ALT_AVALON_I2C_CTRL_REG)
60 #define IOWR_ALT_AVALON_I2C_CTRL(base, data)                IOWR(base, ALT_AVALON_I2C_CTRL_REG, data)
61 #define IORMW_ALT_AVALON_I2C_CTRL(base, data, mask)         IORMW(base,ALT_AVALON_I2C_CTRL_REG,data,mask)
62 #define ALT_AVALON_I2C_CTRL_RX_DATA_FIFO_THD_OFST           (4)
63 #define ALT_AVALON_I2C_CTRL_RX_DATA_FIFO_THD_MSK            (3 << ALT_AVALON_I2C_CTRL_RX_DATA_FIFO_THD_OFST)
64 #define ALT_AVALON_I2C_CTRL_TFR_CMD_FIFO_THD_OFST           (2)
65 #define ALT_AVALON_I2C_CTRL_TFR_CMD_FIFO_THD_MSK            (3 << ALT_AVALON_I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
66 #define ALT_AVALON_I2C_CTRL_BUS_SPEED_OFST                  (1)
67 #define ALT_AVALON_I2C_CTRL_BUS_SPEED_MSK                   (1 << ALT_AVALON_I2C_CTRL_BUS_SPEED_OFST)
68 #define ALT_AVALON_I2C_CTRL_EN_OFST                         (0)
69 #define ALT_AVALON_I2C_CTRL_EN_MSK                          (1 << ALT_AVALON_I2C_CTRL_EN_OFST)
70 
71 #define ALT_AVALON_I2C_ISER_REG                             3
72 #define IOADDR_ALT_AVALON_I2C_ISER(base)                    __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_ISER_REG)
73 #define IORD_ALT_AVALON_I2C_ISER(base)                      IORD(base, ALT_AVALON_I2C_ISER_REG)
74 #define IOWR_ALT_AVALON_I2C_ISER(base, data)                IOWR(base, ALT_AVALON_I2C_ISER_REG, data)
75 #define IORMW_ALT_AVALON_I2C_ISER(base, data, mask)         IORMW(base,ALT_AVALON_I2C_ISER_REG,data,mask)
76 #define ALT_AVALON_I2C_ISER_RX_OVER_EN_OFST                 (4)
77 #define ALT_AVALON_I2C_ISER_RX_OVER_EN_MSK                  (1 << ALT_AVALON_I2C_ISER_RX_OVER_EN_OFST)
78 #define ALT_AVALON_I2C_ISER_ARBLOST_DET_EN_OFST             (3)
79 #define ALT_AVALON_I2C_ISER_ARBLOST_DET_EN_MSK              (1 << ALT_AVALON_I2C_ISER_ARBLOST_DET_EN_OFST)
80 #define ALT_AVALON_I2C_ISER_NACK_DET_EN_OFST                (2)
81 #define ALT_AVALON_I2C_ISER_NACK_DET_EN_MSK                 (1 << ALT_AVALON_I2C_ISER_NACK_DET_EN_OFST)
82 #define ALT_AVALON_I2C_ISER_RX_READY_EN_OFST                (1)
83 #define ALT_AVALON_I2C_ISER_RX_READY_EN_MSK                 (1 << ALT_AVALON_I2C_ISER_RX_READY_EN_OFST)
84 #define ALT_AVALON_I2C_ISER_TX_READY_EN_OFST                (0)
85 #define ALT_AVALON_I2C_ISER_TX_READY_EN_MSK                 (1 << ALT_AVALON_I2C_ISER_TX_READY_EN_OFST)
86 
87 #define ALT_AVALON_I2C_ISR_REG                              4
88 #define IOADDR_ALT_AVALON_I2C_ISR(base)                     __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_ISR_REG)
89 #define IORD_ALT_AVALON_I2C_ISR(base)                       IORD(base, ALT_AVALON_I2C_ISR_REG)
90 #define IOWR_ALT_AVALON_I2C_ISR(base, data)                 IOWR(base, ALT_AVALON_I2C_ISR_REG, data)
91 #define IORMW_ALT_AVALON_I2C_ISR(base, data, mask)          IORMW(base,ALT_AVALON_I2C_ISR_REG,data,mask)
92 #define ALT_AVALON_I2C_ISR_RX_OVER_OFST                    (4)
93 #define ALT_AVALON_I2C_ISR_RX_OVER_MSK                     (1 << ALT_AVALON_I2C_ISR_RX_OVER_OFST)
94 #define ALT_AVALON_I2C_ISR_ARBLOST_DET_OFST                (3)
95 #define ALT_AVALON_I2C_ISR_ARBLOST_DET_MSK                 (1 << ALT_AVALON_I2C_ISR_ARBLOST_DET_OFST)
96 #define ALT_AVALON_I2C_ISR_NACK_DET_OFST                   (2)
97 #define ALT_AVALON_I2C_ISR_NACK_DET_MSK                    (1 << ALT_AVALON_I2C_ISR_NACK_DET_OFST)
98 #define ALT_AVALON_I2C_ISR_RX_READY_OFST                   (1)
99 #define ALT_AVALON_I2C_ISR_RX_READY_MSK                    (1 << ALT_AVALON_I2C_ISR_RX_READY_OFST)
100 #define ALT_AVALON_I2C_ISR_TX_READY_OFST                   (0)
101 #define ALT_AVALON_I2C_ISR_TX_READY_MSK                    (1 << ALT_AVALON_I2C_ISR_TX_READY_OFST)
102 #define ALT_AVALON_I2C_ISR_ALLINTS_MSK                     (ALT_AVALON_I2C_ISR_RX_OVER_MSK | ALT_AVALON_I2C_ISR_ARBLOST_DET_MSK |  \
103                                                                ALT_AVALON_I2C_ISR_NACK_DET_MSK | ALT_AVALON_I2C_ISR_RX_READY_MSK | \
104                                                                ALT_AVALON_I2C_ISR_TX_READY_MSK)
105 #define ALT_AVALON_I2C_ISR_ALL_CLEARABLE_INTS_MSK          (ALT_AVALON_I2C_ISR_RX_OVER_MSK | ALT_AVALON_I2C_ISR_ARBLOST_DET_MSK |  \
106                                                                ALT_AVALON_I2C_ISR_NACK_DET_MSK)
107 
108 #define ALT_AVALON_I2C_STATUS_REG                           5
109 #define IOADDR_ALT_AVALON_I2C_STATUS(base)                  __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_STATUS_REG)
110 #define IORD_ALT_AVALON_I2C_STATUS(base)                    IORD(base, ALT_AVALON_I2C_STATUS_REG)
111 #define IOWR_ALT_AVALON_I2C_STATUS(base, data)              IOWR(base, ALT_AVALON_I2C_STATUS_REG, data)
112 #define ALT_AVALON_I2C_STATUS_CORE_STATUS_OFST              (0)
113 #define ALT_AVALON_I2C_STATUS_CORE_STATUS_MSK               (1 << ALT_AVALON_I2C_STATUS_CORE_STATUS_OFST)
114 
115 #define ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_REG                 6
116 #define IOADDR_ALT_AVALON_I2C_TFR_CMD_FIFO_LVL(base)        __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_REG)
117 #define IORD_ALT_AVALON_I2C_TFR_CMD_FIFO_LVL(base)          IORD(base, ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_REG)
118 #define IOWR_ALT_AVALON_I2C_TFR_CMD_FIFO_LVL(base, data)    IOWR(base, ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_REG, data)
119 #define ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_FIFO_DEPTH_OFST     (0)
120 #define ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_FIFO_DEPTH_MSK(cmdfifodepth)      ((cmdfifodepth-1) << ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_FIFO_DEPTH_OFST)
121 
122 #define ALT_AVALON_I2C_RX_DATA_FIFO_LVL_REG                 7
123 #define IOADDR_ALT_AVALON_I2C_RX_DATA_FIFO_LVL(base)        __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_RX_DATA_FIFO_LVL_REG)
124 #define IORD_ALT_AVALON_I2C_RX_DATA_FIFO_LVL(base)          IORD(base, ALT_AVALON_I2C_RX_DATA_FIFO_LVL_REG)
125 #define IOWR_ALT_AVALON_I2C_RX_DATA_FIFO_LVL(base, data)    IOWR(base, ALT_AVALON_I2C_RX_DATA_FIFO_LVL_REG, data)
126 #define ALT_AVALON_I2C_RX_DATA_FIFO_LVL_FIFO_DEPTH_OFST     (0)
127 #define ALT_AVALON_I2C_RX_DATA_FIFO_LVL_FIFO_DEPTH_MSK(rxfifodepth)      ((rxfifodepth-1) << ALT_AVALON_I2C_TFR_CMD_FIFO_LVL_FIFO_DEPTH_OFST)
128 
129 #define ALT_AVALON_I2C_SCL_LOW_REG                          8
130 #define IOADDR_ALT_AVALON_I2C_SCL_LOW(base)                 __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_SCL_LOW_REG)
131 #define IORD_ALT_AVALON_I2C_SCL_LOW(base)                   IORD(base, ALT_AVALON_I2C_SCL_LOW_REG)
132 #define IOWR_ALT_AVALON_I2C_SCL_LOW(base, data)             IOWR(base, ALT_AVALON_I2C_SCL_LOW_REG, data)
133 #define ALT_AVALON_I2C_SCL_LOW_COUNT_PERIOD_OFST            (0)
134 #define ALT_AVALON_I2C_SCL_LOW_COUNT_PERIOD_MSK             (0xffff << ALT_AVALON_I2C_SCL_LOW_COUNT_PERIOD_OFST)
135 
136 #define ALT_AVALON_I2C_SCL_HIGH_REG                         9
137 #define IOADDR_ALT_AVALON_I2C_SCL_HIGH(base)                __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_SCL_HIGH_REG)
138 #define IORD_ALT_AVALON_I2C_SCL_HIGH(base)                  IORD(base, ALT_AVALON_I2C_SCL_HIGH_REG)
139 #define IOWR_ALT_AVALON_I2C_SCL_HIGH(base, data)            IOWR(base, ALT_AVALON_I2C_SCL_HIGH_REG, data)
140 #define ALT_AVALON_I2C_SCL_HIGH_COUNT_PERIOD_OFST           (0)
141 #define ALT_AVALON_I2C_SCL_HIGH_COUNT_PERIOD_MSK            (0xffff << ALT_AVALON_I2C_SCL_HIGH_COUNT_PERIOD_OFST)
142 
143 #define ALT_AVALON_I2C_SDA_HOLD_REG                         0xa
144 #define IOADDR_ALT_AVALON_I2C_SDA_HOLD(base)                __IO_CALC_ADDRESS_NATIVE(base, ALT_AVALON_I2C_SDA_HOLD_REG)
145 #define IORD_ALT_AVALON_I2C_SDA_HOLD(base)                  IORD(base, ALT_AVALON_I2C_SDA_HOLD_REG)
146 #define IOWR_ALT_AVALON_I2C_SDA_HOLD(base, data)            IOWR(base, ALT_AVALON_I2C_SDA_HOLD_REG, data)
147 #define ALT_AVALON_I2C_SDA_HOLD_COUNT_PERIOD_OFST           (0)
148 #define ALT_AVALON_I2C_SDA_HOLD_COUNT_PERIOD_MSK            (0xffff << ALT_AVALON_I2C_SDA_HOLD_COUNT_PERIOD_OFST)
149 
150 #endif /* __ALT_AVALON_I2C_REGS_H__ */
151