1 /****************************************************************************** 2 * 3 * Copyright (C) 2023 Analog Devices, Inc. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 19 #include "max32665.h" 20 #include "mxc_sys.h" 21 #include "gcr_regs.h" 22 #include "icc_regs.h" 23 #include "pwrseq_regs.h" 24 #include "simo_regs.h" 25 #include "mcr_regs.h" 26 pre_init(void)27static int pre_init(void) 28 { 29 uint32_t psc = MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC; 30 31 /* Disable USB switch to minimize current consumption */ 32 MXC_MCR->ctrl |= MXC_F_MCR_CTRL_USBSWEN_N; 33 34 /* Divide down system clock until SIMO is ready */ 35 MXC_GCR->clkcn = (MXC_GCR->clkcn & ~(MXC_F_GCR_CLKCN_PSC)) | (MXC_S_GCR_CLKCN_PSC_DIV128); 36 37 while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA)) {} 38 while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB)) {} 39 while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC)) {} 40 41 /* Restore system clock divider */ 42 MXC_GCR->clkcn = (MXC_GCR->clkcn & ~(MXC_F_GCR_CLKCN_PSC)) | (psc); 43 44 /* Set the proper OVR setting */ 45 MXC_GCR->scon = (MXC_GCR->scon & ~(MXC_F_GCR_SCON_OVR)) | (MXC_S_GCR_SCON_OVR_1_1V); 46 47 return 0; 48 } 49 50 /* 51 * This function is called during boot up. 52 */ max32xx_system_init(void)53void max32xx_system_init(void) 54 { 55 pre_init(); 56 57 /* Disable SRAM ECC until it is handled on zephyr side */ 58 MXC_MCR->eccen &= ~(MXC_F_MCR_ECCEN_SYSRAM0ECCEN | MXC_F_MCR_ECCEN_SYSRAM1ECCEN | 59 MXC_F_MCR_ECCEN_SYSRAM2ECCEN | MXC_F_MCR_ECCEN_SYSRAM3ECCEN | 60 MXC_F_MCR_ECCEN_SYSRAM4ECCEN | MXC_F_MCR_ECCEN_SYSRAM5ECCEN); 61 62 /* We'd like to switch to the fast clock, but can only do so if the 63 * core's operating voltage (VregO_B) is high enough to support it 64 * Otherwise, we need to remain on the slow clock 65 */ 66 if ((MXC_SIMO->vrego_b > 48) && (MXC_SIMO->buck_out_ready & 0x2)) { 67 // Switch to fast clock on startup 68 MXC_GCR->clkcn &= ~(MXC_S_GCR_CLKCN_PSC_DIV128); 69 MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC96); 70 } 71 72 // FIXME Pre-production parts: Enable TME, disable ICache Read Buffer, disable TME 73 *(uint32_t *)0x40000c00 = 1; 74 *(uint32_t *)0x4000040c = (1 << 6); 75 *(uint32_t *)0x40000c00 = 0; 76 77 // Flush and enable instruction cache 78 MXC_ICC0->invalidate = 1; 79 while (!(MXC_ICC0->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {} 80 MXC_ICC0->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_EN; 81 while (!(MXC_ICC0->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {} 82 83 // Set all GPIO to 25K pullup mode by default 84 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); 85 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); 86 MXC_GPIO0->vssel |= 0xFFFFFFFF; 87 MXC_GPIO0->ps |= 0xFFFFFFFF; 88 MXC_GPIO0->pad_cfg1 |= 0xFFFFFFFF; 89 MXC_GPIO0->pad_cfg2 &= ~(0xFFFFFFFF); 90 MXC_GPIO1->vssel |= 0xFFFFFFFF; 91 MXC_GPIO1->ps |= 0xFFFFFFFF; 92 MXC_GPIO1->pad_cfg1 |= 0xFFFFFFFF; 93 MXC_GPIO1->pad_cfg2 &= ~(0xFFFFFFFF); 94 95 /* Disable fast wakeup due to issues with SIMO in wakeup */ 96 MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_FWKM; 97 } 98
