1 /****************************************************************************** 2 * 3 * Copyright (C) 2025 Analog Devices, Inc. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 19 #include "max32650.h" 20 #include "mxc_sys.h" 21 #include "icc.h" 22 23 /* 24 * This function is called during boot up. 25 */ max32xx_system_init(void)26void max32xx_system_init(void) 27 { 28 /* Workaround: Write to SCON register on power up to fix trim issue for SRAM */ 29 MXC_GCR->scon = (MXC_GCR->scon & ~(MXC_F_GCR_SCON_OVR)) | (MXC_S_GCR_SCON_OVR_1V1); 30 31 /* Erratum #?: Adjust register timing for VCORE == 1.1v, prevents USB failure. 2017-10-04 ZNM/HTN */ 32 MXC_GCR->scon |= MXC_S_GCR_SCON_OVR_1V1; 33 34 // Flush and enable instruction cache 35 MXC_ICC->invalidate = 1; 36 while (!(MXC_ICC->cache_ctrl & MXC_F_ICC_CACHE_CTRL_READY)) {} 37 MXC_ICC->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_ENABLE; 38 while (!(MXC_ICC->cache_ctrl & MXC_F_ICC_CACHE_CTRL_READY)) {} 39 40 /* Shutdown all peripheral clocks initially. They will be re-enabled by each periph's init function. */ 41 /* GPIO Clocks are left enabled */ 42 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_USB); 43 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TFT); 44 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA); 45 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0); 46 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); 47 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI2); 48 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0); 49 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1); 50 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); 51 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TPU); 52 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TIMER0); 53 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TIMER1); 54 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TIMER2); 55 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TIMER3); 56 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TIMER4); 57 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TIMER5); 58 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_ADC); 59 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); 60 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_PT); 61 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPIXIPF); 62 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPIXIPM); 63 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART2); 64 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TRNG); 65 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_FLC); 66 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_HBC); 67 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SCACHE); 68 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SDMA); 69 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SEMA); 70 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SDHC); 71 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_ICACHE); 72 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_ICACHEXIP); 73 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_OWIRE); 74 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI3); 75 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2S); 76 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPIXIPR); 77 } 78
