1 /** 2 * @file wut_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the WUT_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _WUT_REVA_REGS_H_ 27 #define _WUT_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup wut_reva 65 * @defgroup wut_reva_registers WUT_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the WUT_REVA Peripheral Module. 67 * @details Wake Up Timer 68 */ 69 70 /** 71 * @ingroup wut_reva_registers 72 * Structure type to access the WUT_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cnt; /**< <tt>\b 0x0000:</tt> WUT_REVA CNT Register */ 76 __IO uint32_t cmp; /**< <tt>\b 0x0004:</tt> WUT_REVA CMP Register */ 77 __IO uint32_t pwm; /**< <tt>\b 0x0008:</tt> WUT_REVA PWM Register */ 78 __IO uint32_t intfl; /**< <tt>\b 0x000C:</tt> WUT_REVA INTFL Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x0010:</tt> WUT_REVA CTRL Register */ 80 __IO uint32_t nolcmp; /**< <tt>\b 0x0014:</tt> WUT_REVA NOLCMP Register */ 81 __IO uint32_t preset; /**< <tt>\b 0x0018:</tt> WUT_REVA PRESET Register */ 82 __IO uint32_t reload; /**< <tt>\b 0x001C:</tt> WUT_REVA RELOAD Register */ 83 __IO uint32_t snapshot; /**< <tt>\b 0x0020:</tt> WUT_REVA SNAPSHOT Register */ 84 } mxc_wut_reva_regs_t; 85 86 /** 87 * @ingroup wut_reva_registers 88 * @defgroup WUT_REVA_CNT WUT_REVA_CNT 89 * @brief Wakeup Timer Count Register 90 * @{ 91 */ 92 #define MXC_F_WUT_REVA_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ 93 #define MXC_F_WUT_REVA_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_REVA_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ 94 95 /**@} end of group WUT_REVA_CNT_Register */ 96 97 /** 98 * @ingroup wut_reva_registers 99 * @defgroup WUT_REVA_CMP WUT_REVA_CMP 100 * @brief Wakeup Timer Compare Register 101 * @{ 102 */ 103 #define MXC_F_WUT_REVA_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ 104 #define MXC_F_WUT_REVA_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_REVA_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ 105 106 /**@} end of group WUT_REVA_CMP_Register */ 107 108 /** 109 * @ingroup wut_reva_registers 110 * @defgroup WUT_REVA_PWM WUT_REVA_PWM 111 * @brief Wakeup Timer PWM Register 112 * @{ 113 */ 114 #define MXC_F_WUT_REVA_PWM_PWM_POS 0 /**< PWM_PWM Position */ 115 #define MXC_F_WUT_REVA_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_REVA_PWM_PWM_POS)) /**< PWM_PWM Mask */ 116 117 /**@} end of group WUT_REVA_PWM_Register */ 118 119 /** 120 * @ingroup wut_reva_registers 121 * @defgroup WUT_REVA_INTFL WUT_REVA_INTFL 122 * @brief Wakeup Timer Interrupt Register 123 * @{ 124 */ 125 #define MXC_F_WUT_REVA_INTFL_IRQ_CLR_POS 0 /**< INTFL_IRQ_CLR Position */ 126 #define MXC_F_WUT_REVA_INTFL_IRQ_CLR ((uint32_t)(0x1UL << MXC_F_WUT_REVA_INTFL_IRQ_CLR_POS)) /**< INTFL_IRQ_CLR Mask */ 127 128 /**@} end of group WUT_REVA_INTFL_Register */ 129 130 /** 131 * @ingroup wut_reva_registers 132 * @defgroup WUT_REVA_CTRL WUT_REVA_CTRL 133 * @brief Wakeup Timer Control Register 134 * @{ 135 */ 136 #define MXC_F_WUT_REVA_CTRL_TMODE_POS 0 /**< CTRL_TMODE Position */ 137 #define MXC_F_WUT_REVA_CTRL_TMODE ((uint32_t)(0x7UL << MXC_F_WUT_REVA_CTRL_TMODE_POS)) /**< CTRL_TMODE Mask */ 138 #define MXC_V_WUT_REVA_CTRL_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CTRL_TMODE_ONESHOT Value */ 139 #define MXC_S_WUT_REVA_CTRL_TMODE_ONESHOT (MXC_V_WUT_REVA_CTRL_TMODE_ONESHOT << MXC_F_WUT_REVA_CTRL_TMODE_POS) /**< CTRL_TMODE_ONESHOT Setting */ 140 #define MXC_V_WUT_REVA_CTRL_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL_TMODE_CONTINUOUS Value */ 141 #define MXC_S_WUT_REVA_CTRL_TMODE_CONTINUOUS (MXC_V_WUT_REVA_CTRL_TMODE_CONTINUOUS << MXC_F_WUT_REVA_CTRL_TMODE_POS) /**< CTRL_TMODE_CONTINUOUS Setting */ 142 143 #define MXC_F_WUT_REVA_CTRL_PRES_POS 3 /**< CTRL_PRES Position */ 144 #define MXC_F_WUT_REVA_CTRL_PRES ((uint32_t)(0x7UL << MXC_F_WUT_REVA_CTRL_PRES_POS)) /**< CTRL_PRES Mask */ 145 #define MXC_V_WUT_REVA_CTRL_PRES_DIV1 ((uint32_t)0x0UL) /**< CTRL_PRES_DIV1 Value */ 146 #define MXC_S_WUT_REVA_CTRL_PRES_DIV1 (MXC_V_WUT_REVA_CTRL_PRES_DIV1 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV1 Setting */ 147 #define MXC_V_WUT_REVA_CTRL_PRES_DIV2 ((uint32_t)0x1UL) /**< CTRL_PRES_DIV2 Value */ 148 #define MXC_S_WUT_REVA_CTRL_PRES_DIV2 (MXC_V_WUT_REVA_CTRL_PRES_DIV2 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV2 Setting */ 149 #define MXC_V_WUT_REVA_CTRL_PRES_DIV4 ((uint32_t)0x2UL) /**< CTRL_PRES_DIV4 Value */ 150 #define MXC_S_WUT_REVA_CTRL_PRES_DIV4 (MXC_V_WUT_REVA_CTRL_PRES_DIV4 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV4 Setting */ 151 #define MXC_V_WUT_REVA_CTRL_PRES_DIV8 ((uint32_t)0x3UL) /**< CTRL_PRES_DIV8 Value */ 152 #define MXC_S_WUT_REVA_CTRL_PRES_DIV8 (MXC_V_WUT_REVA_CTRL_PRES_DIV8 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV8 Setting */ 153 #define MXC_V_WUT_REVA_CTRL_PRES_DIV16 ((uint32_t)0x4UL) /**< CTRL_PRES_DIV16 Value */ 154 #define MXC_S_WUT_REVA_CTRL_PRES_DIV16 (MXC_V_WUT_REVA_CTRL_PRES_DIV16 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV16 Setting */ 155 #define MXC_V_WUT_REVA_CTRL_PRES_DIV32 ((uint32_t)0x5UL) /**< CTRL_PRES_DIV32 Value */ 156 #define MXC_S_WUT_REVA_CTRL_PRES_DIV32 (MXC_V_WUT_REVA_CTRL_PRES_DIV32 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV32 Setting */ 157 #define MXC_V_WUT_REVA_CTRL_PRES_DIV64 ((uint32_t)0x6UL) /**< CTRL_PRES_DIV64 Value */ 158 #define MXC_S_WUT_REVA_CTRL_PRES_DIV64 (MXC_V_WUT_REVA_CTRL_PRES_DIV64 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV64 Setting */ 159 #define MXC_V_WUT_REVA_CTRL_PRES_DIV128 ((uint32_t)0x7UL) /**< CTRL_PRES_DIV128 Value */ 160 #define MXC_S_WUT_REVA_CTRL_PRES_DIV128 (MXC_V_WUT_REVA_CTRL_PRES_DIV128 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV128 Setting */ 161 #define MXC_V_WUT_REVA_CTRL_PRES_DIV256 ((uint32_t)0x0UL) /**< CTRL_PRES_DIV256 Value */ 162 #define MXC_S_WUT_REVA_CTRL_PRES_DIV256 (MXC_V_WUT_REVA_CTRL_PRES_DIV256 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV256 Setting */ 163 #define MXC_V_WUT_REVA_CTRL_PRES_DIV512 ((uint32_t)0x2UL) /**< CTRL_PRES_DIV512 Value */ 164 #define MXC_S_WUT_REVA_CTRL_PRES_DIV512 (MXC_V_WUT_REVA_CTRL_PRES_DIV512 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV512 Setting */ 165 #define MXC_V_WUT_REVA_CTRL_PRES_DIV1024 ((uint32_t)0x3UL) /**< CTRL_PRES_DIV1024 Value */ 166 #define MXC_S_WUT_REVA_CTRL_PRES_DIV1024 (MXC_V_WUT_REVA_CTRL_PRES_DIV1024 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV1024 Setting */ 167 #define MXC_V_WUT_REVA_CTRL_PRES_DIV2048 ((uint32_t)0x4UL) /**< CTRL_PRES_DIV2048 Value */ 168 #define MXC_S_WUT_REVA_CTRL_PRES_DIV2048 (MXC_V_WUT_REVA_CTRL_PRES_DIV2048 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV2048 Setting */ 169 #define MXC_V_WUT_REVA_CTRL_PRES_DIV4096 ((uint32_t)0x5UL) /**< CTRL_PRES_DIV4096 Value */ 170 #define MXC_S_WUT_REVA_CTRL_PRES_DIV4096 (MXC_V_WUT_REVA_CTRL_PRES_DIV4096 << MXC_F_WUT_REVA_CTRL_PRES_POS) /**< CTRL_PRES_DIV4096 Setting */ 171 172 #define MXC_F_WUT_REVA_CTRL_TPOL_POS 6 /**< CTRL_TPOL Position */ 173 #define MXC_F_WUT_REVA_CTRL_TPOL ((uint32_t)(0x1UL << MXC_F_WUT_REVA_CTRL_TPOL_POS)) /**< CTRL_TPOL Mask */ 174 175 #define MXC_F_WUT_REVA_CTRL_TEN_POS 7 /**< CTRL_TEN Position */ 176 #define MXC_F_WUT_REVA_CTRL_TEN ((uint32_t)(0x1UL << MXC_F_WUT_REVA_CTRL_TEN_POS)) /**< CTRL_TEN Mask */ 177 178 #define MXC_F_WUT_REVA_CTRL_PRES3_POS 8 /**< CTRL_PRES3 Position */ 179 #define MXC_F_WUT_REVA_CTRL_PRES3 ((uint32_t)(0x1UL << MXC_F_WUT_REVA_CTRL_PRES3_POS)) /**< CTRL_PRES3 Mask */ 180 181 #define MXC_F_WUT_REVA_CTRL_PWMSYNC_POS 9 /**< CTRL_PWMSYNC Position */ 182 #define MXC_F_WUT_REVA_CTRL_PWMSYNC ((uint32_t)(0x1UL << MXC_F_WUT_REVA_CTRL_PWMSYNC_POS)) /**< CTRL_PWMSYNC Mask */ 183 184 #define MXC_F_WUT_REVA_CTRL_NOLHPOL_POS 10 /**< CTRL_NOLHPOL Position */ 185 #define MXC_F_WUT_REVA_CTRL_NOLHPOL ((uint32_t)(0x1UL << MXC_F_WUT_REVA_CTRL_NOLHPOL_POS)) /**< CTRL_NOLHPOL Mask */ 186 187 #define MXC_F_WUT_REVA_CTRL_NOLLPOL_POS 11 /**< CTRL_NOLLPOL Position */ 188 #define MXC_F_WUT_REVA_CTRL_NOLLPOL ((uint32_t)(0x1UL << MXC_F_WUT_REVA_CTRL_NOLLPOL_POS)) /**< CTRL_NOLLPOL Mask */ 189 190 #define MXC_F_WUT_REVA_CTRL_PWMCKBD_POS 12 /**< CTRL_PWMCKBD Position */ 191 #define MXC_F_WUT_REVA_CTRL_PWMCKBD ((uint32_t)(0x1UL << MXC_F_WUT_REVA_CTRL_PWMCKBD_POS)) /**< CTRL_PWMCKBD Mask */ 192 193 /**@} end of group WUT_REVA_CTRL_Register */ 194 195 /** 196 * @ingroup wut_reva_registers 197 * @defgroup WUT_REVA_NOLCMP WUT_REVA_NOLCMP 198 * @brief Non Overlaping Compare Register 199 * @{ 200 */ 201 #define MXC_F_WUT_REVA_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ 202 #define MXC_F_WUT_REVA_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_WUT_REVA_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ 203 204 #define MXC_F_WUT_REVA_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ 205 #define MXC_F_WUT_REVA_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_WUT_REVA_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ 206 207 /**@} end of group WUT_REVA_NOLCMP_Register */ 208 209 #ifdef __cplusplus 210 } 211 #endif 212 213 #endif /* _WUT_REVA_REGS_H_ */ 214
