1 /** 2 * @file wdt_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _WDT_REVA_REGS_H_ 27 #define _WDT_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup wdt 65 * @defgroup wdt_registers WDT_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. 67 * @details Watchdog Timer 0 68 */ 69 70 /** 71 * @ingroup wdt_registers 72 * Structure type to access the WDT Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> WDT CTRL Register */ 76 __O uint32_t rst; /**< <tt>\b 0x04:</tt> WDT RST Register */ 77 } mxc_wdt_reva_regs_t; 78 79 /* Register offsets for module WDT */ 80 /** 81 * @ingroup wdt_registers 82 * @defgroup WDT_Register_Offsets Register Offsets 83 * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. 84 * @{ 85 */ 86 #define MXC_R_WDT_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */ 87 #define MXC_R_WDT_REVA_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */ 88 /**@} end of group wdt_registers */ 89 90 /** 91 * @ingroup wdt_registers 92 * @defgroup WDT_CTRL WDT_CTRL 93 * @brief Watchdog Timer Control Register. 94 * @{ 95 */ 96 #define MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ 97 #define MXC_F_WDT_REVA_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */ 98 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ 99 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */ 100 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ 101 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */ 102 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ 103 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */ 104 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ 105 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */ 106 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ 107 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */ 108 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ 109 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */ 110 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ 111 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */ 112 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ 113 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */ 114 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ 115 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */ 116 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ 117 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */ 118 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ 119 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */ 120 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ 121 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */ 122 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ 123 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */ 124 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ 125 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */ 126 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ 127 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */ 128 #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ 129 #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */ 130 131 #define MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ 132 #define MXC_F_WDT_REVA_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */ 133 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ 134 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */ 135 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ 136 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */ 137 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ 138 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */ 139 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ 140 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */ 141 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ 142 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */ 143 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ 144 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */ 145 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ 146 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */ 147 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ 148 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */ 149 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ 150 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */ 151 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ 152 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */ 153 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ 154 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */ 155 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ 156 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */ 157 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ 158 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */ 159 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ 160 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */ 161 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ 162 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */ 163 #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ 164 #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */ 165 166 #define MXC_F_WDT_REVA_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ 167 #define MXC_F_WDT_REVA_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ 168 169 #define MXC_F_WDT_REVA_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ 170 #define MXC_F_WDT_REVA_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ 171 172 #define MXC_F_WDT_REVA_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ 173 #define MXC_F_WDT_REVA_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ 174 175 #define MXC_F_WDT_REVA_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ 176 #define MXC_F_WDT_REVA_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ 177 178 #define MXC_F_WDT_REVA_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ 179 #define MXC_F_WDT_REVA_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ 180 181 /**@} end of group WDT_CTRL_Register */ 182 183 /** 184 * @ingroup wdt_registers 185 * @defgroup WDT_RST WDT_RST 186 * @brief Watchdog Timer Reset Register. 187 * @{ 188 */ 189 #define MXC_F_WDT_REVA_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ 190 #define MXC_F_WDT_REVA_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_REVA_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ 191 #define MXC_V_WDT_REVA_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ 192 #define MXC_S_WDT_REVA_RST_WDT_RST_SEQ0 (MXC_V_WDT_REVA_RST_WDT_RST_SEQ0 << MXC_F_WDT_REVA_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ 193 #define MXC_V_WDT_REVA_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ 194 #define MXC_S_WDT_REVA_RST_WDT_RST_SEQ1 (MXC_V_WDT_REVA_RST_WDT_RST_SEQ1 << MXC_F_WDT_REVA_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ 195 196 /**@} end of group WDT_RST_Register */ 197 198 #ifdef __cplusplus 199 } 200 #endif 201 202 #endif /* _WDT_REVA_REGS_H_ */ 203
