1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>WDT0</name> 5 <description>Watchdog Timer 0</description> 6 <baseAddress>0x40003000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x0400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>WDT0</name> 14<!-- IRQ Name --> 15 <value>1</value> 16<!-- IRQ Number Device Specific --> 17 </interrupt> 18 <registers> 19 <register> 20 <name>CTRL</name> 21 <description>Watchdog Timer Control Register.</description> 22 <addressOffset>0x00</addressOffset> 23 <resetMask>0x7FFFF000</resetMask> 24 <fields> 25 <field> 26 <name>INT_PERIOD</name> 27 <description>Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 28 <bitOffset>0</bitOffset> 29 <bitWidth>4</bitWidth> 30 <enumeratedValues> 31 <enumeratedValue> 32 <name>wdt2pow31</name> 33 <description>2**31 clock cycles.</description> 34 <value>0</value> 35 </enumeratedValue> 36 <enumeratedValue> 37 <name>wdt2pow30</name> 38 <description>2**30 clock cycles.</description> 39 <value>1</value> 40 </enumeratedValue> 41 <enumeratedValue> 42 <name>wdt2pow29</name> 43 <description>2**29 clock cycles.</description> 44 <value>2</value> 45 </enumeratedValue> 46 <enumeratedValue> 47 <name>wdt2pow28</name> 48 <description>2**28 clock cycles.</description> 49 <value>3</value> 50 </enumeratedValue> 51 <enumeratedValue> 52 <name>wdt2pow27</name> 53 <description>2^27 clock cycles.</description> 54 <value>4</value> 55 </enumeratedValue> 56 <enumeratedValue> 57 <name>wdt2pow26</name> 58 <description>2**26 clock cycles.</description> 59 <value>5</value> 60 </enumeratedValue> 61 <enumeratedValue> 62 <name>wdt2pow25</name> 63 <description>2**25 clock cycles.</description> 64 <value>6</value> 65 </enumeratedValue> 66 <enumeratedValue> 67 <name>wdt2pow24</name> 68 <description>2**24 clock cycles.</description> 69 <value>7</value> 70 </enumeratedValue> 71 <enumeratedValue> 72 <name>wdt2pow23</name> 73 <description>2**23 clock cycles.</description> 74 <value>8</value> 75 </enumeratedValue> 76 <enumeratedValue> 77 <name>wdt2pow22</name> 78 <description>2**22 clock cycles.</description> 79 <value>9</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>wdt2pow21</name> 83 <description>2**21 clock cycles.</description> 84 <value>10</value> 85 </enumeratedValue> 86 <enumeratedValue> 87 <name>wdt2pow20</name> 88 <description>2**20 clock cycles.</description> 89 <value>11</value> 90 </enumeratedValue> 91 <enumeratedValue> 92 <name>wdt2pow19</name> 93 <description>2**19 clock cycles.</description> 94 <value>12</value> 95 </enumeratedValue> 96 <enumeratedValue> 97 <name>wdt2pow18</name> 98 <description>2**18 clock cycles.</description> 99 <value>13</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>wdt2pow17</name> 103 <description>2**17 clock cycles.</description> 104 <value>14</value> 105 </enumeratedValue> 106 <enumeratedValue> 107 <name>wdt2pow16</name> 108 <description>2**16 clock cycles.</description> 109 <value>15</value> 110 </enumeratedValue> 111 </enumeratedValues> 112 </field> 113 <field> 114 <name>RST_PERIOD</name> 115 <description>Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 116 <bitOffset>4</bitOffset> 117 <bitWidth>4</bitWidth> 118 <enumeratedValues> 119 <enumeratedValue> 120 <name>wdt2pow31</name> 121 <description>2**31 clock cycles.</description> 122 <value>0</value> 123 </enumeratedValue> 124 <enumeratedValue> 125 <name>wdt2pow30</name> 126 <description>2**30 clock cycles.</description> 127 <value>1</value> 128 </enumeratedValue> 129 <enumeratedValue> 130 <name>wdt2pow29</name> 131 <description>2**29 clock cycles.</description> 132 <value>2</value> 133 </enumeratedValue> 134 <enumeratedValue> 135 <name>wdt2pow28</name> 136 <description>2**28 clock cycles.</description> 137 <value>3</value> 138 </enumeratedValue> 139 <enumeratedValue> 140 <name>wdt2pow27</name> 141 <description>2^27 clock cycles.</description> 142 <value>4</value> 143 </enumeratedValue> 144 <enumeratedValue> 145 <name>wdt2pow26</name> 146 <description>2**26 clock cycles.</description> 147 <value>5</value> 148 </enumeratedValue> 149 <enumeratedValue> 150 <name>wdt2pow25</name> 151 <description>2**25 clock cycles.</description> 152 <value>6</value> 153 </enumeratedValue> 154 <enumeratedValue> 155 <name>wdt2pow24</name> 156 <description>2**24 clock cycles.</description> 157 <value>7</value> 158 </enumeratedValue> 159 <enumeratedValue> 160 <name>wdt2pow23</name> 161 <description>2**23 clock cycles.</description> 162 <value>8</value> 163 </enumeratedValue> 164 <enumeratedValue> 165 <name>wdt2pow22</name> 166 <description>2**22 clock cycles.</description> 167 <value>9</value> 168 </enumeratedValue> 169 <enumeratedValue> 170 <name>wdt2pow21</name> 171 <description>2**21 clock cycles.</description> 172 <value>10</value> 173 </enumeratedValue> 174 <enumeratedValue> 175 <name>wdt2pow20</name> 176 <description>2**20 clock cycles.</description> 177 <value>11</value> 178 </enumeratedValue> 179 <enumeratedValue> 180 <name>wdt2pow19</name> 181 <description>2**19 clock cycles.</description> 182 <value>12</value> 183 </enumeratedValue> 184 <enumeratedValue> 185 <name>wdt2pow18</name> 186 <description>2**18 clock cycles.</description> 187 <value>13</value> 188 </enumeratedValue> 189 <enumeratedValue> 190 <name>wdt2pow17</name> 191 <description>2**17 clock cycles.</description> 192 <value>14</value> 193 </enumeratedValue> 194 <enumeratedValue> 195 <name>wdt2pow16</name> 196 <description>2**16 clock cycles.</description> 197 <value>15</value> 198 </enumeratedValue> 199 </enumeratedValues> 200 </field> 201 <field> 202 <name>WDT_EN</name> 203 <description>Watchdog Timer Enable.</description> 204 <bitOffset>8</bitOffset> 205 <bitWidth>1</bitWidth> 206 <enumeratedValues> 207 <enumeratedValue> 208 <name>dis</name> 209 <description>Disable.</description> 210 <value>0</value> 211 </enumeratedValue> 212 <enumeratedValue> 213 <name>en</name> 214 <description>Enable.</description> 215 <value>1</value> 216 </enumeratedValue> 217 </enumeratedValues> 218 </field> 219 <field> 220 <name>INT_FLAG</name> 221 <description>Watchdog Timer Interrupt Flag.</description> 222 <bitOffset>9</bitOffset> 223 <bitWidth>1</bitWidth> 224 <modifiedWriteValues>oneToClear</modifiedWriteValues> 225 <enumeratedValues> 226 <enumeratedValue> 227 <name>inactive</name> 228 <description>No interrupt is pending.</description> 229 <value>0</value> 230 </enumeratedValue> 231 <enumeratedValue> 232 <name>pending</name> 233 <description>An interrupt is pending.</description> 234 <value>1</value> 235 </enumeratedValue> 236 </enumeratedValues> 237 </field> 238 <field> 239 <name>INT_EN</name> 240 <description>Watchdog Timer Interrupt Enable.</description> 241 <bitOffset>10</bitOffset> 242 <bitWidth>1</bitWidth> 243 <enumeratedValues> 244 <enumeratedValue> 245 <name>dis</name> 246 <description>Disable.</description> 247 <value>0</value> 248 </enumeratedValue> 249 <enumeratedValue> 250 <name>en</name> 251 <description>Enable.</description> 252 <value>1</value> 253 </enumeratedValue> 254 </enumeratedValues> 255 </field> 256 <field> 257 <name>RST_EN</name> 258 <description>Watchdog Timer Reset Enable.</description> 259 <bitOffset>11</bitOffset> 260 <bitWidth>1</bitWidth> 261 <enumeratedValues> 262 <enumeratedValue> 263 <name>dis</name> 264 <description>Disable.</description> 265 <value>0</value> 266 </enumeratedValue> 267 <enumeratedValue> 268 <name>en</name> 269 <description>Enable.</description> 270 <value>1</value> 271 </enumeratedValue> 272 </enumeratedValues> 273 </field> 274 <field> 275 <name>RST_FLAG</name> 276 <description>Watchdog Timer Reset Flag.</description> 277 <bitOffset>31</bitOffset> 278 <bitWidth>1</bitWidth> 279 <enumeratedValues> 280 <usage>read-write</usage> 281 <enumeratedValue> 282 <name>noEvent</name> 283 <description>The event has not occurred.</description> 284 <value>0</value> 285 </enumeratedValue> 286 <enumeratedValue> 287 <name>rst_occurred</name> 288 <description>The event has occurred.</description> 289 <value>1</value> 290 </enumeratedValue> 291 </enumeratedValues> 292 </field> 293 </fields> 294 </register> 295 <register> 296 <name>RST</name> 297 <description>Watchdog Timer Reset Register.</description> 298 <addressOffset>0x04</addressOffset> 299 <access>write-only</access> 300 <fields> 301 <field> 302 <name>WDT_RST</name> 303 <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.</description> 304 <bitOffset>0</bitOffset> 305 <bitWidth>8</bitWidth> 306 <enumeratedValues> 307 <enumeratedValue> 308 <name>seq0</name> 309 <description>The first value to be written to reset the WDT.</description> 310 <value>0x000000A5</value> 311 </enumeratedValue> 312 <enumeratedValue> 313 <name>seq1</name> 314 <description>The second value to be written to reset the WDT.</description> 315 <value>0x0000005A</value> 316 </enumeratedValue> 317 </enumeratedValues> 318 </field> 319 </fields> 320 </register> 321 </registers> 322 </peripheral> 323<!-- WDT: Watchdog Timer --> 324</device> 325
