1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>UART0</name> 5 <description>UART</description> 6 <baseAddress>0x40020000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>UART0</name> 14 <description>UART0 IRQ</description> 15 <value>14</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CTRL</name> 20 <description>Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <size>32</size> 23 <fields> 24 <field> 25 <name>RXTHD</name> 26 <description>Receive Threshhold.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>4</bitWidth> 29 </field> 30 <field> 31 <name>PAREN</name> 32 <description>Enable/disable Parity bit (9th character).</description> 33 <bitOffset>4</bitOffset> 34 <bitWidth>1</bitWidth> 35 <enumeratedValues> 36 <enumeratedValue> 37 <name>dis</name> 38 <description>No Parity </description> 39 <value>0</value> 40 </enumeratedValue> 41 <enumeratedValue> 42 <name>en</name> 43 <description>Parity enabled as 9th bit</description> 44 <value>1</value> 45 </enumeratedValue> 46 </enumeratedValues> 47 </field> 48 <field> 49 <name>PAREO</name> 50 <description>When PARITY_EN=1, selects odd or even parity.</description> 51 <bitOffset>5</bitOffset> 52 <bitWidth>1</bitWidth> 53 <enumeratedValues> 54 <enumeratedValue> 55 <name>Even</name> 56 <description>Even parity selected.</description> 57 <value>0</value> 58 </enumeratedValue> 59 <enumeratedValue> 60 <name>ODD</name> 61 <description>Odd parity selected.</description> 62 <value>1</value> 63 </enumeratedValue> 64 </enumeratedValues> 65 </field> 66 <field> 67 <name>PARMD</name> 68 <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description> 69 <bitOffset>6</bitOffset> 70 <bitWidth>1</bitWidth> 71 <enumeratedValues> 72 <enumeratedValue> 73 <name>1</name> 74 <description>Parity calculation is based on number of 1s in frame.</description> 75 <value>0</value> 76 </enumeratedValue> 77 <enumeratedValue> 78 <name>0</name> 79 <description>Parity calculation is based on number of 0s in frame.</description> 80 <value>1</value> 81 </enumeratedValue> 82 </enumeratedValues> 83 </field> 84 <field> 85 <name>TXFLUSH</name> 86 <description>Flushes the TX FIFO buffer.</description> 87 <bitOffset>8</bitOffset> 88 <bitWidth>1</bitWidth> 89 </field> 90 <field> 91 <name>RXFLUSH</name> 92 <description>Flushes the RX FIFO buffer.</description> 93 <bitOffset>9</bitOffset> 94 <bitWidth>1</bitWidth> 95 </field> 96 <field> 97 <name>SIZE</name> 98 <description>Selects UART character size.</description> 99 <bitOffset>10</bitOffset> 100 <bitWidth>2</bitWidth> 101 <enumeratedValues> 102 <enumeratedValue> 103 <name>5</name> 104 <description>5 bits.</description> 105 <value>0</value> 106 </enumeratedValue> 107 <enumeratedValue> 108 <name>6</name> 109 <description>6 bits.</description> 110 <value>1</value> 111 </enumeratedValue> 112 <enumeratedValue> 113 <name>7</name> 114 <description>7 bits.</description> 115 <value>2</value> 116 </enumeratedValue> 117 <enumeratedValue> 118 <name>8</name> 119 <description>8 bits.</description> 120 <value>3</value> 121 </enumeratedValue> 122 </enumeratedValues> 123 </field> 124 <field> 125 <name>STOP</name> 126 <description>Selects the number of stop bits that will be generated.</description> 127 <bitOffset>12</bitOffset> 128 <bitWidth>1</bitWidth> 129 <enumeratedValues> 130 <enumeratedValue> 131 <name>1</name> 132 <description>1 stop bit.</description> 133 <value>0</value> 134 </enumeratedValue> 135 <enumeratedValue> 136 <name>1_5</name> 137 <description>1.5 stop bits.</description> 138 <value>1</value> 139 </enumeratedValue> 140 </enumeratedValues> 141 </field> 142 </fields> 143 </register> 144 <register> 145 <name>STAT</name> 146 <description>Status Register.</description> 147 <addressOffset>0x04</addressOffset> 148 <size>32</size> 149 <access>read-only</access> 150 <fields> 151 <field> 152 <name>TXBUSY</name> 153 <description>Read-only flag indicating the UART transmit status.</description> 154 <bitOffset>0</bitOffset> 155 <bitWidth>1</bitWidth> 156 <access>read-only</access> 157 </field> 158 <field> 159 <name>RXBUSY</name> 160 <description>Read-only flag indicating the UART receiver status.</description> 161 <bitOffset>1</bitOffset> 162 <bitWidth>1</bitWidth> 163 <access>read-only</access> 164 </field> 165 <field> 166 <name>RXEMPTY</name> 167 <description>Read-only flag indicating the RX FIFO state.</description> 168 <bitOffset>4</bitOffset> 169 <bitWidth>1</bitWidth> 170 <access>read-only</access> 171 </field> 172 <field> 173 <name>RXFULL</name> 174 <description>Read-only flag indicating the RX FIFO state.</description> 175 <bitOffset>5</bitOffset> 176 <bitWidth>1</bitWidth> 177 <access>read-only</access> 178 </field> 179 <field> 180 <name>TXEMPTY</name> 181 <description>Read-only flag indicating the TX FIFO state.</description> 182 <bitOffset>6</bitOffset> 183 <bitWidth>1</bitWidth> 184 <access>read-only</access> 185 </field> 186 <field> 187 <name>TXFULL</name> 188 <description>Read-only flag indicating the TX FIFO state.</description> 189 <bitOffset>7</bitOffset> 190 <bitWidth>1</bitWidth> 191 <access>read-only</access> 192 </field> 193 <field> 194 <name>RXELT</name> 195 <description>Indicates the number of bytes currently in the RX FIFO.</description> 196 <bitOffset>8</bitOffset> 197 <bitWidth>4</bitWidth> 198 <access>read-only</access> 199 </field> 200 <field> 201 <name>TXELT</name> 202 <description>Indicates the number of bytes currently in the TX FIFO.</description> 203 <bitOffset>12</bitOffset> 204 <bitWidth>4</bitWidth> 205 <access>read-only</access> 206 </field> 207 </fields> 208 </register> 209 <register> 210 <name>INT_EN</name> 211 <description>Interrupt Enable Register.</description> 212 <addressOffset>0x08</addressOffset> 213 <size>32</size> 214 <fields> 215 <field> 216 <name>FRAMIE</name> 217 <description>Enable for RX Frame Error Interrupt.</description> 218 <bitOffset>0</bitOffset> 219 <bitWidth>1</bitWidth> 220 </field> 221 <field> 222 <name>PARITYIE</name> 223 <description>Enable for RX Parity Error interrupt.</description> 224 <bitOffset>1</bitOffset> 225 <bitWidth>1</bitWidth> 226 </field> 227 <field> 228 <name>OVERIE</name> 229 <description>Enable for RX FIFO OVerrun interrupt.</description> 230 <bitOffset>3</bitOffset> 231 <bitWidth>1</bitWidth> 232 </field> 233 <field> 234 <name>FFRXIE</name> 235 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 236 <bitOffset>4</bitOffset> 237 <bitWidth>1</bitWidth> 238 </field> 239 <field> 240 <name>FFTXOIE</name> 241 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 242 <bitOffset>5</bitOffset> 243 <bitWidth>1</bitWidth> 244 </field> 245 <field> 246 <name>FFTXHIE</name> 247 <description>Enable for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less.</description> 248 <bitOffset>6</bitOffset> 249 <bitWidth>1</bitWidth> 250 </field> 251 </fields> 252 </register> 253 <register> 254 <name>INT_STAT</name> 255 <description>Interrupt Status Flags.</description> 256 <addressOffset>0x0C</addressOffset> 257 <size>32</size> 258 <modifiedWriteValues>oneToClear</modifiedWriteValues> 259 <fields> 260 <field> 261 <name>FRAMIS</name> 262 <description>FLAG for RX Frame Error Interrupt.</description> 263 <bitOffset>0</bitOffset> 264 <bitWidth>1</bitWidth> 265 </field> 266 <field> 267 <name>PARITYIS</name> 268 <description>FLAG for RX Parity Error interrupt.</description> 269 <bitOffset>1</bitOffset> 270 <bitWidth>1</bitWidth> 271 </field> 272 <field> 273 <name>OVERIS</name> 274 <description>FLAG for RX FIFO Overrun interrupt.</description> 275 <bitOffset>3</bitOffset> 276 <bitWidth>1</bitWidth> 277 </field> 278 <field> 279 <name>FFRXIS</name> 280 <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 281 <bitOffset>4</bitOffset> 282 <bitWidth>1</bitWidth> 283 </field> 284 <field> 285 <name>FFTXOIS</name> 286 <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description> 287 <bitOffset>5</bitOffset> 288 <bitWidth>1</bitWidth> 289 </field> 290 <field> 291 <name>FFTXHIS</name> 292 <description>FLAG for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less.</description> 293 <bitOffset>6</bitOffset> 294 <bitWidth>1</bitWidth> 295 </field> 296 </fields> 297 </register> 298 <register> 299 <name>BAUD0</name> 300 <description>Baud rate register. Integer portion.</description> 301 <addressOffset>0x10</addressOffset> 302 <size>32</size> 303 <fields> 304 <field> 305 <name>IDIV</name> 306 <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description> 307 <bitOffset>0</bitOffset> 308 <bitWidth>12</bitWidth> 309 </field> 310 </fields> 311 </register> 312 <register> 313 <name>BAUD1</name> 314 <description>Baud rate register. Decimal Setting.</description> 315 <addressOffset>0x14</addressOffset> 316 <size>32</size> 317 <fields> 318 <field> 319 <name>DDIV</name> 320 <description>Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.</description> 321 <bitOffset>0</bitOffset> 322 <bitWidth>7</bitWidth> 323 </field> 324 </fields> 325 </register> 326 <register> 327 <name>DATA</name> 328 <description>FIFO Data buffer.</description> 329 <addressOffset>0x20</addressOffset> 330 <size>32</size> 331 <fields> 332 <field> 333 <name>DATA</name> 334 <description>Load/unload location for TX and RX FIFO buffers.</description> 335 <bitOffset>0</bitOffset> 336 <bitWidth>8</bitWidth> 337 </field> 338 <field> 339 <name>PARITY</name> 340 <description>Parity error flag for next byte to be read from FIFO.</description> 341 <bitOffset>8</bitOffset> 342 <bitWidth>1</bitWidth> 343 </field> 344 </fields> 345 </register> 346 <register> 347 <name>DMA</name> 348 <description>DMA Configuration.</description> 349 <addressOffset>0x30</addressOffset> 350 <size>32</size> 351 <fields> 352 <field> 353 <name>TXCNT</name> 354 <description>TX threshold for DMA transmission.</description> 355 <bitOffset>0</bitOffset> 356 <bitWidth>4</bitWidth> 357 </field> 358 <field> 359 <name>TXEN</name> 360 <description>TX DMA channel enable.</description> 361 <bitOffset>4</bitOffset> 362 <bitWidth>1</bitWidth> 363 <enumeratedValues> 364 <enumeratedValue> 365 <name>dis</name> 366 <description>DMA is disabled </description> 367 <value>0</value> 368 </enumeratedValue> 369 <enumeratedValue> 370 <name>en</name> 371 <description>DMA is enabled </description> 372 <value>1</value> 373 </enumeratedValue> 374 </enumeratedValues> 375 </field> 376 <field> 377 <name>RXCNT</name> 378 <description>RX threshold for DMA transmission.</description> 379 <bitOffset>5</bitOffset> 380 <bitWidth>4</bitWidth> 381 </field> 382 <field> 383 <name>RXEN</name> 384 <description>RX DMA channel enable.</description> 385 <bitOffset>9</bitOffset> 386 <bitWidth>1</bitWidth> 387 <enumeratedValues> 388 <enumeratedValue> 389 <name>dis</name> 390 <description>DMA is disabled </description> 391 <value>0</value> 392 </enumeratedValue> 393 <enumeratedValue> 394 <name>en</name> 395 <description>DMA is enabled </description> 396 <value>1</value> 397 </enumeratedValue> 398 </enumeratedValues> 399 </field> 400 </fields> 401 </register> 402 </registers> 403 </peripheral> 404 <!-- UART: UART --> 405</device>
