1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>UART</name> 5 <description>UART Low Power Registers</description> 6 <baseAddress>0x40042000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>CTRL</name> 15 <description>Control register</description> 16 <addressOffset>0x0000</addressOffset> 17 <fields> 18 <field> 19 <name>RX_THD_VAL</name> 20 <description>This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>4</bitWidth> 23 </field> 24 <field> 25 <name>PAR_EN</name> 26 <description>Parity Enable</description> 27 <bitOffset>4</bitOffset> 28 <bitWidth>1</bitWidth> 29 </field> 30 <field> 31 <name>PAR_EO</name> 32 <description>when PAREN=1 selects odd or even parity odd is 1 even is 0</description> 33 <bitOffset>5</bitOffset> 34 <bitWidth>1</bitWidth> 35 </field> 36 <field> 37 <name>PAR_MD</name> 38 <description>Selects parity based on 1s or 0s count (when PAREN=1) </description> 39 <bitOffset>6</bitOffset> 40 <bitWidth>1</bitWidth> 41 </field> 42 <field> 43 <name>CTS_DIS</name> 44 <description>CTS Sampling Disable </description> 45 <bitOffset>7</bitOffset> 46 <bitWidth>1</bitWidth> 47 </field> 48 <field> 49 <name>TX_FLUSH</name> 50 <description>Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 51 <bitOffset>8</bitOffset> 52 <bitWidth>1</bitWidth> 53 </field> 54 <field> 55 <name>RX_FLUSH</name> 56 <description>Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 57 <bitOffset>9</bitOffset> 58 <bitWidth>1</bitWidth> 59 </field> 60 <field> 61 <name>CHAR_SIZE</name> 62 <description>Selects UART character size</description> 63 <bitOffset>10</bitOffset> 64 <bitWidth>2</bitWidth> 65 <enumeratedValues> 66 <enumeratedValue> 67 <name>5bits</name> 68 <description>5 bits</description> 69 <value>0</value> 70 </enumeratedValue> 71 <enumeratedValue> 72 <name>6bits</name> 73 <description>6 bits</description> 74 <value>1</value> 75 </enumeratedValue> 76 <enumeratedValue> 77 <name>7bits</name> 78 <description>7 bits</description> 79 <value>2</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>8bits</name> 83 <description>8 bits</description> 84 <value>3</value> 85 </enumeratedValue> 86 </enumeratedValues> 87 </field> 88 <field> 89 <name>STOPBITS</name> 90 <description>Selects the number of stop bits that will be generated</description> 91 <bitOffset>12</bitOffset> 92 <bitWidth>1</bitWidth> 93 </field> 94 <field> 95 <name>HFC_EN</name> 96 <description>Enables/disables hardware flow control</description> 97 <bitOffset>13</bitOffset> 98 <bitWidth>1</bitWidth> 99 </field> 100 <field> 101 <name>RTSDC</name> 102 <description>Hardware Flow Control RTS Mode</description> 103 <bitOffset>14</bitOffset> 104 <bitWidth>1</bitWidth> 105 </field> 106 <field> 107 <name>BCLKEN</name> 108 <description>Baud clock enable</description> 109 <bitOffset>15</bitOffset> 110 <bitWidth>1</bitWidth> 111 </field> 112 <field> 113 <name>BCLKSRC</name> 114 <description>To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.</description> 115 <bitOffset>16</bitOffset> 116 <bitWidth>2</bitWidth> 117 <enumeratedValues> 118 <enumeratedValue> 119 <name>Peripheral_Clock</name> 120 <description>apb clock</description> 121 <value>0</value> 122 </enumeratedValue> 123 <enumeratedValue> 124 <name>External_Clock</name> 125 <description>Clock 1</description> 126 <value>1</value> 127 </enumeratedValue> 128 <enumeratedValue> 129 <name>CLK2</name> 130 <description>Clock 2</description> 131 <value>2</value> 132 </enumeratedValue> 133 <enumeratedValue> 134 <name>CLK3</name> 135 <description>Clock 3</description> 136 <value>3</value> 137 </enumeratedValue> 138 </enumeratedValues> 139 </field> 140 <field> 141 <name>DPFE_EN</name> 142 <description>Data/Parity bit frame error detection enable</description> 143 <bitOffset>18</bitOffset> 144 <bitWidth>1</bitWidth> 145 </field> 146 <field> 147 <name>BCLKRDY</name> 148 <description>Baud clock Ready read only bit</description> 149 <bitOffset>19</bitOffset> 150 <bitWidth>1</bitWidth> 151 </field> 152 <field> 153 <name>UCAGM</name> 154 <description>UART Clock Auto Gating mode</description> 155 <bitOffset>20</bitOffset> 156 <bitWidth>1</bitWidth> 157 </field> 158 <field> 159 <name>FDM</name> 160 <description>Fractional Division Mode</description> 161 <bitOffset>21</bitOffset> 162 <bitWidth>1</bitWidth> 163 </field> 164 <field> 165 <name>DESM</name> 166 <description>RX Dual Edge Sampling Mode</description> 167 <bitOffset>22</bitOffset> 168 <bitWidth>1</bitWidth> 169 </field> 170 </fields> 171 </register> 172 <register> 173 <name>STATUS</name> 174 <description>Status register</description> 175 <addressOffset>0x0004</addressOffset> 176 <access>read-only</access> 177 <fields> 178 <field> 179 <name>TX_BUSY</name> 180 <description>Read-only flag indicating the UART transmit status</description> 181 <bitOffset>0</bitOffset> 182 <bitWidth>1</bitWidth> 183 </field> 184 <field> 185 <name>RX_BUSY</name> 186 <description>Read-only flag indicating the UART receiver status</description> 187 <bitOffset>1</bitOffset> 188 <bitWidth>1</bitWidth> 189 </field> 190 <field> 191 <name>RX_EM</name> 192 <description>Read-only flag indicating the RX FIFO state</description> 193 <bitOffset>4</bitOffset> 194 <bitWidth>1</bitWidth> 195 </field> 196 <field> 197 <name>RX_FULL</name> 198 <description>Read-only flag indicating the RX FIFO state</description> 199 <bitOffset>5</bitOffset> 200 <bitWidth>1</bitWidth> 201 </field> 202 <field> 203 <name>TX_EM</name> 204 <description>Read-only flag indicating the TX FIFO state</description> 205 <bitOffset>6</bitOffset> 206 <bitWidth>1</bitWidth> 207 </field> 208 <field> 209 <name>TX_FULL</name> 210 <description>Read-only flag indicating the TX FIFO state</description> 211 <bitOffset>7</bitOffset> 212 <bitWidth>1</bitWidth> 213 </field> 214 <field> 215 <name>RX_LVL</name> 216 <description>Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) </description> 217 <bitOffset>8</bitOffset> 218 <bitWidth>4</bitWidth> 219 </field> 220 <field> 221 <name>TX_LVL</name> 222 <description>Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) </description> 223 <bitOffset>12</bitOffset> 224 <bitWidth>4</bitWidth> 225 </field> 226 </fields> 227 </register> 228 <register> 229 <name>INTEN</name> 230 <description>Interrupt Enable control register</description> 231 <addressOffset>0x0008</addressOffset> 232 <fields> 233 <field> 234 <name>RX_FERR</name> 235 <description>Enable Interrupt For RX Frame Error</description> 236 <bitOffset>0</bitOffset> 237 <bitWidth>1</bitWidth> 238 </field> 239 <field> 240 <name>RX_PAR</name> 241 <description>Enable Interrupt For RX Parity Error</description> 242 <bitOffset>1</bitOffset> 243 <bitWidth>1</bitWidth> 244 </field> 245 <field> 246 <name>CTS_EV</name> 247 <description>Enable Interrupt For changeCTS signal change Error</description> 248 <bitOffset>2</bitOffset> 249 <bitWidth>1</bitWidth> 250 </field> 251 <field> 252 <name>RX_OV</name> 253 <description>Enable Interrupt For RX FIFO Overrun Error</description> 254 <bitOffset>3</bitOffset> 255 <bitWidth>1</bitWidth> 256 </field> 257 <field> 258 <name>RX_THD</name> 259 <description>Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD</description> 260 <bitOffset>4</bitOffset> 261 <bitWidth>1</bitWidth> 262 </field> 263 <field> 264 <name>TX_OB</name> 265 <description>Enable Interrupt For TX FIFO has one byte remaning</description> 266 <bitOffset>5</bitOffset> 267 <bitWidth>1</bitWidth> 268 </field> 269 <field> 270 <name>TX_HE</name> 271 <description>Enable Interrupt For TX FIFO has half empty</description> 272 <bitOffset>6</bitOffset> 273 <bitWidth>1</bitWidth> 274 </field> 275 </fields> 276 </register> 277 <register> 278 <name>INTFL</name> 279 <description>Interrupt status flags Control register</description> 280 <addressOffset>0x000C</addressOffset> 281 <fields> 282 <field> 283 <name>RX_FERR</name> 284 <description>Flag for RX Frame Error Interrupt.</description> 285 <bitOffset>0</bitOffset> 286 <bitWidth>1</bitWidth> 287 </field> 288 <field> 289 <name>RX_PAR</name> 290 <description>Flag for RX Parity Error interrupt</description> 291 <bitOffset>1</bitOffset> 292 <bitWidth>1</bitWidth> 293 </field> 294 <field> 295 <name>CTS_EV</name> 296 <description>Flag for CTS signal change interrupt (hardware flow control disabled) </description> 297 <bitOffset>2</bitOffset> 298 <bitWidth>1</bitWidth> 299 </field> 300 <field> 301 <name>RX_OV</name> 302 <description>Flag for RX FIFO Overrun interrupt</description> 303 <bitOffset>3</bitOffset> 304 <bitWidth>1</bitWidth> 305 </field> 306 <field> 307 <name>RX_THD</name> 308 <description>Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field</description> 309 <bitOffset>4</bitOffset> 310 <bitWidth>1</bitWidth> 311 </field> 312 <field> 313 <name>TX_OB</name> 314 <description>Flag for interrupt when TX FIFO has one byte remaining</description> 315 <bitOffset>5</bitOffset> 316 <bitWidth>1</bitWidth> 317 </field> 318 <field> 319 <name>TX_HE</name> 320 <description>Flag for interrupt when TX FIFO is half empty</description> 321 <bitOffset>6</bitOffset> 322 <bitWidth>1</bitWidth> 323 </field> 324 </fields> 325 </register> 326 <register> 327 <name>CLKDIV</name> 328 <description>Clock Divider register</description> 329 <addressOffset>0x0010</addressOffset> 330 <fields> 331 <field> 332 <name>CLKDIV</name> 333 <description>Baud rate divisor value</description> 334 <bitOffset>0</bitOffset> 335 <bitWidth>20</bitWidth> 336 </field> 337 </fields> 338 </register> 339 <register> 340 <name>OSR</name> 341 <description>Over Sampling Rate register</description> 342 <addressOffset>0x0014</addressOffset> 343 <fields> 344 <field> 345 <name>OSR</name> 346 <description>OSR</description> 347 <bitOffset>0</bitOffset> 348 <bitWidth>3</bitWidth> 349 </field> 350 </fields> 351 </register> 352 <register> 353 <name>TXPEEK</name> 354 <description>TX FIFO Output Peek register</description> 355 <addressOffset>0x0018</addressOffset> 356 <fields> 357 <field> 358 <name>DATA</name> 359 <description>Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field.</description> 360 <bitOffset>0</bitOffset> 361 <bitWidth>8</bitWidth> 362 </field> 363 </fields> 364 </register> 365 <register> 366 <name>PNR</name> 367 <description> Pin register</description> 368 <addressOffset>0x001C</addressOffset> 369 <fields> 370 <field> 371 <name>CTS</name> 372 <description>Current sampled value of CTS IO</description> 373 <bitOffset>0</bitOffset> 374 <bitWidth>1</bitWidth> 375 <access>read-only</access> 376 </field> 377 <field> 378 <name>RTS</name> 379 <description>This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.</description> 380 <bitOffset>1</bitOffset> 381 <bitWidth>1</bitWidth> 382 </field> 383 </fields> 384 </register> 385 <register> 386 <name>FIFO</name> 387 <description>FIFO Read/Write register</description> 388 <addressOffset>0x0020</addressOffset> 389 <fields> 390 <field> 391 <name>DATA</name> 392 <description>Load/unload location for TX and RX FIFO buffers.</description> 393 <bitOffset>0</bitOffset> 394 <bitWidth>8</bitWidth> 395 </field> 396 <field> 397 <name>RX_PAR</name> 398 <description>Parity error flag for next byte to be read from FIFO.</description> 399 <bitOffset>8</bitOffset> 400 <bitWidth>1</bitWidth> 401 </field> 402 </fields> 403 </register> 404 <register> 405 <name>DMA</name> 406 <description>DMA Configuration register</description> 407 <addressOffset>0x0030</addressOffset> 408 <fields> 409 <field> 410 <name>TX_THD_VAL</name> 411 <description>TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory.</description> 412 <bitOffset>0</bitOffset> 413 <bitWidth>4</bitWidth> 414 </field> 415 <field> 416 <name>TX_EN</name> 417 <description>TX DMA channel enable</description> 418 <bitOffset>4</bitOffset> 419 <bitWidth>1</bitWidth> 420 </field> 421 <field> 422 <name>RX_THD_VAL</name> 423 <description>Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory.</description> 424 <bitOffset>5</bitOffset> 425 <bitWidth>4</bitWidth> 426 </field> 427 <field> 428 <name>RX_EN</name> 429 <description>RX DMA channel enable</description> 430 <bitOffset>9</bitOffset> 431 <bitWidth>1</bitWidth> 432 </field> 433 </fields> 434 </register> 435 <register> 436 <name>WKEN</name> 437 <description>Wake up enable Control register</description> 438 <addressOffset>0x0034</addressOffset> 439 <fields> 440 <field> 441 <name>RX_NE</name> 442 <description>Wake-Up Enable for RX FIFO Not Empty</description> 443 <bitOffset>0</bitOffset> 444 <bitWidth>1</bitWidth> 445 </field> 446 <field> 447 <name>RX_FULL</name> 448 <description>Wake-Up Enable for RX FIFO Full</description> 449 <bitOffset>1</bitOffset> 450 <bitWidth>1</bitWidth> 451 </field> 452 <field> 453 <name>RX_THD</name> 454 <description>Wake-Up Enable for RX FIFO Threshold Met</description> 455 <bitOffset>2</bitOffset> 456 <bitWidth>1</bitWidth> 457 </field> 458 </fields> 459 </register> 460 <register> 461 <name>WKFL</name> 462 <description>Wake up Flags register</description> 463 <addressOffset>0x0038</addressOffset> 464 <fields> 465 <field> 466 <name>RX_NE</name> 467 <description>Wake-Up Flag for RX FIFO Not Empty</description> 468 <bitOffset>0</bitOffset> 469 <bitWidth>1</bitWidth> 470 </field> 471 <field> 472 <name>RX_FULL</name> 473 <description>Wake-Up Flag for RX FIFO Full</description> 474 <bitOffset>1</bitOffset> 475 <bitWidth>1</bitWidth> 476 </field> 477 <field> 478 <name>RX_THD</name> 479 <description>Wake-Up Flag for RX FIFO Threshold Met</description> 480 <bitOffset>2</bitOffset> 481 <bitWidth>1</bitWidth> 482 </field> 483 </fields> 484 </register> 485 </registers> 486 </peripheral> 487 <!-- uart: Uart low power Registers--> 488</device>
