1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>UART0</name> 5 <description>UART</description> 6 <baseAddress>0x40042000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>UART0</name> 14 <description>UART0 IRQ</description> 15 <value>14</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CTRL0</name> 20 <description>Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <size>32</size> 23 <fields> 24 <field> 25 <name>ENABLE</name> 26 <description>UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>dis</name> 32 <description>UART disabled. FIFOs are flushed. Clock is gated off for power savings. </description> 33 <value>0</value> 34 </enumeratedValue> 35 <enumeratedValue> 36 <name>en</name> 37 <description>UART enabled. </description> 38 <value>1</value> 39 </enumeratedValue> 40 </enumeratedValues> 41 </field> 42 <field> 43 <name>PARITY_EN</name> 44 <description>Enable/disable Parity bit (9th character).</description> 45 <bitOffset>1</bitOffset> 46 <bitWidth>1</bitWidth> 47 <enumeratedValues> 48 <enumeratedValue> 49 <name>dis</name> 50 <description>No Parity </description> 51 <value>0</value> 52 </enumeratedValue> 53 <enumeratedValue> 54 <name>en</name> 55 <description>Parity enabled as 9th bit</description> 56 <value>1</value> 57 </enumeratedValue> 58 </enumeratedValues> 59 </field> 60 <field> 61 <name>PARITY_MODE</name> 62 <description>When PARITY_EN=1, selects odd, even, Mark or Space parity. 63 Mark parity = always 1; Space parity = always 0.</description> 64 <bitOffset>2</bitOffset> 65 <bitWidth>2</bitWidth> 66 <enumeratedValues> 67 <enumeratedValue> 68 <name>Even</name> 69 <description>Even parity selected.</description> 70 <value>0</value> 71 </enumeratedValue> 72 <enumeratedValue> 73 <name>ODD</name> 74 <description>Odd parity selected.</description> 75 <value>1</value> 76 </enumeratedValue> 77 <enumeratedValue> 78 <name>MARK</name> 79 <description>Mark parity selected.</description> 80 <value>2</value> 81 </enumeratedValue> 82 <enumeratedValue> 83 <name>SPACE</name> 84 <description>Space parity selected.</description> 85 <value>3</value> 86 </enumeratedValue> 87 </enumeratedValues> 88 </field> 89 <field> 90 <name>PARITY_LVL</name> 91 <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description> 92 <bitOffset>4</bitOffset> 93 <bitWidth>1</bitWidth> 94 <enumeratedValues> 95 <enumeratedValue> 96 <name>1</name> 97 <description>Parity calculation is based on number of 1s in frame.</description> 98 <value>0</value> 99 </enumeratedValue> 100 <enumeratedValue> 101 <name>0</name> 102 <description>Parity calculation is based on number of 0s in frame.</description> 103 <value>1</value> 104 </enumeratedValue> 105 </enumeratedValues> 106 </field> 107 <field> 108 <name>TXFLUSH</name> 109 <description>Flushes the TX FIFO buffer.</description> 110 <bitOffset>5</bitOffset> 111 <bitWidth>1</bitWidth> 112 </field> 113 <field> 114 <name>RXFLUSH</name> 115 <description>Flushes the RX FIFO buffer.</description> 116 <bitOffset>6</bitOffset> 117 <bitWidth>1</bitWidth> 118 </field> 119 <field> 120 <name>BITACC</name> 121 <description>If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.</description> 122 <bitOffset>7</bitOffset> 123 <bitWidth>1</bitWidth> 124 <enumeratedValues> 125 <enumeratedValue> 126 <name>FRAME</name> 127 <description>Frame accuracy.</description> 128 <value>0</value> 129 </enumeratedValue> 130 <enumeratedValue> 131 <name>BIT</name> 132 <description>Bit accuracy.</description> 133 <value>1</value> 134 </enumeratedValue> 135 </enumeratedValues> 136 </field> 137 <field> 138 <name>SIZE</name> 139 <description>Selects UART character size.</description> 140 <bitOffset>8</bitOffset> 141 <bitWidth>2</bitWidth> 142 <enumeratedValues> 143 <enumeratedValue> 144 <name>5</name> 145 <description>5 bits.</description> 146 <value>0</value> 147 </enumeratedValue> 148 <enumeratedValue> 149 <name>6</name> 150 <description>6 bits.</description> 151 <value>1</value> 152 </enumeratedValue> 153 <enumeratedValue> 154 <name>7</name> 155 <description>7 bits.</description> 156 <value>2</value> 157 </enumeratedValue> 158 <enumeratedValue> 159 <name>8</name> 160 <description>8 bits.</description> 161 <value>3</value> 162 </enumeratedValue> 163 </enumeratedValues> 164 </field> 165 <field> 166 <name>STOP</name> 167 <description>Selects the number of stop bits that will be generated.</description> 168 <bitOffset>10</bitOffset> 169 <bitWidth>1</bitWidth> 170 <enumeratedValues> 171 <enumeratedValue> 172 <name>1</name> 173 <description>1 stop bit.</description> 174 <value>0</value> 175 </enumeratedValue> 176 <enumeratedValue> 177 <name>1_5</name> 178 <description>1.5 stop bits.</description> 179 <value>1</value> 180 </enumeratedValue> 181 </enumeratedValues> 182 </field> 183 <field> 184 <name>FLOW</name> 185 <description>Enables/disables hardware flow control.</description> 186 <bitOffset>11</bitOffset> 187 <bitWidth>1</bitWidth> 188 <enumeratedValues> 189 <enumeratedValue> 190 <name>en</name> 191 <description>HW Flow Control with RTS/CTS enabled</description> 192 <value>1</value> 193 </enumeratedValue> 194 <enumeratedValue> 195 <name>dis</name> 196 <description>HW Flow Control disabled</description> 197 <value>0</value> 198 </enumeratedValue> 199 </enumeratedValues> 200 </field> 201 <field> 202 <name>FLOWPOL</name> 203 <description>RTS/CTS polarity.</description> 204 <bitOffset>12</bitOffset> 205 <bitWidth>1</bitWidth> 206 <enumeratedValues> 207 <enumeratedValue> 208 <name>0</name> 209 <description>RTS/CTS asserted is logic 0.</description> 210 <value>0</value> 211 </enumeratedValue> 212 <enumeratedValue> 213 <name>1</name> 214 <description>RTS/CTS asserted is logic 1.</description> 215 <value>1</value> 216 </enumeratedValue> 217 </enumeratedValues> 218 </field> 219 <field> 220 <name>NULLMOD</name> 221 <description>NULL Modem Support (RTS/CTS and TXD/RXD swap).</description> 222 <bitOffset>13</bitOffset> 223 <bitWidth>1</bitWidth> 224 <enumeratedValues> 225 <enumeratedValue> 226 <name>DIS</name> 227 <description>Direct convention.</description> 228 <value>0</value> 229 </enumeratedValue> 230 <enumeratedValue> 231 <name>EN</name> 232 <description>Null Modem Mode.</description> 233 <value>1</value> 234 </enumeratedValue> 235 </enumeratedValues> 236 </field> 237 <field> 238 <name>BREAK</name> 239 <description>Break control bit. It causes a break condition to be transmitted to receiving UART.</description> 240 <bitOffset>14</bitOffset> 241 <bitWidth>1</bitWidth> 242 <enumeratedValues> 243 <enumeratedValue> 244 <name>DIS</name> 245 <description>Break characters are not generated.</description> 246 <value>0</value> 247 </enumeratedValue> 248 <enumeratedValue> 249 <name>EN</name> 250 <description>Break characters are sent(all the bits are at '0' including start/parity/stop).</description> 251 <value>1</value> 252 </enumeratedValue> 253 </enumeratedValues> 254 </field> 255 <field> 256 <name>CLK_SEL</name> 257 <description>Baud Rate Clock Source Select. Selects the baud rate clock.</description> 258 <bitOffset>15</bitOffset> 259 <bitWidth>1</bitWidth> 260 <enumeratedValues> 261 <enumeratedValue> 262 <name>SYSTEM</name> 263 <description>System clock.</description> 264 <value>0</value> 265 </enumeratedValue> 266 <enumeratedValue> 267 <name>ALTERNATE</name> 268 <description>Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.</description> 269 <value>1</value> 270 </enumeratedValue> 271 </enumeratedValues> 272 </field> 273 <field> 274 <name>TO_CNT</name> 275 <description>RX Time Out. RX time out interrupt will occur after RXTO Uart 276 characters if RX-FIFO is not empty and RX FIFO has not been read.</description> 277 <bitOffset>16</bitOffset> 278 <bitWidth>8</bitWidth> 279 </field> 280 </fields> 281 </register> 282 <register> 283 <name>CTRL1</name> 284 <description>Threshold Control register.</description> 285 <addressOffset>0x04</addressOffset> 286 <size>32</size> 287 <fields> 288 <field> 289 <name>RX_FIFO_LVL</name> 290 <description>RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.</description> 291 <bitOffset>0</bitOffset> 292 <bitWidth>6</bitWidth> 293 </field> 294 <field> 295 <name>TX_FIFO_LVL</name> 296 <description>TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.</description> 297 <bitOffset>8</bitOffset> 298 <bitWidth>6</bitWidth> 299 </field> 300 <field> 301 <name>RTS_FIFO_LVL</name> 302 <description>RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.</description> 303 <bitOffset>16</bitOffset> 304 <bitWidth>6</bitWidth> 305 </field> 306 </fields> 307 </register> 308 <register> 309 <name>STAT</name> 310 <description>Status Register.</description> 311 <addressOffset>0x08</addressOffset> 312 <size>32</size> 313 <access>read-only</access> 314 <fields> 315 <field> 316 <name>TX_BUSY</name> 317 <description>Read-only flag indicating the UART transmit status.</description> 318 <bitOffset>0</bitOffset> 319 <bitWidth>1</bitWidth> 320 <access>read-only</access> 321 </field> 322 <field> 323 <name>RX_BUSY</name> 324 <description>Read-only flag indicating the UARTreceiver status.</description> 325 <bitOffset>1</bitOffset> 326 <bitWidth>1</bitWidth> 327 <access>read-only</access> 328 </field> 329 <field> 330 <name>PARITY</name> 331 <description>9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.</description> 332 <bitOffset>2</bitOffset> 333 <bitWidth>1</bitWidth> 334 <access>read-only</access> 335 </field> 336 <field> 337 <name>BREAK</name> 338 <description>Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).</description> 339 <bitOffset>3</bitOffset> 340 <bitWidth>1</bitWidth> 341 <access>read-only</access> 342 </field> 343 <field> 344 <name>RX_EMPTY</name> 345 <description>Read-only flag indicating the RX FIFO state.</description> 346 <bitOffset>4</bitOffset> 347 <bitWidth>1</bitWidth> 348 <access>read-only</access> 349 </field> 350 <field> 351 <name>RX_FULL</name> 352 <description>Read-only flag indicating the RX FIFO state.</description> 353 <bitOffset>5</bitOffset> 354 <bitWidth>1</bitWidth> 355 <access>read-only</access> 356 </field> 357 <field> 358 <name>TX_EMPTY</name> 359 <description>Read-only flag indicating the TX FIFO state.</description> 360 <bitOffset>6</bitOffset> 361 <bitWidth>1</bitWidth> 362 <access>read-only</access> 363 </field> 364 <field> 365 <name>TX_FULL</name> 366 <description>Read-only flag indicating the TX FIFO state.</description> 367 <bitOffset>7</bitOffset> 368 <bitWidth>1</bitWidth> 369 <access>read-only</access> 370 </field> 371 <field> 372 <name>RX_NUM</name> 373 <description>Indicates the number of bytes currently in the RX FIFO.</description> 374 <bitOffset>8</bitOffset> 375 <bitWidth>6</bitWidth> 376 <access>read-only</access> 377 </field> 378 <field> 379 <name>TX_NUM</name> 380 <description>Indicates the number of bytes currently in the TX FIFO.</description> 381 <bitOffset>16</bitOffset> 382 <bitWidth>6</bitWidth> 383 <access>read-only</access> 384 </field> 385 <field> 386 <name>RX_TO</name> 387 <description>RX Timeout status.</description> 388 <bitOffset>24</bitOffset> 389 <bitWidth>1</bitWidth> 390 <access>read-only</access> 391 </field> 392 </fields> 393 </register> 394 <register> 395 <name>INT_EN</name> 396 <description>Interrupt Enable Register.</description> 397 <addressOffset>0x0C</addressOffset> 398 <size>32</size> 399 <fields> 400 <field> 401 <name>RX_FRAME_ERROR</name> 402 <description>Enable for RX Frame Error Interrupt.</description> 403 <bitOffset>0</bitOffset> 404 <bitWidth>1</bitWidth> 405 </field> 406 <field> 407 <name>RX_PARITY_ERROR</name> 408 <description>Enable for RX Parity Error interrupt.</description> 409 <bitOffset>1</bitOffset> 410 <bitWidth>1</bitWidth> 411 </field> 412 <field> 413 <name>CTS</name> 414 <description>Enable for CTS signal change interrupt.</description> 415 <bitOffset>2</bitOffset> 416 <bitWidth>1</bitWidth> 417 </field> 418 <field> 419 <name>RX_OVERRUN</name> 420 <description>Enable for RX FIFO OVerrun interrupt.</description> 421 <bitOffset>3</bitOffset> 422 <bitWidth>1</bitWidth> 423 </field> 424 <field> 425 <name>RX_FIFO_LVL</name> 426 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 427 <bitOffset>4</bitOffset> 428 <bitWidth>1</bitWidth> 429 </field> 430 <field> 431 <name>TX_FIFO_AE</name> 432 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 433 <bitOffset>5</bitOffset> 434 <bitWidth>1</bitWidth> 435 </field> 436 <field> 437 <name>TX_FIFO_LVL</name> 438 <description>Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 439 <bitOffset>6</bitOffset> 440 <bitWidth>1</bitWidth> 441 </field> 442 <field> 443 <name>BREAK</name> 444 <description>Enable for received BREAK character interrupt.</description> 445 <bitOffset>7</bitOffset> 446 <bitWidth>1</bitWidth> 447 </field> 448 <field> 449 <name>RX_TO</name> 450 <description>Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 451 <bitOffset>8</bitOffset> 452 <bitWidth>1</bitWidth> 453 </field> 454 <field> 455 <name>LAST_BREAK</name> 456 <description>Enable for Last break character interrupt.</description> 457 <bitOffset>9</bitOffset> 458 <bitWidth>1</bitWidth> 459 </field> 460 </fields> 461 </register> 462 <register> 463 <name>INT_FL</name> 464 <description>Interrupt Status Flags.</description> 465 <addressOffset>0x10</addressOffset> 466 <size>32</size> 467 <modifiedWriteValues>oneToClear</modifiedWriteValues> 468 <fields> 469 <field> 470 <name>FRAME</name> 471 <description>FLAG for RX Frame Error Interrupt.</description> 472 <bitOffset>0</bitOffset> 473 <bitWidth>1</bitWidth> 474 </field> 475 <field> 476 <name>PARITY</name> 477 <description>FLAG for RX Parity Error interrupt.</description> 478 <bitOffset>1</bitOffset> 479 <bitWidth>1</bitWidth> 480 </field> 481 <field> 482 <name>CTS</name> 483 <description>FLAG for CTS signal change interrupt.</description> 484 <bitOffset>2</bitOffset> 485 <bitWidth>1</bitWidth> 486 </field> 487 <field> 488 <name>RX_OVR</name> 489 <description>FLAG for RX FIFO Overrun interrupt.</description> 490 <bitOffset>3</bitOffset> 491 <bitWidth>1</bitWidth> 492 </field> 493 <field> 494 <name>RX_FIFO_LVL</name> 495 <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 496 <bitOffset>4</bitOffset> 497 <bitWidth>1</bitWidth> 498 </field> 499 <field> 500 <name>TX_FIFO_AE</name> 501 <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description> 502 <bitOffset>5</bitOffset> 503 <bitWidth>1</bitWidth> 504 </field> 505 <field> 506 <name>TX_FIFO_LVL</name> 507 <description>FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 508 <bitOffset>6</bitOffset> 509 <bitWidth>1</bitWidth> 510 </field> 511 <field> 512 <name>BREAK</name> 513 <description>FLAG for received BREAK character interrupt.</description> 514 <bitOffset>7</bitOffset> 515 <bitWidth>1</bitWidth> 516 </field> 517 <field> 518 <name>RX_TO</name> 519 <description>FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 520 <bitOffset>8</bitOffset> 521 <bitWidth>1</bitWidth> 522 </field> 523 <field> 524 <name>LAST_BREAK</name> 525 <description>FLAG for Last break character interrupt.</description> 526 <bitOffset>9</bitOffset> 527 <bitWidth>1</bitWidth> 528 </field> 529 </fields> 530 </register> 531 <register> 532 <name>BAUD0</name> 533 <description>Baud rate register. Integer portion.</description> 534 <addressOffset>0x14</addressOffset> 535 <size>32</size> 536 <fields> 537 <field> 538 <name>IBAUD</name> 539 <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description> 540 <bitOffset>0</bitOffset> 541 <bitWidth>12</bitWidth> 542 </field> 543 <field> 544 <name>CLKDIV</name> 545 <description>FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.</description> 546 <bitOffset>16</bitOffset> 547 <bitWidth>3</bitWidth> 548 <enumeratedValues> 549 <enumeratedValue> 550 <name>128</name> 551 <description>Baud Factor 128</description> 552 <value>0</value> 553 </enumeratedValue> 554 <enumeratedValue> 555 <name>64</name> 556 <description>Baud Factor 64</description> 557 <value>1</value> 558 </enumeratedValue> 559 <enumeratedValue> 560 <name>32</name> 561 <description>Baud Factor 32</description> 562 <value>2</value> 563 </enumeratedValue> 564 <enumeratedValue> 565 <name>16</name> 566 <description>Baud Factor 16</description> 567 <value>3</value> 568 </enumeratedValue> 569 <enumeratedValue> 570 <name>8</name> 571 <description>Baud Factor 8</description> 572 <value>4</value> 573 </enumeratedValue> 574 </enumeratedValues> 575 </field> 576 </fields> 577 </register> 578 <register> 579 <name>BAUD1</name> 580 <description>Baud rate register. Decimal Setting.</description> 581 <addressOffset>0x18</addressOffset> 582 <size>32</size> 583 <fields> 584 <field> 585 <name>DBAUD</name> 586 <description>Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.</description> 587 <bitOffset>0</bitOffset> 588 <bitWidth>12</bitWidth> 589 </field> 590 </fields> 591 </register> 592 <register> 593 <name>FIFO</name> 594 <description>FIFO Data buffer.</description> 595 <addressOffset>0x1C</addressOffset> 596 <size>32</size> 597 <fields> 598 <field> 599 <name>FIFO</name> 600 <description>Load/unload location for TX and RX FIFO buffers.</description> 601 <bitOffset>0</bitOffset> 602 <bitWidth>8</bitWidth> 603 </field> 604 </fields> 605 </register> 606 <register> 607 <name>DMA</name> 608 <description>DMA Configuration.</description> 609 <addressOffset>0x20</addressOffset> 610 <size>32</size> 611 <fields> 612 <field> 613 <name>TXDMA_EN</name> 614 <description>TX DMA channel enable.</description> 615 <bitOffset>0</bitOffset> 616 <bitWidth>1</bitWidth> 617 <enumeratedValues> 618 <enumeratedValue> 619 <name>dis</name> 620 <description>DMA is disabled </description> 621 <value>0</value> 622 </enumeratedValue> 623 <enumeratedValue> 624 <name>en</name> 625 <description>DMA is enabled </description> 626 <value>1</value> 627 </enumeratedValue> 628 </enumeratedValues> 629 </field> 630 <field> 631 <name>RXDMA_EN</name> 632 <description>RX DMA channel enable.</description> 633 <bitOffset>1</bitOffset> 634 <bitWidth>1</bitWidth> 635 <enumeratedValues> 636 <enumeratedValue> 637 <name>dis</name> 638 <description>DMA is disabled </description> 639 <value>0</value> 640 </enumeratedValue> 641 <enumeratedValue> 642 <name>en</name> 643 <description>DMA is enabled </description> 644 <value>1</value> 645 </enumeratedValue> 646 </enumeratedValues> 647 </field> 648 <field> 649 <name>TXDMA_LVL</name> 650 <description>TX threshold for DMA transmission.</description> 651 <bitOffset>8</bitOffset> 652 <bitWidth>6</bitWidth> 653 </field> 654 <field> 655 <name>RXDMA_LVL</name> 656 <description>RX threshold for DMA transmission.</description> 657 <bitOffset>16</bitOffset> 658 <bitWidth>6</bitWidth> 659 </field> 660 </fields> 661 </register> 662 <register> 663 <name>TXFIFO</name> 664 <description>Transmit FIFO Status register.</description> 665 <addressOffset>0x24</addressOffset> 666 <size>32</size> 667 <fields> 668 <field> 669 <name>DATA</name> 670 <description>Reading from this field returns the next character available at the 671 output of the TX FIFO (if one is available, otherwise 00h is returned).</description> 672 <bitOffset>0</bitOffset> 673 <bitWidth>7</bitWidth> 674 </field> 675 </fields> 676 </register> 677 </registers> 678 </peripheral> 679 <!-- UART: UART --> 680</device>
