1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>UART0</name> 5 <description>UART</description> 6 <baseAddress>0x40042000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>UART0</name> 14 <description>UART0 IRQ</description> 15 <value>14</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CTRL0</name> 20 <description>Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <size>32</size> 23 <fields> 24 <field> 25 <name>ENABLE</name> 26 <description>UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>dis</name> 32 <description>UART disabled. FIFOs are flushed. Clock is gated off for power savings. </description> 33 <value>0</value> 34 </enumeratedValue> 35 <enumeratedValue> 36 <name>en</name> 37 <description>UART enabled. </description> 38 <value>1</value> 39 </enumeratedValue> 40 </enumeratedValues> 41 </field> 42 <field> 43 <name>PARITY_EN</name> 44 <description>Enable/disable Parity bit (9th character).</description> 45 <bitOffset>1</bitOffset> 46 <bitWidth>1</bitWidth> 47 <enumeratedValues> 48 <enumeratedValue> 49 <name>dis</name> 50 <description>No Parity </description> 51 <value>0</value> 52 </enumeratedValue> 53 <enumeratedValue> 54 <name>en</name> 55 <description>Parity enabled as 9th bit</description> 56 <value>1</value> 57 </enumeratedValue> 58 </enumeratedValues> 59 </field> 60 <field> 61 <name>PARITY_MODE</name> 62 <description>When PARITY_EN=1, selects odd, even, Mark or Space parity. 63 Mark parity = always 1; 64 65 Space parity = always 0.</description> 66 <bitOffset>2</bitOffset> 67 <bitWidth>2</bitWidth> 68 <enumeratedValues> 69 <enumeratedValue> 70 <name>even</name> 71 <description>Even parity selected.</description> 72 <value>0</value> 73 </enumeratedValue> 74 <enumeratedValue> 75 <name>odd</name> 76 <description>Odd parity selected.</description> 77 <value>1</value> 78 </enumeratedValue> 79 <enumeratedValue> 80 <name>mark</name> 81 <description>Mark parity selected.</description> 82 <value>2</value> 83 </enumeratedValue> 84 <enumeratedValue> 85 <name>space</name> 86 <description>Space parity selected.</description> 87 <value>3</value> 88 </enumeratedValue> 89 </enumeratedValues> 90 </field> 91 <field> 92 <name>PARITY_LVL</name> 93 <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description> 94 <bitOffset>4</bitOffset> 95 <bitWidth>1</bitWidth> 96 <enumeratedValues> 97 <enumeratedValue> 98 <name>ZERO</name> 99 <description>Parity calculation is based on number of 0s in frame.</description> 100 <value>0</value> 101 </enumeratedValue> 102 <enumeratedValue> 103 <name>ONE</name> 104 <description>Parity calculation is based on number of 1s in frame.</description> 105 <value>1</value> 106 </enumeratedValue> 107 </enumeratedValues> 108 </field> 109 <field> 110 <name>TXFLUSH</name> 111 <description>Flushes the TX FIFO buffer.</description> 112 <bitOffset>5</bitOffset> 113 <bitWidth>1</bitWidth> 114 <enumeratedValues> 115 <enumeratedValue> 116 <name>nop</name> 117 <description>No flush operation in progress/no effect.</description> 118 <value>0</value> 119 </enumeratedValue> 120 <enumeratedValue> 121 <name>flush</name> 122 <description>TX FIFO flush initiation or flush operation currently in progress.</description> 123 <value>1</value> 124 </enumeratedValue> 125 </enumeratedValues> 126 </field> 127 <field> 128 <name>RXFLUSH</name> 129 <description>Flushes the RX FIFO buffer.</description> 130 <bitOffset>6</bitOffset> 131 <bitWidth>1</bitWidth> 132 <enumeratedValues> 133 <enumeratedValue> 134 <name>nop</name> 135 <description>No flush operation in progress/no effect.</description> 136 <value>0</value> 137 </enumeratedValue> 138 <enumeratedValue> 139 <name>flush</name> 140 <description>RX FIFO flush initiation or flush operation currently in progress.</description> 141 <value>1</value> 142 </enumeratedValue> 143 </enumeratedValues> 144 </field> 145 <field> 146 <name>BITACC</name> 147 <description>If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.</description> 148 <bitOffset>7</bitOffset> 149 <bitWidth>1</bitWidth> 150 <enumeratedValues> 151 <enumeratedValue> 152 <name>frame</name> 153 <description>Frame accuracy.</description> 154 <value>0</value> 155 </enumeratedValue> 156 <enumeratedValue> 157 <name>bit</name> 158 <description>Bit accuracy.</description> 159 <value>1</value> 160 </enumeratedValue> 161 </enumeratedValues> 162 </field> 163 <field> 164 <name>SIZE</name> 165 <description>Selects UART character size.</description> 166 <bitOffset>8</bitOffset> 167 <bitWidth>2</bitWidth> 168 <enumeratedValues> 169 <enumeratedValue> 170 <name>5bit_data</name> 171 <description>5 bits.</description> 172 <value>0</value> 173 </enumeratedValue> 174 <enumeratedValue> 175 <name>6bit_data</name> 176 <description>6 bits.</description> 177 <value>1</value> 178 </enumeratedValue> 179 <enumeratedValue> 180 <name>7bit_data</name> 181 <description>7 bits.</description> 182 <value>2</value> 183 </enumeratedValue> 184 <enumeratedValue> 185 <name>8bit_data</name> 186 <description>8 bits.</description> 187 <value>3</value> 188 </enumeratedValue> 189 </enumeratedValues> 190 </field> 191 <field> 192 <name>STOP</name> 193 <description>Selects the number of stop bits that will be generated.</description> 194 <bitOffset>10</bitOffset> 195 <bitWidth>1</bitWidth> 196 <enumeratedValues> 197 <enumeratedValue> 198 <name>1_stopbits</name> 199 <description>1 stop bit.</description> 200 <value>0</value> 201 </enumeratedValue> 202 <enumeratedValue> 203 <name>2_stopbits</name> 204 <description>1.5 stop bits if the character size is 5, 2 stop bits for all other character sizes.</description> 205 <value>1</value> 206 </enumeratedValue> 207 </enumeratedValues> 208 </field> 209 <field> 210 <name>FLOW</name> 211 <description>Enables/disables hardware flow control.</description> 212 <bitOffset>11</bitOffset> 213 <bitWidth>1</bitWidth> 214 <enumeratedValues> 215 <enumeratedValue> 216 <name>dis</name> 217 <description>HW Flow Control disabled</description> 218 <value>0</value> 219 </enumeratedValue> 220 <enumeratedValue> 221 <name>en</name> 222 <description>HW Flow Control with RTS/CTS enabled</description> 223 <value>1</value> 224 </enumeratedValue> 225 </enumeratedValues> 226 </field> 227 <field> 228 <name>FLOWPOL</name> 229 <description>RTS/CTS polarity.</description> 230 <bitOffset>12</bitOffset> 231 <bitWidth>1</bitWidth> 232 <enumeratedValues> 233 <enumeratedValue> 234 <name>active_low</name> 235 <description>RTS/CTS asserted is logic 0.</description> 236 <value>0</value> 237 </enumeratedValue> 238 <enumeratedValue> 239 <name>active_high</name> 240 <description>RTS/CTS asserted is logic 1.</description> 241 <value>1</value> 242 </enumeratedValue> 243 </enumeratedValues> 244 </field> 245 <field> 246 <name>NULLMOD</name> 247 <description>NULL Modem Support (RTS/CTS and TXD/RXD swap).</description> 248 <bitOffset>13</bitOffset> 249 <bitWidth>1</bitWidth> 250 <enumeratedValues> 251 <enumeratedValue> 252 <name>normal</name> 253 <description>Direct convention.</description> 254 <value>0</value> 255 </enumeratedValue> 256 <enumeratedValue> 257 <name>swapped</name> 258 <description>Null Modem Mode. RTS/CTS swapped and TX/RX swapped.</description> 259 <value>1</value> 260 </enumeratedValue> 261 </enumeratedValues> 262 </field> 263 <field> 264 <name>BREAK</name> 265 <description>Break control bit. It causes a break condition to be transmitted to receiving UART.</description> 266 <bitOffset>14</bitOffset> 267 <bitWidth>1</bitWidth> 268 <enumeratedValues> 269 <enumeratedValue> 270 <name>normal</name> 271 <description>Break characters are not generated.</description> 272 <value>0</value> 273 </enumeratedValue> 274 <enumeratedValue> 275 <name>break</name> 276 <description>Break characters are sent (all the bits are at '0' including start/parity/stop).</description> 277 <value>1</value> 278 </enumeratedValue> 279 </enumeratedValues> 280 </field> 281 <field> 282 <name>CLK_SEL</name> 283 <description>Baud Rate Clock Source Select. Selects the baud rate clock.</description> 284 <bitOffset>15</bitOffset> 285 <bitWidth>1</bitWidth> 286 <enumeratedValues> 287 <enumeratedValue> 288 <name>periph_clk</name> 289 <description>System clock.</description> 290 <value>0</value> 291 </enumeratedValue> 292 <enumeratedValue> 293 <name>alt_clk</name> 294 <description>Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.</description> 295 <value>1</value> 296 </enumeratedValue> 297 </enumeratedValues> 298 </field> 299 <field> 300 <name>TO_CNT</name> 301 <description>RX Time Out. RX time out interrupt will occur after TO_CNT Uart 302 characters if RX-FIFO is not empty and RX FIFO has not been read.</description> 303 <bitOffset>16</bitOffset> 304 <bitWidth>8</bitWidth> 305 </field> 306 </fields> 307 </register> 308 <register> 309 <name>CTRL1</name> 310 <description>Threshold Control register.</description> 311 <addressOffset>0x04</addressOffset> 312 <size>32</size> 313 <fields> 314 <field> 315 <name>RX_FIFO_LVL</name> 316 <description>RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.</description> 317 <bitOffset>0</bitOffset> 318 <bitWidth>6</bitWidth> 319 </field> 320 <field> 321 <name>TX_FIFO_LVL</name> 322 <description>TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.</description> 323 <bitOffset>8</bitOffset> 324 <bitWidth>6</bitWidth> 325 </field> 326 <field> 327 <name>RTS_FIFO_LVL</name> 328 <description>RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.</description> 329 <bitOffset>16</bitOffset> 330 <bitWidth>6</bitWidth> 331 </field> 332 </fields> 333 </register> 334 <register> 335 <name>STAT</name> 336 <description>Status Register.</description> 337 <addressOffset>0x08</addressOffset> 338 <size>32</size> 339 <access>read-only</access> 340 <fields> 341 <field> 342 <name>TX_BUSY</name> 343 <description>Read-only flag indicating the UART transmit status.</description> 344 <bitOffset>0</bitOffset> 345 <bitWidth>1</bitWidth> 346 <access>read-only</access> 347 <enumeratedValues> 348 <enumeratedValue> 349 <name>idle</name> 350 <description>The UART block is not currently transmitting chracters.</description> 351 <value>0</value> 352 </enumeratedValue> 353 <enumeratedValue> 354 <name>busy</name> 355 <description>UART block currently transmitting chracters.</description> 356 <value>1</value> 357 </enumeratedValue> 358 </enumeratedValues> 359 </field> 360 <field> 361 <name>RX_BUSY</name> 362 <description>Read-only flag indicating the UARTreceiver status.</description> 363 <bitOffset>1</bitOffset> 364 <bitWidth>1</bitWidth> 365 <access>read-only</access> 366 <enumeratedValues> 367 <enumeratedValue> 368 <name>idle</name> 369 <description>The UART block is not currently receiving chracters.</description> 370 <value>0</value> 371 </enumeratedValue> 372 <enumeratedValue> 373 <name>busy</name> 374 <description>UART block currently receiving chracters.</description> 375 <value>1</value> 376 </enumeratedValue> 377 </enumeratedValues> 378 </field> 379 <field> 380 <name>PARITY</name> 381 <description>9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.</description> 382 <bitOffset>2</bitOffset> 383 <bitWidth>1</bitWidth> 384 <access>read-only</access> 385 <enumeratedValues> 386 <enumeratedValue> 387 <name>0</name> 388 <description>Received a parity bit of 0.</description> 389 <value>0</value> 390 </enumeratedValue> 391 <enumeratedValue> 392 <name>1</name> 393 <description>Received a parity bit of 1.</description> 394 <value>1</value> 395 </enumeratedValue> 396 </enumeratedValues> 397 </field> 398 <field> 399 <name>BREAK</name> 400 <description>Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).</description> 401 <bitOffset>3</bitOffset> 402 <bitWidth>1</bitWidth> 403 <access>read-only</access> 404 <enumeratedValues> 405 <enumeratedValue> 406 <name>recv</name> 407 <description>Break frame received.</description> 408 <value>1</value> 409 </enumeratedValue> 410 </enumeratedValues> 411 </field> 412 <field> 413 <name>RX_EMPTY</name> 414 <description>Read-only flag indicating the RX FIFO state.</description> 415 <bitOffset>4</bitOffset> 416 <bitWidth>1</bitWidth> 417 <access>read-only</access> 418 <enumeratedValues> 419 <enumeratedValue> 420 <name>empty</name> 421 <description>RX FIFO empty.</description> 422 <value>1</value> 423 </enumeratedValue> 424 </enumeratedValues> 425 </field> 426 <field> 427 <name>RX_FULL</name> 428 <description>Read-only flag indicating the RX FIFO state.</description> 429 <bitOffset>5</bitOffset> 430 <bitWidth>1</bitWidth> 431 <access>read-only</access> 432 <enumeratedValues> 433 <enumeratedValue> 434 <name>full</name> 435 <description>RX FIFO full.</description> 436 <value>1</value> 437 </enumeratedValue> 438 </enumeratedValues> 439 </field> 440 <field> 441 <name>TX_EMPTY</name> 442 <description>Read-only flag indicating the TX FIFO state.</description> 443 <bitOffset>6</bitOffset> 444 <bitWidth>1</bitWidth> 445 <access>read-only</access> 446 <enumeratedValues> 447 <enumeratedValue> 448 <name>empty</name> 449 <description>TX FIFO empty.</description> 450 <value>1</value> 451 </enumeratedValue> 452 </enumeratedValues> 453 </field> 454 <field> 455 <name>TX_FULL</name> 456 <description>Read-only flag indicating the TX FIFO state.</description> 457 <bitOffset>7</bitOffset> 458 <bitWidth>1</bitWidth> 459 <access>read-only</access> 460 <enumeratedValues> 461 <enumeratedValue> 462 <name>full</name> 463 <description>TX FIFO empty.</description> 464 <value>1</value> 465 </enumeratedValue> 466 </enumeratedValues> 467 </field> 468 <field> 469 <name>RX_NUM</name> 470 <description>Indicates the number of bytes currently in the RX FIFO.</description> 471 <bitOffset>8</bitOffset> 472 <bitWidth>6</bitWidth> 473 <access>read-only</access> 474 </field> 475 <field> 476 <name>TX_NUM</name> 477 <description>Indicates the number of bytes currently in the TX FIFO.</description> 478 <bitOffset>16</bitOffset> 479 <bitWidth>6</bitWidth> 480 <access>read-only</access> 481 </field> 482 <field> 483 <name>RX_TO</name> 484 <description>Receiver Timeout Status. Indicates if timeout has occurred.</description> 485 <bitOffset>24</bitOffset> 486 <bitWidth>1</bitWidth> 487 <access>read-only</access> 488 <enumeratedValues> 489 <enumeratedValue> 490 <name>expired</name> 491 <description>RX timeout has occurred.</description> 492 <value>1</value> 493 </enumeratedValue> 494 </enumeratedValues> 495 </field> 496 </fields> 497 </register> 498 <register> 499 <name>INT_EN</name> 500 <description>Interrupt Enable Register.</description> 501 <addressOffset>0x0C</addressOffset> 502 <size>32</size> 503 <fields> 504 <field> 505 <name>RX_FRAME_ERROR</name> 506 <description>Enable for RX Frame Error Interrupt.</description> 507 <bitOffset>0</bitOffset> 508 <bitWidth>1</bitWidth> 509 <enumeratedValues> 510 <enumeratedValue> 511 <name>dis</name> 512 <description>RX Frame error interrupt disabled.</description> 513 <value>0</value> 514 </enumeratedValue> 515 <enumeratedValue> 516 <name>en</name> 517 <description>RX Frame error interrupt enabled.</description> 518 <value>1</value> 519 </enumeratedValue> 520 </enumeratedValues> 521 </field> 522 <field> 523 <name>RX_PARITY_ERROR</name> 524 <description>Enable for RX Parity Error interrupt.</description> 525 <bitOffset>1</bitOffset> 526 <bitWidth>1</bitWidth> 527 <enumeratedValues> 528 <enumeratedValue> 529 <name>dis</name> 530 <description>RX Parity error interrupt disabled.</description> 531 <value>0</value> 532 </enumeratedValue> 533 <enumeratedValue> 534 <name>en</name> 535 <description>RX Parity error interrupt enabled.</description> 536 <value>1</value> 537 </enumeratedValue> 538 </enumeratedValues> 539 </field> 540 <field> 541 <name>CTS</name> 542 <description>Enable for CTS signal change interrupt.</description> 543 <bitOffset>2</bitOffset> 544 <bitWidth>1</bitWidth> 545 <enumeratedValues> 546 <enumeratedValue> 547 <name>dis</name> 548 <description>CTS State Change interrupt disabled.</description> 549 <value>0</value> 550 </enumeratedValue> 551 <enumeratedValue> 552 <name>en</name> 553 <description>CTS State Change interrupt enabled.</description> 554 <value>1</value> 555 </enumeratedValue> 556 </enumeratedValues> 557 </field> 558 <field> 559 <name>RX_OVERRUN</name> 560 <description>Enable for RX FIFO OVerrun interrupt.</description> 561 <bitOffset>3</bitOffset> 562 <bitWidth>1</bitWidth> 563 <enumeratedValues> 564 <enumeratedValue> 565 <name>dis</name> 566 <description>RX Overrun interrupt disabled.</description> 567 <value>0</value> 568 </enumeratedValue> 569 <enumeratedValue> 570 <name>en</name> 571 <description>RX Overrun interrupt enabled.</description> 572 <value>1</value> 573 </enumeratedValue> 574 </enumeratedValues> 575 </field> 576 <field> 577 <name>RX_FIFO_LVL</name> 578 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 579 <bitOffset>4</bitOffset> 580 <bitWidth>1</bitWidth> 581 <enumeratedValues> 582 <enumeratedValue> 583 <name>dis</name> 584 <description>RX FIFO Threshold Level interrupt disabled.</description> 585 <value>0</value> 586 </enumeratedValue> 587 <enumeratedValue> 588 <name>en</name> 589 <description>RX FIFO Threshold Level interrupt enabled.</description> 590 <value>1</value> 591 </enumeratedValue> 592 </enumeratedValues> 593 </field> 594 <field> 595 <name>TX_FIFO_AE</name> 596 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 597 <bitOffset>5</bitOffset> 598 <bitWidth>1</bitWidth> 599 <enumeratedValues> 600 <enumeratedValue> 601 <name>dis</name> 602 <description>TX FIFO One byte remaining (almost empty) interrupt disabled.</description> 603 <value>0</value> 604 </enumeratedValue> 605 <enumeratedValue> 606 <name>en</name> 607 <description>TX FIFO one byte remaining (almost empty) interrupt enabled.</description> 608 <value>1</value> 609 </enumeratedValue> 610 </enumeratedValues> 611 </field> 612 <field> 613 <name>TX_FIFO_LVL</name> 614 <description>Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 615 <bitOffset>6</bitOffset> 616 <bitWidth>1</bitWidth> 617 <enumeratedValues> 618 <enumeratedValue> 619 <name>dis</name> 620 <description>TX FIFO Threshold Level interrupt disabled.</description> 621 <value>0</value> 622 </enumeratedValue> 623 <enumeratedValue> 624 <name>en</name> 625 <description>TX FIFO Threshold Level interrupt enabled.</description> 626 <value>1</value> 627 </enumeratedValue> 628 </enumeratedValues> 629 </field> 630 <field> 631 <name>BREAK</name> 632 <description>Enable for received BREAK character interrupt.</description> 633 <bitOffset>7</bitOffset> 634 <bitWidth>1</bitWidth> 635 <enumeratedValues> 636 <enumeratedValue> 637 <name>dis</name> 638 <description> Break character received interrupt disabled.</description> 639 <value>0</value> 640 </enumeratedValue> 641 <enumeratedValue> 642 <name>en</name> 643 <description>Break character recevied interrupt enabled.</description> 644 <value>1</value> 645 </enumeratedValue> 646 </enumeratedValues> 647 </field> 648 <field> 649 <name>RX_TO</name> 650 <description>Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 651 <bitOffset>8</bitOffset> 652 <bitWidth>1</bitWidth> 653 <enumeratedValues> 654 <enumeratedValue> 655 <name>dis</name> 656 <description>RX Timeout interrupt disabled.</description> 657 <value>0</value> 658 </enumeratedValue> 659 <enumeratedValue> 660 <name>en</name> 661 <description>RX Timeout interrupt enabled.</description> 662 <value>1</value> 663 </enumeratedValue> 664 </enumeratedValues> 665 </field> 666 <field> 667 <name>LAST_BREAK</name> 668 <description>Enable for Last break character interrupt.</description> 669 <bitOffset>9</bitOffset> 670 <bitWidth>1</bitWidth> 671 <enumeratedValues> 672 <enumeratedValue> 673 <name>dis</name> 674 <description>Last break frame received interrupt disabled.</description> 675 <value>0</value> 676 </enumeratedValue> 677 <enumeratedValue> 678 <name>en</name> 679 <description>Last break frame received interrupt enabled.</description> 680 <value>1</value> 681 </enumeratedValue> 682 </enumeratedValues> 683 </field> 684 </fields> 685 </register> 686 <register> 687 <name>INT_FL</name> 688 <description>Interrupt Status Flags.</description> 689 <addressOffset>0x10</addressOffset> 690 <size>32</size> 691 <modifiedWriteValues>oneToClear</modifiedWriteValues> 692 <fields> 693 <field> 694 <name>FRAME</name> 695 <description>FLAG for RX Frame Error Interrupt.</description> 696 <bitOffset>0</bitOffset> 697 <bitWidth>1</bitWidth> 698 <enumeratedValues> 699 <enumeratedValue> 700 <name>active</name> 701 <description>Frame Error interrupt active.</description> 702 <value>1</value> 703 </enumeratedValue> 704 </enumeratedValues> 705 </field> 706 <field> 707 <name>PARITY</name> 708 <description>FLAG for RX Parity Error interrupt.</description> 709 <bitOffset>1</bitOffset> 710 <bitWidth>1</bitWidth> 711 <enumeratedValues> 712 <enumeratedValue> 713 <name>active</name> 714 <description>Receive parity error interrupt active.</description> 715 <value>1</value> 716 </enumeratedValue> 717 </enumeratedValues> 718 </field> 719 <field> 720 <name>CTS_CHANGE</name> 721 <description>FLAG for CTS signal change interrupt.</description> 722 <bitOffset>2</bitOffset> 723 <bitWidth>1</bitWidth> 724 <enumeratedValues> 725 <enumeratedValue> 726 <name>active</name> 727 <description>CTS State change interrupt active.</description> 728 <value>1</value> 729 </enumeratedValue> 730 </enumeratedValues> 731 </field> 732 <field> 733 <name>RX_OVR</name> 734 <description>FLAG for RX FIFO Overrun interrupt.</description> 735 <bitOffset>3</bitOffset> 736 <bitWidth>1</bitWidth> 737 <enumeratedValues> 738 <enumeratedValue> 739 <name>active</name> 740 <description>RX Overrun interrupt active.</description> 741 <value>1</value> 742 </enumeratedValue> 743 </enumeratedValues> 744 </field> 745 <field> 746 <name>RX_FIFO_LVL</name> 747 <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 748 <bitOffset>4</bitOffset> 749 <bitWidth>1</bitWidth> 750 <enumeratedValues> 751 <enumeratedValue> 752 <name>active</name> 753 <description>RX FIFO Threshold level interrupt active.</description> 754 <value>1</value> 755 </enumeratedValue> 756 </enumeratedValues> 757 </field> 758 <field> 759 <name>TX_FIFO_AE</name> 760 <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description> 761 <bitOffset>5</bitOffset> 762 <bitWidth>1</bitWidth> 763 <enumeratedValues> 764 <enumeratedValue> 765 <name>active</name> 766 <description>TX FIFO one byte remaining interrupt active.</description> 767 <value>1</value> 768 </enumeratedValue> 769 </enumeratedValues> 770 </field> 771 <field> 772 <name>TX_FIFO_LVL</name> 773 <description>FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 774 <bitOffset>6</bitOffset> 775 <bitWidth>1</bitWidth> 776 <enumeratedValues> 777 <enumeratedValue> 778 <name>active</name> 779 <description>TX FIFO threshold level interrupt active.</description> 780 <value>1</value> 781 </enumeratedValue> 782 </enumeratedValues> 783 </field> 784 <field> 785 <name>BREAK</name> 786 <description>FLAG for received BREAK character interrupt.</description> 787 <bitOffset>7</bitOffset> 788 <bitWidth>1</bitWidth> 789 <enumeratedValues> 790 <enumeratedValue> 791 <name>active</name> 792 <description>Break character received interrupt active.</description> 793 <value>1</value> 794 </enumeratedValue> 795 </enumeratedValues> 796 </field> 797 <field> 798 <name>RX_TO</name> 799 <description>FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 800 <bitOffset>8</bitOffset> 801 <bitWidth>1</bitWidth> 802 <enumeratedValues> 803 <enumeratedValue> 804 <name>active</name> 805 <description>Receive timeout expired interrupt active.</description> 806 <value>1</value> 807 </enumeratedValue> 808 </enumeratedValues> 809 </field> 810 <field> 811 <name>LAST_BREAK</name> 812 <description>FLAG for Last break character interrupt.</description> 813 <bitOffset>9</bitOffset> 814 <bitWidth>1</bitWidth> 815 <enumeratedValues> 816 <enumeratedValue> 817 <name>active</name> 818 <description>Last break character received interrupt active.</description> 819 <value>1</value> 820 </enumeratedValue> 821 </enumeratedValues> 822 </field> 823 </fields> 824 </register> 825 <register> 826 <name>BAUD0</name> 827 <description>Baud rate register. Integer portion.</description> 828 <addressOffset>0x14</addressOffset> 829 <size>32</size> 830 <fields> 831 <field> 832 <name>IBAUD</name> 833 <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description> 834 <bitOffset>0</bitOffset> 835 <bitWidth>12</bitWidth> 836 </field> 837 <field> 838 <name>CLKDIV</name> 839 <description>FACTOR must be chosen to have IDIV> 840 0. factor used in calculation = 128 > 841 > 842 FACTOR. 843 </description> 844 <bitOffset>16</bitOffset> 845 <bitWidth>3</bitWidth> 846 <enumeratedValues> 847 <enumeratedValue> 848 <name>div128</name> 849 <description>Baud Factor 128</description> 850 <value>0</value> 851 </enumeratedValue> 852 <enumeratedValue> 853 <name>div64</name> 854 <description>Baud Factor 64</description> 855 <value>1</value> 856 </enumeratedValue> 857 <enumeratedValue> 858 <name>div32</name> 859 <description>Baud Factor 32</description> 860 <value>2</value> 861 </enumeratedValue> 862 <enumeratedValue> 863 <name>div16</name> 864 <description>Baud Factor 16</description> 865 <value>3</value> 866 </enumeratedValue> 867 <enumeratedValue> 868 <name>div8</name> 869 <description>Baud Factor 8</description> 870 <value>4</value> 871 </enumeratedValue> 872 </enumeratedValues> 873 </field> 874 </fields> 875 </register> 876 <register> 877 <name>BAUD1</name> 878 <description>Baud rate register. Decimal Setting.</description> 879 <addressOffset>0x18</addressOffset> 880 <size>32</size> 881 <fields> 882 <field> 883 <name>DBAUD</name> 884 <description>Decimal portion of baud rate divisor value. DIV = InputClock/ (factor*Baud Rate Frequency). DDIV= (DIV-IDIV) *128.</description> 885 <bitOffset>0</bitOffset> 886 <bitWidth>7</bitWidth> 887 </field> 888 </fields> 889 </register> 890 <register> 891 <name>FIFO</name> 892 <description>FIFO Data buffer.</description> 893 <addressOffset>0x1C</addressOffset> 894 <size>32</size> 895 <fields> 896 <field> 897 <name>FIFO</name> 898 <description>Load/unload location for TX and RX FIFO buffers.</description> 899 <bitOffset>0</bitOffset> 900 <bitWidth>8</bitWidth> 901 </field> 902 </fields> 903 </register> 904 <register> 905 <name>DMA</name> 906 <description>DMA Configuration.</description> 907 <addressOffset>0x20</addressOffset> 908 <size>32</size> 909 <fields> 910 <field> 911 <name>TXDMA_EN</name> 912 <description>TX DMA channel enable.</description> 913 <bitOffset>0</bitOffset> 914 <bitWidth>1</bitWidth> 915 <enumeratedValues> 916 <enumeratedValue> 917 <name>dis</name> 918 <description>DMA is disabled </description> 919 <value>0</value> 920 </enumeratedValue> 921 <enumeratedValue> 922 <name>en</name> 923 <description>DMA is enabled </description> 924 <value>1</value> 925 </enumeratedValue> 926 </enumeratedValues> 927 </field> 928 <field> 929 <name>RXDMA_EN</name> 930 <description>RX DMA channel enable.</description> 931 <bitOffset>1</bitOffset> 932 <bitWidth>1</bitWidth> 933 <enumeratedValues> 934 <enumeratedValue> 935 <name>dis</name> 936 <description>DMA is disabled </description> 937 <value>0</value> 938 </enumeratedValue> 939 <enumeratedValue> 940 <name>en</name> 941 <description>DMA is enabled </description> 942 <value>1</value> 943 </enumeratedValue> 944 </enumeratedValues> 945 </field> 946 <field> 947 <name>TXDMA_LVL</name> 948 <description>TX threshold for DMA transmission.</description> 949 <bitOffset>8</bitOffset> 950 <bitWidth>6</bitWidth> 951 </field> 952 <field> 953 <name>RXDMA_LVL</name> 954 <description>RX threshold for DMA transmission.</description> 955 <bitOffset>16</bitOffset> 956 <bitWidth>6</bitWidth> 957 </field> 958 </fields> 959 </register> 960 <register> 961 <name>TXFIFO</name> 962 <description>Transmit FIFO Status register.</description> 963 <addressOffset>0x24</addressOffset> 964 <size>32</size> 965 <fields> 966 <field> 967 <name>DATA</name> 968 <description>Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).</description> 969 <bitOffset>0</bitOffset> 970 <bitWidth>7</bitWidth> 971 </field> 972 </fields> 973 </register> 974 </registers> 975 </peripheral> 976 <!-- UART: UART --> 977</device>
