1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>UART0</name> 5 <description>UART</description> 6 <baseAddress>0x40042000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>UART0</name> 14 <description>UART0 IRQ</description> 15 <value>14</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CTRL</name> 20 <description>Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <size>32</size> 23 <fields> 24 <field> 25 <name>ENABLE</name> 26 <description>UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>dis</name> 32 <description>UART disabled. FIFOs are flushed. Clock is gated off for power savings. </description> 33 <value>0</value> 34 </enumeratedValue> 35 <enumeratedValue> 36 <name>en</name> 37 <description>UART enabled. </description> 38 <value>1</value> 39 </enumeratedValue> 40 </enumeratedValues> 41 </field> 42 <field> 43 <name>PARITY_EN</name> 44 <description>Enable/disable Parity bit (9th character).</description> 45 <bitOffset>1</bitOffset> 46 <bitWidth>1</bitWidth> 47 <enumeratedValues> 48 <enumeratedValue> 49 <name>dis</name> 50 <description>No Parity </description> 51 <value>0</value> 52 </enumeratedValue> 53 <enumeratedValue> 54 <name>en</name> 55 <description>Parity enabled as 9th bit</description> 56 <value>1</value> 57 </enumeratedValue> 58 </enumeratedValues> 59 </field> 60 <field> 61 <name>PARITY</name> 62 <description>When PARITY_EN=1, selects odd, even, Mark or Space parity. 63 Mark parity = always 1; 64 65 Space parity = always 0.</description> 66 <bitOffset>2</bitOffset> 67 <bitWidth>2</bitWidth> 68 <enumeratedValues> 69 <enumeratedValue> 70 <name>Even</name> 71 <description>Even parity selected.</description> 72 <value>0</value> 73 </enumeratedValue> 74 <enumeratedValue> 75 <name>ODD</name> 76 <description>Odd parity selected.</description> 77 <value>1</value> 78 </enumeratedValue> 79 <enumeratedValue> 80 <name>MARK</name> 81 <description>Mark parity selected.</description> 82 <value>2</value> 83 </enumeratedValue> 84 <enumeratedValue> 85 <name>SPACE</name> 86 <description>Space parity selected.</description> 87 <value>3</value> 88 </enumeratedValue> 89 </enumeratedValues> 90 </field> 91 <field> 92 <name>PARMD</name> 93 <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description> 94 <bitOffset>4</bitOffset> 95 <bitWidth>1</bitWidth> 96 <enumeratedValues> 97 <enumeratedValue> 98 <name>1</name> 99 <description>Parity calculation is based on number of 1s in frame.</description> 100 <value>0</value> 101 </enumeratedValue> 102 <enumeratedValue> 103 <name>0</name> 104 <description>Parity calculation is based on number of 0s in frame.</description> 105 <value>1</value> 106 </enumeratedValue> 107 </enumeratedValues> 108 </field> 109 <field> 110 <name>TX_FLUSH</name> 111 <description>Flushes the TX FIFO buffer.</description> 112 <bitOffset>5</bitOffset> 113 <bitWidth>1</bitWidth> 114 </field> 115 <field> 116 <name>RX_FLUSH</name> 117 <description>Flushes the RX FIFO buffer.</description> 118 <bitOffset>6</bitOffset> 119 <bitWidth>1</bitWidth> 120 </field> 121 <field> 122 <name>BITACC</name> 123 <description>If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.</description> 124 <bitOffset>7</bitOffset> 125 <bitWidth>1</bitWidth> 126 <enumeratedValues> 127 <enumeratedValue> 128 <name>FRAME</name> 129 <description>Frame accuracy.</description> 130 <value>0</value> 131 </enumeratedValue> 132 <enumeratedValue> 133 <name>BIT</name> 134 <description>Bit accuracy.</description> 135 <value>1</value> 136 </enumeratedValue> 137 </enumeratedValues> 138 </field> 139 <field> 140 <name>CHAR_SIZE</name> 141 <description>Selects UART character size.</description> 142 <bitOffset>8</bitOffset> 143 <bitWidth>2</bitWidth> 144 <enumeratedValues> 145 <enumeratedValue> 146 <name>5</name> 147 <description>5 bits.</description> 148 <value>0</value> 149 </enumeratedValue> 150 <enumeratedValue> 151 <name>6</name> 152 <description>6 bits.</description> 153 <value>1</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>7</name> 157 <description>7 bits.</description> 158 <value>2</value> 159 </enumeratedValue> 160 <enumeratedValue> 161 <name>8</name> 162 <description>8 bits.</description> 163 <value>3</value> 164 </enumeratedValue> 165 </enumeratedValues> 166 </field> 167 <field> 168 <name>STOPBITS</name> 169 <description>Selects the number of stop bits that will be generated.</description> 170 <bitOffset>10</bitOffset> 171 <bitWidth>1</bitWidth> 172 <enumeratedValues> 173 <enumeratedValue> 174 <name>1</name> 175 <description>1 stop bit.</description> 176 <value>0</value> 177 </enumeratedValue> 178 <enumeratedValue> 179 <name>1_5</name> 180 <description>1.5 stop bits.</description> 181 <value>1</value> 182 </enumeratedValue> 183 </enumeratedValues> 184 </field> 185 <field> 186 <name>FLOW_CTRL</name> 187 <description>Enables/disables hardware flow control.</description> 188 <bitOffset>11</bitOffset> 189 <bitWidth>1</bitWidth> 190 <enumeratedValues> 191 <enumeratedValue> 192 <name>en</name> 193 <description>HW Flow Control with RTS/CTS enabled</description> 194 <value>1</value> 195 </enumeratedValue> 196 <enumeratedValue> 197 <name>dis</name> 198 <description>HW Flow Control disabled</description> 199 <value>0</value> 200 </enumeratedValue> 201 </enumeratedValues> 202 </field> 203 <field> 204 <name>FLOW_POL</name> 205 <description>RTS/CTS polarity.</description> 206 <bitOffset>12</bitOffset> 207 <bitWidth>1</bitWidth> 208 <enumeratedValues> 209 <enumeratedValue> 210 <name>0</name> 211 <description>RTS/CTS asserted is logic 0.</description> 212 <value>0</value> 213 </enumeratedValue> 214 <enumeratedValue> 215 <name>1</name> 216 <description>RTS/CTS asserted is logic 1.</description> 217 <value>1</value> 218 </enumeratedValue> 219 </enumeratedValues> 220 </field> 221 <field> 222 <name>NULL_MODEM</name> 223 <description>NULL Modem Support (RTS/CTS and TXD/RXD swap).</description> 224 <bitOffset>13</bitOffset> 225 <bitWidth>1</bitWidth> 226 <enumeratedValues> 227 <enumeratedValue> 228 <name>DIS</name> 229 <description>Direct convention.</description> 230 <value>0</value> 231 </enumeratedValue> 232 <enumeratedValue> 233 <name>EN</name> 234 <description>Null Modem Mode.</description> 235 <value>1</value> 236 </enumeratedValue> 237 </enumeratedValues> 238 </field> 239 <field> 240 <name>BREAK</name> 241 <description>Break control bit. It causes a break condition to be transmitted to receiving UART.</description> 242 <bitOffset>14</bitOffset> 243 <bitWidth>1</bitWidth> 244 <enumeratedValues> 245 <enumeratedValue> 246 <name>DIS</name> 247 <description>Break characters are not generated.</description> 248 <value>0</value> 249 </enumeratedValue> 250 <enumeratedValue> 251 <name>EN</name> 252 <description>Break characters are sent (all the bits are at '0' including start/parity/stop).</description> 253 <value>1</value> 254 </enumeratedValue> 255 </enumeratedValues> 256 </field> 257 <field> 258 <name>CLKSEL</name> 259 <description>Baud Rate Clock Source Select. Selects the baud rate clock.</description> 260 <bitOffset>15</bitOffset> 261 <bitWidth>1</bitWidth> 262 <enumeratedValues> 263 <enumeratedValue> 264 <name>SYSTEM</name> 265 <description>System clock.</description> 266 <value>0</value> 267 </enumeratedValue> 268 <enumeratedValue> 269 <name>ALTERNATE</name> 270 <description>Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.</description> 271 <value>1</value> 272 </enumeratedValue> 273 </enumeratedValues> 274 </field> 275 <field> 276 <name>RX_TO</name> 277 <description>RX Time Out. RX time out interrupt will occur after RXTO Uart 278 characters if RX-FIFO is not empty and RX FIFO has not been read.</description> 279 <bitOffset>16</bitOffset> 280 <bitWidth>8</bitWidth> 281 </field> 282 </fields> 283 </register> 284 <register> 285 <name>THRESH_CTRL</name> 286 <description>Threshold Control register.</description> 287 <addressOffset>0x04</addressOffset> 288 <size>32</size> 289 <fields> 290 <field> 291 <name>RX_FIFO_THRESH</name> 292 <description>RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.</description> 293 <bitOffset>0</bitOffset> 294 <bitWidth>6</bitWidth> 295 </field> 296 <field> 297 <name>TX_FIFO_THRESH</name> 298 <description>TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.</description> 299 <bitOffset>8</bitOffset> 300 <bitWidth>6</bitWidth> 301 </field> 302 <field> 303 <name>RTS_FIFO_THRESH</name> 304 <description>RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.</description> 305 <bitOffset>16</bitOffset> 306 <bitWidth>6</bitWidth> 307 </field> 308 </fields> 309 </register> 310 <register> 311 <name>STATUS</name> 312 <description>Status Register.</description> 313 <addressOffset>0x08</addressOffset> 314 <size>32</size> 315 <access>read-only</access> 316 <fields> 317 <field> 318 <name>TX_BUSY</name> 319 <description>Read-only flag indicating the UART transmit status.</description> 320 <bitOffset>0</bitOffset> 321 <bitWidth>1</bitWidth> 322 <access>read-only</access> 323 </field> 324 <field> 325 <name>RX_BUSY</name> 326 <description>Read-only flag indicating the UARTreceiver status.</description> 327 <bitOffset>1</bitOffset> 328 <bitWidth>1</bitWidth> 329 <access>read-only</access> 330 </field> 331 <field> 332 <name>PARITY</name> 333 <description>9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.</description> 334 <bitOffset>2</bitOffset> 335 <bitWidth>1</bitWidth> 336 <access>read-only</access> 337 </field> 338 <field> 339 <name>BREAK</name> 340 <description>Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).</description> 341 <bitOffset>3</bitOffset> 342 <bitWidth>1</bitWidth> 343 <access>read-only</access> 344 </field> 345 <field> 346 <name>RX_EMPTY</name> 347 <description>Read-only flag indicating the RX FIFO state.</description> 348 <bitOffset>4</bitOffset> 349 <bitWidth>1</bitWidth> 350 <access>read-only</access> 351 </field> 352 <field> 353 <name>RX_FULL</name> 354 <description>Read-only flag indicating the RX FIFO state.</description> 355 <bitOffset>5</bitOffset> 356 <bitWidth>1</bitWidth> 357 <access>read-only</access> 358 </field> 359 <field> 360 <name>TX_EMPTY</name> 361 <description>Read-only flag indicating the TX FIFO state.</description> 362 <bitOffset>6</bitOffset> 363 <bitWidth>1</bitWidth> 364 <access>read-only</access> 365 </field> 366 <field> 367 <name>TX_FULL</name> 368 <description>Read-only flag indicating the TX FIFO state.</description> 369 <bitOffset>7</bitOffset> 370 <bitWidth>1</bitWidth> 371 <access>read-only</access> 372 </field> 373 <field> 374 <name>RX_FIFO_CNT</name> 375 <description>Indicates the number of bytes currently in the RX FIFO.</description> 376 <bitOffset>8</bitOffset> 377 <bitWidth>6</bitWidth> 378 <access>read-only</access> 379 </field> 380 <field> 381 <name>TX_FIFO_CNT</name> 382 <description>Indicates the number of bytes currently in the TX FIFO.</description> 383 <bitOffset>16</bitOffset> 384 <bitWidth>6</bitWidth> 385 <access>read-only</access> 386 </field> 387 </fields> 388 </register> 389 <register> 390 <name>INT_EN</name> 391 <description>Interrupt Enable Register.</description> 392 <addressOffset>0x0C</addressOffset> 393 <size>32</size> 394 <fields> 395 <field> 396 <name>RX_FRAME_ERROR</name> 397 <description>Enable for RX Frame Error Interrupt.</description> 398 <bitOffset>0</bitOffset> 399 <bitWidth>1</bitWidth> 400 </field> 401 <field> 402 <name>RX_PARITY_ERROR</name> 403 <description>Enable for RX Parity Error interrupt.</description> 404 <bitOffset>1</bitOffset> 405 <bitWidth>1</bitWidth> 406 </field> 407 <field> 408 <name>CTS_CHANGE</name> 409 <description>Enable for CTS signal change interrupt.</description> 410 <bitOffset>2</bitOffset> 411 <bitWidth>1</bitWidth> 412 </field> 413 <field> 414 <name>RX_OVERRUN</name> 415 <description>Enable for RX FIFO OVerrun interrupt.</description> 416 <bitOffset>3</bitOffset> 417 <bitWidth>1</bitWidth> 418 </field> 419 <field> 420 <name>RX_FIFO_THRESH</name> 421 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 422 <bitOffset>4</bitOffset> 423 <bitWidth>1</bitWidth> 424 </field> 425 <field> 426 <name>TX_FIFO_ALMOST_EMPTY</name> 427 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 428 <bitOffset>5</bitOffset> 429 <bitWidth>1</bitWidth> 430 </field> 431 <field> 432 <name>TX_FIFO_THRESH</name> 433 <description>Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 434 <bitOffset>6</bitOffset> 435 <bitWidth>1</bitWidth> 436 </field> 437 <field> 438 <name>BREAK</name> 439 <description>Enable for received BREAK character interrupt.</description> 440 <bitOffset>7</bitOffset> 441 <bitWidth>1</bitWidth> 442 </field> 443 <field> 444 <name>RX_TIMEOUT</name> 445 <description>Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 446 <bitOffset>8</bitOffset> 447 <bitWidth>1</bitWidth> 448 </field> 449 <field> 450 <name>LAST_BREAK</name> 451 <description>Enable for Last break character interrupt.</description> 452 <bitOffset>9</bitOffset> 453 <bitWidth>1</bitWidth> 454 </field> 455 </fields> 456 </register> 457 <register> 458 <name>INT_FL</name> 459 <description>Interrupt Status Flags.</description> 460 <addressOffset>0x10</addressOffset> 461 <size>32</size> 462 <modifiedWriteValues>oneToClear</modifiedWriteValues> 463 <fields> 464 <field> 465 <name>RX_FRAME_ERROR</name> 466 <description>FLAG for RX Frame Error Interrupt.</description> 467 <bitOffset>0</bitOffset> 468 <bitWidth>1</bitWidth> 469 </field> 470 <field> 471 <name>RX_PARITY_ERROR</name> 472 <description>FLAG for RX Parity Error interrupt.</description> 473 <bitOffset>1</bitOffset> 474 <bitWidth>1</bitWidth> 475 </field> 476 <field> 477 <name>CTS_CHANGE</name> 478 <description>FLAG for CTS signal change interrupt.</description> 479 <bitOffset>2</bitOffset> 480 <bitWidth>1</bitWidth> 481 </field> 482 <field> 483 <name>RX_OVERRUN</name> 484 <description>FLAG for RX FIFO Overrun interrupt.</description> 485 <bitOffset>3</bitOffset> 486 <bitWidth>1</bitWidth> 487 </field> 488 <field> 489 <name>RX_FIFO_THRESH</name> 490 <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 491 <bitOffset>4</bitOffset> 492 <bitWidth>1</bitWidth> 493 </field> 494 <field> 495 <name>TX_FIFO_ALMOST_EMPTY</name> 496 <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description> 497 <bitOffset>5</bitOffset> 498 <bitWidth>1</bitWidth> 499 </field> 500 <field> 501 <name>TX_FIFO_THRESH</name> 502 <description>FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 503 <bitOffset>6</bitOffset> 504 <bitWidth>1</bitWidth> 505 </field> 506 <field> 507 <name>BREAK</name> 508 <description>FLAG for received BREAK character interrupt.</description> 509 <bitOffset>7</bitOffset> 510 <bitWidth>1</bitWidth> 511 </field> 512 <field> 513 <name>RX_TIMEOUT</name> 514 <description>FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 515 <bitOffset>8</bitOffset> 516 <bitWidth>1</bitWidth> 517 </field> 518 <field> 519 <name>LAST_BREAK</name> 520 <description>FLAG for Last break character interrupt.</description> 521 <bitOffset>9</bitOffset> 522 <bitWidth>1</bitWidth> 523 </field> 524 </fields> 525 </register> 526 <register> 527 <name>BAUD0</name> 528 <description>Baud rate register. Integer portion.</description> 529 <addressOffset>0x14</addressOffset> 530 <size>32</size> 531 <fields> 532 <field> 533 <name>IBAUD</name> 534 <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description> 535 <bitOffset>0</bitOffset> 536 <bitWidth>12</bitWidth> 537 </field> 538 <field> 539 <name>FACTOR</name> 540 <description>FACTOR must be chosen to have IDIV> 541 0. factor used in calculation = 128 > 542 > 543 FACTOR. 544 </description> 545 <bitOffset>16</bitOffset> 546 <bitWidth>2</bitWidth> 547 <enumeratedValues> 548 <enumeratedValue> 549 <name>128</name> 550 <description>Baud Factor 128</description> 551 <value>0</value> 552 </enumeratedValue> 553 <enumeratedValue> 554 <name>64</name> 555 <description>Baud Factor 64</description> 556 <value>1</value> 557 </enumeratedValue> 558 <enumeratedValue> 559 <name>32</name> 560 <description>Baud Factor 32</description> 561 <value>2</value> 562 </enumeratedValue> 563 <enumeratedValue> 564 <name>16</name> 565 <description>Baud Factor 16</description> 566 <value>3</value> 567 </enumeratedValue> 568 </enumeratedValues> 569 </field> 570 </fields> 571 </register> 572 <register> 573 <name>BAUD1</name> 574 <description>Baud rate register. Decimal Setting.</description> 575 <addressOffset>0x18</addressOffset> 576 <size>32</size> 577 <fields> 578 <field> 579 <name>DBAUD</name> 580 <description>Decimal portion of baud rate divisor value. DIV = InputClock/ (factor*Baud Rate Frequency). DDIV= (DIV-IDIV) *128.</description> 581 <bitOffset>0</bitOffset> 582 <bitWidth>12</bitWidth> 583 </field> 584 </fields> 585 </register> 586 <register> 587 <name>FIFO</name> 588 <description>FIFO Data buffer.</description> 589 <addressOffset>0x1C</addressOffset> 590 <size>32</size> 591 <fields> 592 <field> 593 <name>FIFO</name> 594 <description>Load/unload location for TX and RX FIFO buffers.</description> 595 <bitOffset>0</bitOffset> 596 <bitWidth>8</bitWidth> 597 </field> 598 </fields> 599 </register> 600 <register> 601 <name>DMA</name> 602 <description>DMA Configuration.</description> 603 <addressOffset>0x20</addressOffset> 604 <size>32</size> 605 <fields> 606 <field> 607 <name>TXDMA_EN</name> 608 <description>TX DMA channel enable.</description> 609 <bitOffset>0</bitOffset> 610 <bitWidth>1</bitWidth> 611 <enumeratedValues> 612 <enumeratedValue> 613 <name>dis</name> 614 <description>DMA is disabled </description> 615 <value>0</value> 616 </enumeratedValue> 617 <enumeratedValue> 618 <name>en</name> 619 <description>DMA is enabled </description> 620 <value>1</value> 621 </enumeratedValue> 622 </enumeratedValues> 623 </field> 624 <field> 625 <name>RXDMA_EN</name> 626 <description>RX DMA channel enable.</description> 627 <bitOffset>1</bitOffset> 628 <bitWidth>1</bitWidth> 629 <enumeratedValues> 630 <enumeratedValue> 631 <name>dis</name> 632 <description>DMA is disabled </description> 633 <value>0</value> 634 </enumeratedValue> 635 <enumeratedValue> 636 <name>en</name> 637 <description>DMA is enabled </description> 638 <value>1</value> 639 </enumeratedValue> 640 </enumeratedValues> 641 </field> 642 <field> 643 <name>RXDMA_START</name> 644 <description>Receive DMA Start.</description> 645 <bitOffset>3</bitOffset> 646 <bitWidth>1</bitWidth> 647 </field> 648 <field> 649 <name>RXDMA_AUTO_TO</name> 650 <description>Receive DMA Timeout Start.</description> 651 <bitOffset>5</bitOffset> 652 <bitWidth>1</bitWidth> 653 </field> 654 <field> 655 <name>TXDMA_LEVEL</name> 656 <description>TX threshold for DMA transmission.</description> 657 <bitOffset>8</bitOffset> 658 <bitWidth>6</bitWidth> 659 </field> 660 <field> 661 <name>RXDMA_LEVEL</name> 662 <description>RX threshold for DMA transmission.</description> 663 <bitOffset>16</bitOffset> 664 <bitWidth>6</bitWidth> 665 </field> 666 </fields> 667 </register> 668 <register> 669 <name>TX_FIFO</name> 670 <description>Transmit FIFO Status register.</description> 671 <addressOffset>0x24</addressOffset> 672 <size>32</size> 673 <fields> 674 <field> 675 <name>DATA</name> 676 <description>Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).</description> 677 <bitOffset>0</bitOffset> 678 <bitWidth>7</bitWidth> 679 </field> 680 </fields> 681 </register> 682 </registers> 683 </peripheral> 684<!-- UART: UART --> 685</device> 686
