1 /** 2 * @file trng_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TRNG_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _TRNG_REVA_REGS_H_ 27 #define _TRNG_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup trng_reva 65 * @defgroup trng_reva_registers TRNG_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the TRNG_REVA Peripheral Module. 67 * @details Random Number Generator. 68 */ 69 70 /** 71 * @ingroup trng_reva_registers 72 * Structure type to access the TRNG_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> TRNG_REVA CTRL Register */ 76 __I uint32_t data; /**< <tt>\b 0x04:</tt> TRNG_REVA DATA Register */ 77 } mxc_trng_reva_regs_t; 78 79 /** 80 * @ingroup trng_reva_registers 81 * @defgroup TRNG_REVA_CTRL TRNG_REVA_CTRL 82 * @brief TRNG_REVA Control Register. 83 * @{ 84 */ 85 #define MXC_F_TRNG_REVA_CTRL_RNG_IE_POS 2 /**< CTRL_RNG_IE Position */ 86 #define MXC_F_TRNG_REVA_CTRL_RNG_IE ((uint32_t)(0x1UL << MXC_F_TRNG_REVA_CTRL_RNG_IE_POS)) /**< CTRL_RNG_IE Mask */ 87 #define MXC_V_TRNG_REVA_CTRL_RNG_IE_DIS ((uint32_t)0x0UL) /**< CTRL_RNG_IE_DIS Value */ 88 #define MXC_S_TRNG_REVA_CTRL_RNG_IE_DIS (MXC_V_TRNG_REVA_CTRL_RNG_IE_DIS << MXC_F_TRNG_REVA_CTRL_RNG_IE_POS) /**< CTRL_RNG_IE_DIS Setting */ 89 #define MXC_V_TRNG_REVA_CTRL_RNG_IE_EN ((uint32_t)0x1UL) /**< CTRL_RNG_IE_EN Value */ 90 #define MXC_S_TRNG_REVA_CTRL_RNG_IE_EN (MXC_V_TRNG_REVA_CTRL_RNG_IE_EN << MXC_F_TRNG_REVA_CTRL_RNG_IE_POS) /**< CTRL_RNG_IE_EN Setting */ 91 92 #define MXC_F_TRNG_REVA_CTRL_RNG_ISC_POS 3 /**< CTRL_RNG_ISC Position */ 93 #define MXC_F_TRNG_REVA_CTRL_RNG_ISC ((uint32_t)(0x1UL << MXC_F_TRNG_REVA_CTRL_RNG_ISC_POS)) /**< CTRL_RNG_ISC Mask */ 94 #define MXC_V_TRNG_REVA_CTRL_RNG_ISC_CLEAR ((uint32_t)0x1UL) /**< CTRL_RNG_ISC_CLEAR Value */ 95 #define MXC_S_TRNG_REVA_CTRL_RNG_ISC_CLEAR (MXC_V_TRNG_REVA_CTRL_RNG_ISC_CLEAR << MXC_F_TRNG_REVA_CTRL_RNG_ISC_POS) /**< CTRL_RNG_ISC_CLEAR Setting */ 96 97 #define MXC_F_TRNG_REVA_CTRL_RNG_I4S_POS 4 /**< CTRL_RNG_I4S Position */ 98 #define MXC_F_TRNG_REVA_CTRL_RNG_I4S ((uint32_t)(0x1UL << MXC_F_TRNG_REVA_CTRL_RNG_I4S_POS)) /**< CTRL_RNG_I4S Mask */ 99 #define MXC_V_TRNG_REVA_CTRL_RNG_I4S_NOT_READY ((uint32_t)0x0UL) /**< CTRL_RNG_I4S_NOT_READY Value */ 100 #define MXC_S_TRNG_REVA_CTRL_RNG_I4S_NOT_READY (MXC_V_TRNG_REVA_CTRL_RNG_I4S_NOT_READY << MXC_F_TRNG_REVA_CTRL_RNG_I4S_POS) /**< CTRL_RNG_I4S_NOT_READY Setting */ 101 #define MXC_V_TRNG_REVA_CTRL_RNG_I4S_READY ((uint32_t)0x1UL) /**< CTRL_RNG_I4S_READY Value */ 102 #define MXC_S_TRNG_REVA_CTRL_RNG_I4S_READY (MXC_V_TRNG_REVA_CTRL_RNG_I4S_READY << MXC_F_TRNG_REVA_CTRL_RNG_I4S_POS) /**< CTRL_RNG_I4S_READY Setting */ 103 104 #define MXC_F_TRNG_REVA_CTRL_RNG_IS_POS 5 /**< CTRL_RNG_IS Position */ 105 #define MXC_F_TRNG_REVA_CTRL_RNG_IS ((uint32_t)(0x1UL << MXC_F_TRNG_REVA_CTRL_RNG_IS_POS)) /**< CTRL_RNG_IS Mask */ 106 #define MXC_V_TRNG_REVA_CTRL_RNG_IS_NOT_READY ((uint32_t)0x0UL) /**< CTRL_RNG_IS_NOT_READY Value */ 107 #define MXC_S_TRNG_REVA_CTRL_RNG_IS_NOT_READY (MXC_V_TRNG_REVA_CTRL_RNG_IS_NOT_READY << MXC_F_TRNG_REVA_CTRL_RNG_IS_POS) /**< CTRL_RNG_IS_NOT_READY Setting */ 108 #define MXC_V_TRNG_REVA_CTRL_RNG_IS_READY ((uint32_t)0x1UL) /**< CTRL_RNG_IS_READY Value */ 109 #define MXC_S_TRNG_REVA_CTRL_RNG_IS_READY (MXC_V_TRNG_REVA_CTRL_RNG_IS_READY << MXC_F_TRNG_REVA_CTRL_RNG_IS_POS) /**< CTRL_RNG_IS_READY Setting */ 110 111 #define MXC_F_TRNG_REVA_CTRL_AESKG_POS 6 /**< CTRL_AESKG Position */ 112 #define MXC_F_TRNG_REVA_CTRL_AESKG ((uint32_t)(0x1UL << MXC_F_TRNG_REVA_CTRL_AESKG_POS)) /**< CTRL_AESKG Mask */ 113 114 /**@} end of group TRNG_REVA_CTRL_Register */ 115 116 /** 117 * @ingroup trng_reva_registers 118 * @defgroup TRNG_REVA_DATA TRNG_REVA_DATA 119 * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG_REVA is 120 * disabled, read returns 0x0000 0000. 121 * @{ 122 */ 123 #define MXC_F_TRNG_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ 124 #define MXC_F_TRNG_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ 125 126 /**@} end of group TRNG_REVA_DATA_Register */ 127 128 #ifdef __cplusplus 129 } 130 #endif 131 132 #endif /* _TRNG_REVA_REGS_H_ */ 133
