1 /** 2 * @file trng_revc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TRNG_REVC Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _TRNG_REVC_REGS_H_ 27 #define _TRNG_REVC_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup trng_revc 65 * @defgroup trng_revc_registers TRNG_REVC_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the TRNG_REVC Peripheral Module. 67 * @details Random Number Generator. 68 */ 69 70 /** 71 * @ingroup trng_revc_registers 72 * Structure type to access the TRNG_REVC Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cn; /**< <tt>\b 0x00:</tt> TRNG_REVC CN Register */ 76 __I uint32_t st; /**< <tt>\b 0x04:</tt> TRNG_REVC ST Register */ 77 __I uint32_t data; /**< <tt>\b 0x08:</tt> TRNG_REVC DATA Register */ 78 } mxc_trng_revc_regs_t; 79 80 /* Register offsets for module TRNG_REVC */ 81 /** 82 * @ingroup trng_revc_registers 83 * @defgroup TRNG_REVC_Register_Offsets Register Offsets 84 * @brief TRNG_REVC Peripheral Register Offsets from the TRNG_REVC Base Peripheral Address. 85 * @{ 86 */ 87 #define MXC_R_TRNG_REVC_CN ((uint32_t)0x00000000UL) /**< Offset from TRNG_REVC Base Address: <tt> 0x0000</tt> */ 88 #define MXC_R_TRNG_REVC_ST ((uint32_t)0x00000004UL) /**< Offset from TRNG_REVC Base Address: <tt> 0x0004</tt> */ 89 #define MXC_R_TRNG_REVC_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG_REVC Base Address: <tt> 0x0008</tt> */ 90 /**@} end of group trng_revc_registers */ 91 92 /** 93 * @ingroup trng_revc_registers 94 * @defgroup TRNG_REVC_CN TRNG_REVC_CN 95 * @brief TRNG Control Register. 96 * @{ 97 */ 98 #define MXC_F_TRNG_REVC_CN_ODHT_POS 0 /**< CN_ODHT Position */ 99 #define MXC_F_TRNG_REVC_CN_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_ODHT_POS)) /**< CN_ODHT Mask */ 100 101 #define MXC_F_TRNG_REVC_CN_RND_IRQ_EN_POS 1 /**< CN_RND_IRQ_EN Position */ 102 #define MXC_F_TRNG_REVC_CN_RND_IRQ_EN ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_RND_IRQ_EN_POS)) /**< CN_RND_IRQ_EN Mask */ 103 104 #define MXC_F_TRNG_REVC_CN_HEALTH_EN_POS 2 /**< CN_HEALTH_EN Position */ 105 #define MXC_F_TRNG_REVC_CN_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_HEALTH_EN_POS)) /**< CN_HEALTH_EN Mask */ 106 107 #define MXC_F_TRNG_REVC_CN_AESKG_MEU_POS 3 /**< CN_AESKG_MEU Position */ 108 #define MXC_F_TRNG_REVC_CN_AESKG_MEU ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_AESKG_MEU_POS)) /**< CN_AESKG_MEU Mask */ 109 110 #define MXC_F_TRNG_REVC_CN_AESKG_MEMPROTE_POS 4 /**< CN_AESKG_MEMPROTE Position */ 111 #define MXC_F_TRNG_REVC_CN_AESKG_MEMPROTE ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_AESKG_MEMPROTE_POS)) /**< CN_AESKG_MEMPROTE Mask */ 112 113 #define MXC_F_TRNG_REVC_CN_AESKG_MEMPROTA_POS 5 /**< CN_AESKG_MEMPROTA Position */ 114 #define MXC_F_TRNG_REVC_CN_AESKG_MEMPROTA ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_AESKG_MEMPROTA_POS)) /**< CN_AESKG_MEMPROTA Mask */ 115 116 #define MXC_F_TRNG_REVC_CN_RSV16_POS 16 /**< CN_RSV16 Position */ 117 #define MXC_F_TRNG_REVC_CN_RSV16 ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_RSV16_POS)) /**< CN_RSV16 Mask */ 118 119 #define MXC_F_TRNG_REVC_CN_RSV17_POS 17 /**< CN_RSV17 Position */ 120 #define MXC_F_TRNG_REVC_CN_RSV17 ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_CN_RSV17_POS)) /**< CN_RSV17 Mask */ 121 122 /**@} end of group TRNG_REVC_CN_Register */ 123 124 /** 125 * @ingroup trng_revc_registers 126 * @defgroup TRNG_REVC_ST TRNG_REVC_ST 127 * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is 128 * disabled, read returns 0x0000 0000. 129 * @{ 130 */ 131 #define MXC_F_TRNG_REVC_ST_RND_RDY_POS 0 /**< ST_RND_RDY Position */ 132 #define MXC_F_TRNG_REVC_ST_RND_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_ST_RND_RDY_POS)) /**< ST_RND_RDY Mask */ 133 134 #define MXC_F_TRNG_REVC_ST_ODHTS_POS 1 /**< ST_ODHTS Position */ 135 #define MXC_F_TRNG_REVC_ST_ODHTS ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_ST_ODHTS_POS)) /**< ST_ODHTS Mask */ 136 137 #define MXC_F_TRNG_REVC_ST_HTS_POS 2 /**< ST_HTS Position */ 138 #define MXC_F_TRNG_REVC_ST_HTS ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_ST_HTS_POS)) /**< ST_HTS Mask */ 139 140 #define MXC_F_TRNG_REVC_ST_SRCFAIL_POS 3 /**< ST_SRCFAIL Position */ 141 #define MXC_F_TRNG_REVC_ST_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_ST_SRCFAIL_POS)) /**< ST_SRCFAIL Mask */ 142 143 #define MXC_F_TRNG_REVC_ST_AESKGD_MEU_S_POS 4 /**< ST_AESKGD_MEU_S Position */ 144 #define MXC_F_TRNG_REVC_ST_AESKGD_MEU_S ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_ST_AESKGD_MEU_S_POS)) /**< ST_AESKGD_MEU_S Mask */ 145 146 #define MXC_F_TRNG_REVC_ST_RSV16_POS 16 /**< ST_RSV16 Position */ 147 #define MXC_F_TRNG_REVC_ST_RSV16 ((uint32_t)(0x1UL << MXC_F_TRNG_REVC_ST_RSV16_POS)) /**< ST_RSV16 Mask */ 148 149 /**@} end of group TRNG_REVC_ST_Register */ 150 151 /** 152 * @ingroup trng_revc_registers 153 * @defgroup TRNG_REVC_DATA TRNG_REVC_DATA 154 * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is 155 * disabled, read returns 0x0000 0000. 156 * @{ 157 */ 158 #define MXC_F_TRNG_REVC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 159 #define MXC_F_TRNG_REVC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_REVC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 160 161 /**@} end of group TRNG_REVC_DATA_Register */ 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif /* _TRNG_REVC_REGS_H_ */ 168
