1 /** 2 * @file tmr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _TMR_REVA_REGS_H_ 27 #define _TMR_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup tmr 65 * @defgroup tmr_registers TMR_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. 67 * @details 32-bit reloadable timer that can be used for timing and event counting. 68 */ 69 70 /** 71 * @ingroup tmr_registers 72 * Structure type to access the TMR Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR CNT Register */ 76 __IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR CMP Register */ 77 __IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR PWM Register */ 78 __IO uint32_t intr; /**< <tt>\b 0x0C:</tt> TMR INTR Register */ 79 __IO uint32_t cn; /**< <tt>\b 0x10:</tt> TMR CN Register */ 80 __IO uint32_t nolcmp; /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */ 81 } mxc_tmr_reva_regs_t; 82 83 /* Register offsets for module TMR */ 84 /** 85 * @ingroup tmr_registers 86 * @defgroup TMR_Register_Offsets Register Offsets 87 * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_TMR_REVA_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_TMR_REVA_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_TMR_REVA_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_TMR_REVA_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */ 94 #define MXC_R_TMR_REVA_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */ 95 #define MXC_R_TMR_REVA_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */ 96 /**@} end of group tmr_registers */ 97 98 /** 99 * @ingroup tmr_registers 100 * @defgroup TMR_INTR TMR_INTR 101 * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the 102 * associated interrupt. 103 * @{ 104 */ 105 #define MXC_F_TMR_REVA_INTR_IRQ_POS 0 /**< INTR_IRQ Position */ 106 #define MXC_F_TMR_REVA_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_REVA_INTR_IRQ_POS)) /**< INTR_IRQ Mask */ 107 108 /**@} end of group TMR_INTR_Register */ 109 110 /** 111 * @ingroup tmr_registers 112 * @defgroup TMR_CN TMR_CN 113 * @brief Timer Control Register. 114 * @{ 115 */ 116 #define MXC_F_TMR_REVA_CN_TMODE_POS 0 /**< CN_TMODE Position */ 117 #define MXC_F_TMR_REVA_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_REVA_CN_TMODE_POS)) /**< CN_TMODE Mask */ 118 #define MXC_V_TMR_REVA_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ 119 #define MXC_S_TMR_REVA_CN_TMODE_ONESHOT (MXC_V_TMR_REVA_CN_TMODE_ONESHOT << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ 120 #define MXC_V_TMR_REVA_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ 121 #define MXC_S_TMR_REVA_CN_TMODE_CONTINUOUS (MXC_V_TMR_REVA_CN_TMODE_CONTINUOUS << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ 122 #define MXC_V_TMR_REVA_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ 123 #define MXC_S_TMR_REVA_CN_TMODE_COUNTER (MXC_V_TMR_REVA_CN_TMODE_COUNTER << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ 124 #define MXC_V_TMR_REVA_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ 125 #define MXC_S_TMR_REVA_CN_TMODE_PWM (MXC_V_TMR_REVA_CN_TMODE_PWM << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ 126 #define MXC_V_TMR_REVA_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ 127 #define MXC_S_TMR_REVA_CN_TMODE_CAPTURE (MXC_V_TMR_REVA_CN_TMODE_CAPTURE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ 128 #define MXC_V_TMR_REVA_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ 129 #define MXC_S_TMR_REVA_CN_TMODE_COMPARE (MXC_V_TMR_REVA_CN_TMODE_COMPARE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ 130 #define MXC_V_TMR_REVA_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ 131 #define MXC_S_TMR_REVA_CN_TMODE_GATED (MXC_V_TMR_REVA_CN_TMODE_GATED << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ 132 #define MXC_V_TMR_REVA_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ 133 #define MXC_S_TMR_REVA_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_REVA_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ 134 135 #define MXC_F_TMR_REVA_CN_PRES_POS 3 /**< CN_PRES Position */ 136 #define MXC_F_TMR_REVA_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_REVA_CN_PRES_POS)) /**< CN_PRES Mask */ 137 #define MXC_V_TMR_REVA_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ 138 #define MXC_S_TMR_REVA_CN_PRES_DIV1 (MXC_V_TMR_REVA_CN_PRES_DIV1 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ 139 #define MXC_V_TMR_REVA_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ 140 #define MXC_S_TMR_REVA_CN_PRES_DIV2 (MXC_V_TMR_REVA_CN_PRES_DIV2 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ 141 #define MXC_V_TMR_REVA_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ 142 #define MXC_S_TMR_REVA_CN_PRES_DIV4 (MXC_V_TMR_REVA_CN_PRES_DIV4 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ 143 #define MXC_V_TMR_REVA_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ 144 #define MXC_S_TMR_REVA_CN_PRES_DIV8 (MXC_V_TMR_REVA_CN_PRES_DIV8 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ 145 #define MXC_V_TMR_REVA_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ 146 #define MXC_S_TMR_REVA_CN_PRES_DIV16 (MXC_V_TMR_REVA_CN_PRES_DIV16 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ 147 #define MXC_V_TMR_REVA_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ 148 #define MXC_S_TMR_REVA_CN_PRES_DIV32 (MXC_V_TMR_REVA_CN_PRES_DIV32 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ 149 #define MXC_V_TMR_REVA_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ 150 #define MXC_S_TMR_REVA_CN_PRES_DIV64 (MXC_V_TMR_REVA_CN_PRES_DIV64 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ 151 #define MXC_V_TMR_REVA_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */ 152 #define MXC_S_TMR_REVA_CN_PRES_DIV128 (MXC_V_TMR_REVA_CN_PRES_DIV128 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ 153 154 #define MXC_F_TMR_REVA_CN_TPOL_POS 6 /**< CN_TPOL Position */ 155 #define MXC_F_TMR_REVA_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_TPOL_POS)) /**< CN_TPOL Mask */ 156 157 #define MXC_F_TMR_REVA_CN_TEN_POS 7 /**< CN_TEN Position */ 158 #define MXC_F_TMR_REVA_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_TEN_POS)) /**< CN_TEN Mask */ 159 160 #define MXC_F_TMR_REVA_CN_PRES3_POS 8 /**< CN_PRES3 Position */ 161 #define MXC_F_TMR_REVA_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PRES3_POS)) /**< CN_PRES3 Mask */ 162 163 #define MXC_F_TMR_REVA_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ 164 #define MXC_F_TMR_REVA_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ 165 166 #define MXC_F_TMR_REVA_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ 167 #define MXC_F_TMR_REVA_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ 168 169 #define MXC_F_TMR_REVA_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ 170 #define MXC_F_TMR_REVA_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ 171 172 #define MXC_F_TMR_REVA_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ 173 #define MXC_F_TMR_REVA_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ 174 175 /**@} end of group TMR_CN_Register */ 176 177 /** 178 * @ingroup tmr_registers 179 * @defgroup TMR_NOLCMP TMR_NOLCMP 180 * @brief Timer Non-Overlapping Compare Register. 181 * @{ 182 */ 183 #define MXC_F_TMR_REVA_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ 184 #define MXC_F_TMR_REVA_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_REVA_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ 185 186 #define MXC_F_TMR_REVA_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ 187 #define MXC_F_TMR_REVA_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_REVA_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ 188 189 /**@} end of group TMR_NOLCMP_Register */ 190 191 #ifdef __cplusplus 192 } 193 #endif 194 195 #endif /* _TMR_REVA_REGS_H_ */ 196
