1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXR</name> 5 <description>SPIXR peripheral.</description> 6 <baseAddress>0x4003A000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>DATA32</name> 15 <description>Register for reading and writing the FIFO.</description> 16 <addressOffset>0x00</addressOffset> 17 <size>32</size> 18 <access>read-write</access> 19 <fields> 20 <field> 21 <name>DATA</name> 22 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 23 <bitOffset>0</bitOffset> 24 <bitWidth>32</bitWidth> 25 </field> 26 </fields> 27 </register> 28 <register> 29 <dim>2</dim> 30 <dimIncrement>2</dimIncrement> 31 <name>DATA16[%s]</name> 32 <description>Register for reading and writing the FIFO.</description> 33 <alternateRegister>DATA32</alternateRegister> 34 <addressOffset>0x00</addressOffset> 35 <size>16</size> 36 <access>read-write</access> 37 <fields> 38 <field> 39 <name>DATA</name> 40 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>16</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <dim>4</dim> 48 <dimIncrement>1</dimIncrement> 49 <name>DATA8[%s]</name> 50 <description>Register for reading and writing the FIFO.</description> 51 <alternateRegister>DATA32</alternateRegister> 52 <addressOffset>0x00</addressOffset> 53 <size>8</size> 54 <access>read-write</access> 55 <fields> 56 <field> 57 <name>DATA</name> 58 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 59 <bitOffset>0</bitOffset> 60 <bitWidth>8</bitWidth> 61 </field> 62 </fields> 63 </register> 64 <register> 65 <name>CTRL0</name> 66 <description>Register for controlling SPI peripheral.</description> 67 <addressOffset>0x04</addressOffset> 68 <access>read-write</access> 69 <fields> 70 <field> 71 <name>EN</name> 72 <description>SPI Enable.</description> 73 <bitOffset>0</bitOffset> 74 <bitWidth>1</bitWidth> 75 <enumeratedValues> 76 <enumeratedValue> 77 <name>dis</name> 78 <description>SPI is disabled.</description> 79 <value>0</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>en</name> 83 <description>SPI is enabled.</description> 84 <value>1</value> 85 </enumeratedValue> 86 </enumeratedValues> 87 </field> 88 <field> 89 <name>MSTR_EN</name> 90 <description>Master Mode Enable.</description> 91 <bitOffset>1</bitOffset> 92 <bitWidth>1</bitWidth> 93 <enumeratedValues> 94 <enumeratedValue> 95 <name>dis</name> 96 <description>SPI is Slave mode.</description> 97 <value>0</value> 98 </enumeratedValue> 99 <enumeratedValue> 100 <name>en</name> 101 <description>SPI is Master mode.</description> 102 <value>1</value> 103 </enumeratedValue> 104 </enumeratedValues> 105 </field> 106 <field> 107 <name>SSIO</name> 108 <description>Slave Select 0, IO direction, to support Multi-Master mode, 109 Slave Select 0 can be input in Master mode. This bit has no 110 effect in slave mode.</description> 111 <bitOffset>4</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>output</name> 116 <description>Slave select 0 is output.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>input</name> 121 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>TX_START</name> 128 <description>Start Transmit.</description> 129 <bitOffset>5</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>start</name> 134 <description>Master Initiates a transaction, this bit is 135 self clearing when transactions are done. If 136 a transaction completes, and the TX FIFO 137 is empty, the Master halts, if a transaction 138 completes, and the TX FIFO is not empty, 139 the Master initiates another transaction.</description> 140 <value>1</value> 141 </enumeratedValue> 142 </enumeratedValues> 143 </field> 144 <field> 145 <name>SS_CTRL</name> 146 <description>Slave Select Control.</description> 147 <bitOffset>8</bitOffset> 148 <bitWidth>1</bitWidth> 149 <enumeratedValues> 150 <enumeratedValue> 151 <name>deassert</name> 152 <description>SPI de-asserts Slave Select at the end of a transaction.</description> 153 <value>0</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>assert</name> 157 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 158 <value>1</value> 159 </enumeratedValue> 160 </enumeratedValues> 161 </field> 162 <field> 163 <name>SS</name> 164 <description>Slave Select, when in Master mode selects which Slave devices are 165 selected. More than one Slave device can be selected.</description> 166 <bitOffset>16</bitOffset> 167 <bitWidth>1</bitWidth> 168 <enumeratedValues> 169 <enumeratedValue> 170 <name>SS0</name> 171 <description>Slave Select 0</description> 172 <value>1</value> 173 </enumeratedValue> 174 </enumeratedValues> 175 </field> 176 </fields> 177 </register> 178 <register> 179 <name>CTRL1</name> 180 <description>Register for controlling SPI peripheral.</description> 181 <addressOffset>0x08</addressOffset> 182 <access>read-write</access> 183 <fields> 184 <field> 185 <name>TX_NUM_CHAR</name> 186 <description>Nubmer of Characters to transmit.</description> 187 <bitOffset>0</bitOffset> 188 <bitWidth>16</bitWidth> 189 </field> 190 <field> 191 <name>RX_NUM_CHAR</name> 192 <description>Nubmer of Characters to receive.</description> 193 <bitOffset>16</bitOffset> 194 <bitWidth>16</bitWidth> 195 </field> 196 </fields> 197 </register> 198 <register> 199 <name>CTRL2</name> 200 <description>Register for controlling SPI peripheral.</description> 201 <addressOffset>0x0C</addressOffset> 202 <access>read-write</access> 203 <fields> 204 <field> 205 <name>CPHA</name> 206 <description>Clock Phase.</description> 207 <bitOffset>0</bitOffset> 208 <bitWidth>1</bitWidth> 209 </field> 210 <field> 211 <name>CPOL</name> 212 <description>Clock Polarity.</description> 213 <bitOffset>1</bitOffset> 214 <bitWidth>1</bitWidth> 215 </field> 216 <field> 217 <name>SCLK_FB_INV</name> 218 <description>Invert SCLK Feedback in Master Mode.</description> 219 <bitOffset>4</bitOffset> 220 <bitWidth>1</bitWidth> 221 <enumeratedValues> 222 <enumeratedValue> 223 <name>NON_INV</name> 224 <description>SCLK is not inverted to Line Receiver.</description> 225 <value>0</value> 226 </enumeratedValue> 227 <enumeratedValue> 228 <name>INV</name> 229 <description>SCLK is inverted to Line Receiver.</description> 230 <value>1</value> 231 </enumeratedValue> 232 </enumeratedValues> 233 </field> 234 <field> 235 <name>NUMBITS</name> 236 <description>Number of Bits per character.</description> 237 <bitOffset>8</bitOffset> 238 <bitWidth>4</bitWidth> 239 <enumeratedValues> 240 <enumeratedValue> 241 <name>0</name> 242 <description>16 bits per character.</description> 243 <value>0</value> 244 </enumeratedValue> 245 </enumeratedValues> 246 </field> 247 <field> 248 <name>DATA_WIDTH</name> 249 <description>SPI Data width.</description> 250 <bitOffset>12</bitOffset> 251 <bitWidth>2</bitWidth> 252 <enumeratedValues> 253 <enumeratedValue> 254 <name>Mono</name> 255 <description>1 data pin.</description> 256 <value>0</value> 257 </enumeratedValue> 258 <enumeratedValue> 259 <name>Dual</name> 260 <description>2 data pins.</description> 261 <value>1</value> 262 </enumeratedValue> 263 <enumeratedValue> 264 <name>Quad</name> 265 <description>4 data pins.</description> 266 <value>2</value> 267 </enumeratedValue> 268 </enumeratedValues> 269 </field> 270 <field> 271 <name>THREE_WIRE</name> 272 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 273 <bitOffset>15</bitOffset> 274 <bitWidth>1</bitWidth> 275 <enumeratedValues> 276 <enumeratedValue> 277 <name>dis</name> 278 <description>Use four wire mode (Mono only).</description> 279 <value>0</value> 280 </enumeratedValue> 281 <enumeratedValue> 282 <name>en</name> 283 <description>Use three wire mode.</description> 284 <value>1</value> 285 </enumeratedValue> 286 </enumeratedValues> 287 </field> 288 <field> 289 <name>SSPOL</name> 290 <description>Slave Select Polarity</description> 291 <bitOffset>16</bitOffset> 292 <bitWidth>1</bitWidth> 293 </field> 294 </fields> 295 </register> 296 <register> 297 <name>CTRL3</name> 298 <description>Register for controlling SPI peripheral.</description> 299 <addressOffset>0x10</addressOffset> 300 <access>read-write</access> 301 <fields> 302 <field> 303 <name>SSACT1</name> 304 <description>Slave Select Action delay 1.</description> 305 <bitOffset>0</bitOffset> 306 <bitWidth>8</bitWidth> 307 <enumeratedValues> 308 <enumeratedValue> 309 <name>256</name> 310 <description>256 system clocks between SS active and first serial clock edge.</description> 311 <value>0</value> 312 </enumeratedValue> 313 </enumeratedValues> 314 </field> 315 <field> 316 <name>SSACT2</name> 317 <description>Slave Select Action delay 2.</description> 318 <bitOffset>8</bitOffset> 319 <bitWidth>8</bitWidth> 320 <enumeratedValues> 321 <enumeratedValue> 322 <name>256</name> 323 <description>256 system clocks between last serial clock edge and SS inactive.</description> 324 <value>0</value> 325 </enumeratedValue> 326 </enumeratedValues> 327 </field> 328 <field> 329 <name>SSIACT</name> 330 <description>Slave Select Inactive delay.</description> 331 <bitOffset>16</bitOffset> 332 <bitWidth>8</bitWidth> 333 <enumeratedValues> 334 <enumeratedValue> 335 <name>256</name> 336 <description>256 system clocks between transactions.</description> 337 <value>0</value> 338 </enumeratedValue> 339 </enumeratedValues> 340 </field> 341 </fields> 342 </register> 343 <register> 344 <name>BRGCTRL</name> 345 <description>Register for controlling SPI clock rate.</description> 346 <addressOffset>0x14</addressOffset> 347 <access>read-write</access> 348 <fields> 349 <field> 350 <name>LOW</name> 351 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 352 <bitOffset>0</bitOffset> 353 <bitWidth>8</bitWidth> 354 <enumeratedValues> 355 <enumeratedValue> 356 <name>Dis</name> 357 <description>Duty cycle control of serial clock generation is disabled.</description> 358 <value>0</value> 359 </enumeratedValue> 360 </enumeratedValues> 361 </field> 362 <field> 363 <name>HIGH</name> 364 <description>High duty cycle control. In timer mode, reload[15:8].</description> 365 <bitOffset>8</bitOffset> 366 <bitWidth>8</bitWidth> 367 <enumeratedValues> 368 <enumeratedValue> 369 <name>Dis</name> 370 <description>Duty cycle control of serial clock generation is disabled.</description> 371 <value>0</value> 372 </enumeratedValue> 373 </enumeratedValues> 374 </field> 375 <field> 376 <name>SCALE</name> 377 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 378 <bitOffset>16</bitOffset> 379 <bitWidth>4</bitWidth> 380 </field> 381 </fields> 382 </register> 383 <register> 384 <name>DMA</name> 385 <description>Register for controlling DMA.</description> 386 <addressOffset>0x1C</addressOffset> 387 <access>read-write</access> 388 <fields> 389 <field> 390 <name>TX_FIFO_LVL</name> 391 <description>Transmit FIFO level that will trigger a DMA request, also level for 392 threshold status. When TX FIFO has fewer than this many bytes, the 393 associated events and conditions are triggered.</description> 394 <bitOffset>0</bitOffset> 395 <bitWidth>6</bitWidth> 396 </field> 397 <field> 398 <name>TX_FIFO_EN</name> 399 <description>Transmit FIFO enabled for SPI transactions.</description> 400 <bitOffset>6</bitOffset> 401 <bitWidth>1</bitWidth> 402 <enumeratedValues> 403 <enumeratedValue> 404 <name>dis</name> 405 <description>Transmit FIFO is not enabled.</description> 406 <value>0</value> 407 </enumeratedValue> 408 <enumeratedValue> 409 <name>en</name> 410 <description>Transmit FIFO is enabled.</description> 411 <value>1</value> 412 </enumeratedValue> 413 </enumeratedValues> 414 </field> 415 <field> 416 <name>TX_FIFO_CLEAR</name> 417 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 418 pointers. This should be done when FIFO is not being accessed on the SPI side. 419 </description> 420 <bitOffset>7</bitOffset> 421 <bitWidth>1</bitWidth> 422 <enumeratedValues> 423 <enumeratedValue> 424 <name>CLEAR</name> 425 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 426 <value>1</value> 427 </enumeratedValue> 428 </enumeratedValues> 429 </field> 430 <field> 431 <name>TX_FIFO_CNT</name> 432 <description>Count of entries in TX FIFO.</description> 433 <bitOffset>8</bitOffset> 434 <bitWidth>5</bitWidth> 435 </field> 436 <field> 437 <name>DMA_TX_EN</name> 438 <description>TX DMA Enable.</description> 439 <bitOffset>15</bitOffset> 440 <bitWidth>1</bitWidth> 441 <enumeratedValues> 442 <enumeratedValue> 443 <name>DIS</name> 444 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 445 <value>0</value> 446 </enumeratedValue> 447 <enumeratedValue> 448 <name>en</name> 449 <description>TX DMA requests are enabled.</description> 450 <value>1</value> 451 </enumeratedValue> 452 </enumeratedValues> 453 </field> 454 <field> 455 <name>RX_FIFO_LVL</name> 456 <description>Receive FIFO level that will trigger a DMA request, also level for 457 threshold status. When RX FIFO has more than this many bytes, the 458 associated events and conditions are triggered.</description> 459 <bitOffset>16</bitOffset> 460 <bitWidth>6</bitWidth> 461 </field> 462 <field> 463 <name>RX_FIFO_EN</name> 464 <description>Receive FIFO enabled for SPI transactions.</description> 465 <bitOffset>22</bitOffset> 466 <bitWidth>1</bitWidth> 467 <enumeratedValues> 468 <enumeratedValue> 469 <name>DIS</name> 470 <description>Receive FIFO is not enabled.</description> 471 <value>0</value> 472 </enumeratedValue> 473 <enumeratedValue> 474 <name>en</name> 475 <description>Receive FIFO is enabled.</description> 476 <value>1</value> 477 </enumeratedValue> 478 </enumeratedValues> 479 </field> 480 <field> 481 <name>RX_FIFO_CLR</name> 482 <description>Clear RX FIFO, clear is accomplished by resetting the read and write 483 pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 484 <bitOffset>23</bitOffset> 485 <bitWidth>1</bitWidth> 486 <enumeratedValues> 487 <enumeratedValue> 488 <name>CLEAR</name> 489 <description>Clear the Receive FIFIO, clears any pending RX FIFO status.</description> 490 <value>1</value> 491 </enumeratedValue> 492 </enumeratedValues> 493 </field> 494 <field> 495 <name>RX_FIFO_CNT</name> 496 <description>Count of entries in RX FIFO.</description> 497 <bitOffset>24</bitOffset> 498 <bitWidth>6</bitWidth> 499 </field> 500 <field> 501 <name>DMA_RX_EN</name> 502 <description>RX DMA Enable.</description> 503 <bitOffset>31</bitOffset> 504 <bitWidth>1</bitWidth> 505 <enumeratedValues> 506 <enumeratedValue> 507 <name>dis</name> 508 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 509 <value>0</value> 510 </enumeratedValue> 511 <enumeratedValue> 512 <name>en</name> 513 <description>RX DMA requests are enabled.</description> 514 <value>1</value> 515 </enumeratedValue> 516 </enumeratedValues> 517 </field> 518 </fields> 519 </register> 520 <register> 521 <name>INTFL</name> 522 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 523 <addressOffset>0x20</addressOffset> 524 <access>read-write</access> 525 <fields> 526 <field> 527 <name>TX_THRESH</name> 528 <description>TX FIFO Threshold Crossed.</description> 529 <bitOffset>0</bitOffset> 530 <bitWidth>1</bitWidth> 531 <enumeratedValues> 532 <enumeratedValue> 533 <name>clear</name> 534 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 535 <value>1</value> 536 </enumeratedValue> 537 </enumeratedValues> 538 </field> 539 <field> 540 <name>TX_EMPTY</name> 541 <description>TX FIFO Empty.</description> 542 <bitOffset>1</bitOffset> 543 <bitWidth>1</bitWidth> 544 <enumeratedValues> 545 <enumeratedValue> 546 <name>clear</name> 547 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 548 <value>1</value> 549 </enumeratedValue> 550 </enumeratedValues> 551 </field> 552 <field> 553 <name>RX_THRESH</name> 554 <description>RX FIFO Threshold Crossed.</description> 555 <bitOffset>2</bitOffset> 556 <bitWidth>1</bitWidth> 557 <enumeratedValues> 558 <enumeratedValue> 559 <name>clear</name> 560 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 561 <value>1</value> 562 </enumeratedValue> 563 </enumeratedValues> 564 </field> 565 <field> 566 <name>RX_FULL</name> 567 <description>RX FIFO FULL.</description> 568 <bitOffset>3</bitOffset> 569 <bitWidth>1</bitWidth> 570 <enumeratedValues> 571 <enumeratedValue> 572 <name>clear</name> 573 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 574 <value>1</value> 575 </enumeratedValue> 576 </enumeratedValues> 577 </field> 578 <field> 579 <name>SSA</name> 580 <description>Slave Select Asserted.</description> 581 <bitOffset>4</bitOffset> 582 <bitWidth>1</bitWidth> 583 <enumeratedValues> 584 <enumeratedValue> 585 <name>clear</name> 586 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 587 <value>1</value> 588 </enumeratedValue> 589 </enumeratedValues> 590 </field> 591 <field> 592 <name>SSD</name> 593 <description>Slave Select Deasserted.</description> 594 <bitOffset>5</bitOffset> 595 <bitWidth>1</bitWidth> 596 <enumeratedValues> 597 <enumeratedValue> 598 <name>clear</name> 599 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 600 <value>1</value> 601 </enumeratedValue> 602 </enumeratedValues> 603 </field> 604 <field> 605 <name>FAULT</name> 606 <description>Multi-Master Mode Fault.</description> 607 <bitOffset>8</bitOffset> 608 <bitWidth>1</bitWidth> 609 <enumeratedValues> 610 <enumeratedValue> 611 <name>clear</name> 612 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 613 <value>1</value> 614 </enumeratedValue> 615 </enumeratedValues> 616 </field> 617 <field> 618 <name>ABORT</name> 619 <description>Slave Abort Detected.</description> 620 <bitOffset>9</bitOffset> 621 <bitWidth>1</bitWidth> 622 <enumeratedValues> 623 <enumeratedValue> 624 <name>clear</name> 625 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 626 <value>1</value> 627 </enumeratedValue> 628 </enumeratedValues> 629 </field> 630 <field> 631 <name>M_DONE</name> 632 <description>Master Done, set when SPI Master has completed any transactions.</description> 633 <bitOffset>11</bitOffset> 634 <bitWidth>1</bitWidth> 635 <enumeratedValues> 636 <enumeratedValue> 637 <name>clear</name> 638 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 639 <value>1</value> 640 </enumeratedValue> 641 </enumeratedValues> 642 </field> 643 <field> 644 <name>TX_OVR</name> 645 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data 646 to a full transmit FIFO.</description> 647 <bitOffset>12</bitOffset> 648 <bitWidth>1</bitWidth> 649 <enumeratedValues> 650 <enumeratedValue> 651 <name>clear</name> 652 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 653 <value>1</value> 654 </enumeratedValue> 655 </enumeratedValues> 656 </field> 657 <field> 658 <name>TX_UND</name> 659 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data 660 from an empty transmit FIFO.</description> 661 <bitOffset>13</bitOffset> 662 <bitWidth>1</bitWidth> 663 <enumeratedValues> 664 <enumeratedValue> 665 <name>clear</name> 666 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 667 <value>1</value> 668 </enumeratedValue> 669 </enumeratedValues> 670 </field> 671 <field> 672 <name>RX_OVR</name> 673 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 674 <bitOffset>14</bitOffset> 675 <bitWidth>1</bitWidth> 676 <enumeratedValues> 677 <enumeratedValue> 678 <name>clear</name> 679 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 680 <value>1</value> 681 </enumeratedValue> 682 </enumeratedValues> 683 </field> 684 <field> 685 <name>RX_UND</name> 686 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 687 <bitOffset>15</bitOffset> 688 <bitWidth>1</bitWidth> 689 <enumeratedValues> 690 <enumeratedValue> 691 <name>clear</name> 692 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 693 <value>1</value> 694 </enumeratedValue> 695 </enumeratedValues> 696 </field> 697 </fields> 698 </register> 699 <register> 700 <name>INTEN</name> 701 <description>Register for enabling interrupts.</description> 702 <addressOffset>0x24</addressOffset> 703 <access>read-write</access> 704 <fields> 705 <field> 706 <name>TX_THRESH</name> 707 <description>TX FIFO Threshold interrupt enable.</description> 708 <bitOffset>0</bitOffset> 709 <bitWidth>1</bitWidth> 710 <enumeratedValues> 711 <enumeratedValue> 712 <name>dis</name> 713 <description>Interrupt is disabled.</description> 714 <value>0</value> 715 </enumeratedValue> 716 <enumeratedValue> 717 <name>en</name> 718 <description>Interrupt is enabled.</description> 719 <value>1</value> 720 </enumeratedValue> 721 </enumeratedValues> 722 </field> 723 <field> 724 <name>TX_EMPTY</name> 725 <description>TX FIFO Empty interrupt enable.</description> 726 <bitOffset>1</bitOffset> 727 <bitWidth>1</bitWidth> 728 <enumeratedValues> 729 <enumeratedValue> 730 <name>dis</name> 731 <description>Interrupt is disabled.</description> 732 <value>0</value> 733 </enumeratedValue> 734 <enumeratedValue> 735 <name>en</name> 736 <description>Interrupt is enabled.</description> 737 <value>1</value> 738 </enumeratedValue> 739 </enumeratedValues> 740 </field> 741 <field> 742 <name>RX_THRESH</name> 743 <description>RX FIFO Threshold Crossed interrupt enable.</description> 744 <bitOffset>2</bitOffset> 745 <bitWidth>1</bitWidth> 746 <enumeratedValues> 747 <enumeratedValue> 748 <name>dis</name> 749 <description>Interrupt is disabled.</description> 750 <value>0</value> 751 </enumeratedValue> 752 <enumeratedValue> 753 <name>en</name> 754 <description>Interrupt is enabled.</description> 755 <value>1</value> 756 </enumeratedValue> 757 </enumeratedValues> 758 </field> 759 <field> 760 <name>RX_FULL</name> 761 <description>RX FIFO FULL interrupt enable.</description> 762 <bitOffset>3</bitOffset> 763 <bitWidth>1</bitWidth> 764 <enumeratedValues> 765 <enumeratedValue> 766 <name>dis</name> 767 <description>Interrupt is disabled.</description> 768 <value>0</value> 769 </enumeratedValue> 770 <enumeratedValue> 771 <name>en</name> 772 <description>Interrupt is enabled.</description> 773 <value>1</value> 774 </enumeratedValue> 775 </enumeratedValues> 776 </field> 777 <field> 778 <name>SSA</name> 779 <description>Slave Select Asserted interrupt enable.</description> 780 <bitOffset>4</bitOffset> 781 <bitWidth>1</bitWidth> 782 <enumeratedValues> 783 <enumeratedValue> 784 <name>dis</name> 785 <description>Interrupt is disabled.</description> 786 <value>0</value> 787 </enumeratedValue> 788 <enumeratedValue> 789 <name>en</name> 790 <description>Interrupt is enabled.</description> 791 <value>1</value> 792 </enumeratedValue> 793 </enumeratedValues> 794 </field> 795 <field> 796 <name>SSD</name> 797 <description>Slave Select Deasserted interrupt enable.</description> 798 <bitOffset>5</bitOffset> 799 <bitWidth>1</bitWidth> 800 <enumeratedValues> 801 <enumeratedValue> 802 <name>dis</name> 803 <description>Interrupt is disabled.</description> 804 <value>0</value> 805 </enumeratedValue> 806 <enumeratedValue> 807 <name>en</name> 808 <description>Interrupt is enabled.</description> 809 <value>1</value> 810 </enumeratedValue> 811 </enumeratedValues> 812 </field> 813 <field> 814 <name>FAULT</name> 815 <description>Multi-Master Mode Fault interrupt enable.</description> 816 <bitOffset>8</bitOffset> 817 <bitWidth>1</bitWidth> 818 <enumeratedValues> 819 <enumeratedValue> 820 <name>dis</name> 821 <description>Interrupt is disabled.</description> 822 <value>0</value> 823 </enumeratedValue> 824 <enumeratedValue> 825 <name>en</name> 826 <description>Interrupt is enabled.</description> 827 <value>1</value> 828 </enumeratedValue> 829 </enumeratedValues> 830 </field> 831 <field> 832 <name>ABORT</name> 833 <description>Slave Abort Detected interrupt enable.</description> 834 <bitOffset>9</bitOffset> 835 <bitWidth>1</bitWidth> 836 <enumeratedValues> 837 <enumeratedValue> 838 <name>dis</name> 839 <description>Interrupt is disabled.</description> 840 <value>0</value> 841 </enumeratedValue> 842 <enumeratedValue> 843 <name>en</name> 844 <description>Interrupt is enabled.</description> 845 <value>1</value> 846 </enumeratedValue> 847 </enumeratedValues> 848 </field> 849 <field> 850 <name>M_DONE</name> 851 <description>Master Done interrupt enable.</description> 852 <bitOffset>11</bitOffset> 853 <bitWidth>1</bitWidth> 854 <enumeratedValues> 855 <enumeratedValue> 856 <name>dis</name> 857 <description>Interrupt is disabled.</description> 858 <value>0</value> 859 </enumeratedValue> 860 <enumeratedValue> 861 <name>en</name> 862 <description>Interrupt is enabled.</description> 863 <value>1</value> 864 </enumeratedValue> 865 </enumeratedValues> 866 </field> 867 <field> 868 <name>TX_OVR</name> 869 <description>Transmit FIFO Overrun interrupt enable.</description> 870 <bitOffset>12</bitOffset> 871 <bitWidth>1</bitWidth> 872 <enumeratedValues> 873 <enumeratedValue> 874 <name>dis</name> 875 <description>Interrupt is disabled.</description> 876 <value>0</value> 877 </enumeratedValue> 878 <enumeratedValue> 879 <name>en</name> 880 <description>Interrupt is enabled.</description> 881 <value>1</value> 882 </enumeratedValue> 883 </enumeratedValues> 884 </field> 885 <field> 886 <name>TX_UND</name> 887 <description>Transmit FIFO Underrun interrupt enable.</description> 888 <bitOffset>13</bitOffset> 889 <bitWidth>1</bitWidth> 890 <enumeratedValues> 891 <enumeratedValue> 892 <name>dis</name> 893 <description>Interrupt is disabled.</description> 894 <value>0</value> 895 </enumeratedValue> 896 <enumeratedValue> 897 <name>en</name> 898 <description>Interrupt is enabled.</description> 899 <value>1</value> 900 </enumeratedValue> 901 </enumeratedValues> 902 </field> 903 <field> 904 <name>RX_OVR</name> 905 <description>Receive FIFO Overrun interrupt enable.</description> 906 <bitOffset>14</bitOffset> 907 <bitWidth>1</bitWidth> 908 <enumeratedValues> 909 <enumeratedValue> 910 <name>dis</name> 911 <description>Interrupt is disabled.</description> 912 <value>0</value> 913 </enumeratedValue> 914 <enumeratedValue> 915 <name>en</name> 916 <description>Interrupt is enabled.</description> 917 <value>1</value> 918 </enumeratedValue> 919 </enumeratedValues> 920 </field> 921 <field> 922 <name>RX_UND</name> 923 <description>Receive FIFO Underrun interrupt enable.</description> 924 <bitOffset>15</bitOffset> 925 <bitWidth>1</bitWidth> 926 <enumeratedValues> 927 <enumeratedValue> 928 <name>dis</name> 929 <description>Interrupt is disabled.</description> 930 <value>0</value> 931 </enumeratedValue> 932 <enumeratedValue> 933 <name>en</name> 934 <description>Interrupt is enabled.</description> 935 <value>1</value> 936 </enumeratedValue> 937 </enumeratedValues> 938 </field> 939 </fields> 940 </register> 941 <register> 942 <name>WKFL</name> 943 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 944 <addressOffset>0x28</addressOffset> 945 <access>read-write</access> 946 <fields> 947 <field> 948 <name>TX_THRESH</name> 949 <description>Wake on TX FIFO Threshold Crossed.</description> 950 <bitOffset>0</bitOffset> 951 <bitWidth>1</bitWidth> 952 <enumeratedValues> 953 <enumeratedValue> 954 <name>clear</name> 955 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 956 <value>1</value> 957 </enumeratedValue> 958 </enumeratedValues> 959 </field> 960 <field> 961 <name>TX_EM</name> 962 <description>Wake on TX FIFO Empty.</description> 963 <bitOffset>1</bitOffset> 964 <bitWidth>1</bitWidth> 965 <enumeratedValues> 966 <enumeratedValue> 967 <name>clear</name> 968 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 969 <value>1</value> 970 </enumeratedValue> 971 </enumeratedValues> 972 </field> 973 <field> 974 <name>RX_THRESH</name> 975 <description>Wake on RX FIFO Threshold Crossed.</description> 976 <bitOffset>2</bitOffset> 977 <bitWidth>1</bitWidth> 978 <enumeratedValues> 979 <enumeratedValue> 980 <name>clear</name> 981 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 982 <value>1</value> 983 </enumeratedValue> 984 </enumeratedValues> 985 </field> 986 <field> 987 <name>RX_FULL</name> 988 <description>Wake on RX FIFO Full.</description> 989 <bitOffset>3</bitOffset> 990 <bitWidth>1</bitWidth> 991 <enumeratedValues> 992 <enumeratedValue> 993 <name>clear</name> 994 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 995 <value>1</value> 996 </enumeratedValue> 997 </enumeratedValues> 998 </field> 999 </fields> 1000 </register> 1001 <register> 1002 <name>WKEN</name> 1003 <description>Register for wake up enable.</description> 1004 <addressOffset>0x2C</addressOffset> 1005 <access>read-write</access> 1006 <fields> 1007 <field> 1008 <name>TX_THRESH</name> 1009 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1010 <bitOffset>0</bitOffset> 1011 <bitWidth>1</bitWidth> 1012 <enumeratedValues> 1013 <enumeratedValue> 1014 <name>dis</name> 1015 <description>Wakeup source disabled.</description> 1016 <value>0</value> 1017 </enumeratedValue> 1018 <enumeratedValue> 1019 <name>en</name> 1020 <description>Wakeup source enabled.</description> 1021 <value>1</value> 1022 </enumeratedValue> 1023 </enumeratedValues> 1024 </field> 1025 <field> 1026 <name>TX_EM</name> 1027 <description>Wake on TX FIFO Empty Enable.</description> 1028 <bitOffset>1</bitOffset> 1029 <bitWidth>1</bitWidth> 1030 <enumeratedValues> 1031 <enumeratedValue> 1032 <name>dis</name> 1033 <description>Wakeup source disabled.</description> 1034 <value>0</value> 1035 </enumeratedValue> 1036 <enumeratedValue> 1037 <name>en</name> 1038 <description>Wakeup source enabled.</description> 1039 <value>1</value> 1040 </enumeratedValue> 1041 </enumeratedValues> 1042 </field> 1043 <field> 1044 <name>RX_THRESH</name> 1045 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1046 <bitOffset>2</bitOffset> 1047 <bitWidth>1</bitWidth> 1048 <enumeratedValues> 1049 <enumeratedValue> 1050 <name>dis</name> 1051 <description>Wakeup source disabled.</description> 1052 <value>0</value> 1053 </enumeratedValue> 1054 <enumeratedValue> 1055 <name>en</name> 1056 <description>Wakeup source enabled.</description> 1057 <value>1</value> 1058 </enumeratedValue> 1059 </enumeratedValues> 1060 </field> 1061 <field> 1062 <name>RX_FULL</name> 1063 <description>Wake on RX FIFO Full Enable.</description> 1064 <bitOffset>3</bitOffset> 1065 <bitWidth>1</bitWidth> 1066 <enumeratedValues> 1067 <enumeratedValue> 1068 <name>dis</name> 1069 <description>Wakeup source disabled.</description> 1070 <value>0</value> 1071 </enumeratedValue> 1072 <enumeratedValue> 1073 <name>en</name> 1074 <description>Wakeup source enabled.</description> 1075 <value>1</value> 1076 </enumeratedValue> 1077 </enumeratedValues> 1078 </field> 1079 </fields> 1080 </register> 1081 <register> 1082 <name>STAT</name> 1083 <description>SPI Status register.</description> 1084 <addressOffset>0x30</addressOffset> 1085 <access>read-only</access> 1086 <fields> 1087 <field> 1088 <name>BUSY</name> 1089 <description>SPI active status. In Master mode, set when transaction starts, 1090 cleared when last bit of last character is acted upon and Slave Select 1091 de-assertion would occur. In Slave mode, set when Slave Select is 1092 asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 1093 </description> 1094 <bitOffset>0</bitOffset> 1095 <bitWidth>1</bitWidth> 1096 <enumeratedValues> 1097 <enumeratedValue> 1098 <name>not</name> 1099 <description>SPI not active.</description> 1100 <value>0</value> 1101 </enumeratedValue> 1102 <enumeratedValue> 1103 <name>active</name> 1104 <description>SPI active.</description> 1105 <value>1</value> 1106 </enumeratedValue> 1107 </enumeratedValues> 1108 </field> 1109 </fields> 1110 </register> 1111 <register> 1112 <name>XMEMCTRL</name> 1113 <description>Register to control external memory.</description> 1114 <addressOffset>0x34</addressOffset> 1115 <access>read-write</access> 1116 <fields> 1117 <field> 1118 <name>RD_CMD</name> 1119 <description>Read command.</description> 1120 <bitOffset>0</bitOffset> 1121 <bitWidth>8</bitWidth> 1122 </field> 1123 <field> 1124 <name>WR_CMD</name> 1125 <description>Write command.</description> 1126 <bitOffset>8</bitOffset> 1127 <bitWidth>8</bitWidth> 1128 </field> 1129 <field> 1130 <name>DUMMY_CLK</name> 1131 <description>Dummy clocks.</description> 1132 <bitOffset>16</bitOffset> 1133 <bitWidth>8</bitWidth> 1134 </field> 1135 <field> 1136 <name>XMEM_EN</name> 1137 <description>XMEM enable.</description> 1138 <bitOffset>31</bitOffset> 1139 <bitWidth>1</bitWidth> 1140 </field> 1141 </fields> 1142 </register> 1143 </registers> 1144 </peripheral> 1145 <!-- SPIXR for Data XIP interface --> 1146</device>
