1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXR</name> 5 <description>SPIXR peripheral.</description> 6 <baseAddress>0x4003A000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>DATA32</name> 15 <description>Register for reading and writing the FIFO.</description> 16 <addressOffset>0x00</addressOffset> 17 <size>32</size> 18 <access>read-write</access> 19 <fields> 20 <field> 21 <name>DATA</name> 22 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 23 <bitOffset>0</bitOffset> 24 <bitWidth>32</bitWidth> 25 </field> 26 </fields> 27 </register> 28 <register> 29 <dim>2</dim> 30 <dimIncrement>2</dimIncrement> 31 <name>DATA16[%s]</name> 32 <description>Register for reading and writing the FIFO.</description> 33 <alternateRegister>DATA32</alternateRegister> 34 <addressOffset>0x00</addressOffset> 35 <size>16</size> 36 <access>read-write</access> 37 <fields> 38 <field> 39 <name>DATA</name> 40 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>16</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <dim>4</dim> 48 <dimIncrement>1</dimIncrement> 49 <name>DATA8[%s]</name> 50 <description>Register for reading and writing the FIFO.</description> 51 <alternateRegister>DATA32</alternateRegister> 52 <addressOffset>0x00</addressOffset> 53 <size>8</size> 54 <access>read-write</access> 55 <fields> 56 <field> 57 <name>DATA</name> 58 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 59 <bitOffset>0</bitOffset> 60 <bitWidth>8</bitWidth> 61 </field> 62 </fields> 63 </register> 64 <register> 65 <name>CTRL1</name> 66 <description>Register for controlling SPI peripheral.</description> 67 <addressOffset>0x04</addressOffset> 68 <access>read-write</access> 69 <fields> 70 <field> 71 <name>SPIEN</name> 72 <description>SPI Enable.</description> 73 <bitOffset>0</bitOffset> 74 <bitWidth>1</bitWidth> 75 <enumeratedValues> 76 <enumeratedValue> 77 <name>dis</name> 78 <description>SPI is disabled.</description> 79 <value>0</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>en</name> 83 <description>SPI is enabled.</description> 84 <value>1</value> 85 </enumeratedValue> 86 </enumeratedValues> 87 </field> 88 <field> 89 <name>MMEN</name> 90 <description>Master Mode Enable.</description> 91 <bitOffset>1</bitOffset> 92 <bitWidth>1</bitWidth> 93 <enumeratedValues> 94 <enumeratedValue> 95 <name>dis</name> 96 <description>SPI is Slave mode.</description> 97 <value>0</value> 98 </enumeratedValue> 99 <enumeratedValue> 100 <name>en</name> 101 <description>SPI is Master mode.</description> 102 <value>1</value> 103 </enumeratedValue> 104 </enumeratedValues> 105 </field> 106 <field> 107 <name>TIMER</name> 108 <description>Timer Enable.</description> 109 <bitOffset>2</bitOffset> 110 <bitWidth>1</bitWidth> 111 <enumeratedValues> 112 <enumeratedValue> 113 <name>dis</name> 114 <description>Timer is disabled.</description> 115 <value>0</value> 116 </enumeratedValue> 117 <enumeratedValue> 118 <name>en</name> 119 <description>Timer is enabled, only valid if SPIEN=0.</description> 120 <value>1</value> 121 </enumeratedValue> 122 </enumeratedValues> 123 </field> 124 <field> 125 <name>FL_EN</name> 126 <description>Flow Control Mode Enable.</description> 127 <bitOffset>3</bitOffset> 128 <bitWidth>1</bitWidth> 129 <enumeratedValues> 130 <enumeratedValue> 131 <name>dis</name> 132 <description>Flow Control mode is disabled.</description> 133 <value>0</value> 134 </enumeratedValue> 135 <enumeratedValue> 136 <name>en</name> 137 <description>Flow Control Mode is enabled.</description> 138 <value>1</value> 139 </enumeratedValue> 140 </enumeratedValues> 141 </field> 142 <field> 143 <name>SSIO</name> 144 <description>Slave Select 0, IO direction, to support Multi-Master mode, 145 Slave Select 0 can be input in Master mode. This bit has no 146 effect in slave mode.</description> 147 <bitOffset>4</bitOffset> 148 <bitWidth>1</bitWidth> 149 <enumeratedValues> 150 <enumeratedValue> 151 <name>output</name> 152 <description>Slave select 0 is output.</description> 153 <value>0</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>input</name> 157 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 158 <value>1</value> 159 </enumeratedValue> 160 </enumeratedValues> 161 </field> 162 <field> 163 <name>TX_START</name> 164 <description>Start Transmit.</description> 165 <bitOffset>5</bitOffset> 166 <bitWidth>1</bitWidth> 167 <enumeratedValues> 168 <enumeratedValue> 169 <name>start</name> 170 <description>Master Initiates a transaction, this bit is 171 self clearing when transactions are done. If 172 a transaction completes, and the TX FIFO 173 is empty, the Master halts, if a transaction 174 completes, and the TX FIFO is not empty, 175 the Master initiates another transaction.</description> 176 <value>1</value> 177 </enumeratedValue> 178 </enumeratedValues> 179 </field> 180 <field> 181 <name>SS_CTRL</name> 182 <description>Slave Select Control.</description> 183 <bitOffset>8</bitOffset> 184 <bitWidth>1</bitWidth> 185 <enumeratedValues> 186 <enumeratedValue> 187 <name>deassert</name> 188 <description>SPI de-asserts Slave Select at the end of a transaction.</description> 189 <value>0</value> 190 </enumeratedValue> 191 <enumeratedValue> 192 <name>assert</name> 193 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 194 <value>1</value> 195 </enumeratedValue> 196 </enumeratedValues> 197 </field> 198 <field> 199 <name>SS</name> 200 <description>Slave Select, when in Master mode selects which Slave devices are 201 selected. More than one Slave device can be selected.</description> 202 <bitOffset>16</bitOffset> 203 <bitWidth>8</bitWidth> 204 <enumeratedValues> 205 <enumeratedValue> 206 <name>SS0</name> 207 <description>SS0 is selected.</description> 208 <value>0x1</value> 209 </enumeratedValue> 210 <enumeratedValue> 211 <name>SS1</name> 212 <description>SS1 is selected.</description> 213 <value>0x2</value> 214 </enumeratedValue> 215 <enumeratedValue> 216 <name>SS2</name> 217 <description>SS2 is selected.</description> 218 <value>0x4</value> 219 </enumeratedValue> 220 <enumeratedValue> 221 <name>SS3</name> 222 <description>SS3 is selected.</description> 223 <value>0x8</value> 224 </enumeratedValue> 225 <enumeratedValue> 226 <name>SS4</name> 227 <description>SS4 is selected.</description> 228 <value>0x10</value> 229 </enumeratedValue> 230 <enumeratedValue> 231 <name>SS5</name> 232 <description>SS5 is selected.</description> 233 <value>0x20</value> 234 </enumeratedValue> 235 <enumeratedValue> 236 <name>SS6</name> 237 <description>SS6 is selected.</description> 238 <value>0x40</value> 239 </enumeratedValue> 240 <enumeratedValue> 241 <name>SS7</name> 242 <description>SS7 is selected.</description> 243 <value>0x80</value> 244 </enumeratedValue> 245 </enumeratedValues> 246 </field> 247 </fields> 248 </register> 249 <register> 250 <name>CTRL2</name> 251 <description>Register for controlling SPI peripheral.</description> 252 <addressOffset>0x08</addressOffset> 253 <access>read-write</access> 254 <fields> 255 <field> 256 <name>TX_NUM_CHAR</name> 257 <description>Nubmer of Characters to transmit.</description> 258 <bitOffset>0</bitOffset> 259 <bitWidth>16</bitWidth> 260 </field> 261 <field> 262 <name>RX_NUM_CHAR</name> 263 <description>Nubmer of Characters to receive.</description> 264 <bitOffset>16</bitOffset> 265 <bitWidth>16</bitWidth> 266 </field> 267 </fields> 268 </register> 269 <register> 270 <name>CTRL3</name> 271 <description>Register for controlling SPI peripheral.</description> 272 <addressOffset>0x0C</addressOffset> 273 <access>read-write</access> 274 <fields> 275 <field> 276 <name>CPHA</name> 277 <description>Clock Phase.</description> 278 <bitOffset>0</bitOffset> 279 <bitWidth>1</bitWidth> 280 </field> 281 <field> 282 <name>CPOL</name> 283 <description>Clock Polarity.</description> 284 <bitOffset>1</bitOffset> 285 <bitWidth>1</bitWidth> 286 </field> 287 <field> 288 <name>SCLK_FB_INV</name> 289 <description>Invert SCLK Feedback in Master Mode.</description> 290 <bitOffset>4</bitOffset> 291 <bitWidth>1</bitWidth> 292 <enumeratedValues> 293 <enumeratedValue> 294 <name>NON_INV</name> 295 <description>SCLK is not inverted to Line Receiver.</description> 296 <value>0</value> 297 </enumeratedValue> 298 <enumeratedValue> 299 <name>INV</name> 300 <description>SCLK is inverted to Line Receiver.</description> 301 <value>1</value> 302 </enumeratedValue> 303 </enumeratedValues> 304 </field> 305 <field> 306 <name>NUMBITS</name> 307 <description>Number of Bits per character.</description> 308 <bitOffset>8</bitOffset> 309 <bitWidth>4</bitWidth> 310 <enumeratedValues> 311 <enumeratedValue> 312 <name>0</name> 313 <description>16 bits per character.</description> 314 <value>0</value> 315 </enumeratedValue> 316 </enumeratedValues> 317 </field> 318 <field> 319 <name>DATA_WIDTH</name> 320 <description>SPI Data width.</description> 321 <bitOffset>12</bitOffset> 322 <bitWidth>2</bitWidth> 323 <enumeratedValues> 324 <enumeratedValue> 325 <name>Mono</name> 326 <description>1 data pin.</description> 327 <value>0</value> 328 </enumeratedValue> 329 <enumeratedValue> 330 <name>Dual</name> 331 <description>2 data pins.</description> 332 <value>1</value> 333 </enumeratedValue> 334 <enumeratedValue> 335 <name>Quad</name> 336 <description>4 data pins.</description> 337 <value>2</value> 338 </enumeratedValue> 339 </enumeratedValues> 340 </field> 341 <field> 342 <name>THREE_WIRE</name> 343 <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description> 344 <bitOffset>15</bitOffset> 345 <bitWidth>1</bitWidth> 346 <enumeratedValues> 347 <enumeratedValue> 348 <name>dis</name> 349 <description>Use four wire mode (Mono only).</description> 350 <value>0</value> 351 </enumeratedValue> 352 <enumeratedValue> 353 <name>en</name> 354 <description>Use three wire mode.</description> 355 <value>1</value> 356 </enumeratedValue> 357 </enumeratedValues> 358 </field> 359 <field> 360 <name>SSPOL</name> 361 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 362 <bitOffset>16</bitOffset> 363 <bitWidth>8</bitWidth> 364 <enumeratedValues> 365 <enumeratedValue> 366 <name>SS0_high</name> 367 <description>SS0 active high.</description> 368 <value>0x1</value> 369 </enumeratedValue> 370 <enumeratedValue> 371 <name>SS1_high</name> 372 <description>SS1 active high.</description> 373 <value>0x2</value> 374 </enumeratedValue> 375 <enumeratedValue> 376 <name>SS2_high</name> 377 <description>SS2 active high.</description> 378 <value>0x4</value> 379 </enumeratedValue> 380 <enumeratedValue> 381 <name>SS3_high</name> 382 <description>SS3 active high.</description> 383 <value>0x8</value> 384 </enumeratedValue> 385 <enumeratedValue> 386 <name>SS4_high</name> 387 <description>SS4 active high.</description> 388 <value>0x10</value> 389 </enumeratedValue> 390 <enumeratedValue> 391 <name>SS5_high</name> 392 <description>SS5 active high.</description> 393 <value>0x20</value> 394 </enumeratedValue> 395 <enumeratedValue> 396 <name>SS6_high</name> 397 <description>SS6 active high.</description> 398 <value>0x40</value> 399 </enumeratedValue> 400 <enumeratedValue> 401 <name>SS7_high</name> 402 <description>SS7 active high.</description> 403 <value>0x80</value> 404 </enumeratedValue> 405 </enumeratedValues> 406 </field> 407 </fields> 408 </register> 409 <register> 410 <name>CTRL4</name> 411 <description>Register for controlling SPI peripheral.</description> 412 <addressOffset>0x10</addressOffset> 413 <access>read-write</access> 414 <fields> 415 <field> 416 <name>SSACT1</name> 417 <description>Slave Select Action delay 1.</description> 418 <bitOffset>0</bitOffset> 419 <bitWidth>8</bitWidth> 420 <enumeratedValues> 421 <enumeratedValue> 422 <name>256</name> 423 <description>256 system clocks between SS active and first serial clock edge.</description> 424 <value>0</value> 425 </enumeratedValue> 426 </enumeratedValues> 427 </field> 428 <field> 429 <name>SSACT2</name> 430 <description>Slave Select Action delay 2.</description> 431 <bitOffset>8</bitOffset> 432 <bitWidth>8</bitWidth> 433 <enumeratedValues> 434 <enumeratedValue> 435 <name>256</name> 436 <description>256 system clocks between last serial clock edge and SS inactive.</description> 437 <value>0</value> 438 </enumeratedValue> 439 </enumeratedValues> 440 </field> 441 <field> 442 <name>SSINACT</name> 443 <description>Slave Select Inactive delay.</description> 444 <bitOffset>16</bitOffset> 445 <bitWidth>8</bitWidth> 446 <enumeratedValues> 447 <enumeratedValue> 448 <name>256</name> 449 <description>256 system clocks between transactions.</description> 450 <value>0</value> 451 </enumeratedValue> 452 </enumeratedValues> 453 </field> 454 </fields> 455 </register> 456 <register> 457 <name>BRG_CTRL</name> 458 <description>Register for controlling SPI clock rate.</description> 459 <addressOffset>0x14</addressOffset> 460 <access>read-write</access> 461 <fields> 462 <field> 463 <name>LOW</name> 464 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 465 <bitOffset>0</bitOffset> 466 <bitWidth>8</bitWidth> 467 <enumeratedValues> 468 <enumeratedValue> 469 <name>Dis</name> 470 <description>Duty cycle control of serial clock generation is disabled.</description> 471 <value>0</value> 472 </enumeratedValue> 473 </enumeratedValues> 474 </field> 475 <field> 476 <name>HI</name> 477 <description>High duty cycle control. In timer mode, reload[15:8].</description> 478 <bitOffset>8</bitOffset> 479 <bitWidth>8</bitWidth> 480 <enumeratedValues> 481 <enumeratedValue> 482 <name>Dis</name> 483 <description>Duty cycle control of serial clock generation is disabled.</description> 484 <value>0</value> 485 </enumeratedValue> 486 </enumeratedValues> 487 </field> 488 <field> 489 <name>SCALE</name> 490 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 491 <bitOffset>16</bitOffset> 492 <bitWidth>4</bitWidth> 493 </field> 494 </fields> 495 </register> 496 <register> 497 <name>DMA</name> 498 <description>Register for controlling DMA.</description> 499 <addressOffset>0x1C</addressOffset> 500 <access>read-write</access> 501 <fields> 502 <field> 503 <name>TX_FIFO_LEVEL</name> 504 <description>Transmit FIFO level that will trigger a DMA request, also level for 505 threshold status. When TX FIFO has fewer than this many bytes, the 506 associated events and conditions are triggered.</description> 507 <bitOffset>0</bitOffset> 508 <bitWidth>6</bitWidth> 509 </field> 510 <field> 511 <name>TX_FIFO_EN</name> 512 <description>Transmit FIFO enabled for SPI transactions.</description> 513 <bitOffset>6</bitOffset> 514 <bitWidth>1</bitWidth> 515 <enumeratedValues> 516 <enumeratedValue> 517 <name>dis</name> 518 <description>Transmit FIFO is not enabled.</description> 519 <value>0</value> 520 </enumeratedValue> 521 <enumeratedValue> 522 <name>en</name> 523 <description>Transmit FIFO is enabled.</description> 524 <value>1</value> 525 </enumeratedValue> 526 </enumeratedValues> 527 </field> 528 <field> 529 <name>TX_FIFO_CLEAR</name> 530 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 531 pointers. This should be done when FIFO is not being accessed on the SPI side. 532 </description> 533 <bitOffset>7</bitOffset> 534 <bitWidth>1</bitWidth> 535 <enumeratedValues> 536 <enumeratedValue> 537 <name>CLEAR</name> 538 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 539 <value>1</value> 540 </enumeratedValue> 541 </enumeratedValues> 542 </field> 543 <field> 544 <name>TX_FIFO_CNT</name> 545 <description>Count of entries in TX FIFO.</description> 546 <bitOffset>8</bitOffset> 547 <bitWidth>5</bitWidth> 548 </field> 549 <field> 550 <name>TX_DMA_EN</name> 551 <description>TX DMA Enable.</description> 552 <bitOffset>15</bitOffset> 553 <bitWidth>1</bitWidth> 554 <enumeratedValues> 555 <enumeratedValue> 556 <name>DIS</name> 557 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 558 <value>0</value> 559 </enumeratedValue> 560 <enumeratedValue> 561 <name>en</name> 562 <description>TX DMA requests are enabled.</description> 563 <value>1</value> 564 </enumeratedValue> 565 </enumeratedValues> 566 </field> 567 <field> 568 <name>RX_FIFO_LEVEL</name> 569 <description>Receive FIFO level that will trigger a DMA request, also level for 570 threshold status. When RX FIFO has more than this many bytes, the 571 associated events and conditions are triggered.</description> 572 <bitOffset>16</bitOffset> 573 <bitWidth>6</bitWidth> 574 </field> 575 <field> 576 <name>RX_FIFO_EN</name> 577 <description>Receive FIFO enabled for SPI transactions.</description> 578 <bitOffset>22</bitOffset> 579 <bitWidth>1</bitWidth> 580 <enumeratedValues> 581 <enumeratedValue> 582 <name>DIS</name> 583 <description>Receive FIFO is not enabled.</description> 584 <value>0</value> 585 </enumeratedValue> 586 <enumeratedValue> 587 <name>en</name> 588 <description>Receive FIFO is enabled.</description> 589 <value>1</value> 590 </enumeratedValue> 591 </enumeratedValues> 592 </field> 593 <field> 594 <name>RX_FIFO_CLEAR</name> 595 <description>Clear RX FIFO, clear is accomplished by resetting the read and write 596 pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 597 <bitOffset>23</bitOffset> 598 <bitWidth>1</bitWidth> 599 <enumeratedValues> 600 <enumeratedValue> 601 <name>CLEAR</name> 602 <description>Clear the Receive FIFIO, clears any pending RX FIFO status.</description> 603 <value>1</value> 604 </enumeratedValue> 605 </enumeratedValues> 606 </field> 607 <field> 608 <name>RX_FIFO_CNT</name> 609 <description>Count of entries in RX FIFO.</description> 610 <bitOffset>24</bitOffset> 611 <bitWidth>6</bitWidth> 612 </field> 613 <field> 614 <name>RX_DMA_EN</name> 615 <description>RX DMA Enable.</description> 616 <bitOffset>31</bitOffset> 617 <bitWidth>1</bitWidth> 618 <enumeratedValues> 619 <enumeratedValue> 620 <name>dis</name> 621 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 622 <value>0</value> 623 </enumeratedValue> 624 <enumeratedValue> 625 <name>en</name> 626 <description>RX DMA requests are enabled.</description> 627 <value>1</value> 628 </enumeratedValue> 629 </enumeratedValues> 630 </field> 631 </fields> 632 </register> 633 <register> 634 <name>IRQ</name> 635 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 636 <addressOffset>0x20</addressOffset> 637 <access>read-write</access> 638 <fields> 639 <field> 640 <name>TX_THRESH</name> 641 <description>TX FIFO Threshold Crossed.</description> 642 <bitOffset>0</bitOffset> 643 <bitWidth>1</bitWidth> 644 <enumeratedValues> 645 <enumeratedValue> 646 <name>clear</name> 647 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 648 <value>1</value> 649 </enumeratedValue> 650 </enumeratedValues> 651 </field> 652 <field> 653 <name>TX_EMPTY</name> 654 <description>TX FIFO Empty.</description> 655 <bitOffset>1</bitOffset> 656 <bitWidth>1</bitWidth> 657 <enumeratedValues> 658 <enumeratedValue> 659 <name>clear</name> 660 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 661 <value>1</value> 662 </enumeratedValue> 663 </enumeratedValues> 664 </field> 665 <field> 666 <name>RX_THRESH</name> 667 <description>RX FIFO Threshold Crossed.</description> 668 <bitOffset>2</bitOffset> 669 <bitWidth>1</bitWidth> 670 <enumeratedValues> 671 <enumeratedValue> 672 <name>clear</name> 673 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 674 <value>1</value> 675 </enumeratedValue> 676 </enumeratedValues> 677 </field> 678 <field> 679 <name>RX_FULL</name> 680 <description>RX FIFO FULL.</description> 681 <bitOffset>3</bitOffset> 682 <bitWidth>1</bitWidth> 683 <enumeratedValues> 684 <enumeratedValue> 685 <name>clear</name> 686 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 687 <value>1</value> 688 </enumeratedValue> 689 </enumeratedValues> 690 </field> 691 <field> 692 <name>SSA</name> 693 <description>Slave Select Asserted.</description> 694 <bitOffset>4</bitOffset> 695 <bitWidth>1</bitWidth> 696 <enumeratedValues> 697 <enumeratedValue> 698 <name>clear</name> 699 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 700 <value>1</value> 701 </enumeratedValue> 702 </enumeratedValues> 703 </field> 704 <field> 705 <name>SSD</name> 706 <description>Slave Select Deasserted.</description> 707 <bitOffset>5</bitOffset> 708 <bitWidth>1</bitWidth> 709 <enumeratedValues> 710 <enumeratedValue> 711 <name>clear</name> 712 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 713 <value>1</value> 714 </enumeratedValue> 715 </enumeratedValues> 716 </field> 717 <field> 718 <name>FAULT</name> 719 <description>Multi-Master Mode Fault.</description> 720 <bitOffset>8</bitOffset> 721 <bitWidth>1</bitWidth> 722 <enumeratedValues> 723 <enumeratedValue> 724 <name>clear</name> 725 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 726 <value>1</value> 727 </enumeratedValue> 728 </enumeratedValues> 729 </field> 730 <field> 731 <name>ABORT</name> 732 <description>Slave Abort Detected.</description> 733 <bitOffset>9</bitOffset> 734 <bitWidth>1</bitWidth> 735 <enumeratedValues> 736 <enumeratedValue> 737 <name>clear</name> 738 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 739 <value>1</value> 740 </enumeratedValue> 741 </enumeratedValues> 742 </field> 743 <field> 744 <name>M_DONE</name> 745 <description>Master Done, set when SPI Master has completed any transactions.</description> 746 <bitOffset>11</bitOffset> 747 <bitWidth>1</bitWidth> 748 <enumeratedValues> 749 <enumeratedValue> 750 <name>clear</name> 751 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 752 <value>1</value> 753 </enumeratedValue> 754 </enumeratedValues> 755 </field> 756 <field> 757 <name>TX_OVR</name> 758 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data 759 to a full transmit FIFO.</description> 760 <bitOffset>12</bitOffset> 761 <bitWidth>1</bitWidth> 762 <enumeratedValues> 763 <enumeratedValue> 764 <name>clear</name> 765 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 766 <value>1</value> 767 </enumeratedValue> 768 </enumeratedValues> 769 </field> 770 <field> 771 <name>TX_UND</name> 772 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data 773 from an empty transmit FIFO.</description> 774 <bitOffset>13</bitOffset> 775 <bitWidth>1</bitWidth> 776 <enumeratedValues> 777 <enumeratedValue> 778 <name>clear</name> 779 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 780 <value>1</value> 781 </enumeratedValue> 782 </enumeratedValues> 783 </field> 784 <field> 785 <name>RX_OVR</name> 786 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 787 <bitOffset>14</bitOffset> 788 <bitWidth>1</bitWidth> 789 <enumeratedValues> 790 <enumeratedValue> 791 <name>clear</name> 792 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 793 <value>1</value> 794 </enumeratedValue> 795 </enumeratedValues> 796 </field> 797 <field> 798 <name>RX_UND</name> 799 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 800 <bitOffset>15</bitOffset> 801 <bitWidth>1</bitWidth> 802 <enumeratedValues> 803 <enumeratedValue> 804 <name>clear</name> 805 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 806 <value>1</value> 807 </enumeratedValue> 808 </enumeratedValues> 809 </field> 810 </fields> 811 </register> 812 <register> 813 <name>IRQE</name> 814 <description>Register for enabling interrupts.</description> 815 <addressOffset>0x24</addressOffset> 816 <access>read-write</access> 817 <fields> 818 <field> 819 <name>TX_THRESH</name> 820 <description>TX FIFO Threshold interrupt enable.</description> 821 <bitOffset>0</bitOffset> 822 <bitWidth>1</bitWidth> 823 <enumeratedValues> 824 <enumeratedValue> 825 <name>dis</name> 826 <description>Interrupt is disabled.</description> 827 <value>0</value> 828 </enumeratedValue> 829 <enumeratedValue> 830 <name>en</name> 831 <description>Interrupt is enabled.</description> 832 <value>1</value> 833 </enumeratedValue> 834 </enumeratedValues> 835 </field> 836 <field> 837 <name>TX_EMPTY</name> 838 <description>TX FIFO Empty interrupt enable.</description> 839 <bitOffset>1</bitOffset> 840 <bitWidth>1</bitWidth> 841 <enumeratedValues> 842 <enumeratedValue> 843 <name>dis</name> 844 <description>Interrupt is disabled.</description> 845 <value>0</value> 846 </enumeratedValue> 847 <enumeratedValue> 848 <name>en</name> 849 <description>Interrupt is enabled.</description> 850 <value>1</value> 851 </enumeratedValue> 852 </enumeratedValues> 853 </field> 854 <field> 855 <name>RX_THRESH</name> 856 <description>RX FIFO Threshold Crossed interrupt enable.</description> 857 <bitOffset>2</bitOffset> 858 <bitWidth>1</bitWidth> 859 <enumeratedValues> 860 <enumeratedValue> 861 <name>dis</name> 862 <description>Interrupt is disabled.</description> 863 <value>0</value> 864 </enumeratedValue> 865 <enumeratedValue> 866 <name>en</name> 867 <description>Interrupt is enabled.</description> 868 <value>1</value> 869 </enumeratedValue> 870 </enumeratedValues> 871 </field> 872 <field> 873 <name>RX_FULL</name> 874 <description>RX FIFO FULL interrupt enable.</description> 875 <bitOffset>3</bitOffset> 876 <bitWidth>1</bitWidth> 877 <enumeratedValues> 878 <enumeratedValue> 879 <name>dis</name> 880 <description>Interrupt is disabled.</description> 881 <value>0</value> 882 </enumeratedValue> 883 <enumeratedValue> 884 <name>en</name> 885 <description>Interrupt is enabled.</description> 886 <value>1</value> 887 </enumeratedValue> 888 </enumeratedValues> 889 </field> 890 <field> 891 <name>SSA</name> 892 <description>Slave Select Asserted interrupt enable.</description> 893 <bitOffset>4</bitOffset> 894 <bitWidth>1</bitWidth> 895 <enumeratedValues> 896 <enumeratedValue> 897 <name>dis</name> 898 <description>Interrupt is disabled.</description> 899 <value>0</value> 900 </enumeratedValue> 901 <enumeratedValue> 902 <name>en</name> 903 <description>Interrupt is enabled.</description> 904 <value>1</value> 905 </enumeratedValue> 906 </enumeratedValues> 907 </field> 908 <field> 909 <name>SSD</name> 910 <description>Slave Select Deasserted interrupt enable.</description> 911 <bitOffset>5</bitOffset> 912 <bitWidth>1</bitWidth> 913 <enumeratedValues> 914 <enumeratedValue> 915 <name>dis</name> 916 <description>Interrupt is disabled.</description> 917 <value>0</value> 918 </enumeratedValue> 919 <enumeratedValue> 920 <name>en</name> 921 <description>Interrupt is enabled.</description> 922 <value>1</value> 923 </enumeratedValue> 924 </enumeratedValues> 925 </field> 926 <field> 927 <name>FAULT</name> 928 <description>Multi-Master Mode Fault interrupt enable.</description> 929 <bitOffset>8</bitOffset> 930 <bitWidth>1</bitWidth> 931 <enumeratedValues> 932 <enumeratedValue> 933 <name>dis</name> 934 <description>Interrupt is disabled.</description> 935 <value>0</value> 936 </enumeratedValue> 937 <enumeratedValue> 938 <name>en</name> 939 <description>Interrupt is enabled.</description> 940 <value>1</value> 941 </enumeratedValue> 942 </enumeratedValues> 943 </field> 944 <field> 945 <name>ABORT</name> 946 <description>Slave Abort Detected interrupt enable.</description> 947 <bitOffset>9</bitOffset> 948 <bitWidth>1</bitWidth> 949 <enumeratedValues> 950 <enumeratedValue> 951 <name>dis</name> 952 <description>Interrupt is disabled.</description> 953 <value>0</value> 954 </enumeratedValue> 955 <enumeratedValue> 956 <name>en</name> 957 <description>Interrupt is enabled.</description> 958 <value>1</value> 959 </enumeratedValue> 960 </enumeratedValues> 961 </field> 962 <field> 963 <name>M_DONE</name> 964 <description>Master Done interrupt enable.</description> 965 <bitOffset>11</bitOffset> 966 <bitWidth>1</bitWidth> 967 <enumeratedValues> 968 <enumeratedValue> 969 <name>dis</name> 970 <description>Interrupt is disabled.</description> 971 <value>0</value> 972 </enumeratedValue> 973 <enumeratedValue> 974 <name>en</name> 975 <description>Interrupt is enabled.</description> 976 <value>1</value> 977 </enumeratedValue> 978 </enumeratedValues> 979 </field> 980 <field> 981 <name>TX_OVR</name> 982 <description>Transmit FIFO Overrun interrupt enable.</description> 983 <bitOffset>12</bitOffset> 984 <bitWidth>1</bitWidth> 985 <enumeratedValues> 986 <enumeratedValue> 987 <name>dis</name> 988 <description>Interrupt is disabled.</description> 989 <value>0</value> 990 </enumeratedValue> 991 <enumeratedValue> 992 <name>en</name> 993 <description>Interrupt is enabled.</description> 994 <value>1</value> 995 </enumeratedValue> 996 </enumeratedValues> 997 </field> 998 <field> 999 <name>TX_UND</name> 1000 <description>Transmit FIFO Underrun interrupt enable.</description> 1001 <bitOffset>13</bitOffset> 1002 <bitWidth>1</bitWidth> 1003 <enumeratedValues> 1004 <enumeratedValue> 1005 <name>dis</name> 1006 <description>Interrupt is disabled.</description> 1007 <value>0</value> 1008 </enumeratedValue> 1009 <enumeratedValue> 1010 <name>en</name> 1011 <description>Interrupt is enabled.</description> 1012 <value>1</value> 1013 </enumeratedValue> 1014 </enumeratedValues> 1015 </field> 1016 <field> 1017 <name>RX_OVR</name> 1018 <description>Receive FIFO Overrun interrupt enable.</description> 1019 <bitOffset>14</bitOffset> 1020 <bitWidth>1</bitWidth> 1021 <enumeratedValues> 1022 <enumeratedValue> 1023 <name>dis</name> 1024 <description>Interrupt is disabled.</description> 1025 <value>0</value> 1026 </enumeratedValue> 1027 <enumeratedValue> 1028 <name>en</name> 1029 <description>Interrupt is enabled.</description> 1030 <value>1</value> 1031 </enumeratedValue> 1032 </enumeratedValues> 1033 </field> 1034 <field> 1035 <name>RX_UND</name> 1036 <description>Receive FIFO Underrun interrupt enable.</description> 1037 <bitOffset>15</bitOffset> 1038 <bitWidth>1</bitWidth> 1039 <enumeratedValues> 1040 <enumeratedValue> 1041 <name>dis</name> 1042 <description>Interrupt is disabled.</description> 1043 <value>0</value> 1044 </enumeratedValue> 1045 <enumeratedValue> 1046 <name>en</name> 1047 <description>Interrupt is enabled.</description> 1048 <value>1</value> 1049 </enumeratedValue> 1050 </enumeratedValues> 1051 </field> 1052 </fields> 1053 </register> 1054 <register> 1055 <name>WAKE</name> 1056 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1057 <addressOffset>0x28</addressOffset> 1058 <access>read-write</access> 1059 <fields> 1060 <field> 1061 <name>TX_THRESH</name> 1062 <description>Wake on TX FIFO Threshold Crossed.</description> 1063 <bitOffset>0</bitOffset> 1064 <bitWidth>1</bitWidth> 1065 <enumeratedValues> 1066 <enumeratedValue> 1067 <name>clear</name> 1068 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1069 <value>1</value> 1070 </enumeratedValue> 1071 </enumeratedValues> 1072 </field> 1073 <field> 1074 <name>TX_EMPTY</name> 1075 <description>Wake on TX FIFO Empty.</description> 1076 <bitOffset>1</bitOffset> 1077 <bitWidth>1</bitWidth> 1078 <enumeratedValues> 1079 <enumeratedValue> 1080 <name>clear</name> 1081 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1082 <value>1</value> 1083 </enumeratedValue> 1084 </enumeratedValues> 1085 </field> 1086 <field> 1087 <name>RX_THRESH</name> 1088 <description>Wake on RX FIFO Threshold Crossed.</description> 1089 <bitOffset>2</bitOffset> 1090 <bitWidth>1</bitWidth> 1091 <enumeratedValues> 1092 <enumeratedValue> 1093 <name>clear</name> 1094 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1095 <value>1</value> 1096 </enumeratedValue> 1097 </enumeratedValues> 1098 </field> 1099 <field> 1100 <name>RX_FULL</name> 1101 <description>Wake on RX FIFO Full.</description> 1102 <bitOffset>3</bitOffset> 1103 <bitWidth>1</bitWidth> 1104 <enumeratedValues> 1105 <enumeratedValue> 1106 <name>clear</name> 1107 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1108 <value>1</value> 1109 </enumeratedValue> 1110 </enumeratedValues> 1111 </field> 1112 </fields> 1113 </register> 1114 <register> 1115 <name>WAKEE</name> 1116 <description>Register for wake up enable.</description> 1117 <addressOffset>0x2C</addressOffset> 1118 <access>read-write</access> 1119 <fields> 1120 <field> 1121 <name>TX_THRESH</name> 1122 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1123 <bitOffset>0</bitOffset> 1124 <bitWidth>1</bitWidth> 1125 <enumeratedValues> 1126 <enumeratedValue> 1127 <name>dis</name> 1128 <description>Wakeup source disabled.</description> 1129 <value>0</value> 1130 </enumeratedValue> 1131 <enumeratedValue> 1132 <name>en</name> 1133 <description>Wakeup source enabled.</description> 1134 <value>1</value> 1135 </enumeratedValue> 1136 </enumeratedValues> 1137 </field> 1138 <field> 1139 <name>TX_EMPTY</name> 1140 <description>Wake on TX FIFO Empty Enable.</description> 1141 <bitOffset>1</bitOffset> 1142 <bitWidth>1</bitWidth> 1143 <enumeratedValues> 1144 <enumeratedValue> 1145 <name>dis</name> 1146 <description>Wakeup source disabled.</description> 1147 <value>0</value> 1148 </enumeratedValue> 1149 <enumeratedValue> 1150 <name>en</name> 1151 <description>Wakeup source enabled.</description> 1152 <value>1</value> 1153 </enumeratedValue> 1154 </enumeratedValues> 1155 </field> 1156 <field> 1157 <name>RX_THRESH</name> 1158 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1159 <bitOffset>2</bitOffset> 1160 <bitWidth>1</bitWidth> 1161 <enumeratedValues> 1162 <enumeratedValue> 1163 <name>dis</name> 1164 <description>Wakeup source disabled.</description> 1165 <value>0</value> 1166 </enumeratedValue> 1167 <enumeratedValue> 1168 <name>en</name> 1169 <description>Wakeup source enabled.</description> 1170 <value>1</value> 1171 </enumeratedValue> 1172 </enumeratedValues> 1173 </field> 1174 <field> 1175 <name>RX_FULL</name> 1176 <description>Wake on RX FIFO Full Enable.</description> 1177 <bitOffset>3</bitOffset> 1178 <bitWidth>1</bitWidth> 1179 <enumeratedValues> 1180 <enumeratedValue> 1181 <name>dis</name> 1182 <description>Wakeup source disabled.</description> 1183 <value>0</value> 1184 </enumeratedValue> 1185 <enumeratedValue> 1186 <name>en</name> 1187 <description>Wakeup source enabled.</description> 1188 <value>1</value> 1189 </enumeratedValue> 1190 </enumeratedValues> 1191 </field> 1192 </fields> 1193 </register> 1194 <register> 1195 <name>STAT</name> 1196 <description>SPI Status register.</description> 1197 <addressOffset>0x30</addressOffset> 1198 <access>read-only</access> 1199 <fields> 1200 <field> 1201 <name>BUSY</name> 1202 <description>SPI active status. In Master mode, set when transaction starts, 1203 cleared when last bit of last character is acted upon and Slave Select 1204 de-assertion would occur. In Slave mode, set when Slave Select is 1205 asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 1206 </description> 1207 <bitOffset>0</bitOffset> 1208 <bitWidth>1</bitWidth> 1209 <enumeratedValues> 1210 <enumeratedValue> 1211 <name>not</name> 1212 <description>SPI not active.</description> 1213 <value>0</value> 1214 </enumeratedValue> 1215 <enumeratedValue> 1216 <name>active</name> 1217 <description>SPI active.</description> 1218 <value>1</value> 1219 </enumeratedValue> 1220 </enumeratedValues> 1221 </field> 1222 </fields> 1223 </register> 1224 <register> 1225 <name>XMEM_CTRL</name> 1226 <description>Register to control external memory.</description> 1227 <addressOffset>0x34</addressOffset> 1228 <access>read-write</access> 1229 <fields> 1230 <field> 1231 <name>RD_CMD</name> 1232 <description>Read command.</description> 1233 <bitOffset>0</bitOffset> 1234 <bitWidth>8</bitWidth> 1235 </field> 1236 <field> 1237 <name>WR_CMD</name> 1238 <description>Write command.</description> 1239 <bitOffset>8</bitOffset> 1240 <bitWidth>8</bitWidth> 1241 </field> 1242 <field> 1243 <name>DUMMY_CLK</name> 1244 <description>Dummy clocks.</description> 1245 <bitOffset>16</bitOffset> 1246 <bitWidth>8</bitWidth> 1247 </field> 1248 <field> 1249 <name>XMEM_EN</name> 1250 <description>XMEM enable.</description> 1251 <bitOffset>31</bitOffset> 1252 <bitWidth>1</bitWidth> 1253 </field> 1254 </fields> 1255 </register> 1256 </registers> 1257 </peripheral> 1258 <!-- SPIXR for Data XIP interface --> 1259</device>
