1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXR</name> 5 <description>SPIXR peripheral.</description> 6 <baseAddress>0x4003A000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>DATA32</name> 15 <description>Register for reading and writing the FIFO.</description> 16 <addressOffset>0x00</addressOffset> 17 <size>32</size> 18 <access>read-write</access> 19 <fields> 20 <field> 21 <name>DATA</name> 22 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 23 <bitOffset>0</bitOffset> 24 <bitWidth>32</bitWidth> 25 </field> 26 </fields> 27 </register> 28 <register> 29 <dim>2</dim> 30 <dimIncrement>2</dimIncrement> 31 <name>DATA16[%s]</name> 32 <description>Register for reading and writing the FIFO.</description> 33 <alternateRegister>DATA32</alternateRegister> 34 <addressOffset>0x00</addressOffset> 35 <size>16</size> 36 <access>read-write</access> 37 <fields> 38 <field> 39 <name>DATA</name> 40 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>16</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <dim>4</dim> 48 <dimIncrement>1</dimIncrement> 49 <name>DATA8[%s]</name> 50 <description>Register for reading and writing the FIFO.</description> 51 <alternateRegister>DATA32</alternateRegister> 52 <addressOffset>0x00</addressOffset> 53 <size>8</size> 54 <access>read-write</access> 55 <fields> 56 <field> 57 <name>DATA</name> 58 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 59 <bitOffset>0</bitOffset> 60 <bitWidth>8</bitWidth> 61 </field> 62 </fields> 63 </register> 64 <register> 65 <name>CTRL1</name> 66 <description>Register for controlling SPI peripheral.</description> 67 <addressOffset>0x04</addressOffset> 68 <access>read-write</access> 69 <fields> 70 <field> 71 <name>SPIEN</name> 72 <description>SPI Enable.</description> 73 <bitOffset>0</bitOffset> 74 <bitWidth>1</bitWidth> 75 <enumeratedValues> 76 <enumeratedValue> 77 <name>dis</name> 78 <description>SPI is disabled.</description> 79 <value>0</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>en</name> 83 <description>SPI is enabled.</description> 84 <value>1</value> 85 </enumeratedValue> 86 </enumeratedValues> 87 </field> 88 <field> 89 <name>MMEN</name> 90 <description>Master Mode Enable.</description> 91 <bitOffset>1</bitOffset> 92 <bitWidth>1</bitWidth> 93 <enumeratedValues> 94 <enumeratedValue> 95 <name>dis</name> 96 <description>SPI is Slave mode.</description> 97 <value>0</value> 98 </enumeratedValue> 99 <enumeratedValue> 100 <name>en</name> 101 <description>SPI is Master mode.</description> 102 <value>1</value> 103 </enumeratedValue> 104 </enumeratedValues> 105 </field> 106 <field> 107 <name>SSIO</name> 108 <description>Slave Select 0, IO direction, to support Multi-Master mode, 109 Slave Select 0 can be input in Master mode. This bit has no 110 effect in slave mode.</description> 111 <bitOffset>4</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>output</name> 116 <description>Slave select 0 is output.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>input</name> 121 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>TX_START</name> 128 <description>Start Transmit.</description> 129 <bitOffset>5</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>start</name> 134 <description>Master Initiates a transaction, this bit is 135 self clearing when transactions are done. If 136 a transaction completes, and the TX FIFO 137 is empty, the Master halts, if a transaction 138 completes, and the TX FIFO is not empty, 139 the Master initiates another transaction.</description> 140 <value>1</value> 141 </enumeratedValue> 142 </enumeratedValues> 143 </field> 144 <field> 145 <name>SS_CTRL</name> 146 <description>Slave Select Control.</description> 147 <bitOffset>8</bitOffset> 148 <bitWidth>1</bitWidth> 149 <enumeratedValues> 150 <enumeratedValue> 151 <name>deassert</name> 152 <description>SPI de-asserts Slave Select at the end of a transaction.</description> 153 <value>0</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>assert</name> 157 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 158 <value>1</value> 159 </enumeratedValue> 160 </enumeratedValues> 161 </field> 162 <field> 163 <name>SS</name> 164 <description>Slave Select, when in Master mode selects which Slave devices are 165 selected. More than one Slave device can be selected.</description> 166 <bitOffset>16</bitOffset> 167 <bitWidth>8</bitWidth> 168 <enumeratedValues> 169 <enumeratedValue> 170 <name>SS0</name> 171 <description>SS0 is selected.</description> 172 <value>0x1</value> 173 </enumeratedValue> 174 <enumeratedValue> 175 <name>SS1</name> 176 <description>SS1 is selected.</description> 177 <value>0x2</value> 178 </enumeratedValue> 179 <enumeratedValue> 180 <name>SS2</name> 181 <description>SS2 is selected.</description> 182 <value>0x4</value> 183 </enumeratedValue> 184 <enumeratedValue> 185 <name>SS3</name> 186 <description>SS3 is selected.</description> 187 <value>0x8</value> 188 </enumeratedValue> 189 <enumeratedValue> 190 <name>SS4</name> 191 <description>SS4 is selected.</description> 192 <value>0x10</value> 193 </enumeratedValue> 194 <enumeratedValue> 195 <name>SS5</name> 196 <description>SS5 is selected.</description> 197 <value>0x20</value> 198 </enumeratedValue> 199 <enumeratedValue> 200 <name>SS6</name> 201 <description>SS6 is selected.</description> 202 <value>0x40</value> 203 </enumeratedValue> 204 <enumeratedValue> 205 <name>SS7</name> 206 <description>SS7 is selected.</description> 207 <value>0x80</value> 208 </enumeratedValue> 209 </enumeratedValues> 210 </field> 211 </fields> 212 </register> 213 <register> 214 <name>CTRL2</name> 215 <description>Register for controlling SPI peripheral.</description> 216 <addressOffset>0x08</addressOffset> 217 <access>read-write</access> 218 <fields> 219 <field> 220 <name>TX_NUM_CHAR</name> 221 <description>Nubmer of Characters to transmit.</description> 222 <bitOffset>0</bitOffset> 223 <bitWidth>16</bitWidth> 224 </field> 225 <field> 226 <name>RX_NUM_CHAR</name> 227 <description>Nubmer of Characters to receive.</description> 228 <bitOffset>16</bitOffset> 229 <bitWidth>16</bitWidth> 230 </field> 231 </fields> 232 </register> 233 <register> 234 <name>CTRL3</name> 235 <description>Register for controlling SPI peripheral.</description> 236 <addressOffset>0x0C</addressOffset> 237 <access>read-write</access> 238 <fields> 239 <field> 240 <name>CPHA</name> 241 <description>Clock Phase.</description> 242 <bitOffset>0</bitOffset> 243 <bitWidth>1</bitWidth> 244 </field> 245 <field> 246 <name>CPOL</name> 247 <description>Clock Polarity.</description> 248 <bitOffset>1</bitOffset> 249 <bitWidth>1</bitWidth> 250 </field> 251 <field> 252 <name>SCLK_FB_INV</name> 253 <description>Invert SCLK Feedback in Master Mode.</description> 254 <bitOffset>4</bitOffset> 255 <bitWidth>1</bitWidth> 256 <enumeratedValues> 257 <enumeratedValue> 258 <name>NON_INV</name> 259 <description>SCLK is not inverted to Line Receiver.</description> 260 <value>0</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>INV</name> 264 <description>SCLK is inverted to Line Receiver.</description> 265 <value>1</value> 266 </enumeratedValue> 267 </enumeratedValues> 268 </field> 269 <field> 270 <name>NUMBITS</name> 271 <description>Number of Bits per character.</description> 272 <bitOffset>8</bitOffset> 273 <bitWidth>4</bitWidth> 274 <enumeratedValues> 275 <enumeratedValue> 276 <name>0</name> 277 <description>16 bits per character.</description> 278 <value>0</value> 279 </enumeratedValue> 280 </enumeratedValues> 281 </field> 282 <field> 283 <name>DATA_WIDTH</name> 284 <description>SPI Data width.</description> 285 <bitOffset>12</bitOffset> 286 <bitWidth>2</bitWidth> 287 <enumeratedValues> 288 <enumeratedValue> 289 <name>Mono</name> 290 <description>1 data pin.</description> 291 <value>0</value> 292 </enumeratedValue> 293 <enumeratedValue> 294 <name>Dual</name> 295 <description>2 data pins.</description> 296 <value>1</value> 297 </enumeratedValue> 298 <enumeratedValue> 299 <name>Quad</name> 300 <description>4 data pins.</description> 301 <value>2</value> 302 </enumeratedValue> 303 </enumeratedValues> 304 </field> 305 <field> 306 <name>THREE_WIRE</name> 307 <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description> 308 <bitOffset>15</bitOffset> 309 <bitWidth>1</bitWidth> 310 <enumeratedValues> 311 <enumeratedValue> 312 <name>dis</name> 313 <description>Use four wire mode (Mono only).</description> 314 <value>0</value> 315 </enumeratedValue> 316 <enumeratedValue> 317 <name>en</name> 318 <description>Use three wire mode.</description> 319 <value>1</value> 320 </enumeratedValue> 321 </enumeratedValues> 322 </field> 323 <field> 324 <name>SSPOL</name> 325 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 326 <bitOffset>16</bitOffset> 327 <bitWidth>8</bitWidth> 328 <enumeratedValues> 329 <enumeratedValue> 330 <name>SS0_high</name> 331 <description>SS0 active high.</description> 332 <value>0x1</value> 333 </enumeratedValue> 334 <enumeratedValue> 335 <name>SS1_high</name> 336 <description>SS1 active high.</description> 337 <value>0x2</value> 338 </enumeratedValue> 339 <enumeratedValue> 340 <name>SS2_high</name> 341 <description>SS2 active high.</description> 342 <value>0x4</value> 343 </enumeratedValue> 344 <enumeratedValue> 345 <name>SS3_high</name> 346 <description>SS3 active high.</description> 347 <value>0x8</value> 348 </enumeratedValue> 349 <enumeratedValue> 350 <name>SS4_high</name> 351 <description>SS4 active high.</description> 352 <value>0x10</value> 353 </enumeratedValue> 354 <enumeratedValue> 355 <name>SS5_high</name> 356 <description>SS5 active high.</description> 357 <value>0x20</value> 358 </enumeratedValue> 359 <enumeratedValue> 360 <name>SS6_high</name> 361 <description>SS6 active high.</description> 362 <value>0x40</value> 363 </enumeratedValue> 364 <enumeratedValue> 365 <name>SS7_high</name> 366 <description>SS7 active high.</description> 367 <value>0x80</value> 368 </enumeratedValue> 369 </enumeratedValues> 370 </field> 371 </fields> 372 </register> 373 <register> 374 <name>SS_TIME</name> 375 <description>Register for controlling SPI peripheral.</description> 376 <addressOffset>0x10</addressOffset> 377 <access>read-write</access> 378 <fields> 379 <field> 380 <name>SSACT1</name> 381 <description>Slave Select Action delay 1.</description> 382 <bitOffset>0</bitOffset> 383 <bitWidth>8</bitWidth> 384 <enumeratedValues> 385 <enumeratedValue> 386 <name>256</name> 387 <description>256 system clocks between SS active and first serial clock edge.</description> 388 <value>0</value> 389 </enumeratedValue> 390 </enumeratedValues> 391 </field> 392 <field> 393 <name>SSACT2</name> 394 <description>Slave Select Action delay 2.</description> 395 <bitOffset>8</bitOffset> 396 <bitWidth>8</bitWidth> 397 <enumeratedValues> 398 <enumeratedValue> 399 <name>256</name> 400 <description>256 system clocks between last serial clock edge and SS inactive.</description> 401 <value>0</value> 402 </enumeratedValue> 403 </enumeratedValues> 404 </field> 405 <field> 406 <name>SSINACT</name> 407 <description>Slave Select Inactive delay.</description> 408 <bitOffset>16</bitOffset> 409 <bitWidth>8</bitWidth> 410 <enumeratedValues> 411 <enumeratedValue> 412 <name>256</name> 413 <description>256 system clocks between transactions.</description> 414 <value>0</value> 415 </enumeratedValue> 416 </enumeratedValues> 417 </field> 418 </fields> 419 </register> 420 <register> 421 <name>BRG_CTRL</name> 422 <description>Register for controlling SPI clock rate.</description> 423 <addressOffset>0x14</addressOffset> 424 <access>read-write</access> 425 <fields> 426 <field> 427 <name>LOW</name> 428 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 429 <bitOffset>0</bitOffset> 430 <bitWidth>8</bitWidth> 431 <enumeratedValues> 432 <enumeratedValue> 433 <name>Dis</name> 434 <description>Duty cycle control of serial clock generation is disabled.</description> 435 <value>0</value> 436 </enumeratedValue> 437 </enumeratedValues> 438 </field> 439 <field> 440 <name>HI</name> 441 <description>High duty cycle control. In timer mode, reload[15:8].</description> 442 <bitOffset>8</bitOffset> 443 <bitWidth>8</bitWidth> 444 <enumeratedValues> 445 <enumeratedValue> 446 <name>Dis</name> 447 <description>Duty cycle control of serial clock generation is disabled.</description> 448 <value>0</value> 449 </enumeratedValue> 450 </enumeratedValues> 451 </field> 452 <field> 453 <name>SCALE</name> 454 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 455 <bitOffset>16</bitOffset> 456 <bitWidth>4</bitWidth> 457 </field> 458 </fields> 459 </register> 460 <register> 461 <name>DMA</name> 462 <description>Register for controlling DMA.</description> 463 <addressOffset>0x1C</addressOffset> 464 <access>read-write</access> 465 <fields> 466 <field> 467 <name>TX_FIFO_LEVEL</name> 468 <description>Transmit FIFO level that will trigger a DMA request, also level for 469 threshold status. When TX FIFO has fewer than this many bytes, the 470 associated events and conditions are triggered.</description> 471 <bitOffset>0</bitOffset> 472 <bitWidth>5</bitWidth> 473 </field> 474 <field> 475 <name>TX_FIFO_EN</name> 476 <description>Transmit FIFO enabled for SPI transactions.</description> 477 <bitOffset>6</bitOffset> 478 <bitWidth>1</bitWidth> 479 <enumeratedValues> 480 <enumeratedValue> 481 <name>dis</name> 482 <description>Transmit FIFO is not enabled.</description> 483 <value>0</value> 484 </enumeratedValue> 485 <enumeratedValue> 486 <name>en</name> 487 <description>Transmit FIFO is enabled.</description> 488 <value>1</value> 489 </enumeratedValue> 490 </enumeratedValues> 491 </field> 492 <field> 493 <name>TX_FIFO_CLEAR</name> 494 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 495 pointers. This should be done when FIFO is not being accessed on the SPI side. 496 </description> 497 <bitOffset>7</bitOffset> 498 <bitWidth>1</bitWidth> 499 <enumeratedValues> 500 <enumeratedValue> 501 <name>CLEAR</name> 502 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 503 <value>1</value> 504 </enumeratedValue> 505 </enumeratedValues> 506 </field> 507 <field> 508 <name>TX_FIFO_CNT</name> 509 <description>Count of entries in TX FIFO.</description> 510 <bitOffset>8</bitOffset> 511 <bitWidth>5</bitWidth> 512 </field> 513 <field> 514 <name>TX_DMA_EN</name> 515 <description>TX DMA Enable.</description> 516 <bitOffset>15</bitOffset> 517 <bitWidth>1</bitWidth> 518 <enumeratedValues> 519 <enumeratedValue> 520 <name>DIS</name> 521 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 522 <value>0</value> 523 </enumeratedValue> 524 <enumeratedValue> 525 <name>en</name> 526 <description>TX DMA requests are enabled.</description> 527 <value>1</value> 528 </enumeratedValue> 529 </enumeratedValues> 530 </field> 531 <field> 532 <name>RX_FIFO_LEVEL</name> 533 <description>Receive FIFO level that will trigger a DMA request, also level for 534 threshold status. When RX FIFO has more than this many bytes, the 535 associated events and conditions are triggered.</description> 536 <bitOffset>16</bitOffset> 537 <bitWidth>6</bitWidth> 538 </field> 539 <field> 540 <name>RX_FIFO_EN</name> 541 <description>Receive FIFO enabled for SPI transactions.</description> 542 <bitOffset>22</bitOffset> 543 <bitWidth>1</bitWidth> 544 <enumeratedValues> 545 <enumeratedValue> 546 <name>DIS</name> 547 <description>Receive FIFO is not enabled.</description> 548 <value>0</value> 549 </enumeratedValue> 550 <enumeratedValue> 551 <name>en</name> 552 <description>Receive FIFO is enabled.</description> 553 <value>1</value> 554 </enumeratedValue> 555 </enumeratedValues> 556 </field> 557 <field> 558 <name>RX_FIFO_CLEAR</name> 559 <description>Clear RX FIFO, clear is accomplished by resetting the read and write 560 pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 561 <bitOffset>23</bitOffset> 562 <bitWidth>1</bitWidth> 563 <enumeratedValues> 564 <enumeratedValue> 565 <name>CLEAR</name> 566 <description>Clear the Receive FIFIO, clears any pending RX FIFO status.</description> 567 <value>1</value> 568 </enumeratedValue> 569 </enumeratedValues> 570 </field> 571 <field> 572 <name>RX_FIFO_CNT</name> 573 <description>Count of entries in RX FIFO.</description> 574 <bitOffset>24</bitOffset> 575 <bitWidth>6</bitWidth> 576 </field> 577 <field> 578 <name>RX_DMA_EN</name> 579 <description>RX DMA Enable.</description> 580 <bitOffset>31</bitOffset> 581 <bitWidth>1</bitWidth> 582 <enumeratedValues> 583 <enumeratedValue> 584 <name>dis</name> 585 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 586 <value>0</value> 587 </enumeratedValue> 588 <enumeratedValue> 589 <name>en</name> 590 <description>RX DMA requests are enabled.</description> 591 <value>1</value> 592 </enumeratedValue> 593 </enumeratedValues> 594 </field> 595 </fields> 596 </register> 597 <register> 598 <name>INT_FL</name> 599 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 600 <addressOffset>0x20</addressOffset> 601 <access>read-write</access> 602 <fields> 603 <field> 604 <name>TX_THRESH</name> 605 <description>TX FIFO Threshold Crossed.</description> 606 <bitOffset>0</bitOffset> 607 <bitWidth>1</bitWidth> 608 <enumeratedValues> 609 <enumeratedValue> 610 <name>clear</name> 611 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 612 <value>1</value> 613 </enumeratedValue> 614 </enumeratedValues> 615 </field> 616 <field> 617 <name>TX_EMPTY</name> 618 <description>TX FIFO Empty.</description> 619 <bitOffset>1</bitOffset> 620 <bitWidth>1</bitWidth> 621 <enumeratedValues> 622 <enumeratedValue> 623 <name>clear</name> 624 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 625 <value>1</value> 626 </enumeratedValue> 627 </enumeratedValues> 628 </field> 629 <field> 630 <name>RX_THRESH</name> 631 <description>RX FIFO Threshold Crossed.</description> 632 <bitOffset>2</bitOffset> 633 <bitWidth>1</bitWidth> 634 <enumeratedValues> 635 <enumeratedValue> 636 <name>clear</name> 637 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 638 <value>1</value> 639 </enumeratedValue> 640 </enumeratedValues> 641 </field> 642 <field> 643 <name>RX_FULL</name> 644 <description>RX FIFO FULL.</description> 645 <bitOffset>3</bitOffset> 646 <bitWidth>1</bitWidth> 647 <enumeratedValues> 648 <enumeratedValue> 649 <name>clear</name> 650 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 651 <value>1</value> 652 </enumeratedValue> 653 </enumeratedValues> 654 </field> 655 <field> 656 <name>SSA</name> 657 <description>Slave Select Asserted.</description> 658 <bitOffset>4</bitOffset> 659 <bitWidth>1</bitWidth> 660 <enumeratedValues> 661 <enumeratedValue> 662 <name>clear</name> 663 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 664 <value>1</value> 665 </enumeratedValue> 666 </enumeratedValues> 667 </field> 668 <field> 669 <name>SSD</name> 670 <description>Slave Select Deasserted.</description> 671 <bitOffset>5</bitOffset> 672 <bitWidth>1</bitWidth> 673 <enumeratedValues> 674 <enumeratedValue> 675 <name>clear</name> 676 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 677 <value>1</value> 678 </enumeratedValue> 679 </enumeratedValues> 680 </field> 681 <field> 682 <name>FAULT</name> 683 <description>Multi-Master Mode Fault.</description> 684 <bitOffset>8</bitOffset> 685 <bitWidth>1</bitWidth> 686 <enumeratedValues> 687 <enumeratedValue> 688 <name>clear</name> 689 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 690 <value>1</value> 691 </enumeratedValue> 692 </enumeratedValues> 693 </field> 694 <field> 695 <name>ABORT</name> 696 <description>Slave Abort Detected.</description> 697 <bitOffset>9</bitOffset> 698 <bitWidth>1</bitWidth> 699 <enumeratedValues> 700 <enumeratedValue> 701 <name>clear</name> 702 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 703 <value>1</value> 704 </enumeratedValue> 705 </enumeratedValues> 706 </field> 707 <field> 708 <name>M_DONE</name> 709 <description>Master Done, set when SPI Master has completed any transactions.</description> 710 <bitOffset>11</bitOffset> 711 <bitWidth>1</bitWidth> 712 <enumeratedValues> 713 <enumeratedValue> 714 <name>clear</name> 715 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 716 <value>1</value> 717 </enumeratedValue> 718 </enumeratedValues> 719 </field> 720 <field> 721 <name>TX_OVR</name> 722 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data 723 to a full transmit FIFO.</description> 724 <bitOffset>12</bitOffset> 725 <bitWidth>1</bitWidth> 726 <enumeratedValues> 727 <enumeratedValue> 728 <name>clear</name> 729 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 730 <value>1</value> 731 </enumeratedValue> 732 </enumeratedValues> 733 </field> 734 <field> 735 <name>TX_UND</name> 736 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data 737 from an empty transmit FIFO.</description> 738 <bitOffset>13</bitOffset> 739 <bitWidth>1</bitWidth> 740 <enumeratedValues> 741 <enumeratedValue> 742 <name>clear</name> 743 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 744 <value>1</value> 745 </enumeratedValue> 746 </enumeratedValues> 747 </field> 748 <field> 749 <name>RX_OVR</name> 750 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 751 <bitOffset>14</bitOffset> 752 <bitWidth>1</bitWidth> 753 <enumeratedValues> 754 <enumeratedValue> 755 <name>clear</name> 756 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 757 <value>1</value> 758 </enumeratedValue> 759 </enumeratedValues> 760 </field> 761 <field> 762 <name>RX_UND</name> 763 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 764 <bitOffset>15</bitOffset> 765 <bitWidth>1</bitWidth> 766 <enumeratedValues> 767 <enumeratedValue> 768 <name>clear</name> 769 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 770 <value>1</value> 771 </enumeratedValue> 772 </enumeratedValues> 773 </field> 774 </fields> 775 </register> 776 <register> 777 <name>INT_EN</name> 778 <description>Register for enabling interrupts.</description> 779 <addressOffset>0x24</addressOffset> 780 <access>read-write</access> 781 <fields> 782 <field> 783 <name>TX_THRESH</name> 784 <description>TX FIFO Threshold interrupt enable.</description> 785 <bitOffset>0</bitOffset> 786 <bitWidth>1</bitWidth> 787 <enumeratedValues> 788 <enumeratedValue> 789 <name>dis</name> 790 <description>Interrupt is disabled.</description> 791 <value>0</value> 792 </enumeratedValue> 793 <enumeratedValue> 794 <name>en</name> 795 <description>Interrupt is enabled.</description> 796 <value>1</value> 797 </enumeratedValue> 798 </enumeratedValues> 799 </field> 800 <field> 801 <name>TX_EMPTY</name> 802 <description>TX FIFO Empty interrupt enable.</description> 803 <bitOffset>1</bitOffset> 804 <bitWidth>1</bitWidth> 805 <enumeratedValues> 806 <enumeratedValue> 807 <name>dis</name> 808 <description>Interrupt is disabled.</description> 809 <value>0</value> 810 </enumeratedValue> 811 <enumeratedValue> 812 <name>en</name> 813 <description>Interrupt is enabled.</description> 814 <value>1</value> 815 </enumeratedValue> 816 </enumeratedValues> 817 </field> 818 <field> 819 <name>RX_THRESH</name> 820 <description>RX FIFO Threshold Crossed interrupt enable.</description> 821 <bitOffset>2</bitOffset> 822 <bitWidth>1</bitWidth> 823 <enumeratedValues> 824 <enumeratedValue> 825 <name>dis</name> 826 <description>Interrupt is disabled.</description> 827 <value>0</value> 828 </enumeratedValue> 829 <enumeratedValue> 830 <name>en</name> 831 <description>Interrupt is enabled.</description> 832 <value>1</value> 833 </enumeratedValue> 834 </enumeratedValues> 835 </field> 836 <field> 837 <name>RX_FULL</name> 838 <description>RX FIFO FULL interrupt enable.</description> 839 <bitOffset>3</bitOffset> 840 <bitWidth>1</bitWidth> 841 <enumeratedValues> 842 <enumeratedValue> 843 <name>dis</name> 844 <description>Interrupt is disabled.</description> 845 <value>0</value> 846 </enumeratedValue> 847 <enumeratedValue> 848 <name>en</name> 849 <description>Interrupt is enabled.</description> 850 <value>1</value> 851 </enumeratedValue> 852 </enumeratedValues> 853 </field> 854 <field> 855 <name>SSA</name> 856 <description>Slave Select Asserted interrupt enable.</description> 857 <bitOffset>4</bitOffset> 858 <bitWidth>1</bitWidth> 859 <enumeratedValues> 860 <enumeratedValue> 861 <name>dis</name> 862 <description>Interrupt is disabled.</description> 863 <value>0</value> 864 </enumeratedValue> 865 <enumeratedValue> 866 <name>en</name> 867 <description>Interrupt is enabled.</description> 868 <value>1</value> 869 </enumeratedValue> 870 </enumeratedValues> 871 </field> 872 <field> 873 <name>SSD</name> 874 <description>Slave Select Deasserted interrupt enable.</description> 875 <bitOffset>5</bitOffset> 876 <bitWidth>1</bitWidth> 877 <enumeratedValues> 878 <enumeratedValue> 879 <name>dis</name> 880 <description>Interrupt is disabled.</description> 881 <value>0</value> 882 </enumeratedValue> 883 <enumeratedValue> 884 <name>en</name> 885 <description>Interrupt is enabled.</description> 886 <value>1</value> 887 </enumeratedValue> 888 </enumeratedValues> 889 </field> 890 <field> 891 <name>FAULT</name> 892 <description>Multi-Master Mode Fault interrupt enable.</description> 893 <bitOffset>8</bitOffset> 894 <bitWidth>1</bitWidth> 895 <enumeratedValues> 896 <enumeratedValue> 897 <name>dis</name> 898 <description>Interrupt is disabled.</description> 899 <value>0</value> 900 </enumeratedValue> 901 <enumeratedValue> 902 <name>en</name> 903 <description>Interrupt is enabled.</description> 904 <value>1</value> 905 </enumeratedValue> 906 </enumeratedValues> 907 </field> 908 <field> 909 <name>ABORT</name> 910 <description>Slave Abort Detected interrupt enable.</description> 911 <bitOffset>9</bitOffset> 912 <bitWidth>1</bitWidth> 913 <enumeratedValues> 914 <enumeratedValue> 915 <name>dis</name> 916 <description>Interrupt is disabled.</description> 917 <value>0</value> 918 </enumeratedValue> 919 <enumeratedValue> 920 <name>en</name> 921 <description>Interrupt is enabled.</description> 922 <value>1</value> 923 </enumeratedValue> 924 </enumeratedValues> 925 </field> 926 <field> 927 <name>M_DONE</name> 928 <description>Master Done interrupt enable.</description> 929 <bitOffset>11</bitOffset> 930 <bitWidth>1</bitWidth> 931 <enumeratedValues> 932 <enumeratedValue> 933 <name>dis</name> 934 <description>Interrupt is disabled.</description> 935 <value>0</value> 936 </enumeratedValue> 937 <enumeratedValue> 938 <name>en</name> 939 <description>Interrupt is enabled.</description> 940 <value>1</value> 941 </enumeratedValue> 942 </enumeratedValues> 943 </field> 944 <field> 945 <name>TX_OVR</name> 946 <description>Transmit FIFO Overrun interrupt enable.</description> 947 <bitOffset>12</bitOffset> 948 <bitWidth>1</bitWidth> 949 <enumeratedValues> 950 <enumeratedValue> 951 <name>dis</name> 952 <description>Interrupt is disabled.</description> 953 <value>0</value> 954 </enumeratedValue> 955 <enumeratedValue> 956 <name>en</name> 957 <description>Interrupt is enabled.</description> 958 <value>1</value> 959 </enumeratedValue> 960 </enumeratedValues> 961 </field> 962 <field> 963 <name>TX_UND</name> 964 <description>Transmit FIFO Underrun interrupt enable.</description> 965 <bitOffset>13</bitOffset> 966 <bitWidth>1</bitWidth> 967 <enumeratedValues> 968 <enumeratedValue> 969 <name>dis</name> 970 <description>Interrupt is disabled.</description> 971 <value>0</value> 972 </enumeratedValue> 973 <enumeratedValue> 974 <name>en</name> 975 <description>Interrupt is enabled.</description> 976 <value>1</value> 977 </enumeratedValue> 978 </enumeratedValues> 979 </field> 980 <field> 981 <name>RX_OVR</name> 982 <description>Receive FIFO Overrun interrupt enable.</description> 983 <bitOffset>14</bitOffset> 984 <bitWidth>1</bitWidth> 985 <enumeratedValues> 986 <enumeratedValue> 987 <name>dis</name> 988 <description>Interrupt is disabled.</description> 989 <value>0</value> 990 </enumeratedValue> 991 <enumeratedValue> 992 <name>en</name> 993 <description>Interrupt is enabled.</description> 994 <value>1</value> 995 </enumeratedValue> 996 </enumeratedValues> 997 </field> 998 <field> 999 <name>RX_UND</name> 1000 <description>Receive FIFO Underrun interrupt enable.</description> 1001 <bitOffset>15</bitOffset> 1002 <bitWidth>1</bitWidth> 1003 <enumeratedValues> 1004 <enumeratedValue> 1005 <name>dis</name> 1006 <description>Interrupt is disabled.</description> 1007 <value>0</value> 1008 </enumeratedValue> 1009 <enumeratedValue> 1010 <name>en</name> 1011 <description>Interrupt is enabled.</description> 1012 <value>1</value> 1013 </enumeratedValue> 1014 </enumeratedValues> 1015 </field> 1016 </fields> 1017 </register> 1018 <register> 1019 <name>WAKE_FL</name> 1020 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1021 <addressOffset>0x28</addressOffset> 1022 <access>read-write</access> 1023 <fields> 1024 <field> 1025 <name>TX_THRESH</name> 1026 <description>Wake on TX FIFO Threshold Crossed.</description> 1027 <bitOffset>0</bitOffset> 1028 <bitWidth>1</bitWidth> 1029 <enumeratedValues> 1030 <enumeratedValue> 1031 <name>clear</name> 1032 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1033 <value>1</value> 1034 </enumeratedValue> 1035 </enumeratedValues> 1036 </field> 1037 <field> 1038 <name>TX_EMPTY</name> 1039 <description>Wake on TX FIFO Empty.</description> 1040 <bitOffset>1</bitOffset> 1041 <bitWidth>1</bitWidth> 1042 <enumeratedValues> 1043 <enumeratedValue> 1044 <name>clear</name> 1045 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1046 <value>1</value> 1047 </enumeratedValue> 1048 </enumeratedValues> 1049 </field> 1050 <field> 1051 <name>RX_THRESH</name> 1052 <description>Wake on RX FIFO Threshold Crossed.</description> 1053 <bitOffset>2</bitOffset> 1054 <bitWidth>1</bitWidth> 1055 <enumeratedValues> 1056 <enumeratedValue> 1057 <name>clear</name> 1058 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1059 <value>1</value> 1060 </enumeratedValue> 1061 </enumeratedValues> 1062 </field> 1063 <field> 1064 <name>RX_FULL</name> 1065 <description>Wake on RX FIFO Full.</description> 1066 <bitOffset>3</bitOffset> 1067 <bitWidth>1</bitWidth> 1068 <enumeratedValues> 1069 <enumeratedValue> 1070 <name>clear</name> 1071 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1072 <value>1</value> 1073 </enumeratedValue> 1074 </enumeratedValues> 1075 </field> 1076 </fields> 1077 </register> 1078 <register> 1079 <name>WAKE_EN</name> 1080 <description>Register for wake up enable.</description> 1081 <addressOffset>0x2C</addressOffset> 1082 <access>read-write</access> 1083 <fields> 1084 <field> 1085 <name>TX_THRESH</name> 1086 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1087 <bitOffset>0</bitOffset> 1088 <bitWidth>1</bitWidth> 1089 <enumeratedValues> 1090 <enumeratedValue> 1091 <name>dis</name> 1092 <description>Wakeup source disabled.</description> 1093 <value>0</value> 1094 </enumeratedValue> 1095 <enumeratedValue> 1096 <name>en</name> 1097 <description>Wakeup source enabled.</description> 1098 <value>1</value> 1099 </enumeratedValue> 1100 </enumeratedValues> 1101 </field> 1102 <field> 1103 <name>TX_EMPTY</name> 1104 <description>Wake on TX FIFO Empty Enable.</description> 1105 <bitOffset>1</bitOffset> 1106 <bitWidth>1</bitWidth> 1107 <enumeratedValues> 1108 <enumeratedValue> 1109 <name>dis</name> 1110 <description>Wakeup source disabled.</description> 1111 <value>0</value> 1112 </enumeratedValue> 1113 <enumeratedValue> 1114 <name>en</name> 1115 <description>Wakeup source enabled.</description> 1116 <value>1</value> 1117 </enumeratedValue> 1118 </enumeratedValues> 1119 </field> 1120 <field> 1121 <name>RX_THRESH</name> 1122 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1123 <bitOffset>2</bitOffset> 1124 <bitWidth>1</bitWidth> 1125 <enumeratedValues> 1126 <enumeratedValue> 1127 <name>dis</name> 1128 <description>Wakeup source disabled.</description> 1129 <value>0</value> 1130 </enumeratedValue> 1131 <enumeratedValue> 1132 <name>en</name> 1133 <description>Wakeup source enabled.</description> 1134 <value>1</value> 1135 </enumeratedValue> 1136 </enumeratedValues> 1137 </field> 1138 <field> 1139 <name>RX_FULL</name> 1140 <description>Wake on RX FIFO Full Enable.</description> 1141 <bitOffset>3</bitOffset> 1142 <bitWidth>1</bitWidth> 1143 <enumeratedValues> 1144 <enumeratedValue> 1145 <name>dis</name> 1146 <description>Wakeup source disabled.</description> 1147 <value>0</value> 1148 </enumeratedValue> 1149 <enumeratedValue> 1150 <name>en</name> 1151 <description>Wakeup source enabled.</description> 1152 <value>1</value> 1153 </enumeratedValue> 1154 </enumeratedValues> 1155 </field> 1156 </fields> 1157 </register> 1158 <register> 1159 <name>STAT</name> 1160 <description>SPI Status register.</description> 1161 <addressOffset>0x30</addressOffset> 1162 <access>read-only</access> 1163 <fields> 1164 <field> 1165 <name>BUSY</name> 1166 <description>SPI active status. In Master mode, set when transaction starts, 1167 cleared when last bit of last character is acted upon and Slave Select 1168 de-assertion would occur. In Slave mode, set when Slave Select is 1169 asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 1170 </description> 1171 <bitOffset>0</bitOffset> 1172 <bitWidth>1</bitWidth> 1173 <enumeratedValues> 1174 <enumeratedValue> 1175 <name>not</name> 1176 <description>SPI not active.</description> 1177 <value>0</value> 1178 </enumeratedValue> 1179 <enumeratedValue> 1180 <name>active</name> 1181 <description>SPI active.</description> 1182 <value>1</value> 1183 </enumeratedValue> 1184 </enumeratedValues> 1185 </field> 1186 </fields> 1187 </register> 1188 <register> 1189 <name>XMEM_CTRL</name> 1190 <description>Register to control external memory.</description> 1191 <addressOffset>0x34</addressOffset> 1192 <access>read-write</access> 1193 <fields> 1194 <field> 1195 <name>RD_CMD</name> 1196 <description>Read command.</description> 1197 <bitOffset>0</bitOffset> 1198 <bitWidth>8</bitWidth> 1199 </field> 1200 <field> 1201 <name>WR_CMD</name> 1202 <description>Write command.</description> 1203 <bitOffset>8</bitOffset> 1204 <bitWidth>8</bitWidth> 1205 </field> 1206 <field> 1207 <name>DUMMY_CLK</name> 1208 <description>Dummy clocks.</description> 1209 <bitOffset>16</bitOffset> 1210 <bitWidth>8</bitWidth> 1211 </field> 1212 <field> 1213 <name>XMEM_EN</name> 1214 <description>XMEM enable.</description> 1215 <bitOffset>31</bitOffset> 1216 <bitWidth>1</bitWidth> 1217 </field> 1218 </fields> 1219 </register> 1220 </registers> 1221 </peripheral> 1222 <!-- SPIXR for Data XIP interface --> 1223</device>
