1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXR</name> 5 <description>SPIXR peripheral.</description> 6 <baseAddress>0x4003A000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>DATA32</name> 15 <description>Register for reading and writing the FIFO.</description> 16 <addressOffset>0x00</addressOffset> 17 <size>32</size> 18 <access>read-write</access> 19 <fields> 20 <field> 21 <name>DATA</name> 22 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 23 <bitOffset>0</bitOffset> 24 <bitWidth>32</bitWidth> 25 </field> 26 </fields> 27 </register> 28 <register> 29 <dim>2</dim> 30 <dimIncrement>2</dimIncrement> 31 <name>DATA16[%s]</name> 32 <description>Register for reading and writing the FIFO.</description> 33 <alternateRegister>DATA32</alternateRegister> 34 <addressOffset>0x00</addressOffset> 35 <size>16</size> 36 <access>read-write</access> 37 <fields> 38 <field> 39 <name>DATA</name> 40 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>16</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <dim>4</dim> 48 <dimIncrement>1</dimIncrement> 49 <name>DATA8[%s]</name> 50 <description>Register for reading and writing the FIFO.</description> 51 <alternateRegister>DATA32</alternateRegister> 52 <addressOffset>0x00</addressOffset> 53 <size>8</size> 54 <access>read-write</access> 55 <fields> 56 <field> 57 <name>DATA</name> 58 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 59 <bitOffset>0</bitOffset> 60 <bitWidth>8</bitWidth> 61 </field> 62 </fields> 63 </register> 64 <register> 65 <name>ctrl1</name> 66 <description>Register for controlling SPI peripheral.</description> 67 <addressOffset>0x04</addressOffset> 68 <access>read-write</access> 69 <fields> 70 <field> 71 <name>SPIEN</name> 72 <description>SPI Enable.</description> 73 <bitOffset>0</bitOffset> 74 <bitWidth>1</bitWidth> 75 <enumeratedValues> 76 <enumeratedValue> 77 <name>dis</name> 78 <description>SPI is disabled.</description> 79 <value>0</value> 80 </enumeratedValue> 81 <enumeratedValue> 82 <name>en</name> 83 <description>SPI is enabled.</description> 84 <value>1</value> 85 </enumeratedValue> 86 </enumeratedValues> 87 </field> 88 <field> 89 <name>MMEN</name> 90 <description>Master Mode Enable.</description> 91 <bitOffset>1</bitOffset> 92 <bitWidth>1</bitWidth> 93 <enumeratedValues> 94 <enumeratedValue> 95 <name>dis</name> 96 <description>SPI is Slave mode.</description> 97 <value>0</value> 98 </enumeratedValue> 99 <enumeratedValue> 100 <name>en</name> 101 <description>SPI is Master mode.</description> 102 <value>1</value> 103 </enumeratedValue> 104 </enumeratedValues> 105 </field> 106 <field> 107 <name>SSIO</name> 108 <description>Slave Select 0, IO direction, to support Multi-Master mode, 109 Slave Select 0 can be input in Master mode. This bit has no 110 effect in slave mode.</description> 111 <bitOffset>4</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>output</name> 116 <description>Slave select 0 is output.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>input</name> 121 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>TX_START</name> 128 <description>Start Transmit.</description> 129 <bitOffset>5</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>start</name> 134 <description>Master Initiates a transaction, this bit is 135 self clearing when transactions are done. If 136 a transaction completes, and the TX FIFO 137 is empty, the Master halts, if a transaction 138 completes, and the TX FIFO is not empty, 139 the Master initiates another transaction.</description> 140 <value>1</value> 141 </enumeratedValue> 142 </enumeratedValues> 143 </field> 144 <field> 145 <name>SS_CTRL</name> 146 <description>Slave Select Control.</description> 147 <bitOffset>8</bitOffset> 148 <bitWidth>1</bitWidth> 149 <enumeratedValues> 150 <enumeratedValue> 151 <name>deassert</name> 152 <description>SPI de-asserts Slave Select at the end of a transaction.</description> 153 <value>0</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>assert</name> 157 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 158 <value>1</value> 159 </enumeratedValue> 160 </enumeratedValues> 161 </field> 162 <field> 163 <name>SS</name> 164 <description>Slave Select, when in Master mode selects which Slave devices are 165 selected. More than one Slave device can be selected.</description> 166 <bitOffset>16</bitOffset> 167 <bitWidth>1</bitWidth> 168 </field> 169 </fields> 170 </register> 171 <register> 172 <name>ctrl2</name> 173 <description>Register for controlling SPI peripheral.</description> 174 <addressOffset>0x08</addressOffset> 175 <access>read-write</access> 176 <fields> 177 <field> 178 <name>TX_NUM_CHAR</name> 179 <description>Nubmer of Characters to transmit.</description> 180 <bitOffset>0</bitOffset> 181 <bitWidth>16</bitWidth> 182 </field> 183 <field> 184 <name>RX_NUM_CHAR</name> 185 <description>Nubmer of Characters to receive.</description> 186 <bitOffset>16</bitOffset> 187 <bitWidth>16</bitWidth> 188 </field> 189 </fields> 190 </register> 191 <register> 192 <name>ctrl3</name> 193 <description>Register for controlling SPI peripheral.</description> 194 <addressOffset>0x0C</addressOffset> 195 <access>read-write</access> 196 <fields> 197 <field> 198 <name>CPHA</name> 199 <description>Clock Phase.</description> 200 <bitOffset>0</bitOffset> 201 <bitWidth>1</bitWidth> 202 </field> 203 <field> 204 <name>CPOL</name> 205 <description>Clock Polarity.</description> 206 <bitOffset>1</bitOffset> 207 <bitWidth>1</bitWidth> 208 </field> 209 <field> 210 <name>SCLK_FB_INV</name> 211 <description>Invert SCLK Feedback in Master Mode.</description> 212 <bitOffset>4</bitOffset> 213 <bitWidth>1</bitWidth> 214 <enumeratedValues> 215 <enumeratedValue> 216 <name>NON_INV</name> 217 <description>SCLK is not inverted to Line Receiver.</description> 218 <value>0</value> 219 </enumeratedValue> 220 <enumeratedValue> 221 <name>INV</name> 222 <description>SCLK is inverted to Line Receiver.</description> 223 <value>1</value> 224 </enumeratedValue> 225 </enumeratedValues> 226 </field> 227 <field> 228 <name>NUMBITS</name> 229 <description>Number of Bits per character.</description> 230 <bitOffset>8</bitOffset> 231 <bitWidth>4</bitWidth> 232 <enumeratedValues> 233 <enumeratedValue> 234 <name>0</name> 235 <description>16 bits per character.</description> 236 <value>0</value> 237 </enumeratedValue> 238 </enumeratedValues> 239 </field> 240 <field> 241 <name>DATA_WIDTH</name> 242 <description>SPI Data width.</description> 243 <bitOffset>12</bitOffset> 244 <bitWidth>2</bitWidth> 245 <enumeratedValues> 246 <enumeratedValue> 247 <name>Mono</name> 248 <description>1 data pin.</description> 249 <value>0</value> 250 </enumeratedValue> 251 <enumeratedValue> 252 <name>Dual</name> 253 <description>2 data pins.</description> 254 <value>1</value> 255 </enumeratedValue> 256 <enumeratedValue> 257 <name>Quad</name> 258 <description>4 data pins.</description> 259 <value>2</value> 260 </enumeratedValue> 261 </enumeratedValues> 262 </field> 263 <field> 264 <name>THREE_WIRE</name> 265 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 266 <bitOffset>15</bitOffset> 267 <bitWidth>1</bitWidth> 268 <enumeratedValues> 269 <enumeratedValue> 270 <name>dis</name> 271 <description>Use four wire mode (Mono only).</description> 272 <value>0</value> 273 </enumeratedValue> 274 <enumeratedValue> 275 <name>en</name> 276 <description>Use three wire mode.</description> 277 <value>1</value> 278 </enumeratedValue> 279 </enumeratedValues> 280 </field> 281 <field> 282 <name>SSPOL</name> 283 <description>Slave Select Polarity</description> 284 <bitOffset>16</bitOffset> 285 <bitWidth>1</bitWidth> 286 </field> 287 </fields> 288 </register> 289 <register> 290 <name>ss_time</name> 291 <description>Register for controlling SPI peripheral.</description> 292 <addressOffset>0x10</addressOffset> 293 <access>read-write</access> 294 <fields> 295 <field> 296 <name>SSACT1</name> 297 <description>Slave Select Action delay 1.</description> 298 <bitOffset>0</bitOffset> 299 <bitWidth>8</bitWidth> 300 <enumeratedValues> 301 <enumeratedValue> 302 <name>256</name> 303 <description>256 system clocks between SS active and first serial clock edge.</description> 304 <value>0</value> 305 </enumeratedValue> 306 </enumeratedValues> 307 </field> 308 <field> 309 <name>SSACT2</name> 310 <description>Slave Select Action delay 2.</description> 311 <bitOffset>8</bitOffset> 312 <bitWidth>8</bitWidth> 313 <enumeratedValues> 314 <enumeratedValue> 315 <name>256</name> 316 <description>256 system clocks between last serial clock edge and SS inactive.</description> 317 <value>0</value> 318 </enumeratedValue> 319 </enumeratedValues> 320 </field> 321 <field> 322 <name>SSINACT</name> 323 <description>Slave Select Inactive delay.</description> 324 <bitOffset>16</bitOffset> 325 <bitWidth>8</bitWidth> 326 <enumeratedValues> 327 <enumeratedValue> 328 <name>256</name> 329 <description>256 system clocks between transactions.</description> 330 <value>0</value> 331 </enumeratedValue> 332 </enumeratedValues> 333 </field> 334 </fields> 335 </register> 336 <register> 337 <name>BRG_CTRL</name> 338 <description>Register for controlling SPI clock rate.</description> 339 <addressOffset>0x14</addressOffset> 340 <access>read-write</access> 341 <fields> 342 <field> 343 <name>LOW</name> 344 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 345 <bitOffset>0</bitOffset> 346 <bitWidth>8</bitWidth> 347 <enumeratedValues> 348 <enumeratedValue> 349 <name>Dis</name> 350 <description>Duty cycle control of serial clock generation is disabled.</description> 351 <value>0</value> 352 </enumeratedValue> 353 </enumeratedValues> 354 </field> 355 <field> 356 <name>HI</name> 357 <description>High duty cycle control. In timer mode, reload[15:8].</description> 358 <bitOffset>8</bitOffset> 359 <bitWidth>8</bitWidth> 360 <enumeratedValues> 361 <enumeratedValue> 362 <name>Dis</name> 363 <description>Duty cycle control of serial clock generation is disabled.</description> 364 <value>0</value> 365 </enumeratedValue> 366 </enumeratedValues> 367 </field> 368 <field> 369 <name>SCALE</name> 370 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 371 <bitOffset>16</bitOffset> 372 <bitWidth>4</bitWidth> 373 </field> 374 </fields> 375 </register> 376 <register> 377 <name>DMA</name> 378 <description>Register for controlling DMA.</description> 379 <addressOffset>0x1C</addressOffset> 380 <access>read-write</access> 381 <fields> 382 <field> 383 <name>TX_FIFO_LEVEL</name> 384 <description>Transmit FIFO level that will trigger a DMA request, also level for 385 threshold status. When TX FIFO has fewer than this many bytes, the 386 associated events and conditions are triggered.</description> 387 <bitOffset>0</bitOffset> 388 <bitWidth>6</bitWidth> 389 </field> 390 <field> 391 <name>TX_FIFO_EN</name> 392 <description>Transmit FIFO enabled for SPI transactions.</description> 393 <bitOffset>6</bitOffset> 394 <bitWidth>1</bitWidth> 395 <enumeratedValues> 396 <enumeratedValue> 397 <name>dis</name> 398 <description>Transmit FIFO is not enabled.</description> 399 <value>0</value> 400 </enumeratedValue> 401 <enumeratedValue> 402 <name>en</name> 403 <description>Transmit FIFO is enabled.</description> 404 <value>1</value> 405 </enumeratedValue> 406 </enumeratedValues> 407 </field> 408 <field> 409 <name>TX_FIFO_CLEAR</name> 410 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 411 pointers. This should be done when FIFO is not being accessed on the SPI side. 412 </description> 413 <bitOffset>7</bitOffset> 414 <bitWidth>1</bitWidth> 415 <enumeratedValues> 416 <enumeratedValue> 417 <name>CLEAR</name> 418 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 419 <value>1</value> 420 </enumeratedValue> 421 </enumeratedValues> 422 </field> 423 <field> 424 <name>TX_FIFO_CNT</name> 425 <description>Count of entries in TX FIFO.</description> 426 <bitOffset>8</bitOffset> 427 <bitWidth>5</bitWidth> 428 </field> 429 <field> 430 <name>TX_DMA_EN</name> 431 <description>TX DMA Enable.</description> 432 <bitOffset>15</bitOffset> 433 <bitWidth>1</bitWidth> 434 <enumeratedValues> 435 <enumeratedValue> 436 <name>DIS</name> 437 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 438 <value>0</value> 439 </enumeratedValue> 440 <enumeratedValue> 441 <name>en</name> 442 <description>TX DMA requests are enabled.</description> 443 <value>1</value> 444 </enumeratedValue> 445 </enumeratedValues> 446 </field> 447 <field> 448 <name>RX_FIFO_LEVEL</name> 449 <description>Receive FIFO level that will trigger a DMA request, also level for 450 threshold status. When RX FIFO has more than this many bytes, the 451 associated events and conditions are triggered.</description> 452 <bitOffset>16</bitOffset> 453 <bitWidth>6</bitWidth> 454 </field> 455 <field> 456 <name>RX_FIFO_EN</name> 457 <description>Receive FIFO enabled for SPI transactions.</description> 458 <bitOffset>22</bitOffset> 459 <bitWidth>1</bitWidth> 460 <enumeratedValues> 461 <enumeratedValue> 462 <name>DIS</name> 463 <description>Receive FIFO is not enabled.</description> 464 <value>0</value> 465 </enumeratedValue> 466 <enumeratedValue> 467 <name>en</name> 468 <description>Receive FIFO is enabled.</description> 469 <value>1</value> 470 </enumeratedValue> 471 </enumeratedValues> 472 </field> 473 <field> 474 <name>RX_FIFO_CLEAR</name> 475 <description>Clear RX FIFO, clear is accomplished by resetting the read and write 476 pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 477 <bitOffset>23</bitOffset> 478 <bitWidth>1</bitWidth> 479 <enumeratedValues> 480 <enumeratedValue> 481 <name>CLEAR</name> 482 <description>Clear the Receive FIFIO, clears any pending RX FIFO status.</description> 483 <value>1</value> 484 </enumeratedValue> 485 </enumeratedValues> 486 </field> 487 <field> 488 <name>RX_FIFO_CNT</name> 489 <description>Count of entries in RX FIFO.</description> 490 <bitOffset>24</bitOffset> 491 <bitWidth>6</bitWidth> 492 </field> 493 <field> 494 <name>RX_DMA_EN</name> 495 <description>RX DMA Enable.</description> 496 <bitOffset>31</bitOffset> 497 <bitWidth>1</bitWidth> 498 <enumeratedValues> 499 <enumeratedValue> 500 <name>dis</name> 501 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 502 <value>0</value> 503 </enumeratedValue> 504 <enumeratedValue> 505 <name>en</name> 506 <description>RX DMA requests are enabled.</description> 507 <value>1</value> 508 </enumeratedValue> 509 </enumeratedValues> 510 </field> 511 </fields> 512 </register> 513 <register> 514 <name>int_fl</name> 515 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 516 <addressOffset>0x20</addressOffset> 517 <access>read-write</access> 518 <fields> 519 <field> 520 <name>TX_THRESH</name> 521 <description>TX FIFO Threshold Crossed.</description> 522 <bitOffset>0</bitOffset> 523 <bitWidth>1</bitWidth> 524 <enumeratedValues> 525 <enumeratedValue> 526 <name>clear</name> 527 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 528 <value>1</value> 529 </enumeratedValue> 530 </enumeratedValues> 531 </field> 532 <field> 533 <name>TX_EMPTY</name> 534 <description>TX FIFO Empty.</description> 535 <bitOffset>1</bitOffset> 536 <bitWidth>1</bitWidth> 537 <enumeratedValues> 538 <enumeratedValue> 539 <name>clear</name> 540 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 541 <value>1</value> 542 </enumeratedValue> 543 </enumeratedValues> 544 </field> 545 <field> 546 <name>RX_THRESH</name> 547 <description>RX FIFO Threshold Crossed.</description> 548 <bitOffset>2</bitOffset> 549 <bitWidth>1</bitWidth> 550 <enumeratedValues> 551 <enumeratedValue> 552 <name>clear</name> 553 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 554 <value>1</value> 555 </enumeratedValue> 556 </enumeratedValues> 557 </field> 558 <field> 559 <name>RX_FULL</name> 560 <description>RX FIFO FULL.</description> 561 <bitOffset>3</bitOffset> 562 <bitWidth>1</bitWidth> 563 <enumeratedValues> 564 <enumeratedValue> 565 <name>clear</name> 566 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 567 <value>1</value> 568 </enumeratedValue> 569 </enumeratedValues> 570 </field> 571 <field> 572 <name>SSA</name> 573 <description>Slave Select Asserted.</description> 574 <bitOffset>4</bitOffset> 575 <bitWidth>1</bitWidth> 576 <enumeratedValues> 577 <enumeratedValue> 578 <name>clear</name> 579 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 580 <value>1</value> 581 </enumeratedValue> 582 </enumeratedValues> 583 </field> 584 <field> 585 <name>SSD</name> 586 <description>Slave Select Deasserted.</description> 587 <bitOffset>5</bitOffset> 588 <bitWidth>1</bitWidth> 589 <enumeratedValues> 590 <enumeratedValue> 591 <name>clear</name> 592 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 593 <value>1</value> 594 </enumeratedValue> 595 </enumeratedValues> 596 </field> 597 <field> 598 <name>FAULT</name> 599 <description>Multi-Master Mode Fault.</description> 600 <bitOffset>8</bitOffset> 601 <bitWidth>1</bitWidth> 602 <enumeratedValues> 603 <enumeratedValue> 604 <name>clear</name> 605 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 606 <value>1</value> 607 </enumeratedValue> 608 </enumeratedValues> 609 </field> 610 <field> 611 <name>ABORT</name> 612 <description>Slave Abort Detected.</description> 613 <bitOffset>9</bitOffset> 614 <bitWidth>1</bitWidth> 615 <enumeratedValues> 616 <enumeratedValue> 617 <name>clear</name> 618 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 619 <value>1</value> 620 </enumeratedValue> 621 </enumeratedValues> 622 </field> 623 <field> 624 <name>M_DONE</name> 625 <description>Master Done, set when SPI Master has completed any transactions.</description> 626 <bitOffset>11</bitOffset> 627 <bitWidth>1</bitWidth> 628 <enumeratedValues> 629 <enumeratedValue> 630 <name>clear</name> 631 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 632 <value>1</value> 633 </enumeratedValue> 634 </enumeratedValues> 635 </field> 636 <field> 637 <name>TX_OVR</name> 638 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data 639 to a full transmit FIFO.</description> 640 <bitOffset>12</bitOffset> 641 <bitWidth>1</bitWidth> 642 <enumeratedValues> 643 <enumeratedValue> 644 <name>clear</name> 645 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 646 <value>1</value> 647 </enumeratedValue> 648 </enumeratedValues> 649 </field> 650 <field> 651 <name>TX_UND</name> 652 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data 653 from an empty transmit FIFO.</description> 654 <bitOffset>13</bitOffset> 655 <bitWidth>1</bitWidth> 656 <enumeratedValues> 657 <enumeratedValue> 658 <name>clear</name> 659 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 660 <value>1</value> 661 </enumeratedValue> 662 </enumeratedValues> 663 </field> 664 <field> 665 <name>RX_OVR</name> 666 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 667 <bitOffset>14</bitOffset> 668 <bitWidth>1</bitWidth> 669 <enumeratedValues> 670 <enumeratedValue> 671 <name>clear</name> 672 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 673 <value>1</value> 674 </enumeratedValue> 675 </enumeratedValues> 676 </field> 677 <field> 678 <name>RX_UND</name> 679 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 680 <bitOffset>15</bitOffset> 681 <bitWidth>1</bitWidth> 682 <enumeratedValues> 683 <enumeratedValue> 684 <name>clear</name> 685 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 686 <value>1</value> 687 </enumeratedValue> 688 </enumeratedValues> 689 </field> 690 </fields> 691 </register> 692 <register> 693 <name>int_en</name> 694 <description>Register for enabling interrupts.</description> 695 <addressOffset>0x24</addressOffset> 696 <access>read-write</access> 697 <fields> 698 <field> 699 <name>TX_THRESH</name> 700 <description>TX FIFO Threshold interrupt enable.</description> 701 <bitOffset>0</bitOffset> 702 <bitWidth>1</bitWidth> 703 <enumeratedValues> 704 <enumeratedValue> 705 <name>dis</name> 706 <description>Interrupt is disabled.</description> 707 <value>0</value> 708 </enumeratedValue> 709 <enumeratedValue> 710 <name>en</name> 711 <description>Interrupt is enabled.</description> 712 <value>1</value> 713 </enumeratedValue> 714 </enumeratedValues> 715 </field> 716 <field> 717 <name>TX_EMPTY</name> 718 <description>TX FIFO Empty interrupt enable.</description> 719 <bitOffset>1</bitOffset> 720 <bitWidth>1</bitWidth> 721 <enumeratedValues> 722 <enumeratedValue> 723 <name>dis</name> 724 <description>Interrupt is disabled.</description> 725 <value>0</value> 726 </enumeratedValue> 727 <enumeratedValue> 728 <name>en</name> 729 <description>Interrupt is enabled.</description> 730 <value>1</value> 731 </enumeratedValue> 732 </enumeratedValues> 733 </field> 734 <field> 735 <name>RX_THRESH</name> 736 <description>RX FIFO Threshold Crossed interrupt enable.</description> 737 <bitOffset>2</bitOffset> 738 <bitWidth>1</bitWidth> 739 <enumeratedValues> 740 <enumeratedValue> 741 <name>dis</name> 742 <description>Interrupt is disabled.</description> 743 <value>0</value> 744 </enumeratedValue> 745 <enumeratedValue> 746 <name>en</name> 747 <description>Interrupt is enabled.</description> 748 <value>1</value> 749 </enumeratedValue> 750 </enumeratedValues> 751 </field> 752 <field> 753 <name>RX_FULL</name> 754 <description>RX FIFO FULL interrupt enable.</description> 755 <bitOffset>3</bitOffset> 756 <bitWidth>1</bitWidth> 757 <enumeratedValues> 758 <enumeratedValue> 759 <name>dis</name> 760 <description>Interrupt is disabled.</description> 761 <value>0</value> 762 </enumeratedValue> 763 <enumeratedValue> 764 <name>en</name> 765 <description>Interrupt is enabled.</description> 766 <value>1</value> 767 </enumeratedValue> 768 </enumeratedValues> 769 </field> 770 <field> 771 <name>SSA</name> 772 <description>Slave Select Asserted interrupt enable.</description> 773 <bitOffset>4</bitOffset> 774 <bitWidth>1</bitWidth> 775 <enumeratedValues> 776 <enumeratedValue> 777 <name>dis</name> 778 <description>Interrupt is disabled.</description> 779 <value>0</value> 780 </enumeratedValue> 781 <enumeratedValue> 782 <name>en</name> 783 <description>Interrupt is enabled.</description> 784 <value>1</value> 785 </enumeratedValue> 786 </enumeratedValues> 787 </field> 788 <field> 789 <name>SSD</name> 790 <description>Slave Select Deasserted interrupt enable.</description> 791 <bitOffset>5</bitOffset> 792 <bitWidth>1</bitWidth> 793 <enumeratedValues> 794 <enumeratedValue> 795 <name>dis</name> 796 <description>Interrupt is disabled.</description> 797 <value>0</value> 798 </enumeratedValue> 799 <enumeratedValue> 800 <name>en</name> 801 <description>Interrupt is enabled.</description> 802 <value>1</value> 803 </enumeratedValue> 804 </enumeratedValues> 805 </field> 806 <field> 807 <name>FAULT</name> 808 <description>Multi-Master Mode Fault interrupt enable.</description> 809 <bitOffset>8</bitOffset> 810 <bitWidth>1</bitWidth> 811 <enumeratedValues> 812 <enumeratedValue> 813 <name>dis</name> 814 <description>Interrupt is disabled.</description> 815 <value>0</value> 816 </enumeratedValue> 817 <enumeratedValue> 818 <name>en</name> 819 <description>Interrupt is enabled.</description> 820 <value>1</value> 821 </enumeratedValue> 822 </enumeratedValues> 823 </field> 824 <field> 825 <name>ABORT</name> 826 <description>Slave Abort Detected interrupt enable.</description> 827 <bitOffset>9</bitOffset> 828 <bitWidth>1</bitWidth> 829 <enumeratedValues> 830 <enumeratedValue> 831 <name>dis</name> 832 <description>Interrupt is disabled.</description> 833 <value>0</value> 834 </enumeratedValue> 835 <enumeratedValue> 836 <name>en</name> 837 <description>Interrupt is enabled.</description> 838 <value>1</value> 839 </enumeratedValue> 840 </enumeratedValues> 841 </field> 842 <field> 843 <name>M_DONE</name> 844 <description>Master Done interrupt enable.</description> 845 <bitOffset>11</bitOffset> 846 <bitWidth>1</bitWidth> 847 <enumeratedValues> 848 <enumeratedValue> 849 <name>dis</name> 850 <description>Interrupt is disabled.</description> 851 <value>0</value> 852 </enumeratedValue> 853 <enumeratedValue> 854 <name>en</name> 855 <description>Interrupt is enabled.</description> 856 <value>1</value> 857 </enumeratedValue> 858 </enumeratedValues> 859 </field> 860 <field> 861 <name>TX_OVR</name> 862 <description>Transmit FIFO Overrun interrupt enable.</description> 863 <bitOffset>12</bitOffset> 864 <bitWidth>1</bitWidth> 865 <enumeratedValues> 866 <enumeratedValue> 867 <name>dis</name> 868 <description>Interrupt is disabled.</description> 869 <value>0</value> 870 </enumeratedValue> 871 <enumeratedValue> 872 <name>en</name> 873 <description>Interrupt is enabled.</description> 874 <value>1</value> 875 </enumeratedValue> 876 </enumeratedValues> 877 </field> 878 <field> 879 <name>TX_UND</name> 880 <description>Transmit FIFO Underrun interrupt enable.</description> 881 <bitOffset>13</bitOffset> 882 <bitWidth>1</bitWidth> 883 <enumeratedValues> 884 <enumeratedValue> 885 <name>dis</name> 886 <description>Interrupt is disabled.</description> 887 <value>0</value> 888 </enumeratedValue> 889 <enumeratedValue> 890 <name>en</name> 891 <description>Interrupt is enabled.</description> 892 <value>1</value> 893 </enumeratedValue> 894 </enumeratedValues> 895 </field> 896 <field> 897 <name>RX_OVR</name> 898 <description>Receive FIFO Overrun interrupt enable.</description> 899 <bitOffset>14</bitOffset> 900 <bitWidth>1</bitWidth> 901 <enumeratedValues> 902 <enumeratedValue> 903 <name>dis</name> 904 <description>Interrupt is disabled.</description> 905 <value>0</value> 906 </enumeratedValue> 907 <enumeratedValue> 908 <name>en</name> 909 <description>Interrupt is enabled.</description> 910 <value>1</value> 911 </enumeratedValue> 912 </enumeratedValues> 913 </field> 914 <field> 915 <name>RX_UND</name> 916 <description>Receive FIFO Underrun interrupt enable.</description> 917 <bitOffset>15</bitOffset> 918 <bitWidth>1</bitWidth> 919 <enumeratedValues> 920 <enumeratedValue> 921 <name>dis</name> 922 <description>Interrupt is disabled.</description> 923 <value>0</value> 924 </enumeratedValue> 925 <enumeratedValue> 926 <name>en</name> 927 <description>Interrupt is enabled.</description> 928 <value>1</value> 929 </enumeratedValue> 930 </enumeratedValues> 931 </field> 932 </fields> 933 </register> 934 <register> 935 <name>WAKE_FL</name> 936 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 937 <addressOffset>0x28</addressOffset> 938 <access>read-write</access> 939 <fields> 940 <field> 941 <name>TX_THRESH</name> 942 <description>Wake on TX FIFO Threshold Crossed.</description> 943 <bitOffset>0</bitOffset> 944 <bitWidth>1</bitWidth> 945 <enumeratedValues> 946 <enumeratedValue> 947 <name>clear</name> 948 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 949 <value>1</value> 950 </enumeratedValue> 951 </enumeratedValues> 952 </field> 953 <field> 954 <name>TX_EMPTY</name> 955 <description>Wake on TX FIFO Empty.</description> 956 <bitOffset>1</bitOffset> 957 <bitWidth>1</bitWidth> 958 <enumeratedValues> 959 <enumeratedValue> 960 <name>clear</name> 961 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 962 <value>1</value> 963 </enumeratedValue> 964 </enumeratedValues> 965 </field> 966 <field> 967 <name>RX_THRESH</name> 968 <description>Wake on RX FIFO Threshold Crossed.</description> 969 <bitOffset>2</bitOffset> 970 <bitWidth>1</bitWidth> 971 <enumeratedValues> 972 <enumeratedValue> 973 <name>clear</name> 974 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 975 <value>1</value> 976 </enumeratedValue> 977 </enumeratedValues> 978 </field> 979 <field> 980 <name>RX_FULL</name> 981 <description>Wake on RX FIFO Full.</description> 982 <bitOffset>3</bitOffset> 983 <bitWidth>1</bitWidth> 984 <enumeratedValues> 985 <enumeratedValue> 986 <name>clear</name> 987 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 988 <value>1</value> 989 </enumeratedValue> 990 </enumeratedValues> 991 </field> 992 </fields> 993 </register> 994 <register> 995 <name>WAKE_EN</name> 996 <description>Register for wake up enable.</description> 997 <addressOffset>0x2C</addressOffset> 998 <access>read-write</access> 999 <fields> 1000 <field> 1001 <name>TX_THRESH</name> 1002 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1003 <bitOffset>0</bitOffset> 1004 <bitWidth>1</bitWidth> 1005 <enumeratedValues> 1006 <enumeratedValue> 1007 <name>dis</name> 1008 <description>Wakeup source disabled.</description> 1009 <value>0</value> 1010 </enumeratedValue> 1011 <enumeratedValue> 1012 <name>en</name> 1013 <description>Wakeup source enabled.</description> 1014 <value>1</value> 1015 </enumeratedValue> 1016 </enumeratedValues> 1017 </field> 1018 <field> 1019 <name>TX_EMPTY</name> 1020 <description>Wake on TX FIFO Empty Enable.</description> 1021 <bitOffset>1</bitOffset> 1022 <bitWidth>1</bitWidth> 1023 <enumeratedValues> 1024 <enumeratedValue> 1025 <name>dis</name> 1026 <description>Wakeup source disabled.</description> 1027 <value>0</value> 1028 </enumeratedValue> 1029 <enumeratedValue> 1030 <name>en</name> 1031 <description>Wakeup source enabled.</description> 1032 <value>1</value> 1033 </enumeratedValue> 1034 </enumeratedValues> 1035 </field> 1036 <field> 1037 <name>RX_THRESH</name> 1038 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1039 <bitOffset>2</bitOffset> 1040 <bitWidth>1</bitWidth> 1041 <enumeratedValues> 1042 <enumeratedValue> 1043 <name>dis</name> 1044 <description>Wakeup source disabled.</description> 1045 <value>0</value> 1046 </enumeratedValue> 1047 <enumeratedValue> 1048 <name>en</name> 1049 <description>Wakeup source enabled.</description> 1050 <value>1</value> 1051 </enumeratedValue> 1052 </enumeratedValues> 1053 </field> 1054 <field> 1055 <name>RX_FULL</name> 1056 <description>Wake on RX FIFO Full Enable.</description> 1057 <bitOffset>3</bitOffset> 1058 <bitWidth>1</bitWidth> 1059 <enumeratedValues> 1060 <enumeratedValue> 1061 <name>dis</name> 1062 <description>Wakeup source disabled.</description> 1063 <value>0</value> 1064 </enumeratedValue> 1065 <enumeratedValue> 1066 <name>en</name> 1067 <description>Wakeup source enabled.</description> 1068 <value>1</value> 1069 </enumeratedValue> 1070 </enumeratedValues> 1071 </field> 1072 </fields> 1073 </register> 1074 <register> 1075 <name>STAT</name> 1076 <description>SPI Status register.</description> 1077 <addressOffset>0x30</addressOffset> 1078 <access>read-only</access> 1079 <fields> 1080 <field> 1081 <name>BUSY</name> 1082 <description>SPI active status. In Master mode, set when transaction starts, 1083 cleared when last bit of last character is acted upon and Slave Select 1084 de-assertion would occur. In Slave mode, set when Slave Select is 1085 asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 1086 </description> 1087 <bitOffset>0</bitOffset> 1088 <bitWidth>1</bitWidth> 1089 <enumeratedValues> 1090 <enumeratedValue> 1091 <name>not</name> 1092 <description>SPI not active.</description> 1093 <value>0</value> 1094 </enumeratedValue> 1095 <enumeratedValue> 1096 <name>active</name> 1097 <description>SPI active.</description> 1098 <value>1</value> 1099 </enumeratedValue> 1100 </enumeratedValues> 1101 </field> 1102 </fields> 1103 </register> 1104 <register> 1105 <name>XMEM_CTRL</name> 1106 <description>Register to control external memory.</description> 1107 <addressOffset>0x34</addressOffset> 1108 <access>read-write</access> 1109 <fields> 1110 <field> 1111 <name>RD_CMD</name> 1112 <description>Read command.</description> 1113 <bitOffset>0</bitOffset> 1114 <bitWidth>8</bitWidth> 1115 </field> 1116 <field> 1117 <name>WR_CMD</name> 1118 <description>Write command.</description> 1119 <bitOffset>8</bitOffset> 1120 <bitWidth>8</bitWidth> 1121 </field> 1122 <field> 1123 <name>DUMMY_CLK</name> 1124 <description>Dummy clocks.</description> 1125 <bitOffset>16</bitOffset> 1126 <bitWidth>8</bitWidth> 1127 </field> 1128 <field> 1129 <name>XMEM_EN</name> 1130 <description>XMEM enable.</description> 1131 <bitOffset>31</bitOffset> 1132 <bitWidth>1</bitWidth> 1133 </field> 1134 </fields> 1135 </register> 1136 </registers> 1137 </peripheral> 1138<!-- SPIXR for Data XIP interface --> 1139</device> 1140
