1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXFM</name> 5 <description>SPIXF Master</description> 6 <baseAddress>0x40026000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>CTRL</name> 15 <description>SPIX Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>MODE</name> 20 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>2</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>SCLK_HI_SAMPLE_RISING</name> 26 <description>Description not available.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>SCLK_LO_SAMPLE_FAILLING</name> 31 <description>Description not available.</description> 32 <value>3</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 <field> 37 <name>SSPOL</name> 38 <description>Slave Select Polarity.</description> 39 <bitOffset>2</bitOffset> 40 <bitWidth>1</bitWidth> 41 <enumeratedValues> 42 <enumeratedValue> 43 <name>ACTIVE_HIGH</name> 44 <description>Slave Select is Active High.</description> 45 <value>0</value> 46 </enumeratedValue> 47 <enumeratedValue> 48 <name>ACTIVE_LOW</name> 49 <description>Slave Select is Active Low.</description> 50 <value>1</value> 51 </enumeratedValue> 52 </enumeratedValues> 53 </field> 54 <field> 55 <name>SSEL</name> 56 <description>Slave Select. Only valid value is zero.</description> 57 <bitOffset>4</bitOffset> 58 <bitWidth>3</bitWidth> 59 </field> 60 <field> 61 <name>LOCLK</name> 62 <description>Number of system clocks that SCLK will be low when SCLK pulses are generated.</description> 63 <bitOffset>8</bitOffset> 64 <bitWidth>4</bitWidth> 65 </field> 66 <field> 67 <name>HICLK</name> 68 <description>Number of system clocks that SCLK will be high when SCLK pulses are generated.</description> 69 <bitOffset>12</bitOffset> 70 <bitWidth>4</bitWidth> 71 </field> 72 <field> 73 <name>SSACT</name> 74 <description>Slave Select Active Timing.</description> 75 <bitOffset>16</bitOffset> 76 <bitWidth>2</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>off</name> 80 <description>0 system clocks.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>for_2_mod_clk</name> 85 <description>2 System clocks.</description> 86 <value>1</value> 87 </enumeratedValue> 88 <enumeratedValue> 89 <name>for_4_mod_clk</name> 90 <description>4 System clocks.</description> 91 <value>2</value> 92 </enumeratedValue> 93 <enumeratedValue> 94 <name>for_8_mod_clk</name> 95 <description>8 System clocks.</description> 96 <value>3</value> 97 </enumeratedValue> 98 </enumeratedValues> 99 </field> 100 <field> 101 <name>SSINACT</name> 102 <description>Slave Select Inactive Timing.</description> 103 <bitOffset>18</bitOffset> 104 <bitWidth>2</bitWidth> 105 <enumeratedValues> 106 <enumeratedValue> 107 <name>for_1_mod_clk</name> 108 <description>1 system clocks.</description> 109 <value>0</value> 110 </enumeratedValue> 111 <enumeratedValue> 112 <name>for_3_mod_clk</name> 113 <description>3 System clocks.</description> 114 <value>1</value> 115 </enumeratedValue> 116 <enumeratedValue> 117 <name>for_5_mod_clk</name> 118 <description>5 System clocks.</description> 119 <value>2</value> 120 </enumeratedValue> 121 <enumeratedValue> 122 <name>for_9_mod_clk</name> 123 <description>9 System clocks.</description> 124 <value>3</value> 125 </enumeratedValue> 126 </enumeratedValues> 127 </field> 128 </fields> 129 </register> 130 <register> 131 <name>FETCHCTRL</name> 132 <description>SPIX Fetch Control Register.</description> 133 <addressOffset>0x04</addressOffset> 134 <fields> 135 <field> 136 <name>CMD_VAL</name> 137 <description>Command Value sent to target to initiate fetching from SPI flash.</description> 138 <bitOffset>0</bitOffset> 139 <bitWidth>8</bitWidth> 140 </field> 141 <field> 142 <name>CMD_WDTH</name> 143 <description>Command Width. Number of data I/O used to send commands.</description> 144 <bitOffset>8</bitOffset> 145 <bitWidth>2</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>Single</name> 149 <description>Single SDIO.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>Dual_IO</name> 154 <description>Dual SDIO.</description> 155 <value>1</value> 156 </enumeratedValue> 157 <enumeratedValue> 158 <name>Quad_IO</name> 159 <description>Quad SDIO.</description> 160 <value>2</value> 161 </enumeratedValue> 162 <enumeratedValue> 163 <name>Invalid</name> 164 <description>Invalid.</description> 165 <value>3</value> 166 </enumeratedValue> 167 </enumeratedValues> 168 </field> 169 <field> 170 <name>ADDR_WDTH</name> 171 <description>Address Width. Number of data I/O used to send address, and mode/dummy clocks.</description> 172 <bitOffset>10</bitOffset> 173 <bitWidth>2</bitWidth> 174 <enumeratedValues> 175 <enumeratedValue> 176 <name>Single</name> 177 <description>Single SDIO.</description> 178 <value>0</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>Dual_IO</name> 182 <description>Dual SDIO.</description> 183 <value>1</value> 184 </enumeratedValue> 185 <enumeratedValue> 186 <name>Quad_IO</name> 187 <description>Quad SDIO.</description> 188 <value>2</value> 189 </enumeratedValue> 190 <enumeratedValue> 191 <name>Invalid</name> 192 <description>Invalid.</description> 193 <value>3</value> 194 </enumeratedValue> 195 </enumeratedValues> 196 </field> 197 <field> 198 <name>DATA_WDTH</name> 199 <description>Data Width. Number of data I/O used to receive data.</description> 200 <bitOffset>12</bitOffset> 201 <bitWidth>2</bitWidth> 202 <enumeratedValues> 203 <enumeratedValue> 204 <name>Single</name> 205 <description>Single SDIO.</description> 206 <value>0</value> 207 </enumeratedValue> 208 <enumeratedValue> 209 <name>Dual_IO</name> 210 <description>Dual SDIO.</description> 211 <value>1</value> 212 </enumeratedValue> 213 <enumeratedValue> 214 <name>Quad_IO</name> 215 <description>Quad SDIO.</description> 216 <value>2</value> 217 </enumeratedValue> 218 <enumeratedValue> 219 <name>Invalid</name> 220 <description>Invalid.</description> 221 <value>3</value> 222 </enumeratedValue> 223 </enumeratedValues> 224 </field> 225 <field> 226 <name>4BADDR</name> 227 <description>Four Byte Address Mode. Enables 4-byte Flash Address Mode.</description> 228 <bitOffset>16</bitOffset> 229 <bitWidth>1</bitWidth> 230 <enumeratedValues> 231 <enumeratedValue> 232 <name>3</name> 233 <description>3 Byte Address Mode.</description> 234 <value>0</value> 235 </enumeratedValue> 236 <enumeratedValue> 237 <name>4</name> 238 <description>4 Byte Address Mode.</description> 239 <value>1</value> 240 </enumeratedValue> 241 </enumeratedValues> 242 </field> 243 </fields> 244 </register> 245 <register> 246 <name>MODECTRL</name> 247 <description>SPIX Mode Control Register.</description> 248 <addressOffset>0x08</addressOffset> 249 <fields> 250 <field> 251 <name>MDCLK</name> 252 <description>Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.</description> 253 <bitOffset>0</bitOffset> 254 <bitWidth>4</bitWidth> 255 </field> 256 <field> 257 <name>NOCMD</name> 258 <description>No Command Mode.</description> 259 <bitOffset>8</bitOffset> 260 <bitWidth>1</bitWidth> 261 <enumeratedValues> 262 <enumeratedValue> 263 <name>always</name> 264 <description>Send read command every time SPI transaction is initiated.</description> 265 <value>0</value> 266 </enumeratedValue> 267 <enumeratedValue> 268 <name>once</name> 269 <description>Send read command only once. NO read command in subsequent SPI transactions.</description> 270 <value>1</value> 271 </enumeratedValue> 272 </enumeratedValues> 273 </field> 274 <field> 275 <name>EXIT_NOCMD</name> 276 <description>Mode Send.</description> 277 <bitOffset>9</bitOffset> 278 <bitWidth>1</bitWidth> 279 </field> 280 </fields> 281 </register> 282 <register> 283 <name>MODEDATA</name> 284 <description>SPIX Mode Data Register.</description> 285 <addressOffset>0x0C</addressOffset> 286 <fields> 287 <field> 288 <name>DATA</name> 289 <description>Mode Data. Specifies the data to send with the Dummy/Mode clocks.</description> 290 <bitOffset>0</bitOffset> 291 <bitWidth>16</bitWidth> 292 </field> 293 <field> 294 <name>OUT_EN</name> 295 <description>Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA.</description> 296 <bitOffset>16</bitOffset> 297 <bitWidth>16</bitWidth> 298 </field> 299 </fields> 300 </register> 301 <register> 302 <name>FBCTRL</name> 303 <description>SPIX Feedback Control Register.</description> 304 <addressOffset>0x10</addressOffset> 305 <fields> 306 <field> 307 <name>EN</name> 308 <description>Enable SCLK feedback mode.</description> 309 <bitOffset>0</bitOffset> 310 <bitWidth>1</bitWidth> 311 <enumeratedValues> 312 <enumeratedValue> 313 <name>dis</name> 314 <description>Disable SCLK feedback mode.</description> 315 <value>0</value> 316 </enumeratedValue> 317 <enumeratedValue> 318 <name>en</name> 319 <description>Enable SCLK feedback mode.</description> 320 <value>1</value> 321 </enumeratedValue> 322 </enumeratedValues> 323 </field> 324 <field> 325 <name>INVERT</name> 326 <description>Invert SCLK in feedback mode.</description> 327 <bitOffset>1</bitOffset> 328 <bitWidth>1</bitWidth> 329 <enumeratedValues> 330 <enumeratedValue> 331 <name>dis</name> 332 <description>Disable Invert SCLK feedback mode.</description> 333 <value>0</value> 334 </enumeratedValue> 335 <enumeratedValue> 336 <name>en</name> 337 <description>Enable Invert SCLK feedback mode.</description> 338 <value>1</value> 339 </enumeratedValue> 340 </enumeratedValues> 341 </field> 342 </fields> 343 </register> 344 <register> 345 <name>IOCTRL</name> 346 <description>SPIX IO Control Register.</description> 347 <addressOffset>0x1C</addressOffset> 348 <fields> 349 <field> 350 <name>SCLK_DS</name> 351 <description>SCLK drive Strength. This bit controls the drive strength on the SCLK pin.</description> 352 <bitOffset>0</bitOffset> 353 <bitWidth>1</bitWidth> 354 <enumeratedValues> 355 <enumeratedValue> 356 <name>Low</name> 357 <description>Low drive strength.</description> 358 <value>0</value> 359 </enumeratedValue> 360 <enumeratedValue> 361 <name>High</name> 362 <description>High drive strength.</description> 363 <value>1</value> 364 </enumeratedValue> 365 </enumeratedValues> 366 </field> 367 <field> 368 <name>SS_DS</name> 369 <description>Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin.</description> 370 <bitOffset>1</bitOffset> 371 <bitWidth>1</bitWidth> 372 <enumeratedValues> 373 <enumeratedValue> 374 <name>Low</name> 375 <description>Low drive strength.</description> 376 <value>0</value> 377 </enumeratedValue> 378 <enumeratedValue> 379 <name>High</name> 380 <description>High drive strength.</description> 381 <value>1</value> 382 </enumeratedValue> 383 </enumeratedValues> 384 </field> 385 <field> 386 <name>SDIO_DS</name> 387 <description>SDIO Drive Strength. This bit controls the drive strength of all SDIO pins.</description> 388 <bitOffset>2</bitOffset> 389 <bitWidth>1</bitWidth> 390 <enumeratedValues> 391 <enumeratedValue> 392 <name>Low</name> 393 <description>Low drive strength.</description> 394 <value>0</value> 395 </enumeratedValue> 396 <enumeratedValue> 397 <name>High</name> 398 <description>High drive strength.</description> 399 <value>1</value> 400 </enumeratedValue> 401 </enumeratedValues> 402 </field> 403 <field> 404 <name>PADCTRL</name> 405 <description>IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins.</description> 406 <bitOffset>3</bitOffset> 407 <bitWidth>2</bitWidth> 408 <enumeratedValues> 409 <enumeratedValue> 410 <name>tri_state</name> 411 <description>Tristate.</description> 412 <value>0</value> 413 </enumeratedValue> 414 <enumeratedValue> 415 <name>Pull_Up</name> 416 <description>Pull-Up.</description> 417 <value>1</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>Pull_down</name> 421 <description>Pull-Down.</description> 422 <value>2</value> 423 </enumeratedValue> 424 </enumeratedValues> 425 </field> 426 </fields> 427 </register> 428 <register> 429 <name>MEMSECCTRL</name> 430 <description>SPIX Memory Security Control Register.</description> 431 <addressOffset>0x20</addressOffset> 432 <fields> 433 <field> 434 <name>DEC_EN</name> 435 <description>Decryption Enable.</description> 436 <bitOffset>0</bitOffset> 437 <bitWidth>1</bitWidth> 438 <enumeratedValues> 439 <enumeratedValue> 440 <name>dis</name> 441 <description>Disable decryption of SPIX data.</description> 442 <value>0</value> 443 </enumeratedValue> 444 <enumeratedValue> 445 <name>en</name> 446 <description>Enable decryption of SPIX data.</description> 447 <value>1</value> 448 </enumeratedValue> 449 </enumeratedValues> 450 </field> 451 <field> 452 <name>AUTH_DIS</name> 453 <description>Integrity Enable.</description> 454 <bitOffset>1</bitOffset> 455 <bitWidth>1</bitWidth> 456 <enumeratedValues> 457 <enumeratedValue> 458 <name>en</name> 459 <description>Integrity checking enabled.</description> 460 <value>0</value> 461 </enumeratedValue> 462 <enumeratedValue> 463 <name>dis</name> 464 <description>Integrity checking disabled.</description> 465 <value>1</value> 466 </enumeratedValue> 467 </enumeratedValues> 468 </field> 469 <field> 470 <name>CNTOPT_EN</name> 471 <description>Enable counters optimization (when authentication is enabled).</description> 472 <bitOffset>2</bitOffset> 473 <bitWidth>1</bitWidth> 474 <enumeratedValues> 475 <enumeratedValue> 476 <name>dis</name> 477 <description>Disable counter optimization.</description> 478 <value>0</value> 479 </enumeratedValue> 480 <enumeratedValue> 481 <name>en</name> 482 <description>Enable counter optimization.</description> 483 <value>1</value> 484 </enumeratedValue> 485 </enumeratedValues> 486 </field> 487 <field> 488 <name>INTERL_DIS</name> 489 <description>Disable authenticity interleaving (when authentication is enabled)</description> 490 <bitOffset>3</bitOffset> 491 <bitWidth>1</bitWidth> 492 <enumeratedValues> 493 <enumeratedValue> 494 <name>dis</name> 495 <description>Disable interleaving of SPIX data.</description> 496 <value>1</value> 497 </enumeratedValue> 498 <enumeratedValue> 499 <name>en</name> 500 <description>Enable interleaving of SPIX data.</description> 501 <value>0</value> 502 </enumeratedValue> 503 </enumeratedValues> 504 </field> 505 <field> 506 <name>AUTHERR_FL</name> 507 <description>Authentication Error Flag Bit.</description> 508 <bitOffset>4</bitOffset> 509 <bitWidth>1</bitWidth> 510 </field> 511 </fields> 512 </register> 513 <register> 514 <name>BUSIDLE</name> 515 <description>Bus Idle</description> 516 <addressOffset>0x24</addressOffset> 517 <fields> 518 <field> 519 <name>BUSIDLE</name> 520 <description>A 16-bit timer will be triggered for each external access. The timer will be 521 restarted if another access is performed before the timer expires. When the 522 timer expires, slave select will be deactivated.</description> 523 <bitOffset>0</bitOffset> 524 <bitWidth>16</bitWidth> 525 </field> 526 </fields> 527 </register> 528 <register> 529 <name>AUTHOFFSET</name> 530 <description>Auth Offset</description> 531 <addressOffset>0x28</addressOffset> 532 </register> 533 <register> 534 <name>BYPASS_MODE</name> 535 <description>Bypass Mode Register.</description> 536 <addressOffset>0x2C</addressOffset> 537 <fields> 538 <field> 539 <name>EN</name> 540 <description>Enable bypass.</description> 541 <bitOffset>0</bitOffset> 542 <bitWidth>1</bitWidth> 543 </field> 544 <field> 545 <name>FCLK_DELAY</name> 546 <description>FCLK Delay.</description> 547 <bitOffset>1</bitOffset> 548 <bitWidth>3</bitWidth> 549 <enumeratedValues> 550 <enumeratedValue> 551 <name>0_NS</name> 552 <description>0ns</description> 553 <value>0</value> 554 </enumeratedValue> 555 <enumeratedValue> 556 <name>0P5_NS</name> 557 <description>0.5ns</description> 558 <value>1</value> 559 </enumeratedValue> 560 <enumeratedValue> 561 <name>1P0_NS</name> 562 <description>1.0ns</description> 563 <value>2</value> 564 </enumeratedValue> 565 <enumeratedValue> 566 <name>1P5_NS</name> 567 <description>1.5ns</description> 568 <value>3</value> 569 </enumeratedValue> 570 <enumeratedValue> 571 <name>2P0_NS</name> 572 <description>2.0ns</description> 573 <value>4</value> 574 </enumeratedValue> 575 <enumeratedValue> 576 <name>2P5_NS</name> 577 <description>2.5ns</description> 578 <value>5</value> 579 </enumeratedValue> 580 <enumeratedValue> 581 <name>3P0_NS</name> 582 <description>3.0ns</description> 583 <value>6</value> 584 </enumeratedValue> 585 <enumeratedValue> 586 <name>3P5_NS</name> 587 <description>3.0ns</description> 588 <value>7</value> 589 </enumeratedValue> 590 </enumeratedValues> 591 </field> 592 <field> 593 <name>SCLK_DELAY</name> 594 <description>SCLK Delay.</description> 595 <bitOffset>4</bitOffset> 596 <bitWidth>3</bitWidth> 597 <enumeratedValues> 598 <enumeratedValue> 599 <name>0_NS</name> 600 <description>0ns</description> 601 <value>0</value> 602 </enumeratedValue> 603 <enumeratedValue> 604 <name>0P5_NS</name> 605 <description>0.5ns</description> 606 <value>1</value> 607 </enumeratedValue> 608 <enumeratedValue> 609 <name>1P0_NS</name> 610 <description>1.0ns</description> 611 <value>2</value> 612 </enumeratedValue> 613 <enumeratedValue> 614 <name>1P5_NS</name> 615 <description>1.5ns</description> 616 <value>3</value> 617 </enumeratedValue> 618 <enumeratedValue> 619 <name>2P0_NS</name> 620 <description>2.0ns</description> 621 <value>4</value> 622 </enumeratedValue> 623 <enumeratedValue> 624 <name>2P5_NS</name> 625 <description>2.5ns</description> 626 <value>5</value> 627 </enumeratedValue> 628 <enumeratedValue> 629 <name>3P0_NS</name> 630 <description>3.0ns</description> 631 <value>6</value> 632 </enumeratedValue> 633 <enumeratedValue> 634 <name>3P5_NS</name> 635 <description>3.0ns</description> 636 <value>7</value> 637 </enumeratedValue> 638 </enumeratedValues> 639 </field> 640 </fields> 641 </register> 642 </registers> 643 </peripheral> 644 <!-- SPIXFM: 645 SPI XiP Master --> 646</device>
