1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXFC</name> 5 <description>SPI XiP Flash Configuration Controller</description> 6 <baseAddress>0x40027000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPIXFC</name> 14 <description>SPIXFC IRQ</description> 15 <value>38</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CFG</name> 20 <description>Configuration Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <fields> 23 <field> 24 <name>SSEL</name> 25 <description>Slaves Select.</description> 26 <bitOffset>0</bitOffset> 27 <bitWidth>3</bitWidth> 28 <enumeratedValues> 29 <enumeratedValue> 30 <name>Slave_0</name> 31 <description>Slave 0 is selected.</description> 32 <value>0</value> 33 </enumeratedValue> 34 <enumeratedValue> 35 <name>Slave_1</name> 36 <description>Slave 1 is selected.</description> 37 <value>1</value> 38 </enumeratedValue> 39 </enumeratedValues> 40 </field> 41 <field> 42 <name>MODE</name> 43 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 44 <bitOffset>4</bitOffset> 45 <bitWidth>2</bitWidth> 46 <enumeratedValues> 47 <enumeratedValue> 48 <name>SPIX_Mode_0</name> 49 <description>SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0.</description> 50 <value>0</value> 51 </enumeratedValue> 52 <enumeratedValue> 53 <name>SPIX_Mode_3</name> 54 <description>SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1.</description> 55 <value>3</value> 56 </enumeratedValue> 57 </enumeratedValues> 58 </field> 59 <field> 60 <name>PAGE_SIZE</name> 61 <description>Page Size.</description> 62 <bitOffset>6</bitOffset> 63 <bitWidth>2</bitWidth> 64 <enumeratedValues> 65 <enumeratedValue> 66 <name>4_bytes</name> 67 <description>4 bytes.</description> 68 <value>0</value> 69 </enumeratedValue> 70 <enumeratedValue> 71 <name>8_bytes</name> 72 <description>8 bytes.</description> 73 <value>1</value> 74 </enumeratedValue> 75 <enumeratedValue> 76 <name>16_bytes</name> 77 <description>16 bytes.</description> 78 <value>2</value> 79 </enumeratedValue> 80 <enumeratedValue> 81 <name>32_bytes</name> 82 <description>32 bytes.</description> 83 <value>3</value> 84 </enumeratedValue> 85 </enumeratedValues> 86 </field> 87 <field> 88 <name>HI_CLK</name> 89 <description>SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high.</description> 90 <bitOffset>8</bitOffset> 91 <bitWidth>4</bitWidth> 92 <enumeratedValues> 93 <enumeratedValue> 94 <name>16_SCLK</name> 95 <description>16 system clocks.</description> 96 <value>0</value> 97 </enumeratedValue> 98 </enumeratedValues> 99 </field> 100 <field> 101 <name>LO_CLK</name> 102 <description>SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low.</description> 103 <bitOffset>12</bitOffset> 104 <bitWidth>4</bitWidth> 105 <enumeratedValues> 106 <enumeratedValue> 107 <name>16_SCLK</name> 108 <description>16 system clocks.</description> 109 <value>0</value> 110 </enumeratedValue> 111 </enumeratedValues> 112 </field> 113 <field> 114 <name>SSACT</name> 115 <description>Slaves Select Activate Timing.</description> 116 <bitOffset>16</bitOffset> 117 <bitWidth>2</bitWidth> 118 <enumeratedValues> 119 <enumeratedValue> 120 <name>0_CLKS</name> 121 <description>0 sytem clocks.</description> 122 <value>0</value> 123 </enumeratedValue> 124 <enumeratedValue> 125 <name>2_CLKS</name> 126 <description>2 sytem clocks.</description> 127 <value>1</value> 128 </enumeratedValue> 129 <enumeratedValue> 130 <name>4_CLKS</name> 131 <description>4 sytem clocks.</description> 132 <value>2</value> 133 </enumeratedValue> 134 <enumeratedValue> 135 <name>8_CLKS</name> 136 <description>8 sytem clocks.</description> 137 <value>3</value> 138 </enumeratedValue> 139 </enumeratedValues> 140 </field> 141 <field> 142 <name>SSIACT</name> 143 <description>Slaves Select Inactive Timing.</description> 144 <bitOffset>18</bitOffset> 145 <bitWidth>2</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>4_CLKS</name> 149 <description>4 sytem clocks.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>6_CLKS</name> 154 <description>6 sytem clocks.</description> 155 <value>1</value> 156 </enumeratedValue> 157 <enumeratedValue> 158 <name>8_CLKS</name> 159 <description>8 sytem clocks.</description> 160 <value>2</value> 161 </enumeratedValue> 162 <enumeratedValue> 163 <name>12_CLKS</name> 164 <description>12 sytem clocks.</description> 165 <value>3</value> 166 </enumeratedValue> 167 </enumeratedValues> 168 </field> 169 <field> 170 <name>IOSMPL</name> 171 <description>Sample Delay</description> 172 <bitOffset>20</bitOffset> 173 <bitWidth>4</bitWidth> 174 </field> 175 </fields> 176 </register> 177 <register> 178 <name>SS_POL</name> 179 <description>SPIX Controller Slave Select Polarity Register.</description> 180 <addressOffset>0x04</addressOffset> 181 <fields> 182 <field> 183 <name>SSPOL_0</name> 184 <description>Slave Select Polarity.</description> 185 <bitOffset>0</bitOffset> 186 <bitWidth>1</bitWidth> 187 <enumeratedValues> 188 <enumeratedValue> 189 <name>lo</name> 190 <description>Active Low.</description> 191 <value>0</value> 192 </enumeratedValue> 193 <enumeratedValue> 194 <name>hi</name> 195 <description>Active High.</description> 196 <value>1</value> 197 </enumeratedValue> 198 </enumeratedValues> 199 </field> 200 </fields> 201 </register> 202 <register> 203 <name>GEN_CTRL</name> 204 <description>SPIX Controller General Controller Register.</description> 205 <addressOffset>0x08</addressOffset> 206 <fields> 207 <field> 208 <name>ENABLE</name> 209 <description>SPI Master enable.</description> 210 <bitOffset>0</bitOffset> 211 <bitWidth>1</bitWidth> 212 <enumeratedValues> 213 <enumeratedValue> 214 <name>dis</name> 215 <description>Disable SPI Master, putting a reset state.</description> 216 <value>0</value> 217 </enumeratedValue> 218 <enumeratedValue> 219 <name>en</name> 220 <description>Enable SPI Master for processing transactions.</description> 221 <value>1</value> 222 </enumeratedValue> 223 </enumeratedValues> 224 </field> 225 <field> 226 <name>TX_FIFO_EN</name> 227 <description>Transaction FIFO Enable.</description> 228 <bitOffset>1</bitOffset> 229 <bitWidth>1</bitWidth> 230 <enumeratedValues> 231 <enumeratedValue> 232 <name>dis_txfifo</name> 233 <description>Disable Transaction FIFO.</description> 234 <value>0</value> 235 </enumeratedValue> 236 <enumeratedValue> 237 <name>en_txfifo</name> 238 <description>Enable Transaction FIFO.</description> 239 <value>1</value> 240 </enumeratedValue> 241 </enumeratedValues> 242 </field> 243 <field> 244 <name>RX_FIFO_EN</name> 245 <description>Result FIFO Enable.</description> 246 <bitOffset>2</bitOffset> 247 <bitWidth>1</bitWidth> 248 <enumeratedValues> 249 <enumeratedValue> 250 <name>dis_rxfifo</name> 251 <description>Disable Result FIFO.</description> 252 <value>0</value> 253 </enumeratedValue> 254 <enumeratedValue> 255 <name>en_rxfifo</name> 256 <description>Enable Result FIFO.</description> 257 <value>1</value> 258 </enumeratedValue> 259 </enumeratedValues> 260 </field> 261 <field> 262 <name>BBMODE</name> 263 <description>Bit-Bang Mode.</description> 264 <bitOffset>3</bitOffset> 265 <bitWidth>1</bitWidth> 266 <enumeratedValues> 267 <enumeratedValue> 268 <name>dis</name> 269 <description>Disable Bit-Bang Mode.</description> 270 <value>0</value> 271 </enumeratedValue> 272 <enumeratedValue> 273 <name>en</name> 274 <description>Enable Bit-Bang Mode.</description> 275 <value>1</value> 276 </enumeratedValue> 277 </enumeratedValues> 278 </field> 279 <field> 280 <name>SSDR</name> 281 <description>This bits reflects the state of the currently selected slave select.</description> 282 <bitOffset>4</bitOffset> 283 <bitWidth>1</bitWidth> 284 <enumeratedValues> 285 <enumeratedValue> 286 <name>output0</name> 287 <description>Selected Slave select output = 0.</description> 288 <value>0</value> 289 </enumeratedValue> 290 <enumeratedValue> 291 <name>output1</name> 292 <description>Selected Slave select output = 1.</description> 293 <value>1</value> 294 </enumeratedValue> 295 </enumeratedValues> 296 </field> 297 <field> 298 <name>SCLK_DR</name> 299 <description>SSCLK Drive and State.</description> 300 <bitOffset>6</bitOffset> 301 <bitWidth>1</bitWidth> 302 <enumeratedValues> 303 <enumeratedValue> 304 <name>SCLK_0</name> 305 <description>SCLK is 0.</description> 306 <value>0</value> 307 </enumeratedValue> 308 <enumeratedValue> 309 <name>SCLK_1</name> 310 <description>SCLK is 1.</description> 311 <value>1</value> 312 </enumeratedValue> 313 </enumeratedValues> 314 </field> 315 <field> 316 <name>SDIO_DATA_IN</name> 317 <description>SDIO Input Data Value.</description> 318 <bitOffset>8</bitOffset> 319 <bitWidth>4</bitWidth> 320 <enumeratedValues> 321 <enumeratedValue> 322 <name>SDIO0</name> 323 <description>SDIO[0]</description> 324 <value>0</value> 325 </enumeratedValue> 326 <enumeratedValue> 327 <name>SDIO1</name> 328 <description>SDIO[1]</description> 329 <value>1</value> 330 </enumeratedValue> 331 <enumeratedValue> 332 <name>SDIO2</name> 333 <description>SDIO[2]</description> 334 <value>2</value> 335 </enumeratedValue> 336 <enumeratedValue> 337 <name>SDIO3</name> 338 <description>SDIO[3]</description> 339 <value>3</value> 340 </enumeratedValue> 341 </enumeratedValues> 342 </field> 343 <field> 344 <name>BB_DATA</name> 345 <description>No description available.</description> 346 <bitOffset>12</bitOffset> 347 <bitWidth>4</bitWidth> 348 <enumeratedValues> 349 <enumeratedValue> 350 <name>SDIO0</name> 351 <description>SDIO[0]</description> 352 <value>0</value> 353 </enumeratedValue> 354 <enumeratedValue> 355 <name>SDIO1</name> 356 <description>SDIO[1]</description> 357 <value>1</value> 358 </enumeratedValue> 359 <enumeratedValue> 360 <name>SDIO2</name> 361 <description>SDIO[2]</description> 362 <value>2</value> 363 </enumeratedValue> 364 <enumeratedValue> 365 <name>SDIO3</name> 366 <description>SDIO[3]</description> 367 <value>3</value> 368 </enumeratedValue> 369 </enumeratedValues> 370 </field> 371 <field> 372 <name>BB_DATA_OUT_EN</name> 373 <description>Bit Bang SDIO Output Enable.</description> 374 <bitOffset>16</bitOffset> 375 <bitWidth>4</bitWidth> 376 <enumeratedValues> 377 <enumeratedValue> 378 <name>SDIO0</name> 379 <description>SDIO[0]</description> 380 <value>0</value> 381 </enumeratedValue> 382 <enumeratedValue> 383 <name>SDIO1</name> 384 <description>SDIO[1]</description> 385 <value>1</value> 386 </enumeratedValue> 387 <enumeratedValue> 388 <name>SDIO2</name> 389 <description>SDIO[2]</description> 390 <value>2</value> 391 </enumeratedValue> 392 <enumeratedValue> 393 <name>SDIO3</name> 394 <description>SDIO[3]</description> 395 <value>3</value> 396 </enumeratedValue> 397 </enumeratedValues> 398 </field> 399 <field> 400 <name>SIMPLE</name> 401 <description>Simple Mode Enable.</description> 402 <bitOffset>20</bitOffset> 403 <bitWidth>1</bitWidth> 404 </field> 405 <field> 406 <name>SIMPLE_RX</name> 407 <description>Simple Receive Enable.</description> 408 <bitOffset>21</bitOffset> 409 <bitWidth>1</bitWidth> 410 </field> 411 <field> 412 <name>SIMPLE_SS</name> 413 <description>Simple Mode Slave Select.</description> 414 <bitOffset>22</bitOffset> 415 <bitWidth>1</bitWidth> 416 </field> 417 <field> 418 <name>SCLK_FB</name> 419 <description>Enable SCLK Feedback Mode.</description> 420 <bitOffset>24</bitOffset> 421 <bitWidth>1</bitWidth> 422 <enumeratedValues> 423 <enumeratedValue> 424 <name>dis</name> 425 <value>0</value> 426 </enumeratedValue> 427 <enumeratedValue> 428 <name>en</name> 429 <value>1</value> 430 </enumeratedValue> 431 </enumeratedValues> 432 </field> 433 <field> 434 <name>SCLK_FB_INVERT</name> 435 <description>SCK Invert.</description> 436 <bitOffset>25</bitOffset> 437 <bitWidth>1</bitWidth> 438 </field> 439 </fields> 440 </register> 441 <register> 442 <name>FIFO_CTRL</name> 443 <description>SPIX Controller FIFO Control and Status Register.</description> 444 <addressOffset>0x0C</addressOffset> 445 <fields> 446 <field> 447 <name>TX_FIFO_AE_LVL</name> 448 <description>Transaction FIFO Almost Empty Level.</description> 449 <bitOffset>0</bitOffset> 450 <bitWidth>4</bitWidth> 451 </field> 452 <field> 453 <name>TX_FIFO_CNT</name> 454 <description>Transaction FIFO Used.</description> 455 <bitOffset>8</bitOffset> 456 <bitWidth>5</bitWidth> 457 </field> 458 <field> 459 <name>RX_FIFO_AF_LVL</name> 460 <description>Results FIFO Almost Full Level.</description> 461 <bitOffset>16</bitOffset> 462 <bitWidth>5</bitWidth> 463 </field> 464 <field> 465 <name>RX_FIFO_CNT</name> 466 <description>Result FIFO Used.</description> 467 <bitOffset>24</bitOffset> 468 <bitWidth>6</bitWidth> 469 </field> 470 </fields> 471 </register> 472 <register> 473 <name>SP_CTRL</name> 474 <description>SPIX Controller Special Control Register.</description> 475 <addressOffset>0x10</addressOffset> 476 <fields> 477 <field> 478 <name>SAMPL</name> 479 <description>Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must 480 only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the 481 next slave select assertion.</description> 482 <bitOffset>0</bitOffset> 483 <bitWidth>1</bitWidth> 484 </field> 485 <field> 486 <name>SDIO_OUT</name> 487 <description>SDIO Output Value Sample Mode</description> 488 <bitOffset>4</bitOffset> 489 <bitWidth>4</bitWidth> 490 </field> 491 <field> 492 <name>SDIO_OUT_EN</name> 493 <description>SDIO Output Enable Sample Mode</description> 494 <bitOffset>8</bitOffset> 495 <bitWidth>4</bitWidth> 496 </field> 497 <field> 498 <name>SCLKINH3</name> 499 <description>SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams.</description> 500 <bitOffset>16</bitOffset> 501 <bitWidth>1</bitWidth> 502 <enumeratedValues> 503 <enumeratedValue> 504 <name>EN</name> 505 <description>Allow trailing SCLK low pulse prior to Slave Select de-assertion.</description> 506 <value>0</value> 507 </enumeratedValue> 508 <enumeratedValue> 509 <name>DIS</name> 510 <description>Inhibit trailing SCLK low pulse prior to Slave Select de-assertion.</description> 511 <value>1</value> 512 </enumeratedValue> 513 </enumeratedValues> 514 </field> 515 </fields> 516 </register> 517 <register> 518 <name>INT_FL</name> 519 <description>SPIX Controller Interrupt Status Register.</description> 520 <addressOffset>0x14</addressOffset> 521 <fields> 522 <field> 523 <name>TX_STALLED</name> 524 <description>Transaction Stalled Interrupt Flag.</description> 525 <bitOffset>0</bitOffset> 526 <bitWidth>1</bitWidth> 527 <enumeratedValues> 528 <enumeratedValue> 529 <name>CLR</name> 530 <description>Normal FIFO Transaction.</description> 531 <value>0</value> 532 </enumeratedValue> 533 <enumeratedValue> 534 <name>SET</name> 535 <description>Stalled FIFO Transaction.</description> 536 <value>1</value> 537 </enumeratedValue> 538 </enumeratedValues> 539 </field> 540 <field> 541 <name>RX_STALLED</name> 542 <description>Results Stalled Interrupt Flag.</description> 543 <bitOffset>1</bitOffset> 544 <bitWidth>1</bitWidth> 545 <enumeratedValues> 546 <enumeratedValue> 547 <name>CLR</name> 548 <description>Normal FIFO Operation.</description> 549 <value>0</value> 550 </enumeratedValue> 551 <enumeratedValue> 552 <name>SET</name> 553 <description>Stalled FIFO.</description> 554 <value>1</value> 555 </enumeratedValue> 556 </enumeratedValues> 557 </field> 558 <field> 559 <name>TX_READY</name> 560 <description>Transaction Ready Interrupt Status.</description> 561 <bitOffset>2</bitOffset> 562 <bitWidth>1</bitWidth> 563 <enumeratedValues> 564 <enumeratedValue> 565 <name>CLR</name> 566 <description>FIFO Transaction not ready.</description> 567 <value>0</value> 568 </enumeratedValue> 569 <enumeratedValue> 570 <name>SET</name> 571 <description>FIFO Transaction ready.</description> 572 <value>1</value> 573 </enumeratedValue> 574 </enumeratedValues> 575 </field> 576 <field> 577 <name>RX_DONE</name> 578 <description>Results Done Interrupt Status.</description> 579 <bitOffset>3</bitOffset> 580 <bitWidth>1</bitWidth> 581 <enumeratedValues> 582 <enumeratedValue> 583 <name>CLR</name> 584 <description>Results FIFO ready.</description> 585 <value>0</value> 586 </enumeratedValue> 587 <enumeratedValue> 588 <name>SET</name> 589 <description>Results FIFO Not ready.</description> 590 <value>1</value> 591 </enumeratedValue> 592 </enumeratedValues> 593 </field> 594 <field> 595 <name>TX_FIFO_AE</name> 596 <description>Transaction FIFO Almost Empty Flag.</description> 597 <bitOffset>4</bitOffset> 598 <bitWidth>1</bitWidth> 599 <enumeratedValues> 600 <enumeratedValue> 601 <name>CLR</name> 602 <description>Transaction FIFO not Almost Empty.</description> 603 <value>0</value> 604 </enumeratedValue> 605 <enumeratedValue> 606 <name>SET</name> 607 <description>Transaction FIFO Almost Empty.</description> 608 <value>1</value> 609 </enumeratedValue> 610 </enumeratedValues> 611 </field> 612 <field> 613 <name>RX_FIFO_AF</name> 614 <description>Results FIFO Almost Full Flag.</description> 615 <bitOffset>5</bitOffset> 616 <bitWidth>1</bitWidth> 617 <enumeratedValues> 618 <enumeratedValue> 619 <name>CLR</name> 620 <description>Results FIFO level below the Almost Full level.</description> 621 <value>0</value> 622 </enumeratedValue> 623 <enumeratedValue> 624 <name>SET</name> 625 <description>Results FIFO level at Almost Full level.</description> 626 <value>1</value> 627 </enumeratedValue> 628 </enumeratedValues> 629 </field> 630 </fields> 631 </register> 632 <register> 633 <name>INT_EN</name> 634 <description>SPIX Controller Interrupt Enable Register.</description> 635 <addressOffset>0x18</addressOffset> 636 <fields> 637 <field> 638 <name>TX_STALLED</name> 639 <description>Transaction Stalled Interrupt Enable.</description> 640 <bitOffset>0</bitOffset> 641 <bitWidth>1</bitWidth> 642 <enumeratedValues> 643 <enumeratedValue> 644 <name>en</name> 645 <description>Disable Transaction Stalled Interrupt.</description> 646 <value>0</value> 647 </enumeratedValue> 648 <enumeratedValue> 649 <name>dis</name> 650 <description>Enable Transaction Stalled Interrupt.</description> 651 <value>1</value> 652 </enumeratedValue> 653 </enumeratedValues> 654 </field> 655 <field> 656 <name>RX_STALLED</name> 657 <description>Results Stalled Interrupt Enable.</description> 658 <bitOffset>1</bitOffset> 659 <bitWidth>1</bitWidth> 660 <enumeratedValues> 661 <enumeratedValue> 662 <name>en</name> 663 <description>Disable Results Stalled Interrupt.</description> 664 <value>0</value> 665 </enumeratedValue> 666 <enumeratedValue> 667 <name>dis</name> 668 <description>Enable Results Stalled Interrupt.</description> 669 <value>1</value> 670 </enumeratedValue> 671 </enumeratedValues> 672 </field> 673 <field> 674 <name>TX_READY</name> 675 <description>Transaction Ready Interrupt Enable.</description> 676 <bitOffset>2</bitOffset> 677 <bitWidth>1</bitWidth> 678 <enumeratedValues> 679 <enumeratedValue> 680 <name>en</name> 681 <description>Disable FIFO Transaction Ready Interrupt.</description> 682 <value>0</value> 683 </enumeratedValue> 684 <enumeratedValue> 685 <name>dis</name> 686 <description>Enable FIFO Transaction Ready Interrupt.</description> 687 <value>1</value> 688 </enumeratedValue> 689 </enumeratedValues> 690 </field> 691 <field> 692 <name>RX_DONE</name> 693 <description>Results Done Interrupt Enable.</description> 694 <bitOffset>3</bitOffset> 695 <bitWidth>1</bitWidth> 696 <enumeratedValues> 697 <enumeratedValue> 698 <name>en</name> 699 <description>Disable Results Done Interrupt.</description> 700 <value>0</value> 701 </enumeratedValue> 702 <enumeratedValue> 703 <name>dis</name> 704 <description>Enable Results Done Interrupt.</description> 705 <value>1</value> 706 </enumeratedValue> 707 </enumeratedValues> 708 </field> 709 <field> 710 <name>TX_FIFO_AE</name> 711 <description>Transaction FIFO Almost Empty Interrupt Enable.</description> 712 <bitOffset>4</bitOffset> 713 <bitWidth>1</bitWidth> 714 <enumeratedValues> 715 <enumeratedValue> 716 <name>en</name> 717 <description>Disable Transaction FIFO Almost Empty Interrupt.</description> 718 <value>0</value> 719 </enumeratedValue> 720 <enumeratedValue> 721 <name>dis</name> 722 <description>Enable Transaction FIFO Almost Empty Interrupt.</description> 723 <value>1</value> 724 </enumeratedValue> 725 </enumeratedValues> 726 </field> 727 <field> 728 <name>RX_FIFO_AF</name> 729 <description>Results FIFO Almost Full Interrupt Enable.</description> 730 <bitOffset>5</bitOffset> 731 <bitWidth>1</bitWidth> 732 <enumeratedValues> 733 <enumeratedValue> 734 <name>en</name> 735 <description>Disable Results FIFO Almost Full Interrupt.</description> 736 <value>0</value> 737 </enumeratedValue> 738 <enumeratedValue> 739 <name>dis</name> 740 <description>Enable Results FIFO Almost Full Interrupt.</description> 741 <value>1</value> 742 </enumeratedValue> 743 </enumeratedValues> 744 </field> 745 </fields> 746 </register> 747 </registers> 748 </peripheral> 749 <!-- SPIXFC: 750 SPI XiP Master controller --> 751</device>
