1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIMSS</name> 5 <description>Serial Peripheral Interface.</description> 6 <prependToName>SPIMSS</prependToName> 7 <baseAddress>0x40018000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <registers> 14 <register> 15 <name>DATA</name> 16 <description>SPI 16-bit Data Access</description> 17 <addressOffset>0x00</addressOffset> 18 <access>read-write</access> 19 <fields> 20 <field> 21 <name>DATA</name> 22 <description>SPI data.</description> 23 <bitOffset>0</bitOffset> 24 <bitWidth>16</bitWidth> 25 </field> 26 </fields> 27 </register> 28 <register> 29 <name>CTRL</name> 30 <description>SPI Control Register.</description> 31 <addressOffset>0x04</addressOffset> 32 <fields> 33 <field> 34 <name>START</name> 35 <description>SPI Enable.</description> 36 <bitOffset>0</bitOffset> 37 <bitWidth>1</bitWidth> 38 <enumeratedValues> 39 <enumeratedValue> 40 <name>stop</name> 41 <value>0</value> 42 </enumeratedValue> 43 <enumeratedValue> 44 <name>start</name> 45 <value>1</value> 46 </enumeratedValue> 47 </enumeratedValues> 48 </field> 49 <field> 50 <name>MMEN</name> 51 <description>SPI Master Mode Enable.</description> 52 <bitOffset>1</bitOffset> 53 <bitWidth>1</bitWidth> 54 <enumeratedValues> 55 <enumeratedValue> 56 <name>slave</name> 57 <value>0</value> 58 </enumeratedValue> 59 <enumeratedValue> 60 <name>master</name> 61 <value>1</value> 62 </enumeratedValue> 63 </enumeratedValues> 64 </field> 65 <field> 66 <name>OD_OUT_EN</name> 67 <description>Wired OR (open drain) Enable.</description> 68 <bitOffset>2</bitOffset> 69 <bitWidth>1</bitWidth> 70 <enumeratedValues> 71 <enumeratedValue> 72 <name>dis</name> 73 <value>0</value> 74 </enumeratedValue> 75 <enumeratedValue> 76 <name>en</name> 77 <value>1</value> 78 </enumeratedValue> 79 </enumeratedValues> 80 </field> 81 <field> 82 <name>CLKPOL</name> 83 <description>Clock Polarity.</description> 84 <bitOffset>3</bitOffset> 85 <bitWidth>1</bitWidth> 86 <enumeratedValues> 87 <enumeratedValue> 88 <name>idleLo</name> 89 <description>SCLK idles Low (0) after character transmission/reception.</description> 90 <value>0</value> 91 </enumeratedValue> 92 <enumeratedValue> 93 <name>idleHi</name> 94 <description>SCLK idles High (1) after character transmission/reception.</description> 95 <value>1</value> 96 </enumeratedValue> 97 </enumeratedValues> 98 </field> 99 <field> 100 <name>PHASE</name> 101 <description>Phase Select.</description> 102 <bitOffset>4</bitOffset> 103 <bitWidth>1</bitWidth> 104 <enumeratedValues> 105 <enumeratedValue> 106 <name>activeEdge</name> 107 <description>Transmit on active edge of SCLK.</description> 108 <value>0</value> 109 </enumeratedValue> 110 <enumeratedValue> 111 <name>inactiveEdge</name> 112 <description>Transmit on inactive edge of SCLK.</description> 113 <value>1</value> 114 </enumeratedValue> 115 </enumeratedValues> 116 </field> 117 <field> 118 <name>BIRQ</name> 119 <description>Baud Rate Generator Timer Interrupt Request.</description> 120 <bitOffset>5</bitOffset> 121 <bitWidth>1</bitWidth> 122 <enumeratedValues> 123 <enumeratedValue> 124 <name>dis</name> 125 <value>0</value> 126 </enumeratedValue> 127 <enumeratedValue> 128 <name>en</name> 129 <value>1</value> 130 </enumeratedValue> 131 </enumeratedValues> 132 </field> 133 <field> 134 <name>STR</name> 135 <description>Start SPI Interrupt.</description> 136 <bitOffset>6</bitOffset> 137 <bitWidth>1</bitWidth> 138 <enumeratedValues> 139 <enumeratedValue> 140 <name>complete</name> 141 <description>No operation/complete.</description> 142 <value>0</value> 143 </enumeratedValue> 144 <enumeratedValue> 145 <name>start</name> 146 <description>Start operation.</description> 147 <value>1</value> 148 </enumeratedValue> 149 </enumeratedValues> 150 </field> 151 <field> 152 <name>IRQE</name> 153 <description>Interrupt Request Enable.</description> 154 <bitOffset>7</bitOffset> 155 <bitWidth>1</bitWidth> 156 <enumeratedValues> 157 <enumeratedValue> 158 <name>dis</name> 159 <value>0</value> 160 </enumeratedValue> 161 <enumeratedValue> 162 <name>en</name> 163 <value>1</value> 164 </enumeratedValue> 165 </enumeratedValues> 166 </field> 167 </fields> 168 </register> 169 <register> 170 <name>INT_FL</name> 171 <description>SPI Interrupt Flag Register.</description> 172 <addressOffset>0x08</addressOffset> 173 <resetValue>0x00000001</resetValue> 174 <fields> 175 <field> 176 <name>SLAS</name> 177 <description>Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.</description> 178 <bitOffset>0</bitOffset> 179 <bitWidth>1</bitWidth> 180 <access>read-only</access> 181 <enumeratedValues> 182 <enumeratedValue> 183 <name>selected</name> 184 <value>0</value> 185 </enumeratedValue> 186 <enumeratedValue> 187 <name>notSelected</name> 188 <value>1</value> 189 </enumeratedValue> 190 </enumeratedValues> 191 </field> 192 <field> 193 <name>TXST</name> 194 <description>Transmit Status.</description> 195 <bitOffset>1</bitOffset> 196 <bitWidth>1</bitWidth> 197 <access>read-only</access> 198 <enumeratedValues> 199 <enumeratedValue> 200 <name>idle</name> 201 <value>0</value> 202 </enumeratedValue> 203 <enumeratedValue> 204 <name>busy</name> 205 <value>1</value> 206 </enumeratedValue> 207 </enumeratedValues> 208 </field> 209 <field> 210 <name>TUND</name> 211 <description>Transmit Underrun.</description> 212 <bitOffset>2</bitOffset> 213 <bitWidth>1</bitWidth> 214 <modifiedWriteValues>oneToClear</modifiedWriteValues> 215 <enumeratedValues> 216 <enumeratedValue> 217 <name>noEvent</name> 218 <description>The event has not occurred.</description> 219 <value>0</value> 220 </enumeratedValue> 221 <enumeratedValue> 222 <name>underrun</name> 223 <description>The event has occurred.</description> 224 <value>1</value> 225 </enumeratedValue> 226 </enumeratedValues> 227 </field> 228 <field> 229 <name>ROVR</name> 230 <description>Receive Overrun.</description> 231 <bitOffset>3</bitOffset> 232 <bitWidth>1</bitWidth> 233 <enumeratedValues> 234 <enumeratedValue> 235 <name>noEvent</name> 236 <description>The event has not occurred.</description> 237 <value>0</value> 238 </enumeratedValue> 239 <enumeratedValue> 240 <name>overrun</name> 241 <description>The event has occurred.</description> 242 <value>1</value> 243 </enumeratedValue> 244 </enumeratedValues> 245 </field> 246 <field> 247 <name>ABT</name> 248 <description>Slave Mode Transaction Abort.</description> 249 <bitOffset>4</bitOffset> 250 <bitWidth>1</bitWidth> 251 <enumeratedValues> 252 <enumeratedValue> 253 <name>noEvent</name> 254 <description>The event has not occurred.</description> 255 <value>0</value> 256 </enumeratedValue> 257 <enumeratedValue> 258 <name>aborted</name> 259 <description>The event has occurred.</description> 260 <value>1</value> 261 </enumeratedValue> 262 </enumeratedValues> 263 </field> 264 <field> 265 <name>COL</name> 266 <description>Collision.</description> 267 <bitOffset>5</bitOffset> 268 <bitWidth>1</bitWidth> 269 <enumeratedValues> 270 <enumeratedValue> 271 <name>noEvent</name> 272 <description>The event has not occurred.</description> 273 <value>0</value> 274 </enumeratedValue> 275 <enumeratedValue> 276 <name>collision</name> 277 <description>The event has occurred.</description> 278 <value>1</value> 279 </enumeratedValue> 280 </enumeratedValues> 281 </field> 282 <field> 283 <name>TOVR</name> 284 <description>Transmit Overrun.</description> 285 <bitOffset>6</bitOffset> 286 <bitWidth>1</bitWidth> 287 <enumeratedValues> 288 <enumeratedValue> 289 <name>noEvent</name> 290 <description>The event has not occurred.</description> 291 <value>0</value> 292 </enumeratedValue> 293 <enumeratedValue> 294 <name>overrun</name> 295 <description>The event has occurred.</description> 296 <value>1</value> 297 </enumeratedValue> 298 </enumeratedValues> 299 </field> 300 <field> 301 <name>IRQ</name> 302 <description>SPI Interrupt Request.</description> 303 <bitOffset>7</bitOffset> 304 <bitWidth>1</bitWidth> 305 <modifiedWriteValues>oneToClear</modifiedWriteValues> 306 <enumeratedValues> 307 <enumeratedValue> 308 <name>inactive</name> 309 <description>No interrupt is pending.</description> 310 <value>0</value> 311 </enumeratedValue> 312 <enumeratedValue> 313 <name>pending</name> 314 <description>An interrupt is pending.</description> 315 <value>1</value> 316 </enumeratedValue> 317 </enumeratedValues> 318 </field> 319 </fields> 320 </register> 321 <register> 322 <name>MOD</name> 323 <description>SPI Mode Register.</description> 324 <addressOffset>0x0C</addressOffset> 325 <fields> 326 <field> 327 <name>SSV</name> 328 <description>Slave Select Value.</description> 329 <bitOffset>0</bitOffset> 330 <bitWidth>1</bitWidth> 331 <enumeratedValues> 332 <enumeratedValue> 333 <name>lo</name> 334 <description>The SSEL pin will be driven low.</description> 335 <value>0</value> 336 </enumeratedValue> 337 <enumeratedValue> 338 <name>hi</name> 339 <description>The SSEL pin will be driven high.</description> 340 <value>1</value> 341 </enumeratedValue> 342 </enumeratedValues> 343 </field> 344 <field> 345 <name>SSEL</name> 346 <description>Slave Select I/O.</description> 347 <bitOffset>1</bitOffset> 348 <bitWidth>1</bitWidth> 349 <enumeratedValues> 350 <enumeratedValue> 351 <name>input</name> 352 <value>0</value> 353 </enumeratedValue> 354 <enumeratedValue> 355 <name>output</name> 356 <value>1</value> 357 </enumeratedValue> 358 </enumeratedValues> 359 </field> 360 <field> 361 <name>NUMBITS</name> 362 <bitOffset>2</bitOffset> 363 <bitWidth>4</bitWidth> 364 <enumeratedValues> 365 <enumeratedValue> 366 <name>16bits</name> 367 <value>0</value> 368 </enumeratedValue> 369 <enumeratedValue> 370 <name>1bits</name> 371 <value>1</value> 372 </enumeratedValue> 373 <enumeratedValue> 374 <name>2bits</name> 375 <value>2</value> 376 </enumeratedValue> 377 <enumeratedValue> 378 <name>3bits</name> 379 <value>3</value> 380 </enumeratedValue> 381 <enumeratedValue> 382 <name>4bits</name> 383 <value>4</value> 384 </enumeratedValue> 385 <enumeratedValue> 386 <name>5bits</name> 387 <value>5</value> 388 </enumeratedValue> 389 <enumeratedValue> 390 <name>6bits</name> 391 <value>6</value> 392 </enumeratedValue> 393 <enumeratedValue> 394 <name>7bits</name> 395 <value>7</value> 396 </enumeratedValue> 397 <enumeratedValue> 398 <name>8bits</name> 399 <value>8</value> 400 </enumeratedValue> 401 <enumeratedValue> 402 <name>9bits</name> 403 <value>9</value> 404 </enumeratedValue> 405 <enumeratedValue> 406 <name>10bits</name> 407 <value>10</value> 408 </enumeratedValue> 409 <enumeratedValue> 410 <name>11bits</name> 411 <value>11</value> 412 </enumeratedValue> 413 <enumeratedValue> 414 <name>12bits</name> 415 <value>12</value> 416 </enumeratedValue> 417 <enumeratedValue> 418 <name>13bits</name> 419 <value>13</value> 420 </enumeratedValue> 421 <enumeratedValue> 422 <name>14bits</name> 423 <value>14</value> 424 </enumeratedValue> 425 <enumeratedValue> 426 <name>15bits</name> 427 <value>15</value> 428 </enumeratedValue> 429 </enumeratedValues> 430 </field> 431 <field> 432 <name>TX_ALIGN</name> 433 <description>Transmit Left Justify.</description> 434 <bitOffset>7</bitOffset> 435 <bitWidth>1</bitWidth> 436 <enumeratedValues> 437 <enumeratedValue> 438 <name>lsb</name> 439 <value>0</value> 440 </enumeratedValue> 441 <enumeratedValue> 442 <name>msb</name> 443 <value>1</value> 444 </enumeratedValue> 445 </enumeratedValues> 446 </field> 447 </fields> 448 </register> 449 <register> 450 <name>BRG</name> 451 <description>Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).</description> 452 <addressOffset>0x14</addressOffset> 453 <resetValue>0x0000FFFF</resetValue> 454 <fields> 455 <field> 456 <name>DIV</name> 457 <description>Baud Rate Reload Value.</description> 458 <bitOffset>0</bitOffset> 459 <bitWidth>16</bitWidth> 460 </field> 461 </fields> 462 </register> 463 <register> 464 <name>DMA</name> 465 <description>SPI DMA Register.</description> 466 <addressOffset>0x18</addressOffset> 467 <resetValue>0x00070007</resetValue> 468 <fields> 469 <field> 470 <name>TX_FIFO_LVL</name> 471 <description>Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.</description> 472 <bitOffset>0</bitOffset> 473 <bitWidth>3</bitWidth> 474 <enumeratedValues> 475 <enumeratedValue> 476 <name>1entries</name> 477 <value>0</value> 478 </enumeratedValue> 479 <enumeratedValue> 480 <name>2entries</name> 481 <value>1</value> 482 </enumeratedValue> 483 <enumeratedValue> 484 <name>3entries</name> 485 <value>2</value> 486 </enumeratedValue> 487 <enumeratedValue> 488 <name>4entries</name> 489 <value>3</value> 490 </enumeratedValue> 491 <enumeratedValue> 492 <name>5entries</name> 493 <value>4</value> 494 </enumeratedValue> 495 <enumeratedValue> 496 <name>6entries</name> 497 <value>5</value> 498 </enumeratedValue> 499 <enumeratedValue> 500 <name>7entries</name> 501 <value>6</value> 502 </enumeratedValue> 503 <enumeratedValue> 504 <name>8entries</name> 505 <value>7</value> 506 </enumeratedValue> 507 </enumeratedValues> 508 </field> 509 <field> 510 <name>TX_FIFO_CLR</name> 511 <description>Transmit FIFO Clear.</description> 512 <bitOffset>4</bitOffset> 513 <bitWidth>1</bitWidth> 514 <access>write-only</access> 515 <enumeratedValues> 516 <enumeratedValue> 517 <name>clear</name> 518 <description>Start TX FIFO Clear operation.</description> 519 <value>1</value> 520 </enumeratedValue> 521 </enumeratedValues> 522 </field> 523 <field> 524 <name>TX_FIFO_CNT</name> 525 <description>Transmit FIFO Count.</description> 526 <bitOffset>8</bitOffset> 527 <bitWidth>4</bitWidth> 528 <access>read-only</access> 529 </field> 530 <field> 531 <name>TX_DMA_EN</name> 532 <description>Transmit DMA Enable.</description> 533 <bitOffset>15</bitOffset> 534 <bitWidth>1</bitWidth> 535 <enumeratedValues> 536 <enumeratedValue> 537 <name>dis</name> 538 <value>0</value> 539 </enumeratedValue> 540 <enumeratedValue> 541 <name>en</name> 542 <value>1</value> 543 </enumeratedValue> 544 </enumeratedValues> 545 </field> 546 <field> 547 <name>RX_FIFO_LVL</name> 548 <description>Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.</description> 549 <bitOffset>16</bitOffset> 550 <bitWidth>3</bitWidth> 551 <enumeratedValues> 552 <name>fifo_level_enum</name> 553 <enumeratedValue> 554 <name>1entries</name> 555 <value>0</value> 556 </enumeratedValue> 557 <enumeratedValue> 558 <name>2entries</name> 559 <value>1</value> 560 </enumeratedValue> 561 <enumeratedValue> 562 <name>3entries</name> 563 <value>2</value> 564 </enumeratedValue> 565 <enumeratedValue> 566 <name>4entries</name> 567 <value>3</value> 568 </enumeratedValue> 569 <enumeratedValue> 570 <name>5entries</name> 571 <value>4</value> 572 </enumeratedValue> 573 <enumeratedValue> 574 <name>6entries</name> 575 <value>5</value> 576 </enumeratedValue> 577 <enumeratedValue> 578 <name>7entries</name> 579 <value>6</value> 580 </enumeratedValue> 581 <enumeratedValue> 582 <name>8entries</name> 583 <value>7</value> 584 </enumeratedValue> 585 </enumeratedValues> 586 </field> 587 <field> 588 <name>RX_FIFO_CLR</name> 589 <description>Receive FIFO Clear.</description> 590 <bitOffset>20</bitOffset> 591 <bitWidth>1</bitWidth> 592 <enumeratedValues> 593 <enumeratedValue> 594 <name>clear</name> 595 <description>Start RX FIFO clear operation.</description> 596 <value>1</value> 597 </enumeratedValue> 598 </enumeratedValues> 599 </field> 600 <field> 601 <name>RX_FIFO_CNT</name> 602 <description>Receive FIFO Count.</description> 603 <bitOffset>24</bitOffset> 604 <bitWidth>4</bitWidth> 605 <access>read-only</access> 606 </field> 607 <field> 608 <name>RX_DMA_EN</name> 609 <description>Receive DMA Enable.</description> 610 <bitOffset>31</bitOffset> 611 <bitWidth>1</bitWidth> 612 <enumeratedValues> 613 <enumeratedValue> 614 <name>dis</name> 615 <value>0</value> 616 </enumeratedValue> 617 <enumeratedValue> 618 <name>en</name> 619 <value>1</value> 620 </enumeratedValue> 621 </enumeratedValues> 622 </field> 623 </fields> 624 </register> 625 <register> 626 <name>I2S_CTRL</name> 627 <description>I2S Control Register.</description> 628 <addressOffset>0x1C</addressOffset> 629 <fields> 630 <field> 631 <name>I2S_EN</name> 632 <description>I2S Mode Enable.</description> 633 <bitOffset>0</bitOffset> 634 <bitWidth>1</bitWidth> 635 <enumeratedValues> 636 <enumeratedValue> 637 <name>dis</name> 638 <value>0</value> 639 </enumeratedValue> 640 <enumeratedValue> 641 <name>en</name> 642 <value>1</value> 643 </enumeratedValue> 644 </enumeratedValues> 645 </field> 646 <field> 647 <name>I2S_MUTE</name> 648 <description>I2S Mute transmit.</description> 649 <bitOffset>1</bitOffset> 650 <bitWidth>1</bitWidth> 651 <enumeratedValues> 652 <enumeratedValue> 653 <name>normal</name> 654 <description>Normal Transmit.</description> 655 <value>0</value> 656 </enumeratedValue> 657 <enumeratedValue> 658 <name>muted</name> 659 <description>Transmit data is replaced with 0.</description> 660 <value>1</value> 661 </enumeratedValue> 662 </enumeratedValues> 663 </field> 664 <field> 665 <name>I2S_PAUSE</name> 666 <description>I2S Pause transmit/receive.</description> 667 <bitOffset>2</bitOffset> 668 <bitWidth>1</bitWidth> 669 <enumeratedValues> 670 <enumeratedValue> 671 <name>normal</name> 672 <description>Normal Transmit.</description> 673 <value>0</value> 674 </enumeratedValue> 675 <enumeratedValue> 676 <name>pause</name> 677 <description>Halt transmit and receive FIFO and DMA access, transmit 0's.</description> 678 <value>1</value> 679 </enumeratedValue> 680 </enumeratedValues> 681 </field> 682 <field> 683 <name>I2S_MONO</name> 684 <description>I2S Monophonic Audio Mode.</description> 685 <bitOffset>3</bitOffset> 686 <bitWidth>1</bitWidth> 687 <enumeratedValues> 688 <enumeratedValue> 689 <name>stereo</name> 690 <description>Stereophonic audio.</description> 691 <value>0</value> 692 </enumeratedValue> 693 <enumeratedValue> 694 <name>mono</name> 695 <description>Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.</description> 696 <value>1</value> 697 </enumeratedValue> 698 </enumeratedValues> 699 </field> 700 <field> 701 <name>I2S_LJ</name> 702 <description>I2S Left Justify.</description> 703 <bitOffset>4</bitOffset> 704 <bitWidth>1</bitWidth> 705 <enumeratedValues> 706 <enumeratedValue> 707 <name>lag</name> 708 <description>Normal I2S audio protocol.</description> 709 <value>0</value> 710 </enumeratedValue> 711 <enumeratedValue> 712 <name>syncronized</name> 713 <description>Audio data is synchronized with SSEL.</description> 714 <value>1</value> 715 </enumeratedValue> 716 </enumeratedValues> 717 </field> 718 </fields> 719 </register> 720 </registers> 721 </peripheral> 722 <!-- SPIMSS: SPI MSS --> 723</device>
