1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include <stdio.h>
22 #include <stddef.h>
23 #include <stdint.h>
24 #include "mxc_device.h"
25 #include "mxc_assert.h"
26 #include "mxc_lock.h"
27 #include "mxc_sys.h"
28 #include "mxc_delay.h"
29 #include "spimss_reva_regs.h"
30 #include "spimss_reva.h"
31
32 /* **** Functions **** */
33
34 /* ************************************************************************** */
MXC_SPIMSS_Init(mxc_spimss_regs_t * spi,unsigned mode,unsigned freq)35 int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq)
36 {
37 if (mode > 3) {
38 return E_BAD_PARAM;
39 }
40
41 // Check if frequency is too high
42 if (freq > PeripheralClock) {
43 return E_BAD_PARAM;
44 }
45
46 // Configure GPIO for spimss
47 if (spi == MXC_SPIMSS) {
48 MXC_SYS_Reset_Periph(MXC_SYS_RESET_I2S);
49 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2S);
50 MXC_GPIO_Config(&gpio_cfg_i2s);
51 } else {
52 return E_NO_DEVICE;
53 }
54
55 return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq);
56 }
57 /* ************************************************************************* */
MXC_SPIMSS_Shutdown(mxc_spimss_regs_t * spi)58 int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
59 {
60 MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t *)spi);
61
62 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2S);
63 return E_NO_ERROR;
64 }
65 /* ************************************************************************** */
MXC_SPIMSS_Handler(mxc_spimss_regs_t * spi)66 void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ
67 {
68 MXC_SPIMSS_RevA_Handler((mxc_spimss_reva_regs_t *)spi);
69 }
70
71 /* ************************************************************************** */
MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t * spi,mxc_spimss_req_t * req)72 int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
73 {
74 return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
75 }
76
77 /* ************************************************************************** */
MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t * spi,mxc_spimss_req_t * req)78 int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
79 {
80 return MXC_SPIMSS_RevA_SlaveTrans((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
81 }
82
83 /* ************************************************************************** */
MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t * spi,mxc_spimss_req_t * req)84 int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
85 {
86 return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t *)spi,
87 (spimss_reva_req_t *)req);
88 }
89
90 /* ************************************************************************** */
MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t * spi,mxc_spimss_req_t * req)91 int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
92 {
93 return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
94 }
95
96 /* ************************************************************************* */
MXC_SPIMSS_AbortAsync(mxc_spimss_req_t * req)97 int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req)
98 {
99 return MXC_SPIMSS_RevA_AbortAsync((spimss_reva_req_t *)req);
100 }
101
102 /* ************************************************************************** */
MXC_SPIMSS_MasterTransDMA(mxc_spimss_regs_t * spi,mxc_spimss_req_t * req)103 int MXC_SPIMSS_MasterTransDMA(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
104 {
105 return MXC_SPIMSS_RevA_MasterTransDMA((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req);
106 }
107
108 /* ************************************************************************* */
MXC_SPIMSS_SetAutoDMAHandlers(mxc_spimss_regs_t * spi,bool enable)109 int MXC_SPIMSS_SetAutoDMAHandlers(mxc_spimss_regs_t *spi, bool enable)
110 {
111 return MXC_SPIMSS_RevA_SetAutoDMAHandlers((mxc_spimss_reva_regs_t *)spi, enable);
112 }
113
114 /* ************************************************************************* */
MXC_SPIMSS_SetTXDMAChannel(mxc_spimss_regs_t * spi,unsigned int channel)115 int MXC_SPIMSS_SetTXDMAChannel(mxc_spimss_regs_t *spi, unsigned int channel)
116 {
117 return MXC_SPIMSS_RevA_SetTXDMAChannel((mxc_spimss_reva_regs_t *)spi, channel);
118 }
119
120 /* ************************************************************************* */
MXC_SPIMSS_GetTXDMAChannel(mxc_spimss_regs_t * spi)121 int MXC_SPIMSS_GetTXDMAChannel(mxc_spimss_regs_t *spi)
122 {
123 return MXC_SPIMSS_RevA_GetTXDMAChannel((mxc_spimss_reva_regs_t *)spi);
124 }
125
126 /* ************************************************************************* */
MXC_SPIMSS_SetRXDMAChannel(mxc_spimss_regs_t * spi,unsigned int channel)127 int MXC_SPIMSS_SetRXDMAChannel(mxc_spimss_regs_t *spi, unsigned int channel)
128 {
129 return MXC_SPIMSS_RevA_SetRXDMAChannel((mxc_spimss_reva_regs_t *)spi, channel);
130 }
131
132 /* ************************************************************************* */
MXC_SPIMSS_GetRXDMAChannel(mxc_spimss_regs_t * spi)133 int MXC_SPIMSS_GetRXDMAChannel(mxc_spimss_regs_t *spi)
134 {
135 return MXC_SPIMSS_RevA_GetRXDMAChannel((mxc_spimss_reva_regs_t *)spi);
136 }
137
