1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x400BE000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>FIFO32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>DATA</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>FIFO16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <alternateRegister>FIFO32</alternateRegister> 38 <addressOffset>0x00</addressOffset> 39 <size>16</size> 40 <access>read-write</access> 41 <fields> 42 <field> 43 <name>DATA</name> 44 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 45 <bitOffset>0</bitOffset> 46 <bitWidth>16</bitWidth> 47 </field> 48 </fields> 49 </register> 50 <register> 51 <dim>4</dim> 52 <dimIncrement>1</dimIncrement> 53 <name>FIFO8[%s]</name> 54 <description>Register for reading and writing the FIFO.</description> 55 <alternateRegister>FIFO32</alternateRegister> 56 <addressOffset>0x00</addressOffset> 57 <size>8</size> 58 <access>read-write</access> 59 <fields> 60 <field> 61 <name>DATA</name> 62 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 63 <bitOffset>0</bitOffset> 64 <bitWidth>8</bitWidth> 65 </field> 66 </fields> 67 </register> 68 <register> 69 <name>CTRL0</name> 70 <description>Register for controlling SPI peripheral.</description> 71 <addressOffset>0x04</addressOffset> 72 <access>read-write</access> 73 <fields> 74 <field> 75 <name>EN</name> 76 <description>SPI Enable.</description> 77 <bitOffset>0</bitOffset> 78 <bitWidth>1</bitWidth> 79 <enumeratedValues> 80 <enumeratedValue> 81 <name>dis</name> 82 <description>SPI is disabled.</description> 83 <value>0</value> 84 </enumeratedValue> 85 <enumeratedValue> 86 <name>en</name> 87 <description>SPI is enabled.</description> 88 <value>1</value> 89 </enumeratedValue> 90 </enumeratedValues> 91 </field> 92 <field> 93 <name>MST_MODE</name> 94 <description>Master Mode Enable.</description> 95 <bitOffset>1</bitOffset> 96 <bitWidth>1</bitWidth> 97 <enumeratedValues> 98 <enumeratedValue> 99 <name>dis</name> 100 <description>SPI is Slave mode.</description> 101 <value>0</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>en</name> 105 <description>SPI is Master mode.</description> 106 <value>1</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 <field> 111 <name>SS_IO</name> 112 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 113 <bitOffset>4</bitOffset> 114 <bitWidth>1</bitWidth> 115 <enumeratedValues> 116 <enumeratedValue> 117 <name>output</name> 118 <description>Slave select 0 is output.</description> 119 <value>0</value> 120 </enumeratedValue> 121 <enumeratedValue> 122 <name>input</name> 123 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 124 <value>1</value> 125 </enumeratedValue> 126 </enumeratedValues> 127 </field> 128 <field> 129 <name>START</name> 130 <description>Start Transmit.</description> 131 <bitOffset>5</bitOffset> 132 <bitWidth>1</bitWidth> 133 <enumeratedValues> 134 <enumeratedValue> 135 <name>start</name> 136 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 137 <value>1</value> 138 </enumeratedValue> 139 </enumeratedValues> 140 </field> 141 <field> 142 <name>SS_CTRL</name> 143 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 144 <bitOffset>8</bitOffset> 145 <bitWidth>1</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>DEASSERT</name> 149 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>ASSERT</name> 154 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 155 <value>1</value> 156 </enumeratedValue> 157 </enumeratedValues> 158 </field> 159 <field> 160 <name>SS_ACTIVE</name> 161 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 162 <bitOffset>16</bitOffset> 163 <bitWidth>4</bitWidth> 164 <enumeratedValues> 165 <enumeratedValue> 166 <name>SS0</name> 167 <description>SS0 is selected.</description> 168 <value>0x1</value> 169 </enumeratedValue> 170 <enumeratedValue> 171 <name>SS1</name> 172 <description>SS1 is selected.</description> 173 <value>0x2</value> 174 </enumeratedValue> 175 <enumeratedValue> 176 <name>SS2</name> 177 <description>SS2 is selected.</description> 178 <value>0x4</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>SS3</name> 182 <description>SS3 is selected.</description> 183 <value>0x8</value> 184 </enumeratedValue> 185 </enumeratedValues> 186 </field> 187 </fields> 188 </register> 189 <register> 190 <name>CTRL1</name> 191 <description>Register for controlling SPI peripheral.</description> 192 <addressOffset>0x08</addressOffset> 193 <access>read-write</access> 194 <fields> 195 <field> 196 <name>TX_NUM_CHAR</name> 197 <description>Nubmer of Characters to transmit.</description> 198 <bitOffset>0</bitOffset> 199 <bitWidth>16</bitWidth> 200 </field> 201 <field> 202 <name>RX_NUM_CHAR</name> 203 <description>Nubmer of Characters to receive.</description> 204 <bitOffset>16</bitOffset> 205 <bitWidth>16</bitWidth> 206 </field> 207 </fields> 208 </register> 209 <register> 210 <name>CTRL2</name> 211 <description>Register for controlling SPI peripheral.</description> 212 <addressOffset>0x0C</addressOffset> 213 <access>read-write</access> 214 <fields> 215 <field> 216 <name>CLKPHA</name> 217 <description>Clock Phase.</description> 218 <bitOffset>0</bitOffset> 219 <bitWidth>1</bitWidth> 220 <enumeratedValues> 221 <enumeratedValue> 222 <name>Rising_Edge</name> 223 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 224 <value>0</value> 225 </enumeratedValue> 226 <enumeratedValue> 227 <name>Falling_Edge</name> 228 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 229 <value>1</value> 230 </enumeratedValue> 231 </enumeratedValues> 232 </field> 233 <field> 234 <name>CLKPOL</name> 235 <description>Clock Polarity.</description> 236 <bitOffset>1</bitOffset> 237 <bitWidth>1</bitWidth> 238 <enumeratedValues> 239 <enumeratedValue> 240 <name>Normal</name> 241 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 242 <value>0</value> 243 </enumeratedValue> 244 <enumeratedValue> 245 <name>Inverted</name> 246 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 247 <value>1</value> 248 </enumeratedValue> 249 </enumeratedValues> 250 </field> 251 <field> 252 <name>SCLK_FB_INV</name> 253 <description>Clock Polarity.</description> 254 <bitOffset>4</bitOffset> 255 <bitWidth>1</bitWidth> 256 <enumeratedValues> 257 <enumeratedValue> 258 <name>Normal</name> 259 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 260 <value>0</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>Inverted</name> 264 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 265 <value>1</value> 266 </enumeratedValue> 267 </enumeratedValues> 268 </field> 269 <field> 270 <name>NUMBITS</name> 271 <description>Number of Bits per character.</description> 272 <bitOffset>8</bitOffset> 273 <bitWidth>4</bitWidth> 274 <enumeratedValues> 275 <enumeratedValue> 276 <name>16</name> 277 <description>16 bits per character.</description> 278 <value>0</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>1</name> 282 <description>1 bits per character.</description> 283 <value>1</value> 284 </enumeratedValue> 285 <enumeratedValue> 286 <name>2</name> 287 <description>2 bits per character.</description> 288 <value>2</value> 289 </enumeratedValue> 290 <enumeratedValue> 291 <name>3</name> 292 <description>3 bits per character.</description> 293 <value>3</value> 294 </enumeratedValue> 295 <enumeratedValue> 296 <name>4</name> 297 <description>4 bits per character.</description> 298 <value>4</value> 299 </enumeratedValue> 300 <enumeratedValue> 301 <name>5</name> 302 <description>5 bits per character.</description> 303 <value>5</value> 304 </enumeratedValue> 305 <enumeratedValue> 306 <name>6</name> 307 <description>6 bits per character.</description> 308 <value>6</value> 309 </enumeratedValue> 310 <enumeratedValue> 311 <name>7</name> 312 <description>7 bits per character.</description> 313 <value>7</value> 314 </enumeratedValue> 315 <enumeratedValue> 316 <name>8</name> 317 <description>8 bits per character.</description> 318 <value>8</value> 319 </enumeratedValue> 320 <enumeratedValue> 321 <name>9</name> 322 <description>9 bits per character.</description> 323 <value>9</value> 324 </enumeratedValue> 325 <enumeratedValue> 326 <name>10</name> 327 <description>10 bits per character.</description> 328 <value>10</value> 329 </enumeratedValue> 330 <enumeratedValue> 331 <name>11</name> 332 <description>11 bits per character.</description> 333 <value>11</value> 334 </enumeratedValue> 335 <enumeratedValue> 336 <name>12</name> 337 <description>12 bits per character.</description> 338 <value>12</value> 339 </enumeratedValue> 340 <enumeratedValue> 341 <name>13</name> 342 <description>13 bits per character.</description> 343 <value>13</value> 344 </enumeratedValue> 345 <enumeratedValue> 346 <name>14</name> 347 <description>14 bits per character.</description> 348 <value>14</value> 349 </enumeratedValue> 350 <enumeratedValue> 351 <name>15</name> 352 <description>15 bits per character.</description> 353 <value>15</value> 354 </enumeratedValue> 355 </enumeratedValues> 356 </field> 357 <field> 358 <name>DATA_WIDTH</name> 359 <description>SPI Data width.</description> 360 <bitOffset>12</bitOffset> 361 <bitWidth>2</bitWidth> 362 <enumeratedValues> 363 <enumeratedValue> 364 <name>Mono</name> 365 <description>1 data pin.</description> 366 <value>0</value> 367 </enumeratedValue> 368 <enumeratedValue> 369 <name>Dual</name> 370 <description>2 data pins.</description> 371 <value>1</value> 372 </enumeratedValue> 373 <enumeratedValue> 374 <name>Quad</name> 375 <description>4 data pins.</description> 376 <value>2</value> 377 </enumeratedValue> 378 </enumeratedValues> 379 </field> 380 <field> 381 <name>THREE_WIRE</name> 382 <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description> 383 <bitOffset>15</bitOffset> 384 <bitWidth>1</bitWidth> 385 <enumeratedValues> 386 <enumeratedValue> 387 <name>dis</name> 388 <description>Use four wire mode (Mono only).</description> 389 <value>0</value> 390 </enumeratedValue> 391 <enumeratedValue> 392 <name>en</name> 393 <description>Use three wire mode.</description> 394 <value>1</value> 395 </enumeratedValue> 396 </enumeratedValues> 397 </field> 398 <field> 399 <name>SSPOL</name> 400 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 401 <bitOffset>16</bitOffset> 402 <bitWidth>4</bitWidth> 403 <enumeratedValues> 404 <enumeratedValue> 405 <name>SS0_high</name> 406 <description>SS0 active high.</description> 407 <value>0x1</value> 408 </enumeratedValue> 409 <enumeratedValue> 410 <name>SS1_high</name> 411 <description>SS1 active high.</description> 412 <value>0x2</value> 413 </enumeratedValue> 414 <enumeratedValue> 415 <name>SS2_high</name> 416 <description>SS2 active high.</description> 417 <value>0x4</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>SS3_high</name> 421 <description>SS3 active high.</description> 422 <value>0x8</value> 423 </enumeratedValue> 424 </enumeratedValues> 425 </field> 426 </fields> 427 </register> 428 <register> 429 <name>SSTIME</name> 430 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 431 <addressOffset>0x10</addressOffset> 432 <access>read-write</access> 433 <fields> 434 <field> 435 <name>PRE</name> 436 <description>Slave Select Pre delay 1.</description> 437 <bitOffset>0</bitOffset> 438 <bitWidth>8</bitWidth> 439 <enumeratedValues> 440 <enumeratedValue> 441 <name>256</name> 442 <description>256 system clocks between SS active and first serial clock edge.</description> 443 <value>0</value> 444 </enumeratedValue> 445 </enumeratedValues> 446 </field> 447 <field> 448 <name>POST</name> 449 <description>Slave Select Post delay 2.</description> 450 <bitOffset>8</bitOffset> 451 <bitWidth>8</bitWidth> 452 <enumeratedValues> 453 <enumeratedValue> 454 <name>256</name> 455 <description>256 system clocks between last serial clock edge and SS inactive.</description> 456 <value>0</value> 457 </enumeratedValue> 458 </enumeratedValues> 459 </field> 460 <field> 461 <name>INACT</name> 462 <description>Slave Select Inactive delay.</description> 463 <bitOffset>16</bitOffset> 464 <bitWidth>8</bitWidth> 465 <enumeratedValues> 466 <enumeratedValue> 467 <name>256</name> 468 <description>256 system clocks between transactions.</description> 469 <value>0</value> 470 </enumeratedValue> 471 </enumeratedValues> 472 </field> 473 </fields> 474 </register> 475 <register> 476 <name>CLKCTRL</name> 477 <description>Register for controlling SPI clock rate.</description> 478 <addressOffset>0x14</addressOffset> 479 <access>read-write</access> 480 <fields> 481 <field> 482 <name>LO</name> 483 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 484 <bitOffset>0</bitOffset> 485 <bitWidth>8</bitWidth> 486 <enumeratedValues> 487 <enumeratedValue> 488 <name>Dis</name> 489 <description>Duty cycle control of serial clock generation is disabled.</description> 490 <value>0</value> 491 </enumeratedValue> 492 </enumeratedValues> 493 </field> 494 <field> 495 <name>HI</name> 496 <description>High duty cycle control. In timer mode, reload[15:8].</description> 497 <bitOffset>8</bitOffset> 498 <bitWidth>8</bitWidth> 499 <enumeratedValues> 500 <enumeratedValue> 501 <name>Dis</name> 502 <description>Duty cycle control of serial clock generation is disabled.</description> 503 <value>0</value> 504 </enumeratedValue> 505 </enumeratedValues> 506 </field> 507 <field> 508 <name>CLKDIV</name> 509 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 510 <bitOffset>16</bitOffset> 511 <bitWidth>4</bitWidth> 512 </field> 513 </fields> 514 </register> 515 <register> 516 <name>DMA</name> 517 <description>Register for controlling DMA.</description> 518 <addressOffset>0x1C</addressOffset> 519 <access>read-write</access> 520 <fields> 521 <field> 522 <name>TX_THD_VAL</name> 523 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 524 <bitOffset>0</bitOffset> 525 <bitWidth>5</bitWidth> 526 </field> 527 <field> 528 <name>TX_FIFO_EN</name> 529 <description>Transmit FIFO enabled for SPI transactions.</description> 530 <bitOffset>6</bitOffset> 531 <bitWidth>1</bitWidth> 532 <enumeratedValues> 533 <enumeratedValue> 534 <name>dis</name> 535 <description>Transmit FIFO is not enabled.</description> 536 <value>0</value> 537 </enumeratedValue> 538 <enumeratedValue> 539 <name>en</name> 540 <description>Transmit FIFO is enabled.</description> 541 <value>1</value> 542 </enumeratedValue> 543 </enumeratedValues> 544 </field> 545 <field> 546 <name>TX_FLUSH</name> 547 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 548 pointers. This should be done when FIFO is not being accessed on the SPI side. 549 .</description> 550 <bitOffset>7</bitOffset> 551 <bitWidth>1</bitWidth> 552 <enumeratedValues> 553 <enumeratedValue> 554 <name>CLEAR</name> 555 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 556 <value>1</value> 557 </enumeratedValue> 558 </enumeratedValues> 559 </field> 560 <field> 561 <name>TX_LVL</name> 562 <description>Count of entries in TX FIFO.</description> 563 <bitOffset>8</bitOffset> 564 <bitWidth>6</bitWidth> 565 <access>read-only</access> 566 </field> 567 <field> 568 <name>TX_EN</name> 569 <description>TX DMA Enable.</description> 570 <bitOffset>15</bitOffset> 571 <bitWidth>1</bitWidth> 572 <enumeratedValues> 573 <enumeratedValue> 574 <name>DIS</name> 575 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 576 <value>0</value> 577 </enumeratedValue> 578 <enumeratedValue> 579 <name>en</name> 580 <description>TX DMA requests are enabled.</description> 581 <value>1</value> 582 </enumeratedValue> 583 </enumeratedValues> 584 </field> 585 <field> 586 <name>RX_THD_VAL</name> 587 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 588 <bitOffset>16</bitOffset> 589 <bitWidth>5</bitWidth> 590 </field> 591 <field> 592 <name>RX_FIFO_EN</name> 593 <description>Receive FIFO enabled for SPI transactions.</description> 594 <bitOffset>22</bitOffset> 595 <bitWidth>1</bitWidth> 596 <enumeratedValues> 597 <enumeratedValue> 598 <name>DIS</name> 599 <description>Receive FIFO is not enabled.</description> 600 <value>0</value> 601 </enumeratedValue> 602 <enumeratedValue> 603 <name>en</name> 604 <description>Receive FIFO is enabled.</description> 605 <value>1</value> 606 </enumeratedValue> 607 </enumeratedValues> 608 </field> 609 <field> 610 <name>RX_FLUSH</name> 611 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 612 <bitOffset>23</bitOffset> 613 <bitWidth>1</bitWidth> 614 <enumeratedValues> 615 <enumeratedValue> 616 <name>CLEAR</name> 617 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 618 <value>1</value> 619 </enumeratedValue> 620 </enumeratedValues> 621 </field> 622 <field> 623 <name>RX_LVL</name> 624 <description>Count of entries in RX FIFO.</description> 625 <bitOffset>24</bitOffset> 626 <bitWidth>6</bitWidth> 627 <access>read-only</access> 628 </field> 629 <field> 630 <name>RX_EN</name> 631 <description>RX DMA Enable.</description> 632 <bitOffset>31</bitOffset> 633 <bitWidth>1</bitWidth> 634 <enumeratedValues> 635 <enumeratedValue> 636 <name>dis</name> 637 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 638 <value>0</value> 639 </enumeratedValue> 640 <enumeratedValue> 641 <name>en</name> 642 <description>RX DMA requests are enabled.</description> 643 <value>1</value> 644 </enumeratedValue> 645 </enumeratedValues> 646 </field> 647 </fields> 648 </register> 649 <register> 650 <name>INTFL</name> 651 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 652 <addressOffset>0x20</addressOffset> 653 <access>read-write</access> 654 <fields> 655 <field> 656 <name>TX_THD</name> 657 <description>TX FIFO Threshold Crossed.</description> 658 <bitOffset>0</bitOffset> 659 <bitWidth>1</bitWidth> 660 <enumeratedValues> 661 <enumeratedValue> 662 <name>clear</name> 663 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 664 <value>1</value> 665 </enumeratedValue> 666 </enumeratedValues> 667 </field> 668 <field> 669 <name>TX_EM</name> 670 <description>TX FIFO Empty.</description> 671 <bitOffset>1</bitOffset> 672 <bitWidth>1</bitWidth> 673 <enumeratedValues> 674 <enumeratedValue> 675 <name>clear</name> 676 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 677 <value>1</value> 678 </enumeratedValue> 679 </enumeratedValues> 680 </field> 681 <field> 682 <name>RX_THD</name> 683 <description>RX FIFO Threshold Crossed.</description> 684 <bitOffset>2</bitOffset> 685 <bitWidth>1</bitWidth> 686 <enumeratedValues> 687 <enumeratedValue> 688 <name>clear</name> 689 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 690 <value>1</value> 691 </enumeratedValue> 692 </enumeratedValues> 693 </field> 694 <field> 695 <name>RX_FULL</name> 696 <description>RX FIFO FULL.</description> 697 <bitOffset>3</bitOffset> 698 <bitWidth>1</bitWidth> 699 <enumeratedValues> 700 <enumeratedValue> 701 <name>clear</name> 702 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 703 <value>1</value> 704 </enumeratedValue> 705 </enumeratedValues> 706 </field> 707 <field> 708 <name>SSA</name> 709 <description>Slave Select Asserted.</description> 710 <bitOffset>4</bitOffset> 711 <bitWidth>1</bitWidth> 712 <enumeratedValues> 713 <enumeratedValue> 714 <name>clear</name> 715 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 716 <value>1</value> 717 </enumeratedValue> 718 </enumeratedValues> 719 </field> 720 <field> 721 <name>SSD</name> 722 <description>Slave Select Deasserted.</description> 723 <bitOffset>5</bitOffset> 724 <bitWidth>1</bitWidth> 725 <enumeratedValues> 726 <enumeratedValue> 727 <name>clear</name> 728 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 729 <value>1</value> 730 </enumeratedValue> 731 </enumeratedValues> 732 </field> 733 <field> 734 <name>FAULT</name> 735 <description>Multi-Master Mode Fault.</description> 736 <bitOffset>8</bitOffset> 737 <bitWidth>1</bitWidth> 738 <enumeratedValues> 739 <enumeratedValue> 740 <name>clear</name> 741 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 742 <value>1</value> 743 </enumeratedValue> 744 </enumeratedValues> 745 </field> 746 <field> 747 <name>ABORT</name> 748 <description>Slave Abort Detected.</description> 749 <bitOffset>9</bitOffset> 750 <bitWidth>1</bitWidth> 751 <enumeratedValues> 752 <enumeratedValue> 753 <name>clear</name> 754 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 755 <value>1</value> 756 </enumeratedValue> 757 </enumeratedValues> 758 </field> 759 <field> 760 <name>MST_DONE</name> 761 <description>Master Done, set when SPI Master has completed any transactions.</description> 762 <bitOffset>11</bitOffset> 763 <bitWidth>1</bitWidth> 764 <enumeratedValues> 765 <enumeratedValue> 766 <name>clear</name> 767 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 768 <value>1</value> 769 </enumeratedValue> 770 </enumeratedValues> 771 </field> 772 <field> 773 <name>TX_OV</name> 774 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 775 <bitOffset>12</bitOffset> 776 <bitWidth>1</bitWidth> 777 <enumeratedValues> 778 <enumeratedValue> 779 <name>clear</name> 780 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 781 <value>1</value> 782 </enumeratedValue> 783 </enumeratedValues> 784 </field> 785 <field> 786 <name>TX_UN</name> 787 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 788 <bitOffset>13</bitOffset> 789 <bitWidth>1</bitWidth> 790 <enumeratedValues> 791 <enumeratedValue> 792 <name>clear</name> 793 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 794 <value>1</value> 795 </enumeratedValue> 796 </enumeratedValues> 797 </field> 798 <field> 799 <name>RX_OV</name> 800 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 801 <bitOffset>14</bitOffset> 802 <bitWidth>1</bitWidth> 803 <enumeratedValues> 804 <enumeratedValue> 805 <name>clear</name> 806 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 807 <value>1</value> 808 </enumeratedValue> 809 </enumeratedValues> 810 </field> 811 <field> 812 <name>RX_UN</name> 813 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 814 <bitOffset>15</bitOffset> 815 <bitWidth>1</bitWidth> 816 <enumeratedValues> 817 <enumeratedValue> 818 <name>clear</name> 819 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 820 <value>1</value> 821 </enumeratedValue> 822 </enumeratedValues> 823 </field> 824 </fields> 825 </register> 826 <register> 827 <name>INTEN</name> 828 <description>Register for enabling interrupts.</description> 829 <addressOffset>0x24</addressOffset> 830 <access>read-write</access> 831 <fields> 832 <field> 833 <name>TX_THD</name> 834 <description>TX FIFO Threshold interrupt enable.</description> 835 <bitOffset>0</bitOffset> 836 <bitWidth>1</bitWidth> 837 <enumeratedValues> 838 <enumeratedValue> 839 <name>dis</name> 840 <description>Interrupt is disabled.</description> 841 <value>0</value> 842 </enumeratedValue> 843 <enumeratedValue> 844 <name>en</name> 845 <description>Interrupt is enabled.</description> 846 <value>1</value> 847 </enumeratedValue> 848 </enumeratedValues> 849 </field> 850 <field> 851 <name>TX_EM</name> 852 <description>TX FIFO Empty interrupt enable.</description> 853 <bitOffset>1</bitOffset> 854 <bitWidth>1</bitWidth> 855 <enumeratedValues> 856 <enumeratedValue> 857 <name>dis</name> 858 <description>Interrupt is disabled.</description> 859 <value>0</value> 860 </enumeratedValue> 861 <enumeratedValue> 862 <name>en</name> 863 <description>Interrupt is enabled.</description> 864 <value>1</value> 865 </enumeratedValue> 866 </enumeratedValues> 867 </field> 868 <field> 869 <name>RX_THD</name> 870 <description>RX FIFO Threshold Crossed interrupt enable.</description> 871 <bitOffset>2</bitOffset> 872 <bitWidth>1</bitWidth> 873 <enumeratedValues> 874 <enumeratedValue> 875 <name>dis</name> 876 <description>Interrupt is disabled.</description> 877 <value>0</value> 878 </enumeratedValue> 879 <enumeratedValue> 880 <name>en</name> 881 <description>Interrupt is enabled.</description> 882 <value>1</value> 883 </enumeratedValue> 884 </enumeratedValues> 885 </field> 886 <field> 887 <name>RX_FULL</name> 888 <description>RX FIFO FULL interrupt enable.</description> 889 <bitOffset>3</bitOffset> 890 <bitWidth>1</bitWidth> 891 <enumeratedValues> 892 <enumeratedValue> 893 <name>dis</name> 894 <description>Interrupt is disabled.</description> 895 <value>0</value> 896 </enumeratedValue> 897 <enumeratedValue> 898 <name>en</name> 899 <description>Interrupt is enabled.</description> 900 <value>1</value> 901 </enumeratedValue> 902 </enumeratedValues> 903 </field> 904 <field> 905 <name>SSA</name> 906 <description>Slave Select Asserted interrupt enable.</description> 907 <bitOffset>4</bitOffset> 908 <bitWidth>1</bitWidth> 909 <enumeratedValues> 910 <enumeratedValue> 911 <name>dis</name> 912 <description>Interrupt is disabled.</description> 913 <value>0</value> 914 </enumeratedValue> 915 <enumeratedValue> 916 <name>en</name> 917 <description>Interrupt is enabled.</description> 918 <value>1</value> 919 </enumeratedValue> 920 </enumeratedValues> 921 </field> 922 <field> 923 <name>SSD</name> 924 <description>Slave Select Deasserted interrupt enable.</description> 925 <bitOffset>5</bitOffset> 926 <bitWidth>1</bitWidth> 927 <enumeratedValues> 928 <enumeratedValue> 929 <name>dis</name> 930 <description>Interrupt is disabled.</description> 931 <value>0</value> 932 </enumeratedValue> 933 <enumeratedValue> 934 <name>en</name> 935 <description>Interrupt is enabled.</description> 936 <value>1</value> 937 </enumeratedValue> 938 </enumeratedValues> 939 </field> 940 <field> 941 <name>FAULT</name> 942 <description>Multi-Master Mode Fault interrupt enable.</description> 943 <bitOffset>8</bitOffset> 944 <bitWidth>1</bitWidth> 945 <enumeratedValues> 946 <enumeratedValue> 947 <name>dis</name> 948 <description>Interrupt is disabled.</description> 949 <value>0</value> 950 </enumeratedValue> 951 <enumeratedValue> 952 <name>en</name> 953 <description>Interrupt is enabled.</description> 954 <value>1</value> 955 </enumeratedValue> 956 </enumeratedValues> 957 </field> 958 <field> 959 <name>ABORT</name> 960 <description>Slave Abort Detected interrupt enable.</description> 961 <bitOffset>9</bitOffset> 962 <bitWidth>1</bitWidth> 963 <enumeratedValues> 964 <enumeratedValue> 965 <name>dis</name> 966 <description>Interrupt is disabled.</description> 967 <value>0</value> 968 </enumeratedValue> 969 <enumeratedValue> 970 <name>en</name> 971 <description>Interrupt is enabled.</description> 972 <value>1</value> 973 </enumeratedValue> 974 </enumeratedValues> 975 </field> 976 <field> 977 <name>MST_DONE</name> 978 <description>Master Done interrupt enable.</description> 979 <bitOffset>11</bitOffset> 980 <bitWidth>1</bitWidth> 981 <enumeratedValues> 982 <enumeratedValue> 983 <name>dis</name> 984 <description>Interrupt is disabled.</description> 985 <value>0</value> 986 </enumeratedValue> 987 <enumeratedValue> 988 <name>en</name> 989 <description>Interrupt is enabled.</description> 990 <value>1</value> 991 </enumeratedValue> 992 </enumeratedValues> 993 </field> 994 <field> 995 <name>TX_OV</name> 996 <description>Transmit FIFO Overrun interrupt enable.</description> 997 <bitOffset>12</bitOffset> 998 <bitWidth>1</bitWidth> 999 <enumeratedValues> 1000 <enumeratedValue> 1001 <name>dis</name> 1002 <description>Interrupt is disabled.</description> 1003 <value>0</value> 1004 </enumeratedValue> 1005 <enumeratedValue> 1006 <name>en</name> 1007 <description>Interrupt is enabled.</description> 1008 <value>1</value> 1009 </enumeratedValue> 1010 </enumeratedValues> 1011 </field> 1012 <field> 1013 <name>TX_UN</name> 1014 <description>Transmit FIFO Underrun interrupt enable.</description> 1015 <bitOffset>13</bitOffset> 1016 <bitWidth>1</bitWidth> 1017 <enumeratedValues> 1018 <enumeratedValue> 1019 <name>dis</name> 1020 <description>Interrupt is disabled.</description> 1021 <value>0</value> 1022 </enumeratedValue> 1023 <enumeratedValue> 1024 <name>en</name> 1025 <description>Interrupt is enabled.</description> 1026 <value>1</value> 1027 </enumeratedValue> 1028 </enumeratedValues> 1029 </field> 1030 <field> 1031 <name>RX_OV</name> 1032 <description>Receive FIFO Overrun interrupt enable.</description> 1033 <bitOffset>14</bitOffset> 1034 <bitWidth>1</bitWidth> 1035 <enumeratedValues> 1036 <enumeratedValue> 1037 <name>dis</name> 1038 <description>Interrupt is disabled.</description> 1039 <value>0</value> 1040 </enumeratedValue> 1041 <enumeratedValue> 1042 <name>en</name> 1043 <description>Interrupt is enabled.</description> 1044 <value>1</value> 1045 </enumeratedValue> 1046 </enumeratedValues> 1047 </field> 1048 <field> 1049 <name>RX_UN</name> 1050 <description>Receive FIFO Underrun interrupt enable.</description> 1051 <bitOffset>15</bitOffset> 1052 <bitWidth>1</bitWidth> 1053 <enumeratedValues> 1054 <enumeratedValue> 1055 <name>dis</name> 1056 <description>Interrupt is disabled.</description> 1057 <value>0</value> 1058 </enumeratedValue> 1059 <enumeratedValue> 1060 <name>en</name> 1061 <description>Interrupt is enabled.</description> 1062 <value>1</value> 1063 </enumeratedValue> 1064 </enumeratedValues> 1065 </field> 1066 </fields> 1067 </register> 1068 <register> 1069 <name>WKFL</name> 1070 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1071 <addressOffset>0x28</addressOffset> 1072 <access>read-write</access> 1073 <fields> 1074 <field> 1075 <name>TX_THD</name> 1076 <description>Wake on TX FIFO Threshold Crossed.</description> 1077 <bitOffset>0</bitOffset> 1078 <bitWidth>1</bitWidth> 1079 <enumeratedValues> 1080 <enumeratedValue> 1081 <name>clear</name> 1082 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1083 <value>1</value> 1084 </enumeratedValue> 1085 </enumeratedValues> 1086 </field> 1087 <field> 1088 <name>TX_EM</name> 1089 <description>Wake on TX FIFO Empty.</description> 1090 <bitOffset>1</bitOffset> 1091 <bitWidth>1</bitWidth> 1092 <enumeratedValues> 1093 <enumeratedValue> 1094 <name>clear</name> 1095 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1096 <value>1</value> 1097 </enumeratedValue> 1098 </enumeratedValues> 1099 </field> 1100 <field> 1101 <name>RX_THD</name> 1102 <description>Wake on RX FIFO Threshold Crossed.</description> 1103 <bitOffset>2</bitOffset> 1104 <bitWidth>1</bitWidth> 1105 <enumeratedValues> 1106 <enumeratedValue> 1107 <name>clear</name> 1108 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1109 <value>1</value> 1110 </enumeratedValue> 1111 </enumeratedValues> 1112 </field> 1113 <field> 1114 <name>RX_FULL</name> 1115 <description>Wake on RX FIFO Full.</description> 1116 <bitOffset>3</bitOffset> 1117 <bitWidth>1</bitWidth> 1118 <enumeratedValues> 1119 <enumeratedValue> 1120 <name>clear</name> 1121 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1122 <value>1</value> 1123 </enumeratedValue> 1124 </enumeratedValues> 1125 </field> 1126 </fields> 1127 </register> 1128 <register> 1129 <name>WKEN</name> 1130 <description>Register for wake up enable.</description> 1131 <addressOffset>0x2C</addressOffset> 1132 <access>read-write</access> 1133 <fields> 1134 <field> 1135 <name>TX_THD</name> 1136 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1137 <bitOffset>0</bitOffset> 1138 <bitWidth>1</bitWidth> 1139 <enumeratedValues> 1140 <enumeratedValue> 1141 <name>dis</name> 1142 <description>Wakeup source disabled.</description> 1143 <value>0</value> 1144 </enumeratedValue> 1145 <enumeratedValue> 1146 <name>en</name> 1147 <description>Wakeup source enabled.</description> 1148 <value>1</value> 1149 </enumeratedValue> 1150 </enumeratedValues> 1151 </field> 1152 <field> 1153 <name>TX_EM</name> 1154 <description>Wake on TX FIFO Empty Enable.</description> 1155 <bitOffset>1</bitOffset> 1156 <bitWidth>1</bitWidth> 1157 <enumeratedValues> 1158 <enumeratedValue> 1159 <name>dis</name> 1160 <description>Wakeup source disabled.</description> 1161 <value>0</value> 1162 </enumeratedValue> 1163 <enumeratedValue> 1164 <name>en</name> 1165 <description>Wakeup source enabled.</description> 1166 <value>1</value> 1167 </enumeratedValue> 1168 </enumeratedValues> 1169 </field> 1170 <field> 1171 <name>RX_THD</name> 1172 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1173 <bitOffset>2</bitOffset> 1174 <bitWidth>1</bitWidth> 1175 <enumeratedValues> 1176 <enumeratedValue> 1177 <name>dis</name> 1178 <description>Wakeup source disabled.</description> 1179 <value>0</value> 1180 </enumeratedValue> 1181 <enumeratedValue> 1182 <name>en</name> 1183 <description>Wakeup source enabled.</description> 1184 <value>1</value> 1185 </enumeratedValue> 1186 </enumeratedValues> 1187 </field> 1188 <field> 1189 <name>RX_FULL</name> 1190 <description>Wake on RX FIFO Full Enable.</description> 1191 <bitOffset>3</bitOffset> 1192 <bitWidth>1</bitWidth> 1193 <enumeratedValues> 1194 <enumeratedValue> 1195 <name>dis</name> 1196 <description>Wakeup source disabled.</description> 1197 <value>0</value> 1198 </enumeratedValue> 1199 <enumeratedValue> 1200 <name>en</name> 1201 <description>Wakeup source enabled.</description> 1202 <value>1</value> 1203 </enumeratedValue> 1204 </enumeratedValues> 1205 </field> 1206 </fields> 1207 </register> 1208 <register> 1209 <name>STATUS</name> 1210 <description>SPI Status register.</description> 1211 <addressOffset>0x30</addressOffset> 1212 <access>read-only</access> 1213 <fields> 1214 <field> 1215 <name>BUSY</name> 1216 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1217 <bitOffset>0</bitOffset> 1218 <bitWidth>1</bitWidth> 1219 <enumeratedValues> 1220 <enumeratedValue> 1221 <name>not</name> 1222 <description>SPI not active.</description> 1223 <value>0</value> 1224 </enumeratedValue> 1225 <enumeratedValue> 1226 <name>active</name> 1227 <description>SPI active.</description> 1228 <value>1</value> 1229 </enumeratedValue> 1230 </enumeratedValues> 1231 </field> 1232 </fields> 1233 </register> 1234 </registers> 1235 </peripheral> 1236 <!-- SPI: Serial Peripheral Interface --> 1237</device>
