1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI0</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x40046000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>FIFO32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>DATA</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>FIFO16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <addressOffset>0x00</addressOffset> 38 <size>16</size> 39 <access>read-write</access> 40 <fields> 41 <field> 42 <name>DATA</name> 43 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 44 <bitOffset>0</bitOffset> 45 <bitWidth>16</bitWidth> 46 </field> 47 </fields> 48 </register> 49 <register> 50 <dim>4</dim> 51 <dimIncrement>1</dimIncrement> 52 <name>FIFO8[%s]</name> 53 <description>Register for reading and writing the FIFO.</description> 54 <addressOffset>0x00</addressOffset> 55 <size>8</size> 56 <access>read-write</access> 57 <fields> 58 <field> 59 <name>DATA</name> 60 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 61 <bitOffset>0</bitOffset> 62 <bitWidth>8</bitWidth> 63 </field> 64 </fields> 65 </register> 66 <register> 67 <name>CTRL0</name> 68 <description>Register for controlling SPI peripheral.</description> 69 <addressOffset>0x04</addressOffset> 70 <access>read-write</access> 71 <fields> 72 <field> 73 <name>EN</name> 74 <description>SPI Enable.</description> 75 <bitOffset>0</bitOffset> 76 <bitWidth>1</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>dis</name> 80 <description>SPI is disabled.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>en</name> 85 <description>SPI is enabled.</description> 86 <value>1</value> 87 </enumeratedValue> 88 </enumeratedValues> 89 </field> 90 <field> 91 <name>MST_MODE</name> 92 <description>Master Mode Enable.</description> 93 <bitOffset>1</bitOffset> 94 <bitWidth>1</bitWidth> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>dis</name> 98 <description>SPI is Slave mode.</description> 99 <value>0</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>en</name> 103 <description>SPI is Master mode.</description> 104 <value>1</value> 105 </enumeratedValue> 106 </enumeratedValues> 107 </field> 108 <field> 109 <name>SS_IO</name> 110 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 111 <bitOffset>4</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>output</name> 116 <description>Slave select 0 is output.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>input</name> 121 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>START</name> 128 <description>Start Transmit.</description> 129 <bitOffset>5</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>start</name> 134 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 135 <value>1</value> 136 </enumeratedValue> 137 </enumeratedValues> 138 </field> 139 <field> 140 <name>SS_CTRL</name> 141 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 142 <bitOffset>8</bitOffset> 143 <bitWidth>1</bitWidth> 144 <enumeratedValues> 145 <enumeratedValue> 146 <name>DEASSERT</name> 147 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 148 <value>0</value> 149 </enumeratedValue> 150 <enumeratedValue> 151 <name>ASSERT</name> 152 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 153 <value>1</value> 154 </enumeratedValue> 155 </enumeratedValues> 156 </field> 157 <field> 158 <name>SS_ACTIVE</name> 159 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 160 <bitOffset>16</bitOffset> 161 <bitWidth>4</bitWidth> 162 <enumeratedValues> 163 <enumeratedValue> 164 <name>SS0</name> 165 <description>SS0 is selected.</description> 166 <value>0x1</value> 167 </enumeratedValue> 168 <enumeratedValue> 169 <name>SS1</name> 170 <description>SS1 is selected.</description> 171 <value>0x2</value> 172 </enumeratedValue> 173 <enumeratedValue> 174 <name>SS2</name> 175 <description>SS2 is selected.</description> 176 <value>0x4</value> 177 </enumeratedValue> 178 <enumeratedValue> 179 <name>SS3</name> 180 <description>SS3 is selected.</description> 181 <value>0x8</value> 182 </enumeratedValue> 183 </enumeratedValues> 184 </field> 185 </fields> 186 </register> 187 <register> 188 <name>CTRL1</name> 189 <description>Register for controlling SPI peripheral.</description> 190 <addressOffset>0x08</addressOffset> 191 <access>read-write</access> 192 <fields> 193 <field> 194 <name>TX_NUM_CHAR</name> 195 <description>Nubmer of Characters to transmit.</description> 196 <bitOffset>0</bitOffset> 197 <bitWidth>16</bitWidth> 198 </field> 199 <field> 200 <name>RX_NUM_CHAR</name> 201 <description>Nubmer of Characters to receive.</description> 202 <bitOffset>16</bitOffset> 203 <bitWidth>16</bitWidth> 204 </field> 205 </fields> 206 </register> 207 <register> 208 <name>CTRL2</name> 209 <description>Register for controlling SPI peripheral.</description> 210 <addressOffset>0x0C</addressOffset> 211 <access>read-write</access> 212 <fields> 213 <field> 214 <name>CLKPHA</name> 215 <description>Clock Phase.</description> 216 <bitOffset>0</bitOffset> 217 <bitWidth>1</bitWidth> 218 <enumeratedValues> 219 <enumeratedValue> 220 <name>Rising_Edge</name> 221 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 222 <value>0</value> 223 </enumeratedValue> 224 <enumeratedValue> 225 <name>Falling_Edge</name> 226 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 227 <value>1</value> 228 </enumeratedValue> 229 </enumeratedValues> 230 </field> 231 <field> 232 <name>CLKPOL</name> 233 <description>Clock Polarity.</description> 234 <bitOffset>1</bitOffset> 235 <bitWidth>1</bitWidth> 236 <enumeratedValues> 237 <enumeratedValue> 238 <name>Normal</name> 239 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 240 <value>0</value> 241 </enumeratedValue> 242 <enumeratedValue> 243 <name>Inverted</name> 244 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 245 <value>1</value> 246 </enumeratedValue> 247 </enumeratedValues> 248 </field> 249 <field> 250 <name>NUMBITS</name> 251 <description>Number of Bits per character.</description> 252 <bitOffset>8</bitOffset> 253 <bitWidth>4</bitWidth> 254 <enumeratedValues> 255 <enumeratedValue> 256 <name>16</name> 257 <description>16 bits per character.</description> 258 <value>0</value> 259 </enumeratedValue> 260 <enumeratedValue> 261 <name>1</name> 262 <description>1 bits per character.</description> 263 <value>1</value> 264 </enumeratedValue> 265 <enumeratedValue> 266 <name>2</name> 267 <description>2 bits per character.</description> 268 <value>2</value> 269 </enumeratedValue> 270 <enumeratedValue> 271 <name>3</name> 272 <description>3 bits per character.</description> 273 <value>3</value> 274 </enumeratedValue> 275 <enumeratedValue> 276 <name>4</name> 277 <description>4 bits per character.</description> 278 <value>4</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>5</name> 282 <description>5 bits per character.</description> 283 <value>5</value> 284 </enumeratedValue> 285 <enumeratedValue> 286 <name>6</name> 287 <description>6 bits per character.</description> 288 <value>6</value> 289 </enumeratedValue> 290 <enumeratedValue> 291 <name>7</name> 292 <description>7 bits per character.</description> 293 <value>7</value> 294 </enumeratedValue> 295 <enumeratedValue> 296 <name>8</name> 297 <description>8 bits per character.</description> 298 <value>8</value> 299 </enumeratedValue> 300 <enumeratedValue> 301 <name>9</name> 302 <description>9 bits per character.</description> 303 <value>9</value> 304 </enumeratedValue> 305 <enumeratedValue> 306 <name>10</name> 307 <description>10 bits per character.</description> 308 <value>10</value> 309 </enumeratedValue> 310 <enumeratedValue> 311 <name>11</name> 312 <description>11 bits per character.</description> 313 <value>11</value> 314 </enumeratedValue> 315 <enumeratedValue> 316 <name>12</name> 317 <description>12 bits per character.</description> 318 <value>12</value> 319 </enumeratedValue> 320 <enumeratedValue> 321 <name>13</name> 322 <description>13 bits per character.</description> 323 <value>13</value> 324 </enumeratedValue> 325 <enumeratedValue> 326 <name>14</name> 327 <description>14 bits per character.</description> 328 <value>14</value> 329 </enumeratedValue> 330 <enumeratedValue> 331 <name>15</name> 332 <description>15 bits per character.</description> 333 <value>15</value> 334 </enumeratedValue> 335 </enumeratedValues> 336 </field> 337 <field> 338 <name>DATA_WIDTH</name> 339 <description>SPI Data width.</description> 340 <bitOffset>12</bitOffset> 341 <bitWidth>2</bitWidth> 342 <enumeratedValues> 343 <enumeratedValue> 344 <name>Mono</name> 345 <description>1 data pin.</description> 346 <value>0</value> 347 </enumeratedValue> 348 <enumeratedValue> 349 <name>Dual</name> 350 <description>2 data pins.</description> 351 <value>1</value> 352 </enumeratedValue> 353 <enumeratedValue> 354 <name>Quad</name> 355 <description>4 data pins.</description> 356 <value>2</value> 357 </enumeratedValue> 358 </enumeratedValues> 359 </field> 360 <field> 361 <name>THREE_WIRE</name> 362 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 363 <bitOffset>15</bitOffset> 364 <bitWidth>1</bitWidth> 365 <enumeratedValues> 366 <enumeratedValue> 367 <name>dis</name> 368 <description>Use four wire mode (Mono only).</description> 369 <value>0</value> 370 </enumeratedValue> 371 <enumeratedValue> 372 <name>en</name> 373 <description>Use three wire mode.</description> 374 <value>1</value> 375 </enumeratedValue> 376 </enumeratedValues> 377 </field> 378 <field> 379 <name>SS_POL</name> 380 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 381 <bitOffset>16</bitOffset> 382 <bitWidth>8</bitWidth> 383 <enumeratedValues> 384 <enumeratedValue> 385 <name>SS0_high</name> 386 <description>SS0 active high.</description> 387 <value>0x1</value> 388 </enumeratedValue> 389 <enumeratedValue> 390 <name>SS1_high</name> 391 <description>SS1 active high.</description> 392 <value>0x2</value> 393 </enumeratedValue> 394 <enumeratedValue> 395 <name>SS2_high</name> 396 <description>SS2 active high.</description> 397 <value>0x4</value> 398 </enumeratedValue> 399 <enumeratedValue> 400 <name>SS3_high</name> 401 <description>SS3 active high.</description> 402 <value>0x8</value> 403 </enumeratedValue> 404 </enumeratedValues> 405 </field> 406 </fields> 407 </register> 408 <register> 409 <name>SSTIME</name> 410 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 411 <addressOffset>0x10</addressOffset> 412 <access>read-write</access> 413 <fields> 414 <field> 415 <name>PRE</name> 416 <description>Slave Select Pre delay 1.</description> 417 <bitOffset>0</bitOffset> 418 <bitWidth>8</bitWidth> 419 <enumeratedValues> 420 <enumeratedValue> 421 <name>256</name> 422 <description>256 system clocks between SS active and first serial clock edge.</description> 423 <value>0</value> 424 </enumeratedValue> 425 </enumeratedValues> 426 </field> 427 <field> 428 <name>POST</name> 429 <description>Slave Select Post delay 2.</description> 430 <bitOffset>8</bitOffset> 431 <bitWidth>8</bitWidth> 432 <enumeratedValues> 433 <enumeratedValue> 434 <name>256</name> 435 <description>256 system clocks between last serial clock edge and SS inactive.</description> 436 <value>0</value> 437 </enumeratedValue> 438 </enumeratedValues> 439 </field> 440 <field> 441 <name>INACT</name> 442 <description>Slave Select Inactive delay.</description> 443 <bitOffset>16</bitOffset> 444 <bitWidth>8</bitWidth> 445 <enumeratedValues> 446 <enumeratedValue> 447 <name>256</name> 448 <description>256 system clocks between transactions.</description> 449 <value>0</value> 450 </enumeratedValue> 451 </enumeratedValues> 452 </field> 453 </fields> 454 </register> 455 <register> 456 <name>CLKCTRL</name> 457 <description>Register for controlling SPI clock rate.</description> 458 <addressOffset>0x14</addressOffset> 459 <access>read-write</access> 460 <fields> 461 <field> 462 <name>LO</name> 463 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 464 <bitOffset>0</bitOffset> 465 <bitWidth>8</bitWidth> 466 <enumeratedValues> 467 <enumeratedValue> 468 <name>Dis</name> 469 <description>Duty cycle control of serial clock generation is disabled.</description> 470 <value>0</value> 471 </enumeratedValue> 472 </enumeratedValues> 473 </field> 474 <field> 475 <name>HI</name> 476 <description>High duty cycle control. In timer mode, reload[15:8].</description> 477 <bitOffset>8</bitOffset> 478 <bitWidth>8</bitWidth> 479 <enumeratedValues> 480 <enumeratedValue> 481 <name>Dis</name> 482 <description>Duty cycle control of serial clock generation is disabled.</description> 483 <value>0</value> 484 </enumeratedValue> 485 </enumeratedValues> 486 </field> 487 <field> 488 <name>CLKDIV</name> 489 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 490 <bitOffset>16</bitOffset> 491 <bitWidth>4</bitWidth> 492 </field> 493 </fields> 494 </register> 495 <register> 496 <name>DMA</name> 497 <description>Register for controlling DMA.</description> 498 <addressOffset>0x1C</addressOffset> 499 <access>read-write</access> 500 <fields> 501 <field> 502 <name>TX_THD_VAL</name> 503 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 504 <bitOffset>0</bitOffset> 505 <bitWidth>5</bitWidth> 506 </field> 507 <field> 508 <name>TX_FIFO_EN</name> 509 <description>Transmit FIFO enabled for SPI transactions.</description> 510 <bitOffset>6</bitOffset> 511 <bitWidth>1</bitWidth> 512 <enumeratedValues> 513 <enumeratedValue> 514 <name>dis</name> 515 <description>Transmit FIFO is not enabled.</description> 516 <value>0</value> 517 </enumeratedValue> 518 <enumeratedValue> 519 <name>en</name> 520 <description>Transmit FIFO is enabled.</description> 521 <value>1</value> 522 </enumeratedValue> 523 </enumeratedValues> 524 </field> 525 <field> 526 <name>TX_FLUSH</name> 527 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 528 <bitOffset>7</bitOffset> 529 <bitWidth>1</bitWidth> 530 <enumeratedValues> 531 <enumeratedValue> 532 <name>CLEAR</name> 533 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 534 <value>1</value> 535 </enumeratedValue> 536 </enumeratedValues> 537 </field> 538 <field> 539 <name>TX_LVL</name> 540 <description>Count of entries in TX FIFO.</description> 541 <bitOffset>8</bitOffset> 542 <bitWidth>6</bitWidth> 543 <access>read-only</access> 544 </field> 545 <field> 546 <name>DMA_TX_EN</name> 547 <description>TX DMA Enable.</description> 548 <bitOffset>15</bitOffset> 549 <bitWidth>1</bitWidth> 550 <enumeratedValues> 551 <enumeratedValue> 552 <name>DIS</name> 553 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 554 <value>0</value> 555 </enumeratedValue> 556 <enumeratedValue> 557 <name>en</name> 558 <description>TX DMA requests are enabled.</description> 559 <value>1</value> 560 </enumeratedValue> 561 </enumeratedValues> 562 </field> 563 <field> 564 <name>RX_THD_VAL</name> 565 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 566 <bitOffset>16</bitOffset> 567 <bitWidth>5</bitWidth> 568 </field> 569 <field> 570 <name>RX_FIFO_EN</name> 571 <description>Receive FIFO enabled for SPI transactions.</description> 572 <bitOffset>22</bitOffset> 573 <bitWidth>1</bitWidth> 574 <enumeratedValues> 575 <enumeratedValue> 576 <name>DIS</name> 577 <description>Receive FIFO is not enabled.</description> 578 <value>0</value> 579 </enumeratedValue> 580 <enumeratedValue> 581 <name>en</name> 582 <description>Receive FIFO is enabled.</description> 583 <value>1</value> 584 </enumeratedValue> 585 </enumeratedValues> 586 </field> 587 <field> 588 <name>RX_FLUSH</name> 589 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 590 <bitOffset>23</bitOffset> 591 <bitWidth>1</bitWidth> 592 <enumeratedValues> 593 <enumeratedValue> 594 <name>CLEAR</name> 595 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 596 <value>1</value> 597 </enumeratedValue> 598 </enumeratedValues> 599 </field> 600 <field> 601 <name>RX_LVL</name> 602 <description>Count of entries in RX FIFO.</description> 603 <bitOffset>24</bitOffset> 604 <bitWidth>6</bitWidth> 605 <access>read-only</access> 606 </field> 607 <field> 608 <name>DMA_RX_EN</name> 609 <description>RX DMA Enable.</description> 610 <bitOffset>31</bitOffset> 611 <bitWidth>1</bitWidth> 612 <enumeratedValues> 613 <enumeratedValue> 614 <name>dis</name> 615 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 616 <value>0</value> 617 </enumeratedValue> 618 <enumeratedValue> 619 <name>en</name> 620 <description>RX DMA requests are enabled.</description> 621 <value>1</value> 622 </enumeratedValue> 623 </enumeratedValues> 624 </field> 625 </fields> 626 </register> 627 <register> 628 <name>INTFL</name> 629 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 630 <addressOffset>0x20</addressOffset> 631 <access>read-write</access> 632 <fields> 633 <field> 634 <name>TX_THD</name> 635 <description>TX FIFO Threshold Crossed.</description> 636 <bitOffset>0</bitOffset> 637 <bitWidth>1</bitWidth> 638 <enumeratedValues> 639 <enumeratedValue> 640 <name>clear</name> 641 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 642 <value>1</value> 643 </enumeratedValue> 644 </enumeratedValues> 645 </field> 646 <field> 647 <name>TX_EM</name> 648 <description>TX FIFO Empty.</description> 649 <bitOffset>1</bitOffset> 650 <bitWidth>1</bitWidth> 651 <enumeratedValues> 652 <enumeratedValue> 653 <name>clear</name> 654 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 655 <value>1</value> 656 </enumeratedValue> 657 </enumeratedValues> 658 </field> 659 <field> 660 <name>RX_THD</name> 661 <description>RX FIFO Threshold Crossed.</description> 662 <bitOffset>2</bitOffset> 663 <bitWidth>1</bitWidth> 664 <enumeratedValues> 665 <enumeratedValue> 666 <name>clear</name> 667 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 668 <value>1</value> 669 </enumeratedValue> 670 </enumeratedValues> 671 </field> 672 <field> 673 <name>RX_FULL</name> 674 <description>RX FIFO FULL.</description> 675 <bitOffset>3</bitOffset> 676 <bitWidth>1</bitWidth> 677 <enumeratedValues> 678 <enumeratedValue> 679 <name>clear</name> 680 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 681 <value>1</value> 682 </enumeratedValue> 683 </enumeratedValues> 684 </field> 685 <field> 686 <name>SSA</name> 687 <description>Slave Select Asserted.</description> 688 <bitOffset>4</bitOffset> 689 <bitWidth>1</bitWidth> 690 <enumeratedValues> 691 <enumeratedValue> 692 <name>clear</name> 693 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 694 <value>1</value> 695 </enumeratedValue> 696 </enumeratedValues> 697 </field> 698 <field> 699 <name>SSD</name> 700 <description>Slave Select Deasserted.</description> 701 <bitOffset>5</bitOffset> 702 <bitWidth>1</bitWidth> 703 <enumeratedValues> 704 <enumeratedValue> 705 <name>clear</name> 706 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 707 <value>1</value> 708 </enumeratedValue> 709 </enumeratedValues> 710 </field> 711 <field> 712 <name>FAULT</name> 713 <description>Multi-Master Mode Fault.</description> 714 <bitOffset>8</bitOffset> 715 <bitWidth>1</bitWidth> 716 <enumeratedValues> 717 <enumeratedValue> 718 <name>clear</name> 719 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 720 <value>1</value> 721 </enumeratedValue> 722 </enumeratedValues> 723 </field> 724 <field> 725 <name>ABORT</name> 726 <description>Slave Abort Detected.</description> 727 <bitOffset>9</bitOffset> 728 <bitWidth>1</bitWidth> 729 <enumeratedValues> 730 <enumeratedValue> 731 <name>clear</name> 732 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 733 <value>1</value> 734 </enumeratedValue> 735 </enumeratedValues> 736 </field> 737 <field> 738 <name>MST_DONE</name> 739 <description>Master Done, set when SPI Master has completed any transactions.</description> 740 <bitOffset>11</bitOffset> 741 <bitWidth>1</bitWidth> 742 <enumeratedValues> 743 <enumeratedValue> 744 <name>clear</name> 745 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 746 <value>1</value> 747 </enumeratedValue> 748 </enumeratedValues> 749 </field> 750 <field> 751 <name>TX_OV</name> 752 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 753 <bitOffset>12</bitOffset> 754 <bitWidth>1</bitWidth> 755 <enumeratedValues> 756 <enumeratedValue> 757 <name>clear</name> 758 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 759 <value>1</value> 760 </enumeratedValue> 761 </enumeratedValues> 762 </field> 763 <field> 764 <name>TX_UN</name> 765 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 766 <bitOffset>13</bitOffset> 767 <bitWidth>1</bitWidth> 768 <enumeratedValues> 769 <enumeratedValue> 770 <name>clear</name> 771 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 772 <value>1</value> 773 </enumeratedValue> 774 </enumeratedValues> 775 </field> 776 <field> 777 <name>RX_OV</name> 778 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 779 <bitOffset>14</bitOffset> 780 <bitWidth>1</bitWidth> 781 <enumeratedValues> 782 <enumeratedValue> 783 <name>clear</name> 784 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 785 <value>1</value> 786 </enumeratedValue> 787 </enumeratedValues> 788 </field> 789 <field> 790 <name>RX_UN</name> 791 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 792 <bitOffset>15</bitOffset> 793 <bitWidth>1</bitWidth> 794 <enumeratedValues> 795 <enumeratedValue> 796 <name>clear</name> 797 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 798 <value>1</value> 799 </enumeratedValue> 800 </enumeratedValues> 801 </field> 802 </fields> 803 </register> 804 <register> 805 <name>INTEN</name> 806 <description>Register for enabling interrupts.</description> 807 <addressOffset>0x24</addressOffset> 808 <access>read-write</access> 809 <fields> 810 <field> 811 <name>TX_THD</name> 812 <description>TX FIFO Threshold interrupt enable.</description> 813 <bitOffset>0</bitOffset> 814 <bitWidth>1</bitWidth> 815 <enumeratedValues> 816 <enumeratedValue> 817 <name>dis</name> 818 <description>Interrupt is disabled.</description> 819 <value>0</value> 820 </enumeratedValue> 821 <enumeratedValue> 822 <name>en</name> 823 <description>Interrupt is enabled.</description> 824 <value>1</value> 825 </enumeratedValue> 826 </enumeratedValues> 827 </field> 828 <field> 829 <name>TX_EM</name> 830 <description>TX FIFO Empty interrupt enable.</description> 831 <bitOffset>1</bitOffset> 832 <bitWidth>1</bitWidth> 833 <enumeratedValues> 834 <enumeratedValue> 835 <name>dis</name> 836 <description>Interrupt is disabled.</description> 837 <value>0</value> 838 </enumeratedValue> 839 <enumeratedValue> 840 <name>en</name> 841 <description>Interrupt is enabled.</description> 842 <value>1</value> 843 </enumeratedValue> 844 </enumeratedValues> 845 </field> 846 <field> 847 <name>RX_THD</name> 848 <description>RX FIFO Threshold Crossed interrupt enable.</description> 849 <bitOffset>2</bitOffset> 850 <bitWidth>1</bitWidth> 851 <enumeratedValues> 852 <enumeratedValue> 853 <name>dis</name> 854 <description>Interrupt is disabled.</description> 855 <value>0</value> 856 </enumeratedValue> 857 <enumeratedValue> 858 <name>en</name> 859 <description>Interrupt is enabled.</description> 860 <value>1</value> 861 </enumeratedValue> 862 </enumeratedValues> 863 </field> 864 <field> 865 <name>RX_FULL</name> 866 <description>RX FIFO FULL interrupt enable.</description> 867 <bitOffset>3</bitOffset> 868 <bitWidth>1</bitWidth> 869 <enumeratedValues> 870 <enumeratedValue> 871 <name>dis</name> 872 <description>Interrupt is disabled.</description> 873 <value>0</value> 874 </enumeratedValue> 875 <enumeratedValue> 876 <name>en</name> 877 <description>Interrupt is enabled.</description> 878 <value>1</value> 879 </enumeratedValue> 880 </enumeratedValues> 881 </field> 882 <field> 883 <name>SSA</name> 884 <description>Slave Select Asserted interrupt enable.</description> 885 <bitOffset>4</bitOffset> 886 <bitWidth>1</bitWidth> 887 <enumeratedValues> 888 <enumeratedValue> 889 <name>dis</name> 890 <description>Interrupt is disabled.</description> 891 <value>0</value> 892 </enumeratedValue> 893 <enumeratedValue> 894 <name>en</name> 895 <description>Interrupt is enabled.</description> 896 <value>1</value> 897 </enumeratedValue> 898 </enumeratedValues> 899 </field> 900 <field> 901 <name>SSD</name> 902 <description>Slave Select Deasserted interrupt enable.</description> 903 <bitOffset>5</bitOffset> 904 <bitWidth>1</bitWidth> 905 <enumeratedValues> 906 <enumeratedValue> 907 <name>dis</name> 908 <description>Interrupt is disabled.</description> 909 <value>0</value> 910 </enumeratedValue> 911 <enumeratedValue> 912 <name>en</name> 913 <description>Interrupt is enabled.</description> 914 <value>1</value> 915 </enumeratedValue> 916 </enumeratedValues> 917 </field> 918 <field> 919 <name>FAULT</name> 920 <description>Multi-Master Mode Fault interrupt enable.</description> 921 <bitOffset>8</bitOffset> 922 <bitWidth>1</bitWidth> 923 <enumeratedValues> 924 <enumeratedValue> 925 <name>dis</name> 926 <description>Interrupt is disabled.</description> 927 <value>0</value> 928 </enumeratedValue> 929 <enumeratedValue> 930 <name>en</name> 931 <description>Interrupt is enabled.</description> 932 <value>1</value> 933 </enumeratedValue> 934 </enumeratedValues> 935 </field> 936 <field> 937 <name>ABORT</name> 938 <description>Slave Abort Detected interrupt enable.</description> 939 <bitOffset>9</bitOffset> 940 <bitWidth>1</bitWidth> 941 <enumeratedValues> 942 <enumeratedValue> 943 <name>dis</name> 944 <description>Interrupt is disabled.</description> 945 <value>0</value> 946 </enumeratedValue> 947 <enumeratedValue> 948 <name>en</name> 949 <description>Interrupt is enabled.</description> 950 <value>1</value> 951 </enumeratedValue> 952 </enumeratedValues> 953 </field> 954 <field> 955 <name>MST_DONE</name> 956 <description>Master Done interrupt enable.</description> 957 <bitOffset>11</bitOffset> 958 <bitWidth>1</bitWidth> 959 <enumeratedValues> 960 <enumeratedValue> 961 <name>dis</name> 962 <description>Interrupt is disabled.</description> 963 <value>0</value> 964 </enumeratedValue> 965 <enumeratedValue> 966 <name>en</name> 967 <description>Interrupt is enabled.</description> 968 <value>1</value> 969 </enumeratedValue> 970 </enumeratedValues> 971 </field> 972 <field> 973 <name>TX_OV</name> 974 <description>Transmit FIFO Overrun interrupt enable.</description> 975 <bitOffset>12</bitOffset> 976 <bitWidth>1</bitWidth> 977 <enumeratedValues> 978 <enumeratedValue> 979 <name>dis</name> 980 <description>Interrupt is disabled.</description> 981 <value>0</value> 982 </enumeratedValue> 983 <enumeratedValue> 984 <name>en</name> 985 <description>Interrupt is enabled.</description> 986 <value>1</value> 987 </enumeratedValue> 988 </enumeratedValues> 989 </field> 990 <field> 991 <name>TX_UN</name> 992 <description>Transmit FIFO Underrun interrupt enable.</description> 993 <bitOffset>13</bitOffset> 994 <bitWidth>1</bitWidth> 995 <enumeratedValues> 996 <enumeratedValue> 997 <name>dis</name> 998 <description>Interrupt is disabled.</description> 999 <value>0</value> 1000 </enumeratedValue> 1001 <enumeratedValue> 1002 <name>en</name> 1003 <description>Interrupt is enabled.</description> 1004 <value>1</value> 1005 </enumeratedValue> 1006 </enumeratedValues> 1007 </field> 1008 <field> 1009 <name>RX_OV</name> 1010 <description>Receive FIFO Overrun interrupt enable.</description> 1011 <bitOffset>14</bitOffset> 1012 <bitWidth>1</bitWidth> 1013 <enumeratedValues> 1014 <enumeratedValue> 1015 <name>dis</name> 1016 <description>Interrupt is disabled.</description> 1017 <value>0</value> 1018 </enumeratedValue> 1019 <enumeratedValue> 1020 <name>en</name> 1021 <description>Interrupt is enabled.</description> 1022 <value>1</value> 1023 </enumeratedValue> 1024 </enumeratedValues> 1025 </field> 1026 <field> 1027 <name>RX_UN</name> 1028 <description>Receive FIFO Underrun interrupt enable.</description> 1029 <bitOffset>15</bitOffset> 1030 <bitWidth>1</bitWidth> 1031 <enumeratedValues> 1032 <enumeratedValue> 1033 <name>dis</name> 1034 <description>Interrupt is disabled.</description> 1035 <value>0</value> 1036 </enumeratedValue> 1037 <enumeratedValue> 1038 <name>en</name> 1039 <description>Interrupt is enabled.</description> 1040 <value>1</value> 1041 </enumeratedValue> 1042 </enumeratedValues> 1043 </field> 1044 </fields> 1045 </register> 1046 <register> 1047 <name>WKFL</name> 1048 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1049 <addressOffset>0x28</addressOffset> 1050 <access>read-write</access> 1051 <fields> 1052 <field> 1053 <name>TX_THD</name> 1054 <description>Wake on TX FIFO Threshold Crossed.</description> 1055 <bitOffset>0</bitOffset> 1056 <bitWidth>1</bitWidth> 1057 <enumeratedValues> 1058 <enumeratedValue> 1059 <name>clear</name> 1060 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1061 <value>1</value> 1062 </enumeratedValue> 1063 </enumeratedValues> 1064 </field> 1065 <field> 1066 <name>TX_EM</name> 1067 <description>Wake on TX FIFO Empty.</description> 1068 <bitOffset>1</bitOffset> 1069 <bitWidth>1</bitWidth> 1070 <enumeratedValues> 1071 <enumeratedValue> 1072 <name>clear</name> 1073 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1074 <value>1</value> 1075 </enumeratedValue> 1076 </enumeratedValues> 1077 </field> 1078 <field> 1079 <name>RX_THD</name> 1080 <description>Wake on RX FIFO Threshold Crossed.</description> 1081 <bitOffset>2</bitOffset> 1082 <bitWidth>1</bitWidth> 1083 <enumeratedValues> 1084 <enumeratedValue> 1085 <name>clear</name> 1086 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1087 <value>1</value> 1088 </enumeratedValue> 1089 </enumeratedValues> 1090 </field> 1091 <field> 1092 <name>RX_FULL</name> 1093 <description>Wake on RX FIFO Full.</description> 1094 <bitOffset>3</bitOffset> 1095 <bitWidth>1</bitWidth> 1096 <enumeratedValues> 1097 <enumeratedValue> 1098 <name>clear</name> 1099 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1100 <value>1</value> 1101 </enumeratedValue> 1102 </enumeratedValues> 1103 </field> 1104 </fields> 1105 </register> 1106 <register> 1107 <name>WKEN</name> 1108 <description>Register for wake up enable.</description> 1109 <addressOffset>0x2C</addressOffset> 1110 <access>read-write</access> 1111 <fields> 1112 <field> 1113 <name>TX_THD</name> 1114 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1115 <bitOffset>0</bitOffset> 1116 <bitWidth>1</bitWidth> 1117 <enumeratedValues> 1118 <enumeratedValue> 1119 <name>dis</name> 1120 <description>Wakeup source disabled.</description> 1121 <value>0</value> 1122 </enumeratedValue> 1123 <enumeratedValue> 1124 <name>en</name> 1125 <description>Wakeup source enabled.</description> 1126 <value>1</value> 1127 </enumeratedValue> 1128 </enumeratedValues> 1129 </field> 1130 <field> 1131 <name>TX_EM</name> 1132 <description>Wake on TX FIFO Empty Enable.</description> 1133 <bitOffset>1</bitOffset> 1134 <bitWidth>1</bitWidth> 1135 <enumeratedValues> 1136 <enumeratedValue> 1137 <name>dis</name> 1138 <description>Wakeup source disabled.</description> 1139 <value>0</value> 1140 </enumeratedValue> 1141 <enumeratedValue> 1142 <name>en</name> 1143 <description>Wakeup source enabled.</description> 1144 <value>1</value> 1145 </enumeratedValue> 1146 </enumeratedValues> 1147 </field> 1148 <field> 1149 <name>RX_THD</name> 1150 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1151 <bitOffset>2</bitOffset> 1152 <bitWidth>1</bitWidth> 1153 <enumeratedValues> 1154 <enumeratedValue> 1155 <name>dis</name> 1156 <description>Wakeup source disabled.</description> 1157 <value>0</value> 1158 </enumeratedValue> 1159 <enumeratedValue> 1160 <name>en</name> 1161 <description>Wakeup source enabled.</description> 1162 <value>1</value> 1163 </enumeratedValue> 1164 </enumeratedValues> 1165 </field> 1166 <field> 1167 <name>RX_FULL</name> 1168 <description>Wake on RX FIFO Full Enable.</description> 1169 <bitOffset>3</bitOffset> 1170 <bitWidth>1</bitWidth> 1171 <enumeratedValues> 1172 <enumeratedValue> 1173 <name>dis</name> 1174 <description>Wakeup source disabled.</description> 1175 <value>0</value> 1176 </enumeratedValue> 1177 <enumeratedValue> 1178 <name>en</name> 1179 <description>Wakeup source enabled.</description> 1180 <value>1</value> 1181 </enumeratedValue> 1182 </enumeratedValues> 1183 </field> 1184 </fields> 1185 </register> 1186 <register> 1187 <name>STAT</name> 1188 <description>SPI Status register.</description> 1189 <addressOffset>0x30</addressOffset> 1190 <access>read-only</access> 1191 <fields> 1192 <field> 1193 <name>BUSY</name> 1194 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1195 <bitOffset>0</bitOffset> 1196 <bitWidth>1</bitWidth> 1197 <enumeratedValues> 1198 <enumeratedValue> 1199 <name>not</name> 1200 <description>SPI not active.</description> 1201 <value>0</value> 1202 </enumeratedValue> 1203 <enumeratedValue> 1204 <name>active</name> 1205 <description>SPI active.</description> 1206 <value>1</value> 1207 </enumeratedValue> 1208 </enumeratedValues> 1209 </field> 1210 </fields> 1211 </register> 1212 </registers> 1213 </peripheral> 1214 <!-- SPI: Serial Peripheral Interface --> 1215</device>
