1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x400BE000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>DATA32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>QSPIFIFO</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>DATA16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <alternateRegister>DATA32</alternateRegister> 38 <addressOffset>0x00</addressOffset> 39 <size>16</size> 40 <access>read-write</access> 41 <fields> 42 <field> 43 <name>QSPIFIFO</name> 44 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 45 <bitOffset>0</bitOffset> 46 <bitWidth>16</bitWidth> 47 </field> 48 </fields> 49 </register> 50 <register> 51 <dim>4</dim> 52 <dimIncrement>1</dimIncrement> 53 <name>DATA8[%s]</name> 54 <description>Register for reading and writing the FIFO.</description> 55 <alternateRegister>DATA32</alternateRegister> 56 <addressOffset>0x00</addressOffset> 57 <size>8</size> 58 <access>read-write</access> 59 <fields> 60 <field> 61 <name>QSPIFIFO</name> 62 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 63 <bitOffset>0</bitOffset> 64 <bitWidth>8</bitWidth> 65 </field> 66 </fields> 67 </register> 68 <register> 69 <name>CTRL0</name> 70 <description>Register for controlling SPI peripheral.</description> 71 <addressOffset>0x04</addressOffset> 72 <access>read-write</access> 73 <fields> 74 <field> 75 <name>EN</name> 76 <description>SPI Enable.</description> 77 <bitOffset>0</bitOffset> 78 <bitWidth>1</bitWidth> 79 <enumeratedValues> 80 <enumeratedValue> 81 <name>dis</name> 82 <description>SPI is disabled.</description> 83 <value>0</value> 84 </enumeratedValue> 85 <enumeratedValue> 86 <name>en</name> 87 <description>SPI is enabled.</description> 88 <value>1</value> 89 </enumeratedValue> 90 </enumeratedValues> 91 </field> 92 <field> 93 <name>MASTER</name> 94 <description>Master Mode Enable.</description> 95 <bitOffset>1</bitOffset> 96 <bitWidth>1</bitWidth> 97 <enumeratedValues> 98 <enumeratedValue> 99 <name>dis</name> 100 <description>SPI is Slave mode.</description> 101 <value>0</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>en</name> 105 <description>SPI is Master mode.</description> 106 <value>1</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 <field> 111 <name>SS_IO</name> 112 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 113 <bitOffset>4</bitOffset> 114 <bitWidth>1</bitWidth> 115 <enumeratedValues> 116 <enumeratedValue> 117 <name>output</name> 118 <description>Slave select 0 is output.</description> 119 <value>0</value> 120 </enumeratedValue> 121 <enumeratedValue> 122 <name>input</name> 123 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 124 <value>1</value> 125 </enumeratedValue> 126 </enumeratedValues> 127 </field> 128 <field> 129 <name>START</name> 130 <description>Start Transmit.</description> 131 <bitOffset>5</bitOffset> 132 <bitWidth>1</bitWidth> 133 <enumeratedValues> 134 <enumeratedValue> 135 <name>start</name> 136 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 137 <value>1</value> 138 </enumeratedValue> 139 </enumeratedValues> 140 </field> 141 <field> 142 <name>SS_CTRL</name> 143 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 144 <bitOffset>8</bitOffset> 145 <bitWidth>1</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>DEASSERT</name> 149 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>ASSERT</name> 154 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 155 <value>1</value> 156 </enumeratedValue> 157 </enumeratedValues> 158 </field> 159 <field> 160 <name>SS</name> 161 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 162 <bitOffset>16</bitOffset> 163 <bitWidth>4</bitWidth> 164 <enumeratedValues> 165 <enumeratedValue> 166 <name>SS0</name> 167 <description>SS0 is selected.</description> 168 <value>0x1</value> 169 </enumeratedValue> 170 <enumeratedValue> 171 <name>SS1</name> 172 <description>SS1 is selected.</description> 173 <value>0x2</value> 174 </enumeratedValue> 175 <enumeratedValue> 176 <name>SS2</name> 177 <description>SS2 is selected.</description> 178 <value>0x4</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>SS3</name> 182 <description>SS3 is selected.</description> 183 <value>0x8</value> 184 </enumeratedValue> 185 </enumeratedValues> 186 </field> 187 </fields> 188 </register> 189 <register> 190 <name>CTRL1</name> 191 <description>Register for controlling SPI peripheral.</description> 192 <addressOffset>0x08</addressOffset> 193 <access>read-write</access> 194 <fields> 195 <field> 196 <name>TX_NUM_CHAR</name> 197 <description>Nubmer of Characters to transmit.</description> 198 <bitOffset>0</bitOffset> 199 <bitWidth>16</bitWidth> 200 </field> 201 <field> 202 <name>RX_NUM_CHAR</name> 203 <description>Nubmer of Characters to receive.</description> 204 <bitOffset>16</bitOffset> 205 <bitWidth>16</bitWidth> 206 </field> 207 </fields> 208 </register> 209 <register> 210 <name>CTRL2</name> 211 <description>Register for controlling SPI peripheral.</description> 212 <addressOffset>0x0C</addressOffset> 213 <access>read-write</access> 214 <fields> 215 <field> 216 <name>CPHA</name> 217 <description>Clock Phase.</description> 218 <bitOffset>0</bitOffset> 219 <bitWidth>1</bitWidth> 220 <enumeratedValues> 221 <enumeratedValue> 222 <name>Rising_Edge</name> 223 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 224 <value>0</value> 225 </enumeratedValue> 226 <enumeratedValue> 227 <name>Falling_Edge</name> 228 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 229 <value>1</value> 230 </enumeratedValue> 231 </enumeratedValues> 232 </field> 233 <field> 234 <name>CPOL</name> 235 <description>Clock Polarity.</description> 236 <bitOffset>1</bitOffset> 237 <bitWidth>1</bitWidth> 238 <enumeratedValues> 239 <enumeratedValue> 240 <name>Normal</name> 241 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 242 <value>0</value> 243 </enumeratedValue> 244 <enumeratedValue> 245 <name>Inverted</name> 246 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 247 <value>1</value> 248 </enumeratedValue> 249 </enumeratedValues> 250 </field> 251 <field> 252 <name>NUMBITS</name> 253 <description>Number of Bits per character.</description> 254 <bitOffset>8</bitOffset> 255 <bitWidth>4</bitWidth> 256 <enumeratedValues> 257 <enumeratedValue> 258 <name>0</name> 259 <description>16 bits per character.</description> 260 <value>0</value> 261 </enumeratedValue> 262 </enumeratedValues> 263 </field> 264 <field> 265 <name>DATA_WIDTH</name> 266 <description>SPI Data width.</description> 267 <bitOffset>12</bitOffset> 268 <bitWidth>2</bitWidth> 269 <enumeratedValues> 270 <enumeratedValue> 271 <name>Mono</name> 272 <description>1 data pin.</description> 273 <value>0</value> 274 </enumeratedValue> 275 <enumeratedValue> 276 <name>Dual</name> 277 <description>2 data pins.</description> 278 <value>1</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>Quad</name> 282 <description>4 data pins.</description> 283 <value>2</value> 284 </enumeratedValue> 285 </enumeratedValues> 286 </field> 287 <field> 288 <name>THREE_WIRE</name> 289 <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description> 290 <bitOffset>15</bitOffset> 291 <bitWidth>1</bitWidth> 292 <enumeratedValues> 293 <enumeratedValue> 294 <name>dis</name> 295 <description>Use four wire mode (Mono only).</description> 296 <value>0</value> 297 </enumeratedValue> 298 <enumeratedValue> 299 <name>en</name> 300 <description>Use three wire mode.</description> 301 <value>1</value> 302 </enumeratedValue> 303 </enumeratedValues> 304 </field> 305 <field> 306 <name>SS_POL</name> 307 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 308 <bitOffset>16</bitOffset> 309 <bitWidth>4</bitWidth> 310 <enumeratedValues> 311 <enumeratedValue> 312 <name>SS0_high</name> 313 <description>SS0 active high.</description> 314 <value>0x1</value> 315 </enumeratedValue> 316 <enumeratedValue> 317 <name>SS1_high</name> 318 <description>SS1 active high.</description> 319 <value>0x2</value> 320 </enumeratedValue> 321 <enumeratedValue> 322 <name>SS2_high</name> 323 <description>SS2 active high.</description> 324 <value>0x4</value> 325 </enumeratedValue> 326 <enumeratedValue> 327 <name>SS3_high</name> 328 <description>SS3 active high.</description> 329 <value>0x8</value> 330 </enumeratedValue> 331 </enumeratedValues> 332 </field> 333 </fields> 334 </register> 335 <register> 336 <name>SS_TIME</name> 337 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 338 <addressOffset>0x10</addressOffset> 339 <access>read-write</access> 340 <fields> 341 <field> 342 <name>PRE</name> 343 <description>Slave Select Pre delay 1.</description> 344 <bitOffset>0</bitOffset> 345 <bitWidth>8</bitWidth> 346 <enumeratedValues> 347 <enumeratedValue> 348 <name>256</name> 349 <description>256 system clocks between SS active and first serial clock edge.</description> 350 <value>0</value> 351 </enumeratedValue> 352 </enumeratedValues> 353 </field> 354 <field> 355 <name>POST</name> 356 <description>Slave Select Post delay 2.</description> 357 <bitOffset>8</bitOffset> 358 <bitWidth>8</bitWidth> 359 <enumeratedValues> 360 <enumeratedValue> 361 <name>256</name> 362 <description>256 system clocks between last serial clock edge and SS inactive.</description> 363 <value>0</value> 364 </enumeratedValue> 365 </enumeratedValues> 366 </field> 367 <field> 368 <name>INACT</name> 369 <description>Slave Select Inactive delay.</description> 370 <bitOffset>16</bitOffset> 371 <bitWidth>8</bitWidth> 372 <enumeratedValues> 373 <enumeratedValue> 374 <name>256</name> 375 <description>256 system clocks between transactions.</description> 376 <value>0</value> 377 </enumeratedValue> 378 </enumeratedValues> 379 </field> 380 </fields> 381 </register> 382 <register> 383 <name>CLK_CFG</name> 384 <description>Register for controlling SPI clock rate.</description> 385 <addressOffset>0x14</addressOffset> 386 <access>read-write</access> 387 <fields> 388 <field> 389 <name>LO</name> 390 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 391 <bitOffset>0</bitOffset> 392 <bitWidth>8</bitWidth> 393 <enumeratedValues> 394 <enumeratedValue> 395 <name>Dis</name> 396 <description>Duty cycle control of serial clock generation is disabled.</description> 397 <value>0</value> 398 </enumeratedValue> 399 </enumeratedValues> 400 </field> 401 <field> 402 <name>HI</name> 403 <description>High duty cycle control. In timer mode, reload[15:8].</description> 404 <bitOffset>8</bitOffset> 405 <bitWidth>8</bitWidth> 406 <enumeratedValues> 407 <enumeratedValue> 408 <name>Dis</name> 409 <description>Duty cycle control of serial clock generation is disabled.</description> 410 <value>0</value> 411 </enumeratedValue> 412 </enumeratedValues> 413 </field> 414 <field> 415 <name>SCALE</name> 416 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 417 <bitOffset>16</bitOffset> 418 <bitWidth>4</bitWidth> 419 </field> 420 </fields> 421 </register> 422 <register> 423 <name>DMA</name> 424 <description>Register for controlling DMA.</description> 425 <addressOffset>0x1C</addressOffset> 426 <access>read-write</access> 427 <fields> 428 <field> 429 <name>TX_FIFO_LEVEL</name> 430 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 431 <bitOffset>0</bitOffset> 432 <bitWidth>5</bitWidth> 433 </field> 434 <field> 435 <name>TX_FIFO_EN</name> 436 <description>Transmit FIFO enabled for SPI transactions.</description> 437 <bitOffset>6</bitOffset> 438 <bitWidth>1</bitWidth> 439 <enumeratedValues> 440 <enumeratedValue> 441 <name>dis</name> 442 <description>Transmit FIFO is not enabled.</description> 443 <value>0</value> 444 </enumeratedValue> 445 <enumeratedValue> 446 <name>en</name> 447 <description>Transmit FIFO is enabled.</description> 448 <value>1</value> 449 </enumeratedValue> 450 </enumeratedValues> 451 </field> 452 <field> 453 <name>TX_FIFO_CLEAR</name> 454 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 455 pointers. This should be done when FIFO is not being accessed on the SPI side. 456 .</description> 457 <bitOffset>7</bitOffset> 458 <bitWidth>1</bitWidth> 459 <enumeratedValues> 460 <enumeratedValue> 461 <name>CLEAR</name> 462 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 463 <value>1</value> 464 </enumeratedValue> 465 </enumeratedValues> 466 </field> 467 <field> 468 <name>TX_FIFO_CNT</name> 469 <description>Count of entries in TX FIFO.</description> 470 <bitOffset>8</bitOffset> 471 <bitWidth>6</bitWidth> 472 <access>read-only</access> 473 </field> 474 <field> 475 <name>TX_DMA_EN</name> 476 <description>TX DMA Enable.</description> 477 <bitOffset>15</bitOffset> 478 <bitWidth>1</bitWidth> 479 <enumeratedValues> 480 <enumeratedValue> 481 <name>DIS</name> 482 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 483 <value>0</value> 484 </enumeratedValue> 485 <enumeratedValue> 486 <name>en</name> 487 <description>TX DMA requests are enabled.</description> 488 <value>1</value> 489 </enumeratedValue> 490 </enumeratedValues> 491 </field> 492 <field> 493 <name>RX_FIFO_LEVEL</name> 494 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 495 <bitOffset>16</bitOffset> 496 <bitWidth>5</bitWidth> 497 </field> 498 <field> 499 <name>RX_FIFO_EN</name> 500 <description>Receive FIFO enabled for SPI transactions.</description> 501 <bitOffset>22</bitOffset> 502 <bitWidth>1</bitWidth> 503 <enumeratedValues> 504 <enumeratedValue> 505 <name>DIS</name> 506 <description>Receive FIFO is not enabled.</description> 507 <value>0</value> 508 </enumeratedValue> 509 <enumeratedValue> 510 <name>en</name> 511 <description>Receive FIFO is enabled.</description> 512 <value>1</value> 513 </enumeratedValue> 514 </enumeratedValues> 515 </field> 516 <field> 517 <name>RX_FIFO_CLEAR</name> 518 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 519 <bitOffset>23</bitOffset> 520 <bitWidth>1</bitWidth> 521 <enumeratedValues> 522 <enumeratedValue> 523 <name>CLEAR</name> 524 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 525 <value>1</value> 526 </enumeratedValue> 527 </enumeratedValues> 528 </field> 529 <field> 530 <name>RX_FIFO_CNT</name> 531 <description>Count of entries in RX FIFO.</description> 532 <bitOffset>24</bitOffset> 533 <bitWidth>6</bitWidth> 534 <access>read-only</access> 535 </field> 536 <field> 537 <name>RX_DMA_EN</name> 538 <description>RX DMA Enable.</description> 539 <bitOffset>31</bitOffset> 540 <bitWidth>1</bitWidth> 541 <enumeratedValues> 542 <enumeratedValue> 543 <name>dis</name> 544 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 545 <value>0</value> 546 </enumeratedValue> 547 <enumeratedValue> 548 <name>en</name> 549 <description>RX DMA requests are enabled.</description> 550 <value>1</value> 551 </enumeratedValue> 552 </enumeratedValues> 553 </field> 554 </fields> 555 </register> 556 <register> 557 <name>INT_FL</name> 558 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 559 <addressOffset>0x20</addressOffset> 560 <access>read-write</access> 561 <fields> 562 <field> 563 <name>TX_THRESH</name> 564 <description>TX FIFO Threshold Crossed.</description> 565 <bitOffset>0</bitOffset> 566 <bitWidth>1</bitWidth> 567 <enumeratedValues> 568 <enumeratedValue> 569 <name>clear</name> 570 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 571 <value>1</value> 572 </enumeratedValue> 573 </enumeratedValues> 574 </field> 575 <field> 576 <name>TX_EMPTY</name> 577 <description>TX FIFO Empty.</description> 578 <bitOffset>1</bitOffset> 579 <bitWidth>1</bitWidth> 580 <enumeratedValues> 581 <enumeratedValue> 582 <name>clear</name> 583 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 584 <value>1</value> 585 </enumeratedValue> 586 </enumeratedValues> 587 </field> 588 <field> 589 <name>RX_THRESH</name> 590 <description>RX FIFO Threshold Crossed.</description> 591 <bitOffset>2</bitOffset> 592 <bitWidth>1</bitWidth> 593 <enumeratedValues> 594 <enumeratedValue> 595 <name>clear</name> 596 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 597 <value>1</value> 598 </enumeratedValue> 599 </enumeratedValues> 600 </field> 601 <field> 602 <name>RX_FULL</name> 603 <description>RX FIFO FULL.</description> 604 <bitOffset>3</bitOffset> 605 <bitWidth>1</bitWidth> 606 <enumeratedValues> 607 <enumeratedValue> 608 <name>clear</name> 609 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 610 <value>1</value> 611 </enumeratedValue> 612 </enumeratedValues> 613 </field> 614 <field> 615 <name>SSA</name> 616 <description>Slave Select Asserted.</description> 617 <bitOffset>4</bitOffset> 618 <bitWidth>1</bitWidth> 619 <enumeratedValues> 620 <enumeratedValue> 621 <name>clear</name> 622 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 623 <value>1</value> 624 </enumeratedValue> 625 </enumeratedValues> 626 </field> 627 <field> 628 <name>SSD</name> 629 <description>Slave Select Deasserted.</description> 630 <bitOffset>5</bitOffset> 631 <bitWidth>1</bitWidth> 632 <enumeratedValues> 633 <enumeratedValue> 634 <name>clear</name> 635 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 636 <value>1</value> 637 </enumeratedValue> 638 </enumeratedValues> 639 </field> 640 <field> 641 <name>FAULT</name> 642 <description>Multi-Master Mode Fault.</description> 643 <bitOffset>8</bitOffset> 644 <bitWidth>1</bitWidth> 645 <enumeratedValues> 646 <enumeratedValue> 647 <name>clear</name> 648 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 649 <value>1</value> 650 </enumeratedValue> 651 </enumeratedValues> 652 </field> 653 <field> 654 <name>ABORT</name> 655 <description>Slave Abort Detected.</description> 656 <bitOffset>9</bitOffset> 657 <bitWidth>1</bitWidth> 658 <enumeratedValues> 659 <enumeratedValue> 660 <name>clear</name> 661 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 662 <value>1</value> 663 </enumeratedValue> 664 </enumeratedValues> 665 </field> 666 <field> 667 <name>M_DONE</name> 668 <description>Master Done, set when SPI Master has completed any transactions.</description> 669 <bitOffset>11</bitOffset> 670 <bitWidth>1</bitWidth> 671 <enumeratedValues> 672 <enumeratedValue> 673 <name>clear</name> 674 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 675 <value>1</value> 676 </enumeratedValue> 677 </enumeratedValues> 678 </field> 679 <field> 680 <name>TX_OVR</name> 681 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 682 <bitOffset>12</bitOffset> 683 <bitWidth>1</bitWidth> 684 <enumeratedValues> 685 <enumeratedValue> 686 <name>clear</name> 687 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 688 <value>1</value> 689 </enumeratedValue> 690 </enumeratedValues> 691 </field> 692 <field> 693 <name>TX_UND</name> 694 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 695 <bitOffset>13</bitOffset> 696 <bitWidth>1</bitWidth> 697 <enumeratedValues> 698 <enumeratedValue> 699 <name>clear</name> 700 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 701 <value>1</value> 702 </enumeratedValue> 703 </enumeratedValues> 704 </field> 705 <field> 706 <name>RX_OVR</name> 707 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 708 <bitOffset>14</bitOffset> 709 <bitWidth>1</bitWidth> 710 <enumeratedValues> 711 <enumeratedValue> 712 <name>clear</name> 713 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 714 <value>1</value> 715 </enumeratedValue> 716 </enumeratedValues> 717 </field> 718 <field> 719 <name>RX_UND</name> 720 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 721 <bitOffset>15</bitOffset> 722 <bitWidth>1</bitWidth> 723 <enumeratedValues> 724 <enumeratedValue> 725 <name>clear</name> 726 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 727 <value>1</value> 728 </enumeratedValue> 729 </enumeratedValues> 730 </field> 731 </fields> 732 </register> 733 <register> 734 <name>INT_EN</name> 735 <description>Register for enabling interrupts.</description> 736 <addressOffset>0x24</addressOffset> 737 <access>read-write</access> 738 <fields> 739 <field> 740 <name>TX_THRESH</name> 741 <description>TX FIFO Threshold interrupt enable.</description> 742 <bitOffset>0</bitOffset> 743 <bitWidth>1</bitWidth> 744 <enumeratedValues> 745 <enumeratedValue> 746 <name>dis</name> 747 <description>Interrupt is disabled.</description> 748 <value>0</value> 749 </enumeratedValue> 750 <enumeratedValue> 751 <name>en</name> 752 <description>Interrupt is enabled.</description> 753 <value>1</value> 754 </enumeratedValue> 755 </enumeratedValues> 756 </field> 757 <field> 758 <name>TX_EMPTY</name> 759 <description>TX FIFO Empty interrupt enable.</description> 760 <bitOffset>1</bitOffset> 761 <bitWidth>1</bitWidth> 762 <enumeratedValues> 763 <enumeratedValue> 764 <name>dis</name> 765 <description>Interrupt is disabled.</description> 766 <value>0</value> 767 </enumeratedValue> 768 <enumeratedValue> 769 <name>en</name> 770 <description>Interrupt is enabled.</description> 771 <value>1</value> 772 </enumeratedValue> 773 </enumeratedValues> 774 </field> 775 <field> 776 <name>RX_THRESH</name> 777 <description>RX FIFO Threshold Crossed interrupt enable.</description> 778 <bitOffset>2</bitOffset> 779 <bitWidth>1</bitWidth> 780 <enumeratedValues> 781 <enumeratedValue> 782 <name>dis</name> 783 <description>Interrupt is disabled.</description> 784 <value>0</value> 785 </enumeratedValue> 786 <enumeratedValue> 787 <name>en</name> 788 <description>Interrupt is enabled.</description> 789 <value>1</value> 790 </enumeratedValue> 791 </enumeratedValues> 792 </field> 793 <field> 794 <name>RX_FULL</name> 795 <description>RX FIFO FULL interrupt enable.</description> 796 <bitOffset>3</bitOffset> 797 <bitWidth>1</bitWidth> 798 <enumeratedValues> 799 <enumeratedValue> 800 <name>dis</name> 801 <description>Interrupt is disabled.</description> 802 <value>0</value> 803 </enumeratedValue> 804 <enumeratedValue> 805 <name>en</name> 806 <description>Interrupt is enabled.</description> 807 <value>1</value> 808 </enumeratedValue> 809 </enumeratedValues> 810 </field> 811 <field> 812 <name>SSA</name> 813 <description>Slave Select Asserted interrupt enable.</description> 814 <bitOffset>4</bitOffset> 815 <bitWidth>1</bitWidth> 816 <enumeratedValues> 817 <enumeratedValue> 818 <name>dis</name> 819 <description>Interrupt is disabled.</description> 820 <value>0</value> 821 </enumeratedValue> 822 <enumeratedValue> 823 <name>en</name> 824 <description>Interrupt is enabled.</description> 825 <value>1</value> 826 </enumeratedValue> 827 </enumeratedValues> 828 </field> 829 <field> 830 <name>SSD</name> 831 <description>Slave Select Deasserted interrupt enable.</description> 832 <bitOffset>5</bitOffset> 833 <bitWidth>1</bitWidth> 834 <enumeratedValues> 835 <enumeratedValue> 836 <name>dis</name> 837 <description>Interrupt is disabled.</description> 838 <value>0</value> 839 </enumeratedValue> 840 <enumeratedValue> 841 <name>en</name> 842 <description>Interrupt is enabled.</description> 843 <value>1</value> 844 </enumeratedValue> 845 </enumeratedValues> 846 </field> 847 <field> 848 <name>FAULT</name> 849 <description>Multi-Master Mode Fault interrupt enable.</description> 850 <bitOffset>8</bitOffset> 851 <bitWidth>1</bitWidth> 852 <enumeratedValues> 853 <enumeratedValue> 854 <name>dis</name> 855 <description>Interrupt is disabled.</description> 856 <value>0</value> 857 </enumeratedValue> 858 <enumeratedValue> 859 <name>en</name> 860 <description>Interrupt is enabled.</description> 861 <value>1</value> 862 </enumeratedValue> 863 </enumeratedValues> 864 </field> 865 <field> 866 <name>ABORT</name> 867 <description>Slave Abort Detected interrupt enable.</description> 868 <bitOffset>9</bitOffset> 869 <bitWidth>1</bitWidth> 870 <enumeratedValues> 871 <enumeratedValue> 872 <name>dis</name> 873 <description>Interrupt is disabled.</description> 874 <value>0</value> 875 </enumeratedValue> 876 <enumeratedValue> 877 <name>en</name> 878 <description>Interrupt is enabled.</description> 879 <value>1</value> 880 </enumeratedValue> 881 </enumeratedValues> 882 </field> 883 <field> 884 <name>M_DONE</name> 885 <description>Master Done interrupt enable.</description> 886 <bitOffset>11</bitOffset> 887 <bitWidth>1</bitWidth> 888 <enumeratedValues> 889 <enumeratedValue> 890 <name>dis</name> 891 <description>Interrupt is disabled.</description> 892 <value>0</value> 893 </enumeratedValue> 894 <enumeratedValue> 895 <name>en</name> 896 <description>Interrupt is enabled.</description> 897 <value>1</value> 898 </enumeratedValue> 899 </enumeratedValues> 900 </field> 901 <field> 902 <name>TX_OVR</name> 903 <description>Transmit FIFO Overrun interrupt enable.</description> 904 <bitOffset>12</bitOffset> 905 <bitWidth>1</bitWidth> 906 <enumeratedValues> 907 <enumeratedValue> 908 <name>dis</name> 909 <description>Interrupt is disabled.</description> 910 <value>0</value> 911 </enumeratedValue> 912 <enumeratedValue> 913 <name>en</name> 914 <description>Interrupt is enabled.</description> 915 <value>1</value> 916 </enumeratedValue> 917 </enumeratedValues> 918 </field> 919 <field> 920 <name>TX_UND</name> 921 <description>Transmit FIFO Underrun interrupt enable.</description> 922 <bitOffset>13</bitOffset> 923 <bitWidth>1</bitWidth> 924 <enumeratedValues> 925 <enumeratedValue> 926 <name>dis</name> 927 <description>Interrupt is disabled.</description> 928 <value>0</value> 929 </enumeratedValue> 930 <enumeratedValue> 931 <name>en</name> 932 <description>Interrupt is enabled.</description> 933 <value>1</value> 934 </enumeratedValue> 935 </enumeratedValues> 936 </field> 937 <field> 938 <name>RX_OVR</name> 939 <description>Receive FIFO Overrun interrupt enable.</description> 940 <bitOffset>14</bitOffset> 941 <bitWidth>1</bitWidth> 942 <enumeratedValues> 943 <enumeratedValue> 944 <name>dis</name> 945 <description>Interrupt is disabled.</description> 946 <value>0</value> 947 </enumeratedValue> 948 <enumeratedValue> 949 <name>en</name> 950 <description>Interrupt is enabled.</description> 951 <value>1</value> 952 </enumeratedValue> 953 </enumeratedValues> 954 </field> 955 <field> 956 <name>RX_UND</name> 957 <description>Receive FIFO Underrun interrupt enable.</description> 958 <bitOffset>15</bitOffset> 959 <bitWidth>1</bitWidth> 960 <enumeratedValues> 961 <enumeratedValue> 962 <name>dis</name> 963 <description>Interrupt is disabled.</description> 964 <value>0</value> 965 </enumeratedValue> 966 <enumeratedValue> 967 <name>en</name> 968 <description>Interrupt is enabled.</description> 969 <value>1</value> 970 </enumeratedValue> 971 </enumeratedValues> 972 </field> 973 </fields> 974 </register> 975 <register> 976 <name>WAKE_FL</name> 977 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 978 <addressOffset>0x28</addressOffset> 979 <access>read-write</access> 980 <fields> 981 <field> 982 <name>TX_THRESH</name> 983 <description>Wake on TX FIFO Threshold Crossed.</description> 984 <bitOffset>0</bitOffset> 985 <bitWidth>1</bitWidth> 986 <enumeratedValues> 987 <enumeratedValue> 988 <name>clear</name> 989 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 990 <value>1</value> 991 </enumeratedValue> 992 </enumeratedValues> 993 </field> 994 <field> 995 <name>TX_EMPTY</name> 996 <description>Wake on TX FIFO Empty.</description> 997 <bitOffset>1</bitOffset> 998 <bitWidth>1</bitWidth> 999 <enumeratedValues> 1000 <enumeratedValue> 1001 <name>clear</name> 1002 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1003 <value>1</value> 1004 </enumeratedValue> 1005 </enumeratedValues> 1006 </field> 1007 <field> 1008 <name>RX_THRESH</name> 1009 <description>Wake on RX FIFO Threshold Crossed.</description> 1010 <bitOffset>2</bitOffset> 1011 <bitWidth>1</bitWidth> 1012 <enumeratedValues> 1013 <enumeratedValue> 1014 <name>clear</name> 1015 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1016 <value>1</value> 1017 </enumeratedValue> 1018 </enumeratedValues> 1019 </field> 1020 <field> 1021 <name>RX_FULL</name> 1022 <description>Wake on RX FIFO Full.</description> 1023 <bitOffset>3</bitOffset> 1024 <bitWidth>1</bitWidth> 1025 <enumeratedValues> 1026 <enumeratedValue> 1027 <name>clear</name> 1028 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1029 <value>1</value> 1030 </enumeratedValue> 1031 </enumeratedValues> 1032 </field> 1033 </fields> 1034 </register> 1035 <register> 1036 <name>WAKE_EN</name> 1037 <description>Register for wake up enable.</description> 1038 <addressOffset>0x2C</addressOffset> 1039 <access>read-write</access> 1040 <fields> 1041 <field> 1042 <name>TX_THRESH</name> 1043 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1044 <bitOffset>0</bitOffset> 1045 <bitWidth>1</bitWidth> 1046 <enumeratedValues> 1047 <enumeratedValue> 1048 <name>dis</name> 1049 <description>Wakeup source disabled.</description> 1050 <value>0</value> 1051 </enumeratedValue> 1052 <enumeratedValue> 1053 <name>en</name> 1054 <description>Wakeup source enabled.</description> 1055 <value>1</value> 1056 </enumeratedValue> 1057 </enumeratedValues> 1058 </field> 1059 <field> 1060 <name>TX_EMPTY</name> 1061 <description>Wake on TX FIFO Empty Enable.</description> 1062 <bitOffset>1</bitOffset> 1063 <bitWidth>1</bitWidth> 1064 <enumeratedValues> 1065 <enumeratedValue> 1066 <name>dis</name> 1067 <description>Wakeup source disabled.</description> 1068 <value>0</value> 1069 </enumeratedValue> 1070 <enumeratedValue> 1071 <name>en</name> 1072 <description>Wakeup source enabled.</description> 1073 <value>1</value> 1074 </enumeratedValue> 1075 </enumeratedValues> 1076 </field> 1077 <field> 1078 <name>RX_THRESH</name> 1079 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1080 <bitOffset>2</bitOffset> 1081 <bitWidth>1</bitWidth> 1082 <enumeratedValues> 1083 <enumeratedValue> 1084 <name>dis</name> 1085 <description>Wakeup source disabled.</description> 1086 <value>0</value> 1087 </enumeratedValue> 1088 <enumeratedValue> 1089 <name>en</name> 1090 <description>Wakeup source enabled.</description> 1091 <value>1</value> 1092 </enumeratedValue> 1093 </enumeratedValues> 1094 </field> 1095 <field> 1096 <name>RX_FULL</name> 1097 <description>Wake on RX FIFO Full Enable.</description> 1098 <bitOffset>3</bitOffset> 1099 <bitWidth>1</bitWidth> 1100 <enumeratedValues> 1101 <enumeratedValue> 1102 <name>dis</name> 1103 <description>Wakeup source disabled.</description> 1104 <value>0</value> 1105 </enumeratedValue> 1106 <enumeratedValue> 1107 <name>en</name> 1108 <description>Wakeup source enabled.</description> 1109 <value>1</value> 1110 </enumeratedValue> 1111 </enumeratedValues> 1112 </field> 1113 </fields> 1114 </register> 1115 <register> 1116 <name>STAT</name> 1117 <description>SPI Status register.</description> 1118 <addressOffset>0x30</addressOffset> 1119 <access>read-only</access> 1120 <fields> 1121 <field> 1122 <name>BUSY</name> 1123 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1124 <bitOffset>0</bitOffset> 1125 <bitWidth>1</bitWidth> 1126 <enumeratedValues> 1127 <enumeratedValue> 1128 <name>not</name> 1129 <description>SPI not active.</description> 1130 <value>0</value> 1131 </enumeratedValue> 1132 <enumeratedValue> 1133 <name>active</name> 1134 <description>SPI active.</description> 1135 <value>1</value> 1136 </enumeratedValue> 1137 </enumeratedValues> 1138 </field> 1139 </fields> 1140 </register> 1141 </registers> 1142 </peripheral> 1143 <!-- SPI: Serial Peripheral Interface --> 1144</device>
